| 1 | /*
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| 2 | * Copyright (C) 2006-2022 Oracle Corporation
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| 3 | *
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| 4 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 5 | * available from http://www.virtualbox.org. This file is free software;
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| 6 | * you can redistribute it and/or modify it under the terms of the GNU
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| 7 | * General Public License (GPL) as published by the Free Software
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| 8 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 9 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 10 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 11 | * --------------------------------------------------------------------
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| 12 | *
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| 13 | * This code is based on:
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| 14 | *
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| 15 | * ROM BIOS for use with Bochs/Plex86/QEMU emulation environment
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| 16 | *
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| 17 | * Copyright (C) 2002 MandrakeSoft S.A.
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| 18 | *
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| 19 | * MandrakeSoft S.A.
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| 20 | * 43, rue d'Aboukir
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| 21 | * 75002 Paris - France
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| 22 | * http://www.linux-mandrake.com/
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| 23 | * http://www.mandrakesoft.com/
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| 24 | *
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| 25 | * This library is free software; you can redistribute it and/or
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| 26 | * modify it under the terms of the GNU Lesser General Public
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| 27 | * License as published by the Free Software Foundation; either
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| 28 | * version 2 of the License, or (at your option) any later version.
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| 29 | *
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| 30 | * This library is distributed in the hope that it will be useful,
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| 31 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 33 | * Lesser General Public License for more details.
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| 34 | *
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| 35 | * You should have received a copy of the GNU Lesser General Public
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| 36 | * License along with this library; if not, write to the Free Software
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| 37 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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| 38 | *
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| 39 | */
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| 40 |
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| 41 | /*
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| 42 | * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 43 | * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
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| 44 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 45 | * a choice of LGPL license versions is made available with the language indicating
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| 46 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 47 | * of the LGPL is applied is otherwise unspecified.
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| 48 | */
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| 49 |
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| 50 |
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| 51 | #include <stdint.h>
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| 52 | #include "biosint.h"
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| 53 | #include "inlines.h"
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| 54 |
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| 55 | #if DEBUG_INT1A
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| 56 | # define BX_DEBUG_INT1A(...) BX_DEBUG(__VA_ARGS__)
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| 57 | #else
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| 58 | # define BX_DEBUG_INT1A(...)
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| 59 | #endif
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| 60 |
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| 61 | // for access to RAM area which is used by interrupt vectors
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| 62 | // and BIOS Data Area
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| 63 |
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| 64 | typedef struct {
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| 65 | uint8_t filler1[0x400];
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| 66 | uint8_t filler2[0x6c];
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| 67 | uint16_t ticks_low;
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| 68 | uint16_t ticks_high;
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| 69 | uint8_t midnight_flag;
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| 70 | } bios_data_t;
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| 71 |
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| 72 | #define BiosData ((bios_data_t __far *) 0)
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| 73 |
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| 74 | void init_rtc(void)
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| 75 | {
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| 76 | outb_cmos(0x0a, 0x26);
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| 77 | outb_cmos(0x0b, 0x02);
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| 78 | inb_cmos(0x0c);
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| 79 | inb_cmos(0x0d);
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| 80 | }
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| 81 |
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| 82 | bx_bool rtc_updating(void)
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| 83 | {
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| 84 | // This function checks to see if the update-in-progress bit
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| 85 | // is set in CMOS Status Register A. If not, it returns 0.
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| 86 | // If it is set, it tries to wait until there is a transition
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| 87 | // to 0, and will return 0 if such a transition occurs. A 1
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| 88 | // is returned only after timing out. The maximum period
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| 89 | // that this bit should be set is constrained to 244useconds.
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| 90 | // The count I use below guarantees coverage or more than
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| 91 | // this time, with any reasonable IPS setting.
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| 92 |
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| 93 | uint16_t iter;
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| 94 |
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| 95 | iter = 25000;
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| 96 | while (--iter != 0) {
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| 97 | if ( (inb_cmos(0x0a) & 0x80) == 0 )
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| 98 | return 0;
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| 99 | }
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| 100 | return 1; // update-in-progress never transitioned to 0
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| 101 | }
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| 102 |
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| 103 |
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| 104 | extern void eoi_both_pics(void); /* in assembly code */
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| 105 | #pragma aux eoi_both_pics "*";
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| 106 |
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| 107 | void call_int_4a(void);
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| 108 | #pragma aux call_int_4a = "int 4Ah";
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| 109 |
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| 110 | void BIOSCALL int70_function(pusha_regs_t regs, uint16_t ds, uint16_t es, iret_addr_t iret_addr)
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| 111 | {
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| 112 | // INT 70h: IRQ 8 - CMOS RTC interrupt from periodic or alarm modes
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| 113 | uint8_t registerB = 0, registerC = 0;
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| 114 |
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| 115 | // Check which modes are enabled and have occurred.
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| 116 | registerB = inb_cmos( 0xB );
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| 117 | registerC = inb_cmos( 0xC );
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| 118 |
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| 119 | if( ( registerB & 0x60 ) != 0 ) {
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| 120 | if( ( registerC & 0x20 ) != 0 ) {
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| 121 | // Handle Alarm Interrupt.
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| 122 | int_enable();
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| 123 | call_int_4a();
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| 124 | int_disable();
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| 125 | }
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| 126 | if( ( registerC & 0x40 ) != 0 ) {
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| 127 | // Handle Periodic Interrupt.
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| 128 |
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| 129 | if( read_byte( 0x40, 0xA0 ) != 0 ) {
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| 130 | // Wait Interval (Int 15, AH=83 or AH=86) active.
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| 131 | uint32_t time;
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| 132 |
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| 133 | time = read_dword( 0x40, 0x9C ); // Time left in microseconds.
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| 134 | if( time < 0x3D1 ) {
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| 135 | // Done waiting.
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| 136 | uint16_t segment, offset;
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| 137 |
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| 138 | segment = read_word( 0x40, 0x98 );
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| 139 | offset = read_word( 0x40, 0x9A );
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| 140 | write_byte( 0x40, 0xA0, 0 ); // Turn off status byte.
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| 141 | outb_cmos( 0xB, registerB & 0x37 ); // Clear the Periodic Interrupt.
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| 142 | write_byte( segment, offset, read_byte(segment, offset) | 0x80 ); // Write to specified flag byte.
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| 143 | } else {
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| 144 | // Continue waiting.
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| 145 | time -= 0x3D1;
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| 146 | write_dword( 0x40, 0x9C, time );
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| 147 | }
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| 148 | }
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| 149 | }
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| 150 | }
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| 151 | eoi_both_pics();
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| 152 | }
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| 153 |
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| 154 | /// @todo the coding style WRT register access is totally inconsistent
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| 155 | // in the following routines
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| 156 |
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| 157 | void BIOSCALL int1a_function(pusha_regs_t regs, uint16_t ds, uint16_t es, iret_addr_t iret_addr)
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| 158 | {
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| 159 | uint8_t val8;
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| 160 |
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| 161 | BX_DEBUG_INT1A("int1a: AX=%04x BX=%04x CX=%04x DX=%04x DS=%04x\n",
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| 162 | regs.u.r16.ax, regs.u.r16.bx, regs.u.r16.cx, regs.u.r16.dx, ds);
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| 163 | int_enable();
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| 164 |
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| 165 | switch (regs.u.r8.ah) {
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| 166 | case 0: // get current clock count
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| 167 | int_disable();
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| 168 | regs.u.r16.cx = BiosData->ticks_high;
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| 169 | regs.u.r16.dx = BiosData->ticks_low;
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| 170 | regs.u.r8.al = BiosData->midnight_flag;
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| 171 | BiosData->midnight_flag = 0; // reset flag
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| 172 | int_enable();
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| 173 | // AH already 0
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| 174 | ClearCF(iret_addr.flags); // OK
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| 175 | break;
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| 176 |
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| 177 | case 1: // Set Current Clock Count
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| 178 | int_disable();
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| 179 | BiosData->ticks_high = regs.u.r16.cx;
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| 180 | BiosData->ticks_low = regs.u.r16.dx;
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| 181 | BiosData->midnight_flag = 0; // reset flag
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| 182 | int_enable();
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| 183 | regs.u.r8.ah = 0;
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| 184 | ClearCF(iret_addr.flags); // OK
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| 185 | break;
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| 186 |
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| 187 | case 2: // Read CMOS Time
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| 188 | if (rtc_updating()) {
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| 189 | SetCF(iret_addr.flags);
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| 190 | break;
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| 191 | }
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| 192 |
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| 193 | regs.u.r8.dh = inb_cmos(0x00); // Seconds
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| 194 | regs.u.r8.cl = inb_cmos(0x02); // Minutes
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| 195 | regs.u.r8.ch = inb_cmos(0x04); // Hours
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| 196 | regs.u.r8.dl = inb_cmos(0x0b) & 0x01; // Stat Reg B
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| 197 | regs.u.r8.ah = 0;
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| 198 | regs.u.r8.al = regs.u.r8.ch;
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| 199 | ClearCF(iret_addr.flags); // OK
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| 200 | break;
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| 201 |
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| 202 | case 3: // Set CMOS Time
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| 203 | // Using a debugger, I notice the following masking/setting
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| 204 | // of bits in Status Register B, by setting Reg B to
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| 205 | // a few values and getting its value after INT 1A was called.
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| 206 | //
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| 207 | // try#1 try#2 try#3
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| 208 | // before 1111 1101 0111 1101 0000 0000
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| 209 | // after 0110 0010 0110 0010 0000 0010
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| 210 | //
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| 211 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
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| 212 | // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
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| 213 | if (rtc_updating()) {
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| 214 | init_rtc();
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| 215 | // fall through as if an update were not in progress
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| 216 | }
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| 217 | outb_cmos(0x00, regs.u.r8.dh); // Seconds
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| 218 | outb_cmos(0x02, regs.u.r8.cl); // Minutes
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| 219 | outb_cmos(0x04, regs.u.r8.ch); // Hours
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| 220 | // Set Daylight Savings time enabled bit to requested value
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| 221 | val8 = (inb_cmos(0x0b) & 0x60) | 0x02 | (regs.u.r8.dl & 0x01);
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| 222 | // (reg B already selected)
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| 223 | outb_cmos(0x0b, val8);
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| 224 | regs.u.r8.ah = 0;
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| 225 | regs.u.r8.al = val8; // val last written to Reg B
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| 226 | ClearCF(iret_addr.flags); // OK
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| 227 | break;
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| 228 |
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| 229 | case 4: // Read CMOS Date
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| 230 | regs.u.r8.ah = 0;
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| 231 | if (rtc_updating()) {
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| 232 | SetCF(iret_addr.flags);
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| 233 | break;
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| 234 | }
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| 235 | regs.u.r8.cl = inb_cmos(0x09); // Year
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| 236 | regs.u.r8.dh = inb_cmos(0x08); // Month
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| 237 | regs.u.r8.dl = inb_cmos(0x07); // Day of Month
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| 238 | regs.u.r8.ch = inb_cmos(0x32); // Century
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| 239 | regs.u.r8.al = regs.u.r8.ch;
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| 240 | ClearCF(iret_addr.flags); // OK
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| 241 | break;
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| 242 |
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| 243 | case 5: // Set CMOS Date
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| 244 | // Using a debugger, I notice the following masking/setting
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| 245 | // of bits in Status Register B, by setting Reg B to
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| 246 | // a few values and getting its value after INT 1A was called.
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| 247 | //
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| 248 | // try#1 try#2 try#3 try#4
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| 249 | // before 1111 1101 0111 1101 0000 0010 0000 0000
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| 250 | // after 0110 1101 0111 1101 0000 0010 0000 0000
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| 251 | //
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| 252 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
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| 253 | // My assumption: RegB = (RegB & 01111111b)
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| 254 | if (rtc_updating()) {
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| 255 | init_rtc();
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| 256 | SetCF(iret_addr.flags);
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| 257 | break;
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| 258 | }
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| 259 | outb_cmos(0x09, regs.u.r8.cl); // Year
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| 260 | outb_cmos(0x08, regs.u.r8.dh); // Month
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| 261 | outb_cmos(0x07, regs.u.r8.dl); // Day of Month
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| 262 | outb_cmos(0x32, regs.u.r8.ch); // Century
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| 263 | val8 = inb_cmos(0x0b) & 0x7f; // clear halt-clock bit
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| 264 | outb_cmos(0x0b, val8);
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| 265 | regs.u.r8.ah = 0;
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| 266 | regs.u.r8.al = val8; // AL = val last written to Reg B
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| 267 | ClearCF(iret_addr.flags); // OK
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| 268 | break;
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| 269 |
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| 270 | case 6: // Set Alarm Time in CMOS
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| 271 | // Using a debugger, I notice the following masking/setting
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| 272 | // of bits in Status Register B, by setting Reg B to
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| 273 | // a few values and getting its value after INT 1A was called.
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| 274 | //
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| 275 | // try#1 try#2 try#3
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| 276 | // before 1101 1111 0101 1111 0000 0000
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| 277 | // after 0110 1111 0111 1111 0010 0000
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| 278 | //
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| 279 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
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| 280 | // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
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| 281 | val8 = inb_cmos(0x0b); // Get Status Reg B
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| 282 | regs.u.r16.ax = 0;
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| 283 | if (val8 & 0x20) {
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| 284 | // Alarm interrupt enabled already
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| 285 | SetCF(iret_addr.flags); // Error: alarm in use
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| 286 | break;
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| 287 | }
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| 288 | if (rtc_updating()) {
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| 289 | init_rtc();
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| 290 | // fall through as if an update were not in progress
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| 291 | }
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| 292 | outb_cmos(0x01, regs.u.r8.dh); // Seconds alarm
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| 293 | outb_cmos(0x03, regs.u.r8.cl); // Minutes alarm
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| 294 | outb_cmos(0x05, regs.u.r8.ch); // Hours alarm
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| 295 | outb(0xa1, inb(0xa1) & 0xfe); // enable IRQ 8
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| 296 | // enable Status Reg B alarm bit, clear halt clock bit
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| 297 | outb_cmos(0x0b, (val8 & 0x7f) | 0x20);
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| 298 | ClearCF(iret_addr.flags); // OK
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| 299 | break;
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| 300 |
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| 301 | case 7: // Turn off Alarm
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| 302 | // Using a debugger, I notice the following masking/setting
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| 303 | // of bits in Status Register B, by setting Reg B to
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| 304 | // a few values and getting its value after INT 1A was called.
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| 305 | //
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| 306 | // try#1 try#2 try#3 try#4
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| 307 | // before 1111 1101 0111 1101 0010 0000 0010 0010
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| 308 | // after 0100 0101 0101 0101 0000 0000 0000 0010
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| 309 | //
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| 310 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
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| 311 | // My assumption: RegB = (RegB & 01010111b)
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| 312 | val8 = inb_cmos(0x0b); // Get Status Reg B
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| 313 | // clear clock-halt bit, disable alarm bit
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| 314 | outb_cmos(0x0b, val8 & 0x57); // disable alarm bit
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| 315 | regs.u.r8.ah = 0;
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| 316 | regs.u.r8.al = val8; // val last written to Reg B
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| 317 | ClearCF(iret_addr.flags); // OK
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| 318 | break;
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| 319 |
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| 320 | default:
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| 321 | BX_DEBUG_INT1A("int1a: AX=%04x unsupported\n", regs.u.r16.ax);
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| 322 | SetCF(iret_addr.flags); // Unsupported
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| 323 | }
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| 324 | }
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