VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/BIOS/ahci.c@ 40754

Last change on this file since 40754 was 37427, checked in by vboxsync, 13 years ago

BIOS/AHCI: Updates for the driver, grub can boot from a SATA disk now
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 55.0 KB
Line 
1/* $Id: ahci.c 37427 2011-06-13 17:45:37Z vboxsync $ */
2/** @file
3 * AHCI host adapter driver to boot from SATA disks.
4 */
5
6/*
7 * Copyright (C) 2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17/**
18 * Parts are based on the int13_harddisk code in rombios.c
19 */
20
21#define AHCI_MAX_STORAGE_DEVICES 4
22
23/**
24 * AHCI device data.
25 */
26typedef struct
27{
28 Bit8u type; // Detected type of ata (ata/atapi/none/unknown/scsi)
29 Bit8u device; // Detected type of attached devices (hd/cd/none)
30 Bit8u removable; // Removable device flag
31 Bit8u lock; // Locks for removable devices
32 Bit16u blksize; // block size
33 chs_t lchs; // Logical CHS
34 chs_t pchs; // Physical CHS
35 Bit32u cSectors; // Total sectors count
36 Bit8u port; // Port this device is on.
37} ahci_device_t;
38
39/**
40 * AHCI controller data.
41 */
42typedef struct
43{
44 /** The AHCI command list as defined by chapter 4.2.2 of the Intel AHCI spec.
45 * Because the BIOS doesn't support NCQ only the first command header is defined
46 * to save memory. - Must be aligned on a 1K boundary.
47 */
48 Bit32u abCmdHdr[0x8];
49 /** Align the next structure on a 128 byte boundary. */
50 Bit8u abAlignment1[0x60];
51 /** The command table of one request as defined by chapter 4.2.3 of the Intel AHCI spec.
52 * Must be aligned on 128 byte boundary.
53 */
54 Bit8u abCmd[0x90];
55 /** Alignment */
56 Bit8u abAlignment2[0xF0];
57 /** Memory for the received command FIS area as specified by chapter 4.2.1
58 * of the Intel AHCI spec. This area is normally 256 bytes big but to save memory
59 * only the first 96 bytes are used because it is assumed that the controller
60 * never writes to the UFIS or reserved area. - Must be aligned on a 256byte boundary.
61 */
62 Bit8u abFisRecv[0x60];
63 /** Base I/O port for the index/data register pair. */
64 Bit16u iobase;
65 /** Current port which uses the memory to communicate with the controller. */
66 Bit8u port;
67 /** AHCI device information. */
68 ahci_device_t aDevices[AHCI_MAX_STORAGE_DEVICES];
69 /** Index of the next unoccupied device slot. */
70 Bit8u cDevices;
71 /** Map between (bios hd id - 0x80) and ahci devices. */
72 Bit8u cHardDisks;
73 Bit8u aHdIdMap[AHCI_MAX_STORAGE_DEVICES];
74 /** Map between (bios cd id - 0xE0) and ahci_devices. */
75 Bit8u cCdDrives;
76 Bit8u aCdIdMap[AHCI_MAX_STORAGE_DEVICES];
77 /** int13 handler to call if given device is not from AHCI. */
78 Bit16u pfnInt13Old;
79 /** Number of harddisks detected before the AHCI driver started detection. */
80 Bit8u cHardDisksOld;
81} ahci_t;
82
83#define AhciData ((ahci_t *) 0)
84
85/** Supported methods of the PCI BIOS. */
86#define PCIBIOS_ID 0xb1
87#define PCIBIOS_PCI_BIOS_PRESENT 0x01
88#define PCIBIOS_FIND_PCI_DEVICE 0x02
89#define PCIBIOS_FIND_CLASS_CODE 0x03
90#define PCIBIOS_GENERATE_SPECIAL_CYCLE 0x06
91#define PCIBIOS_READ_CONFIG_BYTE 0x08
92#define PCIBIOS_READ_CONFIG_WORD 0x09
93#define PCIBIOS_READ_CONFIG_DWORD 0x0a
94#define PCIBIOS_WRITE_CONFIG_BYTE 0x0b
95#define PCIBIOS_WRITE_CONFIG_WORD 0x0c
96#define PCIBIOS_WRITE_CONFIG_DWORD 0x0d
97#define PCIBIOS_GET_IRQ_ROUTING_OPTIONS 0x0e
98#define PCIBIOS_SET_PCI_IRQ 0x0f
99
100/** Status codes. */
101#define SUCCESSFUL 0x00
102#define FUNC_NOT_SUPPORTED 0x81
103#define BAD_VENDOR_ID 0x83
104#define DEVICE_NOT_FOUND 0x86
105#define BAD_REGISTER_NUMBER 0x87
106#define SET_FAILED 0x88
107#define BUFFER_TOO_SMALL 0x89
108
109/** PCI configuration fields. */
110#define PCI_CONFIG_CAP 0x34
111
112#define PCI_CAP_ID_SATACR 0x12
113#define VBOX_AHCI_NO_DEVICE 0xffff
114
115//#define VBOX_AHCI_DEBUG 1
116//#define VBOX_AHCI_INT13_DEBUG 1
117
118#ifdef VBOX_AHCI_DEBUG
119# define VBOXAHCI_DEBUG(a...) BX_INFO(a)
120#else
121# define VBOXAHCI_DEBUG(a...)
122#endif
123
124#ifdef VBOX_AHCI_INT13_DEBUG
125# define VBOXAHCI_INT13_DEBUG(a...) BX_INFO(a)
126#else
127# define VBOXAHCI_INT13_DEBUG(a...)
128#endif
129
130#define RT_BIT_32(bit) ((Bit32u)(1L << (bit)))
131
132/** Global register set. */
133#define AHCI_HBA_SIZE 0x100
134
135#define AHCI_REG_CAP ((Bit32u)0x00)
136#define AHCI_REG_GHC ((Bit32u)0x04)
137# define AHCI_GHC_AE RT_BIT_32(31)
138# define AHCI_GHC_IR RT_BIT_32(1)
139# define AHCI_GHC_HR RT_BIT_32(0)
140#define AHCI_REG_IS ((Bit32u)0x08)
141#define AHCI_REG_PI ((Bit32u)0x0c)
142#define AHCI_REG_VS ((Bit32u)0x10)
143
144/** Per port register set. */
145#define AHCI_PORT_SIZE 0x80
146
147#define AHCI_REG_PORT_CLB 0x00
148#define AHCI_REG_PORT_CLBU 0x04
149#define AHCI_REG_PORT_FB 0x08
150#define AHCI_REG_PORT_FBU 0x0c
151#define AHCI_REG_PORT_IS 0x10
152# define AHCI_REG_PORT_IS_DHRS RT_BIT_32(0)
153#define AHCI_REG_PORT_IE 0x14
154#define AHCI_REG_PORT_CMD 0x18
155# define AHCI_REG_PORT_CMD_ST RT_BIT_32(0)
156# define AHCI_REG_PORT_CMD_FRE RT_BIT_32(4)
157# define AHCI_REG_PORT_CMD_FR RT_BIT_32(14)
158# define AHCI_REG_PORT_CMD_CR RT_BIT_32(15)
159#define AHCI_REG_PORT_TFD 0x20
160#define AHCI_REG_PORT_SIG 0x24
161#define AHCI_REG_PORT_SSTS 0x28
162#define AHCI_REG_PORT_SCTL 0x2c
163#define AHCI_REG_PORT_SERR 0x30
164#define AHCI_REG_PORT_SACT 0x34
165#define AHCI_REG_PORT_CI 0x38
166
167/** Returns the absolute register offset from a given port and port register. */
168#define VBOXAHCI_PORT_REG(port, reg) ((Bit32u)(AHCI_HBA_SIZE + (port) * AHCI_PORT_SIZE + (reg)))
169
170#define VBOXAHCI_REG_IDX 0
171#define VBOXAHCI_REG_DATA 4
172
173/** Writes the given value to a AHCI register. */
174#define VBOXAHCI_WRITE_REG(iobase, reg, val) \
175 outl((iobase) + VBOXAHCI_REG_IDX, (Bit32u)(reg)); \
176 outl((iobase) + VBOXAHCI_REG_DATA, (Bit32u)(val))
177
178/** Reads from a AHCI register. */
179#define VBOXAHCI_READ_REG(iobase, reg, val) \
180 outl((iobase) + VBOXAHCI_REG_IDX, (Bit32u)(reg)); \
181 (val) = inl((iobase) + VBOXAHCI_REG_DATA)
182
183/** Writes to the given port register. */
184#define VBOXAHCI_PORT_WRITE_REG(iobase, port, reg, val) \
185 VBOXAHCI_WRITE_REG((iobase), VBOXAHCI_PORT_REG((port), (reg)), val)
186
187/** Reads from the given port register. */
188#define VBOXAHCI_PORT_READ_REG(iobase, port, reg, val) \
189 VBOXAHCI_READ_REG((iobase), VBOXAHCI_PORT_REG((port), (reg)), val)
190
191#define ATA_CMD_IDENTIFY_DEVICE 0xEC
192#define AHCI_CMD_READ_DMA_EXT 0x25
193#define AHCI_CMD_WRITE_DMA_EXT 0x35
194
195/**
196 * Returns the bus/device/function of a PCI device with
197 * the given classcode.
198 *
199 * @returns bus/device/fn in one 16bit integer where
200 * where the upper byte contains the bus number
201 * and lower one the device and function number.
202 * VBOX_AHCI_NO_DEVICE if no device was found.
203 * @param u16Class The classcode to search for.
204 */
205Bit16u ahci_pci_find_classcode(u16Class)
206 Bit32u u16Class;
207{
208 Bit16u u16BusDevFn;
209
210ASM_START
211 push bp
212 mov bp, sp
213
214 mov ah, #PCIBIOS_ID
215 mov al, #PCIBIOS_FIND_CLASS_CODE
216 mov ecx, _ahci_pci_find_classcode.u16Class + 2[bp]
217 mov si, #0 ; First controller
218 int 0x1a
219
220 ; Return from PCIBIOS
221 cmp ah, #SUCCESSFUL
222 jne ahci_pci_find_classcode_not_found
223
224 mov _ahci_pci_find_classcode.u16BusDevFn + 2[bp], bx
225 jmp ahci_pci_find_classcode_done
226
227ahci_pci_find_classcode_not_found:
228 mov _ahci_pci_find_classcode.u16BusDevFn + 2[bp], #VBOX_AHCI_NO_DEVICE
229
230ahci_pci_find_classcode_done:
231 pop bp
232ASM_END
233
234 return u16BusDevFn;
235}
236
237Bit8u ahci_pci_read_config_byte(u8Bus, u8DevFn, u8Reg)
238 Bit8u u8Bus, u8DevFn, u8Reg;
239{
240 Bit8u u8Val;
241
242 u8Val = 0;
243
244ASM_START
245 push bp
246 mov bp, sp
247
248 mov ah, #PCIBIOS_ID
249 mov al, #PCIBIOS_READ_CONFIG_BYTE
250 mov bh, _ahci_pci_read_config_byte.u8Bus + 2[bp]
251 mov bl, _ahci_pci_read_config_byte.u8DevFn + 2[bp]
252 mov di, _ahci_pci_read_config_byte.u8Reg + 2[bp]
253 int 0x1a
254
255 ; Return from PCIBIOS
256 cmp ah, #SUCCESSFUL
257 jne ahci_pci_read_config_byte_done
258
259 mov _ahci_pci_read_config_byte.u8Val + 2[bp], cl
260
261ahci_pci_read_config_byte_done:
262 pop bp
263ASM_END
264
265 return u8Val;
266}
267
268Bit16u ahci_pci_read_config_word(u8Bus, u8DevFn, u8Reg)
269 Bit8u u8Bus, u8DevFn, u8Reg;
270{
271 Bit16u u16Val;
272
273 u16Val = 0;
274
275ASM_START
276 push bp
277 mov bp, sp
278
279 mov ah, #PCIBIOS_ID
280 mov al, #PCIBIOS_READ_CONFIG_WORD
281 mov bh, _ahci_pci_read_config_word.u8Bus + 2[bp]
282 mov bl, _ahci_pci_read_config_word.u8DevFn + 2[bp]
283 mov di, _ahci_pci_read_config_word.u8Reg + 2[bp]
284 int 0x1a
285
286 ; Return from PCIBIOS
287 cmp ah, #SUCCESSFUL
288 jne ahci_pci_read_config_word_done
289
290 mov _ahci_pci_read_config_word.u16Val + 2[bp], cx
291
292ahci_pci_read_config_word_done:
293 pop bp
294ASM_END
295
296 return u16Val;
297}
298
299Bit32u ahci_pci_read_config_dword(u8Bus, u8DevFn, u8Reg)
300 Bit8u u8Bus, u8DevFn, u8Reg;
301{
302 Bit32u u32Val;
303
304 u32Val = 0;
305
306ASM_START
307 push bp
308 mov bp, sp
309
310 mov ah, #PCIBIOS_ID
311 mov al, #PCIBIOS_READ_CONFIG_DWORD
312 mov bh, _ahci_pci_read_config_dword.u8Bus + 2[bp]
313 mov bl, _ahci_pci_read_config_dword.u8DevFn + 2[bp]
314 mov di, _ahci_pci_read_config_dword.u8Reg + 2[bp]
315 int 0x1a
316
317 ; Return from PCIBIOS
318 cmp ah, #SUCCESSFUL
319 jne ahci_pci_read_config_dword_done
320
321 mov _ahci_pci_read_config_dword.u32Val + 2[bp], ecx
322
323ahci_pci_read_config_dword_done:
324 pop bp
325ASM_END
326
327 return u32Val;
328}
329
330#if 0 /* Disabled to save space because they are not needed. Might become useful in the future. */
331/**
332 * Returns the bus/device/function of a PCI device with
333 * the given vendor and device id.
334 *
335 * @returns bus/device/fn in one 16bit integer where
336 * where the upper byte contains the bus number
337 * and lower one the device and function number.
338 * VBOX_AHCI_NO_DEVICE if no device was found.
339 * @param u16Vendor The vendor ID.
340 * @param u16Device The device ID.
341 */
342Bit16u ahci_pci_find_device(u16Vendor, u16Device)
343 Bit16u u16Vendor;
344 Bit16u u16Device;
345{
346 Bit16u u16BusDevFn;
347
348ASM_START
349 push bp
350 mov bp, sp
351
352 mov ah, #PCIBIOS_ID
353 mov al, #PCIBIOS_FIND_PCI_DEVICE
354 mov cx, _ahci_pci_find_device.u16Device + 2[bp]
355 mov dx, _ahci_pci_find_device.u16Vendor + 2[bp]
356 mov si, #0 ; First controller
357 int 0x1a
358
359 ; Return from PCIBIOS
360 cmp ah, #SUCCESSFUL
361 jne ahci_pci_find_device_not_found
362
363 mov _ahci_pci_find_device.u16BusDevFn + 2[bp], bx
364 jmp ahci_pci_find_device_done
365
366ahci_pci_find_device_not_found:
367 mov _ahci_pci_find_device.u16BusDevFn + 2[bp], #VBOX_AHCI_NO_DEVICE
368
369ahci_pci_find_device_done:
370 pop bp
371ASM_END
372
373 return u16BusDevFn;
374}
375
376void ahci_pci_write_config_byte(u8Bus, u8DevFn, u8Reg, u8Val)
377 Bit8u u8Bus, u8DevFn, u8Reg, u8Val;
378{
379ASM_START
380 push bp
381 mov bp, sp
382
383 mov ah, #PCIBIOS_ID
384 mov al, #PCIBIOS_WRITE_CONFIG_BYTE
385 mov bh, _ahci_pci_write_config_byte.u8Bus + 2[bp]
386 mov bl, _ahci_pci_write_config_byte.u8DevFn + 2[bp]
387 mov di, _ahci_pci_write_config_byte.u8Reg + 2[bp]
388 mov cl, _ahci_pci_write_config_byte.u8Val + 2[bp]
389 int 0x1a
390
391 ; Return from PCIBIOS
392 pop bp
393ASM_END
394}
395
396void ahci_pci_write_config_word(u8Bus, u8DevFn, u8Reg, u16Val)
397 Bit8u u8Bus, u8DevFn, u8Reg;
398 Bit16u u16Val;
399{
400ASM_START
401 push bp
402 mov bp, sp
403
404 mov ah, #PCIBIOS_ID
405 mov al, #PCIBIOS_WRITE_CONFIG_WORD
406 mov bh, _ahci_pci_write_config_word.u8Bus + 2[bp]
407 mov bl, _ahci_pci_write_config_word.u8DevFn + 2[bp]
408 mov di, _ahci_pci_write_config_word.u8Reg + 2[bp]
409 mov cx, _ahci_pci_write_config_word.u16Val + 2[bp]
410 int 0x1a
411
412 ; Return from PCIBIOS
413 pop bp
414ASM_END
415}
416
417void ahci_pci_write_config_dword(u8Bus, u8DevFn, u8Reg, u32Val)
418 Bit8u u8Bus, u8DevFn, u8Reg;
419 Bit32u u32Val;
420{
421ASM_START
422 push bp
423 mov bp, sp
424
425 mov ah, #PCIBIOS_ID
426 mov al, #PCIBIOS_WRITE_CONFIG_WORD
427 mov bh, _ahci_pci_write_config_dword.u8Bus + 2[bp]
428 mov bl, _ahci_pci_write_config_dword.u8DevFn + 2[bp]
429 mov di, _ahci_pci_write_config_dword.u8Reg + 2[bp]
430 mov cx, _ahci_pci_write_config_dword.u32Val + 2[bp]
431 int 0x1a
432
433 ; Return from PCIBIOS
434 pop bp
435ASM_END
436}
437#endif /* 0 */
438
439/**
440 * Sets a given set of bits in a register.
441 */
442static void ahci_ctrl_set_bits(u16IoBase, u32Reg, u32Set)
443 Bit16u u16IoBase;
444 Bit32u u32Reg, u32Set;
445{
446ASM_START
447 push bp
448 mov bp, sp
449
450 push eax
451 push edx
452
453 ; Read from the register
454 mov eax, _ahci_ctrl_set_bits.u32Reg + 2[bp]
455 mov dx, _ahci_ctrl_set_bits.u16IoBase + 2[bp]
456 add dx, #VBOXAHCI_REG_IDX
457 out dx, eax
458
459 mov dx, _ahci_ctrl_set_bits.u16IoBase + 2[bp]
460 add dx, #VBOXAHCI_REG_DATA
461 in eax, dx
462
463 ; Set the new bits and write the result to the register again
464 or eax, _ahci_ctrl_set_bits.u32Set + 2[bp]
465 out dx, eax
466
467 pop edx
468 pop eax
469
470 pop bp
471ASM_END
472}
473
474/**
475 * Clears a given set of bits in a register.
476 */
477static void ahci_ctrl_clear_bits(u16IoBase, u32Reg, u32Clear)
478 Bit16u u16IoBase;
479 Bit32u u32Reg, u32Clear;
480{
481ASM_START
482 push bp
483 mov bp, sp
484
485 push eax
486 push ecx
487 push edx
488
489 ; Read from the register
490 mov eax, _ahci_ctrl_clear_bits.u32Reg + 2[bp]
491 mov dx, _ahci_ctrl_clear_bits.u16IoBase + 2[bp]
492 add dx, #VBOXAHCI_REG_IDX
493 out dx, eax
494
495 mov dx, _ahci_ctrl_clear_bits.u16IoBase + 2[bp]
496 add dx, #VBOXAHCI_REG_DATA
497 in eax, dx
498
499 ; Clear the bits and write the result to the register again
500 mov ecx, _ahci_ctrl_clear_bits.u32Clear + 2[bp]
501 not ecx
502 and eax, ecx
503 out dx, eax
504
505 pop edx
506 pop ecx
507 pop eax
508
509 pop bp
510ASM_END
511}
512
513/**
514 * Returns whether at least one of the bits in the given mask is set
515 * for a register.
516 */
517static Bit8u ahci_ctrl_is_bit_set(u16IoBase, u32Reg, u32Mask)
518 Bit16u u16IoBase;
519 Bit32u u32Reg, u32Mask;
520{
521ASM_START
522 push bp
523 mov bp, sp
524
525 push edx
526 push eax
527
528 ; Read from the register
529 mov eax, _ahci_ctrl_is_bit_set.u32Reg + 2[bp]
530 mov dx, _ahci_ctrl_is_bit_set.u16IoBase + 2[bp]
531 add dx, #VBOXAHCI_REG_IDX
532 out dx, eax
533
534 mov dx, _ahci_ctrl_is_bit_set.u16IoBase + 2[bp]
535 add dx, #VBOXAHCI_REG_DATA
536 in eax, dx
537
538 ; Check for set bits
539 mov edx, _ahci_ctrl_is_bit_set.u32Mask + 2[bp]
540 test eax, edx
541 je ahci_ctrl_is_bit_set_not_set
542 mov al, #1 ; At least one of the bits is set
543 jmp ahci_ctrl_is_bit_set_done
544
545ahci_ctrl_is_bit_set_not_set:
546 mov al, #0 ; No bit is set
547
548ahci_ctrl_is_bit_set_done:
549 pop edx ; restore upper 16 bits of eax
550 and edx, #0xffff0000
551 or eax, edx
552 pop edx
553
554 pop bp
555ASM_END
556}
557
558/**
559 * Extracts a range of bits from a register and shifts them
560 * to the right.
561 */
562static Bit16u ahci_ctrl_extract_bits(u32Reg, u32Mask, u8Shift)
563 Bit32u u32Reg, u32Mask, u8Shift;
564{
565ASM_START
566 push bp
567 mov bp, sp
568
569 push cx
570
571 mov eax, _ahci_ctrl_extract_bits.u32Reg + 2[bp]
572 mov cl, _ahci_ctrl_extract_bits.u8Shift + 2[bp]
573 and eax, _ahci_ctrl_extract_bits.u32Mask + 2[bp]
574 shr eax, cl
575
576 pop cx
577
578 pop bp
579ASM_END
580}
581
582/**
583 * Converts a segment:offset pair into a 32bit physical address.
584 */
585static Bit32u ahci_addr_to_phys(u16Segment, u16Offset)
586 Bit16u u16Segment, u16Offset;
587{
588ASM_START
589 push bp
590 mov bp, sp
591
592 push bx
593 push eax
594
595 xor eax, eax
596 xor ebx, ebx
597 mov ax, _ahci_addr_to_phys.u16Segment + 2[bp]
598 shl eax, #4
599 add bx, _ahci_addr_to_phys.u16Offset + 2[bp]
600 add eax, ebx
601
602 mov bx, ax
603 shr eax, #16
604 mov dx, ax
605
606 pop eax
607 mov ax, bx
608 pop bx
609
610 pop bp
611ASM_END
612}
613
614/**
615 * Issues a command to the SATA controller and waits for completion.
616 */
617static void ahci_port_cmd_sync(SegAhci, u16IoBase, fWrite, fAtapi, cFisDWords, cbData)
618 Bit16u SegAhci;
619 Bit16u u16IoBase;
620 bx_bool fWrite;
621 bx_bool fAtapi;
622 Bit8u cFisDWords;
623 Bit16u cbData;
624{
625 Bit8u u8Port;
626
627 u8Port = read_byte(SegAhci, &AhciData->port);
628
629 if (u8Port != 0xff)
630 {
631 Bit32u u32Val;
632
633 /* Prepare the command header. */
634 u32Val = (1L << 16) | RT_BIT_32(7);
635 if (fWrite)
636 u32Val |= RT_BIT_32(6);
637
638 if (fAtapi)
639 u32Val |= RT_BIT_32(5);
640
641 u32Val |= cFisDWords;
642
643 write_dword(SegAhci, &AhciData->abCmdHdr[0], u32Val);
644 write_dword(SegAhci, &AhciData->abCmdHdr[1], (Bit32u)cbData);
645 write_dword(SegAhci, &AhciData->abCmdHdr[2],
646 ahci_addr_to_phys(SegAhci, &AhciData->abCmd[0]));
647
648 /* Enable Command and FIS receive engine. */
649 ahci_ctrl_set_bits(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
650 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
651
652 /* Queue command. */
653 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_CI, 0x1L);
654
655 /* Wait for a D2H Fis. */
656 while (ahci_ctrl_is_bit_set(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_IS),
657 AHCI_REG_PORT_IS_DHRS) == 0)
658 {
659 VBOXAHCI_DEBUG("AHCI: Waiting for a D2H Fis\n");
660 }
661
662 ahci_ctrl_set_bits(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_IS),
663 AHCI_REG_PORT_IS_DHRS); /* Acknowledge received D2H FIS. */
664
665 /* Disable command engine. */
666 ahci_ctrl_clear_bits(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
667 AHCI_REG_PORT_CMD_ST);
668
669 /** @todo: Examine status. */
670 }
671 else
672 VBOXAHCI_DEBUG("AHCI: Invalid port given\n");
673}
674
675/**
676 * Issue command to device.
677 */
678static void ahci_cmd_data(SegAhci, u16IoBase, u8Cmd, u8Feat, u8Device, u8CylHigh, u8CylLow, u8Sect,
679 u8FeatExp, u8CylHighExp, u8CylLowExp, u8SectExp, u8SectCount, u8SectCountExp,
680 SegData, OffData, cbData, fWrite)
681 Bit16u SegAhci;
682 Bit16u u16IoBase;
683 Bit8u u8Cmd, u8Feat, u8Device, u8CylHigh, u8CylLow, u8Sect, u8FeatExp,
684 u8CylHighExp, u8CylLowExp, u8SectExp, u8SectCount, u8SectCountExp;
685 Bit16u SegData, OffData, cbData;
686 bx_bool fWrite;
687{
688 memsetb(SegAhci, &AhciData->abCmd[0], 0, sizeof(AhciData->abCmd));
689
690 /* Prepare the FIS. */
691 write_byte(SegAhci, &AhciData->abCmd[0], 0x27); /* FIS type H2D. */
692 write_byte(SegAhci, &AhciData->abCmd[1], 1 << 7); /* Command update. */
693 write_byte(SegAhci, &AhciData->abCmd[2], u8Cmd);
694 write_byte(SegAhci, &AhciData->abCmd[3], u8Feat);
695
696 write_byte(SegAhci, &AhciData->abCmd[4], u8Sect);
697 write_byte(SegAhci, &AhciData->abCmd[5], u8CylLow);
698 write_byte(SegAhci, &AhciData->abCmd[6], u8CylHigh);
699 write_byte(SegAhci, &AhciData->abCmd[7], u8Device);
700
701 write_byte(SegAhci, &AhciData->abCmd[8], u8SectExp);
702 write_byte(SegAhci, &AhciData->abCmd[9], u8CylLowExp);
703 write_byte(SegAhci, &AhciData->abCmd[10], u8CylHighExp);
704 write_byte(SegAhci, &AhciData->abCmd[11], u8FeatExp);
705
706 write_byte(SegAhci, &AhciData->abCmd[12], u8SectCount);
707 write_byte(SegAhci, &AhciData->abCmd[13], u8SectCountExp);
708
709 /* Prepare PRDT. */
710 write_dword(SegAhci, &AhciData->abCmd[0x80], ahci_addr_to_phys(SegData, OffData));
711 write_dword(SegAhci, &AhciData->abCmd[0x8c], (Bit32u)(cbData - 1));
712
713 ahci_port_cmd_sync(SegAhci, u16IoBase, fWrite, 0, 5, cbData);
714}
715
716/**
717 * Deinits the curent active port.
718 */
719static void ahci_port_deinit_current(SegAhci, u16IoBase)
720 Bit16u SegAhci;
721 Bit16u u16IoBase;
722{
723 Bit8u u8Port;
724
725 u8Port = read_byte(SegAhci, &AhciData->port);
726
727 if (u8Port != 0xff)
728 {
729 /* Put the port into an idle state. */
730 ahci_ctrl_clear_bits(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
731 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
732
733 while (ahci_ctrl_is_bit_set(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
734 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST | AHCI_REG_PORT_CMD_FR | AHCI_REG_PORT_CMD_CR) == 1)
735 {
736 VBOXAHCI_DEBUG("AHCI: Waiting for the port to idle\n");
737 }
738
739 /*
740 * Port idles, set up memory for commands and received FIS and program the
741 * address registers.
742 */
743 memsetb(SegAhci, &AhciData->abFisRecv[0], 0, 0x60);
744 memsetb(SegAhci, &AhciData->abCmdHdr[0], 0, 0x20);
745 memsetb(SegAhci, &AhciData->abCmd[0], 0, 0x84);
746
747 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_FB, 0L);
748 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_FBU, 0L);
749
750 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_CLB, 0L);
751 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_CLBU, 0L);
752
753 /* Disable all interrupts. */
754 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_IE, 0L);
755
756 write_byte(SegAhci, &AhciData->port, 0xff);
757 }
758}
759
760/**
761 * Brings a port into a minimal state to make device detection possible
762 * or to queue requests.
763 */
764static void ahci_port_init(SegAhci, u16IoBase, u8Port)
765 Bit16u SegAhci;
766 Bit16u u16IoBase;
767 Bit8u u8Port;
768{
769 Bit32u u32PhysAddr;
770
771 /* Deinit any other port first. */
772 ahci_port_deinit_current(SegAhci, u16IoBase);
773
774 /* Put the port into an idle state. */
775 ahci_ctrl_clear_bits(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
776 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST);
777
778 while (ahci_ctrl_is_bit_set(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
779 AHCI_REG_PORT_CMD_FRE | AHCI_REG_PORT_CMD_ST | AHCI_REG_PORT_CMD_FR | AHCI_REG_PORT_CMD_CR) == 1)
780 {
781 VBOXAHCI_DEBUG("AHCI: Waiting for the port to idle\n");
782 }
783
784 /*
785 * Port idles, set up memory for commands and received FIS and program the
786 * address registers.
787 */
788 memsetb(SegAhci, &AhciData->abFisRecv[0], 0, 0x60);
789 memsetb(SegAhci, &AhciData->abCmdHdr[0], 0, 0x20);
790 memsetb(SegAhci, &AhciData->abCmd[0], 0, 0x84);
791
792 u32PhysAddr = ahci_addr_to_phys(SegAhci, &AhciData->abFisRecv);
793 VBOXAHCI_DEBUG("AHCI: FIS receive area %lx from %x:%x\n", u32PhysAddr, SegAhci, &AhciData->abFisRecv);
794 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_FB, u32PhysAddr);
795 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_FBU, 0L);
796
797 u32PhysAddr = ahci_addr_to_phys(SegAhci, &AhciData->abCmdHdr);
798 VBOXAHCI_DEBUG("AHCI: CMD list area %lx\n", u32PhysAddr);
799 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_CLB, u32PhysAddr);
800 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_CLBU, 0L);
801
802 /* Disable all interrupts. */
803 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_IE, 0L);
804 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_IS, 0xffffffffL);
805 /* Clear all errors. */
806 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_SERR, 0xffffffffL);
807
808 write_byte(SegAhci, &AhciData->port, u8Port);
809}
810
811/**
812 * Write data to the device.
813 */
814static void ahci_cmd_data_out(SegAhci, u16IoBase, u8Port, u8Cmd, u32Lba, u16Sectors, SegData, OffData)
815 Bit16u SegAhci, u16IoBase;
816 Bit8u u8Port, u8Cmd;
817 Bit32u u32Lba;
818 Bit16u u16Sectors;
819 Bit16u SegData, OffData;
820{
821 Bit8u u8CylLow, u8CylHigh, u8Device, u8Sect, u8CylHighExp, u8CylLowExp, u8SectExp, u8SectCount, u8SectCountExp;
822
823 u8SectCount = (Bit8u)(u16Sectors & 0xff);
824 u8SectCountExp = (Bit8u)((u16Sectors >> 8) & 0xff);;
825 u8Sect = (Bit8u)(u32Lba & 0xff);
826 u8SectExp = (Bit8u)((u32Lba >> 24) & 0xff);
827 u8CylLow = (Bit8u)((u32Lba >> 8) & 0xff);
828 u8CylLowExp = 0;
829 u8CylHigh = (Bit8u)((u32Lba >> 16) & 0xff);
830 u8CylHighExp = 0;
831 u8Device = (1 << 6); /* LBA access */
832
833 ahci_port_init(SegAhci, u16IoBase, u8Port);
834 ahci_cmd_data(SegAhci, u16IoBase, u8Cmd, 0, u8Device, u8CylHigh, u8CylLow,
835 u8Sect,0, u8CylHighExp, u8CylLowExp, u8SectExp, u8SectCount,
836 u8SectCountExp, SegData, OffData, u16Sectors * 512, 1);
837}
838
839/**
840 * Read data from the device.
841 */
842static void ahci_cmd_data_in(SegAhci, u16IoBase, u8Port, u8Cmd, u32Lba, u16Sectors, SegData, OffData)
843 Bit16u SegAhci, u16IoBase;
844 Bit8u u8Port, u8Cmd;
845 Bit32u u32Lba;
846 Bit16u u16Sectors;
847 Bit16u SegData, OffData;
848{
849 Bit8u u8CylLow, u8CylHigh, u8Device, u8Sect, u8CylHighExp, u8CylLowExp, u8SectExp, u8SectCount, u8SectCountExp;
850
851 u8SectCount = (Bit8u)(u16Sectors & 0xff);
852 u8SectCountExp = (Bit8u)((u16Sectors >> 8) & 0xff);;
853 u8Sect = (Bit8u)(u32Lba & 0xff);
854 u8SectExp = (Bit8u)((u32Lba >> 24) & 0xff);
855 u8CylLow = (Bit8u)((u32Lba >> 8) & 0xff);
856 u8CylLowExp = 0;
857 u8CylHigh = (Bit8u)((u32Lba >> 16) & 0xff);
858 u8CylHighExp = 0;
859
860 u8Device = (1 << 6); /* LBA access */
861
862 ahci_port_init(SegAhci, u16IoBase, u8Port);
863 ahci_cmd_data(SegAhci, u16IoBase, u8Cmd, 0, u8Device, u8CylHigh, u8CylLow,
864 u8Sect, 0, u8CylHighExp, u8CylLowExp, u8SectExp, u8SectCount,
865 u8SectCountExp, SegData, OffData, u16Sectors * 512, 0);
866}
867
868static void ahci_port_detect_device(SegAhci, u16IoBase, u8Port)
869 Bit16u SegAhci;
870 Bit16u u16IoBase;
871 Bit8u u8Port;
872{
873 Bit32u val;
874
875 ahci_port_init(SegAhci, u16IoBase, u8Port);
876
877 /* Reset connection. */
878 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_SCTL, 0x01L);
879 /*
880 * According to the spec we should wait at least 1msec until the reset
881 * is cleared but this is a virtual controller so we don't have to.
882 */
883 VBOXAHCI_PORT_WRITE_REG(u16IoBase, u8Port, AHCI_REG_PORT_SCTL, 0x00L);
884
885 /* Check if there is a device on the port. */
886 VBOXAHCI_PORT_READ_REG(u16IoBase, u8Port, AHCI_REG_PORT_SSTS, val);
887 if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 0x3L)
888 {
889 Bit8u idxDevice;
890
891 idxDevice = read_byte(SegAhci, &AhciData->cDevices);
892 VBOXAHCI_DEBUG("AHCI: Device detected on port %d\n", u8Port);
893
894 if (idxDevice < AHCI_MAX_STORAGE_DEVICES)
895 {
896 /* Device detected, enable FIS receive. */
897 ahci_ctrl_set_bits(u16IoBase, VBOXAHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
898 AHCI_REG_PORT_CMD_FRE);
899
900 /* Check signature to determine device type. */
901 VBOXAHCI_PORT_READ_REG(u16IoBase, u8Port, AHCI_REG_PORT_SIG, val);
902 if (val == 0x101L)
903 {
904 Bit8u idxHdCurr;
905 Bit32u cSectors;
906 Bit8u abBuffer[0x0200];
907 Bit8u fRemovable;
908 Bit16u cCylinders, cHeads, cSectorsPerTrack;
909 Bit8u cHardDisksOld;
910 Bit8u idxCmosChsBase;
911
912 idxHdCurr = read_byte(SegAhci, &AhciData->cHardDisks);
913 VBOXAHCI_DEBUG("AHCI: Detected hard disk\n");
914
915 /* Identify device. */
916 ahci_cmd_data(SegAhci, u16IoBase, ATA_CMD_IDENTIFY_DEVICE, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, get_SS(), abBuffer, sizeof(abBuffer), 0);
917
918 write_byte(SegAhci, &AhciData->aDevices[idxDevice].port, u8Port);
919
920 fRemovable = (read_byte(get_SS(),abBuffer+0) & 0x80) ? 1 : 0;
921 cCylinders = read_word(get_SS(),abBuffer+(1*2)); // word 1
922 cHeads = read_word(get_SS(),abBuffer+(3*2)); // word 3
923 cSectorsPerTrack = read_word(get_SS(),abBuffer+(6*2)); // word 6
924 cSectors = read_dword(get_SS(),abBuffer+(60*2)); // word 60 and word 61
925
926 /** @todo update sectors to be a 64 bit number (also lba...). */
927 if (cSectors == 268435455)
928 cSectors = read_dword(get_SS(),abBuffer+(100*2)); // words 100 to 103 (someday)
929
930 VBOXAHCI_DEBUG("AHCI: %ld sectors\n", cSectors);
931
932 write_byte(SegAhci, &AhciData->aDevices[idxDevice].device,ATA_DEVICE_HD);
933 write_byte(SegAhci, &AhciData->aDevices[idxDevice].removable, fRemovable);
934 write_word(SegAhci, &AhciData->aDevices[idxDevice].blksize, 512);
935 write_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.heads, cHeads);
936 write_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.cylinders, cCylinders);
937 write_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.spt, cSectorsPerTrack);
938 write_dword(SegAhci, &AhciData->aDevices[idxDevice].cSectors, cSectors);
939
940 /* Get logical CHS geometry. */
941 switch (idxDevice)
942 {
943 case 0:
944 idxCmosChsBase = 0x40;
945 break;
946 case 1:
947 idxCmosChsBase = 0x48;
948 break;
949 case 2:
950 idxCmosChsBase = 0x50;
951 break;
952 case 3:
953 idxCmosChsBase = 0x58;
954 break;
955 default:
956 idxCmosChsBase = 0;
957 }
958 if (idxCmosChsBase != 0)
959 {
960 cCylinders = inb_cmos(idxCmosChsBase) + (inb_cmos(idxCmosChsBase+1) << 8);
961 cHeads = inb_cmos(idxCmosChsBase+2);
962 cSectorsPerTrack = inb_cmos(idxCmosChsBase+7);
963 }
964 else
965 {
966 cCylinders = 0;
967 cHeads = 0;
968 cSectorsPerTrack = 0;
969 }
970 write_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.heads, cHeads);
971 write_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.cylinders, cCylinders);
972 write_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.spt, cSectorsPerTrack);
973
974 write_byte(SegAhci, &AhciData->aHdIdMap[idxHdCurr], idxDevice);
975 idxHdCurr++;
976 write_byte(SegAhci, &AhciData->cHardDisks, idxHdCurr);
977
978 /* Update hdcount in the BDA. */
979 cHardDisksOld = read_byte(0x40, 0x75);
980 cHardDisksOld++;
981 write_byte(0x40, 0x75, cHardDisksOld);
982 }
983 else if (val == 0xeb140101)
984 {
985 VBOXAHCI_DEBUG("AHCI: Detected ATAPI device\n");
986 }
987 else
988 VBOXAHCI_DEBUG("AHCI: Unknown device ignoring\n");
989
990 idxDevice++;
991 write_byte(SegAhci, &AhciData->cDevices, idxDevice);
992 }
993 else
994 VBOXAHCI_DEBUG("AHCI: Reached maximum device count, skipping\n");
995 }
996}
997
998#define SET_DISK_RET_STATUS(status) write_byte(0x0040, 0x0074, status)
999
1000/**
1001 * Int 13 handler.
1002 */
1003static void ahci_int13(RET, ES, DS, DI, SI, BP, SP, BX, DX, CX, AX, IPIRET, CSIRET, FLAGSIRET, IP, CS, FLAGS)
1004 Bit16u RET, ES, DS, AX, CX, DX, BX, SP, BP, SI, DI, IPIRET, CSIRET, FLAGSIRET, IP, CS, FLAGS;
1005{
1006 Bit16u ebda_seg;
1007 Bit16u SegAhci, u16IoBase;
1008 Bit8u idxDevice;
1009 Bit8u cHardDisksOld;
1010 Bit8u u8Port;
1011
1012 Bit32u lba;
1013 Bit16u cylinder, head, sector;
1014 Bit16u segment, offset;
1015 Bit16u npc, nph, npspt, nlc, nlh, nlspt;
1016 Bit16u size, count;
1017 Bit8u status;
1018
1019 VBOXAHCI_INT13_DEBUG("AHCI: ahci_int13 AX=%x CX=%x DX=%x BX=%x SP=%x BP=%x SI=%x DI=%x IP=%x CS=%x FLAGS=%x\n",
1020 AX, CX, DX, BX, SP, BP, SI, DI, IP, CS, FLAGS);
1021
1022 ebda_seg = read_word(0x0040, 0x000E);
1023 SegAhci = read_word(ebda_seg, &EbdaData->SegAhci);
1024 u16IoBase = read_word(SegAhci, &AhciData->iobase);
1025 VBOXAHCI_INT13_DEBUG("AHCI: ahci_int13: SegAhci=%x u16IoBase=%x\n", SegAhci, u16IoBase);
1026
1027 cHardDisksOld = read_byte(SegAhci, &AhciData->cHardDisksOld);
1028
1029 /* Check if the device is controlled by us first. */
1030 if ( (GET_DL() < 0x80)
1031 || (GET_DL() < 0x80 + cHardDisksOld)
1032 || ((GET_DL() & 0xe0) != 0x80) /* No CD-ROM drives supported for now */)
1033 {
1034 VBOXAHCI_INT13_DEBUG("AHCI: ahci_int13 device not controlled by us, forwarding to old handler (%d)\n", cHardDisksOld);
1035 /* Fill the iret frame to jump to the old handler. */
1036 IPIRET = read_word(SegAhci, &AhciData->pfnInt13Old);
1037 CSIRET = 0xf000;
1038 FLAGSIRET = FLAGS;
1039 RET = 1;
1040 return;
1041 }
1042
1043 idxDevice = read_byte(SegAhci, &AhciData->aHdIdMap[GET_DL()-0x80-cHardDisksOld]);
1044
1045 if (idxDevice >= AHCI_MAX_STORAGE_DEVICES)
1046 {
1047 VBOXAHCI_INT13_DEBUG("AHCI: ahci_int13: function %02x, unmapped device for ELDL=%02x\n", GET_AH(), GET_DL());
1048 goto ahci_int13_fail;
1049 }
1050
1051 u8Port = read_byte(SegAhci, &AhciData->aDevices[idxDevice].port);
1052
1053 switch (GET_AH())
1054 {
1055 case 0x00: /* disk controller reset */
1056 {
1057 /** @todo: not really important I think. */
1058 goto ahci_int13_success;
1059 break;
1060 }
1061 case 0x01: /* read disk status */
1062 {
1063 status = read_byte(0x0040, 0x0074);
1064 SET_AH(status);
1065 SET_DISK_RET_STATUS(0);
1066 /* set CF if error status read */
1067 if (status)
1068 goto ahci_int13_fail_nostatus;
1069 else
1070 goto ahci_int13_success_noah;
1071 break;
1072 }
1073 case 0x02: // read disk sectors
1074 case 0x03: // write disk sectors
1075 case 0x04: // verify disk sectors
1076 {
1077 count = GET_AL();
1078 cylinder = GET_CH();
1079 cylinder |= ( ((Bit16u) GET_CL()) << 2) & 0x300;
1080 sector = (GET_CL() & 0x3f);
1081 head = GET_DH();
1082
1083 segment = ES;
1084 offset = BX;
1085
1086 if ( (count > 128) || (count == 0) )
1087 {
1088 BX_INFO("int13_harddisk: function %02x, count out of range!\n",GET_AH());
1089 goto ahci_int13_fail;
1090 }
1091
1092 nlc = read_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.cylinders);
1093 nlh = read_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.heads);
1094 nlspt = read_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.spt);
1095
1096 // sanity check on cyl heads, sec
1097 if( (cylinder >= nlc) || (head >= nlh) || (sector > nlspt ))
1098 {
1099 BX_INFO("ahci_int13: function %02x, disk %02x, parameters out of range %04x/%04x/%04x!\n", GET_AH(), GET_DL(), cylinder, head, sector);
1100 goto ahci_int13_fail;
1101 }
1102
1103 // FIXME verify
1104 if ( GET_AH() == 0x04 )
1105 goto ahci_int13_success;
1106
1107 lba = ((((Bit32u)cylinder * (Bit32u)nlh) + (Bit32u)head) * (Bit32u)nlspt) + (Bit32u)sector - 1;
1108
1109 status = 0;
1110 if ( GET_AH() == 0x02 )
1111 ahci_cmd_data_in(SegAhci, u16IoBase, u8Port, AHCI_CMD_READ_DMA_EXT, lba, count, segment, offset);
1112 else
1113 ahci_cmd_data_out(SegAhci, u16IoBase, u8Port, AHCI_CMD_WRITE_DMA_EXT, lba, count, segment, offset);
1114
1115 // Set nb of sector transferred
1116 SET_AL(read_word(ebda_seg, &EbdaData->ata.trsfsectors));
1117
1118 if (status != 0)
1119 {
1120 BX_INFO("int13_harddisk: function %02x, error %02x !\n",GET_AH(),status);
1121 SET_AH(0x0c);
1122 goto ahci_int13_fail_noah;
1123 }
1124
1125 goto ahci_int13_success;
1126 break;
1127 }
1128 case 0x05: /* format disk track */
1129 BX_INFO("format disk track called\n");
1130 goto ahci_int13_success;
1131 break;
1132 case 0x08: /* read disk drive parameters */
1133 {
1134 // Get logical geometry from table
1135 nlc = read_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.cylinders);
1136 nlh = read_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.heads);
1137 nlspt = read_word(SegAhci, &AhciData->aDevices[idxDevice].lchs.spt);
1138
1139 count = read_byte(SegAhci, &AhciData->cHardDisks); /** @todo correct? */
1140 /* Maximum cylinder number is just one less than the number of cylinders. */
1141 nlc = nlc - 1; /* 0 based , last sector not used */
1142 SET_AL(0);
1143 SET_CH(nlc & 0xff);
1144 SET_CL(((nlc >> 2) & 0xc0) | (nlspt & 0x3f));
1145 SET_DH(nlh - 1);
1146 SET_DL(count); /* FIXME returns 0, 1, or n hard drives */
1147 // FIXME should set ES & DI
1148 goto ahci_int13_success;
1149 break;
1150 }
1151 case 0x10: /* check drive ready */
1152 {
1153 /** @todo */
1154 goto ahci_int13_success;
1155 break;
1156 }
1157 case 0x15: /* read disk drive size */
1158 {
1159 // Get physical geometry from table
1160 npc = read_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.cylinders);
1161 nph = read_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.heads);
1162 npspt = read_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.spt);
1163
1164 // Compute sector count seen by int13
1165 lba = (Bit32u)npc * (Bit32u)nph * (Bit32u)npspt;
1166 CX = lba >> 16;
1167 DX = lba & 0xffff;
1168
1169 SET_AH(3); // hard disk accessible
1170 goto ahci_int13_success_noah;
1171 break;
1172 }
1173#if 0
1174 case 0x41: // IBM/MS installation check
1175 {
1176 BX=0xaa55; // install check
1177 SET_AH(0x30); // EDD 3.0
1178 CX=0x0007; // ext disk access and edd, removable supported
1179 goto ahci_int13_success_noah;
1180 break;
1181 }
1182 case 0x42: // IBM/MS extended read
1183 case 0x43: // IBM/MS extended write
1184 case 0x44: // IBM/MS verify
1185 case 0x47: // IBM/MS extended seek
1186 {
1187 count=read_word(DS, SI+(Bit16u)&Int13Ext->count);
1188 segment=read_word(DS, SI+(Bit16u)&Int13Ext->segment);
1189 offset=read_word(DS, SI+(Bit16u)&Int13Ext->offset);
1190
1191 // Can't use 64 bits lba
1192 lba=read_dword(DS, SI+(Bit16u)&Int13Ext->lba2);
1193 if (lba != 0L)
1194 {
1195 BX_PANIC("int13_harddisk: function %02x. Can't use 64bits lba\n",GET_AH());
1196 goto ahci_int13_fail;
1197 }
1198
1199 // Get 32 bits lba and check
1200 lba=read_dword(DS, SI+(Bit16u)&Int13Ext->lba1);
1201
1202 if (lba >= read_word(SegAhci, &AhciData->aDevices[idxDevice].cSectors) )
1203 {
1204 BX_INFO("int13_harddisk: function %02x. LBA out of range\n",GET_AH());
1205 goto ahci_int13_fail;
1206 }
1207
1208 // If verify or seek
1209 if (( GET_AH() == 0x44 ) || ( GET_AH() == 0x47 ))
1210 goto ahci_int13_success;
1211
1212 // Execute the command
1213 if ( GET_AH() == 0x42 )
1214 {
1215 if (lba + count >= 268435456)
1216 status=ata_cmd_data_in(device, ATA_CMD_READ_SECTORS_EXT, count, 0, 0, 0, lba, segment, offset);
1217 else
1218 {
1219 write_word(ebda_seg,&EbdaData->ata.devices[device].blksize,count * 0x200);
1220 status=ata_cmd_data_in(device, ATA_CMD_READ_MULTIPLE, count, 0, 0, 0, lba, segment, offset);
1221 write_word(ebda_seg,&EbdaData->ata.devices[device].blksize,0x200);
1222 }
1223 }
1224 else
1225 {
1226 if (lba + count >= 268435456)
1227 status=ata_cmd_data_out(device, ATA_CMD_WRITE_SECTORS_EXT, count, 0, 0, 0, lba, segment, offset);
1228 else
1229 status=ata_cmd_data_out(device, ATA_CMD_WRITE_SECTORS, count, 0, 0, 0, lba, segment, offset);
1230 }
1231
1232 count=read_word(ebda_seg, &EbdaData->ata.trsfsectors);
1233 write_word(DS, SI+(Bit16u)&Int13Ext->count, count);
1234
1235 if (status != 0)
1236 {
1237 BX_INFO("int13_harddisk: function %02x, error %02x !\n",GET_AH(),status);
1238 SET_AH(0x0c);
1239 goto ahci_int13_fail_noah;
1240 }
1241 goto ahci_int13_success;
1242 break;
1243 }
1244 case 0x45: // IBM/MS lock/unlock drive
1245 case 0x49: // IBM/MS extended media change
1246 goto ahci_int13_success; // Always success for HD
1247 break;
1248 case 0x46: // IBM/MS eject media
1249 SET_AH(0xb2); // Volume Not Removable
1250 goto ahci_int13_fail_noah; // Always fail for HD
1251 break;
1252
1253 case 0x48: // IBM/MS get drive parameters
1254 size=read_word(DS,SI+(Bit16u)&Int13DPT->size);
1255
1256 // Buffer is too small
1257 if(size < 0x1a)
1258 goto ahci_int13_fail;
1259
1260 // EDD 1.x
1261 if(size >= 0x1a)
1262 {
1263 Bit16u blksize;
1264
1265 npc = read_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.cylinders);
1266 nph = read_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.heads);
1267 npspt = read_word(SegAhci, &AhciData->aDevices[idxDevice].pchs.spt);
1268 lba = read_dword(SegAhci, &AhciData->aDevices[idxDevice].cSectors);
1269 blksize = read_word(SegAhci, &AhciData->aDevices[idxDevice].blksize);
1270
1271 write_word(DS, SI+(Bit16u)&Int13DPT->size, 0x1a);
1272 write_word(DS, SI+(Bit16u)&Int13DPT->infos, 0x02); // geometry is valid
1273 write_dword(DS, SI+(Bit16u)&Int13DPT->cylinders, (Bit32u)npc);
1274 write_dword(DS, SI+(Bit16u)&Int13DPT->heads, (Bit32u)nph);
1275 write_dword(DS, SI+(Bit16u)&Int13DPT->spt, (Bit32u)npspt);
1276 write_dword(DS, SI+(Bit16u)&Int13DPT->sector_count1, lba); // FIXME should be Bit64
1277 write_dword(DS, SI+(Bit16u)&Int13DPT->sector_count2, 0L);
1278 write_word(DS, SI+(Bit16u)&Int13DPT->blksize, blksize);
1279 }
1280
1281#if 0 /* Disable EDD 2.X and 3.x for now, don't know if it is required by any OS loader yet */
1282 // EDD 2.x
1283 if(size >= 0x1e)
1284 {
1285 Bit8u channel, dev, irq, mode, checksum, i, translation;
1286 Bit16u iobase1, iobase2, options;
1287
1288 translation = ATA_TRANSLATION_LBA;
1289
1290 write_word(DS, SI+(Bit16u)&Int13DPT->size, 0x1e);
1291
1292 write_word(DS, SI+(Bit16u)&Int13DPT->dpte_segment, ebda_seg);
1293 write_word(DS, SI+(Bit16u)&Int13DPT->dpte_offset, &EbdaData->ata.dpte);
1294
1295 // Fill in dpte
1296 channel = device / 2;
1297 iobase1 = read_word(ebda_seg, &EbdaData->ata.channels[channel].iobase1);
1298 iobase2 = read_word(ebda_seg, &EbdaData->ata.channels[channel].iobase2);
1299 irq = read_byte(ebda_seg, &EbdaData->ata.channels[channel].irq);
1300 mode = read_byte(ebda_seg, &EbdaData->ata.devices[device].mode);
1301 translation = read_byte(ebda_seg, &EbdaData->ata.devices[device].translation);
1302
1303 options = (translation==ATA_TRANSLATION_NONE?0:1<<3); // chs translation
1304 options |= (1<<4); // lba translation
1305 options |= (mode==ATA_MODE_PIO32?1:0<<7);
1306 options |= (translation==ATA_TRANSLATION_LBA?1:0<<9);
1307 options |= (translation==ATA_TRANSLATION_RECHS?3:0<<9);
1308
1309 write_word(ebda_seg, &EbdaData->ata.dpte.iobase1, iobase1);
1310 write_word(ebda_seg, &EbdaData->ata.dpte.iobase2, iobase2);
1311 //write_byte(ebda_seg, &EbdaData->ata.dpte.prefix, (0xe | /*(device % 2))<<4*/ );
1312 write_byte(ebda_seg, &EbdaData->ata.dpte.unused, 0xcb );
1313 write_byte(ebda_seg, &EbdaData->ata.dpte.irq, irq );
1314 write_byte(ebda_seg, &EbdaData->ata.dpte.blkcount, 1 );
1315 write_byte(ebda_seg, &EbdaData->ata.dpte.dma, 0 );
1316 write_byte(ebda_seg, &EbdaData->ata.dpte.pio, 0 );
1317 write_word(ebda_seg, &EbdaData->ata.dpte.options, options);
1318 write_word(ebda_seg, &EbdaData->ata.dpte.reserved, 0);
1319 write_byte(ebda_seg, &EbdaData->ata.dpte.revision, 0x11);
1320
1321 checksum=0;
1322 for (i=0; i<15; i++)
1323 checksum+=read_byte(ebda_seg, (&EbdaData->ata.dpte) + i);
1324
1325 checksum = -checksum;
1326 write_byte(ebda_seg, &EbdaData->ata.dpte.checksum, checksum);
1327 }
1328
1329 // EDD 3.x
1330 if(size >= 0x42)
1331 {
1332 Bit8u channel, iface, checksum, i;
1333 Bit16u iobase1;
1334
1335 channel = device / 2;
1336 iface = read_byte(ebda_seg, &EbdaData->ata.channels[channel].iface);
1337 iobase1 = read_word(ebda_seg, &EbdaData->ata.channels[channel].iobase1);
1338
1339 write_word(DS, SI+(Bit16u)&Int13DPT->size, 0x42);
1340 write_word(DS, SI+(Bit16u)&Int13DPT->key, 0xbedd);
1341 write_byte(DS, SI+(Bit16u)&Int13DPT->dpi_length, 0x24);
1342 write_byte(DS, SI+(Bit16u)&Int13DPT->reserved1, 0);
1343 write_word(DS, SI+(Bit16u)&Int13DPT->reserved2, 0);
1344
1345 if (iface==ATA_IFACE_ISA) {
1346 write_byte(DS, SI+(Bit16u)&Int13DPT->host_bus[0], 'I');
1347 write_byte(DS, SI+(Bit16u)&Int13DPT->host_bus[1], 'S');
1348 write_byte(DS, SI+(Bit16u)&Int13DPT->host_bus[2], 'A');
1349 write_byte(DS, SI+(Bit16u)&Int13DPT->host_bus[3], 0);
1350 }
1351 else {
1352 // FIXME PCI
1353 }
1354 write_byte(DS, SI+(Bit16u)&Int13DPT->iface_type[0], 'A');
1355 write_byte(DS, SI+(Bit16u)&Int13DPT->iface_type[1], 'T');
1356 write_byte(DS, SI+(Bit16u)&Int13DPT->iface_type[2], 'A');
1357 write_byte(DS, SI+(Bit16u)&Int13DPT->iface_type[3], 0);
1358
1359 if (iface==ATA_IFACE_ISA) {
1360 write_word(DS, SI+(Bit16u)&Int13DPT->iface_path[0], iobase1);
1361 write_word(DS, SI+(Bit16u)&Int13DPT->iface_path[2], 0);
1362 write_dword(DS, SI+(Bit16u)&Int13DPT->iface_path[4], 0L);
1363 }
1364 else {
1365 // FIXME PCI
1366 }
1367 //write_byte(DS, SI+(Bit16u)&Int13DPT->device_path[0], device%2);
1368 write_byte(DS, SI+(Bit16u)&Int13DPT->device_path[1], 0);
1369 write_word(DS, SI+(Bit16u)&Int13DPT->device_path[2], 0);
1370 write_dword(DS, SI+(Bit16u)&Int13DPT->device_path[4], 0L);
1371
1372 checksum=0;
1373 for (i=30; i<64; i++) checksum+=read_byte(DS, SI + i);
1374 checksum = -checksum;
1375 write_byte(DS, SI+(Bit16u)&Int13DPT->checksum, checksum);
1376 }
1377#endif
1378 goto ahci_int13_success;
1379 break;
1380 case 0x4e: // // IBM/MS set hardware configuration
1381 // DMA, prefetch, PIO maximum not supported
1382 switch (GET_AL())
1383 {
1384 case 0x01:
1385 case 0x03:
1386 case 0x04:
1387 case 0x06:
1388 goto ahci_int13_success;
1389 break;
1390 default :
1391 goto ahci_int13_fail;
1392 }
1393 break;
1394#endif
1395 case 0x09: /* initialize drive parameters */
1396 case 0x0c: /* seek to specified cylinder */
1397 case 0x0d: /* alternate disk reset */
1398 case 0x11: /* recalibrate */
1399 case 0x14: /* controller internal diagnostic */
1400 BX_INFO("ahci_int13: function %02xh unimplemented, returns success\n", GET_AH());
1401 goto ahci_int13_success;
1402 break;
1403
1404 case 0x0a: /* read disk sectors with ECC */
1405 case 0x0b: /* write disk sectors with ECC */
1406 case 0x18: // set media type for format
1407 case 0x50: // IBM/MS send packet command
1408 default:
1409 BX_INFO("ahci_int13: function %02xh unsupported, returns fail\n", GET_AH());
1410 goto ahci_int13_fail;
1411 break;
1412 }
1413
1414ahci_int13_fail:
1415 SET_AH(0x01); // defaults to invalid function in AH or invalid parameter
1416ahci_int13_fail_noah:
1417 SET_DISK_RET_STATUS(GET_AH());
1418ahci_int13_fail_nostatus:
1419 SET_CF(); // error occurred
1420 return;
1421
1422ahci_int13_success:
1423 SET_AH(0x00); // no error
1424ahci_int13_success_noah:
1425 SET_DISK_RET_STATUS(0x00);
1426 CLEAR_CF(); // no error
1427 return;
1428}
1429
1430#undef SET_DISK_RET_STATUS
1431
1432/**
1433 * Assembler part of the int 13 handler.
1434 */
1435ASM_START
1436ahci_int13_handler:
1437 ; Allocate space for an iret frame we have to use
1438 ; to call the old int 13 handler
1439 push #0x0000
1440 push #0x0000
1441 push #0x0000
1442
1443 pusha ; Save 16bit values as arguments
1444 push ds
1445 push es
1446 mov ax, #0 ; Allocate room for the return value on the stack
1447 push ax
1448 call _ahci_int13
1449 pop ax
1450 pop es
1451 pop ds
1452 cmp ax, #0x0 ; Check if the handler processed the request
1453 je ahci_int13_out
1454 popa ; Restore the caller environment
1455 iret ; Call the old interrupt handler. Will not come back here.
1456
1457ahci_int13_out:
1458 popa
1459 add sp, #6 ; Destroy the iret frame
1460 iret
1461ASM_END
1462
1463/**
1464 * Install the in13 interrupt handler
1465 * preserving the previous one.
1466 */
1467static void ahci_install_int_handler(SegAhci)
1468 Bit16u SegAhci;
1469{
1470
1471 Bit16u pfnInt13Old;
1472
1473 VBOXAHCI_DEBUG("AHCI: Hooking int 13h vector\n");
1474
1475 /* Read the old interrupt handler. */
1476 pfnInt13Old = read_word(0x0000, 0x0013*4);
1477 write_word(SegAhci, &AhciData->pfnInt13Old, pfnInt13Old);
1478
1479 /* Set our own */
1480 ASM_START
1481
1482 push bp
1483 mov bp, sp
1484
1485 push ax
1486 SET_INT_VECTOR(0x13, #0xF000, #ahci_int13_handler)
1487 pop ax
1488
1489 pop bp
1490 ASM_END
1491}
1492
1493/**
1494 * Allocates 1K from the base memory.
1495 */
1496static Bit16u ahci_mem_alloc()
1497{
1498 Bit16u cBaseMem1K;
1499 Bit16u SegStart;
1500
1501 cBaseMem1K = read_byte(0x00, 0x0413);
1502
1503 VBOXAHCI_DEBUG("AHCI: %x K of base memory available\n", cBaseMem1K);
1504
1505 if (cBaseMem1K == 0)
1506 return 0;
1507
1508 cBaseMem1K--; /* Allocate one block. */
1509 SegStart = (Bit16u)(((Bit32u)cBaseMem1K * 1024) >> 4); /* Calculate start segment. */
1510
1511 write_byte(0x00, 0x0413, cBaseMem1K);
1512
1513 return SegStart;
1514}
1515
1516/**
1517 * Initializes the SATA controller and detects attached devices.
1518 */
1519static int ahci_ctrl_init(u16IoBase)
1520 Bit16u u16IoBase;
1521{
1522 Bit8u i, cPorts;
1523 Bit32u val;
1524 Bit16u ebda_seg;
1525 Bit16u SegAhci;
1526
1527 ebda_seg = read_word(0x0040, 0x000E);
1528
1529 VBOXAHCI_READ_REG(u16IoBase, AHCI_REG_VS, val);
1530 VBOXAHCI_DEBUG("AHCI: Controller has version: 0x%x (major) 0x%x (minor)\n",
1531 ahci_ctrl_extract_bits(val, 0xffff0000, 16),
1532 ahci_ctrl_extract_bits(val, 0x0000ffff, 0));
1533
1534 /* Allocate 1K of base memory. */
1535 SegAhci = ahci_mem_alloc();
1536 if (SegAhci == 0)
1537 {
1538 VBOXAHCI_DEBUG("AHCI: Could not allocate 1K of memory, can't boot from controller\n");
1539 return 0;
1540 }
1541
1542 write_word(ebda_seg, &EbdaData->SegAhci, SegAhci);
1543 write_byte(SegAhci, &AhciData->port, 0xff);
1544 write_word(SegAhci, &AhciData->iobase, u16IoBase);
1545 write_byte(SegAhci, &AhciData->cHardDisksOld, read_byte(0x40, 0x75));
1546
1547 /* Reset the controller. */
1548 ahci_ctrl_set_bits(u16IoBase, AHCI_REG_GHC, AHCI_GHC_HR);
1549 do
1550 {
1551 VBOXAHCI_READ_REG(u16IoBase, AHCI_REG_GHC, val);
1552 } while (val & AHCI_GHC_HR != 0);
1553
1554 VBOXAHCI_READ_REG(u16IoBase, AHCI_REG_CAP, val);
1555 cPorts = ahci_ctrl_extract_bits(val, 0x1f, 0) + 1; /* Extract number of ports.*/
1556
1557 VBOXAHCI_DEBUG("AHCI: Controller has %u ports\n", cPorts);
1558
1559 /* Go through the ports. */
1560 i = 0;
1561 while (i < 32)
1562 {
1563 if (ahci_ctrl_is_bit_set(u16IoBase, AHCI_REG_PI, RT_BIT_32(i)) != 0)
1564 {
1565 VBOXAHCI_DEBUG("AHCI: Port %u is present\n", i);
1566 ahci_port_detect_device(SegAhci, u16IoBase, i);
1567 cPorts--;
1568 if (cPorts == 0)
1569 break;
1570 }
1571 i++;
1572 }
1573
1574 if (read_byte(SegAhci, &AhciData->cDevices) > 0)
1575 {
1576 /*
1577 * Init completed and there is at least one device present.
1578 * Install our int13 handler.
1579 */
1580 ahci_install_int_handler(SegAhci);
1581 }
1582
1583 return 0;
1584}
1585
1586/**
1587 * Init the AHCI driver and detect attached disks.
1588 */
1589void ahci_init( )
1590{
1591 Bit16u ebda_seg;
1592 Bit16u busdevfn;
1593
1594 ebda_seg = read_word(0x0040, 0x000E);
1595
1596 busdevfn = ahci_pci_find_classcode(0x00010601);
1597 if (busdevfn != VBOX_AHCI_NO_DEVICE)
1598 {
1599 Bit8u u8Bus, u8DevFn;
1600 Bit8u u8PciCapOff;
1601
1602 u8Bus = (busdevfn & 0xff00) >> 8;
1603 u8DevFn = busdevfn & 0x00ff;
1604
1605 VBOXAHCI_DEBUG("Found AHCI controller at Bus %u DevFn 0x%x (raw 0x%x)\n", u8Bus, u8DevFn, busdevfn);
1606
1607 /* Examine the capability list and search for the Serial ATA Capability Register. */
1608 u8PciCapOff = ahci_pci_read_config_byte(u8Bus, u8DevFn, PCI_CONFIG_CAP);
1609
1610 while (u8PciCapOff != 0)
1611 {
1612 Bit8u u8PciCapId = ahci_pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
1613
1614 VBOXAHCI_DEBUG("Capability ID 0x%x at offset 0x%x found\n", u8PciCapId, u8PciCapOff);
1615
1616 if (u8PciCapId == PCI_CAP_ID_SATACR)
1617 break;
1618
1619 /* Go on to the next capability. */
1620 u8PciCapOff = ahci_pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
1621 }
1622
1623 if (u8PciCapOff != 0)
1624 {
1625 Bit8u u8Rev;
1626
1627 VBOXAHCI_DEBUG("AHCI controller with SATA Capability register at offset 0x%x found\n", u8PciCapOff);
1628
1629 /* Advance to the stuff behind the id and next capability pointer. */
1630 u8PciCapOff += 2;
1631
1632 u8Rev = ahci_pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
1633 if (u8Rev == 0x10)
1634 {
1635 /* Read the SATACR1 register and get the bar and offset of the index/data pair register. */
1636 Bit8u u8Bar = 0x00;
1637 Bit16u u16Off = 0x00;
1638 Bit16u u16BarOff = ahci_pci_read_config_word(u8Bus, u8DevFn, u8PciCapOff + 2);
1639
1640 VBOXAHCI_DEBUG("SATACR1 register contains 0x%x\n", u16BarOff);
1641
1642 switch (u16BarOff & 0xf)
1643 {
1644 case 0x04:
1645 u8Bar = 0x10;
1646 break;
1647 case 0x05:
1648 u8Bar = 0x14;
1649 break;
1650 case 0x06:
1651 u8Bar = 0x18;
1652 break;
1653 case 0x07:
1654 u8Bar = 0x1c;
1655 break;
1656 case 0x08:
1657 u8Bar = 0x20;
1658 break;
1659 case 0x09:
1660 u8Bar = 0x24;
1661 break;
1662 case 0x0f:
1663 default:
1664 /* Reserved or unsupported. */
1665 VBOXAHCI_DEBUG("BAR location 0x%x is unsupported\n", u16BarOff & 0xf);
1666 }
1667
1668 /* Get the offset inside the BAR from bits 4:15. */
1669 u16Off = (u16BarOff >> 4) * 4;
1670
1671 if (u8Bar != 0x00)
1672 {
1673 Bit32u u32Bar = ahci_pci_read_config_dword(u8Bus, u8DevFn, u8Bar);
1674
1675 VBOXAHCI_DEBUG("BAR at offset 0x%x contains 0x%x\n", u8Bar, u32Bar);
1676
1677 if ((u32Bar & 0x01) != 0)
1678 {
1679 int rc;
1680 Bit16u u16AhciIoBase = (u32Bar & 0xfff0) + u16Off;
1681
1682 VBOXAHCI_DEBUG("I/O base is 0x%x\n", u16AhciIoBase);
1683 rc = ahci_ctrl_init(u16AhciIoBase);
1684 }
1685 else
1686 VBOXAHCI_DEBUG("BAR is MMIO\n");
1687 }
1688 }
1689 else
1690 VBOXAHCI_DEBUG("Invalid revision 0x%x\n", u8Rev);
1691 }
1692 else
1693 VBOXAHCI_DEBUG("AHCI controller without usable Index/Data register pair found\n");
1694 }
1695 else
1696 VBOXAHCI_DEBUG("No AHCI controller found\n");
1697}
1698
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