1 | /*
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2 | * Copyright (C) 2006-2011 Oracle Corporation
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3 | *
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4 | * This file is part of VirtualBox Open Source Edition (OSE), as
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5 | * available from http://www.virtualbox.org. This file is free software;
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6 | * you can redistribute it and/or modify it under the terms of the GNU
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7 | * General Public License (GPL) as published by the Free Software
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8 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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9 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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10 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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11 | * --------------------------------------------------------------------
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12 | *
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13 | * This code is based on:
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14 | *
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15 | * ROM BIOS for use with Bochs/Plex86/QEMU emulation environment
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16 | *
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17 | * Copyright (C) 2002 MandrakeSoft S.A.
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18 | *
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19 | * MandrakeSoft S.A.
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20 | * 43, rue d'Aboukir
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21 | * 75002 Paris - France
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22 | * http://www.linux-mandrake.com/
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23 | * http://www.mandrakesoft.com/
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24 | *
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25 | * This library is free software; you can redistribute it and/or
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26 | * modify it under the terms of the GNU Lesser General Public
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27 | * License as published by the Free Software Foundation; either
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28 | * version 2 of the License, or (at your option) any later version.
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29 | *
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30 | * This library is distributed in the hope that it will be useful,
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31 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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33 | * Lesser General Public License for more details.
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34 | *
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35 | * You should have received a copy of the GNU Lesser General Public
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36 | * License along with this library; if not, write to the Free Software
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37 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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38 | *
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39 | */
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40 |
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41 |
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42 | #define ATA_DATA_NO 0x00
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43 | #define ATA_DATA_IN 0x01
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44 | #define ATA_DATA_OUT 0x02
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45 |
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46 | #define ATA_IFACE_NONE 0x00
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47 | #define ATA_IFACE_ISA 0x00
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48 | #define ATA_IFACE_PCI 0x01
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49 |
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50 | #define ATA_MODE_NONE 0x00
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51 | #define ATA_MODE_PIO16 0x00
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52 | #define ATA_MODE_PIO32 0x01
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53 | #define ATA_MODE_ISADMA 0x02
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54 | #define ATA_MODE_PCIDMA 0x03
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55 | #define ATA_MODE_USEIRQ 0x10
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56 |
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57 | // Global defines -- ATA register and register bits.
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58 | // command block & control block regs
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59 | #define ATA_CB_DATA 0 // data reg in/out pio_base_addr1+0
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60 | #define ATA_CB_ERR 1 // error in pio_base_addr1+1
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61 | #define ATA_CB_FR 1 // feature reg out pio_base_addr1+1
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62 | #define ATA_CB_SC 2 // sector count in/out pio_base_addr1+2
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63 | #define ATA_CB_SN 3 // sector number in/out pio_base_addr1+3
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64 | #define ATA_CB_CL 4 // cylinder low in/out pio_base_addr1+4
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65 | #define ATA_CB_CH 5 // cylinder high in/out pio_base_addr1+5
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66 | #define ATA_CB_DH 6 // device head in/out pio_base_addr1+6
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67 | #define ATA_CB_STAT 7 // primary status in pio_base_addr1+7
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68 | #define ATA_CB_CMD 7 // command out pio_base_addr1+7
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69 | #define ATA_CB_ASTAT 6 // alternate status in pio_base_addr2+6
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70 | #define ATA_CB_DC 6 // device control out pio_base_addr2+6
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71 | #define ATA_CB_DA 7 // device address in pio_base_addr2+7
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72 |
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73 | #define ATA_CB_ER_ICRC 0x80 // ATA Ultra DMA bad CRC
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74 | #define ATA_CB_ER_BBK 0x80 // ATA bad block
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75 | #define ATA_CB_ER_UNC 0x40 // ATA uncorrected error
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76 | #define ATA_CB_ER_MC 0x20 // ATA media change
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77 | #define ATA_CB_ER_IDNF 0x10 // ATA id not found
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78 | #define ATA_CB_ER_MCR 0x08 // ATA media change request
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79 | #define ATA_CB_ER_ABRT 0x04 // ATA command aborted
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80 | #define ATA_CB_ER_NTK0 0x02 // ATA track 0 not found
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81 | #define ATA_CB_ER_NDAM 0x01 // ATA address mark not found
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82 |
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83 | #define ATA_CB_ER_P_SNSKEY 0xf0 // ATAPI sense key (mask)
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84 | #define ATA_CB_ER_P_MCR 0x08 // ATAPI Media Change Request
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85 | #define ATA_CB_ER_P_ABRT 0x04 // ATAPI command abort
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86 | #define ATA_CB_ER_P_EOM 0x02 // ATAPI End of Media
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87 | #define ATA_CB_ER_P_ILI 0x01 // ATAPI Illegal Length Indication
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88 |
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89 | // ATAPI Interrupt Reason bits in the Sector Count reg (CB_SC)
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90 | #define ATA_CB_SC_P_TAG 0xf8 // ATAPI tag (mask)
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91 | #define ATA_CB_SC_P_REL 0x04 // ATAPI release
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92 | #define ATA_CB_SC_P_IO 0x02 // ATAPI I/O
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93 | #define ATA_CB_SC_P_CD 0x01 // ATAPI C/D
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94 |
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95 | // bits 7-4 of the device/head (CB_DH) reg
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96 | #define ATA_CB_DH_DEV0 0xa0 // select device 0
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97 | #define ATA_CB_DH_DEV1 0xb0 // select device 1
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98 |
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99 | // status reg (CB_STAT and CB_ASTAT) bits
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100 | #define ATA_CB_STAT_BSY 0x80 // busy
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101 | #define ATA_CB_STAT_RDY 0x40 // ready
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102 | #define ATA_CB_STAT_DF 0x20 // device fault
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103 | #define ATA_CB_STAT_WFT 0x20 // write fault (old name)
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104 | #define ATA_CB_STAT_SKC 0x10 // seek complete
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105 | #define ATA_CB_STAT_SERV 0x10 // service
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106 | #define ATA_CB_STAT_DRQ 0x08 // data request
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107 | #define ATA_CB_STAT_CORR 0x04 // corrected
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108 | #define ATA_CB_STAT_IDX 0x02 // index
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109 | #define ATA_CB_STAT_ERR 0x01 // error (ATA)
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110 | #define ATA_CB_STAT_CHK 0x01 // check (ATAPI)
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111 |
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112 | // device control reg (CB_DC) bits
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113 | #define ATA_CB_DC_HD15 0x08 // bit should always be set to one
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114 | #define ATA_CB_DC_SRST 0x04 // soft reset
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115 | #define ATA_CB_DC_NIEN 0x02 // disable interrupts
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116 |
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117 | // Most mandatory and optional ATA commands (from ATA-3),
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118 | #define ATA_CMD_CFA_ERASE_SECTORS 0xC0
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119 | #define ATA_CMD_CFA_REQUEST_EXT_ERR_CODE 0x03
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120 | #define ATA_CMD_CFA_TRANSLATE_SECTOR 0x87
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121 | #define ATA_CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD
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122 | #define ATA_CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38
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123 | #define ATA_CMD_CHECK_POWER_MODE1 0xE5
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124 | #define ATA_CMD_CHECK_POWER_MODE2 0x98
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125 | #define ATA_CMD_DEVICE_RESET 0x08
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126 | #define ATA_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90
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127 | #define ATA_CMD_FLUSH_CACHE 0xE7
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128 | #define ATA_CMD_FORMAT_TRACK 0x50
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129 | #define ATA_CMD_IDENTIFY_DEVICE 0xEC
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130 | #define ATA_CMD_IDENTIFY_DEVICE_PACKET 0xA1
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131 | #define ATA_CMD_IDENTIFY_PACKET_DEVICE 0xA1
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132 | #define ATA_CMD_IDLE1 0xE3
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133 | #define ATA_CMD_IDLE2 0x97
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134 | #define ATA_CMD_IDLE_IMMEDIATE1 0xE1
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135 | #define ATA_CMD_IDLE_IMMEDIATE2 0x95
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136 | #define ATA_CMD_INITIALIZE_DRIVE_PARAMETERS 0x91
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137 | #define ATA_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91
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138 | #define ATA_CMD_NOP 0x00
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139 | #define ATA_CMD_PACKET 0xA0
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140 | #define ATA_CMD_READ_BUFFER 0xE4
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141 | #define ATA_CMD_READ_DMA 0xC8
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142 | #define ATA_CMD_READ_DMA_QUEUED 0xC7
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143 | #define ATA_CMD_READ_MULTIPLE 0xC4
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144 | #define ATA_CMD_READ_SECTORS 0x20
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145 | #define ATA_CMD_READ_SECTORS_EXT 0x24
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146 | #define ATA_CMD_READ_MULTIPLE_EXT 0x29
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147 | #define ATA_CMD_WRITE_MULTIPLE_EXT 0x39
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148 | #define ATA_CMD_READ_VERIFY_SECTORS 0x40
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149 | #define ATA_CMD_RECALIBRATE 0x10
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150 | #define ATA_CMD_SEEK 0x70
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151 | #define ATA_CMD_SET_FEATURES 0xEF
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152 | #define ATA_CMD_SET_MULTIPLE_MODE 0xC6
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153 | #define ATA_CMD_SLEEP1 0xE6
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154 | #define ATA_CMD_SLEEP2 0x99
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155 | #define ATA_CMD_STANDBY1 0xE2
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156 | #define ATA_CMD_STANDBY2 0x96
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157 | #define ATA_CMD_STANDBY_IMMEDIATE1 0xE0
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158 | #define ATA_CMD_STANDBY_IMMEDIATE2 0x94
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159 | #define ATA_CMD_WRITE_BUFFER 0xE8
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160 | #define ATA_CMD_WRITE_DMA 0xCA
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161 | #define ATA_CMD_WRITE_DMA_QUEUED 0xCC
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162 | #define ATA_CMD_WRITE_MULTIPLE 0xC5
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163 | #define ATA_CMD_WRITE_SECTORS 0x30
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164 | #define ATA_CMD_WRITE_SECTORS_EXT 0x34
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165 | #define ATA_CMD_WRITE_VERIFY 0x3C
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166 |
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167 | // for access to the int13ext structure
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168 | typedef struct {
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169 | uint8_t size;
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170 | uint8_t reserved;
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171 | uint16_t count;
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172 | uint16_t offset;
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173 | uint16_t segment;
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174 | uint32_t lba1;
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175 | uint32_t lba2;
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176 | } int13ext_t;
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177 |
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178 | #define Int13Ext ((int13ext_t *) 0)
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179 |
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180 | // Disk Physical Table definition
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181 | typedef struct {
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182 | uint16_t size;
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183 | uint16_t infos;
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184 | uint32_t cylinders;
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185 | uint32_t heads;
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186 | uint32_t spt;
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187 | uint32_t sector_count1;
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188 | uint32_t sector_count2;
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189 | uint16_t blksize;
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190 | uint16_t dpte_offset;
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191 | uint16_t dpte_segment;
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192 | uint16_t key;
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193 | uint8_t dpi_length;
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194 | uint8_t reserved1;
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195 | uint16_t reserved2;
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196 | uint8_t host_bus[4];
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197 | uint8_t iface_type[8];
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198 | uint8_t iface_path[8];
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199 | uint8_t device_path[8];
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200 | uint8_t reserved3;
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201 | uint8_t checksum;
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202 | } dpt_t;
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203 |
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204 | #define Int13DPT ((dpt_t *) 0)
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205 |
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206 |
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207 | extern void ata_reset(uint16_t device);
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208 | extern uint16_t atapi_is_cdrom(uint8_t device);
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209 | extern uint16_t ata_cmd_packet(uint16_t device, uint8_t cmdlen,
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210 | char __far *cmdbuf, uint16_t header,
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211 | uint32_t length, uint8_t inout,
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212 | char __far *buffer);
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