Context Navigation

← Previous Revision
Next Revision →
Blame
Revision Log

svga3d_surfacedefs.h

Last change on this file was 96407, checked in by vboxsync, 22 months ago
scm copyright and license note update
Property svn:eol-style set to `native`
File size: 48.3 KB

Line
1	/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2	/**************************************************************************
3	*
4	* Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the
8	* "Software"), to deal in the Software without restriction, including
9	* without limitation the rights to use, copy, modify, merge, publish,
10	* distribute, sub license, and/or sell copies of the Software, and to
11	* permit persons to whom the Software is furnished to do so, subject to
12	* the following conditions:
13	*
14	* The above copyright notice and this permission notice (including the
15	* next paragraph) shall be included in all copies or substantial portions
16	* of the Software.
17	*
18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
25	*
26	**************************************************************************/
27
28	/*
29	* svga3d_surfacedefs.h --
30	*
31	* Surface definitions and inlineable utilities for SVGA3d.
32	*/
33
34	#ifndef _SVGA3D_SURFACEDEFS_H_
35	#define _SVGA3D_SURFACEDEFS_H_
36
37	#define INCLUDE_ALLOW_USERLEVEL
38	#define INCLUDE_ALLOW_MODULE
39	#include "includeCheck.h"
40
41	#ifndef VBOX
42	#include <linux/kernel.h>
43	#include <drm/vmwgfx_drm.h>
44	#else
45	#include "svga_types.h"
46	typedef uint8_t u8;
47	typedef uint32_t u32;
48	struct drm_vmw_size
49	{
50	uint32_t width;
51	uint32_t height;
52	uint32_t depth;
53	uint32_t pad64;
54	};
55	#define U32_MAX UINT32_MAX
56	#define ARRAY_SIZE RT_ELEMENTS
57	#define __KERNEL_DIV_ROUND_UP(aDividend, aDivisor) (((aDividend) + (aDivisor) - 1) / (aDivisor))
58	#define max_t(aType, aValue1, aValue2) ( (aType)(aValue1) >= (aType)(aValue2) ? (aType)(aValue1) : (aType)(aValue2) )
59	#define min_t(aType, aValue1, aValue2) ( (aType)(aValue1) <= (aType)(aValue2) ? (aType)(aValue1) : (aType)(aValue2) )
60	#endif
61
62	#include "svga3d_reg.h"
63
64	#define surf_size_struct struct drm_vmw_size
65
66	/*
67	* enum svga3d_block_desc - describes generic properties about formats.
68	*/
69	enum svga3d_block_desc {
70	/* Nothing special can be said about this format. */
71	SVGA3DBLOCKDESC_NONE = 0,
72
73	/* Format contains Blue/U data */
74	SVGA3DBLOCKDESC_BLUE = 1 << 0,
75	SVGA3DBLOCKDESC_W = 1 << 0,
76	SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
77
78	/* Format contains Green/V data */
79	SVGA3DBLOCKDESC_GREEN = 1 << 1,
80	SVGA3DBLOCKDESC_V = 1 << 1,
81
82	/* Format contains Red/W/Luminance data */
83	SVGA3DBLOCKDESC_RED = 1 << 2,
84	SVGA3DBLOCKDESC_U = 1 << 2,
85	SVGA3DBLOCKDESC_LUMINANCE = 1 << 2,
86
87	/* Format contains Alpha/Q data */
88	SVGA3DBLOCKDESC_ALPHA = 1 << 3,
89	SVGA3DBLOCKDESC_Q = 1 << 3,
90
91	/* Format is a buffer */
92	SVGA3DBLOCKDESC_BUFFER = 1 << 4,
93
94	/* Format is compressed */
95	SVGA3DBLOCKDESC_COMPRESSED = 1 << 5,
96
97	/* Format uses IEEE floating point */
98	SVGA3DBLOCKDESC_FP = 1 << 6,
99
100	/* Three separate blocks store data. */
101	SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7,
102
103	/* 2 planes of Y, UV, e.g., NV12. */
104	SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8,
105
106	/* 3 planes of separate Y, U, V, e.g., YV12. */
107	SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9,
108
109	/* Block with a stencil channel */
110	SVGA3DBLOCKDESC_STENCIL = 1 << 11,
111
112	/* Typeless format */
113	SVGA3DBLOCKDESC_TYPELESS = 1 << 12,
114
115	/* Channels are signed integers */
116	SVGA3DBLOCKDESC_SINT = 1 << 13,
117
118	/* Channels are unsigned integers */
119	SVGA3DBLOCKDESC_UINT = 1 << 14,
120
121	/* Channels are normalized (when sampling) */
122	SVGA3DBLOCKDESC_NORM = 1 << 15,
123
124	/* Channels are in SRGB */
125	SVGA3DBLOCKDESC_SRGB = 1 << 16,
126
127	/* Shared exponent */
128	SVGA3DBLOCKDESC_EXP = 1 << 17,
129
130	/* Format contains color data. */
131	SVGA3DBLOCKDESC_COLOR = 1 << 18,
132	/* Format contains depth data. */
133	SVGA3DBLOCKDESC_DEPTH = 1 << 19,
134	/* Format contains bump data. */
135	SVGA3DBLOCKDESC_BUMP = 1 << 20,
136
137	/* Format contains YUV video data. */
138	SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21,
139
140	/* For mixed unsigned/signed formats. */
141	SVGA3DBLOCKDESC_MIXED = 1 << 22,
142
143	/* For distingushing CxV8U8. */
144	SVGA3DBLOCKDESC_CX = 1 << 23,
145
146	/* Different compressed format groups. */
147	SVGA3DBLOCKDESC_BC1 = 1 << 24,
148	SVGA3DBLOCKDESC_BC2 = 1 << 25,
149	SVGA3DBLOCKDESC_BC3 = 1 << 26,
150	SVGA3DBLOCKDESC_BC4 = 1 << 27,
151	SVGA3DBLOCKDESC_BC5 = 1 << 28,
152	SVGA3DBLOCKDESC_BC6H = 1 << 29,
153	SVGA3DBLOCKDESC_BC7 = 1 << 30,
154
155	SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA \|
156	SVGA3DBLOCKDESC_UINT \|
157	SVGA3DBLOCKDESC_COLOR,
158	SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT \|
159	SVGA3DBLOCKDESC_NORM,
160	SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED \|
161	SVGA3DBLOCKDESC_UINT \|
162	SVGA3DBLOCKDESC_COLOR,
163	SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT \|
164	SVGA3DBLOCKDESC_NORM,
165	SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED \|
166	SVGA3DBLOCKDESC_SINT \|
167	SVGA3DBLOCKDESC_COLOR,
168	SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT \|
169	SVGA3DBLOCKDESC_NORM,
170	SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN \|
171	SVGA3DBLOCKDESC_UINT \|
172	SVGA3DBLOCKDESC_COLOR,
173	SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED \|
174	SVGA3DBLOCKDESC_GREEN \|
175	SVGA3DBLOCKDESC_UINT \|
176	SVGA3DBLOCKDESC_COLOR,
177	SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT \|
178	SVGA3DBLOCKDESC_NORM,
179	SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED \|
180	SVGA3DBLOCKDESC_GREEN \|
181	SVGA3DBLOCKDESC_SINT \|
182	SVGA3DBLOCKDESC_COLOR,
183	SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT \|
184	SVGA3DBLOCKDESC_NORM,
185	SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED \|
186	SVGA3DBLOCKDESC_GREEN \|
187	SVGA3DBLOCKDESC_BLUE \|
188	SVGA3DBLOCKDESC_UINT \|
189	SVGA3DBLOCKDESC_COLOR,
190	SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED \|
191	SVGA3DBLOCKDESC_GREEN \|
192	SVGA3DBLOCKDESC_BLUE \|
193	SVGA3DBLOCKDESC_SINT \|
194	SVGA3DBLOCKDESC_COLOR,
195	SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT \|
196	SVGA3DBLOCKDESC_NORM,
197	SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM \|
198	SVGA3DBLOCKDESC_SRGB,
199	SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED \|
200	SVGA3DBLOCKDESC_GREEN \|
201	SVGA3DBLOCKDESC_BLUE \|
202	SVGA3DBLOCKDESC_ALPHA \|
203	SVGA3DBLOCKDESC_UINT \|
204	SVGA3DBLOCKDESC_COLOR,
205	SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT \|
206	SVGA3DBLOCKDESC_NORM,
207	SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM \|
208	SVGA3DBLOCKDESC_SRGB,
209	SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED \|
210	SVGA3DBLOCKDESC_GREEN \|
211	SVGA3DBLOCKDESC_BLUE \|
212	SVGA3DBLOCKDESC_ALPHA \|
213	SVGA3DBLOCKDESC_SINT \|
214	SVGA3DBLOCKDESC_COLOR,
215	SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT \|
216	SVGA3DBLOCKDESC_NORM,
217	SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED \|
218	SVGA3DBLOCKDESC_GREEN \|
219	SVGA3DBLOCKDESC_BLUE \|
220	SVGA3DBLOCKDESC_ALPHA \|
221	SVGA3DBLOCKDESC_FP \|
222	SVGA3DBLOCKDESC_COLOR,
223	SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U \|
224	SVGA3DBLOCKDESC_V \|
225	SVGA3DBLOCKDESC_BUMP,
226	SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV \|
227	SVGA3DBLOCKDESC_BUMP_L \|
228	SVGA3DBLOCKDESC_MIXED \|
229	SVGA3DBLOCKDESC_BUMP,
230	SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV \|
231	SVGA3DBLOCKDESC_W \|
232	SVGA3DBLOCKDESC_BUMP,
233	SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW \|
234	SVGA3DBLOCKDESC_ALPHA \|
235	SVGA3DBLOCKDESC_MIXED \|
236	SVGA3DBLOCKDESC_BUMP,
237	SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U \|
238	SVGA3DBLOCKDESC_V \|
239	SVGA3DBLOCKDESC_W \|
240	SVGA3DBLOCKDESC_Q \|
241	SVGA3DBLOCKDESC_BUMP,
242	SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE \|
243	SVGA3DBLOCKDESC_UINT \|
244	SVGA3DBLOCKDESC_NORM \|
245	SVGA3DBLOCKDESC_COLOR,
246	SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE \|
247	SVGA3DBLOCKDESC_ALPHA \|
248	SVGA3DBLOCKDESC_UINT \|
249	SVGA3DBLOCKDESC_NORM \|
250	SVGA3DBLOCKDESC_COLOR,
251	SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED \|
252	SVGA3DBLOCKDESC_FP \|
253	SVGA3DBLOCKDESC_COLOR,
254	SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP \|
255	SVGA3DBLOCKDESC_GREEN \|
256	SVGA3DBLOCKDESC_COLOR,
257	SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP \|
258	SVGA3DBLOCKDESC_BLUE \|
259	SVGA3DBLOCKDESC_COLOR,
260	SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO \|
261	SVGA3DBLOCKDESC_COLOR,
262	SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA \|
263	SVGA3DBLOCKDESC_YUV_VIDEO \|
264	SVGA3DBLOCKDESC_COLOR,
265	SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED \|
266	SVGA3DBLOCKDESC_GREEN \|
267	SVGA3DBLOCKDESC_BLUE \|
268	SVGA3DBLOCKDESC_EXP \|
269	SVGA3DBLOCKDESC_COLOR,
270
271	SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED \|
272	SVGA3DBLOCKDESC_TYPELESS,
273	SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED \|
274	SVGA3DBLOCKDESC_UINT \|
275	SVGA3DBLOCKDESC_NORM \|
276	SVGA3DBLOCKDESC_COLOR,
277	SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED \|
278	SVGA3DBLOCKDESC_SINT \|
279	SVGA3DBLOCKDESC_NORM \|
280	SVGA3DBLOCKDESC_COLOR,
281	SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM \|
282	SVGA3DBLOCKDESC_SRGB,
283	SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 \|
284	SVGA3DBLOCKDESC_COMP_TYPELESS,
285	SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 \|
286	SVGA3DBLOCKDESC_COMP_UNORM,
287	SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM \|
288	SVGA3DBLOCKDESC_SRGB,
289	SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 \|
290	SVGA3DBLOCKDESC_COMP_TYPELESS,
291	SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 \|
292	SVGA3DBLOCKDESC_COMP_UNORM,
293	SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM \|
294	SVGA3DBLOCKDESC_SRGB,
295	SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 \|
296	SVGA3DBLOCKDESC_COMP_TYPELESS,
297	SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 \|
298	SVGA3DBLOCKDESC_COMP_UNORM,
299	SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM \|
300	SVGA3DBLOCKDESC_SRGB,
301	SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 \|
302	SVGA3DBLOCKDESC_COMP_TYPELESS,
303	SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 \|
304	SVGA3DBLOCKDESC_COMP_UNORM,
305	SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 \|
306	SVGA3DBLOCKDESC_COMP_SNORM,
307	SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 \|
308	SVGA3DBLOCKDESC_COMP_TYPELESS,
309	SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 \|
310	SVGA3DBLOCKDESC_COMP_UNORM,
311	SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 \|
312	SVGA3DBLOCKDESC_COMP_SNORM,
313	SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H \|
314	SVGA3DBLOCKDESC_COMP_TYPELESS,
315	SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H \|
316	SVGA3DBLOCKDESC_COMPRESSED,
317	SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H \|
318	SVGA3DBLOCKDESC_COMPRESSED,
319	SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 \|
320	SVGA3DBLOCKDESC_COMP_TYPELESS,
321	SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 \|
322	SVGA3DBLOCKDESC_COMP_UNORM,
323	SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM \|
324	SVGA3DBLOCKDESC_SRGB,
325
326	SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO \|
327	SVGA3DBLOCKDESC_PLANAR_YUV \|
328	SVGA3DBLOCKDESC_2PLANAR_YUV \|
329	SVGA3DBLOCKDESC_COLOR,
330	SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO \|
331	SVGA3DBLOCKDESC_PLANAR_YUV \|
332	SVGA3DBLOCKDESC_3PLANAR_YUV \|
333	SVGA3DBLOCKDESC_COLOR,
334
335	SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH \|
336	SVGA3DBLOCKDESC_UINT,
337	SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT \|
338	SVGA3DBLOCKDESC_NORM,
339	SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH \|
340	SVGA3DBLOCKDESC_STENCIL,
341	SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH \|
342	SVGA3DBLOCKDESC_STENCIL \|
343	SVGA3DBLOCKDESC_UINT,
344	SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT \|
345	SVGA3DBLOCKDESC_NORM,
346	SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH \|
347	SVGA3DBLOCKDESC_FP,
348
349	SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV \|
350	SVGA3DBLOCKDESC_UINT,
351	SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV \|
352	SVGA3DBLOCKDESC_SINT \|
353	SVGA3DBLOCKDESC_NORM,
354	SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM \|
355	SVGA3DBLOCKDESC_CX,
356	SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ \|
357	SVGA3DBLOCKDESC_SINT \|
358	SVGA3DBLOCKDESC_NORM,
359	};
360
361	struct svga3d_channel_def {
362	union {
363	u8 blue;
364	u8 w_bump;
365	u8 l_bump;
366	u8 uv_video;
367	u8 u_video;
368	};
369	union {
370	u8 green;
371	u8 stencil;
372	u8 v_bump;
373	u8 v_video;
374	};
375	union {
376	u8 red;
377	u8 u_bump;
378	u8 luminance;
379	u8 y_video;
380	u8 depth;
381	u8 data;
382	};
383	union {
384	u8 alpha;
385	u8 q_bump;
386	u8 exp;
387	};
388	};
389
390	/*
391	* struct svga3d_surface_desc - describes the actual pixel data.
392	*
393	* @format: Format
394	* @block_desc: Block description
395	* @block_size: Dimensions in pixels of a block
396	* @bytes_per_block: Size of block in bytes
397	* @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch
398	* @bit_depth: Channel bit depths
399	* @bit_offset: Channel bit masks (in bits offset from the start of the pointer)
400	*/
401	struct svga3d_surface_desc {
402	SVGA3dSurfaceFormat format;
403	enum svga3d_block_desc block_desc;
404
405	surf_size_struct block_size;
406	u32 bytes_per_block;
407	u32 pitch_bytes_per_block;
408
409	struct svga3d_channel_def bit_depth;
410	struct svga3d_channel_def bit_offset;
411	};
412
413	static const struct svga3d_surface_desc svga3d_surface_descs[] = {
414	{SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE,
415	{1, 1, 1}, 0, 0,
416	{{0}, {0}, {0}, {0}},
417	{{0}, {0}, {0}, {0}}},
418
419	{SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM,
420	{1, 1, 1}, 4, 4,
421	{{8}, {8}, {8}, {0}},
422	{{0}, {8}, {16}, {24}}},
423
424	{SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM,
425	{1, 1, 1}, 4, 4,
426	{{8}, {8}, {8}, {8}},
427	{{0}, {8}, {16}, {24}}},
428
429	{SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM,
430	{1, 1, 1}, 2, 2,
431	{{5}, {6}, {5}, {0}},
432	{{0}, {5}, {11}, {0}}},
433
434	{SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM,
435	{1, 1, 1}, 2, 2,
436	{{5}, {5}, {5}, {0}},
437	{{0}, {5}, {10}, {0}}},
438
439	{SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM,
440	{1, 1, 1}, 2, 2,
441	{{5}, {5}, {5}, {1}},
442	{{0}, {5}, {10}, {15}}},
443
444	{SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM,
445	{1, 1, 1}, 2, 2,
446	{{4}, {4}, {4}, {4}},
447	{{0}, {4}, {8}, {12}}},
448
449	{SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM,
450	{1, 1, 1}, 4, 4,
451	{{0}, {0}, {32}, {0}},
452	{{0}, {0}, {0}, {0}}},
453
454	{SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM,
455	{1, 1, 1}, 2, 2,
456	{{0}, {0}, {16}, {0}},
457	{{0}, {0}, {0}, {0}}},
458
459	{SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM,
460	{1, 1, 1}, 4, 4,
461	{{0}, {8}, {24}, {0}},
462	{{0}, {0}, {8}, {0}}},
463
464	{SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM,
465	{1, 1, 1}, 2, 2,
466	{{0}, {1}, {15}, {0}},
467	{{0}, {0}, {1}, {0}}},
468
469	{SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM,
470	{1, 1, 1}, 1, 1,
471	{{0}, {0}, {8}, {0}},
472	{{0}, {0}, {0}, {0}}},
473
474	{SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM,
475	{1, 1, 1}, 1, 1,
476	{{0}, {0}, {4}, {4}},
477	{{0}, {0}, {0}, {4}}},
478
479	{SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM,
480	{1, 1, 1}, 2, 2,
481	{{0}, {0}, {16}, {0}},
482	{{0}, {0}, {0}, {0}}},
483
484	{SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM,
485	{1, 1, 1}, 2, 2,
486	{{0}, {0}, {8}, {8}},
487	{{0}, {0}, {0}, {8}}},
488
489	{SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
490	{4, 4, 1}, 8, 8,
491	{{0}, {0}, {64}, {0}},
492	{{0}, {0}, {0}, {0}}},
493
494	{SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
495	{4, 4, 1}, 16, 16,
496	{{0}, {0}, {128}, {0}},
497	{{0}, {0}, {0}, {0}}},
498
499	{SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
500	{4, 4, 1}, 16, 16,
501	{{0}, {0}, {128}, {0}},
502	{{0}, {0}, {0}, {0}}},
503
504	{SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
505	{4, 4, 1}, 16, 16,
506	{{0}, {0}, {128}, {0}},
507	{{0}, {0}, {0}, {0}}},
508
509	{SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
510	{4, 4, 1}, 16, 16,
511	{{0}, {0}, {128}, {0}},
512	{{0}, {0}, {0}, {0}}},
513
514	{SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM,
515	{1, 1, 1}, 2, 2,
516	{{0}, {8}, {8}, {0}},
517	{{0}, {8}, {0}, {0}}},
518
519	{SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL,
520	{1, 1, 1}, 2, 2,
521	{{6}, {5}, {5}, {0}},
522	{{10}, {5}, {0}, {0}}},
523
524	{SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL,
525	{1, 1, 1}, 4, 4,
526	{{8}, {8}, {8}, {0}},
527	{{16}, {8}, {0}, {0}}},
528
529	{SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE,
530	{1, 1, 1}, 3, 3,
531	{{8}, {8}, {8}, {0}},
532	{{16}, {8}, {0}, {0}}},
533
534	{SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP,
535	{1, 1, 1}, 8, 8,
536	{{16}, {16}, {16}, {16}},
537	{{32}, {16}, {0}, {48}}},
538
539	{SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP,
540	{1, 1, 1}, 16, 16,
541	{{32}, {32}, {32}, {32}},
542	{{64}, {32}, {0}, {96}}},
543
544	{SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM,
545	{1, 1, 1}, 4, 4,
546	{{10}, {10}, {10}, {2}},
547	{{0}, {10}, {20}, {30}}},
548
549	{SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM,
550	{1, 1, 1}, 2, 2,
551	{{0}, {8}, {8}, {0}},
552	{{0}, {8}, {0}, {0}}},
553
554	{SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM,
555	{1, 1, 1}, 4, 4,
556	{{8}, {8}, {8}, {8}},
557	{{16}, {8}, {0}, {24}}},
558
559	{SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM,
560	{1, 1, 1}, 2, 2,
561	{{0}, {8}, {8}, {0}},
562	{{0}, {8}, {0}, {0}}},
563
564	{SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL,
565	{1, 1, 1}, 4, 4,
566	{{8}, {8}, {8}, {0}},
567	{{16}, {8}, {0}, {0}}},
568
569	{SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA,
570	{1, 1, 1}, 4, 4,
571	{{10}, {10}, {10}, {2}},
572	{{20}, {10}, {0}, {30}}},
573
574	{SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM,
575	{1, 1, 1}, 1, 1,
576	{{0}, {0}, {0}, {8}},
577	{{0}, {0}, {0}, {0}}},
578
579	{SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP,
580	{1, 1, 1}, 2, 2,
581	{{0}, {0}, {16}, {0}},
582	{{0}, {0}, {0}, {0}}},
583
584	{SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP,
585	{1, 1, 1}, 4, 4,
586	{{0}, {0}, {32}, {0}},
587	{{0}, {0}, {0}, {0}}},
588
589	{SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP,
590	{1, 1, 1}, 4, 4,
591	{{0}, {16}, {16}, {0}},
592	{{0}, {16}, {0}, {0}}},
593
594	{SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP,
595	{1, 1, 1}, 8, 8,
596	{{0}, {32}, {32}, {0}},
597	{{0}, {32}, {0}, {0}}},
598
599	{SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER,
600	{1, 1, 1}, 1, 1,
601	{{0}, {0}, {8}, {0}},
602	{{0}, {0}, {0}, {0}}},
603
604	{SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM,
605	{1, 1, 1}, 4, 4,
606	{{0}, {0}, {24}, {0}},
607	{{0}, {0}, {8}, {0}}},
608
609	{SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM,
610	{1, 1, 1}, 4, 4,
611	{{0}, {16}, {16}, {0}},
612	{{0}, {16}, {0}, {0}}},
613
614	{SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM,
615	{1, 1, 1}, 4, 4,
616	{{0}, {16}, {16}, {0}},
617	{{0}, {16}, {0}, {0}}},
618
619	{SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM,
620	{1, 1, 1}, 8, 8,
621	{{16}, {16}, {16}, {16}},
622	{{32}, {16}, {0}, {48}}},
623
624	{SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV,
625	{2, 1, 1}, 4, 4,
626	{{8}, {0}, {8}, {0}},
627	{{0}, {0}, {8}, {0}}},
628
629	{SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV,
630	{2, 1, 1}, 4, 4,
631	{{8}, {0}, {8}, {0}},
632	{{8}, {0}, {0}, {0}}},
633
634	{SVGA3D_NV12, SVGA3DBLOCKDESC_NV12,
635	{2, 2, 1}, 6, 2,
636	{{0}, {0}, {48}, {0}},
637	{{0}, {0}, {0}, {0}}},
638
639	{SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE,
640	{1, 1, 1}, 4, 4,
641	{{8}, {8}, {8}, {8}},
642	{{0}, {8}, {16}, {24}}},
643
644	{SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
645	{1, 1, 1}, 16, 16,
646	{{32}, {32}, {32}, {32}},
647	{{64}, {32}, {0}, {96}}},
648
649	{SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
650	{1, 1, 1}, 16, 16,
651	{{32}, {32}, {32}, {32}},
652	{{64}, {32}, {0}, {96}}},
653
654	{SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
655	{1, 1, 1}, 16, 16,
656	{{32}, {32}, {32}, {32}},
657	{{64}, {32}, {0}, {96}}},
658
659	{SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
660	{1, 1, 1}, 12, 12,
661	{{32}, {32}, {32}, {0}},
662	{{64}, {32}, {0}, {0}}},
663
664	{SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
665	{1, 1, 1}, 12, 12,
666	{{32}, {32}, {32}, {0}},
667	{{64}, {32}, {0}, {0}}},
668
669	{SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT,
670	{1, 1, 1}, 12, 12,
671	{{32}, {32}, {32}, {0}},
672	{{64}, {32}, {0}, {0}}},
673
674	{SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT,
675	{1, 1, 1}, 12, 12,
676	{{32}, {32}, {32}, {0}},
677	{{64}, {32}, {0}, {0}}},
678
679	{SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
680	{1, 1, 1}, 8, 8,
681	{{16}, {16}, {16}, {16}},
682	{{32}, {16}, {0}, {48}}},
683
684	{SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
685	{1, 1, 1}, 8, 8,
686	{{16}, {16}, {16}, {16}},
687	{{32}, {16}, {0}, {48}}},
688
689	{SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
690	{1, 1, 1}, 8, 8,
691	{{16}, {16}, {16}, {16}},
692	{{32}, {16}, {0}, {48}}},
693
694	{SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
695	{1, 1, 1}, 8, 8,
696	{{16}, {16}, {16}, {16}},
697	{{32}, {16}, {0}, {48}}},
698
699	{SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
700	{1, 1, 1}, 8, 8,
701	{{0}, {32}, {32}, {0}},
702	{{0}, {32}, {0}, {0}}},
703
704	{SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT,
705	{1, 1, 1}, 8, 8,
706	{{0}, {32}, {32}, {0}},
707	{{0}, {32}, {0}, {0}}},
708
709	{SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT,
710	{1, 1, 1}, 8, 8,
711	{{0}, {32}, {32}, {0}},
712	{{0}, {32}, {0}, {0}}},
713
714	{SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
715	{1, 1, 1}, 8, 8,
716	{{0}, {8}, {32}, {0}},
717	{{0}, {32}, {0}, {0}}},
718
719	{SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS,
720	{1, 1, 1}, 8, 8,
721	{{0}, {8}, {32}, {0}},
722	{{0}, {32}, {0}, {0}}},
723
724	{SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP,
725	{1, 1, 1}, 8, 8,
726	{{0}, {0}, {32}, {0}},
727	{{0}, {0}, {0}, {0}}},
728
729	{SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT,
730	{1, 1, 1}, 8, 8,
731	{{0}, {8}, {0}, {0}},
732	{{0}, {32}, {0}, {0}}},
733
734	{SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
735	{1, 1, 1}, 4, 4,
736	{{10}, {10}, {10}, {2}},
737	{{20}, {10}, {0}, {30}}},
738
739	{SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
740	{1, 1, 1}, 4, 4,
741	{{10}, {10}, {10}, {2}},
742	{{20}, {10}, {0}, {30}}},
743
744	{SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
745	{1, 1, 1}, 4, 4,
746	{{10}, {11}, {11}, {0}},
747	{{22}, {11}, {0}, {0}}},
748
749	{SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
750	{1, 1, 1}, 4, 4,
751	{{8}, {8}, {8}, {8}},
752	{{16}, {8}, {0}, {24}}},
753
754	{SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
755	{1, 1, 1}, 4, 4,
756	{{8}, {8}, {8}, {8}},
757	{{16}, {8}, {0}, {24}}},
758
759	{SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
760	{1, 1, 1}, 4, 4,
761	{{8}, {8}, {8}, {8}},
762	{{16}, {8}, {0}, {24}}},
763
764	{SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
765	{1, 1, 1}, 4, 4,
766	{{8}, {8}, {8}, {8}},
767	{{16}, {8}, {0}, {24}}},
768
769	{SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
770	{1, 1, 1}, 4, 4,
771	{{8}, {8}, {8}, {8}},
772	{{16}, {8}, {0}, {24}}},
773
774	{SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
775	{1, 1, 1}, 4, 4,
776	{{0}, {16}, {16}, {0}},
777	{{0}, {16}, {0}, {0}}},
778
779	{SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT,
780	{1, 1, 1}, 4, 4,
781	{{0}, {16}, {16}, {0}},
782	{{0}, {16}, {0}, {0}}},
783
784	{SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT,
785	{1, 1, 1}, 4, 4,
786	{{0}, {16}, {16}, {0}},
787	{{0}, {16}, {0}, {0}}},
788
789	{SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
790	{1, 1, 1}, 4, 4,
791	{{0}, {0}, {32}, {0}},
792	{{0}, {0}, {0}, {0}}},
793
794	{SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP,
795	{1, 1, 1}, 4, 4,
796	{{0}, {0}, {32}, {0}},
797	{{0}, {0}, {0}, {0}}},
798
799	{SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT,
800	{1, 1, 1}, 4, 4,
801	{{0}, {0}, {32}, {0}},
802	{{0}, {0}, {0}, {0}}},
803
804	{SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT,
805	{1, 1, 1}, 4, 4,
806	{{0}, {0}, {32}, {0}},
807	{{0}, {0}, {0}, {0}}},
808
809	{SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
810	{1, 1, 1}, 4, 4,
811	{{0}, {8}, {24}, {0}},
812	{{0}, {24}, {0}, {0}}},
813
814	{SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM,
815	{1, 1, 1}, 4, 4,
816	{{0}, {8}, {24}, {0}},
817	{{0}, {24}, {0}, {0}}},
818
819	{SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM,
820	{1, 1, 1}, 4, 4,
821	{{0}, {0}, {24}, {0}},
822	{{0}, {0}, {0}, {0}}},
823
824	{SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT,
825	{1, 1, 1}, 4, 4,
826	{{0}, {8}, {0}, {0}},
827	{{0}, {24}, {0}, {0}}},
828
829	{SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
830	{1, 1, 1}, 2, 2,
831	{{0}, {8}, {8}, {0}},
832	{{0}, {8}, {0}, {0}}},
833
834	{SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
835	{1, 1, 1}, 2, 2,
836	{{0}, {8}, {8}, {0}},
837	{{0}, {8}, {0}, {0}}},
838
839	{SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT,
840	{1, 1, 1}, 2, 2,
841	{{0}, {8}, {8}, {0}},
842	{{0}, {8}, {0}, {0}}},
843
844	{SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT,
845	{1, 1, 1}, 2, 2,
846	{{0}, {8}, {8}, {0}},
847	{{0}, {8}, {0}, {0}}},
848
849	{SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
850	{1, 1, 1}, 2, 2,
851	{{0}, {0}, {16}, {0}},
852	{{0}, {0}, {0}, {0}}},
853
854	{SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM,
855	{1, 1, 1}, 2, 2,
856	{{0}, {0}, {16}, {0}},
857	{{0}, {0}, {0}, {0}}},
858
859	{SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT,
860	{1, 1, 1}, 2, 2,
861	{{0}, {0}, {16}, {0}},
862	{{0}, {0}, {0}, {0}}},
863
864	{SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM,
865	{1, 1, 1}, 2, 2,
866	{{0}, {0}, {16}, {0}},
867	{{0}, {0}, {0}, {0}}},
868
869	{SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT,
870	{1, 1, 1}, 2, 2,
871	{{0}, {0}, {16}, {0}},
872	{{0}, {0}, {0}, {0}}},
873
874	{SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
875	{1, 1, 1}, 1, 1,
876	{{0}, {0}, {8}, {0}},
877	{{0}, {0}, {0}, {0}}},
878
879	{SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM,
880	{1, 1, 1}, 1, 1,
881	{{0}, {0}, {8}, {0}},
882	{{0}, {0}, {0}, {0}}},
883
884	{SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT,
885	{1, 1, 1}, 1, 1,
886	{{0}, {0}, {8}, {0}},
887	{{0}, {0}, {0}, {0}}},
888
889	{SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM,
890	{1, 1, 1}, 1, 1,
891	{{0}, {0}, {8}, {0}},
892	{{0}, {0}, {0}, {0}}},
893
894	{SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT,
895	{1, 1, 1}, 1, 1,
896	{{0}, {0}, {8}, {0}},
897	{{0}, {0}, {0}, {0}}},
898
899	{SVGA3D_P8, SVGA3DBLOCKDESC_NONE,
900	{1, 1, 1}, 1, 1,
901	{{0}, {0}, {8}, {0}},
902	{{0}, {0}, {0}, {0}}},
903
904	{SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP,
905	{1, 1, 1}, 4, 4,
906	{{9}, {9}, {9}, {5}},
907	{{18}, {9}, {0}, {27}}},
908
909	{SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE,
910	{2, 1, 1}, 4, 4,
911	{{0}, {8}, {8}, {0}},
912	{{0}, {0}, {8}, {0}}},
913
914	{SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE,
915	{2, 1, 1}, 4, 4,
916	{{0}, {8}, {8}, {0}},
917	{{0}, {8}, {0}, {0}}},
918
919	{SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS,
920	{4, 4, 1}, 8, 8,
921	{{0}, {0}, {64}, {0}},
922	{{0}, {0}, {0}, {0}}},
923
924	{SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB,
925	{4, 4, 1}, 8, 8,
926	{{0}, {0}, {64}, {0}},
927	{{0}, {0}, {0}, {0}}},
928
929	{SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS,
930	{4, 4, 1}, 16, 16,
931	{{0}, {0}, {128}, {0}},
932	{{0}, {0}, {0}, {0}}},
933
934	{SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB,
935	{4, 4, 1}, 16, 16,
936	{{0}, {0}, {128}, {0}},
937	{{0}, {0}, {0}, {0}}},
938
939	{SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS,
940	{4, 4, 1}, 16, 16,
941	{{0}, {0}, {128}, {0}},
942	{{0}, {0}, {0}, {0}}},
943
944	{SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB,
945	{4, 4, 1}, 16, 16,
946	{{0}, {0}, {128}, {0}},
947	{{0}, {0}, {0}, {0}}},
948
949	{SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS,
950	{4, 4, 1}, 8, 8,
951	{{0}, {0}, {64}, {0}},
952	{{0}, {0}, {0}, {0}}},
953
954	{SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
955	{4, 4, 1}, 8, 8,
956	{{0}, {0}, {64}, {0}},
957	{{0}, {0}, {0}, {0}}},
958
959	{SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM,
960	{4, 4, 1}, 8, 8,
961	{{0}, {0}, {64}, {0}},
962	{{0}, {0}, {0}, {0}}},
963
964	{SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS,
965	{4, 4, 1}, 16, 16,
966	{{0}, {0}, {128}, {0}},
967	{{0}, {0}, {0}, {0}}},
968
969	{SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
970	{4, 4, 1}, 16, 16,
971	{{0}, {0}, {128}, {0}},
972	{{0}, {0}, {0}, {0}}},
973
974	{SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM,
975	{4, 4, 1}, 16, 16,
976	{{0}, {0}, {128}, {0}},
977	{{0}, {0}, {0}, {0}}},
978
979	{SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
980	{1, 1, 1}, 4, 4,
981	{{10}, {10}, {10}, {2}},
982	{{20}, {10}, {0}, {30}}},
983
984	{SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
985	{1, 1, 1}, 4, 4,
986	{{8}, {8}, {8}, {8}},
987	{{0}, {8}, {16}, {24}}},
988
989	{SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
990	{1, 1, 1}, 4, 4,
991	{{8}, {8}, {8}, {8}},
992	{{0}, {8}, {16}, {24}}},
993
994	{SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
995	{1, 1, 1}, 4, 4,
996	{{8}, {8}, {8}, {0}},
997	{{0}, {8}, {16}, {24}}},
998
999	{SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB,
1000	{1, 1, 1}, 4, 4,
1001	{{8}, {8}, {8}, {0}},
1002	{{0}, {8}, {16}, {24}}},
1003
1004	{SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM,
1005	{1, 1, 1}, 2, 2,
1006	{{0}, {0}, {16}, {0}},
1007	{{0}, {0}, {0}, {0}}},
1008
1009	{SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM,
1010	{1, 1, 1}, 4, 4,
1011	{{0}, {0}, {24}, {0}},
1012	{{0}, {0}, {8}, {0}}},
1013
1014	{SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM,
1015	{1, 1, 1}, 4, 4,
1016	{{0}, {8}, {24}, {0}},
1017	{{0}, {0}, {8}, {0}}},
1018
1019	{SVGA3D_YV12, SVGA3DBLOCKDESC_YV12,
1020	{2, 2, 1}, 6, 2,
1021	{{0}, {0}, {48}, {0}},
1022	{{0}, {0}, {0}, {0}}},
1023
1024	{SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
1025	{1, 1, 1}, 16, 16,
1026	{{32}, {32}, {32}, {32}},
1027	{{64}, {32}, {0}, {96}}},
1028
1029	{SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
1030	{1, 1, 1}, 8, 8,
1031	{{16}, {16}, {16}, {16}},
1032	{{32}, {16}, {0}, {48}}},
1033
1034	{SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1035	{1, 1, 1}, 8, 8,
1036	{{16}, {16}, {16}, {16}},
1037	{{32}, {16}, {0}, {48}}},
1038
1039	{SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP,
1040	{1, 1, 1}, 8, 8,
1041	{{0}, {32}, {32}, {0}},
1042	{{0}, {32}, {0}, {0}}},
1043
1044	{SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1045	{1, 1, 1}, 4, 4,
1046	{{10}, {10}, {10}, {2}},
1047	{{20}, {10}, {0}, {30}}},
1048
1049	{SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
1050	{1, 1, 1}, 4, 4,
1051	{{8}, {8}, {8}, {8}},
1052	{{16}, {8}, {0}, {24}}},
1053
1054	{SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP,
1055	{1, 1, 1}, 4, 4,
1056	{{0}, {16}, {16}, {0}},
1057	{{0}, {16}, {0}, {0}}},
1058
1059	{SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
1060	{1, 1, 1}, 4, 4,
1061	{{0}, {16}, {16}, {0}},
1062	{{0}, {16}, {0}, {0}}},
1063
1064	{SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
1065	{1, 1, 1}, 4, 4,
1066	{{0}, {16}, {16}, {0}},
1067	{{0}, {16}, {0}, {0}}},
1068
1069	{SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP,
1070	{1, 1, 1}, 4, 4,
1071	{{0}, {0}, {32}, {0}},
1072	{{0}, {0}, {0}, {0}}},
1073
1074	{SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
1075	{1, 1, 1}, 2, 2,
1076	{{0}, {8}, {8}, {0}},
1077	{{0}, {8}, {0}, {0}}},
1078
1079	{SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP,
1080	{1, 1, 1}, 2, 2,
1081	{{0}, {0}, {16}, {0}},
1082	{{0}, {0}, {0}, {0}}},
1083
1084	{SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM,
1085	{1, 1, 1}, 2, 2,
1086	{{0}, {0}, {16}, {0}},
1087	{{0}, {0}, {0}, {0}}},
1088
1089	{SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM,
1090	{1, 1, 1}, 1, 1,
1091	{{0}, {0}, {0}, {8}},
1092	{{0}, {0}, {0}, {0}}},
1093
1094	{SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
1095	{4, 4, 1}, 8, 8,
1096	{{0}, {0}, {64}, {0}},
1097	{{0}, {0}, {0}, {0}}},
1098
1099	{SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
1100	{4, 4, 1}, 16, 16,
1101	{{0}, {0}, {128}, {0}},
1102	{{0}, {0}, {0}, {0}}},
1103
1104	{SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
1105	{4, 4, 1}, 16, 16,
1106	{{0}, {0}, {128}, {0}},
1107	{{0}, {0}, {0}, {0}}},
1108
1109	{SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
1110	{1, 1, 1}, 2, 2,
1111	{{5}, {6}, {5}, {0}},
1112	{{0}, {5}, {11}, {0}}},
1113
1114	{SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1115	{1, 1, 1}, 2, 2,
1116	{{5}, {5}, {5}, {1}},
1117	{{0}, {5}, {10}, {15}}},
1118
1119	{SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1120	{1, 1, 1}, 4, 4,
1121	{{8}, {8}, {8}, {8}},
1122	{{0}, {8}, {16}, {24}}},
1123
1124	{SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
1125	{1, 1, 1}, 4, 4,
1126	{{8}, {8}, {8}, {0}},
1127	{{0}, {8}, {16}, {24}}},
1128
1129	{SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
1130	{4, 4, 1}, 8, 8,
1131	{{0}, {0}, {64}, {0}},
1132	{{0}, {0}, {0}, {0}}},
1133
1134	{SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
1135	{4, 4, 1}, 16, 16,
1136	{{0}, {0}, {128}, {0}},
1137	{{0}, {0}, {0}, {0}}},
1138
1139	{SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1140	{1, 1, 1}, 2, 2,
1141	{{4}, {4}, {4}, {4}},
1142	{{0}, {4}, {8}, {12}}},
1143
1144	{SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
1145	{4, 4, 1}, 16, 16,
1146	{{0}, {0}, {128}, {0}},
1147	{{0}, {0}, {0}, {0}}},
1148
1149	{SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16,
1150	{4, 4, 1}, 16, 16,
1151	{{0}, {0}, {128}, {0}},
1152	{{0}, {0}, {0}, {0}}},
1153
1154	{SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16,
1155	{4, 4, 1}, 16, 16,
1156	{{0}, {0}, {128}, {0}},
1157	{{0}, {0}, {0}, {0}}},
1158
1159	{SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
1160	{4, 4, 1}, 16, 16,
1161	{{0}, {0}, {128}, {0}},
1162	{{0}, {0}, {0}, {0}}},
1163
1164	{SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM,
1165	{4, 4, 1}, 16, 16,
1166	{{0}, {0}, {128}, {0}},
1167	{{0}, {0}, {0}, {0}}},
1168
1169	{SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
1170	{4, 4, 1}, 16, 16,
1171	{{0}, {0}, {128}, {0}},
1172	{{0}, {0}, {0}, {0}}},
1173
1174	{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
1175	{1, 1, 1}, 4, 4,
1176	{{8}, {8}, {8}, {8}},
1177	{{0}, {8}, {16}, {24}}},
1178	};
1179
1180	static inline u32 clamped_umul32(u32 a, u32 b)
1181	{
1182	uint64_t tmp = (uint64_t) a*b;
1183	return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
1184	}
1185
1186	/**
1187	* svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
1188	* given format.
1189	*/
1190	static inline const struct svga3d_surface_desc *
1191	svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
1192	{
1193	if (format < ARRAY_SIZE(svga3d_surface_descs))
1194	return &svga3d_surface_descs[format];
1195
1196	return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
1197	}
1198
1199	/**
1200	* svga3dsurface_get_mip_size - Given a base level size and the mip level,
1201	* compute the size of the mip level.
1202	*/
1203	static inline surf_size_struct
1204	svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
1205	{
1206	surf_size_struct size;
1207
1208	size.width = max_t(u32, base_level.width >> mip_level, 1);
1209	size.height = max_t(u32, base_level.height >> mip_level, 1);
1210	size.depth = max_t(u32, base_level.depth >> mip_level, 1);
1211	size.pad64 = 0;
1212
1213	return size;
1214	}
1215
1216	static inline void
1217	svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
1218	const surf_size_struct *pixel_size,
1219	surf_size_struct *block_size)
1220	{
1221	block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width,
1222	desc->block_size.width);
1223	block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height,
1224	desc->block_size.height);
1225	block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth,
1226	desc->block_size.depth);
1227	}
1228
1229	static inline bool
1230	svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
1231	{
1232	return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
1233	}
1234
1235	static inline u32
1236	svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
1237	const surf_size_struct *size)
1238	{
1239	u32 pitch;
1240	surf_size_struct blocks;
1241
1242	svga3dsurface_get_size_in_blocks(desc, size, &blocks);
1243
1244	pitch = blocks.width * desc->pitch_bytes_per_block;
1245
1246	return pitch;
1247	}
1248
1249	/**
1250	* svga3dsurface_get_image_buffer_size - Calculates image buffer size.
1251	*
1252	* Return the number of bytes of buffer space required to store one image of a
1253	* surface, optionally using the specified pitch.
1254	*
1255	* If pitch is zero, it is assumed that rows are tightly packed.
1256	*
1257	* This function is overflow-safe. If the result would have overflowed, instead
1258	* we return MAX_UINT32.
1259	*/
1260	static inline u32
1261	svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
1262	const surf_size_struct *size,
1263	u32 pitch)
1264	{
1265	surf_size_struct image_blocks;
1266	u32 slice_size, total_size;
1267
1268	svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
1269
1270	if (svga3dsurface_is_planar_surface(desc)) {
1271	total_size = clamped_umul32(image_blocks.width,
1272	image_blocks.height);
1273	total_size = clamped_umul32(total_size, image_blocks.depth);
1274	total_size = clamped_umul32(total_size, desc->bytes_per_block);
1275	return total_size;
1276	}
1277
1278	if (pitch == 0)
1279	pitch = svga3dsurface_calculate_pitch(desc, size);
1280
1281	slice_size = clamped_umul32(image_blocks.height, pitch);
1282	total_size = clamped_umul32(slice_size, image_blocks.depth);
1283
1284	return total_size;
1285	}
1286
1287	/**
1288	* svga3dsurface_get_serialized_size - Get the serialized size for the image.
1289	*/
1290	static inline u32
1291	svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
1292	surf_size_struct base_level_size,
1293	u32 num_mip_levels,
1294	u32 num_layers)
1295	{
1296	const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
1297	u32 total_size = 0;
1298	u32 mip;
1299
1300	for (mip = 0; mip < num_mip_levels; mip++) {
1301	surf_size_struct size =
1302	svga3dsurface_get_mip_size(base_level_size, mip);
1303	total_size += svga3dsurface_get_image_buffer_size(desc,
1304	&size, 0);
1305	}
1306
1307	return total_size * num_layers;
1308	}
1309
1310	/**
1311	* svga3dsurface_get_serialized_size_extended - Returns the number of bytes
1312	* required for a surface with given parameters. Support for sample count.
1313	*/
1314	static inline u32
1315	svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format,
1316	surf_size_struct base_level_size,
1317	u32 num_mip_levels,
1318	u32 num_layers,
1319	u32 num_samples)
1320	{
1321	uint64_t total_size =
1322	svga3dsurface_get_serialized_size(format,
1323	base_level_size,
1324	num_mip_levels,
1325	num_layers);
1326	total_size *= max_t(u32, 1, num_samples);
1327
1328	return min_t(uint64_t, total_size, (uint64_t)U32_MAX);
1329	}
1330
1331	/**
1332	* svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel
1333	* in an image (or volume).
1334	*
1335	* @width: The image width in pixels.
1336	* @height: The image height in pixels
1337	*/
1338	static inline u32
1339	svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
1340	u32 width, u32 height,
1341	u32 x, u32 y, u32 z)
1342	{
1343	const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
1344	const u32 bw = desc->block_size.width, bh = desc->block_size.height;
1345	const u32 bd = desc->block_size.depth;
1346	const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) *
1347	desc->bytes_per_block;
1348	const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride;
1349	const u32 offset = (z / bd * imgstride +
1350	y / bh * rowstride +
1351	x / bw * desc->bytes_per_block);
1352	return offset;
1353	}
1354
1355	static inline u32
1356	svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
1357	surf_size_struct baseLevelSize,
1358	u32 numMipLevels,
1359	u32 face,
1360	u32 mip)
1361
1362	{
1363	u32 offset;
1364	u32 mipChainBytes;
1365	u32 mipChainBytesToLevel;
1366	u32 i;
1367	const struct svga3d_surface_desc *desc;
1368	surf_size_struct mipSize;
1369	u32 bytes;
1370
1371	desc = svga3dsurface_get_desc(format);
1372
1373	mipChainBytes = 0;
1374	mipChainBytesToLevel = 0;
1375	for (i = 0; i < numMipLevels; i++) {
1376	mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
1377	bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
1378	mipChainBytes += bytes;
1379	if (i < mip)
1380	mipChainBytesToLevel += bytes;
1381	}
1382
1383	offset = mipChainBytes * face + mipChainBytesToLevel;
1384
1385	return offset;
1386	}
1387
1388
1389	/**
1390	* svga3dsurface_is_gb_screen_target_format - Is the specified format usable as
1391	* a ScreenTarget?
1392	* (with just the GBObjects cap-bit
1393	* set)
1394	* @format: format to queried
1395	*
1396	* RETURNS:
1397	* true if queried format is valid for screen targets
1398	*/
1399	static inline bool
1400	svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
1401	{
1402	return (format == SVGA3D_X8R8G8B8 \|\|
1403	format == SVGA3D_A8R8G8B8 \|\|
1404	format == SVGA3D_R5G6B5 \|\|
1405	format == SVGA3D_X1R5G5B5 \|\|
1406	format == SVGA3D_A1R5G5B5 \|\|
1407	format == SVGA3D_P8);
1408	}
1409
1410
1411	/**
1412	* svga3dsurface_is_dx_screen_target_format - Is the specified format usable as
1413	* a ScreenTarget?
1414	* (with DX10 enabled)
1415	*
1416	* @format: format to queried
1417	*
1418	* Results:
1419	* true if queried format is valid for screen targets
1420	*/
1421	static inline bool
1422	svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
1423	{
1424	return (format == SVGA3D_R8G8B8A8_UNORM \|\|
1425	format == SVGA3D_B8G8R8A8_UNORM \|\|
1426	format == SVGA3D_B8G8R8X8_UNORM);
1427	}
1428
1429
1430	/**
1431	* svga3dsurface_is_screen_target_format - Is the specified format usable as a
1432	* ScreenTarget?
1433	* (for some combination of caps)
1434	*
1435	* @format: format to queried
1436	*
1437	* Results:
1438	* true if queried format is valid for screen targets
1439	*/
1440	static inline bool
1441	svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format)
1442	{
1443	if (svga3dsurface_is_gb_screen_target_format(format)) {
1444	return true;
1445	}
1446	return svga3dsurface_is_dx_screen_target_format(format);
1447	}
1448
1449	#ifndef VBOX
1450	/**
1451	* struct svga3dsurface_mip - Mimpmap level information
1452	* @bytes: Bytes required in the backing store of this mipmap level.
1453	* @img_stride: Byte stride per image.
1454	* @row_stride: Byte stride per block row.
1455	* @size: The size of the mipmap.
1456	*/
1457	struct svga3dsurface_mip {
1458	size_t bytes;
1459	size_t img_stride;
1460	size_t row_stride;
1461	struct drm_vmw_size size;
1462
1463	};
1464
1465	/**
1466	* struct svga3dsurface_cache - Cached surface information
1467	* @desc: Pointer to the surface descriptor
1468	* @mip: Array of mipmap level information. Valid size is @num_mip_levels.
1469	* @mip_chain_bytes: Bytes required in the backing store for the whole chain
1470	* of mip levels.
1471	* @sheet_bytes: Bytes required in the backing store for a sheet
1472	* representing a single sample.
1473	* @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
1474	* a chain.
1475	* @num_layers: Number of slices in an array texture or number of faces in
1476	* a cubemap texture.
1477	*/
1478	struct svga3dsurface_cache {
1479	const struct svga3d_surface_desc *desc;
1480	struct svga3dsurface_mip mip[DRM_VMW_MAX_MIP_LEVELS];
1481	size_t mip_chain_bytes;
1482	size_t sheet_bytes;
1483	u32 num_mip_levels;
1484	u32 num_layers;
1485	};
1486
1487	/**
1488	* struct svga3dsurface_loc - Surface location
1489	* @sheet: The multisample sheet.
1490	* @sub_resource: Surface subresource. Defined as layer * num_mip_levels +
1491	* mip_level.
1492	* @x: X coordinate.
1493	* @y: Y coordinate.
1494	* @z: Z coordinate.
1495	*/
1496	struct svga3dsurface_loc {
1497	u32 sheet;
1498	u32 sub_resource;
1499	u32 x, y, z;
1500	};
1501
1502	/**
1503	* svga3dsurface_subres - Compute the subresource from layer and mipmap.
1504	* @cache: Surface layout data.
1505	* @mip_level: The mipmap level.
1506	* @layer: The surface layer (face or array slice).
1507	*
1508	* Return: The subresource.
1509	*/
1510	static inline u32 svga3dsurface_subres(const struct svga3dsurface_cache *cache,
1511	u32 mip_level, u32 layer)
1512	{
1513	return cache->num_mip_levels * layer + mip_level;
1514	}
1515
1516	/**
1517	* svga3dsurface_setup_cache - Build a surface cache entry
1518	* @size: The surface base level dimensions.
1519	* @format: The surface format.
1520	* @num_mip_levels: Number of mipmap levels.
1521	* @num_layers: Number of layers.
1522	* @cache: Pointer to a struct svga3dsurface_cach object to be filled in.
1523	*
1524	* Return: Zero on success, -EINVAL on invalid surface layout.
1525	*/
1526	static inline int svga3dsurface_setup_cache(const struct drm_vmw_size *size,
1527	SVGA3dSurfaceFormat format,
1528	u32 num_mip_levels,
1529	u32 num_layers,
1530	u32 num_samples,
1531	struct svga3dsurface_cache *cache)
1532	{
1533	const struct svga3d_surface_desc *desc;
1534	u32 i;
1535
1536	memset(cache, 0, sizeof(*cache));
1537	cache->desc = desc = svga3dsurface_get_desc(format);
1538	cache->num_mip_levels = num_mip_levels;
1539	cache->num_layers = num_layers;
1540	for (i = 0; i < cache->num_mip_levels; i++) {
1541	struct svga3dsurface_mip *mip = &cache->mip[i];
1542
1543	mip->size = svga3dsurface_get_mip_size(*size, i);
1544	mip->bytes = svga3dsurface_get_image_buffer_size
1545	(desc, &mip->size, 0);
1546	mip->row_stride =
1547	__KERNEL_DIV_ROUND_UP(mip->size.width,
1548	desc->block_size.width) *
1549	desc->bytes_per_block * num_samples;
1550	if (!mip->row_stride)
1551	goto invalid_dim;
1552
1553	mip->img_stride =
1554	__KERNEL_DIV_ROUND_UP(mip->size.height,
1555	desc->block_size.height) *
1556	mip->row_stride;
1557	if (!mip->img_stride)
1558	goto invalid_dim;
1559
1560	cache->mip_chain_bytes += mip->bytes;
1561	}
1562	cache->sheet_bytes = cache->mip_chain_bytes * num_layers;
1563	if (!cache->sheet_bytes)
1564	goto invalid_dim;
1565
1566	return 0;
1567
1568	invalid_dim:
1569	VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n");
1570	return -EINVAL;
1571	}
1572
1573	/**
1574	* svga3dsurface_get_loc - Get a surface location from an offset into the
1575	* backing store
1576	* @cache: Surface layout data.
1577	* @loc: Pointer to a struct svga3dsurface_loc to be filled in.
1578	* @offset: Offset into the surface backing store.
1579	*/
1580	static inline void
1581	svga3dsurface_get_loc(const struct svga3dsurface_cache *cache,
1582	struct svga3dsurface_loc *loc,
1583	size_t offset)
1584	{
1585	const struct svga3dsurface_mip *mip = &cache->mip[0];
1586	const struct svga3d_surface_desc *desc = cache->desc;
1587	u32 layer;
1588	int i;
1589
1590	loc->sheet = offset / cache->sheet_bytes;
1591	offset -= loc->sheet * cache->sheet_bytes;
1592
1593	layer = offset / cache->mip_chain_bytes;
1594	offset -= layer * cache->mip_chain_bytes;
1595	for (i = 0; i < cache->num_mip_levels; ++i, ++mip) {
1596	if (mip->bytes > offset)
1597	break;
1598	offset -= mip->bytes;
1599	}
1600
1601	loc->sub_resource = svga3dsurface_subres(cache, i, layer);
1602	loc->z = offset / mip->img_stride;
1603	offset -= loc->z * mip->img_stride;
1604	loc->z *= desc->block_size.depth;
1605	loc->y = offset / mip->row_stride;
1606	offset -= loc->y * mip->row_stride;
1607	loc->y *= desc->block_size.height;
1608	loc->x = offset / desc->bytes_per_block;
1609	loc->x *= desc->block_size.width;
1610	}
1611
1612	/**
1613	* svga3dsurface_inc_loc - Clamp increment a surface location with one block
1614	* size
1615	* in each dimension.
1616	* @loc: Pointer to a struct svga3dsurface_loc to be incremented.
1617	*
1618	* When computing the size of a range as size = end - start, the range does not
1619	* include the end element. However a location representing the last byte
1620	* of a touched region in the backing store is included in the range.
1621	* This function modifies such a location to match the end definition
1622	* given as start + size which is the one used in a SVGA3dBox.
1623	*/
1624	static inline void
1625	svga3dsurface_inc_loc(const struct svga3dsurface_cache *cache,
1626	struct svga3dsurface_loc *loc)
1627	{
1628	const struct svga3d_surface_desc *desc = cache->desc;
1629	u32 mip = loc->sub_resource % cache->num_mip_levels;
1630	const struct drm_vmw_size *size = &cache->mip[mip].size;
1631
1632	loc->sub_resource++;
1633	loc->x += desc->block_size.width;
1634	if (loc->x > size->width)
1635	loc->x = size->width;
1636	loc->y += desc->block_size.height;
1637	if (loc->y > size->height)
1638	loc->y = size->height;
1639	loc->z += desc->block_size.depth;
1640	if (loc->z > size->depth)
1641	loc->z = size->depth;
1642	}
1643
1644	/**
1645	* svga3dsurface_min_loc - The start location in a subresource
1646	* @cache: Surface layout data.
1647	* @sub_resource: The subresource.
1648	* @loc: Pointer to a struct svga3dsurface_loc to be filled in.
1649	*/
1650	static inline void
1651	svga3dsurface_min_loc(const struct svga3dsurface_cache *cache,
1652	u32 sub_resource,
1653	struct svga3dsurface_loc *loc)
1654	{
1655	loc->sheet = 0;
1656	loc->sub_resource = sub_resource;
1657	loc->x = loc->y = loc->z = 0;
1658	}
1659
1660	/**
1661	* svga3dsurface_min_loc - The end location in a subresource
1662	* @cache: Surface layout data.
1663	* @sub_resource: The subresource.
1664	* @loc: Pointer to a struct svga3dsurface_loc to be filled in.
1665	*
1666	* Following the end definition given in svga3dsurface_inc_loc(),
1667	* Compute the end location of a surface subresource.
1668	*/
1669	static inline void
1670	svga3dsurface_max_loc(const struct svga3dsurface_cache *cache,
1671	u32 sub_resource,
1672	struct svga3dsurface_loc *loc)
1673	{
1674	const struct drm_vmw_size *size;
1675	u32 mip;
1676
1677	loc->sheet = 0;
1678	loc->sub_resource = sub_resource + 1;
1679	mip = sub_resource % cache->num_mip_levels;
1680	size = &cache->mip[mip].size;
1681	loc->x = size->width;
1682	loc->y = size->height;
1683	loc->z = size->depth;
1684	}
1685	#endif /* !VBOX */
1686
1687	#endif /* _SVGA3D_SURFACEDEFS_H_ */

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga_include/svga3d_surfacedefs.h

Download in other formats: