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source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga/svga3d_shaderdefs.h@ 82781

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1/**********************************************************
2 * Copyright 2007-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_shaderdefs.h --
28 *
29 * SVGA3D byte code format and limit definitions.
30 *
31 * The format of the byte code directly corresponds to that defined
32 * by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can
33 * also be extended so that different shader formats can be supported
34 * for example GLSL, ARB vp/fp, NV/ATI shader formats, etc.
35 *
36 */
37
38#ifndef __SVGA3D_SHADER_DEFS__
39#define __SVGA3D_SHADER_DEFS__
40#ifndef RT_WITHOUT_PRAGMA_ONCE
41# pragma once
42#endif
43
44/* SVGA3D shader hardware limits. */
45
46#define SVGA3D_INPUTREG_MAX 16
47#define SVGA3D_OUTPUTREG_MAX 12
48#define SVGA3D_VERTEX_SAMPLERREG_MAX 4
49#define SVGA3D_PIXEL_SAMPLERREG_MAX 16
50#define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\
51 SVGA3D_VERTEX_SAMPLERREG_MAX)
52#define SVGA3D_TEMPREG_MAX 32
53#define SVGA3D_CONSTREG_MAX 256
54#define SVGA3D_CONSTINTREG_MAX 16
55#define SVGA3D_CONSTBOOLREG_MAX 16
56#define SVGA3D_ADDRREG_MAX 1
57#define SVGA3D_PREDREG_MAX 1
58
59/* SVGA3D byte code specific limits */
60
61#define SVGA3D_MAX_SRC_REGS 4
62#define SVGA3D_MAX_NESTING_LEVEL 32
63
64/* SVGA3D version information. */
65
66#define SVGA3D_VS_TYPE 0xFFFE
67#define SVGA3D_PS_TYPE 0xFFFF
68
69typedef struct {
70 union {
71 struct {
72 uint32_t minor : 8;
73 uint32_t major : 8;
74 uint32_t type : 16;
75 } s;
76
77 uint32_t value;
78 };
79} SVGA3dShaderVersion;
80
81#define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8)
82#define SVGA3D_VS_11 (SVGA3D_VS_10 | 1)
83#define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8)
84#define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8)
85
86#define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8)
87#define SVGA3D_PS_11 (SVGA3D_PS_10 | 1)
88#define SVGA3D_PS_12 (SVGA3D_PS_10 | 2)
89#define SVGA3D_PS_13 (SVGA3D_PS_10 | 3)
90#define SVGA3D_PS_14 (SVGA3D_PS_10 | 4)
91#define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8)
92#define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8)
93
94/* The *_ENABLED are for backwards compatibility with old drivers */
95typedef enum {
96 SVGA3DPSVERSION_NONE = 0,
97 SVGA3DPSVERSION_ENABLED = 1,
98 SVGA3DPSVERSION_11 = 3,
99 SVGA3DPSVERSION_12 = 5,
100 SVGA3DPSVERSION_13 = 7,
101 SVGA3DPSVERSION_14 = 9,
102 SVGA3DPSVERSION_20 = 11,
103 SVGA3DPSVERSION_30 = 13,
104 SVGA3DPSVERSION_40 = 15,
105 SVGA3DPSVERSION_MAX
106} SVGA3dPixelShaderVersion;
107
108typedef enum {
109 SVGA3DVSVERSION_NONE = 0,
110 SVGA3DVSVERSION_ENABLED = 1,
111 SVGA3DVSVERSION_11 = 3,
112 SVGA3DVSVERSION_20 = 5,
113 SVGA3DVSVERSION_30 = 7,
114 SVGA3DVSVERSION_40 = 9,
115 SVGA3DVSVERSION_MAX
116} SVGA3dVertexShaderVersion;
117
118/* SVGA3D instruction op codes. */
119
120typedef enum {
121 SVGA3DOP_NOP = 0,
122 SVGA3DOP_MOV,
123 SVGA3DOP_ADD,
124 SVGA3DOP_SUB,
125 SVGA3DOP_MAD,
126 SVGA3DOP_MUL,
127 SVGA3DOP_RCP,
128 SVGA3DOP_RSQ,
129 SVGA3DOP_DP3,
130 SVGA3DOP_DP4,
131 SVGA3DOP_MIN,
132 SVGA3DOP_MAX,
133 SVGA3DOP_SLT,
134 SVGA3DOP_SGE,
135 SVGA3DOP_EXP,
136 SVGA3DOP_LOG,
137 SVGA3DOP_LIT,
138 SVGA3DOP_DST,
139 SVGA3DOP_LRP,
140 SVGA3DOP_FRC,
141 SVGA3DOP_M4x4,
142 SVGA3DOP_M4x3,
143 SVGA3DOP_M3x4,
144 SVGA3DOP_M3x3,
145 SVGA3DOP_M3x2,
146 SVGA3DOP_CALL,
147 SVGA3DOP_CALLNZ,
148 SVGA3DOP_LOOP,
149 SVGA3DOP_RET,
150 SVGA3DOP_ENDLOOP,
151 SVGA3DOP_LABEL,
152 SVGA3DOP_DCL,
153 SVGA3DOP_POW,
154 SVGA3DOP_CRS,
155 SVGA3DOP_SGN,
156 SVGA3DOP_ABS,
157 SVGA3DOP_NRM,
158 SVGA3DOP_SINCOS,
159 SVGA3DOP_REP,
160 SVGA3DOP_ENDREP,
161 SVGA3DOP_IF,
162 SVGA3DOP_IFC,
163 SVGA3DOP_ELSE,
164 SVGA3DOP_ENDIF,
165 SVGA3DOP_BREAK,
166 SVGA3DOP_BREAKC,
167 SVGA3DOP_MOVA,
168 SVGA3DOP_DEFB,
169 SVGA3DOP_DEFI,
170 SVGA3DOP_TEXCOORD = 64,
171 SVGA3DOP_TEXKILL,
172 SVGA3DOP_TEX,
173 SVGA3DOP_TEXBEM,
174 SVGA3DOP_TEXBEML,
175 SVGA3DOP_TEXREG2AR,
176 SVGA3DOP_TEXREG2GB = 70,
177 SVGA3DOP_TEXM3x2PAD,
178 SVGA3DOP_TEXM3x2TEX,
179 SVGA3DOP_TEXM3x3PAD,
180 SVGA3DOP_TEXM3x3TEX,
181 SVGA3DOP_RESERVED0,
182 SVGA3DOP_TEXM3x3SPEC,
183 SVGA3DOP_TEXM3x3VSPEC,
184 SVGA3DOP_EXPP,
185 SVGA3DOP_LOGP,
186 SVGA3DOP_CND = 80,
187 SVGA3DOP_DEF,
188 SVGA3DOP_TEXREG2RGB,
189 SVGA3DOP_TEXDP3TEX,
190 SVGA3DOP_TEXM3x2DEPTH,
191 SVGA3DOP_TEXDP3,
192 SVGA3DOP_TEXM3x3,
193 SVGA3DOP_TEXDEPTH,
194 SVGA3DOP_CMP,
195 SVGA3DOP_BEM,
196 SVGA3DOP_DP2ADD = 90,
197 SVGA3DOP_DSX,
198 SVGA3DOP_DSY,
199 SVGA3DOP_TEXLDD,
200 SVGA3DOP_SETP,
201 SVGA3DOP_TEXLDL,
202 SVGA3DOP_BREAKP = 96,
203 SVGA3DOP_LAST_INST,
204 SVGA3DOP_PHASE = 0xFFFD,
205 SVGA3DOP_COMMENT = 0xFFFE,
206 SVGA3DOP_END = 0xFFFF
207} SVGA3dShaderOpCodeType;
208
209/* SVGA3D operation control/comparison function types */
210
211typedef enum {
212 SVGA3DOPCONT_NONE,
213 SVGA3DOPCONT_PROJECT, /* Projective texturing */
214 SVGA3DOPCONT_BIAS /* Texturing with a LOD bias */
215} SVGA3dShaderOpCodeControlFnType;
216
217typedef enum {
218 SVGA3DOPCOMP_RESERVED0 = 0,
219 SVGA3DOPCOMP_GT,
220 SVGA3DOPCOMP_EQ,
221 SVGA3DOPCOMP_GE,
222 SVGA3DOPCOMP_LT,
223 SVGA3DOPCOMPC_NE,
224 SVGA3DOPCOMP_LE,
225 SVGA3DOPCOMP_RESERVED1
226} SVGA3dShaderOpCodeCompFnType;
227
228/* SVGA3D register types */
229
230typedef enum {
231 SVGA3DREG_TEMP = 0, /* Temporary register file */
232 SVGA3DREG_INPUT, /* Input register file */
233 SVGA3DREG_CONST, /* Constant register file */
234 SVGA3DREG_ADDR, /* Address register for VS */
235 SVGA3DREG_TEXTURE = 3, /* Texture register file for PS */
236 SVGA3DREG_RASTOUT, /* Rasterizer register file */
237 SVGA3DREG_ATTROUT, /* Attribute output register file */
238 SVGA3DREG_TEXCRDOUT, /* Texture coordinate output register file */
239 SVGA3DREG_OUTPUT = 6, /* Output register file for VS 3.0+ */
240 SVGA3DREG_CONSTINT, /* Constant integer vector register file */
241 SVGA3DREG_COLOROUT, /* Color output register file */
242 SVGA3DREG_DEPTHOUT, /* Depth output register file */
243 SVGA3DREG_SAMPLER, /* Sampler state register file */
244 SVGA3DREG_CONST2, /* Constant register file 2048 - 4095 */
245 SVGA3DREG_CONST3, /* Constant register file 4096 - 6143 */
246 SVGA3DREG_CONST4, /* Constant register file 6144 - 8191 */
247 SVGA3DREG_CONSTBOOL, /* Constant boolean register file */
248 SVGA3DREG_LOOP, /* Loop counter register file */
249 SVGA3DREG_TEMPFLOAT16, /* 16-bit float temp register file */
250 SVGA3DREG_MISCTYPE, /* Miscellaneous (single) registers */
251 SVGA3DREG_LABEL, /* Label */
252 SVGA3DREG_PREDICATE /* Predicate register */
253} SVGA3dShaderRegType;
254
255/* SVGA3D rasterizer output register types */
256
257typedef enum {
258 SVGA3DRASTOUT_POSITION = 0,
259 SVGA3DRASTOUT_FOG,
260 SVGA3DRASTOUT_PSIZE
261} SVGA3dShaderRastOutRegType;
262
263/* SVGA3D miscellaneous register types */
264
265typedef enum {
266 SVGA3DMISCREG_POSITION = 0, /* Input position x,y,z,rhw (PS) */
267 SVGA3DMISCREG_FACE /* Floating point primitive area (PS) */
268} SVGA3DShaderMiscRegType;
269
270/* SVGA3D sampler types */
271
272typedef enum {
273 SVGA3DSAMP_UNKNOWN = 0, /* Uninitialized value */
274 SVGA3DSAMP_2D = 2, /* dcl_2d s# (for declaring a 2-D texture) */
275 SVGA3DSAMP_CUBE, /* dcl_cube s# (for declaring a cube texture) */
276 SVGA3DSAMP_VOLUME /* dcl_volume s# (for declaring a volume texture) */
277} SVGA3dShaderSamplerType;
278
279/* SVGA3D sampler format classes */
280
281typedef enum {
282 SVGA3DSAMPFORMAT_ARGB, /* ARGB formats */
283 SVGA3DSAMPFORMAT_V8U8, /* Sign and normalize (SNORM) V & U */
284 SVGA3DSAMPFORMAT_Q8W8V8U8, /* SNORM all */
285 SVGA3DSAMPFORMAT_CxV8U8, /* SNORM V & U, C=SQRT(1-U^2-V^2) */
286 SVGA3DSAMPFORMAT_X8L8V8U8, /* SNORM V & U */
287 SVGA3DSAMPFORMAT_A2W10V10U10, /* SNORM W, V & U */
288 SVGA3DSAMPFORMAT_DXT_PMA, /* DXT pre-multiplied alpha */
289 SVGA3DSAMPFORMAT_YUV, /* YUV video format */
290 SVGA3DSAMPFORMAT_UYVY, /* UYVY video format */
291 SVGA3DSAMPFORMAT_Rx, /* R16F/32F */
292 SVGA3DSAMPFORMAT_RxGx, /* R16FG16F, R32FG32F */
293 SVGA3DSAMPFORMAT_V16U16 /* SNORM all */
294} SVGA3DShaderSamplerFormatClass;
295
296/* SVGA3D write mask */
297
298#define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */
299#define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */
300#define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */
301#define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */
302#define SVGA3DWRITEMASK_ALL 15 /* All components */
303
304/* SVGA3D destination modifiers */
305
306#define SVGA3DDSTMOD_NONE 0 /* nop */
307#define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */
308#define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */
309
310/*
311 * Relevant to multisampling only:
312 * When the pixel center is not covered, sample
313 * attribute or compute gradients/LOD
314 * using multisample "centroid" location.
315 * "Centroid" is some location within the covered
316 * region of the pixel.
317 */
318
319#define SVGA3DDSTMOD_MSAMPCENTROID 4
320
321/* SVGA3D source swizzle */
322
323#define SVGA3DSWIZZLE_REPLICATEX 0x00
324#define SVGA3DSWIZZLE_REPLICATEY 0x55
325#define SVGA3DSWIZZLE_REPLICATEZ 0xAA
326#define SVGA3DSWIZZLE_REPLICATEW 0xFF
327#define SVGA3DSWIZZLE_NONE 0xE4
328#define SVGA3DSWIZZLE_YZXW 0xC9
329#define SVGA3DSWIZZLE_ZXYW 0xD2
330#define SVGA3DSWIZZLE_WXYZ 0x1B
331
332/* SVGA3D source modifiers */
333
334typedef enum {
335 SVGA3DSRCMOD_NONE = 0, /* nop */
336 SVGA3DSRCMOD_NEG, /* negate */
337 SVGA3DSRCMOD_BIAS, /* bias */
338 SVGA3DSRCMOD_BIASNEG, /* bias and negate */
339 SVGA3DSRCMOD_SIGN, /* sign */
340 SVGA3DSRCMOD_SIGNNEG, /* sign and negate */
341 SVGA3DSRCMOD_COMP, /* complement */
342 SVGA3DSRCMOD_X2, /* x2 */
343 SVGA3DSRCMOD_X2NEG, /* x2 and negate */
344 SVGA3DSRCMOD_DZ, /* divide through by z component */
345 SVGA3DSRCMOD_DW, /* divide through by w component */
346 SVGA3DSRCMOD_ABS, /* abs() */
347 SVGA3DSRCMOD_ABSNEG, /* -abs() */
348 SVGA3DSRCMOD_NOT /* ! (for predicate register) */
349} SVGA3dShaderSrcModType;
350
351/* SVGA3D instruction token */
352
353typedef struct {
354 union {
355 struct {
356 uint32_t comment_op : 16;
357 uint32_t comment_size : 16;
358 } s;
359
360 struct {
361 uint32_t op : 16;
362 uint32_t control : 3;
363 uint32_t reserved2 : 5;
364 uint32_t size : 4;
365 uint32_t predicated : 1;
366 uint32_t reserved1 : 1;
367 uint32_t coissue : 1;
368 uint32_t reserved0 : 1;
369 } s1;
370
371 uint32_t value;
372 };
373} SVGA3dShaderInstToken;
374
375/* SVGA3D destination parameter token */
376
377typedef struct {
378 union {
379 struct {
380 uint32_t num : 11;
381 uint32_t type_upper : 2;
382 uint32_t relAddr : 1;
383 uint32_t reserved1 : 2;
384 uint32_t mask : 4;
385 uint32_t dstMod : 4;
386 uint32_t shfScale : 4;
387 uint32_t type_lower : 3;
388 uint32_t reserved0 : 1;
389 } s;
390
391 uint32_t value;
392 };
393} SVGA3dShaderDestToken;
394
395/* SVGA3D source parameter token */
396
397typedef struct {
398 union {
399 struct {
400 uint32_t num : 11;
401 uint32_t type_upper : 2;
402 uint32_t relAddr : 1;
403 uint32_t reserved1 : 2;
404 uint32_t swizzle : 8;
405 uint32_t srcMod : 4;
406 uint32_t type_lower : 3;
407 uint32_t reserved0 : 1;
408 } s;
409
410 uint32_t value;
411 };
412} SVGA3dShaderSrcToken;
413
414/* SVGA3DOP_DCL parameter tokens */
415
416typedef struct {
417 union {
418 struct {
419 union {
420 struct {
421 uint32_t usage : 5;
422 uint32_t reserved1 : 11;
423 uint32_t index : 4;
424 uint32_t reserved0 : 12;
425 } s; /* input / output declaration */
426
427 struct {
428 uint32_t reserved3 : 27;
429 uint32_t type : 4;
430 uint32_t reserved2 : 1;
431 } s1; /* sampler declaration */
432 };
433
434 SVGA3dShaderDestToken dst;
435 } s2;
436
437 uint32_t values[2];
438 };
439} SVGA3DOpDclArgs;
440
441/* SVGA3DOP_DEF parameter tokens */
442
443typedef struct {
444 union {
445 struct {
446 SVGA3dShaderDestToken dst;
447
448 union {
449 float constValues[4];
450 int constIValues[4];
451 bool constBValue;
452 };
453 } s;
454
455 uint32_t values[5];
456 };
457} SVGA3DOpDefArgs;
458
459/* SVGA3D shader token */
460
461typedef union {
462 uint32_t value;
463 SVGA3dShaderInstToken inst;
464 SVGA3dShaderDestToken dest;
465 SVGA3dShaderSrcToken src;
466} SVGA3dShaderToken;
467
468/* SVGA3D shader program */
469
470typedef struct {
471 SVGA3dShaderVersion version;
472 /* SVGA3dShaderToken stream */
473} SVGA3dShaderProgram;
474
475
476#if 0
477/* SVGA3D version specific register assignments */
478
479static const uint32_t SVGA3D_INPUT_REG_POSITION_VS11 = 0;
480static const uint32_t SVGA3D_INPUT_REG_PSIZE_VS11 = 1;
481static const uint32_t SVGA3D_INPUT_REG_FOG_VS11 = 3;
482static const uint32_t SVGA3D_INPUT_REG_FOG_MASK_VS11 = SVGA3DWRITEMASK_3;
483static const uint32_t SVGA3D_INPUT_REG_COLOR_BASE_VS11 = 2;
484static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_BASE_VS11 = 4;
485
486static const uint32_t SVGA3D_INPUT_REG_COLOR_BASE_PS11 = 0;
487static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_BASE_PS11 = 2;
488static const uint32_t SVGA3D_OUTPUT_REG_DEPTH_PS11 = 0;
489static const uint32_t SVGA3D_OUTPUT_REG_COLOR_PS11 = 1;
490
491static const uint32_t SVGA3D_INPUT_REG_COLOR_BASE_PS20 = 0;
492static const uint32_t SVGA3D_INPUT_REG_COLOR_NUM_PS20 = 2;
493static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_BASE_PS20 = 2;
494static const uint32_t SVGA3D_INPUT_REG_TEXCOORD_NUM_PS20 = 8;
495static const uint32_t SVGA3D_OUTPUT_REG_COLOR_BASE_PS20 = 1;
496static const uint32_t SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4;
497static const uint32_t SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0;
498static const uint32_t SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1;
499
500/*
501 *----------------------------------------------------------------------
502 *
503 * SVGA3dShaderGetRegType --
504 *
505 * As the register type is split into two non sequential fields,
506 * this function provides an useful way of accessing the actual
507 * register type without having to manually concatenate the
508 * type_upper and type_lower fields.
509 *
510 * Results:
511 * Returns the register type.
512 *
513 *----------------------------------------------------------------------
514 */
515
516static INLINE SVGA3dShaderRegType
517SVGA3dShaderGetRegType(uint32_t token)
518{
519 SVGA3dShaderSrcToken src;
520 src.value = token;
521 return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
522}
523#endif
524
525#endif /* !__SVGA3D_SHADER_DEFS__ */
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