VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-hlp.cpp

Last change on this file was 98103, checked in by vboxsync, 16 months ago

Copyright year updates by scm.
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1/* $Id: DevVGA-SVGA3d-hlp.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * DevVMWare - VMWare SVGA device helpers
4 */
5
6/*
7 * Copyright (C) 2020-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
29#include <VBox/AssertGuest.h>
30
31#ifdef SHADER_VERIFY_STANDALONE
32# include <stdio.h>
33//# define Log3(a) printf a - /** @todo r=bird: This is strictly forbidden. Noone redefines Log macros ever! */
34//# define LogRel(a) printf a - /** @todo r=bird: This is strictly forbidden. Noone redefines Log macros ever! */
35#else
36# include <VBox/log.h>
37#endif
38
39#include <iprt/cdefs.h>
40#include <iprt/errcore.h>
41#include <iprt/types.h>
42#include <iprt/string.h>
43
44#include "DevVGA-SVGA.h"
45
46/** Per shader data is stored in this structure. */
47typedef struct VMSVGA3DSHADERPARSECONTEXT
48{
49 /** Version token. */
50 SVGA3dShaderVersion version;
51
52 SVGA3dShaderOpCodeType currentOpcode;
53 union
54 {
55 SVGA3DOpDclArgs *pDclArgs;
56 } u;
57} VMSVGA3DSHADERPARSECONTEXT;
58
59/** Callback which parses a parameter token.
60 *
61 * @param pCtx The shader data.
62 * @param Op Instruction opcode which the token is used with.
63 * @param Token The parameter token which must be parsed.
64 * @param idxToken Index of the parameter token in the instruction. 0 for the first parameter.
65 *
66 * @return VBox error code.
67 */
68typedef int FNSHADERPARSETOKEN(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken);
69typedef FNSHADERPARSETOKEN* PFNSHADERPARSETOKEN;
70
71/** Information about a shader opcode. */
72typedef struct VMSVGA3DSHADERPARSEOP
73{
74 /** Opcode. */
75 SVGA3dShaderOpCodeType Op;
76 /** Maximum number of parameters. */
77 uint32_t Length;
78 /** Pointer to callback, which parse each parameter.
79 * The size is the number of maximum possible parameters: dest + 3 * src
80 */
81 PFNSHADERPARSETOKEN apfnParse[4];
82} VMSVGA3DSHADERPARSEOP;
83
84static int vmsvga3dShaderParseRegOffset(VMSVGA3DSHADERPARSECONTEXT *pCtx,
85 bool fIsSrc,
86 SVGA3dShaderRegType regType,
87 uint32_t off)
88{
89 RT_NOREF(pCtx, fIsSrc);
90
91 switch (regType)
92 {
93 case SVGA3DREG_TEMP:
94 break;
95 case SVGA3DREG_INPUT:
96 break;
97 case SVGA3DREG_CONST:
98 break;
99 case SVGA3DREG_ADDR /* also SVGA3DREG_TEXTURE */:
100 break;
101 case SVGA3DREG_RASTOUT:
102 break;
103 case SVGA3DREG_ATTROUT:
104 break;
105 case SVGA3DREG_TEXCRDOUT /* also SVGA3DREG_OUTPUT */:
106 break;
107 case SVGA3DREG_CONSTINT:
108 break;
109 case SVGA3DREG_COLOROUT:
110 break;
111 case SVGA3DREG_DEPTHOUT:
112 break;
113 case SVGA3DREG_SAMPLER:
114 break;
115 case SVGA3DREG_CONST2:
116 break;
117 case SVGA3DREG_CONST3:
118 break;
119 case SVGA3DREG_CONST4:
120 break;
121 case SVGA3DREG_CONSTBOOL:
122 break;
123 case SVGA3DREG_LOOP:
124 break;
125 case SVGA3DREG_TEMPFLOAT16:
126 break;
127 case SVGA3DREG_MISCTYPE:
128 ASSERT_GUEST_RETURN( off == SVGA3DMISCREG_POSITION
129 || off == SVGA3DMISCREG_FACE, VERR_PARSE_ERROR);
130 break;
131 case SVGA3DREG_LABEL:
132 break;
133 case SVGA3DREG_PREDICATE:
134 break;
135 default:
136 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
137 }
138
139 return VINF_SUCCESS;
140}
141
142/* Parse a declaration parameter token:
143 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/dcl-instruction
144 *
145 * See FNSHADERPARSETOKEN.
146 */
147static int vmsvga3dShaderParseDclToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
148{
149 RT_NOREF(pCtx, Op, Token, idxToken);
150 return VINF_SUCCESS;
151}
152
153/* Parse a label (D3DSPR_LABEL) parameter token.
154 *
155 * See FNSHADERPARSETOKEN.
156 */
157static int vmsvga3dShaderParseLabelToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
158{
159 RT_NOREF(pCtx, Op, Token, idxToken);
160 return VINF_SUCCESS;
161}
162
163/* Parse a destination parameter token:
164 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/destination-parameter-token
165 * See FNSHADERPARSETOKEN.
166 */
167static int vmsvga3dShaderParseDestToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
168{
169 RT_NOREF(pCtx, Op, idxToken);
170
171 SVGA3dShaderDestToken dest;
172 dest.value = Token;
173
174 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(dest.type_upper << 3 | dest.type_lower);
175 Log3(("Dest: type %d, r0 %d, shfScale %d, dstMod %d, mask 0x%x, r1 %d, relAddr %d, num %d\n",
176 regType, dest.reserved0, dest.shfScale, dest.dstMod, dest.mask, dest.reserved1, dest.relAddr, dest.num));
177
178 if (pCtx->currentOpcode == SVGA3DOP_DCL && regType == SVGA3DREG_SAMPLER)
179 {
180 if (pCtx->u.pDclArgs->type == SVGA3DSAMP_UNKNOWN)
181 {
182 Log3(("Replacing SVGA3DSAMP_UNKNOWN with SVGA3DSAMP_2D\n"));
183 pCtx->u.pDclArgs->type = SVGA3DSAMP_2D;
184 }
185 }
186
187 return vmsvga3dShaderParseRegOffset(pCtx, false, regType, dest.num);
188}
189
190/* Parse a source parameter token:
191 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/source-parameter-token
192 * See FNSHADERPARSETOKEN.
193 */
194static int vmsvga3dShaderParseSrcToken(VMSVGA3DSHADERPARSECONTEXT* pCtx, uint32_t Op, uint32_t Token, uint32_t idxToken)
195{
196 RT_NOREF(pCtx, Op, idxToken);
197
198 SVGA3dShaderSrcToken src;
199 src.value = Token;
200
201 SVGA3dShaderRegType const regType = (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
202 Log3(("Src: type %d, r0 %d, srcMod %d, swizzle 0x%x, r1 %d, relAddr %d, num %d\n",
203 regType, src.reserved0, src.srcMod, src.swizzle, src.reserved1, src.relAddr, src.num));
204
205 return vmsvga3dShaderParseRegOffset(pCtx, true, regType, src.num);
206}
207
208/* Shortcut defines. */
209#define PT_DCL vmsvga3dShaderParseDclToken
210#define PT_LBL vmsvga3dShaderParseLabelToken
211#define PT_DEST vmsvga3dShaderParseDestToken
212#define PT_SRC vmsvga3dShaderParseSrcToken
213
214/* Information about opcodes:
215 * https://docs.microsoft.com/en-us/windows-hardware/drivers/ddi/d3d9types/ne-d3d9types-_d3dshader_instruction_opcode_type
216 */
217static const VMSVGA3DSHADERPARSEOP aOps[] =
218{
219 /* Op Length Parameters */
220 /* 00 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
221 /* 01 */ { SVGA3DOP_MOV, 2, { PT_DEST, PT_SRC, NULL, NULL } },
222 /* 02 */ { SVGA3DOP_ADD, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
223 /* 03 */ { SVGA3DOP_SUB, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
224 /* 04 */ { SVGA3DOP_MAD, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
225 /* 05 */ { SVGA3DOP_MUL, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
226 /* 06 */ { SVGA3DOP_RCP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
227 /* 07 */ { SVGA3DOP_RSQ, 2, { PT_DEST, PT_SRC, NULL, NULL } },
228 /* 08 */ { SVGA3DOP_DP3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
229 /* 09 */ { SVGA3DOP_DP4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
230 /* 10 */ { SVGA3DOP_MIN, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
231 /* 11 */ { SVGA3DOP_MAX, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
232 /* 12 */ { SVGA3DOP_SLT, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
233 /* 13 */ { SVGA3DOP_SGE, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
234 /* 14 */ { SVGA3DOP_EXP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
235 /* 15 */ { SVGA3DOP_LOG, 2, { PT_DEST, PT_SRC, NULL, NULL } },
236 /* 16 */ { SVGA3DOP_LIT, 2, { PT_DEST, PT_SRC, NULL, NULL } },
237 /* 17 */ { SVGA3DOP_DST, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
238 /* 18 */ { SVGA3DOP_LRP, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
239 /* 19 */ { SVGA3DOP_FRC, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
240 /* 20 */ { SVGA3DOP_M4x4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
241 /* 21 */ { SVGA3DOP_M4x3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
242 /* 22 */ { SVGA3DOP_M3x4, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
243 /* 23 */ { SVGA3DOP_M3x3, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
244 /* 24 */ { SVGA3DOP_M3x2, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
245 /* 25 */ { SVGA3DOP_CALL, 1, { PT_LBL, NULL, NULL, NULL } },
246 /* 26 */ { SVGA3DOP_CALLNZ, 2, { PT_LBL, PT_SRC, NULL, NULL } },
247 /* 27 */ { SVGA3DOP_LOOP, 1, { PT_SRC, NULL, NULL, NULL } },
248 /* 28 */ { SVGA3DOP_RET, 0, { NULL, NULL, NULL, NULL } },
249 /* 29 */ { SVGA3DOP_ENDLOOP, 0, { NULL, NULL, NULL, NULL } },
250 /* 30 */ { SVGA3DOP_LABEL, 1, { PT_LBL, NULL, NULL, NULL } },
251 /* 31 */ { SVGA3DOP_DCL, 2, { PT_DCL, PT_DEST, NULL, NULL } },
252 /* 32 */ { SVGA3DOP_POW, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
253 /* 33 */ { SVGA3DOP_CRS, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
254 /* 34 */ { SVGA3DOP_SGN, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
255 /* 35 */ { SVGA3DOP_ABS, 2, { PT_DEST, PT_SRC, NULL, NULL } },
256 /* 36 */ { SVGA3DOP_NRM, 2, { PT_DEST, PT_SRC, NULL, NULL } },
257 /* 37 */ { SVGA3DOP_SINCOS, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
258 /* 38 */ { SVGA3DOP_REP, 1, { PT_SRC, NULL, NULL, NULL } },
259 /* 39 */ { SVGA3DOP_ENDREP, 0, { NULL, NULL, NULL, NULL } },
260 /* 40 */ { SVGA3DOP_IF, 1, { PT_SRC, NULL, NULL, NULL } },
261 /* 41 */ { SVGA3DOP_IFC, 2, { PT_SRC, PT_SRC, NULL, NULL } },
262 /* 42 */ { SVGA3DOP_ELSE, 0, { NULL, NULL, NULL, NULL } },
263 /* 43 */ { SVGA3DOP_ENDIF, 0, { NULL, NULL, NULL, NULL } },
264 /* 44 */ { SVGA3DOP_BREAK, 0, { NULL, NULL, NULL, NULL } },
265 /* 45 */ { SVGA3DOP_BREAKC, 2, { PT_SRC, PT_SRC, NULL, NULL } },
266 /* 46 */ { SVGA3DOP_MOVA, 2, { PT_DEST, PT_SRC, NULL, NULL } },
267 /* 47 */ { SVGA3DOP_DEFB, 2, { PT_DEST, NULL, NULL, NULL } },
268 /* 48 */ { SVGA3DOP_DEFI, 5, { PT_DEST, NULL, NULL, NULL } },
269 /* 49 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
270 /* 50 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
271 /* 51 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
272 /* 52 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
273 /* 53 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
274 /* 54 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
275 /* 55 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
276 /* 56 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
277 /* 57 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
278 /* 58 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
279 /* 59 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
280 /* 60 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
281 /* 61 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
282 /* 62 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
283 /* 63 */ { SVGA3DOP_NOP, 0, { NULL, NULL, NULL, NULL } },
284 /* 64 */ { SVGA3DOP_TEXCOORD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
285 /* 65 */ { SVGA3DOP_TEXKILL, 1, { PT_DEST, NULL, NULL, NULL } },
286 /* 66 */ { SVGA3DOP_TEX, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } }, // pre-1.4 = tex dest, post-1.4 = texld dest, src, src
287 /* 67 */ { SVGA3DOP_TEXBEM, 2, { PT_DEST, PT_SRC, NULL, NULL } },
288 /* 68 */ { SVGA3DOP_TEXBEML, 2, { PT_DEST, PT_SRC, NULL, NULL } },
289 /* 69 */ { SVGA3DOP_TEXREG2AR, 2, { PT_DEST, PT_SRC, NULL, NULL } },
290 /* 70 */ { SVGA3DOP_TEXREG2GB, 2, { PT_DEST, PT_SRC, NULL, NULL } },
291 /* 71 */ { SVGA3DOP_TEXM3x2PAD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
292 /* 72 */ { SVGA3DOP_TEXM3x2TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
293 /* 73 */ { SVGA3DOP_TEXM3x3PAD, 2, { PT_DEST, PT_SRC, NULL, NULL } },
294 /* 74 */ { SVGA3DOP_TEXM3x3TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
295 /* 75 */ { SVGA3DOP_RESERVED0, 0, { NULL, NULL, NULL, NULL } },
296 /* 76 */ { SVGA3DOP_TEXM3x3SPEC, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
297 /* 77 */ { SVGA3DOP_TEXM3x3VSPEC, 2, { PT_DEST, PT_SRC, NULL, NULL } },
298 /* 78 */ { SVGA3DOP_EXPP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
299 /* 79 */ { SVGA3DOP_LOGP, 2, { PT_DEST, PT_SRC, NULL, NULL } },
300 /* 80 */ { SVGA3DOP_CND, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
301 /* 81 */ { SVGA3DOP_DEF, 5, { PT_DEST, NULL, NULL, NULL } },
302 /* 82 */ { SVGA3DOP_TEXREG2RGB, 2, { PT_DEST, PT_SRC, NULL, NULL } },
303 /* 83 */ { SVGA3DOP_TEXDP3TEX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
304 /* 84 */ { SVGA3DOP_TEXM3x2DEPTH, 2, { PT_DEST, PT_SRC, NULL, NULL } },
305 /* 85 */ { SVGA3DOP_TEXDP3, 2, { PT_DEST, PT_SRC, NULL, NULL } },
306 /* 86 */ { SVGA3DOP_TEXM3x3, 2, { PT_DEST, PT_SRC, NULL, NULL } },
307 /* 87 */ { SVGA3DOP_TEXDEPTH, 1, { PT_DEST, NULL, NULL, NULL } },
308 /* 88 */ { SVGA3DOP_CMP, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
309 /* 89 */ { SVGA3DOP_BEM, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
310 /* 90 */ { SVGA3DOP_DP2ADD, 4, { PT_DEST, PT_SRC, PT_SRC, PT_SRC } },
311 /* 91 */ { SVGA3DOP_DSX, 2, { PT_DEST, PT_SRC, NULL, NULL } },
312 /* 92 */ { SVGA3DOP_DSY, 2, { PT_DEST, PT_SRC, NULL, NULL } },
313 /* 93 */ { SVGA3DOP_TEXLDD, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
314 /* 94 */ { SVGA3DOP_SETP, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
315 /* 95 */ { SVGA3DOP_TEXLDL, 3, { PT_DEST, PT_SRC, PT_SRC, NULL } },
316 /* 96 */ { SVGA3DOP_BREAKP, 1, { PT_SRC, NULL, NULL, NULL } },
317};
318
319#undef PT_DCL
320#undef PT_LBL
321#undef PT_DEST
322#undef PT_SRC
323
324/* Parse the shader code
325 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/shader-code-format
326 */
327int vmsvga3dShaderParse(SVGA3dShaderType type, uint32_t cbShaderData, uint32_t* pShaderData)
328{
329 uint32_t *paTokensStart = (uint32_t*)pShaderData;
330 uint32_t const cTokens = cbShaderData / sizeof(uint32_t);
331
332 ASSERT_GUEST_RETURN(cTokens * sizeof(uint32_t) == cbShaderData, VERR_INVALID_PARAMETER);
333
334 /* Need at least the version token and SVGA3DOP_END instruction token. 48KB is an arbitrary limit. */
335 ASSERT_GUEST_RETURN(cTokens >= 2 && cTokens < (48 * _1K) / sizeof(paTokensStart[0]), VERR_INVALID_PARAMETER);
336
337#ifdef LOG_ENABLED
338 Log3(("Shader code:\n"));
339 const uint32_t cTokensPerLine = 8;
340 for (uint32_t iToken = 0; iToken < cTokens; ++iToken)
341 {
342 if ((iToken % cTokensPerLine) == 0)
343 {
344 if (iToken == 0)
345 Log3(("0x%08X,", paTokensStart[iToken]));
346 else
347 Log3(("\n0x%08X,", paTokensStart[iToken]));
348 }
349 else
350 Log3((" 0x%08X,", paTokensStart[iToken]));
351 }
352 Log3(("\n"));
353#endif
354
355 VMSVGA3DSHADERPARSECONTEXT ctx;
356 RT_ZERO(ctx);
357
358 /* "The first token must be a version token." */
359 ctx.version = *(SVGA3dShaderVersion*)paTokensStart;
360 ASSERT_GUEST_RETURN(ctx.version.type == SVGA3D_VS_TYPE
361 || ctx.version.type == SVGA3D_PS_TYPE, VERR_PARSE_ERROR);
362 /* A vertex shader should not be defined with a pixel shader bytecode (and visa versa)*/
363 ASSERT_GUEST_RETURN((ctx.version.type == SVGA3D_VS_TYPE && type == SVGA3D_SHADERTYPE_VS)
364 || (ctx.version.type == SVGA3D_PS_TYPE && type == SVGA3D_SHADERTYPE_PS), VERR_PARSE_ERROR);
365 ASSERT_GUEST_RETURN(ctx.version.major >= 2 && ctx.version.major <= 4, VERR_PARSE_ERROR);
366
367 /* Scan the tokens. Immediately return an error code on any unexpected data. */
368 uint32_t *paTokensEnd = &paTokensStart[cTokens];
369 uint32_t *pToken = &paTokensStart[1]; /* Skip the version token. */
370 bool bEndTokenFound = false;
371 while (pToken < paTokensEnd)
372 {
373 SVGA3dShaderInstToken const token = *(SVGA3dShaderInstToken*)pToken;
374
375 /* Figure out the instruction length, which is how many tokens follow the instruction token. */
376 uint32_t const cInstLen = token.op == SVGA3DOP_COMMENT
377 ? token.comment_size
378 : token.size;
379
380 Log3(("op %d, cInstLen %d\n", token.op, cInstLen));
381
382 /* Must not be greater than the number of remaining tokens. */
383 ASSERT_GUEST_RETURN(cInstLen < (uintptr_t)(paTokensEnd - pToken), VERR_PARSE_ERROR);
384
385 /* Stop parsing if this is the SVGA3DOP_END instruction. */
386 if (token.op == SVGA3DOP_END)
387 {
388 ASSERT_GUEST_RETURN(token.value == 0x0000FFFF, VERR_PARSE_ERROR);
389 bEndTokenFound = true;
390 break;
391 }
392
393 ctx.currentOpcode = (SVGA3dShaderOpCodeType)token.op;
394
395 /* If this instrution is in the aOps table. */
396 if (token.op <= SVGA3DOP_BREAKP)
397 {
398 VMSVGA3DSHADERPARSEOP const* pOp = &aOps[token.op];
399
400 if (ctx.currentOpcode == SVGA3DOP_DCL)
401 ctx.u.pDclArgs = (SVGA3DOpDclArgs *)&pToken[1];
402
403 /* cInstLen can be greater than pOp->Length.
404 * W10 guest sends a vertex shader MUL instruction with length 4.
405 * So figure out the actual number of valid parameters.
406 */
407 uint32_t const cParams = RT_MIN(cInstLen, pOp->Length);
408
409 /* Parse paramater tokens. */
410 uint32_t i;
411 for (i = 0; i < RT_MIN(cParams, RT_ELEMENTS(pOp->apfnParse)); ++i)
412 {
413 if (!pOp->apfnParse[i])
414 continue;
415
416 int rc = pOp->apfnParse[i](&ctx, token.op, pToken[i + 1], i);
417 if (RT_FAILURE(rc))
418 return rc;
419 }
420 }
421 else if (token.op == SVGA3DOP_PHASE
422 || token.op == SVGA3DOP_COMMENT)
423 {
424 }
425 else
426 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
427
428 /* Next token. */
429 pToken += cInstLen + 1;
430 }
431
432 if (!bEndTokenFound)
433 {
434 ASSERT_GUEST_FAILED_RETURN(VERR_PARSE_ERROR);
435 }
436
437 return VINF_SUCCESS;
438}
439
440void vmsvga3dShaderLogRel(char const *pszMsg, SVGA3dShaderType type, uint32_t cbShaderData, uint32_t const *pShaderData)
441{
442 /* Dump the shader code. */
443 static int scLogged = 0;
444 if (scLogged < 8)
445 {
446 ++scLogged;
447
448 LogRel(("VMSVGA: %s shader: %s:\n", (type == SVGA3D_SHADERTYPE_VS) ? "VERTEX" : "PIXEL", pszMsg));
449 const uint32_t cTokensPerLine = 8;
450 const uint32_t *paTokens = (uint32_t *)pShaderData;
451 const uint32_t cTokens = cbShaderData / sizeof(uint32_t);
452 for (uint32_t iToken = 0; iToken < cTokens; ++iToken)
453 {
454 if ((iToken % cTokensPerLine) == 0)
455 {
456 if (iToken == 0)
457 LogRel(("0x%08X,", paTokens[iToken]));
458 else
459 LogRel(("\n0x%08X,", paTokens[iToken]));
460 }
461 else
462 LogRel((" 0x%08X,", paTokens[iToken]));
463 }
464 LogRel(("\n"));
465 }
466}
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