VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-dx.cpp@ 103914

Last change on this file since 103914 was 102808, checked in by vboxsync, 9 months ago

Devices/Graphics: multisampling.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 185.3 KB
Line 
1/* $Id: DevVGA-SVGA3d-dx.cpp 102808 2024-01-10 08:16:30Z vboxsync $ */
2/** @file
3 * DevSVGA3d - VMWare SVGA device, 3D parts - Common code for DX backend interface.
4 */
5
6/*
7 * Copyright (C) 2020-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
33#include <VBox/AssertGuest.h>
34#include <iprt/errcore.h>
35#include <VBox/log.h>
36#include <VBox/vmm/pdmdev.h>
37
38#include <iprt/assert.h>
39#include <iprt/mem.h>
40
41#include <VBoxVideo.h> /* required by DevVGA.h */
42
43/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
44#include "DevVGA.h"
45
46#include "DevVGA-SVGA.h"
47#include "DevVGA-SVGA3d.h"
48#include "DevVGA-SVGA3d-internal.h"
49#include "DevVGA-SVGA-internal.h"
50
51
52/*
53 * Helpers.
54 */
55
56static int dxMobWrite(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid, uint32_t off, void const *pvData, uint32_t cbData)
57{
58 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, mobid);
59 ASSERT_GUEST_RETURN(pMob, VERR_INVALID_STATE);
60
61 return vmsvgaR3MobWrite(pSvgaR3State, pMob, off, pvData, cbData);
62}
63
64void vmsvga3dDXInitContextMobData(SVGADXContextMobFormat *p)
65{
66 /* 0xFFFFFFFF (SVGA_ID_INVALID) is a better initial value than 0 for most of svgaDXContext fields. */
67 memset(p, 0xFF, sizeof(*p));
68
69 p->inputAssembly.layoutId = SVGA3D_INVALID_ID;
70 for (uint32_t i = 0; i < RT_ELEMENTS(p->inputAssembly.vertexBuffers); ++i)
71 {
72 p->inputAssembly.vertexBuffers[i].bufferId = SVGA3D_INVALID_ID;
73 p->inputAssembly.vertexBuffers[i].stride = 0;
74 p->inputAssembly.vertexBuffers[i].offset = 0;
75 }
76 p->inputAssembly.indexBufferSid = SVGA3D_INVALID_ID;
77 p->inputAssembly.indexBufferOffset = 0;
78 p->inputAssembly.indexBufferFormat = SVGA3D_FORMAT_INVALID;
79 p->inputAssembly.topology = SVGA3D_PRIMITIVE_INVALID;
80
81 p->renderState.blendStateId = SVGA3D_INVALID_ID;
82 RT_ZERO(p->renderState.blendFactor);
83 p->renderState.sampleMask = 0;
84 p->renderState.depthStencilStateId = SVGA3D_INVALID_ID;
85 p->renderState.stencilRef = 0;
86 p->renderState.rasterizerStateId = SVGA3D_INVALID_ID;
87 p->renderState.depthStencilViewId = SVGA3D_INVALID_ID;
88 for (uint32_t i = 0; i < RT_ELEMENTS(p->renderState.renderTargetViewIds); ++i)
89 p->renderState.renderTargetViewIds[i] = SVGA3D_INVALID_ID;
90
91 for (uint32_t i = 0; i < RT_ELEMENTS(p->streamOut.targets); ++i)
92 p->streamOut.targets[i] = SVGA3D_INVALID_ID;
93 p->streamOut.soid = SVGA3D_INVALID_ID;
94
95 p->uavSpliceIndex = 0;
96 p->numViewports = 0;
97 p->numScissorRects = 0;
98
99 RT_ZERO(p->viewports);
100 RT_ZERO(p->scissorRects);
101
102 p->predication.queryID = SVGA3D_INVALID_ID;
103 p->predication.value = 0;
104
105 p->shaderIfaceMobid = SVGA3D_INVALID_ID;
106 p->shaderIfaceOffset = 0;
107
108 for (uint32_t i = 0; i < RT_ELEMENTS(p->shaderState); ++i)
109 {
110 p->shaderState[i].shaderId = SVGA3D_INVALID_ID;
111 for (uint32_t j = 0; j < RT_ELEMENTS(p->shaderState[0].constantBuffers); ++j)
112 {
113 SVGA3dConstantBufferBinding *cbb = &p->shaderState[i].constantBuffers[j];
114 cbb->sid = SVGA3D_INVALID_ID;
115 cbb->offsetInBytes = 0;
116 cbb->sizeInBytes = 0;
117 }
118 for (uint32_t j = 0; j < RT_ELEMENTS(p->shaderState[0].shaderResources); ++j)
119 p->shaderState[i].shaderResources[j] = SVGA3D_INVALID_ID;
120 for (uint32_t j = 0; j < RT_ELEMENTS(p->shaderState[0].samplers); ++j)
121 p->shaderState[i].samplers[j] = SVGA3D_INVALID_ID;
122 }
123
124 for (uint32_t i = 0; i < RT_ELEMENTS(p->queryID); ++i)
125 p->queryID[i] = SVGA3D_INVALID_ID;
126
127 for (uint32_t i = 0; i < RT_ELEMENTS(p->cotables); ++i)
128 p->cotables[i].mobid = SVGA3D_INVALID_ID;
129
130 for (uint32_t i = 0; i < RT_ELEMENTS(p->uaViewIds); ++i)
131 p->uaViewIds[i] = SVGA3D_INVALID_ID;
132
133 for (uint32_t i = 0; i < RT_ELEMENTS(p->csuaViewIds); ++i)
134 p->csuaViewIds[i] = SVGA3D_INVALID_ID;
135}
136
137/*
138 *
139 * Command handlers.
140 *
141 */
142
143int vmsvga3dDXUnbindContext(PVGASTATECC pThisCC, uint32_t cid, SVGADXContextMobFormat *pSvgaDXContext)
144{
145 int rc;
146 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
147 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBindContext, VERR_INVALID_STATE);
148 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
149 AssertReturn(p3dState, VERR_INVALID_STATE);
150
151 PVMSVGA3DDXCONTEXT pDXContext;
152 rc = vmsvga3dDXContextFromCid(p3dState, cid, &pDXContext);
153 AssertRCReturn(rc, rc);
154
155 /* Copy the host structure back to the guest memory. */
156 memcpy(pSvgaDXContext, &pDXContext->svgaDXContext, sizeof(*pSvgaDXContext));
157
158 return rc;
159}
160
161
162int vmsvga3dDXSwitchContext(PVGASTATECC pThisCC, uint32_t cid)
163{
164 int rc;
165 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
166 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSwitchContext, VERR_INVALID_STATE);
167 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
168 AssertReturn(p3dState, VERR_INVALID_STATE);
169
170 PVMSVGA3DDXCONTEXT pDXContext;
171 rc = vmsvga3dDXContextFromCid(p3dState, cid, &pDXContext);
172 AssertRCReturn(rc, rc);
173
174 /* Notify the host backend that context is about to be switched. */
175 rc = pSvgaR3State->pFuncsDX->pfnDXSwitchContext(pThisCC, pDXContext);
176 if (rc == VINF_NOT_IMPLEMENTED || RT_FAILURE(rc))
177 return rc;
178
179 /** @todo Keep track of changes in the pipeline and apply only modified state. */
180 /* It is not necessary to restore SVGADXContextMobFormat::shaderState::shaderResources
181 * because they are applied by the backend before each Draw call.
182 */
183 #define DX_STATE_SAMPLERS 0x00000004
184 #define DX_STATE_INPUTLAYOUT 0x00000008
185 #define DX_STATE_TOPOLOGY 0x00000010
186 #define DX_STATE_BLENDSTATE 0x00000080
187 #define DX_STATE_DEPTHSTENCILSTATE 0x00000100
188 #define DX_STATE_SOTARGETS 0x00000200
189 #define DX_STATE_VIEWPORTS 0x00000400
190 #define DX_STATE_SCISSORRECTS 0x00000800
191 #define DX_STATE_RASTERIZERSTATE 0x00001000
192 uint32_t u32TrackedState = 0
193 | DX_STATE_SAMPLERS
194 | DX_STATE_INPUTLAYOUT
195 | DX_STATE_TOPOLOGY
196 | DX_STATE_BLENDSTATE
197 | DX_STATE_DEPTHSTENCILSTATE
198 | DX_STATE_SOTARGETS
199 | DX_STATE_VIEWPORTS
200 | DX_STATE_SCISSORRECTS
201 | DX_STATE_RASTERIZERSTATE
202 ;
203
204 LogFunc(("cid = %d, state = 0x%08X\n", cid, u32TrackedState));
205
206 if (u32TrackedState & DX_STATE_SAMPLERS)
207 {
208 u32TrackedState &= ~DX_STATE_SAMPLERS;
209
210 for (int i = SVGA3D_SHADERTYPE_MIN; i < SVGA3D_SHADERTYPE_MAX; ++i)
211 {
212 SVGA3dShaderType const shaderType = (SVGA3dShaderType)i;
213 uint32_t const idxShaderState = shaderType - SVGA3D_SHADERTYPE_MIN;
214
215 uint32_t startSampler = 0;
216 uint32_t cSamplerId = SVGA3D_DX_MAX_SAMPLERS;
217 SVGA3dSamplerId *paSamplerId = &pDXContext->svgaDXContext.shaderState[idxShaderState].samplers[0];
218
219 rc = pSvgaR3State->pFuncsDX->pfnDXSetSamplers(pThisCC, pDXContext, startSampler, shaderType, cSamplerId, paSamplerId);
220 AssertRC(rc);
221 }
222 }
223
224
225 if (u32TrackedState & DX_STATE_INPUTLAYOUT)
226 {
227 u32TrackedState &= ~DX_STATE_INPUTLAYOUT;
228
229 SVGA3dElementLayoutId const elementLayoutId = pDXContext->svgaDXContext.inputAssembly.layoutId;
230
231 rc = pSvgaR3State->pFuncsDX->pfnDXSetInputLayout(pThisCC, pDXContext, elementLayoutId);
232 AssertRC(rc);
233 }
234
235
236 if (u32TrackedState & DX_STATE_TOPOLOGY)
237 {
238 u32TrackedState &= ~DX_STATE_TOPOLOGY;
239
240 SVGA3dPrimitiveType const topology = (SVGA3dPrimitiveType)pDXContext->svgaDXContext.inputAssembly.topology;
241
242 if (topology != SVGA3D_PRIMITIVE_INVALID)
243 rc = pSvgaR3State->pFuncsDX->pfnDXSetTopology(pThisCC, pDXContext, topology);
244 AssertRC(rc);
245 }
246
247
248 if (u32TrackedState & DX_STATE_BLENDSTATE)
249 {
250 u32TrackedState &= ~DX_STATE_BLENDSTATE;
251
252 SVGA3dBlendStateId const blendId = pDXContext->svgaDXContext.renderState.blendStateId;
253 /* SVGADXContextMobFormat uses uint32_t array to store the blend factors, however they are in fact 32 bit floats. */
254 float const *paBlendFactor = (float *)&pDXContext->svgaDXContext.renderState.blendFactor[0];
255 uint32_t const sampleMask = pDXContext->svgaDXContext.renderState.sampleMask;
256
257 rc = pSvgaR3State->pFuncsDX->pfnDXSetBlendState(pThisCC, pDXContext, blendId, paBlendFactor, sampleMask);
258 AssertRC(rc);
259 }
260
261
262 if (u32TrackedState & DX_STATE_DEPTHSTENCILSTATE)
263 {
264 u32TrackedState &= ~DX_STATE_DEPTHSTENCILSTATE;
265
266 SVGA3dDepthStencilStateId const depthStencilId = pDXContext->svgaDXContext.renderState.depthStencilStateId;
267 uint32_t const stencilRef = pDXContext->svgaDXContext.renderState.stencilRef;
268
269 rc = pSvgaR3State->pFuncsDX->pfnDXSetDepthStencilState(pThisCC, pDXContext, depthStencilId, stencilRef);
270 AssertRC(rc);
271 }
272
273
274 if (u32TrackedState & DX_STATE_SOTARGETS)
275 {
276 u32TrackedState &= ~DX_STATE_SOTARGETS;
277
278 uint32_t cSoTarget = SVGA3D_DX_MAX_SOTARGETS;
279 SVGA3dSoTarget aSoTarget[SVGA3D_DX_MAX_SOTARGETS];
280 for (uint32_t i = 0; i < SVGA3D_DX_MAX_SOTARGETS; ++i)
281 {
282 aSoTarget[i].sid = pDXContext->svgaDXContext.streamOut.targets[i];
283 /** @todo Offset is not stored in svgaDXContext. Should it be stored elsewhere by the host? */
284 aSoTarget[i].offset = 0;
285 aSoTarget[i].sizeInBytes = 0;
286 }
287
288 rc = pSvgaR3State->pFuncsDX->pfnDXSetSOTargets(pThisCC, pDXContext, cSoTarget, aSoTarget);
289 AssertRC(rc);
290 }
291
292
293 if (u32TrackedState & DX_STATE_VIEWPORTS)
294 {
295 u32TrackedState &= ~DX_STATE_VIEWPORTS;
296
297 uint32_t const cViewport = pDXContext->svgaDXContext.numViewports;
298 SVGA3dViewport const *paViewport = &pDXContext->svgaDXContext.viewports[0];
299
300 rc = pSvgaR3State->pFuncsDX->pfnDXSetViewports(pThisCC, pDXContext, cViewport, paViewport);
301 AssertRC(rc);
302 }
303
304
305 if (u32TrackedState & DX_STATE_SCISSORRECTS)
306 {
307 u32TrackedState &= ~DX_STATE_SCISSORRECTS;
308
309 uint32_t const cRect = pDXContext->svgaDXContext.numScissorRects;
310 SVGASignedRect const *paRect = &pDXContext->svgaDXContext.scissorRects[0];
311
312 rc = pSvgaR3State->pFuncsDX->pfnDXSetScissorRects(pThisCC, pDXContext, cRect, paRect);
313 AssertRC(rc);
314 }
315
316
317 if (u32TrackedState & DX_STATE_RASTERIZERSTATE)
318 {
319 u32TrackedState &= ~DX_STATE_RASTERIZERSTATE;
320
321 SVGA3dRasterizerStateId const rasterizerId = pDXContext->svgaDXContext.renderState.rasterizerStateId;
322
323 rc = pSvgaR3State->pFuncsDX->pfnDXSetRasterizerState(pThisCC, pDXContext, rasterizerId);
324 AssertRC(rc);
325 }
326
327 Assert(u32TrackedState == 0);
328
329 return rc;
330}
331
332
333/**
334 * Create a new 3D DX context.
335 *
336 * @returns VBox status code.
337 * @param pThisCC The VGA/VMSVGA state for ring-3.
338 * @param cid Context id to be created.
339 */
340int vmsvga3dDXDefineContext(PVGASTATECC pThisCC, uint32_t cid)
341{
342 int rc;
343 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
344 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineContext, VERR_INVALID_STATE);
345 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
346 AssertReturn(p3dState, VERR_INVALID_STATE);
347
348 PVMSVGA3DDXCONTEXT pDXContext;
349
350 LogFunc(("cid %d\n", cid));
351
352 AssertReturn(cid < SVGA3D_MAX_CONTEXT_IDS, VERR_INVALID_PARAMETER);
353
354 if (cid >= p3dState->cDXContexts)
355 {
356 /* Grow the array. */
357 uint32_t cNew = RT_ALIGN(cid + 15, 16);
358 void *pvNew = RTMemRealloc(p3dState->papDXContexts, sizeof(p3dState->papDXContexts[0]) * cNew);
359 AssertReturn(pvNew, VERR_NO_MEMORY);
360 p3dState->papDXContexts = (PVMSVGA3DDXCONTEXT *)pvNew;
361 while (p3dState->cDXContexts < cNew)
362 {
363 pDXContext = (PVMSVGA3DDXCONTEXT)RTMemAllocZ(sizeof(*pDXContext));
364 AssertReturn(pDXContext, VERR_NO_MEMORY);
365 pDXContext->cid = SVGA3D_INVALID_ID;
366 p3dState->papDXContexts[p3dState->cDXContexts++] = pDXContext;
367 }
368 }
369 /* If one already exists with this id, then destroy it now. */
370 if (p3dState->papDXContexts[cid]->cid != SVGA3D_INVALID_ID)
371 vmsvga3dDXDestroyContext(pThisCC, cid);
372
373 pDXContext = p3dState->papDXContexts[cid];
374 memset(pDXContext, 0, sizeof(*pDXContext));
375
376 vmsvga3dDXInitContextMobData(&pDXContext->svgaDXContext);
377 pDXContext->cid = cid;
378
379 /* Init the backend specific data. */
380 rc = pSvgaR3State->pFuncsDX->pfnDXDefineContext(pThisCC, pDXContext);
381
382 /* Cleanup on failure. */
383 if (RT_FAILURE(rc))
384 vmsvga3dDXDestroyContext(pThisCC, cid);
385
386 return rc;
387}
388
389
390int vmsvga3dDXDestroyContext(PVGASTATECC pThisCC, uint32_t cid)
391{
392 int rc;
393 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
394 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyContext, VERR_INVALID_STATE);
395 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
396 AssertReturn(p3dState, VERR_INVALID_STATE);
397
398 PVMSVGA3DDXCONTEXT pDXContext;
399 rc = vmsvga3dDXContextFromCid(p3dState, cid, &pDXContext);
400 AssertRCReturn(rc, rc);
401
402 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyContext(pThisCC, pDXContext);
403
404 RT_ZERO(*pDXContext);
405 pDXContext->cid = SVGA3D_INVALID_ID;
406
407 return rc;
408}
409
410
411int vmsvga3dDXBindContext(PVGASTATECC pThisCC, uint32_t cid, SVGADXContextMobFormat *pSvgaDXContext)
412{
413 int rc;
414 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
415 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBindContext, VERR_INVALID_STATE);
416 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
417 AssertReturn(p3dState, VERR_INVALID_STATE);
418
419 PVMSVGA3DDXCONTEXT pDXContext;
420 rc = vmsvga3dDXContextFromCid(p3dState, cid, &pDXContext);
421 AssertRCReturn(rc, rc);
422
423 if (pSvgaDXContext)
424 memcpy(&pDXContext->svgaDXContext, pSvgaDXContext, sizeof(*pSvgaDXContext));
425
426 rc = pSvgaR3State->pFuncsDX->pfnDXBindContext(pThisCC, pDXContext);
427 return rc;
428}
429
430
431int vmsvga3dDXReadbackContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGADXContextMobFormat *pSvgaDXContext)
432{
433 int rc;
434 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
435 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXReadbackContext, VERR_INVALID_STATE);
436 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
437 AssertReturn(p3dState, VERR_INVALID_STATE);
438
439 PVMSVGA3DDXCONTEXT pDXContext;
440 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
441 AssertRCReturn(rc, rc);
442
443 rc = pSvgaR3State->pFuncsDX->pfnDXReadbackContext(pThisCC, pDXContext);
444 if (RT_SUCCESS(rc))
445 memcpy(pSvgaDXContext, &pDXContext->svgaDXContext, sizeof(*pSvgaDXContext));
446 return rc;
447}
448
449
450int vmsvga3dDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext)
451{
452 int rc;
453 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
454 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXInvalidateContext, VERR_INVALID_STATE);
455 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
456 AssertReturn(p3dState, VERR_INVALID_STATE);
457
458 PVMSVGA3DDXCONTEXT pDXContext;
459 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
460 AssertRCReturn(rc, rc);
461
462 rc = pSvgaR3State->pFuncsDX->pfnDXInvalidateContext(pThisCC, pDXContext);
463 return rc;
464}
465
466
467int vmsvga3dDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd)
468{
469 int rc;
470 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
471 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetSingleConstantBuffer, VERR_INVALID_STATE);
472 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
473 AssertReturn(p3dState, VERR_INVALID_STATE);
474
475 PVMSVGA3DDXCONTEXT pDXContext;
476 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
477 AssertRCReturn(rc, rc);
478
479 ASSERT_GUEST_RETURN(pCmd->slot < SVGA3D_DX_MAX_CONSTBUFFERS, VERR_INVALID_PARAMETER);
480 ASSERT_GUEST_RETURN(pCmd->type >= SVGA3D_SHADERTYPE_MIN && pCmd->type < SVGA3D_SHADERTYPE_MAX, VERR_INVALID_PARAMETER);
481 RT_UNTRUSTED_VALIDATED_FENCE();
482
483 uint32_t const idxShaderState = pCmd->type - SVGA3D_SHADERTYPE_MIN;
484 SVGA3dConstantBufferBinding *pCBB = &pDXContext->svgaDXContext.shaderState[idxShaderState].constantBuffers[pCmd->slot];
485 pCBB->sid = pCmd->sid;
486 pCBB->offsetInBytes = pCmd->offsetInBytes;
487 pCBB->sizeInBytes = pCmd->sizeInBytes;
488
489 rc = pSvgaR3State->pFuncsDX->pfnDXSetSingleConstantBuffer(pThisCC, pDXContext, pCmd->slot, pCmd->type, pCmd->sid, pCmd->offsetInBytes, pCmd->sizeInBytes);
490 return rc;
491}
492
493
494int vmsvga3dDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cShaderResourceViewId, SVGA3dShaderResourceViewId const *paShaderResourceViewId)
495{
496 int rc;
497 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
498 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetShaderResources, VERR_INVALID_STATE);
499 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
500 AssertReturn(p3dState, VERR_INVALID_STATE);
501
502 PVMSVGA3DDXCONTEXT pDXContext;
503 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
504 AssertRCReturn(rc, rc);
505
506 ASSERT_GUEST_RETURN(pCmd->startView < SVGA3D_DX_MAX_SRVIEWS, VERR_INVALID_PARAMETER);
507 ASSERT_GUEST_RETURN(cShaderResourceViewId <= SVGA3D_DX_MAX_SRVIEWS - pCmd->startView, VERR_INVALID_PARAMETER);
508 ASSERT_GUEST_RETURN(pCmd->type >= SVGA3D_SHADERTYPE_MIN && pCmd->type < SVGA3D_SHADERTYPE_MAX, VERR_INVALID_PARAMETER);
509 for (uint32_t i = 0; i < cShaderResourceViewId; ++i)
510 ASSERT_GUEST_RETURN( paShaderResourceViewId[i] < pDXContext->cot.cSRView
511 || paShaderResourceViewId[i] == SVGA3D_INVALID_ID, VERR_INVALID_PARAMETER);
512 RT_UNTRUSTED_VALIDATED_FENCE();
513
514 uint32_t const idxShaderState = pCmd->type - SVGA3D_SHADERTYPE_MIN;
515 for (uint32_t i = 0; i < cShaderResourceViewId; ++i)
516 {
517 SVGA3dShaderResourceViewId const shaderResourceViewId = paShaderResourceViewId[i];
518 pDXContext->svgaDXContext.shaderState[idxShaderState].shaderResources[pCmd->startView + i] = shaderResourceViewId;
519 }
520
521 rc = pSvgaR3State->pFuncsDX->pfnDXSetShaderResources(pThisCC, pDXContext, pCmd->startView, pCmd->type, cShaderResourceViewId, paShaderResourceViewId);
522 return rc;
523}
524
525
526int vmsvga3dDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd)
527{
528 int rc;
529 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
530 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetShader, VERR_INVALID_STATE);
531 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
532 AssertReturn(p3dState, VERR_INVALID_STATE);
533
534 PVMSVGA3DDXCONTEXT pDXContext;
535 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
536 AssertRCReturn(rc, rc);
537
538 ASSERT_GUEST_RETURN( pCmd->shaderId < pDXContext->cot.cShader
539 || pCmd->shaderId == SVGA_ID_INVALID, VERR_INVALID_PARAMETER);
540 ASSERT_GUEST_RETURN(pCmd->type >= SVGA3D_SHADERTYPE_MIN && pCmd->type < SVGA3D_SHADERTYPE_MAX, VERR_INVALID_PARAMETER);
541 RT_UNTRUSTED_VALIDATED_FENCE();
542
543 uint32_t const idxShaderState = pCmd->type - SVGA3D_SHADERTYPE_MIN;
544 pDXContext->svgaDXContext.shaderState[idxShaderState].shaderId = pCmd->shaderId;
545
546 rc = pSvgaR3State->pFuncsDX->pfnDXSetShader(pThisCC, pDXContext, pCmd->shaderId, pCmd->type);
547 return rc;
548}
549
550
551int vmsvga3dDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cSamplerId, SVGA3dSamplerId const *paSamplerId)
552{
553 int rc;
554 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
555 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetSamplers, VERR_INVALID_STATE);
556 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
557 AssertReturn(p3dState, VERR_INVALID_STATE);
558
559 PVMSVGA3DDXCONTEXT pDXContext;
560 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
561 AssertRCReturn(rc, rc);
562
563 ASSERT_GUEST_RETURN(pCmd->startSampler < SVGA3D_DX_MAX_SAMPLERS, VERR_INVALID_PARAMETER);
564 ASSERT_GUEST_RETURN(cSamplerId <= SVGA3D_DX_MAX_SAMPLERS - pCmd->startSampler, VERR_INVALID_PARAMETER);
565 ASSERT_GUEST_RETURN(pCmd->type >= SVGA3D_SHADERTYPE_MIN && pCmd->type < SVGA3D_SHADERTYPE_MAX, VERR_INVALID_PARAMETER);
566 RT_UNTRUSTED_VALIDATED_FENCE();
567
568 uint32_t const idxShaderState = pCmd->type - SVGA3D_SHADERTYPE_MIN;
569 for (uint32_t i = 0; i < cSamplerId; ++i)
570 {
571 SVGA3dSamplerId const samplerId = paSamplerId[i];
572 ASSERT_GUEST_RETURN( samplerId < pDXContext->cot.cSampler
573 || samplerId == SVGA_ID_INVALID, VERR_INVALID_PARAMETER);
574 pDXContext->svgaDXContext.shaderState[idxShaderState].samplers[pCmd->startSampler + i] = samplerId;
575 }
576 RT_UNTRUSTED_VALIDATED_FENCE();
577
578 rc = pSvgaR3State->pFuncsDX->pfnDXSetSamplers(pThisCC, pDXContext, pCmd->startSampler, pCmd->type, cSamplerId, paSamplerId);
579 return rc;
580}
581
582
583#ifdef DUMP_BITMAPS
584static void vmsvga3dDXDrawDumpRenderTargets(PVGASTATECC pThisCC, PVMSVGA3DDXCONTEXT pDXContext, const char *pszPrefix = NULL)
585{
586 for (uint32_t i = 0; i < SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS; ++i)
587 {
588 if (pDXContext->svgaDXContext.renderState.renderTargetViewIds[i] != SVGA3D_INVALID_ID)
589 {
590 SVGACOTableDXRTViewEntry *pRTViewEntry = &pDXContext->cot.paRTView[pDXContext->svgaDXContext.renderState.renderTargetViewIds[i]];
591 Log(("Dump RT[%u] sid = %u rtvid = %u\n", i, pRTViewEntry->sid, pDXContext->svgaDXContext.renderState.renderTargetViewIds[i]));
592
593 SVGA3dSurfaceImageId image;
594 image.sid = pRTViewEntry->sid;
595 image.face = 0;
596 image.mipmap = 0;
597 VMSVGA3D_MAPPED_SURFACE map;
598 int rc = vmsvga3dSurfaceMap(pThisCC, &image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
599 if (RT_SUCCESS(rc))
600 {
601 vmsvga3dMapWriteBmpFile(&map, pszPrefix ? pszPrefix : "rt-");
602 vmsvga3dSurfaceUnmap(pThisCC, &image, &map, /* fWritten = */ false);
603 }
604 else
605 Log(("Map failed %Rrc\n", rc));
606 }
607 }
608}
609#endif
610
611int vmsvga3dDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd)
612{
613 int rc;
614 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
615 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDraw, VERR_INVALID_STATE);
616 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
617 AssertReturn(p3dState, VERR_INVALID_STATE);
618
619 PVMSVGA3DDXCONTEXT pDXContext;
620 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
621 AssertRCReturn(rc, rc);
622
623 rc = pSvgaR3State->pFuncsDX->pfnDXDraw(pThisCC, pDXContext, pCmd->vertexCount, pCmd->startVertexLocation);
624#ifdef DUMP_BITMAPS
625 vmsvga3dDXDrawDumpRenderTargets(pThisCC, pDXContext);
626#endif
627 return rc;
628}
629
630
631int vmsvga3dDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd)
632{
633 int rc;
634 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
635 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDrawIndexed, VERR_INVALID_STATE);
636 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
637 AssertReturn(p3dState, VERR_INVALID_STATE);
638
639 PVMSVGA3DDXCONTEXT pDXContext;
640 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
641 AssertRCReturn(rc, rc);
642
643 rc = pSvgaR3State->pFuncsDX->pfnDXDrawIndexed(pThisCC, pDXContext, pCmd->indexCount, pCmd->startIndexLocation, pCmd->baseVertexLocation);
644#ifdef DUMP_BITMAPS
645 vmsvga3dDXDrawDumpRenderTargets(pThisCC, pDXContext);
646#endif
647 return rc;
648}
649
650
651int vmsvga3dDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd)
652{
653 int rc;
654 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
655 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDrawInstanced, VERR_INVALID_STATE);
656 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
657 AssertReturn(p3dState, VERR_INVALID_STATE);
658
659 PVMSVGA3DDXCONTEXT pDXContext;
660 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
661 AssertRCReturn(rc, rc);
662
663 rc = pSvgaR3State->pFuncsDX->pfnDXDrawInstanced(pThisCC, pDXContext,
664 pCmd->vertexCountPerInstance, pCmd->instanceCount, pCmd->startVertexLocation, pCmd->startInstanceLocation);
665#ifdef DUMP_BITMAPS
666 vmsvga3dDXDrawDumpRenderTargets(pThisCC, pDXContext);
667#endif
668 return rc;
669}
670
671
672int vmsvga3dDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd)
673{
674 int rc;
675 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
676 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstanced, VERR_INVALID_STATE);
677 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
678 AssertReturn(p3dState, VERR_INVALID_STATE);
679
680 PVMSVGA3DDXCONTEXT pDXContext;
681 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
682 AssertRCReturn(rc, rc);
683
684 rc = pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstanced(pThisCC, pDXContext,
685 pCmd->indexCountPerInstance, pCmd->instanceCount, pCmd->startIndexLocation, pCmd->baseVertexLocation, pCmd->startInstanceLocation);
686#ifdef DUMP_BITMAPS
687 vmsvga3dDXDrawDumpRenderTargets(pThisCC, pDXContext);
688#endif
689 return rc;
690}
691
692
693int vmsvga3dDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext)
694{
695 int rc;
696 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
697 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDrawAuto, VERR_INVALID_STATE);
698 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
699 AssertReturn(p3dState, VERR_INVALID_STATE);
700
701 PVMSVGA3DDXCONTEXT pDXContext;
702 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
703 AssertRCReturn(rc, rc);
704
705 rc = pSvgaR3State->pFuncsDX->pfnDXDrawAuto(pThisCC, pDXContext);
706#ifdef DUMP_BITMAPS
707 vmsvga3dDXDrawDumpRenderTargets(pThisCC, pDXContext);
708#endif
709 return rc;
710}
711
712
713int vmsvga3dDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dElementLayoutId elementLayoutId)
714{
715 int rc;
716 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
717 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetInputLayout, VERR_INVALID_STATE);
718 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
719 AssertReturn(p3dState, VERR_INVALID_STATE);
720
721 PVMSVGA3DDXCONTEXT pDXContext;
722 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
723 AssertRCReturn(rc, rc);
724
725 ASSERT_GUEST_RETURN( elementLayoutId == SVGA3D_INVALID_ID
726 || elementLayoutId < pDXContext->cot.cElementLayout, VERR_INVALID_PARAMETER);
727 RT_UNTRUSTED_VALIDATED_FENCE();
728
729 pDXContext->svgaDXContext.inputAssembly.layoutId = elementLayoutId;
730
731 rc = pSvgaR3State->pFuncsDX->pfnDXSetInputLayout(pThisCC, pDXContext, elementLayoutId);
732 return rc;
733}
734
735
736int vmsvga3dDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, uint32_t startBuffer, uint32_t cVertexBuffer, SVGA3dVertexBuffer const *paVertexBuffer)
737{
738 int rc;
739 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
740 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetVertexBuffers, VERR_INVALID_STATE);
741 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
742 AssertReturn(p3dState, VERR_INVALID_STATE);
743
744 PVMSVGA3DDXCONTEXT pDXContext;
745 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
746 AssertRCReturn(rc, rc);
747
748 ASSERT_GUEST_RETURN(startBuffer < SVGA3D_DX_MAX_VERTEXBUFFERS, VERR_INVALID_PARAMETER);
749 ASSERT_GUEST_RETURN(cVertexBuffer <= SVGA3D_DX_MAX_VERTEXBUFFERS - startBuffer, VERR_INVALID_PARAMETER);
750 RT_UNTRUSTED_VALIDATED_FENCE();
751
752 for (uint32_t i = 0; i < cVertexBuffer; ++i)
753 {
754 uint32_t const idxVertexBuffer = startBuffer + i;
755
756 pDXContext->svgaDXContext.inputAssembly.vertexBuffers[idxVertexBuffer].bufferId = paVertexBuffer[i].sid;
757 pDXContext->svgaDXContext.inputAssembly.vertexBuffers[idxVertexBuffer].stride = paVertexBuffer[i].stride;
758 pDXContext->svgaDXContext.inputAssembly.vertexBuffers[idxVertexBuffer].offset = paVertexBuffer[i].offset;
759 }
760
761 rc = pSvgaR3State->pFuncsDX->pfnDXSetVertexBuffers(pThisCC, pDXContext, startBuffer, cVertexBuffer, paVertexBuffer);
762 return rc;
763}
764
765
766int vmsvga3dDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd)
767{
768 int rc;
769 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
770 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetIndexBuffer, VERR_INVALID_STATE);
771 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
772 AssertReturn(p3dState, VERR_INVALID_STATE);
773
774 PVMSVGA3DDXCONTEXT pDXContext;
775 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
776 AssertRCReturn(rc, rc);
777
778 pDXContext->svgaDXContext.inputAssembly.indexBufferSid = pCmd->sid;
779 pDXContext->svgaDXContext.inputAssembly.indexBufferOffset = pCmd->offset;
780 pDXContext->svgaDXContext.inputAssembly.indexBufferFormat = pCmd->format;
781
782 rc = pSvgaR3State->pFuncsDX->pfnDXSetIndexBuffer(pThisCC, pDXContext, pCmd->sid, pCmd->format, pCmd->offset);
783 return rc;
784}
785
786
787int vmsvga3dDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dPrimitiveType topology)
788{
789 int rc;
790 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
791 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetTopology, VERR_INVALID_STATE);
792 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
793 AssertReturn(p3dState, VERR_INVALID_STATE);
794
795 PVMSVGA3DDXCONTEXT pDXContext;
796 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
797 AssertRCReturn(rc, rc);
798
799 ASSERT_GUEST_RETURN(topology >= SVGA3D_PRIMITIVE_MIN && topology < SVGA3D_PRIMITIVE_MAX, VERR_INVALID_PARAMETER);
800
801 pDXContext->svgaDXContext.inputAssembly.topology = topology;
802
803 rc = pSvgaR3State->pFuncsDX->pfnDXSetTopology(pThisCC, pDXContext, topology);
804 return rc;
805}
806
807
808int vmsvga3dDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dDepthStencilViewId depthStencilViewId, uint32_t cRenderTargetViewId, SVGA3dRenderTargetViewId const *paRenderTargetViewId)
809{
810 int rc;
811 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
812 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetRenderTargets, VERR_INVALID_STATE);
813 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
814 AssertReturn(p3dState, VERR_INVALID_STATE);
815
816 PVMSVGA3DDXCONTEXT pDXContext;
817 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
818 AssertRCReturn(rc, rc);
819
820 ASSERT_GUEST_RETURN( depthStencilViewId < pDXContext->cot.cDSView
821 || depthStencilViewId == SVGA_ID_INVALID, VERR_INVALID_PARAMETER);
822 ASSERT_GUEST_RETURN(cRenderTargetViewId <= SVGA3D_MAX_RENDER_TARGETS, VERR_INVALID_PARAMETER);
823 for (uint32_t i = 0; i < cRenderTargetViewId; ++i)
824 ASSERT_GUEST_RETURN( paRenderTargetViewId[i] < pDXContext->cot.cRTView
825 || paRenderTargetViewId[i] == SVGA_ID_INVALID, VERR_INVALID_PARAMETER);
826 RT_UNTRUSTED_VALIDATED_FENCE();
827
828 pDXContext->svgaDXContext.renderState.depthStencilViewId = depthStencilViewId;
829 for (uint32_t i = 0; i < cRenderTargetViewId; ++i)
830 pDXContext->svgaDXContext.renderState.renderTargetViewIds[i] = paRenderTargetViewId[i];
831
832 /* Remember how many render target slots must be set. */
833 pDXContext->cRenderTargets = RT_MAX(pDXContext->cRenderTargets, cRenderTargetViewId);
834
835 rc = pSvgaR3State->pFuncsDX->pfnDXSetRenderTargets(pThisCC, pDXContext, depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
836 return rc;
837}
838
839
840int vmsvga3dDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd)
841{
842 int rc;
843 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
844 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetBlendState, VERR_INVALID_STATE);
845 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
846 AssertReturn(p3dState, VERR_INVALID_STATE);
847
848 PVMSVGA3DDXCONTEXT pDXContext;
849 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
850 AssertRCReturn(rc, rc);
851
852 SVGA3dBlendStateId const blendId = pCmd->blendId;
853
854 ASSERT_GUEST_RETURN( blendId == SVGA3D_INVALID_ID
855 || blendId < pDXContext->cot.cBlendState, VERR_INVALID_PARAMETER);
856 RT_UNTRUSTED_VALIDATED_FENCE();
857
858 pDXContext->svgaDXContext.renderState.blendStateId = blendId;
859 /* SVGADXContextMobFormat uses uint32_t array to store the blend factors, however they are in fact 32 bit floats. */
860 memcpy(pDXContext->svgaDXContext.renderState.blendFactor, pCmd->blendFactor, sizeof(pDXContext->svgaDXContext.renderState.blendFactor));
861 pDXContext->svgaDXContext.renderState.sampleMask = pCmd->sampleMask;
862
863 rc = pSvgaR3State->pFuncsDX->pfnDXSetBlendState(pThisCC, pDXContext, blendId, pCmd->blendFactor, pCmd->sampleMask);
864 return rc;
865}
866
867
868int vmsvga3dDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd)
869{
870 int rc;
871 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
872 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetDepthStencilState, VERR_INVALID_STATE);
873 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
874 AssertReturn(p3dState, VERR_INVALID_STATE);
875
876 PVMSVGA3DDXCONTEXT pDXContext;
877 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
878 AssertRCReturn(rc, rc);
879
880 SVGA3dDepthStencilStateId const depthStencilId = pCmd->depthStencilId;
881
882 ASSERT_GUEST_RETURN( depthStencilId == SVGA3D_INVALID_ID
883 || depthStencilId < pDXContext->cot.cDepthStencil, VERR_INVALID_PARAMETER);
884 RT_UNTRUSTED_VALIDATED_FENCE();
885
886 pDXContext->svgaDXContext.renderState.depthStencilStateId = depthStencilId;
887 pDXContext->svgaDXContext.renderState.stencilRef = pCmd->stencilRef;
888
889 rc = pSvgaR3State->pFuncsDX->pfnDXSetDepthStencilState(pThisCC, pDXContext, depthStencilId, pCmd->stencilRef);
890 return rc;
891}
892
893
894int vmsvga3dDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dRasterizerStateId rasterizerId)
895{
896 int rc;
897 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
898 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetRasterizerState, VERR_INVALID_STATE);
899 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
900 AssertReturn(p3dState, VERR_INVALID_STATE);
901
902 PVMSVGA3DDXCONTEXT pDXContext;
903 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
904 AssertRCReturn(rc, rc);
905
906 ASSERT_GUEST_RETURN( rasterizerId == SVGA3D_INVALID_ID
907 || rasterizerId < pDXContext->cot.cRasterizerState, VERR_INVALID_PARAMETER);
908 RT_UNTRUSTED_VALIDATED_FENCE();
909
910 pDXContext->svgaDXContext.renderState.rasterizerStateId = rasterizerId;
911
912 rc = pSvgaR3State->pFuncsDX->pfnDXSetRasterizerState(pThisCC, pDXContext, rasterizerId);
913 return rc;
914}
915
916
917int vmsvga3dDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd)
918{
919 int rc;
920 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
921 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineQuery, VERR_INVALID_STATE);
922 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
923 AssertReturn(p3dState, VERR_INVALID_STATE);
924
925 PVMSVGA3DDXCONTEXT pDXContext;
926 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
927 AssertRCReturn(rc, rc);
928
929 SVGA3dQueryId const queryId = pCmd->queryId;
930
931 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
932 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
933 ASSERT_GUEST_RETURN(pCmd->type >= SVGA3D_QUERYTYPE_MIN && pCmd->type < SVGA3D_QUERYTYPE_MAX, VERR_INVALID_PARAMETER);
934 RT_UNTRUSTED_VALIDATED_FENCE();
935
936 /* Cleanup the current query. */
937 pSvgaR3State->pFuncsDX->pfnDXDestroyQuery(pThisCC, pDXContext, queryId);
938
939 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[queryId];
940 pEntry->type = pCmd->type;
941 pEntry->state = SVGADX_QDSTATE_IDLE;
942 pEntry->flags = pCmd->flags;
943 pEntry->mobid = SVGA_ID_INVALID;
944 pEntry->offset = 0;
945
946 rc = pSvgaR3State->pFuncsDX->pfnDXDefineQuery(pThisCC, pDXContext, queryId, pEntry);
947 return rc;
948}
949
950
951int vmsvga3dDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd)
952{
953 int rc;
954 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
955 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyQuery, VERR_INVALID_STATE);
956 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
957 AssertReturn(p3dState, VERR_INVALID_STATE);
958
959 PVMSVGA3DDXCONTEXT pDXContext;
960 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
961 AssertRCReturn(rc, rc);
962
963 SVGA3dQueryId const queryId = pCmd->queryId;
964
965 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
966 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
967 RT_UNTRUSTED_VALIDATED_FENCE();
968
969 pSvgaR3State->pFuncsDX->pfnDXDestroyQuery(pThisCC, pDXContext, queryId);
970
971 /* Cleanup COTable entry.*/
972 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[queryId];
973 pEntry->type = SVGA3D_QUERYTYPE_INVALID;
974 pEntry->state = SVGADX_QDSTATE_INVALID;
975 pEntry->flags = 0;
976 pEntry->mobid = SVGA_ID_INVALID;
977 pEntry->offset = 0;
978
979 return rc;
980}
981
982
983int vmsvga3dDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, PVMSVGAMOB pMob)
984{
985 int rc;
986 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
987 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
988 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
989 AssertReturn(p3dState, VERR_INVALID_STATE);
990
991 PVMSVGA3DDXCONTEXT pDXContext;
992 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
993 AssertRCReturn(rc, rc);
994
995 SVGA3dQueryId const queryId = pCmd->queryId;
996
997 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
998 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
999 RT_UNTRUSTED_VALIDATED_FENCE();
1000
1001 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[queryId];
1002 pEntry->mobid = vmsvgaR3MobId(pMob);
1003
1004 return rc;
1005}
1006
1007
1008int vmsvga3dDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd)
1009{
1010 int rc;
1011 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1012 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
1013 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1014 AssertReturn(p3dState, VERR_INVALID_STATE);
1015
1016 PVMSVGA3DDXCONTEXT pDXContext;
1017 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1018 AssertRCReturn(rc, rc);
1019
1020 SVGA3dQueryId const queryId = pCmd->queryId;
1021
1022 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
1023 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
1024 RT_UNTRUSTED_VALIDATED_FENCE();
1025
1026 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[queryId];
1027 pEntry->offset = pCmd->mobOffset;
1028
1029 return rc;
1030}
1031
1032
1033int vmsvga3dDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd)
1034{
1035 int rc;
1036 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1037 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBeginQuery, VERR_INVALID_STATE);
1038 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1039 AssertReturn(p3dState, VERR_INVALID_STATE);
1040
1041 PVMSVGA3DDXCONTEXT pDXContext;
1042 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1043 AssertRCReturn(rc, rc);
1044
1045 SVGA3dQueryId const queryId = pCmd->queryId;
1046
1047 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
1048 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
1049 RT_UNTRUSTED_VALIDATED_FENCE();
1050
1051 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[queryId];
1052 Assert(pEntry->state == SVGADX_QDSTATE_IDLE || pEntry->state == SVGADX_QDSTATE_PENDING || pEntry->state == SVGADX_QDSTATE_FINISHED);
1053 if (pEntry->state != SVGADX_QDSTATE_ACTIVE)
1054 {
1055 rc = pSvgaR3State->pFuncsDX->pfnDXBeginQuery(pThisCC, pDXContext, queryId);
1056 if (RT_SUCCESS(rc))
1057 {
1058 pEntry->state = SVGADX_QDSTATE_ACTIVE;
1059
1060 /* Update the guest status of the query. */
1061 uint32_t const u32 = SVGA3D_QUERYSTATE_PENDING;
1062 dxMobWrite(pSvgaR3State, pEntry->mobid, pEntry->offset, &u32, sizeof(u32));
1063 }
1064 else
1065 {
1066 uint32_t const u32 = SVGA3D_QUERYSTATE_FAILED;
1067 dxMobWrite(pSvgaR3State, pEntry->mobid, pEntry->offset, &u32, sizeof(u32));
1068 }
1069 }
1070 return rc;
1071}
1072
1073
1074static int dxEndQuery(PVGASTATECC pThisCC, PVMSVGA3DDXCONTEXT pDXContext, SVGA3dQueryId queryId, SVGACOTableDXQueryEntry *pEntry)
1075{
1076 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1077
1078 int rc = VINF_SUCCESS;
1079 if (pEntry->state == SVGADX_QDSTATE_ACTIVE || pEntry->state == SVGADX_QDSTATE_IDLE)
1080 {
1081 pEntry->state = SVGADX_QDSTATE_PENDING;
1082
1083 uint32_t u32QueryState;
1084 SVGADXQueryResultUnion queryResult;
1085 uint32_t cbQuery = 0; /* Actual size of query data returned by backend. */
1086 rc = pSvgaR3State->pFuncsDX->pfnDXEndQuery(pThisCC, pDXContext, queryId, &queryResult, &cbQuery);
1087 if (RT_SUCCESS(rc))
1088 {
1089 /* Write the result after SVGA3dQueryState. */
1090 dxMobWrite(pSvgaR3State, pEntry->mobid, pEntry->offset + sizeof(uint32_t), &queryResult, cbQuery);
1091
1092 u32QueryState = SVGA3D_QUERYSTATE_SUCCEEDED;
1093 }
1094 else
1095 u32QueryState = SVGA3D_QUERYSTATE_FAILED;
1096
1097 dxMobWrite(pSvgaR3State, pEntry->mobid, pEntry->offset, &u32QueryState, sizeof(u32QueryState));
1098
1099 if (RT_SUCCESS(rc))
1100 pEntry->state = SVGADX_QDSTATE_FINISHED;
1101 }
1102 else
1103 AssertStmt(pEntry->state == SVGADX_QDSTATE_FINISHED, rc = VERR_INVALID_STATE);
1104
1105 return rc;
1106}
1107
1108
1109int vmsvga3dDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd)
1110{
1111 int rc;
1112 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1113 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXEndQuery, VERR_INVALID_STATE);
1114 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1115 AssertReturn(p3dState, VERR_INVALID_STATE);
1116
1117 PVMSVGA3DDXCONTEXT pDXContext;
1118 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1119 AssertRCReturn(rc, rc);
1120
1121 SVGA3dQueryId const queryId = pCmd->queryId;
1122
1123 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
1124 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
1125 RT_UNTRUSTED_VALIDATED_FENCE();
1126
1127 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[queryId];
1128 rc = dxEndQuery(pThisCC, pDXContext, queryId, pEntry);
1129 return rc;
1130}
1131
1132
1133int vmsvga3dDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd)
1134{
1135 int rc;
1136 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1137 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
1138 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1139 AssertReturn(p3dState, VERR_INVALID_STATE);
1140
1141 PVMSVGA3DDXCONTEXT pDXContext;
1142 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1143 AssertRCReturn(rc, rc);
1144
1145 SVGA3dQueryId const queryId = pCmd->queryId;
1146
1147 ASSERT_GUEST_RETURN(pDXContext->cot.paQuery, VERR_INVALID_STATE);
1148 ASSERT_GUEST_RETURN(queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
1149 RT_UNTRUSTED_VALIDATED_FENCE();
1150
1151 /* The device does not cache queries. So this is a NOP. */
1152
1153 return rc;
1154}
1155
1156
1157int vmsvga3dDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd)
1158{
1159 int rc;
1160 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1161 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetPredication, VERR_INVALID_STATE);
1162 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1163 AssertReturn(p3dState, VERR_INVALID_STATE);
1164
1165 PVMSVGA3DDXCONTEXT pDXContext;
1166 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1167 AssertRCReturn(rc, rc);
1168
1169 SVGA3dQueryId const queryId = pCmd->queryId;
1170
1171 ASSERT_GUEST_RETURN( queryId == SVGA3D_INVALID_ID
1172 || queryId < pDXContext->cot.cQuery, VERR_INVALID_PARAMETER);
1173 RT_UNTRUSTED_VALIDATED_FENCE();
1174
1175 pDXContext->svgaDXContext.predication.queryID = queryId;
1176 pDXContext->svgaDXContext.predication.value = pCmd->predicateValue;
1177
1178 rc = pSvgaR3State->pFuncsDX->pfnDXSetPredication(pThisCC, pDXContext, queryId, pCmd->predicateValue);
1179 return rc;
1180}
1181
1182
1183int vmsvga3dDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, uint32_t cSoTarget, SVGA3dSoTarget const *paSoTarget)
1184{
1185 int rc;
1186 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1187 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetSOTargets, VERR_INVALID_STATE);
1188 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1189 AssertReturn(p3dState, VERR_INVALID_STATE);
1190
1191 PVMSVGA3DDXCONTEXT pDXContext;
1192 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1193 AssertRCReturn(rc, rc);
1194
1195 ASSERT_GUEST_RETURN(cSoTarget <= SVGA3D_DX_MAX_SOTARGETS, VERR_INVALID_PARAMETER);
1196 RT_UNTRUSTED_VALIDATED_FENCE();
1197
1198 /** @todo Offset is not stored in svgaDXContext. Should it be stored elsewhere? */
1199 for (uint32_t i = 0; i < SVGA3D_DX_MAX_SOTARGETS; ++i)
1200 pDXContext->svgaDXContext.streamOut.targets[i] = i < cSoTarget ? paSoTarget[i].sid : SVGA3D_INVALID_ID;
1201
1202 rc = pSvgaR3State->pFuncsDX->pfnDXSetSOTargets(pThisCC, pDXContext, cSoTarget, paSoTarget);
1203 return rc;
1204}
1205
1206
1207int vmsvga3dDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, uint32_t cViewport, SVGA3dViewport const *paViewport)
1208{
1209 int rc;
1210 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1211 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetViewports, VERR_INVALID_STATE);
1212 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1213 AssertReturn(p3dState, VERR_INVALID_STATE);
1214
1215 PVMSVGA3DDXCONTEXT pDXContext;
1216 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1217 AssertRCReturn(rc, rc);
1218
1219 ASSERT_GUEST_RETURN(cViewport <= SVGA3D_DX_MAX_VIEWPORTS, VERR_INVALID_PARAMETER);
1220 RT_UNTRUSTED_VALIDATED_FENCE();
1221
1222 pDXContext->svgaDXContext.numViewports = (uint8_t)cViewport;
1223 for (uint32_t i = 0; i < cViewport; ++i)
1224 pDXContext->svgaDXContext.viewports[i] = paViewport[i];
1225
1226 rc = pSvgaR3State->pFuncsDX->pfnDXSetViewports(pThisCC, pDXContext, cViewport, paViewport);
1227 return rc;
1228}
1229
1230
1231int vmsvga3dDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, uint32_t cRect, SVGASignedRect const *paRect)
1232{
1233 int rc;
1234 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1235 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetScissorRects, VERR_INVALID_STATE);
1236 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1237 AssertReturn(p3dState, VERR_INVALID_STATE);
1238
1239 PVMSVGA3DDXCONTEXT pDXContext;
1240 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1241 AssertRCReturn(rc, rc);
1242
1243 ASSERT_GUEST_RETURN(cRect <= SVGA3D_DX_MAX_SCISSORRECTS, VERR_INVALID_PARAMETER);
1244 RT_UNTRUSTED_VALIDATED_FENCE();
1245
1246 pDXContext->svgaDXContext.numScissorRects = (uint8_t)cRect;
1247 for (uint32_t i = 0; i < cRect; ++i)
1248 pDXContext->svgaDXContext.scissorRects[i] = paRect[i];
1249
1250 rc = pSvgaR3State->pFuncsDX->pfnDXSetScissorRects(pThisCC, pDXContext, cRect, paRect);
1251 return rc;
1252}
1253
1254
1255int vmsvga3dDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd)
1256{
1257 int rc;
1258 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1259 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXClearRenderTargetView, VERR_INVALID_STATE);
1260 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1261 AssertReturn(p3dState, VERR_INVALID_STATE);
1262
1263 PVMSVGA3DDXCONTEXT pDXContext;
1264 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1265 AssertRCReturn(rc, rc);
1266
1267 SVGA3dRenderTargetViewId const renderTargetViewId = pCmd->renderTargetViewId;
1268
1269 ASSERT_GUEST_RETURN(pDXContext->cot.paRTView, VERR_INVALID_STATE);
1270 ASSERT_GUEST_RETURN(renderTargetViewId < pDXContext->cot.cRTView, VERR_INVALID_PARAMETER);
1271 RT_UNTRUSTED_VALIDATED_FENCE();
1272
1273 rc = pSvgaR3State->pFuncsDX->pfnDXClearRenderTargetView(pThisCC, pDXContext, renderTargetViewId, &pCmd->rgba);
1274 return rc;
1275}
1276
1277
1278int vmsvga3dDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd)
1279{
1280 int rc;
1281 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1282 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXClearDepthStencilView, VERR_INVALID_STATE);
1283 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1284 AssertReturn(p3dState, VERR_INVALID_STATE);
1285
1286 PVMSVGA3DDXCONTEXT pDXContext;
1287 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1288 AssertRCReturn(rc, rc);
1289
1290 SVGA3dDepthStencilViewId const depthStencilViewId = pCmd->depthStencilViewId;
1291
1292 ASSERT_GUEST_RETURN(pDXContext->cot.paDSView, VERR_INVALID_STATE);
1293 ASSERT_GUEST_RETURN(depthStencilViewId < pDXContext->cot.cDSView, VERR_INVALID_PARAMETER);
1294 RT_UNTRUSTED_VALIDATED_FENCE();
1295
1296 rc = pSvgaR3State->pFuncsDX->pfnDXClearDepthStencilView(pThisCC, pDXContext, pCmd->flags, depthStencilViewId, pCmd->depth, (uint8_t)pCmd->stencil);
1297 return rc;
1298}
1299
1300
1301int vmsvga3dDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd)
1302{
1303 int rc;
1304 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1305 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXPredCopyRegion, VERR_INVALID_STATE);
1306 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1307 AssertReturn(p3dState, VERR_INVALID_STATE);
1308
1309 PVMSVGA3DDXCONTEXT pDXContext;
1310 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1311 AssertRCReturn(rc, rc);
1312
1313 /** @todo Memcpy if both resources do not have the hardware resource. */
1314
1315 rc = pSvgaR3State->pFuncsDX->pfnDXPredCopyRegion(pThisCC, pDXContext, pCmd->dstSid, pCmd->dstSubResource, pCmd->srcSid, pCmd->srcSubResource, &pCmd->box);
1316 return rc;
1317}
1318
1319
1320int vmsvga3dDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd)
1321{
1322 int rc;
1323 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1324 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXPredCopy, VERR_INVALID_STATE);
1325 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1326 AssertReturn(p3dState, VERR_INVALID_STATE);
1327
1328 PVMSVGA3DDXCONTEXT pDXContext;
1329 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1330 AssertRCReturn(rc, rc);
1331
1332 rc = pSvgaR3State->pFuncsDX->pfnDXPredCopy(pThisCC, pDXContext, pCmd->dstSid, pCmd->srcSid);
1333 return rc;
1334}
1335
1336
1337int vmsvga3dDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd)
1338{
1339 int rc;
1340 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1341 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXPresentBlt, VERR_INVALID_STATE);
1342 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1343 AssertReturn(p3dState, VERR_INVALID_STATE);
1344
1345 PVMSVGA3DDXCONTEXT pDXContext;
1346 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1347 AssertRCReturn(rc, rc);
1348
1349 rc = pSvgaR3State->pFuncsDX->pfnDXPresentBlt(pThisCC, pDXContext,
1350 pCmd->dstSid, pCmd->destSubResource, &pCmd->boxDest,
1351 pCmd->srcSid, pCmd->srcSubResource, &pCmd->boxSrc, pCmd->mode);
1352 return rc;
1353}
1354
1355
1356int vmsvga3dDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd)
1357{
1358 int rc;
1359 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1360 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXGenMips, VERR_INVALID_STATE);
1361 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1362 AssertReturn(p3dState, VERR_INVALID_STATE);
1363
1364 PVMSVGA3DDXCONTEXT pDXContext;
1365 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1366 AssertRCReturn(rc, rc);
1367
1368 SVGA3dShaderResourceViewId const shaderResourceViewId = pCmd->shaderResourceViewId;
1369
1370 ASSERT_GUEST_RETURN(pDXContext->cot.paSRView, VERR_INVALID_STATE);
1371 ASSERT_GUEST_RETURN(shaderResourceViewId < pDXContext->cot.cSRView, VERR_INVALID_PARAMETER);
1372 RT_UNTRUSTED_VALIDATED_FENCE();
1373
1374 rc = pSvgaR3State->pFuncsDX->pfnDXGenMips(pThisCC, pDXContext, shaderResourceViewId);
1375 return rc;
1376}
1377
1378
1379int vmsvga3dDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd)
1380{
1381 int rc;
1382 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1383 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineShaderResourceView, VERR_INVALID_STATE);
1384 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1385 AssertReturn(p3dState, VERR_INVALID_STATE);
1386
1387 PVMSVGA3DDXCONTEXT pDXContext;
1388 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1389 AssertRCReturn(rc, rc);
1390
1391 SVGA3dShaderResourceViewId const shaderResourceViewId = pCmd->shaderResourceViewId;
1392
1393 ASSERT_GUEST_RETURN(pDXContext->cot.paSRView, VERR_INVALID_STATE);
1394 ASSERT_GUEST_RETURN(shaderResourceViewId < pDXContext->cot.cSRView, VERR_INVALID_PARAMETER);
1395 RT_UNTRUSTED_VALIDATED_FENCE();
1396
1397 SVGACOTableDXSRViewEntry *pEntry = &pDXContext->cot.paSRView[shaderResourceViewId];
1398 pEntry->sid = pCmd->sid;
1399 pEntry->format = pCmd->format;
1400 pEntry->resourceDimension = pCmd->resourceDimension;
1401 pEntry->desc = pCmd->desc;
1402
1403 rc = pSvgaR3State->pFuncsDX->pfnDXDefineShaderResourceView(pThisCC, pDXContext, shaderResourceViewId, pEntry);
1404 return rc;
1405}
1406
1407
1408int vmsvga3dDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd)
1409{
1410 int rc;
1411 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1412 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyShaderResourceView, VERR_INVALID_STATE);
1413 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1414 AssertReturn(p3dState, VERR_INVALID_STATE);
1415
1416 PVMSVGA3DDXCONTEXT pDXContext;
1417 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1418 AssertRCReturn(rc, rc);
1419
1420 SVGA3dShaderResourceViewId const shaderResourceViewId = pCmd->shaderResourceViewId;
1421
1422 ASSERT_GUEST_RETURN(pDXContext->cot.paSRView, VERR_INVALID_STATE);
1423 ASSERT_GUEST_RETURN(shaderResourceViewId < pDXContext->cot.cSRView, VERR_INVALID_PARAMETER);
1424 RT_UNTRUSTED_VALIDATED_FENCE();
1425
1426 SVGACOTableDXSRViewEntry *pEntry = &pDXContext->cot.paSRView[shaderResourceViewId];
1427 RT_ZERO(*pEntry);
1428
1429 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyShaderResourceView(pThisCC, pDXContext, shaderResourceViewId);
1430 return rc;
1431}
1432
1433
1434int vmsvga3dDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd)
1435{
1436 int rc;
1437 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1438 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineRenderTargetView, VERR_INVALID_STATE);
1439 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1440 AssertReturn(p3dState, VERR_INVALID_STATE);
1441
1442 PVMSVGA3DDXCONTEXT pDXContext;
1443 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1444 AssertRCReturn(rc, rc);
1445
1446 SVGA3dRenderTargetViewId const renderTargetViewId = pCmd->renderTargetViewId;
1447
1448 ASSERT_GUEST_RETURN(pDXContext->cot.paRTView, VERR_INVALID_STATE);
1449 ASSERT_GUEST_RETURN(renderTargetViewId < pDXContext->cot.cRTView, VERR_INVALID_PARAMETER);
1450 RT_UNTRUSTED_VALIDATED_FENCE();
1451
1452 SVGACOTableDXRTViewEntry *pEntry = &pDXContext->cot.paRTView[renderTargetViewId];
1453 pEntry->sid = pCmd->sid;
1454 pEntry->format = pCmd->format;
1455 pEntry->resourceDimension = pCmd->resourceDimension;
1456 pEntry->desc = pCmd->desc;
1457
1458 rc = pSvgaR3State->pFuncsDX->pfnDXDefineRenderTargetView(pThisCC, pDXContext, renderTargetViewId, pEntry);
1459 return rc;
1460}
1461
1462
1463int vmsvga3dDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd)
1464{
1465 int rc;
1466 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1467 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyRenderTargetView, VERR_INVALID_STATE);
1468 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1469 AssertReturn(p3dState, VERR_INVALID_STATE);
1470
1471 PVMSVGA3DDXCONTEXT pDXContext;
1472 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1473 AssertRCReturn(rc, rc);
1474
1475 SVGA3dRenderTargetViewId const renderTargetViewId = pCmd->renderTargetViewId;
1476
1477 ASSERT_GUEST_RETURN(pDXContext->cot.paRTView, VERR_INVALID_STATE);
1478 ASSERT_GUEST_RETURN(renderTargetViewId < pDXContext->cot.cRTView, VERR_INVALID_PARAMETER);
1479 RT_UNTRUSTED_VALIDATED_FENCE();
1480
1481 SVGACOTableDXRTViewEntry *pEntry = &pDXContext->cot.paRTView[renderTargetViewId];
1482 RT_ZERO(*pEntry);
1483
1484 for (uint32_t i = 0; i < SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS; ++i)
1485 {
1486 if (pDXContext->svgaDXContext.renderState.renderTargetViewIds[i] == renderTargetViewId)
1487 pDXContext->svgaDXContext.renderState.renderTargetViewIds[i] = SVGA_ID_INVALID;
1488 }
1489
1490 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyRenderTargetView(pThisCC, pDXContext, renderTargetViewId);
1491 return rc;
1492}
1493
1494
1495int vmsvga3dDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd)
1496{
1497 int rc;
1498 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1499 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView, VERR_INVALID_STATE);
1500 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1501 AssertReturn(p3dState, VERR_INVALID_STATE);
1502
1503 PVMSVGA3DDXCONTEXT pDXContext;
1504 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1505 AssertRCReturn(rc, rc);
1506
1507 SVGA3dDepthStencilViewId const depthStencilViewId = pCmd->depthStencilViewId;
1508
1509 ASSERT_GUEST_RETURN(pDXContext->cot.paDSView, VERR_INVALID_STATE);
1510 ASSERT_GUEST_RETURN(depthStencilViewId < pDXContext->cot.cDSView, VERR_INVALID_PARAMETER);
1511 RT_UNTRUSTED_VALIDATED_FENCE();
1512
1513 SVGACOTableDXDSViewEntry *pEntry = &pDXContext->cot.paDSView[depthStencilViewId];
1514 pEntry->sid = pCmd->sid;
1515 pEntry->format = pCmd->format;
1516 pEntry->resourceDimension = pCmd->resourceDimension;
1517 pEntry->mipSlice = pCmd->mipSlice;
1518 pEntry->firstArraySlice = pCmd->firstArraySlice;
1519 pEntry->arraySize = pCmd->arraySize;
1520 pEntry->flags = pCmd->flags;
1521
1522 rc = pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilView(pThisCC, pDXContext, depthStencilViewId, pEntry);
1523 return rc;
1524}
1525
1526
1527int vmsvga3dDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd)
1528{
1529 int rc;
1530 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1531 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilView, VERR_INVALID_STATE);
1532 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1533 AssertReturn(p3dState, VERR_INVALID_STATE);
1534
1535 PVMSVGA3DDXCONTEXT pDXContext;
1536 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1537 AssertRCReturn(rc, rc);
1538
1539 SVGA3dDepthStencilViewId const depthStencilViewId = pCmd->depthStencilViewId;
1540
1541 ASSERT_GUEST_RETURN(pDXContext->cot.paDSView, VERR_INVALID_STATE);
1542 ASSERT_GUEST_RETURN(depthStencilViewId < pDXContext->cot.cDSView, VERR_INVALID_PARAMETER);
1543 RT_UNTRUSTED_VALIDATED_FENCE();
1544
1545 SVGACOTableDXDSViewEntry *pEntry = &pDXContext->cot.paDSView[depthStencilViewId];
1546 RT_ZERO(*pEntry);
1547
1548 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilView(pThisCC, pDXContext, depthStencilViewId);
1549 return rc;
1550}
1551
1552
1553int vmsvga3dDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dElementLayoutId elementLayoutId, uint32_t cDesc, SVGA3dInputElementDesc const *paDesc)
1554{
1555 int rc;
1556 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1557 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineElementLayout, VERR_INVALID_STATE);
1558 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1559 AssertReturn(p3dState, VERR_INVALID_STATE);
1560
1561 PVMSVGA3DDXCONTEXT pDXContext;
1562 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1563 AssertRCReturn(rc, rc);
1564
1565 ASSERT_GUEST_RETURN(pDXContext->cot.paElementLayout, VERR_INVALID_STATE);
1566 ASSERT_GUEST_RETURN(elementLayoutId < pDXContext->cot.cElementLayout, VERR_INVALID_PARAMETER);
1567 RT_UNTRUSTED_VALIDATED_FENCE();
1568
1569 SVGACOTableDXElementLayoutEntry *pEntry = &pDXContext->cot.paElementLayout[elementLayoutId];
1570 pEntry->elid = elementLayoutId;
1571 pEntry->numDescs = RT_MIN(cDesc, RT_ELEMENTS(pEntry->descs));
1572 memcpy(pEntry->descs, paDesc, pEntry->numDescs * sizeof(pEntry->descs[0]));
1573
1574#ifdef LOG_ENABLED
1575 Log6(("Element layout %d: slot off fmt class step reg\n", pEntry->elid));
1576 for (uint32_t i = 0; i < pEntry->numDescs; ++i)
1577 {
1578 Log6((" [%u]: %u 0x%02X %d %u %u %u\n",
1579 i,
1580 pEntry->descs[i].inputSlot,
1581 pEntry->descs[i].alignedByteOffset,
1582 pEntry->descs[i].format,
1583 pEntry->descs[i].inputSlotClass,
1584 pEntry->descs[i].instanceDataStepRate,
1585 pEntry->descs[i].inputRegister
1586 ));
1587 }
1588#endif
1589
1590 rc = pSvgaR3State->pFuncsDX->pfnDXDefineElementLayout(pThisCC, pDXContext, elementLayoutId, pEntry);
1591 return rc;
1592}
1593
1594
1595int vmsvga3dDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd)
1596{
1597 int rc;
1598 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1599 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyElementLayout, VERR_INVALID_STATE);
1600 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1601 AssertReturn(p3dState, VERR_INVALID_STATE);
1602
1603 PVMSVGA3DDXCONTEXT pDXContext;
1604 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1605 AssertRCReturn(rc, rc);
1606
1607 SVGA3dElementLayoutId const elementLayoutId = pCmd->elementLayoutId;
1608
1609 ASSERT_GUEST_RETURN(pDXContext->cot.paElementLayout, VERR_INVALID_STATE);
1610 ASSERT_GUEST_RETURN(elementLayoutId < pDXContext->cot.cElementLayout, VERR_INVALID_PARAMETER);
1611 RT_UNTRUSTED_VALIDATED_FENCE();
1612
1613 pSvgaR3State->pFuncsDX->pfnDXDestroyElementLayout(pThisCC, pDXContext, elementLayoutId);
1614
1615 SVGACOTableDXElementLayoutEntry *pEntry = &pDXContext->cot.paElementLayout[elementLayoutId];
1616 RT_ZERO(*pEntry);
1617 pEntry->elid = SVGA3D_INVALID_ID;
1618
1619 return rc;
1620}
1621
1622
1623int vmsvga3dDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd)
1624{
1625 int rc;
1626 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1627 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineBlendState, VERR_INVALID_STATE);
1628 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1629 AssertReturn(p3dState, VERR_INVALID_STATE);
1630
1631 PVMSVGA3DDXCONTEXT pDXContext;
1632 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1633 AssertRCReturn(rc, rc);
1634
1635 SVGA3dBlendStateId const blendId = pCmd->blendId;
1636
1637 ASSERT_GUEST_RETURN(pDXContext->cot.paBlendState, VERR_INVALID_STATE);
1638 ASSERT_GUEST_RETURN(blendId < pDXContext->cot.cBlendState, VERR_INVALID_PARAMETER);
1639 RT_UNTRUSTED_VALIDATED_FENCE();
1640
1641 SVGACOTableDXBlendStateEntry *pEntry = &pDXContext->cot.paBlendState[blendId];
1642 pEntry->alphaToCoverageEnable = pCmd->alphaToCoverageEnable;
1643 pEntry->independentBlendEnable = pCmd->independentBlendEnable;
1644 memcpy(pEntry->perRT, pCmd->perRT, sizeof(pEntry->perRT));
1645
1646 rc = pSvgaR3State->pFuncsDX->pfnDXDefineBlendState(pThisCC, pDXContext, blendId, pEntry);
1647 return rc;
1648}
1649
1650
1651int vmsvga3dDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd)
1652{
1653 int rc;
1654 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1655 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyBlendState, VERR_INVALID_STATE);
1656 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1657 AssertReturn(p3dState, VERR_INVALID_STATE);
1658
1659 PVMSVGA3DDXCONTEXT pDXContext;
1660 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1661 AssertRCReturn(rc, rc);
1662
1663 SVGA3dBlendStateId const blendId = pCmd->blendId;
1664
1665 ASSERT_GUEST_RETURN(pDXContext->cot.paBlendState, VERR_INVALID_STATE);
1666 ASSERT_GUEST_RETURN(blendId < pDXContext->cot.cBlendState, VERR_INVALID_PARAMETER);
1667 RT_UNTRUSTED_VALIDATED_FENCE();
1668
1669 pSvgaR3State->pFuncsDX->pfnDXDestroyBlendState(pThisCC, pDXContext, blendId);
1670
1671 SVGACOTableDXBlendStateEntry *pEntry = &pDXContext->cot.paBlendState[blendId];
1672 RT_ZERO(*pEntry);
1673
1674 return rc;
1675}
1676
1677
1678int vmsvga3dDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd)
1679{
1680 int rc;
1681 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1682 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilState, VERR_INVALID_STATE);
1683 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1684 AssertReturn(p3dState, VERR_INVALID_STATE);
1685
1686 PVMSVGA3DDXCONTEXT pDXContext;
1687 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1688 AssertRCReturn(rc, rc);
1689
1690 SVGA3dDepthStencilStateId const depthStencilId = pCmd->depthStencilId;
1691
1692 ASSERT_GUEST_RETURN(pDXContext->cot.paDepthStencil, VERR_INVALID_STATE);
1693 ASSERT_GUEST_RETURN(depthStencilId < pDXContext->cot.cDepthStencil, VERR_INVALID_PARAMETER);
1694 RT_UNTRUSTED_VALIDATED_FENCE();
1695
1696 SVGACOTableDXDepthStencilEntry *pEntry = &pDXContext->cot.paDepthStencil[depthStencilId];
1697 pEntry->depthEnable = pCmd->depthEnable;
1698 pEntry->depthWriteMask = pCmd->depthWriteMask;
1699 pEntry->depthFunc = pCmd->depthFunc;
1700 pEntry->stencilEnable = pCmd->stencilEnable;
1701 pEntry->frontEnable = pCmd->frontEnable;
1702 pEntry->backEnable = pCmd->backEnable;
1703 pEntry->stencilReadMask = pCmd->stencilReadMask;
1704 pEntry->stencilWriteMask = pCmd->stencilWriteMask;
1705
1706 pEntry->frontStencilFailOp = pCmd->frontStencilFailOp;
1707 pEntry->frontStencilDepthFailOp = pCmd->frontStencilDepthFailOp;
1708 pEntry->frontStencilPassOp = pCmd->frontStencilPassOp;
1709 pEntry->frontStencilFunc = pCmd->frontStencilFunc;
1710
1711 pEntry->backStencilFailOp = pCmd->backStencilFailOp;
1712 pEntry->backStencilDepthFailOp = pCmd->backStencilDepthFailOp;
1713 pEntry->backStencilPassOp = pCmd->backStencilPassOp;
1714 pEntry->backStencilFunc = pCmd->backStencilFunc;
1715
1716 rc = pSvgaR3State->pFuncsDX->pfnDXDefineDepthStencilState(pThisCC, pDXContext, depthStencilId, pEntry);
1717 return rc;
1718}
1719
1720
1721int vmsvga3dDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd)
1722{
1723 int rc;
1724 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1725 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilState, VERR_INVALID_STATE);
1726 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1727 AssertReturn(p3dState, VERR_INVALID_STATE);
1728
1729 PVMSVGA3DDXCONTEXT pDXContext;
1730 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1731 AssertRCReturn(rc, rc);
1732
1733 SVGA3dDepthStencilStateId const depthStencilId = pCmd->depthStencilId;
1734
1735 ASSERT_GUEST_RETURN(pDXContext->cot.paDepthStencil, VERR_INVALID_STATE);
1736 ASSERT_GUEST_RETURN(depthStencilId < pDXContext->cot.cDepthStencil, VERR_INVALID_PARAMETER);
1737 RT_UNTRUSTED_VALIDATED_FENCE();
1738
1739 pSvgaR3State->pFuncsDX->pfnDXDestroyDepthStencilState(pThisCC, pDXContext, depthStencilId);
1740
1741 SVGACOTableDXDepthStencilEntry *pEntry = &pDXContext->cot.paDepthStencil[depthStencilId];
1742 RT_ZERO(*pEntry);
1743
1744 return rc;
1745}
1746
1747
1748int vmsvga3dDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd)
1749{
1750 int rc;
1751 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1752 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineRasterizerState, VERR_INVALID_STATE);
1753 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1754 AssertReturn(p3dState, VERR_INVALID_STATE);
1755
1756 PVMSVGA3DDXCONTEXT pDXContext;
1757 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1758 AssertRCReturn(rc, rc);
1759
1760 SVGA3dRasterizerStateId const rasterizerId = pCmd->rasterizerId;
1761
1762 ASSERT_GUEST_RETURN(pDXContext->cot.paRasterizerState, VERR_INVALID_STATE);
1763 ASSERT_GUEST_RETURN(rasterizerId < pDXContext->cot.cRasterizerState, VERR_INVALID_PARAMETER);
1764 RT_UNTRUSTED_VALIDATED_FENCE();
1765
1766 SVGACOTableDXRasterizerStateEntry *pEntry = &pDXContext->cot.paRasterizerState[rasterizerId];
1767 pEntry->fillMode = pCmd->fillMode;
1768 pEntry->cullMode = pCmd->cullMode;
1769 pEntry->frontCounterClockwise = pCmd->frontCounterClockwise;
1770 pEntry->provokingVertexLast = pCmd->provokingVertexLast;
1771 pEntry->depthBias = pCmd->depthBias;
1772 pEntry->depthBiasClamp = pCmd->depthBiasClamp;
1773 pEntry->slopeScaledDepthBias = pCmd->slopeScaledDepthBias;
1774 pEntry->depthClipEnable = pCmd->depthClipEnable;
1775 pEntry->scissorEnable = pCmd->scissorEnable;
1776 pEntry->multisampleEnable = pCmd->multisampleEnable;
1777 pEntry->antialiasedLineEnable = pCmd->antialiasedLineEnable;
1778 pEntry->lineWidth = pCmd->lineWidth;
1779 pEntry->lineStippleEnable = pCmd->lineStippleEnable;
1780 pEntry->lineStippleFactor = pCmd->lineStippleFactor;
1781 pEntry->lineStipplePattern = pCmd->lineStipplePattern;
1782 pEntry->forcedSampleCount = 0; /** @todo Not in pCmd. */
1783 RT_ZERO(pEntry->mustBeZero);
1784
1785 rc = pSvgaR3State->pFuncsDX->pfnDXDefineRasterizerState(pThisCC, pDXContext, rasterizerId, pEntry);
1786 return rc;
1787}
1788
1789
1790int vmsvga3dDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd)
1791{
1792 int rc;
1793 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1794 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyRasterizerState, VERR_INVALID_STATE);
1795 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1796 AssertReturn(p3dState, VERR_INVALID_STATE);
1797
1798 PVMSVGA3DDXCONTEXT pDXContext;
1799 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1800 AssertRCReturn(rc, rc);
1801
1802 SVGA3dRasterizerStateId const rasterizerId = pCmd->rasterizerId;
1803
1804 ASSERT_GUEST_RETURN(pDXContext->cot.paRasterizerState, VERR_INVALID_STATE);
1805 ASSERT_GUEST_RETURN(rasterizerId < pDXContext->cot.cRasterizerState, VERR_INVALID_PARAMETER);
1806 RT_UNTRUSTED_VALIDATED_FENCE();
1807
1808 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyRasterizerState(pThisCC, pDXContext, rasterizerId);
1809
1810 SVGACOTableDXRasterizerStateEntry *pEntry = &pDXContext->cot.paRasterizerState[rasterizerId];
1811 RT_ZERO(*pEntry);
1812
1813 return rc;
1814}
1815
1816
1817int vmsvga3dDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd)
1818{
1819 int rc;
1820 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1821 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineSamplerState, VERR_INVALID_STATE);
1822 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1823 AssertReturn(p3dState, VERR_INVALID_STATE);
1824
1825 PVMSVGA3DDXCONTEXT pDXContext;
1826 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1827 AssertRCReturn(rc, rc);
1828
1829 SVGA3dSamplerId const samplerId = pCmd->samplerId;
1830
1831 ASSERT_GUEST_RETURN(pDXContext->cot.paSampler, VERR_INVALID_STATE);
1832 ASSERT_GUEST_RETURN(samplerId < pDXContext->cot.cSampler, VERR_INVALID_PARAMETER);
1833 RT_UNTRUSTED_VALIDATED_FENCE();
1834
1835 SVGACOTableDXSamplerEntry *pEntry = &pDXContext->cot.paSampler[samplerId];
1836 pEntry->filter = pCmd->filter;
1837 pEntry->addressU = pCmd->addressU;
1838 pEntry->addressV = pCmd->addressV;
1839 pEntry->addressW = pCmd->addressW;
1840 pEntry->mipLODBias = pCmd->mipLODBias;
1841 pEntry->maxAnisotropy = pCmd->maxAnisotropy;
1842 pEntry->comparisonFunc = pCmd->comparisonFunc;
1843 pEntry->borderColor = pCmd->borderColor;
1844 pEntry->minLOD = pCmd->minLOD;
1845 pEntry->maxLOD = pCmd->maxLOD;
1846
1847 rc = pSvgaR3State->pFuncsDX->pfnDXDefineSamplerState(pThisCC, pDXContext, samplerId, pEntry);
1848 return rc;
1849}
1850
1851
1852int vmsvga3dDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd)
1853{
1854 int rc;
1855 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1856 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroySamplerState, VERR_INVALID_STATE);
1857 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1858 AssertReturn(p3dState, VERR_INVALID_STATE);
1859
1860 PVMSVGA3DDXCONTEXT pDXContext;
1861 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1862 AssertRCReturn(rc, rc);
1863
1864 SVGA3dSamplerId const samplerId = pCmd->samplerId;
1865
1866 ASSERT_GUEST_RETURN(pDXContext->cot.paSampler, VERR_INVALID_STATE);
1867 ASSERT_GUEST_RETURN(samplerId < pDXContext->cot.cSampler, VERR_INVALID_PARAMETER);
1868 RT_UNTRUSTED_VALIDATED_FENCE();
1869
1870 pSvgaR3State->pFuncsDX->pfnDXDestroySamplerState(pThisCC, pDXContext, samplerId);
1871
1872 SVGACOTableDXSamplerEntry *pEntry = &pDXContext->cot.paSampler[samplerId];
1873 RT_ZERO(*pEntry);
1874
1875 return rc;
1876}
1877
1878
1879int vmsvga3dDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd)
1880{
1881 int rc;
1882 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1883 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineShader, VERR_INVALID_STATE);
1884 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1885 AssertReturn(p3dState, VERR_INVALID_STATE);
1886
1887 PVMSVGA3DDXCONTEXT pDXContext;
1888 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1889 AssertRCReturn(rc, rc);
1890
1891 SVGA3dShaderId const shaderId = pCmd->shaderId;
1892
1893 ASSERT_GUEST_RETURN(pDXContext->cot.paShader, VERR_INVALID_STATE);
1894 ASSERT_GUEST_RETURN(shaderId < pDXContext->cot.cShader, VERR_INVALID_PARAMETER);
1895 ASSERT_GUEST_RETURN(pCmd->type >= SVGA3D_SHADERTYPE_MIN && pCmd->type < SVGA3D_SHADERTYPE_MAX, VERR_INVALID_PARAMETER);
1896 ASSERT_GUEST_RETURN(pCmd->sizeInBytes >= 8, VERR_INVALID_PARAMETER); /* Version Token + Length Token. */
1897 RT_UNTRUSTED_VALIDATED_FENCE();
1898
1899 /* Cleanup the current shader. */
1900 pSvgaR3State->pFuncsDX->pfnDXDestroyShader(pThisCC, pDXContext, shaderId);
1901
1902 SVGACOTableDXShaderEntry *pEntry = &pDXContext->cot.paShader[shaderId];
1903 pEntry->type = pCmd->type;
1904 pEntry->sizeInBytes = pCmd->sizeInBytes;
1905 pEntry->offsetInBytes = 0;
1906 pEntry->mobid = SVGA_ID_INVALID;
1907
1908 rc = pSvgaR3State->pFuncsDX->pfnDXDefineShader(pThisCC, pDXContext, shaderId, pEntry);
1909 return rc;
1910}
1911
1912
1913int vmsvga3dDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd)
1914{
1915 int rc;
1916 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1917 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyShader, VERR_INVALID_STATE);
1918 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
1919 AssertReturn(p3dState, VERR_INVALID_STATE);
1920
1921 PVMSVGA3DDXCONTEXT pDXContext;
1922 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
1923 AssertRCReturn(rc, rc);
1924
1925 SVGA3dShaderId const shaderId = pCmd->shaderId;
1926
1927 ASSERT_GUEST_RETURN(pDXContext->cot.paShader, VERR_INVALID_STATE);
1928 ASSERT_GUEST_RETURN(shaderId < pDXContext->cot.cShader, VERR_INVALID_PARAMETER);
1929 RT_UNTRUSTED_VALIDATED_FENCE();
1930
1931 pSvgaR3State->pFuncsDX->pfnDXDestroyShader(pThisCC, pDXContext, shaderId);
1932
1933 /* Cleanup COTable entries.*/
1934 SVGACOTableDXShaderEntry *pEntry = &pDXContext->cot.paShader[shaderId];
1935 pEntry->type = SVGA3D_SHADERTYPE_INVALID;
1936 pEntry->sizeInBytes = 0;
1937 pEntry->offsetInBytes = 0;
1938 pEntry->mobid = SVGA_ID_INVALID;
1939
1940 /** @todo Destroy shaders on context and backend deletion. */
1941 return rc;
1942}
1943
1944
1945static int dxBindShader(DXShaderInfo *pShaderInfo, PVMSVGAMOB pMob, SVGACOTableDXShaderEntry const *pEntry, void const *pvShaderBytecode)
1946{
1947 /* How many bytes the MOB can hold. */
1948 uint32_t const cbMob = vmsvgaR3MobSize(pMob) - pEntry->offsetInBytes;
1949 ASSERT_GUEST_RETURN(cbMob >= pEntry->sizeInBytes, VERR_INVALID_PARAMETER);
1950 AssertReturn(pEntry->sizeInBytes >= 8, VERR_INTERNAL_ERROR); /* Host ensures this in DefineShader. */
1951
1952 int rc = DXShaderParse(pvShaderBytecode, pEntry->sizeInBytes, pShaderInfo);
1953 if (RT_SUCCESS(rc))
1954 {
1955 /* Get the length of the shader bytecode. */
1956 uint32_t const *pau32Token = (uint32_t *)pvShaderBytecode; /* Tokens */
1957 uint32_t const cToken = pau32Token[1]; /* Length of the shader in tokens. */
1958 ASSERT_GUEST_RETURN(cToken <= pEntry->sizeInBytes / 4, VERR_INVALID_PARAMETER);
1959
1960 /* Check if the shader contains SVGA3dDXSignatureHeader and signature entries after the bytecode.
1961 * If they are not there (Linux guest driver does not provide them), then it is fine
1962 * and the signatures generated by DXShaderParse will be used.
1963 */
1964 uint32_t cbSignaturesAvail = pEntry->sizeInBytes - cToken * 4; /* How many bytes for signatures are available. */
1965 if (cbSignaturesAvail >= sizeof(SVGA3dDXSignatureHeader))
1966 {
1967 cbSignaturesAvail -= sizeof(SVGA3dDXSignatureHeader);
1968
1969 SVGA3dDXSignatureHeader const *pSignatureHeader = (SVGA3dDXSignatureHeader *)((uint8_t *)pvShaderBytecode + cToken * 4);
1970 if (pSignatureHeader->headerVersion == SVGADX_SIGNATURE_HEADER_VERSION_0)
1971 {
1972 ASSERT_GUEST_RETURN( pSignatureHeader->numInputSignatures <= RT_ELEMENTS(pShaderInfo->aInputSignature)
1973 && pSignatureHeader->numOutputSignatures <= RT_ELEMENTS(pShaderInfo->aOutputSignature)
1974 && pSignatureHeader->numPatchConstantSignatures <= RT_ELEMENTS(pShaderInfo->aPatchConstantSignature),
1975 VERR_INVALID_PARAMETER);
1976
1977 uint32_t const cSignature = pSignatureHeader->numInputSignatures
1978 + pSignatureHeader->numOutputSignatures
1979 + pSignatureHeader->numPatchConstantSignatures;
1980 uint32_t const cbSignature = cSignature * sizeof(SVGA3dDXSignatureEntry);
1981 ASSERT_GUEST_RETURN(cbSignaturesAvail >= cbSignature, VERR_INVALID_PARAMETER);
1982
1983 /* The shader does not need guesswork. */
1984 pShaderInfo->fGuestSignatures = true;
1985
1986 /* Copy to DXShaderInfo. */
1987 uint8_t const *pu8Signatures = (uint8_t *)&pSignatureHeader[1];
1988 pShaderInfo->cInputSignature = pSignatureHeader->numInputSignatures;
1989 memcpy(pShaderInfo->aInputSignature, pu8Signatures, pSignatureHeader->numInputSignatures * sizeof(SVGA3dDXSignatureEntry));
1990
1991 pu8Signatures += pSignatureHeader->numInputSignatures * sizeof(SVGA3dDXSignatureEntry);
1992 pShaderInfo->cOutputSignature = pSignatureHeader->numOutputSignatures;
1993 memcpy(pShaderInfo->aOutputSignature, pu8Signatures, pSignatureHeader->numOutputSignatures * sizeof(SVGA3dDXSignatureEntry));
1994
1995 pu8Signatures += pSignatureHeader->numOutputSignatures * sizeof(SVGA3dDXSignatureEntry);
1996 pShaderInfo->cPatchConstantSignature = pSignatureHeader->numPatchConstantSignatures;
1997 memcpy(pShaderInfo->aPatchConstantSignature, pu8Signatures, pSignatureHeader->numPatchConstantSignatures * sizeof(SVGA3dDXSignatureEntry));
1998
1999 /* Sort must be called before GenerateSemantics which assigns attribute indices
2000 * based on the order of attributes.
2001 */
2002 DXShaderSortSignatures(pShaderInfo);
2003 DXShaderGenerateSemantics(pShaderInfo);
2004 }
2005 }
2006 }
2007
2008 return rc;
2009}
2010
2011
2012int vmsvga3dDXBindShader(PVGASTATECC pThisCC, SVGA3dCmdDXBindShader const *pCmd, PVMSVGAMOB pMob)
2013{
2014 int rc;
2015 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2016 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBindShader, VERR_INVALID_STATE);
2017 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2018 AssertReturn(p3dState, VERR_INVALID_STATE);
2019
2020 PVMSVGA3DDXCONTEXT pDXContext;
2021 rc = vmsvga3dDXContextFromCid(p3dState, pCmd->cid, &pDXContext);
2022 AssertRCReturn(rc, rc);
2023
2024 ASSERT_GUEST_RETURN(pCmd->shid < pDXContext->cot.cShader, VERR_INVALID_PARAMETER);
2025 RT_UNTRUSTED_VALIDATED_FENCE();
2026
2027 /* 'type' and 'sizeInBytes' has been already initialized by DefineShader. */
2028 SVGACOTableDXShaderEntry *pEntry = &pDXContext->cot.paShader[pCmd->shid];
2029 //pEntry->type;
2030 //pEntry->sizeInBytes;
2031 pEntry->offsetInBytes = pCmd->offsetInBytes;
2032 pEntry->mobid = vmsvgaR3MobId(pMob);
2033
2034 if (pMob)
2035 {
2036 /* Bind a mob to the shader. */
2037
2038 /* Create a memory pointer for the MOB, which is accessible by host. */
2039 rc = vmsvgaR3MobBackingStoreCreate(pSvgaR3State, pMob, vmsvgaR3MobSize(pMob));
2040 if (RT_SUCCESS(rc))
2041 {
2042 /* Get pointer to the shader bytecode. This will also verify the offset. */
2043 void const *pvShaderBytecode = vmsvgaR3MobBackingStorePtr(pMob, pEntry->offsetInBytes);
2044 ASSERT_GUEST_RETURN(pvShaderBytecode, VERR_INVALID_PARAMETER);
2045
2046 /* Get the shader and optional signatures from the MOB. */
2047 DXShaderInfo shaderInfo;
2048 RT_ZERO(shaderInfo);
2049 rc = dxBindShader(&shaderInfo, pMob, pEntry, pvShaderBytecode);
2050 if (RT_SUCCESS(rc))
2051 {
2052 /* pfnDXBindShader makes a copy of shaderInfo on success. */
2053 rc = pSvgaR3State->pFuncsDX->pfnDXBindShader(pThisCC, pDXContext, pCmd->shid, &shaderInfo);
2054 }
2055 AssertRC(rc);
2056
2057 /** @todo Backing store is not needed anymore in any case? */
2058 if (RT_FAILURE(rc))
2059 {
2060 DXShaderFree(&shaderInfo);
2061
2062 vmsvgaR3MobBackingStoreDelete(pSvgaR3State, pMob);
2063 }
2064 }
2065 }
2066 else
2067 {
2068 /* Unbind. */
2069 /** @todo Nothing to do here but release the MOB? */
2070 vmsvgaR3MobBackingStoreDelete(pSvgaR3State, pMob);
2071 }
2072
2073 return rc;
2074}
2075
2076
2077int vmsvga3dDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd)
2078{
2079 int rc;
2080 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2081 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutput, VERR_INVALID_STATE);
2082 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2083 AssertReturn(p3dState, VERR_INVALID_STATE);
2084
2085 PVMSVGA3DDXCONTEXT pDXContext;
2086 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2087 AssertRCReturn(rc, rc);
2088
2089 SVGA3dStreamOutputId const soid = pCmd->soid;
2090
2091 ASSERT_GUEST_RETURN(pDXContext->cot.paStreamOutput, VERR_INVALID_STATE);
2092 ASSERT_GUEST_RETURN(soid < pDXContext->cot.cStreamOutput, VERR_INVALID_PARAMETER);
2093 ASSERT_GUEST_RETURN(pCmd->numOutputStreamEntries < SVGA3D_MAX_DX10_STREAMOUT_DECLS, VERR_INVALID_PARAMETER);
2094 RT_UNTRUSTED_VALIDATED_FENCE();
2095
2096 SVGACOTableDXStreamOutputEntry *pEntry = &pDXContext->cot.paStreamOutput[soid];
2097 pEntry->numOutputStreamEntries = pCmd->numOutputStreamEntries;
2098 memcpy(pEntry->decl, pCmd->decl, sizeof(pEntry->decl));
2099 memcpy(pEntry->streamOutputStrideInBytes, pCmd->streamOutputStrideInBytes, sizeof(pEntry->streamOutputStrideInBytes));
2100 pEntry->rasterizedStream = 0; // Apparently invalid in this command: pCmd->rasterizedStream;
2101 pEntry->numOutputStreamStrides = 0;
2102 pEntry->mobid = SVGA_ID_INVALID;
2103 pEntry->offsetInBytes = 0;
2104 pEntry->usesMob = 0;
2105 pEntry->pad0 = 0;
2106 pEntry->pad1 = 0;
2107 RT_ZERO(pEntry->pad2);
2108
2109 rc = pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutput(pThisCC, pDXContext, soid, pEntry);
2110 return rc;
2111}
2112
2113
2114int vmsvga3dDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd)
2115{
2116 int rc;
2117 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2118 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyStreamOutput, VERR_INVALID_STATE);
2119 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2120 AssertReturn(p3dState, VERR_INVALID_STATE);
2121
2122 PVMSVGA3DDXCONTEXT pDXContext;
2123 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2124 AssertRCReturn(rc, rc);
2125
2126 SVGA3dStreamOutputId const soid = pCmd->soid;
2127
2128 ASSERT_GUEST_RETURN(pDXContext->cot.paStreamOutput, VERR_INVALID_STATE);
2129 ASSERT_GUEST_RETURN(soid < pDXContext->cot.cStreamOutput, VERR_INVALID_PARAMETER);
2130 RT_UNTRUSTED_VALIDATED_FENCE();
2131
2132 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyStreamOutput(pThisCC, pDXContext, soid);
2133
2134 SVGACOTableDXStreamOutputEntry *pEntry = &pDXContext->cot.paStreamOutput[soid];
2135 RT_ZERO(*pEntry);
2136 pEntry->mobid = SVGA_ID_INVALID;
2137
2138 return rc;
2139}
2140
2141
2142int vmsvga3dDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd)
2143{
2144 int rc;
2145 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2146 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetStreamOutput, VERR_INVALID_STATE);
2147 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2148 AssertReturn(p3dState, VERR_INVALID_STATE);
2149
2150 PVMSVGA3DDXCONTEXT pDXContext;
2151 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2152 AssertRCReturn(rc, rc);
2153
2154 SVGA3dStreamOutputId const soid = pCmd->soid;
2155
2156 ASSERT_GUEST_RETURN( soid == SVGA_ID_INVALID
2157 || soid < pDXContext->cot.cStreamOutput, VERR_INVALID_PARAMETER);
2158 RT_UNTRUSTED_VALIDATED_FENCE();
2159
2160 pDXContext->svgaDXContext.streamOut.soid = soid;
2161
2162 rc = pSvgaR3State->pFuncsDX->pfnDXSetStreamOutput(pThisCC, pDXContext, soid);
2163 return rc;
2164}
2165
2166
2167static int dxSetOrGrowCOTable(PVGASTATECC pThisCC, PVMSVGA3DDXCONTEXT pDXContext, PVMSVGAMOB pMob,
2168 SVGACOTableType enmType, uint32_t validSizeInBytes, bool fGrow)
2169{
2170 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2171 int rc = VINF_SUCCESS;
2172
2173 uint32_t idxCOTable;
2174 if (enmType < SVGA_COTABLE_MAX)
2175 idxCOTable = enmType;
2176 else if (enmType >= VBSVGA_COTABLE_MIN && enmType < VBSVGA_COTABLE_MAX)
2177 idxCOTable = SVGA_COTABLE_MAX + (enmType - VBSVGA_COTABLE_MIN);
2178 else
2179 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
2180 RT_UNTRUSTED_VALIDATED_FENCE();
2181
2182 uint32_t cbCOT;
2183 if (pMob)
2184 {
2185 /* Bind a new mob to the COTable. */
2186 cbCOT = vmsvgaR3MobSize(pMob);
2187
2188 ASSERT_GUEST_RETURN(validSizeInBytes <= cbCOT, VERR_INVALID_PARAMETER);
2189 RT_UNTRUSTED_VALIDATED_FENCE();
2190
2191 /* Create a memory pointer, which is accessible by host. */
2192 rc = vmsvgaR3MobBackingStoreCreate(pSvgaR3State, pMob, validSizeInBytes);
2193 }
2194 else
2195 {
2196 /* Unbind. */
2197 validSizeInBytes = 0;
2198 cbCOT = 0;
2199 vmsvgaR3MobBackingStoreDelete(pSvgaR3State, pDXContext->aCOTMobs[idxCOTable]);
2200 }
2201
2202 uint32_t cEntries = 0;
2203 uint32_t cValidEntries = 0;
2204 if (RT_SUCCESS(rc))
2205 {
2206 static uint32_t const s_acbEntry[] =
2207 {
2208 sizeof(SVGACOTableDXRTViewEntry),
2209 sizeof(SVGACOTableDXDSViewEntry),
2210 sizeof(SVGACOTableDXSRViewEntry),
2211 sizeof(SVGACOTableDXElementLayoutEntry),
2212 sizeof(SVGACOTableDXBlendStateEntry),
2213 sizeof(SVGACOTableDXDepthStencilEntry),
2214 sizeof(SVGACOTableDXRasterizerStateEntry),
2215 sizeof(SVGACOTableDXSamplerEntry),
2216 sizeof(SVGACOTableDXStreamOutputEntry),
2217 sizeof(SVGACOTableDXQueryEntry),
2218 sizeof(SVGACOTableDXShaderEntry),
2219 sizeof(SVGACOTableDXUAViewEntry),
2220 sizeof(VBSVGACOTableDXVideoProcessorEntry),
2221 sizeof(VBSVGACOTableDXVideoDecoderOutputViewEntry),
2222 sizeof(VBSVGACOTableDXVideoDecoderEntry),
2223 sizeof(VBSVGACOTableDXVideoProcessorInputViewEntry),
2224 sizeof(VBSVGACOTableDXVideoProcessorOutputViewEntry),
2225 };
2226 AssertCompile(RT_ELEMENTS(s_acbEntry) == VBSVGA_NUM_COTABLES);
2227
2228 cEntries = cbCOT / s_acbEntry[idxCOTable];
2229 cValidEntries = validSizeInBytes / s_acbEntry[idxCOTable];
2230 }
2231
2232 if (RT_SUCCESS(rc))
2233 {
2234 if ( fGrow
2235 && pDXContext->aCOTMobs[idxCOTable]
2236 && cValidEntries)
2237 {
2238 /* Copy entries from the current mob to the new mob. */
2239 void const *pvSrc = vmsvgaR3MobBackingStorePtr(pDXContext->aCOTMobs[idxCOTable], 0);
2240 void *pvDst = vmsvgaR3MobBackingStorePtr(pMob, 0);
2241 if (pvSrc && pvDst)
2242 memcpy(pvDst, pvSrc, validSizeInBytes);
2243 else
2244 AssertFailedStmt(rc = VERR_INVALID_STATE);
2245 }
2246 }
2247
2248 if (RT_SUCCESS(rc))
2249 {
2250 pDXContext->aCOTMobs[idxCOTable] = pMob;
2251
2252 void *pvCOT = vmsvgaR3MobBackingStorePtr(pMob, 0);
2253 switch (enmType)
2254 {
2255 case SVGA_COTABLE_RTVIEW:
2256 pDXContext->cot.paRTView = (SVGACOTableDXRTViewEntry *)pvCOT;
2257 pDXContext->cot.cRTView = cEntries;
2258 break;
2259 case SVGA_COTABLE_DSVIEW:
2260 pDXContext->cot.paDSView = (SVGACOTableDXDSViewEntry *)pvCOT;
2261 pDXContext->cot.cDSView = cEntries;
2262 break;
2263 case SVGA_COTABLE_SRVIEW:
2264 pDXContext->cot.paSRView = (SVGACOTableDXSRViewEntry *)pvCOT;
2265 pDXContext->cot.cSRView = cEntries;
2266 break;
2267 case SVGA_COTABLE_ELEMENTLAYOUT:
2268 pDXContext->cot.paElementLayout = (SVGACOTableDXElementLayoutEntry *)pvCOT;
2269 pDXContext->cot.cElementLayout = cEntries;
2270 break;
2271 case SVGA_COTABLE_BLENDSTATE:
2272 pDXContext->cot.paBlendState = (SVGACOTableDXBlendStateEntry *)pvCOT;
2273 pDXContext->cot.cBlendState = cEntries;
2274 break;
2275 case SVGA_COTABLE_DEPTHSTENCIL:
2276 pDXContext->cot.paDepthStencil = (SVGACOTableDXDepthStencilEntry *)pvCOT;
2277 pDXContext->cot.cDepthStencil = cEntries;
2278 break;
2279 case SVGA_COTABLE_RASTERIZERSTATE:
2280 pDXContext->cot.paRasterizerState = (SVGACOTableDXRasterizerStateEntry *)pvCOT;
2281 pDXContext->cot.cRasterizerState = cEntries;
2282 break;
2283 case SVGA_COTABLE_SAMPLER:
2284 pDXContext->cot.paSampler = (SVGACOTableDXSamplerEntry *)pvCOT;
2285 pDXContext->cot.cSampler = cEntries;
2286 break;
2287 case SVGA_COTABLE_STREAMOUTPUT:
2288 pDXContext->cot.paStreamOutput = (SVGACOTableDXStreamOutputEntry *)pvCOT;
2289 pDXContext->cot.cStreamOutput = cEntries;
2290 break;
2291 case SVGA_COTABLE_DXQUERY:
2292 pDXContext->cot.paQuery = (SVGACOTableDXQueryEntry *)pvCOT;
2293 pDXContext->cot.cQuery = cEntries;
2294 break;
2295 case SVGA_COTABLE_DXSHADER:
2296 pDXContext->cot.paShader = (SVGACOTableDXShaderEntry *)pvCOT;
2297 pDXContext->cot.cShader = cEntries;
2298 break;
2299 case SVGA_COTABLE_UAVIEW:
2300 pDXContext->cot.paUAView = (SVGACOTableDXUAViewEntry *)pvCOT;
2301 pDXContext->cot.cUAView = cEntries;
2302 break;
2303 case SVGA_COTABLE_MAX: break; /* Compiler warning */
2304 case VBSVGA_COTABLE_VIDEOPROCESSOR:
2305 pDXContext->cot.paVideoProcessor = (VBSVGACOTableDXVideoProcessorEntry *)pvCOT;
2306 pDXContext->cot.cVideoProcessor = cEntries;
2307 break;
2308 case VBSVGA_COTABLE_VDOV:
2309 pDXContext->cot.paVideoDecoderOutputView = (VBSVGACOTableDXVideoDecoderOutputViewEntry *)pvCOT;
2310 pDXContext->cot.cVideoDecoderOutputView = cEntries;
2311 break;
2312 case VBSVGA_COTABLE_VIDEODECODER:
2313 pDXContext->cot.paVideoDecoder = (VBSVGACOTableDXVideoDecoderEntry *)pvCOT;
2314 pDXContext->cot.cVideoDecoder = cEntries;
2315 break;
2316 case VBSVGA_COTABLE_VPIV:
2317 pDXContext->cot.paVideoProcessorInputView = (VBSVGACOTableDXVideoProcessorInputViewEntry *)pvCOT;
2318 pDXContext->cot.cVideoProcessorInputView = cEntries;
2319 break;
2320 case VBSVGA_COTABLE_VPOV:
2321 pDXContext->cot.paVideoProcessorOutputView = (VBSVGACOTableDXVideoProcessorOutputViewEntry *)pvCOT;
2322 pDXContext->cot.cVideoProcessorOutputView = cEntries;
2323 break;
2324 case VBSVGA_COTABLE_MAX: break; /* Compiler warning */
2325#ifndef DEBUG_sunlover
2326 default: break; /* Compiler warning. */
2327#endif
2328 }
2329 }
2330 else
2331 vmsvgaR3MobBackingStoreDelete(pSvgaR3State, pMob);
2332
2333 /* Notify the backend. */
2334 if (RT_SUCCESS(rc))
2335 rc = pSvgaR3State->pFuncsDX->pfnDXSetCOTable(pThisCC, pDXContext, enmType, cValidEntries);
2336
2337 return rc;
2338}
2339
2340
2341int vmsvga3dDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, PVMSVGAMOB pMob)
2342{
2343 int rc;
2344 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2345 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetCOTable, VERR_INVALID_STATE);
2346 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2347 AssertReturn(p3dState, VERR_INVALID_STATE);
2348
2349 PVMSVGA3DDXCONTEXT pDXContext;
2350 rc = vmsvga3dDXContextFromCid(p3dState, pCmd->cid, &pDXContext);
2351 AssertRCReturn(rc, rc);
2352 RT_UNTRUSTED_VALIDATED_FENCE();
2353
2354 return dxSetOrGrowCOTable(pThisCC, pDXContext, pMob, pCmd->type, pCmd->validSizeInBytes, false);
2355}
2356
2357
2358int vmsvga3dDXReadbackCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackCOTable const *pCmd)
2359{
2360 int rc;
2361 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2362 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
2363 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2364 AssertReturn(p3dState, VERR_INVALID_STATE);
2365
2366 PVMSVGA3DDXCONTEXT pDXContext;
2367 rc = vmsvga3dDXContextFromCid(p3dState, pCmd->cid, &pDXContext);
2368 AssertRCReturn(rc, rc);
2369 RT_UNTRUSTED_VALIDATED_FENCE();
2370
2371 ASSERT_GUEST_RETURN(pCmd->type < RT_ELEMENTS(pDXContext->aCOTMobs), VERR_INVALID_PARAMETER);
2372 RT_UNTRUSTED_VALIDATED_FENCE();
2373
2374 PVMSVGAMOB pMob = pDXContext->aCOTMobs[pCmd->type];
2375 rc = vmsvgaR3MobBackingStoreWriteToGuest(pSvgaR3State, pMob);
2376 return rc;
2377}
2378
2379
2380int vmsvga3dDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext)
2381{
2382 int rc;
2383 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2384 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBufferCopy, VERR_INVALID_STATE);
2385 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2386 AssertReturn(p3dState, VERR_INVALID_STATE);
2387
2388 PVMSVGA3DDXCONTEXT pDXContext;
2389 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2390 AssertRCReturn(rc, rc);
2391
2392 rc = pSvgaR3State->pFuncsDX->pfnDXBufferCopy(pThisCC, pDXContext);
2393 return rc;
2394}
2395
2396
2397int vmsvga3dDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext)
2398{
2399 int rc;
2400 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2401 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSurfaceCopyAndReadback, VERR_INVALID_STATE);
2402 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2403 AssertReturn(p3dState, VERR_INVALID_STATE);
2404
2405 PVMSVGA3DDXCONTEXT pDXContext;
2406 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2407 AssertRCReturn(rc, rc);
2408
2409 rc = pSvgaR3State->pFuncsDX->pfnDXSurfaceCopyAndReadback(pThisCC, pDXContext);
2410 return rc;
2411}
2412
2413
2414int vmsvga3dDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext)
2415{
2416 int rc;
2417 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2418 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXMoveQuery, VERR_INVALID_STATE);
2419 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2420 AssertReturn(p3dState, VERR_INVALID_STATE);
2421
2422 PVMSVGA3DDXCONTEXT pDXContext;
2423 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2424 AssertRCReturn(rc, rc);
2425
2426 rc = pSvgaR3State->pFuncsDX->pfnDXMoveQuery(pThisCC, pDXContext);
2427 return rc;
2428}
2429
2430
2431int vmsvga3dDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd)
2432{
2433 int rc;
2434 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2435 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
2436 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2437 AssertReturn(p3dState, VERR_INVALID_STATE);
2438
2439 RT_NOREF(idDXContext);
2440
2441 PVMSVGA3DDXCONTEXT pDXContext;
2442 rc = vmsvga3dDXContextFromCid(p3dState, pCmd->cid, &pDXContext);
2443 AssertRCReturn(rc, rc);
2444
2445 for (uint32_t i = 0; i < pDXContext->cot.cQuery; ++i)
2446 {
2447 SVGACOTableDXQueryEntry *pEntry = &pDXContext->cot.paQuery[i];
2448 if (pEntry->type != SVGA3D_QUERYTYPE_INVALID)
2449 pEntry->mobid = pCmd->mobid;
2450 }
2451
2452 return rc;
2453}
2454
2455
2456int vmsvga3dDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd)
2457{
2458 int rc;
2459 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2460 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
2461 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2462 AssertReturn(p3dState, VERR_INVALID_STATE);
2463
2464 RT_NOREF(idDXContext);
2465
2466 PVMSVGA3DDXCONTEXT pDXContext;
2467 rc = vmsvga3dDXContextFromCid(p3dState, pCmd->cid, &pDXContext);
2468 AssertRCReturn(rc, rc);
2469
2470 /* "Read back cached states from the device if they exist."
2471 * The device does not cache queries. So this is a NOP.
2472 */
2473 RT_NOREF(pDXContext);
2474
2475 return rc;
2476}
2477
2478
2479int vmsvga3dDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext)
2480{
2481 int rc;
2482 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2483 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBindAllShader, VERR_INVALID_STATE);
2484 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2485 AssertReturn(p3dState, VERR_INVALID_STATE);
2486
2487 PVMSVGA3DDXCONTEXT pDXContext;
2488 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2489 AssertRCReturn(rc, rc);
2490
2491 rc = pSvgaR3State->pFuncsDX->pfnDXBindAllShader(pThisCC, pDXContext);
2492 return rc;
2493}
2494
2495
2496int vmsvga3dDXHint(PVGASTATECC pThisCC, uint32_t idDXContext)
2497{
2498 int rc;
2499 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2500 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXHint, VERR_INVALID_STATE);
2501 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2502 AssertReturn(p3dState, VERR_INVALID_STATE);
2503
2504 PVMSVGA3DDXCONTEXT pDXContext;
2505 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2506 AssertRCReturn(rc, rc);
2507
2508 rc = pSvgaR3State->pFuncsDX->pfnDXHint(pThisCC, pDXContext);
2509 return rc;
2510}
2511
2512
2513int vmsvga3dDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext)
2514{
2515 int rc;
2516 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2517 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBufferUpdate, VERR_INVALID_STATE);
2518 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2519 AssertReturn(p3dState, VERR_INVALID_STATE);
2520
2521 PVMSVGA3DDXCONTEXT pDXContext;
2522 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2523 AssertRCReturn(rc, rc);
2524
2525 rc = pSvgaR3State->pFuncsDX->pfnDXBufferUpdate(pThisCC, pDXContext);
2526 return rc;
2527}
2528
2529
2530int vmsvga3dDXSetConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetConstantBufferOffset const *pCmd, SVGA3dShaderType type)
2531{
2532 int rc;
2533 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2534 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetSingleConstantBuffer, VERR_INVALID_STATE);
2535 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2536 AssertReturn(p3dState, VERR_INVALID_STATE);
2537
2538 PVMSVGA3DDXCONTEXT pDXContext;
2539 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2540 AssertRCReturn(rc, rc);
2541
2542 ASSERT_GUEST_RETURN(pCmd->slot < SVGA3D_DX_MAX_CONSTBUFFERS, VERR_INVALID_PARAMETER);
2543 RT_UNTRUSTED_VALIDATED_FENCE();
2544
2545 uint32_t const idxShaderState = type - SVGA3D_SHADERTYPE_MIN;
2546 SVGA3dConstantBufferBinding *pCBB = &pDXContext->svgaDXContext.shaderState[idxShaderState].constantBuffers[pCmd->slot];
2547
2548 /* Only 'offsetInBytes' is updated. */
2549 // pCBB->sid;
2550 pCBB->offsetInBytes = pCmd->offsetInBytes;
2551 // pCBB->sizeInBytes;
2552
2553 rc = pSvgaR3State->pFuncsDX->pfnDXSetSingleConstantBuffer(pThisCC, pDXContext, pCmd->slot, type, pCBB->sid, pCBB->offsetInBytes, pCBB->sizeInBytes);
2554 return rc;
2555}
2556
2557
2558int vmsvga3dDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext)
2559{
2560 int rc;
2561 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2562 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXCondBindAllShader, VERR_INVALID_STATE);
2563 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2564 AssertReturn(p3dState, VERR_INVALID_STATE);
2565
2566 PVMSVGA3DDXCONTEXT pDXContext;
2567 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2568 AssertRCReturn(rc, rc);
2569
2570 rc = pSvgaR3State->pFuncsDX->pfnDXCondBindAllShader(pThisCC, pDXContext);
2571 return rc;
2572}
2573
2574
2575int vmsvga3dScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext)
2576{
2577 int rc;
2578 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2579 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnScreenCopy, VERR_INVALID_STATE);
2580 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2581 AssertReturn(p3dState, VERR_INVALID_STATE);
2582
2583 PVMSVGA3DDXCONTEXT pDXContext;
2584 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2585 AssertRCReturn(rc, rc);
2586
2587 rc = pSvgaR3State->pFuncsDX->pfnScreenCopy(pThisCC, pDXContext);
2588 return rc;
2589}
2590
2591
2592int vmsvga3dDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd)
2593{
2594 int rc;
2595 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2596 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetCOTable, VERR_INVALID_STATE);
2597 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2598 AssertReturn(p3dState, VERR_INVALID_STATE);
2599
2600 PVMSVGA3DDXCONTEXT pDXContext;
2601 rc = vmsvga3dDXContextFromCid(p3dState, pCmd->cid, &pDXContext);
2602 AssertRCReturn(rc, rc);
2603
2604 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2605 return dxSetOrGrowCOTable(pThisCC, pDXContext, pMob, pCmd->type, pCmd->validSizeInBytes, true);
2606}
2607
2608
2609int vmsvga3dIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd)
2610{
2611 int rc;
2612 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2613 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnIntraSurfaceCopy, VERR_INVALID_STATE);
2614 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2615 AssertReturn(p3dState, VERR_INVALID_STATE);
2616
2617 PVMSVGA3DDXCONTEXT pDXContext;
2618 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2619 AssertRCReturn(rc, rc);
2620
2621 rc = pSvgaR3State->pFuncsDX->pfnIntraSurfaceCopy(pThisCC, pDXContext, pCmd->surface, pCmd->box);
2622 return rc;
2623}
2624
2625
2626int vmsvga3dDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd)
2627{
2628 int rc;
2629 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2630 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXResolveCopy, VERR_INVALID_STATE);
2631 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2632 AssertReturn(p3dState, VERR_INVALID_STATE);
2633
2634 PVMSVGA3DDXCONTEXT pDXContext;
2635 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2636 AssertRCReturn(rc, rc);
2637
2638 rc = pSvgaR3State->pFuncsDX->pfnDXResolveCopy(pThisCC, pDXContext, pCmd->dstSid, pCmd->dstSubResource,
2639 pCmd->srcSid, pCmd->srcSubResource, pCmd->copyFormat);
2640 return rc;
2641}
2642
2643
2644int vmsvga3dDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext)
2645{
2646 int rc;
2647 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2648 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXPredResolveCopy, VERR_INVALID_STATE);
2649 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2650 AssertReturn(p3dState, VERR_INVALID_STATE);
2651
2652 PVMSVGA3DDXCONTEXT pDXContext;
2653 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2654 AssertRCReturn(rc, rc);
2655
2656 rc = pSvgaR3State->pFuncsDX->pfnDXPredResolveCopy(pThisCC, pDXContext);
2657 return rc;
2658}
2659
2660
2661int vmsvga3dDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext)
2662{
2663 int rc;
2664 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2665 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXPredConvertRegion, VERR_INVALID_STATE);
2666 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2667 AssertReturn(p3dState, VERR_INVALID_STATE);
2668
2669 PVMSVGA3DDXCONTEXT pDXContext;
2670 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2671 AssertRCReturn(rc, rc);
2672
2673 rc = pSvgaR3State->pFuncsDX->pfnDXPredConvertRegion(pThisCC, pDXContext);
2674 return rc;
2675}
2676
2677
2678int vmsvga3dDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext)
2679{
2680 int rc;
2681 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2682 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXPredConvert, VERR_INVALID_STATE);
2683 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2684 AssertReturn(p3dState, VERR_INVALID_STATE);
2685
2686 PVMSVGA3DDXCONTEXT pDXContext;
2687 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2688 AssertRCReturn(rc, rc);
2689
2690 rc = pSvgaR3State->pFuncsDX->pfnDXPredConvert(pThisCC, pDXContext);
2691 return rc;
2692}
2693
2694
2695int vmsvga3dWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext)
2696{
2697 int rc;
2698 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2699 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnWholeSurfaceCopy, VERR_INVALID_STATE);
2700 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2701 AssertReturn(p3dState, VERR_INVALID_STATE);
2702
2703 PVMSVGA3DDXCONTEXT pDXContext;
2704 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2705 AssertRCReturn(rc, rc);
2706
2707 rc = pSvgaR3State->pFuncsDX->pfnWholeSurfaceCopy(pThisCC, pDXContext);
2708 return rc;
2709}
2710
2711
2712int vmsvga3dDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd)
2713{
2714 int rc;
2715 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2716 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDefineUAView, VERR_INVALID_STATE);
2717 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2718 AssertReturn(p3dState, VERR_INVALID_STATE);
2719
2720 PVMSVGA3DDXCONTEXT pDXContext;
2721 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2722 AssertRCReturn(rc, rc);
2723
2724 SVGA3dUAViewId const uaViewId = pCmd->uaViewId;
2725
2726 ASSERT_GUEST_RETURN(pDXContext->cot.paUAView, VERR_INVALID_STATE);
2727 ASSERT_GUEST_RETURN(uaViewId < pDXContext->cot.cUAView, VERR_INVALID_PARAMETER);
2728 RT_UNTRUSTED_VALIDATED_FENCE();
2729
2730 SVGACOTableDXUAViewEntry *pEntry = &pDXContext->cot.paUAView[uaViewId];
2731 pEntry->sid = pCmd->sid;
2732 pEntry->format = pCmd->format;
2733 pEntry->resourceDimension = pCmd->resourceDimension;
2734 pEntry->desc = pCmd->desc;
2735 pEntry->structureCount = 0;
2736
2737 rc = pSvgaR3State->pFuncsDX->pfnDXDefineUAView(pThisCC, pDXContext, uaViewId, pEntry);
2738 return rc;
2739}
2740
2741
2742int vmsvga3dDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd)
2743{
2744 int rc;
2745 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2746 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDestroyUAView, VERR_INVALID_STATE);
2747 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2748 AssertReturn(p3dState, VERR_INVALID_STATE);
2749
2750 PVMSVGA3DDXCONTEXT pDXContext;
2751 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2752 AssertRCReturn(rc, rc);
2753
2754 SVGA3dUAViewId const uaViewId = pCmd->uaViewId;
2755
2756 ASSERT_GUEST_RETURN(pDXContext->cot.paUAView, VERR_INVALID_STATE);
2757 ASSERT_GUEST_RETURN(uaViewId < pDXContext->cot.cUAView, VERR_INVALID_PARAMETER);
2758 RT_UNTRUSTED_VALIDATED_FENCE();
2759
2760 SVGACOTableDXUAViewEntry *pEntry = &pDXContext->cot.paUAView[uaViewId];
2761 RT_ZERO(*pEntry);
2762
2763 rc = pSvgaR3State->pFuncsDX->pfnDXDestroyUAView(pThisCC, pDXContext, uaViewId);
2764 return rc;
2765}
2766
2767
2768int vmsvga3dDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd)
2769{
2770 int rc;
2771 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2772 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXClearUAViewUint, VERR_INVALID_STATE);
2773 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2774 AssertReturn(p3dState, VERR_INVALID_STATE);
2775
2776 PVMSVGA3DDXCONTEXT pDXContext;
2777 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2778 AssertRCReturn(rc, rc);
2779
2780 SVGA3dUAViewId const uaViewId = pCmd->uaViewId;
2781
2782 ASSERT_GUEST_RETURN(pDXContext->cot.paUAView, VERR_INVALID_STATE);
2783 ASSERT_GUEST_RETURN(uaViewId < pDXContext->cot.cUAView, VERR_INVALID_PARAMETER);
2784 RT_UNTRUSTED_VALIDATED_FENCE();
2785
2786 rc = pSvgaR3State->pFuncsDX->pfnDXClearUAViewUint(pThisCC, pDXContext, uaViewId, pCmd->value.value);
2787 return rc;
2788}
2789
2790
2791int vmsvga3dDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd)
2792{
2793 int rc;
2794 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2795 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXClearUAViewFloat, VERR_INVALID_STATE);
2796 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2797 AssertReturn(p3dState, VERR_INVALID_STATE);
2798
2799 PVMSVGA3DDXCONTEXT pDXContext;
2800 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2801 AssertRCReturn(rc, rc);
2802
2803 SVGA3dUAViewId const uaViewId = pCmd->uaViewId;
2804
2805 ASSERT_GUEST_RETURN(pDXContext->cot.paUAView, VERR_INVALID_STATE);
2806 ASSERT_GUEST_RETURN(uaViewId < pDXContext->cot.cUAView, VERR_INVALID_PARAMETER);
2807 RT_UNTRUSTED_VALIDATED_FENCE();
2808
2809 rc = pSvgaR3State->pFuncsDX->pfnDXClearUAViewFloat(pThisCC, pDXContext, uaViewId, pCmd->value.value);
2810 return rc;
2811}
2812
2813
2814int vmsvga3dDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd)
2815{
2816 int rc;
2817 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2818 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXCopyStructureCount, VERR_INVALID_STATE);
2819 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2820 AssertReturn(p3dState, VERR_INVALID_STATE);
2821
2822 PVMSVGA3DDXCONTEXT pDXContext;
2823 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2824 AssertRCReturn(rc, rc);
2825
2826 SVGA3dUAViewId const uaViewId = pCmd->srcUAViewId;
2827
2828 ASSERT_GUEST_RETURN(pDXContext->cot.paUAView, VERR_INVALID_STATE);
2829 ASSERT_GUEST_RETURN(uaViewId < pDXContext->cot.cUAView, VERR_INVALID_PARAMETER);
2830 RT_UNTRUSTED_VALIDATED_FENCE();
2831
2832 rc = pSvgaR3State->pFuncsDX->pfnDXCopyStructureCount(pThisCC, pDXContext, uaViewId, pCmd->destSid, pCmd->destByteOffset);
2833 return rc;
2834}
2835
2836
2837int vmsvga3dDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cUAViewId, SVGA3dUAViewId const *paUAViewId)
2838{
2839 int rc;
2840 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2841 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetUAViews, VERR_INVALID_STATE);
2842 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2843 AssertReturn(p3dState, VERR_INVALID_STATE);
2844
2845 PVMSVGA3DDXCONTEXT pDXContext;
2846 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2847 AssertRCReturn(rc, rc);
2848
2849 ASSERT_GUEST_RETURN(pCmd->uavSpliceIndex <= SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS, VERR_INVALID_PARAMETER);
2850 ASSERT_GUEST_RETURN(cUAViewId <= SVGA3D_DX11_1_MAX_UAVIEWS, VERR_INVALID_PARAMETER);
2851 for (uint32_t i = 0; i < cUAViewId; ++i)
2852 ASSERT_GUEST_RETURN( paUAViewId[i] < pDXContext->cot.cUAView
2853 || paUAViewId[i] == SVGA3D_INVALID_ID, VERR_INVALID_PARAMETER);
2854 RT_UNTRUSTED_VALIDATED_FENCE();
2855
2856 for (uint32_t i = 0; i < cUAViewId; ++i)
2857 {
2858 SVGA3dUAViewId const uaViewId = paUAViewId[i];
2859 pDXContext->svgaDXContext.uaViewIds[i] = uaViewId;
2860 }
2861 pDXContext->svgaDXContext.uavSpliceIndex = pCmd->uavSpliceIndex;
2862
2863 rc = pSvgaR3State->pFuncsDX->pfnDXSetUAViews(pThisCC, pDXContext, pCmd->uavSpliceIndex, cUAViewId, paUAViewId);
2864 return rc;
2865}
2866
2867
2868int vmsvga3dDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd)
2869{
2870 int rc;
2871 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2872 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstancedIndirect, VERR_INVALID_STATE);
2873 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2874 AssertReturn(p3dState, VERR_INVALID_STATE);
2875
2876 PVMSVGA3DDXCONTEXT pDXContext;
2877 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2878 AssertRCReturn(rc, rc);
2879
2880 rc = pSvgaR3State->pFuncsDX->pfnDXDrawIndexedInstancedIndirect(pThisCC, pDXContext, pCmd->argsBufferSid, pCmd->byteOffsetForArgs);
2881 return rc;
2882}
2883
2884
2885int vmsvga3dDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd)
2886{
2887 int rc;
2888 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2889 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDrawInstancedIndirect, VERR_INVALID_STATE);
2890 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2891 AssertReturn(p3dState, VERR_INVALID_STATE);
2892
2893 PVMSVGA3DDXCONTEXT pDXContext;
2894 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2895 AssertRCReturn(rc, rc);
2896
2897 rc = pSvgaR3State->pFuncsDX->pfnDXDrawInstancedIndirect(pThisCC, pDXContext, pCmd->argsBufferSid, pCmd->byteOffsetForArgs);
2898 return rc;
2899}
2900
2901
2902int vmsvga3dDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd)
2903{
2904 int rc;
2905 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2906 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDispatch, VERR_INVALID_STATE);
2907 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2908 AssertReturn(p3dState, VERR_INVALID_STATE);
2909
2910 PVMSVGA3DDXCONTEXT pDXContext;
2911 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2912 AssertRCReturn(rc, rc);
2913
2914 rc = pSvgaR3State->pFuncsDX->pfnDXDispatch(pThisCC, pDXContext, pCmd->threadGroupCountX, pCmd->threadGroupCountY, pCmd->threadGroupCountZ);
2915 return rc;
2916}
2917
2918
2919int vmsvga3dDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext)
2920{
2921 int rc;
2922 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2923 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXDispatchIndirect, VERR_INVALID_STATE);
2924 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2925 AssertReturn(p3dState, VERR_INVALID_STATE);
2926
2927 PVMSVGA3DDXCONTEXT pDXContext;
2928 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2929 AssertRCReturn(rc, rc);
2930
2931 rc = pSvgaR3State->pFuncsDX->pfnDXDispatchIndirect(pThisCC, pDXContext);
2932 return rc;
2933}
2934
2935
2936int vmsvga3dWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext)
2937{
2938 int rc;
2939 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2940 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnWriteZeroSurface, VERR_INVALID_STATE);
2941 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2942 AssertReturn(p3dState, VERR_INVALID_STATE);
2943
2944 PVMSVGA3DDXCONTEXT pDXContext;
2945 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2946 AssertRCReturn(rc, rc);
2947
2948 rc = pSvgaR3State->pFuncsDX->pfnWriteZeroSurface(pThisCC, pDXContext);
2949 return rc;
2950}
2951
2952
2953int vmsvga3dHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext)
2954{
2955 int rc;
2956 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2957 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnHintZeroSurface, VERR_INVALID_STATE);
2958 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2959 AssertReturn(p3dState, VERR_INVALID_STATE);
2960
2961 PVMSVGA3DDXCONTEXT pDXContext;
2962 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2963 AssertRCReturn(rc, rc);
2964
2965 rc = pSvgaR3State->pFuncsDX->pfnHintZeroSurface(pThisCC, pDXContext);
2966 return rc;
2967}
2968
2969
2970int vmsvga3dDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext)
2971{
2972 int rc;
2973 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2974 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXTransferToBuffer, VERR_INVALID_STATE);
2975 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2976 AssertReturn(p3dState, VERR_INVALID_STATE);
2977
2978 PVMSVGA3DDXCONTEXT pDXContext;
2979 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2980 AssertRCReturn(rc, rc);
2981
2982 rc = pSvgaR3State->pFuncsDX->pfnDXTransferToBuffer(pThisCC, pDXContext);
2983 return rc;
2984}
2985
2986
2987int vmsvga3dDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd)
2988{
2989 int rc;
2990 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2991 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
2992 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
2993 AssertReturn(p3dState, VERR_INVALID_STATE);
2994
2995 PVMSVGA3DDXCONTEXT pDXContext;
2996 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
2997 AssertRCReturn(rc, rc);
2998
2999 SVGA3dUAViewId const uaViewId = pCmd->uaViewId;
3000
3001 ASSERT_GUEST_RETURN(pDXContext->cot.paUAView, VERR_INVALID_STATE);
3002 ASSERT_GUEST_RETURN(uaViewId < pDXContext->cot.cUAView, VERR_INVALID_PARAMETER);
3003 RT_UNTRUSTED_VALIDATED_FENCE();
3004
3005 SVGACOTableDXUAViewEntry *pEntry = &pDXContext->cot.paUAView[uaViewId];
3006 pEntry->structureCount = pCmd->structureCount;
3007
3008 return VINF_SUCCESS;
3009}
3010
3011
3012int vmsvga3dLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext)
3013{
3014 int rc;
3015 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3016 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnLogicOpsBitBlt, VERR_INVALID_STATE);
3017 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3018 AssertReturn(p3dState, VERR_INVALID_STATE);
3019
3020 PVMSVGA3DDXCONTEXT pDXContext;
3021 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3022 AssertRCReturn(rc, rc);
3023
3024 rc = pSvgaR3State->pFuncsDX->pfnLogicOpsBitBlt(pThisCC, pDXContext);
3025 return rc;
3026}
3027
3028
3029int vmsvga3dLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext)
3030{
3031 int rc;
3032 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3033 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnLogicOpsTransBlt, VERR_INVALID_STATE);
3034 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3035 AssertReturn(p3dState, VERR_INVALID_STATE);
3036
3037 PVMSVGA3DDXCONTEXT pDXContext;
3038 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3039 AssertRCReturn(rc, rc);
3040
3041 rc = pSvgaR3State->pFuncsDX->pfnLogicOpsTransBlt(pThisCC, pDXContext);
3042 return rc;
3043}
3044
3045
3046int vmsvga3dLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext)
3047{
3048 int rc;
3049 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3050 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnLogicOpsStretchBlt, VERR_INVALID_STATE);
3051 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3052 AssertReturn(p3dState, VERR_INVALID_STATE);
3053
3054 PVMSVGA3DDXCONTEXT pDXContext;
3055 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3056 AssertRCReturn(rc, rc);
3057
3058 rc = pSvgaR3State->pFuncsDX->pfnLogicOpsStretchBlt(pThisCC, pDXContext);
3059 return rc;
3060}
3061
3062
3063int vmsvga3dLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext)
3064{
3065 int rc;
3066 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3067 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnLogicOpsColorFill, VERR_INVALID_STATE);
3068 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3069 AssertReturn(p3dState, VERR_INVALID_STATE);
3070
3071 PVMSVGA3DDXCONTEXT pDXContext;
3072 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3073 AssertRCReturn(rc, rc);
3074
3075 rc = pSvgaR3State->pFuncsDX->pfnLogicOpsColorFill(pThisCC, pDXContext);
3076 return rc;
3077}
3078
3079
3080int vmsvga3dLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext)
3081{
3082 int rc;
3083 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3084 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnLogicOpsAlphaBlend, VERR_INVALID_STATE);
3085 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3086 AssertReturn(p3dState, VERR_INVALID_STATE);
3087
3088 PVMSVGA3DDXCONTEXT pDXContext;
3089 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3090 AssertRCReturn(rc, rc);
3091
3092 rc = pSvgaR3State->pFuncsDX->pfnLogicOpsAlphaBlend(pThisCC, pDXContext);
3093 return rc;
3094}
3095
3096
3097int vmsvga3dLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext)
3098{
3099 int rc;
3100 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3101 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnLogicOpsClearTypeBlend, VERR_INVALID_STATE);
3102 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3103 AssertReturn(p3dState, VERR_INVALID_STATE);
3104
3105 PVMSVGA3DDXCONTEXT pDXContext;
3106 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3107 AssertRCReturn(rc, rc);
3108
3109 rc = pSvgaR3State->pFuncsDX->pfnLogicOpsClearTypeBlend(pThisCC, pDXContext);
3110 return rc;
3111}
3112
3113
3114int vmsvga3dDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cUAViewId, SVGA3dUAViewId const *paUAViewId)
3115{
3116 int rc;
3117 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3118 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetCSUAViews, VERR_INVALID_STATE);
3119 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3120 AssertReturn(p3dState, VERR_INVALID_STATE);
3121
3122 PVMSVGA3DDXCONTEXT pDXContext;
3123 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3124 AssertRCReturn(rc, rc);
3125
3126 ASSERT_GUEST_RETURN(pCmd->startIndex < SVGA3D_DX11_1_MAX_UAVIEWS, VERR_INVALID_PARAMETER);
3127 ASSERT_GUEST_RETURN(cUAViewId <= SVGA3D_DX11_1_MAX_UAVIEWS - pCmd->startIndex, VERR_INVALID_PARAMETER);
3128 for (uint32_t i = 0; i < cUAViewId; ++i)
3129 ASSERT_GUEST_RETURN( paUAViewId[i] < pDXContext->cot.cUAView
3130 || paUAViewId[i] == SVGA3D_INVALID_ID, VERR_INVALID_PARAMETER);
3131 RT_UNTRUSTED_VALIDATED_FENCE();
3132
3133 for (uint32_t i = 0; i < cUAViewId; ++i)
3134 {
3135 SVGA3dUAViewId const uaViewId = paUAViewId[i];
3136 pDXContext->svgaDXContext.csuaViewIds[pCmd->startIndex + i] = uaViewId;
3137 }
3138
3139 rc = pSvgaR3State->pFuncsDX->pfnDXSetCSUAViews(pThisCC, pDXContext, pCmd->startIndex, cUAViewId, paUAViewId);
3140 return rc;
3141}
3142
3143
3144int vmsvga3dDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext)
3145{
3146 int rc;
3147 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3148 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetMinLOD, VERR_INVALID_STATE);
3149 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3150 AssertReturn(p3dState, VERR_INVALID_STATE);
3151
3152 PVMSVGA3DDXCONTEXT pDXContext;
3153 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3154 AssertRCReturn(rc, rc);
3155
3156 rc = pSvgaR3State->pFuncsDX->pfnDXSetMinLOD(pThisCC, pDXContext);
3157 return rc;
3158}
3159
3160
3161int vmsvga3dDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd)
3162{
3163 int rc;
3164 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3165 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
3166 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3167 AssertReturn(p3dState, VERR_INVALID_STATE);
3168
3169 PVMSVGA3DDXCONTEXT pDXContext;
3170 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3171 AssertRCReturn(rc, rc);
3172
3173 SVGA3dStreamOutputId const soid = pCmd->soid;
3174
3175 ASSERT_GUEST_RETURN(pDXContext->cot.paStreamOutput, VERR_INVALID_STATE);
3176 ASSERT_GUEST_RETURN(soid < pDXContext->cot.cStreamOutput, VERR_INVALID_PARAMETER);
3177 ASSERT_GUEST_RETURN(pCmd->numOutputStreamEntries < SVGA3D_MAX_STREAMOUT_DECLS, VERR_INVALID_PARAMETER);
3178 RT_UNTRUSTED_VALIDATED_FENCE();
3179
3180 SVGACOTableDXStreamOutputEntry *pEntry = &pDXContext->cot.paStreamOutput[soid];
3181 pEntry->numOutputStreamEntries = pCmd->numOutputStreamEntries;
3182 RT_ZERO(pEntry->decl);
3183 memcpy(pEntry->streamOutputStrideInBytes, pCmd->streamOutputStrideInBytes, sizeof(pEntry->streamOutputStrideInBytes));
3184 pEntry->rasterizedStream = pCmd->rasterizedStream;
3185 pEntry->numOutputStreamStrides = pCmd->numOutputStreamStrides;
3186 pEntry->mobid = SVGA_ID_INVALID;
3187 pEntry->offsetInBytes = 0;
3188 pEntry->usesMob = 1;
3189 pEntry->pad0 = 0;
3190 pEntry->pad1 = 0;
3191 RT_ZERO(pEntry->pad2);
3192
3193 rc = pSvgaR3State->pFuncsDX->pfnDXDefineStreamOutput(pThisCC, pDXContext, soid, pEntry);
3194 return rc;
3195}
3196
3197
3198int vmsvga3dDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext)
3199{
3200 int rc;
3201 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3202 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXSetShaderIface, VERR_INVALID_STATE);
3203 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3204 AssertReturn(p3dState, VERR_INVALID_STATE);
3205
3206 PVMSVGA3DDXCONTEXT pDXContext;
3207 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3208 AssertRCReturn(rc, rc);
3209
3210 rc = pSvgaR3State->pFuncsDX->pfnDXSetShaderIface(pThisCC, pDXContext);
3211 return rc;
3212}
3213
3214
3215int vmsvga3dDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd)
3216{
3217 int rc;
3218 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3219 AssertReturn(pSvgaR3State->pFuncsDX, VERR_INVALID_STATE);
3220 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3221 AssertReturn(p3dState, VERR_INVALID_STATE);
3222
3223 PVMSVGA3DDXCONTEXT pDXContext;
3224 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3225 AssertRCReturn(rc, rc);
3226 SVGA3dStreamOutputId const soid = pCmd->soid;
3227
3228 ASSERT_GUEST_RETURN(pDXContext->cot.paStreamOutput, VERR_INVALID_STATE);
3229 ASSERT_GUEST_RETURN(soid < pDXContext->cot.cStreamOutput, VERR_INVALID_PARAMETER);
3230 RT_UNTRUSTED_VALIDATED_FENCE();
3231
3232 SVGACOTableDXStreamOutputEntry *pEntry = &pDXContext->cot.paStreamOutput[soid];
3233
3234 ASSERT_GUEST_RETURN(pCmd->sizeInBytes >= pEntry->numOutputStreamEntries * sizeof(SVGA3dStreamOutputDeclarationEntry), VERR_INVALID_PARAMETER);
3235 ASSERT_GUEST(pEntry->usesMob);
3236
3237 pEntry->mobid = pCmd->mobid;
3238 pEntry->offsetInBytes = pCmd->offsetInBytes;
3239 pEntry->usesMob = 1;
3240
3241 return VINF_SUCCESS;
3242}
3243
3244
3245int vmsvga3dSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext)
3246{
3247 int rc;
3248 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3249 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnSurfaceStretchBltNonMSToMS, VERR_INVALID_STATE);
3250 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3251 AssertReturn(p3dState, VERR_INVALID_STATE);
3252
3253 PVMSVGA3DDXCONTEXT pDXContext;
3254 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3255 AssertRCReturn(rc, rc);
3256
3257 rc = pSvgaR3State->pFuncsDX->pfnSurfaceStretchBltNonMSToMS(pThisCC, pDXContext);
3258 return rc;
3259}
3260
3261
3262int vmsvga3dDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext)
3263{
3264 int rc;
3265 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3266 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnDXBindShaderIface, VERR_INVALID_STATE);
3267 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3268 AssertReturn(p3dState, VERR_INVALID_STATE);
3269
3270 PVMSVGA3DDXCONTEXT pDXContext;
3271 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3272 AssertRCReturn(rc, rc);
3273
3274 rc = pSvgaR3State->pFuncsDX->pfnDXBindShaderIface(pThisCC, pDXContext);
3275 return rc;
3276}
3277
3278
3279int vmsvga3dVBDXClearRenderTargetViewRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdVBDXClearRenderTargetViewRegion const *pCmd, uint32_t cRect, SVGASignedRect const *paRect)
3280{
3281 int rc;
3282 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3283 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnVBDXClearRenderTargetViewRegion, VERR_INVALID_STATE);
3284 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3285 AssertReturn(p3dState, VERR_INVALID_STATE);
3286
3287 PVMSVGA3DDXCONTEXT pDXContext;
3288 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3289 AssertRCReturn(rc, rc);
3290
3291 SVGA3dRenderTargetViewId const renderTargetViewId = pCmd->viewId;
3292
3293 ASSERT_GUEST_RETURN(pDXContext->cot.paRTView, VERR_INVALID_STATE);
3294 ASSERT_GUEST_RETURN(renderTargetViewId < pDXContext->cot.cRTView, VERR_INVALID_PARAMETER);
3295 ASSERT_GUEST_RETURN(cRect <= 65536, VERR_INVALID_PARAMETER); /* Arbitrary limit. */
3296 RT_UNTRUSTED_VALIDATED_FENCE();
3297
3298 rc = pSvgaR3State->pFuncsDX->pfnVBDXClearRenderTargetViewRegion(pThisCC, pDXContext, renderTargetViewId, &pCmd->color, cRect, paRect);
3299 return rc;
3300}
3301
3302
3303int vmsvga3dVBDXDefineVideoProcessor(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoProcessor const *pCmd)
3304{
3305 int rc;
3306 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3307 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoProcessor, VERR_INVALID_STATE);
3308 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3309 AssertReturn(p3dState, VERR_INVALID_STATE);
3310
3311 PVMSVGA3DDXCONTEXT pDXContext;
3312 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3313 AssertRCReturn(rc, rc);
3314
3315 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3316
3317 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3318 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3319 RT_UNTRUSTED_VALIDATED_FENCE();
3320
3321 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3322 pEntry->desc = pCmd->desc;
3323
3324 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoProcessor(pThisCC, pDXContext, videoProcessorId, pEntry);
3325 return rc;
3326}
3327
3328
3329int vmsvga3dVBDXDefineVideoDecoderOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoDecoderOutputView const *pCmd)
3330{
3331 int rc;
3332 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3333 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoDecoderOutputView, VERR_INVALID_STATE);
3334 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3335 AssertReturn(p3dState, VERR_INVALID_STATE);
3336
3337 PVMSVGA3DDXCONTEXT pDXContext;
3338 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3339 AssertRCReturn(rc, rc);
3340
3341 VBSVGA3dVideoDecoderOutputViewId const videoDecoderOutputViewId = pCmd->videoDecoderOutputViewId;
3342
3343 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoderOutputView, VERR_INVALID_STATE);
3344 ASSERT_GUEST_RETURN(videoDecoderOutputViewId < pDXContext->cot.cVideoDecoderOutputView, VERR_INVALID_PARAMETER);
3345 RT_UNTRUSTED_VALIDATED_FENCE();
3346
3347 VBSVGACOTableDXVideoDecoderOutputViewEntry *pEntry = &pDXContext->cot.paVideoDecoderOutputView[videoDecoderOutputViewId];
3348 pEntry->sid = pCmd->sid;
3349 pEntry->desc = pCmd->desc;
3350
3351 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoDecoderOutputView(pThisCC, pDXContext, videoDecoderOutputViewId, pEntry);
3352 return rc;
3353}
3354
3355
3356int vmsvga3dVBDXDefineVideoDecoder(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoDecoder const *pCmd)
3357{
3358 int rc;
3359 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3360 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoDecoder, VERR_INVALID_STATE);
3361 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3362 AssertReturn(p3dState, VERR_INVALID_STATE);
3363
3364 PVMSVGA3DDXCONTEXT pDXContext;
3365 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3366 AssertRCReturn(rc, rc);
3367
3368 VBSVGA3dVideoDecoderId const videoDecoderId = pCmd->videoDecoderId;
3369
3370 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoder, VERR_INVALID_STATE);
3371 ASSERT_GUEST_RETURN(videoDecoderId < pDXContext->cot.cVideoDecoder, VERR_INVALID_PARAMETER);
3372 RT_UNTRUSTED_VALIDATED_FENCE();
3373
3374 VBSVGACOTableDXVideoDecoderEntry *pEntry = &pDXContext->cot.paVideoDecoder[videoDecoderId];
3375 pEntry->desc = pCmd->desc;
3376 pEntry->config = pCmd->config;
3377 pEntry->vdovId = SVGA3D_INVALID_ID;
3378
3379 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoDecoder(pThisCC, pDXContext, videoDecoderId, pEntry);
3380 return rc;
3381}
3382
3383
3384int vmsvga3dVBDXVideoDecoderBeginFrame(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoDecoderBeginFrame const *pCmd)
3385{
3386 int rc;
3387 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3388 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoDecoderBeginFrame, VERR_INVALID_STATE);
3389 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3390 AssertReturn(p3dState, VERR_INVALID_STATE);
3391
3392 PVMSVGA3DDXCONTEXT pDXContext;
3393 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3394 AssertRCReturn(rc, rc);
3395
3396 VBSVGA3dVideoDecoderId const videoDecoderId = pCmd->videoDecoderId;
3397
3398 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoder, VERR_INVALID_STATE);
3399 ASSERT_GUEST_RETURN(videoDecoderId < pDXContext->cot.cVideoDecoder, VERR_INVALID_PARAMETER);
3400
3401 VBSVGA3dVideoDecoderOutputViewId const videoDecoderOutputViewId = pCmd->videoDecoderOutputViewId;
3402
3403 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoderOutputView, VERR_INVALID_STATE);
3404 ASSERT_GUEST_RETURN(videoDecoderOutputViewId < pDXContext->cot.cVideoDecoderOutputView, VERR_INVALID_PARAMETER);
3405 RT_UNTRUSTED_VALIDATED_FENCE();
3406
3407 VBSVGACOTableDXVideoDecoderEntry *pEntry = &pDXContext->cot.paVideoDecoder[videoDecoderId];
3408 pEntry->vdovId = videoDecoderOutputViewId;
3409
3410 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoDecoderBeginFrame(pThisCC, pDXContext, videoDecoderId, videoDecoderOutputViewId);
3411 return rc;
3412}
3413
3414
3415int vmsvga3dVBDXVideoDecoderSubmitBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoDecoderSubmitBuffers const *pCmd, uint32_t cBuffer, VBSVGA3dVideoDecoderBufferDesc const *paBufferDesc)
3416{
3417 int rc;
3418 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3419 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoDecoderSubmitBuffers, VERR_INVALID_STATE);
3420 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3421 AssertReturn(p3dState, VERR_INVALID_STATE);
3422
3423 PVMSVGA3DDXCONTEXT pDXContext;
3424 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3425 AssertRCReturn(rc, rc);
3426
3427 VBSVGA3dVideoDecoderId const videoDecoderId = pCmd->videoDecoderId;
3428
3429 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoder, VERR_INVALID_STATE);
3430 ASSERT_GUEST_RETURN(videoDecoderId < pDXContext->cot.cVideoDecoder, VERR_INVALID_PARAMETER);
3431 RT_UNTRUSTED_VALIDATED_FENCE();
3432
3433 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoDecoderSubmitBuffers(pThisCC, pDXContext, videoDecoderId, cBuffer, paBufferDesc);
3434 return rc;
3435}
3436
3437
3438int vmsvga3dVBDXVideoDecoderEndFrame(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoDecoderEndFrame const *pCmd)
3439{
3440 int rc;
3441 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3442 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoDecoderEndFrame, VERR_INVALID_STATE);
3443 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3444 AssertReturn(p3dState, VERR_INVALID_STATE);
3445
3446 PVMSVGA3DDXCONTEXT pDXContext;
3447 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3448 AssertRCReturn(rc, rc);
3449
3450 VBSVGA3dVideoDecoderId const videoDecoderId = pCmd->videoDecoderId;
3451
3452 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoder, VERR_INVALID_STATE);
3453 ASSERT_GUEST_RETURN(videoDecoderId < pDXContext->cot.cVideoDecoder, VERR_INVALID_PARAMETER);
3454 RT_UNTRUSTED_VALIDATED_FENCE();
3455
3456 VBSVGACOTableDXVideoDecoderEntry *pEntry = &pDXContext->cot.paVideoDecoder[videoDecoderId];
3457 pEntry->vdovId = SVGA3D_INVALID_ID;
3458
3459 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoDecoderEndFrame(pThisCC, pDXContext, videoDecoderId);
3460 return rc;
3461}
3462
3463
3464int vmsvga3dVBDXDefineVideoProcessorInputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoProcessorInputView const *pCmd)
3465{
3466 int rc;
3467 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3468 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoProcessorInputView, VERR_INVALID_STATE);
3469 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3470 AssertReturn(p3dState, VERR_INVALID_STATE);
3471
3472 PVMSVGA3DDXCONTEXT pDXContext;
3473 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3474 AssertRCReturn(rc, rc);
3475
3476 VBSVGA3dVideoProcessorInputViewId const videoProcessorInputViewId = pCmd->videoProcessorInputViewId;
3477
3478 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessorInputView, VERR_INVALID_STATE);
3479 ASSERT_GUEST_RETURN(videoProcessorInputViewId < pDXContext->cot.cVideoProcessorInputView, VERR_INVALID_PARAMETER);
3480 RT_UNTRUSTED_VALIDATED_FENCE();
3481
3482 VBSVGACOTableDXVideoProcessorInputViewEntry *pEntry = &pDXContext->cot.paVideoProcessorInputView[videoProcessorInputViewId];
3483 pEntry->sid = pCmd->sid;
3484 pEntry->contentDesc = pCmd->contentDesc;
3485 pEntry->desc = pCmd->desc;
3486
3487 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoProcessorInputView(pThisCC, pDXContext, videoProcessorInputViewId, pEntry);
3488 return rc;
3489}
3490
3491
3492int vmsvga3dVBDXDefineVideoProcessorOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoProcessorOutputView const *pCmd)
3493{
3494 int rc;
3495 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3496 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoProcessorOutputView, VERR_INVALID_STATE);
3497 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3498 AssertReturn(p3dState, VERR_INVALID_STATE);
3499
3500 PVMSVGA3DDXCONTEXT pDXContext;
3501 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3502 AssertRCReturn(rc, rc);
3503
3504 VBSVGA3dVideoProcessorOutputViewId const videoProcessorOutputViewId = pCmd->videoProcessorOutputViewId;
3505
3506 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessorOutputView, VERR_INVALID_STATE);
3507 ASSERT_GUEST_RETURN(videoProcessorOutputViewId < pDXContext->cot.cVideoProcessorOutputView, VERR_INVALID_PARAMETER);
3508 RT_UNTRUSTED_VALIDATED_FENCE();
3509
3510 VBSVGACOTableDXVideoProcessorOutputViewEntry *pEntry = &pDXContext->cot.paVideoProcessorOutputView[videoProcessorOutputViewId];
3511 pEntry->sid = pCmd->sid;
3512 pEntry->contentDesc = pCmd->contentDesc;
3513 pEntry->desc = pCmd->desc;
3514
3515 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDefineVideoProcessorOutputView(pThisCC, pDXContext, videoProcessorOutputViewId, pEntry);
3516 return rc;
3517}
3518
3519
3520int vmsvga3dVBDXVideoProcessorBlt(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorBlt const *pCmd, uint32_t cbCmd)
3521{
3522 int rc;
3523 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3524 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorBlt, VERR_INVALID_STATE);
3525 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3526 AssertReturn(p3dState, VERR_INVALID_STATE);
3527
3528 PVMSVGA3DDXCONTEXT pDXContext;
3529 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3530 AssertRCReturn(rc, rc);
3531
3532 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3533
3534 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3535 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3536
3537 VBSVGA3dVideoProcessorOutputViewId const videoProcessorOutputViewId = pCmd->videoProcessorOutputViewId;
3538
3539 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessorOutputView, VERR_INVALID_STATE);
3540 ASSERT_GUEST_RETURN(videoProcessorOutputViewId < pDXContext->cot.cVideoProcessorOutputView, VERR_INVALID_PARAMETER);
3541
3542 ASSERT_GUEST_RETURN(pCmd->streamCount < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
3543 RT_UNTRUSTED_VALIDATED_FENCE();
3544
3545 VBSVGA3dVideoProcessorStream const *pVPS = (VBSVGA3dVideoProcessorStream *)&pCmd[1];
3546 uint32_t cbLeft = cbCmd - sizeof(*pCmd);
3547 for (uint32_t i = 0; i < pCmd->streamCount; ++i)
3548 {
3549 ASSERT_GUEST_RETURN(cbLeft >= sizeof(VBSVGA3dVideoProcessorStream), VERR_INVALID_PARAMETER);
3550 RT_UNTRUSTED_VALIDATED_FENCE();
3551 cbLeft -= sizeof(VBSVGA3dVideoProcessorStream);
3552
3553 uint32_t const cMaxIds = cbLeft / sizeof(VBSVGA3dVideoProcessorInputViewId);
3554 ASSERT_GUEST_RETURN(pVPS->PastFrames < cMaxIds, VERR_INVALID_PARAMETER);
3555 ASSERT_GUEST_RETURN(pVPS->FutureFrames < cMaxIds, VERR_INVALID_PARAMETER);
3556 RT_UNTRUSTED_VALIDATED_FENCE();
3557
3558 uint32_t const cIds = (pVPS->StereoFormatSeparate == 0 ? 1 : 2) * (pVPS->PastFrames + 1 + pVPS->FutureFrames);
3559 ASSERT_GUEST_RETURN(cIds <= cMaxIds, VERR_INVALID_PARAMETER);
3560 RT_UNTRUSTED_VALIDATED_FENCE();
3561
3562 VBSVGA3dVideoProcessorInputViewId const *pId = (VBSVGA3dVideoProcessorInputViewId *)&pVPS[1];
3563 for (uint32_t j = 0; j < cIds; ++j)
3564 {
3565 VBSVGA3dVideoProcessorInputViewId const videoProcessorInputViewId = pId[j];
3566
3567 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessorInputView, VERR_INVALID_STATE);
3568 ASSERT_GUEST_RETURN(videoProcessorInputViewId < pDXContext->cot.cVideoProcessorInputView, VERR_INVALID_PARAMETER);
3569 RT_UNTRUSTED_VALIDATED_FENCE();
3570 }
3571
3572 pVPS = (VBSVGA3dVideoProcessorStream *)((uint8_t *)&pVPS[1] + cIds * sizeof(VBSVGA3dVideoProcessorInputViewId));
3573 cbLeft -= cIds * sizeof(VBSVGA3dVideoProcessorInputViewId);
3574 }
3575
3576 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorBlt(pThisCC, pDXContext,
3577 videoProcessorId, videoProcessorOutputViewId,
3578 pCmd->outputFrame, pCmd->streamCount,
3579 (VBSVGA3dVideoProcessorStream *)&pCmd[1]);
3580 return rc;
3581}
3582
3583
3584int vmsvga3dVBDXDestroyVideoDecoder(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoDecoder const *pCmd)
3585{
3586 int rc;
3587 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3588 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoDecoder, VERR_INVALID_STATE);
3589 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3590 AssertReturn(p3dState, VERR_INVALID_STATE);
3591
3592 PVMSVGA3DDXCONTEXT pDXContext;
3593 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3594 AssertRCReturn(rc, rc);
3595
3596 VBSVGA3dVideoDecoderId const videoDecoderId = pCmd->videoDecoderId;
3597
3598 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoder, VERR_INVALID_STATE);
3599 ASSERT_GUEST_RETURN(videoDecoderId < pDXContext->cot.cVideoDecoder, VERR_INVALID_PARAMETER);
3600 RT_UNTRUSTED_VALIDATED_FENCE();
3601
3602 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoDecoder(pThisCC, pDXContext, videoDecoderId);
3603
3604 VBSVGACOTableDXVideoDecoderEntry *pEntry = &pDXContext->cot.paVideoDecoder[videoDecoderId];
3605 RT_ZERO(*pEntry);
3606
3607 return rc;
3608}
3609
3610
3611int vmsvga3dVBDXDestroyVideoDecoderOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoDecoderOutputView const *pCmd)
3612{
3613 int rc;
3614 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3615 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoDecoderOutputView, VERR_INVALID_STATE);
3616 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3617 AssertReturn(p3dState, VERR_INVALID_STATE);
3618
3619 PVMSVGA3DDXCONTEXT pDXContext;
3620 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3621 AssertRCReturn(rc, rc);
3622
3623 VBSVGA3dVideoDecoderOutputViewId const videoDecoderOutputViewId = pCmd->videoDecoderOutputViewId;
3624
3625 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoDecoderOutputView, VERR_INVALID_STATE);
3626 ASSERT_GUEST_RETURN(videoDecoderOutputViewId < pDXContext->cot.cVideoDecoderOutputView, VERR_INVALID_PARAMETER);
3627 RT_UNTRUSTED_VALIDATED_FENCE();
3628
3629 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoDecoderOutputView(pThisCC, pDXContext, videoDecoderOutputViewId);
3630
3631 VBSVGACOTableDXVideoDecoderOutputViewEntry *pEntry = &pDXContext->cot.paVideoDecoderOutputView[videoDecoderOutputViewId];
3632 RT_ZERO(*pEntry);
3633
3634 return rc;
3635}
3636
3637
3638int vmsvga3dVBDXDestroyVideoProcessor(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoProcessor const *pCmd)
3639{
3640 int rc;
3641 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3642 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoProcessor, VERR_INVALID_STATE);
3643 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3644 AssertReturn(p3dState, VERR_INVALID_STATE);
3645
3646 PVMSVGA3DDXCONTEXT pDXContext;
3647 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3648 AssertRCReturn(rc, rc);
3649
3650 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3651
3652 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3653 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3654 RT_UNTRUSTED_VALIDATED_FENCE();
3655
3656 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoProcessor(pThisCC, pDXContext, videoProcessorId);
3657
3658 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3659 RT_ZERO(*pEntry);
3660
3661 return rc;
3662}
3663
3664
3665int vmsvga3dVBDXDestroyVideoProcessorInputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoProcessorInputView const *pCmd)
3666{
3667 int rc;
3668 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3669 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoProcessorInputView, VERR_INVALID_STATE);
3670 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3671 AssertReturn(p3dState, VERR_INVALID_STATE);
3672
3673 PVMSVGA3DDXCONTEXT pDXContext;
3674 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3675 AssertRCReturn(rc, rc);
3676
3677 VBSVGA3dVideoProcessorInputViewId const videoProcessorInputViewId = pCmd->videoProcessorInputViewId;
3678
3679 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessorInputView, VERR_INVALID_STATE);
3680 ASSERT_GUEST_RETURN(videoProcessorInputViewId < pDXContext->cot.cVideoProcessorInputView, VERR_INVALID_PARAMETER);
3681 RT_UNTRUSTED_VALIDATED_FENCE();
3682
3683 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoProcessorInputView(pThisCC, pDXContext, videoProcessorInputViewId);
3684
3685 VBSVGACOTableDXVideoProcessorInputViewEntry *pEntry = &pDXContext->cot.paVideoProcessorInputView[videoProcessorInputViewId];
3686 RT_ZERO(*pEntry);
3687
3688 return rc;
3689}
3690
3691
3692int vmsvga3dVBDXDestroyVideoProcessorOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoProcessorOutputView const *pCmd)
3693{
3694 int rc;
3695 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3696 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoProcessorOutputView, VERR_INVALID_STATE);
3697 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3698 AssertReturn(p3dState, VERR_INVALID_STATE);
3699
3700 PVMSVGA3DDXCONTEXT pDXContext;
3701 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3702 AssertRCReturn(rc, rc);
3703
3704 VBSVGA3dVideoProcessorOutputViewId const videoProcessorOutputViewId = pCmd->videoProcessorOutputViewId;
3705
3706 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessorOutputView, VERR_INVALID_STATE);
3707 ASSERT_GUEST_RETURN(videoProcessorOutputViewId < pDXContext->cot.cVideoProcessorOutputView, VERR_INVALID_PARAMETER);
3708 RT_UNTRUSTED_VALIDATED_FENCE();
3709
3710 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXDestroyVideoProcessorOutputView(pThisCC, pDXContext, videoProcessorOutputViewId);
3711
3712 VBSVGACOTableDXVideoProcessorOutputViewEntry *pEntry = &pDXContext->cot.paVideoProcessorOutputView[videoProcessorOutputViewId];
3713 RT_ZERO(*pEntry);
3714
3715 return rc;
3716}
3717
3718
3719int vmsvga3dVBDXVideoProcessorSetOutputTargetRect(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputTargetRect const *pCmd)
3720{
3721 int rc;
3722 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3723 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputTargetRect, VERR_INVALID_STATE);
3724 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3725 AssertReturn(p3dState, VERR_INVALID_STATE);
3726
3727 PVMSVGA3DDXCONTEXT pDXContext;
3728 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3729 AssertRCReturn(rc, rc);
3730
3731 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3732
3733 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3734 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3735 RT_UNTRUSTED_VALIDATED_FENCE();
3736
3737 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3738 pEntry->output.SetMask |= VBSVGA3D_VP_SET_OUTPUT_TARGET_RECT;
3739 pEntry->output.TargetRectEnable = RT_BOOL(pCmd->enable);
3740 pEntry->output.TargetRect = pCmd->outputRect;
3741
3742 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputTargetRect(pThisCC, pDXContext, videoProcessorId,
3743 pCmd->enable, pCmd->outputRect);
3744 return rc;
3745}
3746
3747
3748int vmsvga3dVBDXVideoProcessorSetOutputBackgroundColor(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputBackgroundColor const *pCmd)
3749{
3750 int rc;
3751 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3752 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputBackgroundColor, VERR_INVALID_STATE);
3753 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3754 AssertReturn(p3dState, VERR_INVALID_STATE);
3755
3756 PVMSVGA3DDXCONTEXT pDXContext;
3757 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3758 AssertRCReturn(rc, rc);
3759
3760 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3761
3762 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3763 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3764 RT_UNTRUSTED_VALIDATED_FENCE();
3765
3766 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3767 pEntry->output.SetMask |= VBSVGA3D_VP_SET_OUTPUT_BACKGROUND_COLOR;
3768 pEntry->output.BackgroundColorYCbCr = pCmd->ycbcr;
3769 pEntry->output.BackgroundColor = pCmd->color;
3770
3771 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputBackgroundColor(pThisCC, pDXContext, videoProcessorId, pCmd->ycbcr, pCmd->color);
3772 return rc;
3773}
3774
3775
3776int vmsvga3dVBDXVideoProcessorSetOutputColorSpace(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputColorSpace const *pCmd)
3777{
3778 int rc;
3779 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3780 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputColorSpace, VERR_INVALID_STATE);
3781 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3782 AssertReturn(p3dState, VERR_INVALID_STATE);
3783
3784 PVMSVGA3DDXCONTEXT pDXContext;
3785 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3786 AssertRCReturn(rc, rc);
3787
3788 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3789
3790 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3791 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3792 RT_UNTRUSTED_VALIDATED_FENCE();
3793
3794 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3795 pEntry->output.SetMask |= VBSVGA3D_VP_SET_OUTPUT_COLOR_SPACE;
3796 pEntry->output.ColorSpace = pCmd->colorSpace;
3797
3798 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputColorSpace(pThisCC, pDXContext, videoProcessorId, pCmd->colorSpace);
3799 return rc;
3800}
3801
3802
3803int vmsvga3dVBDXVideoProcessorSetOutputAlphaFillMode(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputAlphaFillMode const *pCmd)
3804{
3805 int rc;
3806 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3807 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputAlphaFillMode, VERR_INVALID_STATE);
3808 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3809 AssertReturn(p3dState, VERR_INVALID_STATE);
3810
3811 PVMSVGA3DDXCONTEXT pDXContext;
3812 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3813 AssertRCReturn(rc, rc);
3814
3815 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3816
3817 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3818 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3819 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
3820 RT_UNTRUSTED_VALIDATED_FENCE();
3821
3822 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3823 pEntry->output.SetMask |= VBSVGA3D_VP_SET_OUTPUT_ALPHA_FILL_MODE;
3824 pEntry->output.AlphaFillMode = pCmd->fillMode;
3825 pEntry->output.AlphaFillStreamIndex = pCmd->streamIndex;
3826
3827 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputAlphaFillMode(pThisCC, pDXContext, videoProcessorId, pCmd->fillMode, pCmd->streamIndex);
3828 return rc;
3829}
3830
3831
3832int vmsvga3dVBDXVideoProcessorSetOutputConstriction(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputConstriction const *pCmd)
3833{
3834 int rc;
3835 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3836 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputConstriction, VERR_INVALID_STATE);
3837 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3838 AssertReturn(p3dState, VERR_INVALID_STATE);
3839
3840 PVMSVGA3DDXCONTEXT pDXContext;
3841 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3842 AssertRCReturn(rc, rc);
3843
3844 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3845
3846 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3847 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3848 RT_UNTRUSTED_VALIDATED_FENCE();
3849
3850 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3851 pEntry->output.SetMask |= VBSVGA3D_VP_SET_OUTPUT_CONSTRICTION;
3852 pEntry->output.ConstrictionEnable = RT_BOOL(pCmd->enabled);
3853 pEntry->output.ConstrictionWidth = pCmd->width;
3854 pEntry->output.ConstrictionHeight = pCmd->height;
3855
3856 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputConstriction(pThisCC, pDXContext, videoProcessorId, pCmd->enabled, pCmd->width, pCmd->height);
3857 return rc;
3858}
3859
3860
3861int vmsvga3dVBDXVideoProcessorSetOutputStereoMode(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputStereoMode const *pCmd)
3862{
3863 int rc;
3864 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3865 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputStereoMode, VERR_INVALID_STATE);
3866 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3867 AssertReturn(p3dState, VERR_INVALID_STATE);
3868
3869 PVMSVGA3DDXCONTEXT pDXContext;
3870 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3871 AssertRCReturn(rc, rc);
3872
3873 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3874
3875 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3876 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3877 RT_UNTRUSTED_VALIDATED_FENCE();
3878
3879 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3880 pEntry->output.SetMask |= VBSVGA3D_VP_SET_OUTPUT_STEREO_MODE;
3881 pEntry->output.StereoModeEnable = RT_BOOL(pCmd->enable);
3882
3883 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetOutputStereoMode(pThisCC, pDXContext, videoProcessorId, pCmd->enable);
3884 return rc;
3885}
3886
3887
3888int vmsvga3dVBDXVideoProcessorSetStreamFrameFormat(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamFrameFormat const *pCmd)
3889{
3890 int rc;
3891 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3892 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamFrameFormat, VERR_INVALID_STATE);
3893 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3894 AssertReturn(p3dState, VERR_INVALID_STATE);
3895
3896 PVMSVGA3DDXCONTEXT pDXContext;
3897 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3898 AssertRCReturn(rc, rc);
3899
3900 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3901
3902 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3903 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3904 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
3905 RT_UNTRUSTED_VALIDATED_FENCE();
3906
3907 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3908 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
3909 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_FRAME_FORMAT;
3910 pStreamState->FrameFormat = pCmd->format;
3911
3912 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamFrameFormat(pThisCC, pDXContext, videoProcessorId, pCmd->streamIndex, pCmd->format);
3913 return rc;
3914}
3915
3916
3917int vmsvga3dVBDXVideoProcessorSetStreamColorSpace(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamColorSpace const *pCmd)
3918{
3919 int rc;
3920 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3921 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamColorSpace, VERR_INVALID_STATE);
3922 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3923 AssertReturn(p3dState, VERR_INVALID_STATE);
3924
3925 PVMSVGA3DDXCONTEXT pDXContext;
3926 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3927 AssertRCReturn(rc, rc);
3928
3929 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3930
3931 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3932 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3933 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
3934 RT_UNTRUSTED_VALIDATED_FENCE();
3935
3936 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3937 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
3938 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_COLOR_SPACE;
3939 pStreamState->ColorSpace = pCmd->colorSpace;
3940
3941 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamColorSpace(pThisCC, pDXContext, videoProcessorId, pCmd->streamIndex, pCmd->colorSpace);
3942 return rc;
3943}
3944
3945
3946int vmsvga3dVBDXVideoProcessorSetStreamOutputRate(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamOutputRate const *pCmd)
3947{
3948 int rc;
3949 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3950 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamOutputRate, VERR_INVALID_STATE);
3951 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3952 AssertReturn(p3dState, VERR_INVALID_STATE);
3953
3954 PVMSVGA3DDXCONTEXT pDXContext;
3955 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3956 AssertRCReturn(rc, rc);
3957
3958 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3959
3960 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3961 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3962 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
3963 RT_UNTRUSTED_VALIDATED_FENCE();
3964
3965 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3966 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
3967 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_OUTPUT_RATE;
3968 pStreamState->OutputRate = pCmd->outputRate;
3969 pStreamState->RepeatFrame = pCmd->repeatFrame;
3970 pStreamState->CustomRate = pCmd->customRate;
3971
3972 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamOutputRate(pThisCC, pDXContext, videoProcessorId,
3973 pCmd->streamIndex, pCmd->outputRate, pCmd->repeatFrame, pCmd->customRate);
3974 return rc;
3975}
3976
3977
3978int vmsvga3dVBDXVideoProcessorSetStreamSourceRect(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamSourceRect const *pCmd)
3979{
3980 int rc;
3981 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3982 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamSourceRect, VERR_INVALID_STATE);
3983 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
3984 AssertReturn(p3dState, VERR_INVALID_STATE);
3985
3986 PVMSVGA3DDXCONTEXT pDXContext;
3987 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
3988 AssertRCReturn(rc, rc);
3989
3990 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
3991
3992 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
3993 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
3994 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
3995 RT_UNTRUSTED_VALIDATED_FENCE();
3996
3997 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
3998 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
3999 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_SOURCE_RECT;
4000 pStreamState->SourceRectEnable = RT_BOOL(pCmd->enable);
4001 pStreamState->SourceRect = pCmd->sourceRect;
4002
4003 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamSourceRect(pThisCC, pDXContext, videoProcessorId,
4004 pCmd->streamIndex, pCmd->enable, pCmd->sourceRect);
4005 return rc;
4006}
4007
4008
4009int vmsvga3dVBDXVideoProcessorSetStreamDestRect(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamDestRect const *pCmd)
4010{
4011 int rc;
4012 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4013 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamDestRect, VERR_INVALID_STATE);
4014 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4015 AssertReturn(p3dState, VERR_INVALID_STATE);
4016
4017 PVMSVGA3DDXCONTEXT pDXContext;
4018 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4019 AssertRCReturn(rc, rc);
4020
4021 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4022
4023 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4024 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4025 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4026 RT_UNTRUSTED_VALIDATED_FENCE();
4027
4028 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4029 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4030 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_DEST_RECT;
4031 pStreamState->DestRectEnable = RT_BOOL(pCmd->enable);
4032 pStreamState->DestRect = pCmd->destRect;
4033
4034 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamDestRect(pThisCC, pDXContext, videoProcessorId,
4035 pCmd->streamIndex, pCmd->enable, pCmd->destRect);
4036 return rc;
4037}
4038
4039
4040int vmsvga3dVBDXVideoProcessorSetStreamAlpha(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamAlpha const *pCmd)
4041{
4042 int rc;
4043 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4044 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamAlpha, VERR_INVALID_STATE);
4045 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4046 AssertReturn(p3dState, VERR_INVALID_STATE);
4047
4048 PVMSVGA3DDXCONTEXT pDXContext;
4049 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4050 AssertRCReturn(rc, rc);
4051
4052 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4053
4054 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4055 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4056 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4057 RT_UNTRUSTED_VALIDATED_FENCE();
4058
4059 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4060 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4061 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_ALPHA;
4062 pStreamState->AlphaEnable = RT_BOOL(pCmd->enable);
4063 pStreamState->Alpha = pCmd->alpha;
4064
4065 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamAlpha(pThisCC, pDXContext, videoProcessorId,
4066 pCmd->streamIndex, pCmd->enable, pCmd->alpha);
4067 return rc;
4068}
4069
4070
4071int vmsvga3dVBDXVideoProcessorSetStreamPalette(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamPalette const *pCmd, uint32_t cEntries, uint32_t const *paEntries)
4072{
4073 int rc;
4074 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4075 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamPalette, VERR_INVALID_STATE);
4076 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4077 AssertReturn(p3dState, VERR_INVALID_STATE);
4078
4079 PVMSVGA3DDXCONTEXT pDXContext;
4080 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4081 AssertRCReturn(rc, rc);
4082
4083 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4084
4085 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4086 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4087 ASSERT_GUEST_RETURN(cEntries <= VBSVGA3D_MAX_VIDEO_PALETTE_ENTRIES, VERR_INVALID_PARAMETER);
4088 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4089 RT_UNTRUSTED_VALIDATED_FENCE();
4090
4091 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4092 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4093 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_PALETTE;
4094 pStreamState->PaletteCount = cEntries;
4095 memcpy(pStreamState->aPalette, paEntries, cEntries * sizeof(paEntries[0]));
4096
4097 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamPalette(pThisCC, pDXContext, videoProcessorId,
4098 pCmd->streamIndex, cEntries, paEntries);
4099 return rc;
4100}
4101
4102
4103int vmsvga3dVBDXVideoProcessorSetStreamPixelAspectRatio(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamPixelAspectRatio const *pCmd)
4104{
4105 int rc;
4106 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4107 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamPixelAspectRatio, VERR_INVALID_STATE);
4108 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4109 AssertReturn(p3dState, VERR_INVALID_STATE);
4110
4111 PVMSVGA3DDXCONTEXT pDXContext;
4112 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4113 AssertRCReturn(rc, rc);
4114
4115 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4116
4117 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4118 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4119 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4120 RT_UNTRUSTED_VALIDATED_FENCE();
4121
4122 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4123 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4124 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_ASPECT_RATIO;
4125 pStreamState->AspectRatioEnable = RT_BOOL(pCmd->enable);
4126 pStreamState->AspectSourceRatio = pCmd->sourceRatio;
4127 pStreamState->AspectDestRatio = pCmd->destRatio;
4128
4129 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamPixelAspectRatio(pThisCC, pDXContext, videoProcessorId,
4130 pCmd->streamIndex, pCmd->enable, pCmd->sourceRatio, pCmd->destRatio);
4131 return rc;
4132}
4133
4134
4135int vmsvga3dVBDXVideoProcessorSetStreamLumaKey(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamLumaKey const *pCmd)
4136{
4137 int rc;
4138 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4139 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamLumaKey, VERR_INVALID_STATE);
4140 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4141 AssertReturn(p3dState, VERR_INVALID_STATE);
4142
4143 PVMSVGA3DDXCONTEXT pDXContext;
4144 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4145 AssertRCReturn(rc, rc);
4146
4147 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4148
4149 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4150 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4151 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4152 RT_UNTRUSTED_VALIDATED_FENCE();
4153
4154 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4155 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4156 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_LUMA_KEY;
4157 pStreamState->LumaKeyEnable = RT_BOOL(pCmd->enable);
4158 pStreamState->LumaKeyLower = pCmd->lower;
4159 pStreamState->LumaKeyUpper = pCmd->upper;
4160
4161 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamLumaKey(pThisCC, pDXContext, videoProcessorId,
4162 pCmd->streamIndex, pCmd->enable, pCmd->lower, pCmd->upper);
4163 return rc;
4164}
4165
4166
4167int vmsvga3dVBDXVideoProcessorSetStreamStereoFormat(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamStereoFormat const *pCmd)
4168{
4169 int rc;
4170 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4171 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamStereoFormat, VERR_INVALID_STATE);
4172 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4173 AssertReturn(p3dState, VERR_INVALID_STATE);
4174
4175 PVMSVGA3DDXCONTEXT pDXContext;
4176 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4177 AssertRCReturn(rc, rc);
4178
4179 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4180
4181 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4182 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4183 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4184 RT_UNTRUSTED_VALIDATED_FENCE();
4185
4186 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4187 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4188 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_STEREO_FORMAT;
4189 pStreamState->StereoFormatEnable = RT_BOOL(pCmd->enable);
4190 pStreamState->StereoFormat = pCmd->stereoFormat;
4191 pStreamState->LeftViewFrame0 = pCmd->leftViewFrame0;
4192 pStreamState->BaseViewFrame0 = pCmd->baseViewFrame0;
4193 pStreamState->FlipMode = pCmd->flipMode;
4194 pStreamState->MonoOffset = pCmd->monoOffset;
4195
4196 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamStereoFormat(pThisCC, pDXContext, videoProcessorId,
4197 pCmd->streamIndex, pCmd->enable, pCmd->stereoFormat,
4198 pCmd->leftViewFrame0, pCmd->baseViewFrame0, pCmd->flipMode, pCmd->monoOffset);
4199 return rc;
4200}
4201
4202
4203int vmsvga3dVBDXVideoProcessorSetStreamAutoProcessingMode(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamAutoProcessingMode const *pCmd)
4204{
4205 int rc;
4206 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4207 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamAutoProcessingMode, VERR_INVALID_STATE);
4208 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4209 AssertReturn(p3dState, VERR_INVALID_STATE);
4210
4211 PVMSVGA3DDXCONTEXT pDXContext;
4212 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4213 AssertRCReturn(rc, rc);
4214
4215 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4216
4217 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4218 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4219 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4220 RT_UNTRUSTED_VALIDATED_FENCE();
4221
4222 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4223 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4224 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_AUTO_PROCESSING_MODE;
4225 pStreamState->AutoProcessingModeEnable = RT_BOOL(pCmd->enable);
4226
4227 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamAutoProcessingMode(pThisCC, pDXContext, videoProcessorId,
4228 pCmd->streamIndex, pCmd->enable);
4229 return rc;
4230}
4231
4232
4233int vmsvga3dVBDXVideoProcessorSetStreamFilter(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamFilter const *pCmd)
4234{
4235 int rc;
4236 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4237 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamFilter, VERR_INVALID_STATE);
4238 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4239 AssertReturn(p3dState, VERR_INVALID_STATE);
4240
4241 PVMSVGA3DDXCONTEXT pDXContext;
4242 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4243 AssertRCReturn(rc, rc);
4244
4245 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4246
4247 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4248 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4249 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4250 ASSERT_GUEST_RETURN(pCmd->filter < VBSVGA3D_VP_MAX_FILTER_COUNT, VERR_INVALID_PARAMETER);
4251 RT_UNTRUSTED_VALIDATED_FENCE();
4252
4253 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4254 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4255 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_FILTER;
4256 if (pCmd->enable)
4257 pStreamState->FilterEnableMask |= 1 << pCmd->filter;
4258 else
4259 pStreamState->FilterEnableMask &= ~(1 << pCmd->filter);
4260 pStreamState->aFilter[pCmd->filter].Level = pCmd->level;
4261
4262 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamFilter(pThisCC, pDXContext, videoProcessorId,
4263 pCmd->streamIndex, pCmd->enable, pCmd->filter, pCmd->level);
4264 return rc;
4265}
4266
4267
4268int vmsvga3dVBDXVideoProcessorSetStreamRotation(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamRotation const *pCmd)
4269{
4270 int rc;
4271 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4272 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamFilter, VERR_INVALID_STATE);
4273 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4274 AssertReturn(p3dState, VERR_INVALID_STATE);
4275
4276 PVMSVGA3DDXCONTEXT pDXContext;
4277 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4278 AssertRCReturn(rc, rc);
4279
4280 VBSVGA3dVideoProcessorId const videoProcessorId = pCmd->videoProcessorId;
4281
4282 ASSERT_GUEST_RETURN(pDXContext->cot.paVideoProcessor, VERR_INVALID_STATE);
4283 ASSERT_GUEST_RETURN(videoProcessorId < pDXContext->cot.cVideoProcessor, VERR_INVALID_PARAMETER);
4284 ASSERT_GUEST_RETURN(pCmd->streamIndex < VBSVGA3D_MAX_VIDEO_STREAMS, VERR_INVALID_PARAMETER);
4285 RT_UNTRUSTED_VALIDATED_FENCE();
4286
4287 VBSVGACOTableDXVideoProcessorEntry *pEntry = &pDXContext->cot.paVideoProcessor[videoProcessorId];
4288 VBSVGA3dVideoProcessorStreamState *pStreamState = &pEntry->aStreamState[pCmd->streamIndex];
4289 pStreamState->SetMask |= VBSVGA3D_VP_SET_STREAM_ROTATION;
4290 pStreamState->RotationEnable = RT_BOOL(pCmd->enable);
4291 pStreamState->Rotation = pCmd->rotation;
4292
4293 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXVideoProcessorSetStreamRotation(pThisCC, pDXContext, videoProcessorId,
4294 pCmd->streamIndex, pCmd->enable, pCmd->rotation);
4295 return rc;
4296}
4297
4298
4299int vmsvga3dVBDXGetVideoCapability(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXGetVideoCapability const *pCmd)
4300{
4301 int rc;
4302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4303 AssertReturn(pSvgaR3State->pFuncsDXVideo && pSvgaR3State->pFuncsDXVideo->pfnVBDXGetVideoCapability, VERR_INVALID_STATE);
4304 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4305 AssertReturn(p3dState, VERR_INVALID_STATE);
4306
4307 PVMSVGA3DDXCONTEXT pDXContext;
4308 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4309 AssertRCReturn(rc, rc);
4310
4311 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
4312 ASSERT_GUEST_RETURN(pMob, VERR_INVALID_PARAMETER);
4313
4314 uint32_t const cbMob = vmsvgaR3MobSize(pMob);
4315 ASSERT_GUEST_RETURN( pCmd->offsetInBytes < cbMob
4316 && pCmd->sizeInBytes <= cbMob - pCmd->offsetInBytes, VERR_INVALID_PARAMETER);
4317
4318 ASSERT_GUEST_RETURN(pCmd->sizeInBytes >= RT_UOFFSETOF(VBSVGA3dVideoCapabilityMobLayout, data), VERR_INVALID_PARAMETER);
4319 RT_UNTRUSTED_VALIDATED_FENCE();
4320
4321 /* Create a memory pointer for the MOB, which is accessible by host. */
4322 rc = vmsvgaR3MobBackingStoreCreate(pSvgaR3State, pMob, cbMob);
4323 AssertReturn(RT_SUCCESS(rc), rc);
4324
4325 /* Get pointer to the data. This will also verify the offset. */
4326 VBSVGA3dVideoCapabilityMobLayout *pCap = (VBSVGA3dVideoCapabilityMobLayout *)vmsvgaR3MobBackingStorePtr(pMob, pCmd->offsetInBytes);
4327 AssertReturnStmt(pCap, vmsvgaR3MobBackingStoreDelete(pSvgaR3State, pMob), VERR_INTERNAL_ERROR);
4328
4329 pCap->cbDataOut = 0;
4330 rc = pSvgaR3State->pFuncsDXVideo->pfnVBDXGetVideoCapability(pThisCC, pDXContext, pCmd->capability, &pCap->data,
4331 pCmd->sizeInBytes - RT_UOFFSETOF(VBSVGA3dVideoCapabilityMobLayout, data),
4332 &pCap->cbDataOut);
4333
4334 pCap->fenceValue = pCmd->fenceValue;
4335 if (RT_SUCCESS(rc))
4336 vmsvgaR3MobBackingStoreWriteToGuest(pSvgaR3State, pMob);
4337
4338 vmsvgaR3MobBackingStoreDelete(pSvgaR3State, pMob);
4339 return rc;
4340}
4341
4342
4343int vmsvga3dVBDXClearRTV(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXClearView const *pCmd, uint32_t cRect, SVGASignedRect const *paRect)
4344{
4345 int rc;
4346 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4347 AssertReturn(pSvgaR3State->pFuncsDX && pSvgaR3State->pFuncsDX->pfnVBDXClearRenderTargetViewRegion, VERR_INVALID_STATE);
4348 PVMSVGA3DSTATE p3dState = pThisCC->svga.p3dState;
4349 AssertReturn(p3dState, VERR_INVALID_STATE);
4350
4351 PVMSVGA3DDXCONTEXT pDXContext;
4352 rc = vmsvga3dDXContextFromCid(p3dState, idDXContext, &pDXContext);
4353 AssertRCReturn(rc, rc);
4354
4355 SVGA3dRenderTargetViewId const renderTargetViewId = pCmd->viewId;
4356
4357 ASSERT_GUEST_RETURN(pDXContext->cot.paRTView, VERR_INVALID_STATE);
4358 ASSERT_GUEST_RETURN(renderTargetViewId < pDXContext->cot.cRTView, VERR_INVALID_PARAMETER);
4359 ASSERT_GUEST_RETURN(cRect <= 65536, VERR_INVALID_PARAMETER); /* Arbitrary limit. */
4360 RT_UNTRUSTED_VALIDATED_FENCE();
4361
4362 rc = pSvgaR3State->pFuncsDX->pfnVBDXClearRenderTargetViewRegion(pThisCC, pDXContext, renderTargetViewId, &pCmd->color, cRect, paRect);
4363 return rc;
4364}
4365
4366