DevVGA-SVGA.cpp@ 83142

Last change on this file since 83142 was 83142, checked in by vboxsync, 5 years ago
bugref:9637. Sending monitor positions (offsets) from GAs to svga device since vmwgfx fails to do so.
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1	/* $Id: DevVGA-SVGA.cpp 83142 2020-02-24 19:24:26Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdEscape;
271	STAMCOUNTER StatR3CmdDefineScreen;
272	STAMCOUNTER StatR3CmdDestroyScreen;
273	STAMCOUNTER StatR3CmdDefineGmrFb;
274	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
275	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
276	STAMCOUNTER StatR3CmdAnnotationFill;
277	STAMCOUNTER StatR3CmdAnnotationCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
279	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
280	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
281	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
282	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
283	STAMCOUNTER StatR3Cmd3dSurfaceDma;
284	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
285	STAMCOUNTER StatR3Cmd3dContextDefine;
286	STAMCOUNTER StatR3Cmd3dContextDestroy;
287	STAMCOUNTER StatR3Cmd3dSetTransform;
288	STAMCOUNTER StatR3Cmd3dSetZRange;
289	STAMCOUNTER StatR3Cmd3dSetRenderState;
290	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
291	STAMCOUNTER StatR3Cmd3dSetTextureState;
292	STAMCOUNTER StatR3Cmd3dSetMaterial;
293	STAMCOUNTER StatR3Cmd3dSetLightData;
294	STAMCOUNTER StatR3Cmd3dSetLightEnable;
295	STAMCOUNTER StatR3Cmd3dSetViewPort;
296	STAMCOUNTER StatR3Cmd3dSetClipPlane;
297	STAMCOUNTER StatR3Cmd3dClear;
298	STAMCOUNTER StatR3Cmd3dPresent;
299	STAMCOUNTER StatR3Cmd3dPresentReadBack;
300	STAMCOUNTER StatR3Cmd3dShaderDefine;
301	STAMCOUNTER StatR3Cmd3dShaderDestroy;
302	STAMCOUNTER StatR3Cmd3dSetShader;
303	STAMCOUNTER StatR3Cmd3dSetShaderConst;
304	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
305	STAMCOUNTER StatR3Cmd3dSetScissorRect;
306	STAMCOUNTER StatR3Cmd3dBeginQuery;
307	STAMCOUNTER StatR3Cmd3dEndQuery;
308	STAMCOUNTER StatR3Cmd3dWaitForQuery;
309	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
310	STAMCOUNTER StatR3Cmd3dActivateSurface;
311	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
312
313	STAMCOUNTER StatR3RegConfigDoneWr;
314	STAMCOUNTER StatR3RegGmrDescriptorWr;
315	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
316	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
317
318	STAMCOUNTER StatFifoCommands;
319	STAMCOUNTER StatFifoErrors;
320	STAMCOUNTER StatFifoUnkCmds;
321	STAMCOUNTER StatFifoTodoTimeout;
322	STAMCOUNTER StatFifoTodoWoken;
323	STAMPROFILE StatFifoStalls;
324	STAMPROFILE StatFifoExtendedSleep;
325	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
326	STAMCOUNTER StatFifoAccessHandler;
327	# endif
328	STAMCOUNTER StatFifoCursorFetchAgain;
329	STAMCOUNTER StatFifoCursorNoChange;
330	STAMCOUNTER StatFifoCursorPosition;
331	STAMCOUNTER StatFifoCursorVisiblity;
332	STAMCOUNTER StatFifoWatchdogWakeUps;
333	} VMSVGAR3STATE, *PVMSVGAR3STATE;
334	#endif /* IN_RING3 */
335
336
337	/*********************************************************************************************************************************
338	* Internal Functions *
339	*********************************************************************************************************************************/
340	#ifdef IN_RING3
341	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
342	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
343	# endif
344	# ifdef DEBUG_GMR_ACCESS
345	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
346	# endif
347	#endif
348
349
350	/*********************************************************************************************************************************
351	* Global Variables *
352	*********************************************************************************************************************************/
353	#ifdef IN_RING3
354
355	/**
356	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
357	*/
358	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
359	{
360	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
361	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
362	SSMFIELD_ENTRY_TERM()
363	};
364
365	/**
366	* SSM descriptor table for the GMR structure.
367	*/
368	static SSMFIELD const g_aGMRFields[] =
369	{
370	SSMFIELD_ENTRY( GMR, cMaxPages),
371	SSMFIELD_ENTRY( GMR, cbTotal),
372	SSMFIELD_ENTRY( GMR, numDescriptors),
373	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
374	SSMFIELD_ENTRY_TERM()
375	};
376
377	/**
378	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
379	*/
380	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
381	{
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
393	SSMFIELD_ENTRY_TERM()
394	};
395
396	/**
397	* SSM descriptor table for the VMSVGAR3STATE structure.
398	*/
399	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
400	{
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
409	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
412	#ifdef VMSVGA_USE_EMT_HALT_CODE
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
414	#else
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
416	#endif
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
480
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
488	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
490	# endif
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
495
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	/**
500	* SSM descriptor table for the VGAState.svga structure.
501	*/
502	static SSMFIELD const g_aVGAStateSVGAFields[] =
503	{
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
524	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
525	SSMFIELD_ENTRY( VMSVGAState, uWidth),
526	SSMFIELD_ENTRY( VMSVGAState, uHeight),
527	SSMFIELD_ENTRY( VMSVGAState, uBpp),
528	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
529	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
530	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
531	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
532	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
533	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
534	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
535	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
536	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
537	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
538	SSMFIELD_ENTRY_TERM()
539	};
540	#endif /* IN_RING3 */
541
542
543	/*********************************************************************************************************************************
544	* Internal Functions *
545	*********************************************************************************************************************************/
546	#ifdef IN_RING3
547	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
548	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
549	uint32_t uVersion, uint32_t uPass);
550	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
551	# ifdef VBOX_WITH_VMSVGA3D
552	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
553	# endif /* VBOX_WITH_VMSVGA3D */
554	#endif /* IN_RING3 */
555
556
557
558	#ifdef IN_RING3
559	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
560	{
561	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
562	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
563	&& pSVGAState
564	&& pSVGAState->aScreens[idScreen].fDefined)
565	{
566	return &pSVGAState->aScreens[idScreen];
567	}
568	return NULL;
569	}
570	#endif /* IN_RING3 */
571
572	#ifdef LOG_ENABLED
573
574	/**
575	* Index register string name lookup
576	*
577	* @returns Index register string or "UNKNOWN"
578	* @param pThis The shared VGA/VMSVGA state.
579	* @param idxReg The index register.
580	*/
581	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
582	{
583	switch (idxReg)
584	{
585	case SVGA_REG_ID: return "SVGA_REG_ID";
586	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
587	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
588	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
589	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
590	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
591	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
592	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
593	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
594	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
595	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
596	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
597	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
598	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
599	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
600	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
601	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
602	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
603	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
604	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
605	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
606	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
607	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
608	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
609	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
610	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
611	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
612	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
613	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
614	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
615	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
616	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
617	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
618	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
619	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
620	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
621	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
622	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
623	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
624	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
625	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
626	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
627	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
628	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
629	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
630	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
631	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
632	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
633	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
634	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
635
636	default:
637	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
638	return "SVGA_SCRATCH_BASE reg";
639	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
640	return "SVGA_PALETTE_BASE reg";
641	return "UNKNOWN";
642	}
643	}
644
645	#ifdef IN_RING3
646	/**
647	* FIFO command name lookup
648	*
649	* @returns FIFO command string or "UNKNOWN"
650	* @param u32Cmd FIFO command
651	*/
652	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
653	{
654	switch (u32Cmd)
655	{
656	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
657	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
658	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
659	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
660	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
661	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
662	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
663	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
664	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
665	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
666	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
667	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
668	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
669	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
670	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
671	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
672	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
673	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
674	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
675	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
676	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
677	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
678	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
679	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
680	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
681	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
682	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
683	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
684	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
685	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
686	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
687	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
688	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
689	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
690	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
691	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
692	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
693	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
694	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
695	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
696	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
697	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
698	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
699	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
700	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
701	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
702	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
703	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
704	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
705	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
706	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
707	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
708	default: return "UNKNOWN";
709	}
710	}
711	# endif /* IN_RING3 */
712
713	#endif /* LOG_ENABLED */
714
715	#ifdef IN_RING3
716	/**
717	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
718	*/
719	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
720	{
721	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
722	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
723
724	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
725	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
726
727	/** @todo Test how it interacts with multiple screen objects. */
728	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
729	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
730	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
731
732	if (x < uWidth)
733	{
734	pThis->svga.viewport.x = x;
735	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
736	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
737	}
738	else
739	{
740	pThis->svga.viewport.x = uWidth;
741	pThis->svga.viewport.cx = 0;
742	pThis->svga.viewport.xRight = uWidth;
743	}
744	if (y < uHeight)
745	{
746	pThis->svga.viewport.y = y;
747	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
748	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
749	pThis->svga.viewport.yHighWC = uHeight - y;
750	}
751	else
752	{
753	pThis->svga.viewport.y = uHeight;
754	pThis->svga.viewport.cy = 0;
755	pThis->svga.viewport.yLowWC = 0;
756	pThis->svga.viewport.yHighWC = 0;
757	}
758
759	# ifdef VBOX_WITH_VMSVGA3D
760	/*
761	* Now inform the 3D backend.
762	*/
763	if (pThis->svga.f3DEnabled)
764	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
765	# else
766	RT_NOREF(OldViewport);
767	# endif
768	}
769	#endif /* IN_RING3 */
770
771	/**
772	* Read port register
773	*
774	* @returns VBox status code.
775	* @param pDevIns The device instance.
776	* @param pThis The shared VGA/VMSVGA state.
777	* @param pu32 Where to store the read value
778	*/
779	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
780	{
781	#ifdef IN_RING3
782	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
783	#endif
784	int rc = VINF_SUCCESS;
785	*pu32 = 0;
786
787	/* Rough index register validation. */
788	uint32_t idxReg = pThis->svga.u32IndexReg;
789	#if !defined(IN_RING3) && defined(VBOX_STRICT)
790	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
791	VINF_IOM_R3_IOPORT_READ);
792	#else
793	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
794	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
795	VINF_SUCCESS);
796	#endif
797	RT_UNTRUSTED_VALIDATED_FENCE();
798
799	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
800	if ( idxReg >= SVGA_REG_CAPABILITIES
801	&& pThis->svga.u32SVGAId == SVGA_ID_0)
802	{
803	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
804	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
805	}
806
807	switch (idxReg)
808	{
809	case SVGA_REG_ID:
810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
811	*pu32 = pThis->svga.u32SVGAId;
812	break;
813
814	case SVGA_REG_ENABLE:
815	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
816	*pu32 = pThis->svga.fEnabled;
817	break;
818
819	case SVGA_REG_WIDTH:
820	{
821	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
822	if ( pThis->svga.fEnabled
823	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
824	*pu32 = pThis->svga.uWidth;
825	else
826	{
827	#ifndef IN_RING3
828	rc = VINF_IOM_R3_IOPORT_READ;
829	#else
830	*pu32 = pThisCC->pDrv->cx;
831	#endif
832	}
833	break;
834	}
835
836	case SVGA_REG_HEIGHT:
837	{
838	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
839	if ( pThis->svga.fEnabled
840	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
841	*pu32 = pThis->svga.uHeight;
842	else
843	{
844	#ifndef IN_RING3
845	rc = VINF_IOM_R3_IOPORT_READ;
846	#else
847	*pu32 = pThisCC->pDrv->cy;
848	#endif
849	}
850	break;
851	}
852
853	case SVGA_REG_MAX_WIDTH:
854	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
855	*pu32 = pThis->svga.u32MaxWidth;
856	break;
857
858	case SVGA_REG_MAX_HEIGHT:
859	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
860	*pu32 = pThis->svga.u32MaxHeight;
861	break;
862
863	case SVGA_REG_DEPTH:
864	/* This returns the color depth of the current mode. */
865	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
866	switch (pThis->svga.uBpp)
867	{
868	case 15:
869	case 16:
870	case 24:
871	*pu32 = pThis->svga.uBpp;
872	break;
873
874	default:
875	case 32:
876	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
877	break;
878	}
879	break;
880
881	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
882	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
883	if ( pThis->svga.fEnabled
884	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
885	*pu32 = pThis->svga.uBpp;
886	else
887	{
888	#ifndef IN_RING3
889	rc = VINF_IOM_R3_IOPORT_READ;
890	#else
891	*pu32 = pThisCC->pDrv->cBits;
892	#endif
893	}
894	break;
895
896	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
897	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
898	if ( pThis->svga.fEnabled
899	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
900	*pu32 = (pThis->svga.uBpp + 7) & ~7;
901	else
902	{
903	#ifndef IN_RING3
904	rc = VINF_IOM_R3_IOPORT_READ;
905	#else
906	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
907	#endif
908	}
909	break;
910
911	case SVGA_REG_PSEUDOCOLOR:
912	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
913	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
914	break;
915
916	case SVGA_REG_RED_MASK:
917	case SVGA_REG_GREEN_MASK:
918	case SVGA_REG_BLUE_MASK:
919	{
920	uint32_t uBpp;
921
922	if ( pThis->svga.fEnabled
923	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
924	{
925	uBpp = pThis->svga.uBpp;
926	}
927	else
928	{
929	#ifndef IN_RING3
930	rc = VINF_IOM_R3_IOPORT_READ;
931	break;
932	#else
933	uBpp = pThisCC->pDrv->cBits;
934	#endif
935	}
936	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
937	switch (uBpp)
938	{
939	case 8:
940	u32RedMask = 0x07;
941	u32GreenMask = 0x38;
942	u32BlueMask = 0xc0;
943	break;
944
945	case 15:
946	u32RedMask = 0x0000001f;
947	u32GreenMask = 0x000003e0;
948	u32BlueMask = 0x00007c00;
949	break;
950
951	case 16:
952	u32RedMask = 0x0000001f;
953	u32GreenMask = 0x000007e0;
954	u32BlueMask = 0x0000f800;
955	break;
956
957	case 24:
958	case 32:
959	default:
960	u32RedMask = 0x00ff0000;
961	u32GreenMask = 0x0000ff00;
962	u32BlueMask = 0x000000ff;
963	break;
964	}
965	switch (idxReg)
966	{
967	case SVGA_REG_RED_MASK:
968	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
969	*pu32 = u32RedMask;
970	break;
971
972	case SVGA_REG_GREEN_MASK:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
974	*pu32 = u32GreenMask;
975	break;
976
977	case SVGA_REG_BLUE_MASK:
978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
979	*pu32 = u32BlueMask;
980	break;
981	}
982	break;
983	}
984
985	case SVGA_REG_BYTES_PER_LINE:
986	{
987	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
988	if ( pThis->svga.fEnabled
989	&& pThis->svga.cbScanline)
990	*pu32 = pThis->svga.cbScanline;
991	else
992	{
993	#ifndef IN_RING3
994	rc = VINF_IOM_R3_IOPORT_READ;
995	#else
996	*pu32 = pThisCC->pDrv->cbScanline;
997	#endif
998	}
999	break;
1000	}
1001
1002	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1003	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1004	*pu32 = pThis->vram_size;
1005	break;
1006
1007	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1008	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1009	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1010	*pu32 = pThis->GCPhysVRAM;
1011	break;
1012
1013	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1015	/* Always zero in our case. */
1016	*pu32 = 0;
1017	break;
1018
1019	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1020	{
1021	#ifndef IN_RING3
1022	rc = VINF_IOM_R3_IOPORT_READ;
1023	#else
1024	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1025
1026	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1027	if ( pThis->svga.fEnabled
1028	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1029	{
1030	/* Hardware enabled; return real framebuffer size .*/
1031	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1032	}
1033	else
1034	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1035
1036	pu32 = RT_MIN(pThis->vram_size, pu32);
1037	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1038	#endif
1039	break;
1040	}
1041
1042	case SVGA_REG_CAPABILITIES:
1043	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1044	*pu32 = pThis->svga.u32RegCaps;
1045	break;
1046
1047	case SVGA_REG_MEM_START: /* FIFO start */
1048	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1049	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1050	*pu32 = pThis->svga.GCPhysFIFO;
1051	break;
1052
1053	case SVGA_REG_MEM_SIZE: /* FIFO size */
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1055	*pu32 = pThis->svga.cbFIFO;
1056	break;
1057
1058	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1060	*pu32 = pThis->svga.fConfigured;
1061	break;
1062
1063	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1065	*pu32 = 0;
1066	break;
1067
1068	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1069	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1070	if (pThis->svga.fBusy)
1071	{
1072	#ifndef IN_RING3
1073	/* Go to ring-3 and halt the CPU. */
1074	rc = VINF_IOM_R3_IOPORT_READ;
1075	RT_NOREF(pDevIns);
1076	break;
1077	#else
1078	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1079	/* The guest is basically doing a HLT via the device here, but with
1080	a special wake up condition on FIFO completion. */
1081	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1082	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1083	PVM pVM = PDMDevHlpGetVM(pDevIns);
1084	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1085	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1086	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1087	if (pThis->svga.fBusy)
1088	{
1089	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1090	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1091	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1092	}
1093	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1094	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1095	# else
1096
1097	/* Delay the EMT a bit so the FIFO and others can get some work done.
1098	This used to be a crude 50 ms sleep. The current code tries to be
1099	more efficient, but the consept is still very crude. */
1100	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1101	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1102	RTThreadYield();
1103	if (pThis->svga.fBusy)
1104	{
1105	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1106
1107	if (pThis->svga.fBusy && cRefs == 1)
1108	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1109	if (pThis->svga.fBusy)
1110	{
1111	/** @todo If this code is going to stay, we need to call into the halt/wait
1112	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1113	* suffer when the guest is polling on a busy FIFO. */
1114	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1115	if (cNsMaxWait >= RT_NS_100US)
1116	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1117	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1118	RT_MIN(cNsMaxWait, RT_NS_10MS));
1119	}
1120
1121	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1122	}
1123	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1124	# endif
1125	*pu32 = pThis->svga.fBusy != 0;
1126	#endif
1127	}
1128	else
1129	*pu32 = false;
1130	break;
1131
1132	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1134	*pu32 = pThis->svga.u32GuestId;
1135	break;
1136
1137	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1139	*pu32 = pThis->svga.cScratchRegion;
1140	break;
1141
1142	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1144	*pu32 = SVGA_FIFO_NUM_REGS;
1145	break;
1146
1147	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1149	*pu32 = pThis->svga.u32PitchLock;
1150	break;
1151
1152	case SVGA_REG_IRQMASK: /* Interrupt mask */
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1154	*pu32 = pThis->svga.u32IrqMask;
1155	break;
1156
1157	/* See "Guest memory regions" below. */
1158	case SVGA_REG_GMR_ID:
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1160	*pu32 = pThis->svga.u32CurrentGMRId;
1161	break;
1162
1163	case SVGA_REG_GMR_DESCRIPTOR:
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1165	/* Write only */
1166	*pu32 = 0;
1167	break;
1168
1169	case SVGA_REG_GMR_MAX_IDS:
1170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1171	*pu32 = pThis->svga.cGMR;
1172	break;
1173
1174	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1175	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1176	*pu32 = VMSVGA_MAX_GMR_PAGES;
1177	break;
1178
1179	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1180	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1181	*pu32 = pThis->svga.fTraces;
1182	break;
1183
1184	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1186	*pu32 = VMSVGA_MAX_GMR_PAGES;
1187	break;
1188
1189	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1190	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1191	*pu32 = VMSVGA_SURFACE_SIZE;
1192	break;
1193
1194	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1195	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1196	break;
1197
1198	/* Mouse cursor support. */
1199	case SVGA_REG_CURSOR_ID:
1200	case SVGA_REG_CURSOR_X:
1201	case SVGA_REG_CURSOR_Y:
1202	case SVGA_REG_CURSOR_ON:
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1204	break;
1205
1206	/* Legacy multi-monitor support */
1207	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1209	*pu32 = 1;
1210	break;
1211
1212	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1214	*pu32 = 0;
1215	break;
1216
1217	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1219	*pu32 = 0;
1220	break;
1221
1222	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1224	*pu32 = 0;
1225	break;
1226
1227	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1229	*pu32 = 0;
1230	break;
1231
1232	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1234	*pu32 = pThis->svga.uWidth;
1235	break;
1236
1237	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1239	*pu32 = pThis->svga.uHeight;
1240	break;
1241
1242	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1244	/* We must return something sensible here otherwise the Linux driver
1245	will take a legacy code path without 3d support. This number also
1246	limits how many screens Linux guests will allow. */
1247	*pu32 = pThis->cMonitors;
1248	break;
1249
1250	default:
1251	{
1252	uint32_t offReg;
1253	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1254	{
1255	RT_UNTRUSTED_VALIDATED_FENCE();
1256	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1257	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1258	}
1259	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1260	{
1261	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1262	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1263	RT_UNTRUSTED_VALIDATED_FENCE();
1264	uint32_t u32 = pThis->last_palette[offReg / 3];
1265	switch (offReg % 3)
1266	{
1267	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1268	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1269	case 2: pu32 = u32 & 0xff; break; / blue */
1270	}
1271	}
1272	else
1273	{
1274	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1275	rc = VINF_IOM_R3_IOPORT_READ;
1276	#else
1277	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1278
1279	/* Do not assert. The guest might be reading all registers. */
1280	LogFunc(("Unknown reg=%#x\n", idxReg));
1281	#endif
1282	}
1283	break;
1284	}
1285	}
1286	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1287	return rc;
1288	}
1289
1290	#ifdef IN_RING3
1291	/**
1292	* Updating screen information in API
1293	*
1294	* @param pThis The The shared VGA/VMSVGA instance data.
1295	* @param pThisCC The VGA/VMSVGA state for ring-3.
1296	*/
1297	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
1298	{
1299	int rc;
1300
1301	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1302
1303	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1304	{
1305	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1306	if (!pScreen->fModified)
1307	continue;
1308
1309	pScreen->fModified = false;
1310
1311	VBVAINFOVIEW view;
1312	RT_ZERO(view);
1313	view.u32ViewIndex = pScreen->idScreen;
1314	// view.u32ViewOffset = 0;
1315	view.u32ViewSize = pThis->vram_size;
1316	view.u32MaxScreenSize = pThis->vram_size;
1317
1318	VBVAINFOSCREEN screen;
1319	RT_ZERO(screen);
1320	screen.u32ViewIndex = pScreen->idScreen;
1321
1322	if (pScreen->fDefined)
1323	{
1324	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1325	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1326	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1327	{
1328	Assert(pThis->svga.fGFBRegisters);
1329	continue;
1330	}
1331
1332	screen.i32OriginX = pScreen->xOrigin;
1333	screen.i32OriginY = pScreen->yOrigin;
1334	screen.u32StartOffset = pScreen->offVRAM;
1335	screen.u32LineSize = pScreen->cbPitch;
1336	screen.u32Width = pScreen->cWidth;
1337	screen.u32Height = pScreen->cHeight;
1338	screen.u16BitsPerPixel = pScreen->cBpp;
1339	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1340	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1341	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1342	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1343	}
1344	else
1345	{
1346	/* Screen is destroyed. */
1347	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1348	}
1349
1350	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1351	AssertRC(rc);
1352	}
1353	}
1354
1355	/**
1356	* Apply the current resolution settings to change the video mode.
1357	*
1358	* @returns VBox status code.
1359	* @param pThis The shared VGA state.
1360	* @param pThisCC The ring-3 VGA state.
1361	*/
1362	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1363	{
1364	/* Always do changemode on FIFO thread. */
1365	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1366
1367	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1368
1369	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1370
1371	if (pThis->svga.fGFBRegisters)
1372	{
1373	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1374	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1375	* deletes all screens other than screen #0, and redefines screen
1376	* #0 according to the specified mode. Drivers that use
1377	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1378	*/
1379
1380	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1381	pScreen->fDefined = true;
1382	pScreen->fModified = true;
1383	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1384	pScreen->idScreen = 0;
1385	pScreen->xOrigin = 0;
1386	pScreen->yOrigin = 0;
1387	pScreen->offVRAM = 0;
1388	pScreen->cbPitch = pThis->svga.cbScanline;
1389	pScreen->cWidth = pThis->svga.uWidth;
1390	pScreen->cHeight = pThis->svga.uHeight;
1391	pScreen->cBpp = pThis->svga.uBpp;
1392
1393	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1394	{
1395	/* Delete screen. */
1396	pScreen = &pSVGAState->aScreens[iScreen];
1397	if (pScreen->fDefined)
1398	{
1399	pScreen->fModified = true;
1400	pScreen->fDefined = false;
1401	}
1402	}
1403	}
1404	else
1405	{
1406	/* "If Screen Objects are supported, they can be used to fully
1407	* replace the functionality provided by the framebuffer registers
1408	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1409	*/
1410	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1411	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1412	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1413	}
1414
1415	vmsvgaR3VBVAResize(pThis, pThisCC);
1416
1417	/* Last stuff. For the VGA device screenshot. */
1418	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1419	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1420	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1421	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1422	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1423
1424	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1425	if ( pThis->svga.viewport.cx == 0
1426	&& pThis->svga.viewport.cy == 0)
1427	{
1428	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1429	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1430	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1431	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1432	pThis->svga.viewport.yLowWC = 0;
1433	}
1434
1435	return VINF_SUCCESS;
1436	}
1437
1438	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1439	{
1440	VBVACMDHDR cmd;
1441	cmd.x = (int16_t)(pScreen->xOrigin + x);
1442	cmd.y = (int16_t)(pScreen->yOrigin + y);
1443	cmd.w = (uint16_t)w;
1444	cmd.h = (uint16_t)h;
1445
1446	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1447	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1448	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1449	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1450
1451	return VINF_SUCCESS;
1452	}
1453
1454	#endif /* IN_RING3 */
1455	#if defined(IN_RING0) \|\| defined(IN_RING3)
1456
1457	/**
1458	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1459	*
1460	* @param pThis The shared VGA/VMSVGA instance data.
1461	* @param pThisCC The VGA/VMSVGA state for the current context.
1462	* @param fState The busy state.
1463	*/
1464	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1465	{
1466	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1467
1468	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1469	{
1470	/* Race / unfortunately scheduling. Highly unlikly. */
1471	uint32_t cLoops = 64;
1472	do
1473	{
1474	ASMNopPause();
1475	fState = (pThis->svga.fBusy != 0);
1476	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1477	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1478	}
1479	}
1480
1481
1482	/**
1483	* Update the scanline pitch in response to the guest changing mode
1484	* width/bpp.
1485	*
1486	* @param pThis The shared VGA/VMSVGA state.
1487	* @param pThisCC The VGA/VMSVGA state for the current context.
1488	*/
1489	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1490	{
1491	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1492	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1493	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1494	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1495
1496	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1497	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1498	* location but it has a different meaning.
1499	*/
1500	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1501	uFifoPitchLock = 0;
1502
1503	/* Sanitize values. */
1504	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1505	uFifoPitchLock = 0;
1506	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1507	uRegPitchLock = 0;
1508
1509	/* Prefer the register value to the FIFO value.*/
1510	if (uRegPitchLock)
1511	pThis->svga.cbScanline = uRegPitchLock;
1512	else if (uFifoPitchLock)
1513	pThis->svga.cbScanline = uFifoPitchLock;
1514	else
1515	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1516
1517	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1518	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1519	}
1520
1521	#endif /* IN_RING0 \|\| IN_RING3 */
1522
1523
1524	/**
1525	* Write port register
1526	*
1527	* @returns Strict VBox status code.
1528	* @param pDevIns The device instance.
1529	* @param pThis The shared VGA/VMSVGA state.
1530	* @param pThisCC The VGA/VMSVGA state for the current context.
1531	* @param u32 Value to write
1532	*/
1533	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1534	{
1535	#ifdef IN_RING3
1536	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1537	#endif
1538	VBOXSTRICTRC rc = VINF_SUCCESS;
1539	RT_NOREF(pThisCC);
1540
1541	/* Rough index register validation. */
1542	uint32_t idxReg = pThis->svga.u32IndexReg;
1543	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1544	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1545	VINF_IOM_R3_IOPORT_WRITE);
1546	#else
1547	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1548	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1549	VINF_SUCCESS);
1550	#endif
1551	RT_UNTRUSTED_VALIDATED_FENCE();
1552
1553	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1554	if ( idxReg >= SVGA_REG_CAPABILITIES
1555	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1556	{
1557	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1558	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1559	}
1560	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1561	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1562	switch (idxReg)
1563	{
1564	case SVGA_REG_WIDTH:
1565	case SVGA_REG_HEIGHT:
1566	case SVGA_REG_PITCHLOCK:
1567	case SVGA_REG_BITS_PER_PIXEL:
1568	pThis->svga.fGFBRegisters = true;
1569	break;
1570	default:
1571	break;
1572	}
1573
1574	switch (idxReg)
1575	{
1576	case SVGA_REG_ID:
1577	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1578	if ( u32 == SVGA_ID_0
1579	\|\| u32 == SVGA_ID_1
1580	\|\| u32 == SVGA_ID_2)
1581	pThis->svga.u32SVGAId = u32;
1582	else
1583	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1584	break;
1585
1586	case SVGA_REG_ENABLE:
1587	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1588	#ifdef IN_RING3
1589	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1590	&& pThis->svga.fEnabled == false)
1591	{
1592	/* Make a backup copy of the first 512kb in order to save font data etc. */
1593	/** @todo should probably swap here, rather than copy + zero */
1594	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1595	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1596	}
1597
1598	pThis->svga.fEnabled = u32;
1599	if (pThis->svga.fEnabled)
1600	{
1601	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1602	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1603	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1604	{
1605	/* Keep the current mode. */
1606	pThis->svga.uWidth = pThisCC->pDrv->cx;
1607	pThis->svga.uHeight = pThisCC->pDrv->cy;
1608	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1609	}
1610
1611	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1612	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1613	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1614	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1615	# ifdef LOG_ENABLED
1616	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1617	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1618	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1619	# endif
1620
1621	/* Disable or enable dirty page tracking according to the current fTraces value. */
1622	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1623
1624	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1625	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1626	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1627	}
1628	else
1629	{
1630	/* Restore the text mode backup. */
1631	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1632
1633	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1634
1635	/* Enable dirty page tracking again when going into legacy mode. */
1636	vmsvgaR3SetTraces(pDevIns, pThis, true);
1637
1638	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1639	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1640	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1641
1642	/* Clear the pitch lock. */
1643	pThis->svga.u32PitchLock = 0;
1644	}
1645	#else /* !IN_RING3 */
1646	rc = VINF_IOM_R3_IOPORT_WRITE;
1647	#endif /* !IN_RING3 */
1648	break;
1649
1650	case SVGA_REG_WIDTH:
1651	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1652	if (pThis->svga.uWidth != u32)
1653	{
1654	#if defined(IN_RING3) \|\| defined(IN_RING0)
1655	pThis->svga.uWidth = u32;
1656	vmsvgaHCUpdatePitch(pThis, pThisCC);
1657	if (pThis->svga.fEnabled)
1658	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1659	#else
1660	rc = VINF_IOM_R3_IOPORT_WRITE;
1661	#endif
1662	}
1663	/* else: nop */
1664	break;
1665
1666	case SVGA_REG_HEIGHT:
1667	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1668	if (pThis->svga.uHeight != u32)
1669	{
1670	pThis->svga.uHeight = u32;
1671	if (pThis->svga.fEnabled)
1672	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1673	}
1674	/* else: nop */
1675	break;
1676
1677	case SVGA_REG_DEPTH:
1678	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1679	/** @todo read-only?? */
1680	break;
1681
1682	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1683	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1684	if (pThis->svga.uBpp != u32)
1685	{
1686	#if defined(IN_RING3) \|\| defined(IN_RING0)
1687	pThis->svga.uBpp = u32;
1688	vmsvgaHCUpdatePitch(pThis, pThisCC);
1689	if (pThis->svga.fEnabled)
1690	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1691	#else
1692	rc = VINF_IOM_R3_IOPORT_WRITE;
1693	#endif
1694	}
1695	/* else: nop */
1696	break;
1697
1698	case SVGA_REG_PSEUDOCOLOR:
1699	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1700	break;
1701
1702	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1703	#ifdef IN_RING3
1704	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1705	pThis->svga.fConfigured = u32;
1706	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1707	if (!pThis->svga.fConfigured)
1708	pThis->svga.fTraces = true;
1709	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1710	#else
1711	rc = VINF_IOM_R3_IOPORT_WRITE;
1712	#endif
1713	break;
1714
1715	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1716	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1717	if ( pThis->svga.fEnabled
1718	&& pThis->svga.fConfigured)
1719	{
1720	#if defined(IN_RING3) \|\| defined(IN_RING0)
1721	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1722	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1723	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1724	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1725
1726	/* Kick the FIFO thread to start processing commands again. */
1727	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1728	#else
1729	rc = VINF_IOM_R3_IOPORT_WRITE;
1730	#endif
1731	}
1732	/* else nothing to do. */
1733	else
1734	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1735
1736	break;
1737
1738	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1739	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1740	break;
1741
1742	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1743	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1744	pThis->svga.u32GuestId = u32;
1745	break;
1746
1747	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1748	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1749	pThis->svga.u32PitchLock = u32;
1750	/* Should this also update the FIFO pitch lock? Unclear. */
1751	break;
1752
1753	case SVGA_REG_IRQMASK: /* Interrupt mask */
1754	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1755	pThis->svga.u32IrqMask = u32;
1756
1757	/* Irq pending after the above change? */
1758	if (pThis->svga.u32IrqStatus & u32)
1759	{
1760	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1761	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1762	}
1763	else
1764	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1765	break;
1766
1767	/* Mouse cursor support */
1768	case SVGA_REG_CURSOR_ID:
1769	case SVGA_REG_CURSOR_X:
1770	case SVGA_REG_CURSOR_Y:
1771	case SVGA_REG_CURSOR_ON:
1772	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1773	break;
1774
1775	/* Legacy multi-monitor support */
1776	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1777	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1778	break;
1779	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1781	break;
1782	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1783	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1784	break;
1785	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1786	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1787	break;
1788	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1789	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1790	break;
1791	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1792	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1793	break;
1794	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1795	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1796	break;
1797	#ifdef VBOX_WITH_VMSVGA3D
1798	/* See "Guest memory regions" below. */
1799	case SVGA_REG_GMR_ID:
1800	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1801	pThis->svga.u32CurrentGMRId = u32;
1802	break;
1803
1804	case SVGA_REG_GMR_DESCRIPTOR:
1805	# ifndef IN_RING3
1806	rc = VINF_IOM_R3_IOPORT_WRITE;
1807	break;
1808	# else /* IN_RING3 */
1809	{
1810	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1811
1812	/* Validate current GMR id. */
1813	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1814	AssertBreak(idGMR < pThis->svga.cGMR);
1815	RT_UNTRUSTED_VALIDATED_FENCE();
1816
1817	/* Free the old GMR if present. */
1818	vmsvgaR3GmrFree(pThisCC, idGMR);
1819
1820	/* Just undefine the GMR? */
1821	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1822	if (GCPhys == 0)
1823	{
1824	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1825	break;
1826	}
1827
1828
1829	/* Never cross a page boundary automatically. */
1830	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1831	uint32_t cPagesTotal = 0;
1832	uint32_t iDesc = 0;
1833	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1834	uint32_t cLoops = 0;
1835	RTGCPHYS GCPhysBase = GCPhys;
1836	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1837	{
1838	/* Read descriptor. */
1839	SVGAGuestMemDescriptor desc;
1840	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1841	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1842
1843	if (desc.numPages != 0)
1844	{
1845	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1846	cPagesTotal += desc.numPages;
1847	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1848
1849	if ((iDesc & 15) == 0)
1850	{
1851	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1852	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1853	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1854	}
1855
1856	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1857	paDescs[iDesc++].numPages = desc.numPages;
1858
1859	/* Continue with the next descriptor. */
1860	GCPhys += sizeof(desc);
1861	}
1862	else if (desc.ppn == 0)
1863	break; /* terminator */
1864	else /* Pointer to the next physical page of descriptors. */
1865	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1866
1867	cLoops++;
1868	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1869	}
1870
1871	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1872	if (RT_SUCCESS(rc))
1873	{
1874	/* Commit the GMR. */
1875	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1876	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1877	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1878	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1879	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1880	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1881	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1882	}
1883	else
1884	{
1885	RTMemFree(paDescs);
1886	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1887	}
1888	break;
1889	}
1890	# endif /* IN_RING3 */
1891	#endif // VBOX_WITH_VMSVGA3D
1892
1893	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1895	if (pThis->svga.fTraces == u32)
1896	break; /* nothing to do */
1897
1898	#ifdef IN_RING3
1899	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1900	#else
1901	rc = VINF_IOM_R3_IOPORT_WRITE;
1902	#endif
1903	break;
1904
1905	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1907	break;
1908
1909	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1910	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1911	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1912	break;
1913
1914	case SVGA_REG_FB_START:
1915	case SVGA_REG_MEM_START:
1916	case SVGA_REG_HOST_BITS_PER_PIXEL:
1917	case SVGA_REG_MAX_WIDTH:
1918	case SVGA_REG_MAX_HEIGHT:
1919	case SVGA_REG_VRAM_SIZE:
1920	case SVGA_REG_FB_SIZE:
1921	case SVGA_REG_CAPABILITIES:
1922	case SVGA_REG_MEM_SIZE:
1923	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1924	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1925	case SVGA_REG_BYTES_PER_LINE:
1926	case SVGA_REG_FB_OFFSET:
1927	case SVGA_REG_RED_MASK:
1928	case SVGA_REG_GREEN_MASK:
1929	case SVGA_REG_BLUE_MASK:
1930	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1931	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1932	case SVGA_REG_GMR_MAX_IDS:
1933	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1934	/* Read only - ignore. */
1935	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1936	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1937	break;
1938
1939	default:
1940	{
1941	uint32_t offReg;
1942	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1943	{
1944	RT_UNTRUSTED_VALIDATED_FENCE();
1945	pThis->svga.au32ScratchRegion[offReg] = u32;
1946	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1947	}
1948	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1949	{
1950	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1951	Btw, see rgb_to_pixel32. */
1952	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1953	u32 &= 0xff;
1954	RT_UNTRUSTED_VALIDATED_FENCE();
1955	uint32_t uRgb = pThis->last_palette[offReg / 3];
1956	switch (offReg % 3)
1957	{
1958	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1959	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1960	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1961	}
1962	pThis->last_palette[offReg / 3] = uRgb;
1963	}
1964	else
1965	{
1966	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1967	rc = VINF_IOM_R3_IOPORT_WRITE;
1968	#else
1969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1970	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1971	#endif
1972	}
1973	break;
1974	}
1975	}
1976	return rc;
1977	}
1978
1979	/**
1980	* @callback_method_impl{FNIOMIOPORTNEWIN}
1981	*/
1982	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1983	{
1984	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
1985	RT_NOREF_PV(pvUser);
1986
1987	/* Only dword accesses. */
1988	if (cb == 4)
1989	{
1990	switch (offPort)
1991	{
1992	case SVGA_INDEX_PORT:
1993	*pu32 = pThis->svga.u32IndexReg;
1994	break;
1995
1996	case SVGA_VALUE_PORT:
1997	return vmsvgaReadPort(pDevIns, pThis, pu32);
1998
1999	case SVGA_BIOS_PORT:
2000	Log(("Ignoring BIOS port read\n"));
2001	*pu32 = 0;
2002	break;
2003
2004	case SVGA_IRQSTATUS_PORT:
2005	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2006	*pu32 = pThis->svga.u32IrqStatus;
2007	break;
2008
2009	default:
2010	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2011	*pu32 = UINT32_MAX;
2012	break;
2013	}
2014	}
2015	else
2016	{
2017	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2018	*pu32 = UINT32_MAX;
2019	}
2020	return VINF_SUCCESS;
2021	}
2022
2023	/**
2024	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2025	*/
2026	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2027	{
2028	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2029	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2030	RT_NOREF_PV(pvUser);
2031
2032	/* Only dword accesses. */
2033	if (cb == 4)
2034	switch (offPort)
2035	{
2036	case SVGA_INDEX_PORT:
2037	pThis->svga.u32IndexReg = u32;
2038	break;
2039
2040	case SVGA_VALUE_PORT:
2041	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2042
2043	case SVGA_BIOS_PORT:
2044	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2045	break;
2046
2047	case SVGA_IRQSTATUS_PORT:
2048	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2049	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2050	/* Clear the irq in case all events have been cleared. */
2051	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2052	{
2053	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2054	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2055	}
2056	break;
2057
2058	default:
2059	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2060	break;
2061	}
2062	else
2063	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2064
2065	return VINF_SUCCESS;
2066	}
2067
2068	#ifdef IN_RING3
2069
2070	# ifdef DEBUG_FIFO_ACCESS
2071	/**
2072	* Handle FIFO memory access.
2073	* @returns VBox status code.
2074	* @param pVM VM handle.
2075	* @param pThis The shared VGA/VMSVGA instance data.
2076	* @param GCPhys The access physical address.
2077	* @param fWriteAccess Read or write access
2078	*/
2079	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2080	{
2081	RT_NOREF(pVM);
2082	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2083	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2084
2085	switch (GCPhysOffset >> 2)
2086	{
2087	case SVGA_FIFO_MIN:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_MAX:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_NEXT_CMD:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_STOP:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_CAPABILITIES:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_FLAGS:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_FENCE:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_3D_HWVERSION:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_PITCHLOCK:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_CURSOR_ON:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_CURSOR_X:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_CURSOR_Y:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_CURSOR_COUNT:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_RESERVED:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_CURSOR_SCREEN_ID:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_DEAD:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_HWVERSION_REVISED:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS_LAST:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_GUEST_3D_HWVERSION:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_FENCE_GOAL:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_BUSY:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	default:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	}
2406
2407	return VINF_EM_RAW_EMULATE_INSTR;
2408	}
2409	# endif /* DEBUG_FIFO_ACCESS */
2410
2411	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2412	/**
2413	* HC access handler for the FIFO.
2414	*
2415	* @returns VINF_SUCCESS if the handler have carried out the operation.
2416	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2417	* @param pVM VM Handle.
2418	* @param pVCpu The cross context CPU structure for the calling EMT.
2419	* @param GCPhys The physical address the guest is writing to.
2420	* @param pvPhys The HC mapping of that address.
2421	* @param pvBuf What the guest is reading/writing.
2422	* @param cbBuf How much it's reading/writing.
2423	* @param enmAccessType The access type.
2424	* @param enmOrigin Who is making the access.
2425	* @param pvUser User argument.
2426	*/
2427	static DECLCALLBACK(VBOXSTRICTRC)
2428	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2429	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2430	{
2431	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2432	PVGASTATE pThis = (PVGASTATE)pvUser;
2433	AssertPtr(pThis);
2434
2435	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2436	/*
2437	* Wake up the FIFO thread as it might have work to do now.
2438	*/
2439	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2440	AssertLogRelRC(rc);
2441	# endif
2442
2443	# ifdef DEBUG_FIFO_ACCESS
2444	/*
2445	* When in debug-fifo-access mode, we do not disable the access handler,
2446	* but leave it on as we wish to catch all access.
2447	*/
2448	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2449	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2450	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2451	/*
2452	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2453	*/
2454	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2455	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2456	# endif
2457	if (RT_SUCCESS(rc))
2458	return VINF_PGM_HANDLER_DO_DEFAULT;
2459	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2460	return rc;
2461	}
2462	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2463
2464	#endif /* IN_RING3 */
2465
2466	#ifdef DEBUG_GMR_ACCESS
2467	# ifdef IN_RING3
2468
2469	/**
2470	* HC access handler for the FIFO.
2471	*
2472	* @returns VINF_SUCCESS if the handler have carried out the operation.
2473	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2474	* @param pVM VM Handle.
2475	* @param pVCpu The cross context CPU structure for the calling EMT.
2476	* @param GCPhys The physical address the guest is writing to.
2477	* @param pvPhys The HC mapping of that address.
2478	* @param pvBuf What the guest is reading/writing.
2479	* @param cbBuf How much it's reading/writing.
2480	* @param enmAccessType The access type.
2481	* @param enmOrigin Who is making the access.
2482	* @param pvUser User argument.
2483	*/
2484	static DECLCALLBACK(VBOXSTRICTRC)
2485	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2486	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2487	{
2488	PVGASTATE pThis = (PVGASTATE)pvUser;
2489	Assert(pThis);
2490	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2491	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2492
2493	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2494
2495	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2496	{
2497	PGMR pGMR = &pSVGAState->paGMR[i];
2498
2499	if (pGMR->numDescriptors)
2500	{
2501	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2502	{
2503	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2504	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2505	{
2506	/*
2507	* Turn off the write handler for this particular page and make it R/W.
2508	* Then return telling the caller to restart the guest instruction.
2509	*/
2510	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2511	AssertRC(rc);
2512	return VINF_PGM_HANDLER_DO_DEFAULT;
2513	}
2514	}
2515	}
2516	}
2517
2518	return VINF_PGM_HANDLER_DO_DEFAULT;
2519	}
2520
2521	/** Callback handler for VMR3ReqCallWaitU */
2522	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2523	{
2524	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2525	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2526	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2527	int rc;
2528
2529	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2530	{
2531	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2532	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2533	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2534	AssertRC(rc);
2535	}
2536	return VINF_SUCCESS;
2537	}
2538
2539	/** Callback handler for VMR3ReqCallWaitU */
2540	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2541	{
2542	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2543	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2544	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2545
2546	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2547	{
2548	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2549	AssertRC(rc);
2550	}
2551	return VINF_SUCCESS;
2552	}
2553
2554	/** Callback handler for VMR3ReqCallWaitU */
2555	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2556	{
2557	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2558
2559	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2560	{
2561	PGMR pGMR = &pSVGAState->paGMR[i];
2562
2563	if (pGMR->numDescriptors)
2564	{
2565	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2566	{
2567	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2568	AssertRC(rc);
2569	}
2570	}
2571	}
2572	return VINF_SUCCESS;
2573	}
2574
2575	# endif /* IN_RING3 */
2576	#endif /* DEBUG_GMR_ACCESS */
2577
2578	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2579
2580	#ifdef IN_RING3
2581
2582
2583	/**
2584	* Common worker for changing the pointer shape.
2585	*
2586	* @param pThisCC The VGA/VMSVGA state for ring-3.
2587	* @param pSVGAState The VMSVGA ring-3 instance data.
2588	* @param fAlpha Whether there is alpha or not.
2589	* @param xHot Hotspot x coordinate.
2590	* @param yHot Hotspot y coordinate.
2591	* @param cx Width.
2592	* @param cy Height.
2593	* @param pbData Heap copy of the cursor data. Consumed.
2594	* @param cbData The size of the data.
2595	*/
2596	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2597	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2598	{
2599	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2600	# ifdef LOG_ENABLED
2601	if (LogIs2Enabled())
2602	{
2603	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2604	if (!fAlpha)
2605	{
2606	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2607	for (uint32_t y = 0; y < cy; y++)
2608	{
2609	Log2(("%3u:", y));
2610	uint8_t const pbLine = &pbData[y cbAndLine];
2611	for (uint32_t x = 0; x < cx; x += 8)
2612	{
2613	uint8_t b = pbLine[x / 8];
2614	char szByte[12];
2615	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2616	szByte[1] = b & 0x40 ? '*' : ' ';
2617	szByte[2] = b & 0x20 ? '*' : ' ';
2618	szByte[3] = b & 0x10 ? '*' : ' ';
2619	szByte[4] = b & 0x08 ? '*' : ' ';
2620	szByte[5] = b & 0x04 ? '*' : ' ';
2621	szByte[6] = b & 0x02 ? '*' : ' ';
2622	szByte[7] = b & 0x01 ? '*' : ' ';
2623	szByte[8] = '\0';
2624	Log2(("%s", szByte));
2625	}
2626	Log2(("\n"));
2627	}
2628	}
2629
2630	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2631	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2632	for (uint32_t y = 0; y < cy; y++)
2633	{
2634	Log2(("%3u:", y));
2635	uint32_t const pu32Line = &pu32Xor[y cx];
2636	for (uint32_t x = 0; x < cx; x++)
2637	Log2((" %08x", pu32Line[x]));
2638	Log2(("\n"));
2639	}
2640	}
2641	# endif
2642
2643	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2644	AssertRC(rc);
2645
2646	if (pSVGAState->Cursor.fActive)
2647	RTMemFree(pSVGAState->Cursor.pData);
2648
2649	pSVGAState->Cursor.fActive = true;
2650	pSVGAState->Cursor.xHotspot = xHot;
2651	pSVGAState->Cursor.yHotspot = yHot;
2652	pSVGAState->Cursor.width = cx;
2653	pSVGAState->Cursor.height = cy;
2654	pSVGAState->Cursor.cbData = cbData;
2655	pSVGAState->Cursor.pData = pbData;
2656	}
2657
2658
2659	/**
2660	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2661	*
2662	* @param pThis The shared VGA/VMSVGA state.
2663	* @param pThisCC The VGA/VMSVGA state for ring-3.
2664	* @param pSVGAState The VMSVGA ring-3 instance data.
2665	* @param pCursor The cursor.
2666	* @param pbSrcAndMask The AND mask.
2667	* @param cbSrcAndLine The scanline length of the AND mask.
2668	* @param pbSrcXorMask The XOR mask.
2669	* @param cbSrcXorLine The scanline length of the XOR mask.
2670	*/
2671	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2672	SVGAFifoCmdDefineCursor const *pCursor,
2673	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2674	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2675	{
2676	uint32_t const cx = pCursor->width;
2677	uint32_t const cy = pCursor->height;
2678
2679	/*
2680	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2681	* The AND data uses 8-bit aligned scanlines.
2682	* The XOR data must be starting on a 32-bit boundrary.
2683	*/
2684	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2685	uint32_t cbDstAndMask = cbDstAndLine * cy;
2686	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2687	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2688
2689	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2690	AssertReturnVoid(pbCopy);
2691
2692	/* Convert the AND mask. */
2693	uint8_t *pbDst = pbCopy;
2694	uint8_t const *pbSrc = pbSrcAndMask;
2695	switch (pCursor->andMaskDepth)
2696	{
2697	case 1:
2698	if (cbSrcAndLine == cbDstAndLine)
2699	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2700	else
2701	{
2702	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2703	for (uint32_t y = 0; y < cy; y++)
2704	{
2705	memcpy(pbDst, pbSrc, cbDstAndLine);
2706	pbDst += cbDstAndLine;
2707	pbSrc += cbSrcAndLine;
2708	}
2709	}
2710	break;
2711	/* Should take the XOR mask into account for the multi-bit AND mask. */
2712	case 8:
2713	for (uint32_t y = 0; y < cy; y++)
2714	{
2715	for (uint32_t x = 0; x < cx; )
2716	{
2717	uint8_t bDst = 0;
2718	uint8_t fBit = 1;
2719	do
2720	{
2721	uintptr_t const idxPal = pbSrc[x] * 3;
2722	if ((( pThis->last_palette[idxPal]
2723	\| (pThis->last_palette[idxPal] >> 8)
2724	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2725	bDst \|= fBit;
2726	fBit <<= 1;
2727	x++;
2728	} while (x < cx && (x & 7));
2729	pbDst[(x - 1) / 8] = bDst;
2730	}
2731	pbDst += cbDstAndLine;
2732	pbSrc += cbSrcAndLine;
2733	}
2734	break;
2735	case 15:
2736	for (uint32_t y = 0; y < cy; y++)
2737	{
2738	for (uint32_t x = 0; x < cx; )
2739	{
2740	uint8_t bDst = 0;
2741	uint8_t fBit = 1;
2742	do
2743	{
2744	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2745	bDst \|= fBit;
2746	fBit <<= 1;
2747	x++;
2748	} while (x < cx && (x & 7));
2749	pbDst[(x - 1) / 8] = bDst;
2750	}
2751	pbDst += cbDstAndLine;
2752	pbSrc += cbSrcAndLine;
2753	}
2754	break;
2755	case 16:
2756	for (uint32_t y = 0; y < cy; y++)
2757	{
2758	for (uint32_t x = 0; x < cx; )
2759	{
2760	uint8_t bDst = 0;
2761	uint8_t fBit = 1;
2762	do
2763	{
2764	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2765	bDst \|= fBit;
2766	fBit <<= 1;
2767	x++;
2768	} while (x < cx && (x & 7));
2769	pbDst[(x - 1) / 8] = bDst;
2770	}
2771	pbDst += cbDstAndLine;
2772	pbSrc += cbSrcAndLine;
2773	}
2774	break;
2775	case 24:
2776	for (uint32_t y = 0; y < cy; y++)
2777	{
2778	for (uint32_t x = 0; x < cx; )
2779	{
2780	uint8_t bDst = 0;
2781	uint8_t fBit = 1;
2782	do
2783	{
2784	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2785	bDst \|= fBit;
2786	fBit <<= 1;
2787	x++;
2788	} while (x < cx && (x & 7));
2789	pbDst[(x - 1) / 8] = bDst;
2790	}
2791	pbDst += cbDstAndLine;
2792	pbSrc += cbSrcAndLine;
2793	}
2794	break;
2795	case 32:
2796	for (uint32_t y = 0; y < cy; y++)
2797	{
2798	for (uint32_t x = 0; x < cx; )
2799	{
2800	uint8_t bDst = 0;
2801	uint8_t fBit = 1;
2802	do
2803	{
2804	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2805	bDst \|= fBit;
2806	fBit <<= 1;
2807	x++;
2808	} while (x < cx && (x & 7));
2809	pbDst[(x - 1) / 8] = bDst;
2810	}
2811	pbDst += cbDstAndLine;
2812	pbSrc += cbSrcAndLine;
2813	}
2814	break;
2815	default:
2816	RTMemFree(pbCopy);
2817	AssertFailedReturnVoid();
2818	}
2819
2820	/* Convert the XOR mask. */
2821	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2822	pbSrc = pbSrcXorMask;
2823	switch (pCursor->xorMaskDepth)
2824	{
2825	case 1:
2826	for (uint32_t y = 0; y < cy; y++)
2827	{
2828	for (uint32_t x = 0; x < cx; )
2829	{
2830	/* most significant bit is the left most one. */
2831	uint8_t bSrc = pbSrc[x / 8];
2832	do
2833	{
2834	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2835	bSrc <<= 1;
2836	x++;
2837	} while ((x & 7) && x < cx);
2838	}
2839	pbSrc += cbSrcXorLine;
2840	}
2841	break;
2842	case 8:
2843	for (uint32_t y = 0; y < cy; y++)
2844	{
2845	for (uint32_t x = 0; x < cx; x++)
2846	{
2847	uint32_t u = pThis->last_palette[pbSrc[x]];
2848	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2849	}
2850	pbSrc += cbSrcXorLine;
2851	}
2852	break;
2853	case 15: /* Src: RGB-5-5-5 */
2854	for (uint32_t y = 0; y < cy; y++)
2855	{
2856	for (uint32_t x = 0; x < cx; x++)
2857	{
2858	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2859	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2860	((uValue >> 5) & 0x1f) << 3,
2861	((uValue >> 10) & 0x1f) << 3, 0);
2862	}
2863	pbSrc += cbSrcXorLine;
2864	}
2865	break;
2866	case 16: /* Src: RGB-5-6-5 */
2867	for (uint32_t y = 0; y < cy; y++)
2868	{
2869	for (uint32_t x = 0; x < cx; x++)
2870	{
2871	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2872	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2873	((uValue >> 5) & 0x3f) << 2,
2874	((uValue >> 11) & 0x1f) << 3, 0);
2875	}
2876	pbSrc += cbSrcXorLine;
2877	}
2878	break;
2879	case 24:
2880	for (uint32_t y = 0; y < cy; y++)
2881	{
2882	for (uint32_t x = 0; x < cx; x++)
2883	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2884	pbSrc += cbSrcXorLine;
2885	}
2886	break;
2887	case 32:
2888	for (uint32_t y = 0; y < cy; y++)
2889	{
2890	for (uint32_t x = 0; x < cx; x++)
2891	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2892	pbSrc += cbSrcXorLine;
2893	}
2894	break;
2895	default:
2896	RTMemFree(pbCopy);
2897	AssertFailedReturnVoid();
2898	}
2899
2900	/*
2901	* Pass it to the frontend/whatever.
2902	*/
2903	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2904	}
2905
2906
2907	/**
2908	* Worker for vmsvgaR3FifoThread that handles an external command.
2909	*
2910	* @param pDevIns The device instance.
2911	* @param pThis The shared VGA/VMSVGA instance data.
2912	* @param pThisCC The VGA/VMSVGA state for ring-3.
2913	*/
2914	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2915	{
2916	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2917	switch (pThis->svga.u8FIFOExtCommand)
2918	{
2919	case VMSVGA_FIFO_EXTCMD_RESET:
2920	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2921	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2922	# ifdef VBOX_WITH_VMSVGA3D
2923	if (pThis->svga.f3DEnabled)
2924	{
2925	/* The 3d subsystem must be reset from the fifo thread. */
2926	vmsvga3dReset(pThisCC);
2927	}
2928	# endif
2929	break;
2930
2931	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2932	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2933	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2934	# ifdef VBOX_WITH_VMSVGA3D
2935	if (pThis->svga.f3DEnabled)
2936	{
2937	/* The 3d subsystem must be shut down from the fifo thread. */
2938	vmsvga3dTerminate(pThisCC);
2939	}
2940	# endif
2941	break;
2942
2943	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2944	{
2945	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2946	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
2947	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2948	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
2949	# ifdef VBOX_WITH_VMSVGA3D
2950	if (pThis->svga.f3DEnabled)
2951	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
2952	# endif
2953	break;
2954	}
2955
2956	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2957	{
2958	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2959	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
2960	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2961	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2962	# ifdef VBOX_WITH_VMSVGA3D
2963	if (pThis->svga.f3DEnabled)
2964	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2965	# endif
2966	break;
2967	}
2968
2969	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2970	{
2971	# ifdef VBOX_WITH_VMSVGA3D
2972	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
2973	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2974	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
2975	# endif
2976	break;
2977	}
2978
2979
2980	default:
2981	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
2982	break;
2983	}
2984
2985	/*
2986	* Signal the end of the external command.
2987	*/
2988	pThisCC->svga.pvFIFOExtCmdParam = NULL;
2989	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2990	ASMMemoryFence(); /* paranoia^2 */
2991	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
2992	AssertLogRelRC(rc);
2993	}
2994
2995	/**
2996	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2997	* doing a job on the FIFO thread (even when it's officially suspended).
2998	*
2999	* @returns VBox status code (fully asserted).
3000	* @param pDevIns The device instance.
3001	* @param pThis The shared VGA/VMSVGA instance data.
3002	* @param pThisCC The VGA/VMSVGA state for ring-3.
3003	* @param uExtCmd The command to execute on the FIFO thread.
3004	* @param pvParam Pointer to command parameters.
3005	* @param cMsWait The time to wait for the command, given in
3006	* milliseconds.
3007	*/
3008	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3009	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3010	{
3011	Assert(cMsWait >= RT_MS_1SEC * 5);
3012	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3013	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3014
3015	int rc;
3016	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3017	PDMTHREADSTATE enmState = pThread->enmState;
3018	if (enmState == PDMTHREADSTATE_SUSPENDED)
3019	{
3020	/*
3021	* The thread is suspended, we have to temporarily wake it up so it can
3022	* perform the task.
3023	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3024	*/
3025	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3026	/* Post the request. */
3027	pThis->svga.fFifoExtCommandWakeup = true;
3028	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3029	pThis->svga.u8FIFOExtCommand = uExtCmd;
3030	ASMMemoryFence(); /* paranoia^3 */
3031
3032	/* Resume the thread. */
3033	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3034	AssertLogRelRC(rc);
3035	if (RT_SUCCESS(rc))
3036	{
3037	/* Wait. Take care in case the semaphore was already posted (same as below). */
3038	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3039	if ( rc == VINF_SUCCESS
3040	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3041	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3042	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3043	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3044
3045	/* suspend the thread */
3046	pThis->svga.fFifoExtCommandWakeup = false;
3047	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3048	AssertLogRelRC(rc2);
3049	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3050	rc = rc2;
3051	}
3052	pThis->svga.fFifoExtCommandWakeup = false;
3053	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3054	}
3055	else if (enmState == PDMTHREADSTATE_RUNNING)
3056	{
3057	/*
3058	* The thread is running, should only happen during reset and vmsvga3dsfc.
3059	* We ASSUME not racing code here, both wrt thread state and ext commands.
3060	*/
3061	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3062	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3063
3064	/* Post the request. */
3065	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3066	pThis->svga.u8FIFOExtCommand = uExtCmd;
3067	ASMMemoryFence(); /* paranoia^2 */
3068	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3069	AssertLogRelRC(rc);
3070
3071	/* Wait. Take care in case the semaphore was already posted (same as above). */
3072	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3073	if ( rc == VINF_SUCCESS
3074	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3075	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3076	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3077	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3078
3079	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3080	}
3081	else
3082	{
3083	/*
3084	* Something is wrong with the thread!
3085	*/
3086	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3087	rc = VERR_INVALID_STATE;
3088	}
3089	return rc;
3090	}
3091
3092
3093	/**
3094	* Marks the FIFO non-busy, notifying any waiting EMTs.
3095	*
3096	* @param pDevIns The device instance.
3097	* @param pThis The shared VGA/VMSVGA instance data.
3098	* @param pThisCC The VGA/VMSVGA state for ring-3.
3099	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3100	* @param offFifoMin The start byte offset of the command FIFO.
3101	*/
3102	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3103	{
3104	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3105	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3106	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3107
3108	/* Wake up any waiting EMTs. */
3109	if (pSVGAState->cBusyDelayedEmts > 0)
3110	{
3111	# ifdef VMSVGA_USE_EMT_HALT_CODE
3112	PVM pVM = PDMDevHlpGetVM(pDevIns);
3113	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3114	if (idCpu != NIL_VMCPUID)
3115	{
3116	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3117	while (idCpu-- > 0)
3118	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3119	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3120	}
3121	# else
3122	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3123	AssertRC(rc2);
3124	# endif
3125	}
3126	}
3127
3128	/**
3129	* Reads (more) payload into the command buffer.
3130	*
3131	* @returns pbBounceBuf on success
3132	* @retval (void *)1 if the thread was requested to stop.
3133	* @retval NULL on FIFO error.
3134	*
3135	* @param cbPayloadReq The number of bytes of payload requested.
3136	* @param pFIFO The FIFO.
3137	* @param offCurrentCmd The FIFO byte offset of the current command.
3138	* @param offFifoMin The start byte offset of the command FIFO.
3139	* @param offFifoMax The end byte offset of the command FIFO.
3140	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3141	* always sufficient size.
3142	* @param pcbAlreadyRead How much payload we've already read into the bounce
3143	* buffer. (We will NEVER re-read anything.)
3144	* @param pThread The calling PDM thread handle.
3145	* @param pThis The shared VGA/VMSVGA instance data.
3146	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3147	* statistics collection.
3148	* @param pDevIns The device instance.
3149	*/
3150	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3151	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3152	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3153	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3154	{
3155	Assert(pbBounceBuf);
3156	Assert(pcbAlreadyRead);
3157	Assert(offFifoMin < offFifoMax);
3158	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3159	Assert(offFifoMax <= pThis->svga.cbFIFO);
3160
3161	/*
3162	* Check if the requested payload size has already been satisfied .
3163	* .
3164	* When called to read more, the caller is responsible for making sure the .
3165	* new command size (cbRequsted) never is smaller than what has already .
3166	* been read.
3167	*/
3168	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3169	if (cbPayloadReq <= cbAlreadyRead)
3170	{
3171	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3172	return pbBounceBuf;
3173	}
3174
3175	/*
3176	* Commands bigger than the fifo buffer are invalid.
3177	*/
3178	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3179	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3180	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3181	NULL);
3182
3183	/*
3184	* Move offCurrentCmd past the command dword.
3185	*/
3186	offCurrentCmd += sizeof(uint32_t);
3187	if (offCurrentCmd >= offFifoMax)
3188	offCurrentCmd = offFifoMin;
3189
3190	/*
3191	* Do we have sufficient payload data available already?
3192	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3193	*/
3194	uint32_t cbAfter, cbBefore;
3195	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3196	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3197	if (offNextCmd >= offCurrentCmd)
3198	{
3199	if (RT_LIKELY(offNextCmd < offFifoMax))
3200	cbAfter = offNextCmd - offCurrentCmd;
3201	else
3202	{
3203	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3204	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3205	offNextCmd, offFifoMin, offFifoMax));
3206	cbAfter = offFifoMax - offCurrentCmd;
3207	}
3208	cbBefore = 0;
3209	}
3210	else
3211	{
3212	cbAfter = offFifoMax - offCurrentCmd;
3213	if (offNextCmd >= offFifoMin)
3214	cbBefore = offNextCmd - offFifoMin;
3215	else
3216	{
3217	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3218	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3219	offNextCmd, offFifoMin, offFifoMax));
3220	cbBefore = 0;
3221	}
3222	}
3223	if (cbAfter + cbBefore < cbPayloadReq)
3224	{
3225	/*
3226	* Insufficient, must wait for it to arrive.
3227	*/
3228	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3229	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3230	for (uint32_t i = 0;; i++)
3231	{
3232	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3233	{
3234	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3235	return (void *)(uintptr_t)1;
3236	}
3237	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3238	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3239
3240	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3241
3242	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3243	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3244	if (offNextCmd >= offCurrentCmd)
3245	{
3246	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3247	cbBefore = 0;
3248	}
3249	else
3250	{
3251	cbAfter = offFifoMax - offCurrentCmd;
3252	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3253	}
3254
3255	if (cbAfter + cbBefore >= cbPayloadReq)
3256	break;
3257	}
3258	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3259	}
3260
3261	/*
3262	* Copy out the memory and update what pcbAlreadyRead points to.
3263	*/
3264	if (cbAfter >= cbPayloadReq)
3265	memcpy(pbBounceBuf + cbAlreadyRead,
3266	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3267	cbPayloadReq - cbAlreadyRead);
3268	else
3269	{
3270	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3271	if (cbAlreadyRead < cbAfter)
3272	{
3273	memcpy(pbBounceBuf + cbAlreadyRead,
3274	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3275	cbAfter - cbAlreadyRead);
3276	cbAlreadyRead = cbAfter;
3277	}
3278	memcpy(pbBounceBuf + cbAlreadyRead,
3279	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3280	cbPayloadReq - cbAlreadyRead);
3281	}
3282	*pcbAlreadyRead = cbPayloadReq;
3283	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3284	return pbBounceBuf;
3285	}
3286
3287
3288	/**
3289	* Sends cursor position and visibility information from the FIFO to the front-end.
3290	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3291	*/
3292	static uint32_t
3293	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3294	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3295	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3296	{
3297	/*
3298	* Check if the cursor update counter has changed and try get a stable
3299	* set of values if it has. This is race-prone, especially consindering
3300	* the screen ID, but little we can do about that.
3301	*/
3302	uint32_t x, y, fVisible, idScreen;
3303	for (uint32_t i = 0; ; i++)
3304	{
3305	x = pFIFO[SVGA_FIFO_CURSOR_X];
3306	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3307	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3308	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3309	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3310	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3311	\|\| i > 3)
3312	break;
3313	if (i == 0)
3314	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3315	ASMNopPause();
3316	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3317	}
3318
3319	/*
3320	* Check if anything has changed, as calling into pDrv is not light-weight.
3321	*/
3322	if ( *pxLast == x
3323	&& *pyLast == y
3324	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3325	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3326	else
3327	{
3328	/*
3329	* Detected changes.
3330	*
3331	* We handle global, not per-screen visibility information by sending
3332	* pfnVBVAMousePointerShape without shape data.
3333	*/
3334	*pxLast = x;
3335	*pyLast = y;
3336	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3337	if (idScreen != SVGA_ID_INVALID)
3338	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3339	else if (*pfLastVisible != fVisible)
3340	{
3341	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3342	*pfLastVisible = fVisible;
3343	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3344	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3345	}
3346	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3347	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3348	}
3349
3350	/*
3351	* Update done. Signal this to the guest.
3352	*/
3353	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3354
3355	return uCursorUpdateCount;
3356	}
3357
3358
3359	/**
3360	* Checks if there is work to be done, either cursor updating or FIFO commands.
3361	*
3362	* @returns true if pending work, false if not.
3363	* @param pFIFO The FIFO to examine.
3364	* @param uLastCursorCount The last cursor update counter value.
3365	*/
3366	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3367	{
3368	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3369	return true;
3370
3371	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3372	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3373	return true;
3374
3375	return false;
3376	}
3377
3378
3379	/**
3380	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3381	*
3382	* @param pDevIns The device instance.
3383	* @param pThis The shared VGA/VMSVGA instance data.
3384	* @param pThisCC The VGA/VMSVGA state for ring-3.
3385	*/
3386	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3387	{
3388	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3389	to recheck it before doing the signalling. */
3390	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3391	AssertReturnVoid(pFIFO);
3392	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3393	&& pThis->svga.fFIFOThreadSleeping)
3394	{
3395	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3396	AssertRC(rc);
3397	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3398	}
3399	}
3400
3401
3402	/*
3403	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3404	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3405	*/
3406	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3407	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3408	*
3409	* Will break out of the switch on failure.
3410	* Will restart and quit the loop if the thread was requested to stop.
3411	*
3412	* @param a_PtrVar Request variable pointer.
3413	* @param a_Type Request typedef (not pointer) for casting.
3414	* @param a_cbPayloadReq How much payload to fetch.
3415	* @remarks Accesses a bunch of variables in the current scope!
3416	*/
3417	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3418	if (1) { \
3419	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3420	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3421	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3422	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3423	} else do {} while (0)
3424	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3425	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3426	* buffer after figuring out the actual command size.
3427	*
3428	* Will break out of the switch on failure.
3429	*
3430	* @param a_PtrVar Request variable pointer.
3431	* @param a_Type Request typedef (not pointer) for casting.
3432	* @param a_cbPayloadReq How much payload to fetch.
3433	* @remarks Accesses a bunch of variables in the current scope!
3434	*/
3435	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3436	if (1) { \
3437	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3438	} else do {} while (0)
3439
3440	/**
3441	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3442	*/
3443	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3444	{
3445	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3446	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3447	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3448	int rc;
3449
3450	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3451	return VINF_SUCCESS;
3452
3453	/*
3454	* Special mode where we only execute an external command and the go back
3455	* to being suspended. Currently, all ext cmds ends up here, with the reset
3456	* one also being eligble for runtime execution further down as well.
3457	*/
3458	if (pThis->svga.fFifoExtCommandWakeup)
3459	{
3460	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3461	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3462	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3463	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3464	else
3465	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3466	return VINF_SUCCESS;
3467	}
3468
3469
3470	/*
3471	* Signal the semaphore to make sure we don't wait for 250ms after a
3472	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3473	*/
3474	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3475
3476	/*
3477	* Allocate a bounce buffer for command we get from the FIFO.
3478	* (All code must return via the end of the function to free this buffer.)
3479	*/
3480	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3481	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3482
3483	/*
3484	* Polling/sleep interval config.
3485	*
3486	* We wait for an a short interval if the guest has recently given us work
3487	* to do, but the interval increases the longer we're kept idle. Once we've
3488	* reached the refresh timer interval, we'll switch to extended waits,
3489	* depending on it or the guest to kick us into action when needed.
3490	*
3491	* Should the refresh time go fishing, we'll just continue increasing the
3492	* sleep length till we reaches the 250 ms max after about 16 seconds.
3493	*/
3494	RTMSINTERVAL const cMsMinSleep = 16;
3495	RTMSINTERVAL const cMsIncSleep = 2;
3496	RTMSINTERVAL const cMsMaxSleep = 250;
3497	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3498	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3499
3500	/*
3501	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3502	*
3503	* Initialize with values that will detect an update from the guest.
3504	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3505	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3506	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3507	*/
3508	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3509	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3510	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3511	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3512	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3513
3514	/*
3515	* The FIFO loop.
3516	*/
3517	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3518	bool fBadOrDisabledFifo = false;
3519	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3520	{
3521	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3522	/*
3523	* Should service the run loop every so often.
3524	*/
3525	if (pThis->svga.f3DEnabled)
3526	vmsvga3dCocoaServiceRunLoop();
3527	# endif
3528
3529	/*
3530	* Unless there's already work pending, go to sleep for a short while.
3531	* (See polling/sleep interval config above.)
3532	*/
3533	if ( fBadOrDisabledFifo
3534	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3535	{
3536	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3537	Assert(pThis->cMilliesRefreshInterval > 0);
3538	if (cMsSleep < pThis->cMilliesRefreshInterval)
3539	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3540	else
3541	{
3542	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3543	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3544	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3545	# endif
3546	if ( !fBadOrDisabledFifo
3547	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3548	rc = VINF_SUCCESS;
3549	else
3550	{
3551	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3552	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3553	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3554	}
3555	}
3556	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3557	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3558	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3559	{
3560	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3561	break;
3562	}
3563	}
3564	else
3565	rc = VINF_SUCCESS;
3566	fBadOrDisabledFifo = false;
3567	if (rc == VERR_TIMEOUT)
3568	{
3569	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3570	{
3571	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3572	continue;
3573	}
3574	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3575
3576	Log(("vmsvgaR3FifoLoop: timeout\n"));
3577	}
3578	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3579	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3580	cMsSleep = cMsMinSleep;
3581
3582	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3583	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3584	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3585
3586	/*
3587	* Handle external commands (currently only reset).
3588	*/
3589	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3590	{
3591	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3592	continue;
3593	}
3594
3595	/*
3596	* The device must be enabled and configured.
3597	*/
3598	if ( !pThis->svga.fEnabled
3599	\|\| !pThis->svga.fConfigured)
3600	{
3601	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3602	fBadOrDisabledFifo = true;
3603	cMsSleep = cMsMaxSleep; /* cheat */
3604	continue;
3605	}
3606
3607	/*
3608	* Get and check the min/max values. We ASSUME that they will remain
3609	* unchanged while we process requests. A further ASSUMPTION is that
3610	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3611	* we don't read it back while in the loop.
3612	*/
3613	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3614	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3615	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3616	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3617	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3618	\|\| offFifoMax <= offFifoMin
3619	\|\| offFifoMax > pThis->svga.cbFIFO
3620	\|\| (offFifoMax & 3) != 0
3621	\|\| (offFifoMin & 3) != 0
3622	\|\| offCurrentCmd < offFifoMin
3623	\|\| offCurrentCmd > offFifoMax))
3624	{
3625	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3626	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3627	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3628	fBadOrDisabledFifo = true;
3629	continue;
3630	}
3631	RT_UNTRUSTED_VALIDATED_FENCE();
3632	if (RT_UNLIKELY(offCurrentCmd & 3))
3633	{
3634	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3635	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3636	offCurrentCmd &= ~UINT32_C(3);
3637	}
3638
3639	/*
3640	* Update the cursor position before we start on the FIFO commands.
3641	*/
3642	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3643	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3644	{
3645	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3646	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3647	{ /* halfways likely */ }
3648	else
3649	{
3650	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3651	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3652	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3653	}
3654	}
3655
3656	/*
3657	* Mark the FIFO as busy.
3658	*/
3659	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3660	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3661	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3662
3663	/*
3664	* Execute all queued FIFO commands.
3665	* Quit if pending external command or changes in the thread state.
3666	*/
3667	bool fDone = false;
3668	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3669	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3670	{
3671	uint32_t cbPayload = 0;
3672	uint32_t u32IrqStatus = 0;
3673
3674	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3675
3676	/* First check any pending actions. */
3677	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3678	{
3679	vmsvgaR3ChangeMode(pThis, pThisCC);
3680	# ifdef VBOX_WITH_VMSVGA3D
3681	if (pThisCC->svga.p3dState != NULL)
3682	vmsvga3dChangeMode(pThisCC);
3683	# endif
3684	}
3685
3686	/* Check for pending external commands (reset). */
3687	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3688	break;
3689
3690	/*
3691	* Process the command.
3692	*/
3693	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3694	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3695	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3696	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3697	switch (enmCmdId)
3698	{
3699	case SVGA_CMD_INVALID_CMD:
3700	/* Nothing to do. */
3701	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3702	break;
3703
3704	case SVGA_CMD_FENCE:
3705	{
3706	SVGAFifoCmdFence *pCmdFence;
3707	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3709	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3710	{
3711	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3712	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3713
3714	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3715	{
3716	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3717	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3718	}
3719	else
3720	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3721	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3722	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3723	{
3724	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3725	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3726	}
3727	}
3728	else
3729	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3730	break;
3731	}
3732	case SVGA_CMD_UPDATE:
3733	case SVGA_CMD_UPDATE_VERBOSE:
3734	{
3735	SVGAFifoCmdUpdate *pUpdate;
3736	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3737	if (enmCmdId == SVGA_CMD_UPDATE)
3738	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3739	else
3740	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3741	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3742	/** @todo Multiple screens? */
3743	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3744	AssertBreak(pScreen);
3745	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3746	break;
3747	}
3748
3749	case SVGA_CMD_DEFINE_CURSOR:
3750	{
3751	/* Followed by bitmap data. */
3752	SVGAFifoCmdDefineCursor *pCursor;
3753	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3754	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3755
3756	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3757	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3758	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3759	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3760	AssertBreak(pCursor->andMaskDepth <= 32);
3761	AssertBreak(pCursor->xorMaskDepth <= 32);
3762	RT_UNTRUSTED_VALIDATED_FENCE();
3763
3764	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3765	uint32_t cbAndMask = cbAndLine * pCursor->height;
3766	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3767	uint32_t cbXorMask = cbXorLine * pCursor->height;
3768	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3769
3770	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3771	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3772	break;
3773	}
3774
3775	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3776	{
3777	/* Followed by bitmap data. */
3778	uint32_t cbCursorShape, cbAndMask;
3779	uint8_t *pCursorCopy;
3780	uint32_t cbCmd;
3781
3782	SVGAFifoCmdDefineAlphaCursor *pCursor;
3783	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3784	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3785
3786	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3787
3788	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3789	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3790	RT_UNTRUSTED_VALIDATED_FENCE();
3791
3792	/* Refetch the bitmap data as well. */
3793	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3794	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3795	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3796
3797	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3798	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3799	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3800	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3801
3802	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3803	AssertBreak(pCursorCopy);
3804
3805	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3806	memset(pCursorCopy, 0xff, cbAndMask);
3807	/* Colour data */
3808	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3809
3810	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3811	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3812	break;
3813	}
3814
3815	case SVGA_CMD_ESCAPE:
3816	{
3817	/* Followed by nsize bytes of data. */
3818	SVGAFifoCmdEscape *pEscape;
3819	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3820	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3821
3822	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3823	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3824	RT_UNTRUSTED_VALIDATED_FENCE();
3825	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3826	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3827
3828	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3829	{
3830	AssertBreak(pEscape->size >= sizeof(uint32_t));
3831	RT_UNTRUSTED_VALIDATED_FENCE();
3832	uint32_t cmd = (uint32_t )(pEscape + 1);
3833	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3834
3835	switch (cmd)
3836	{
3837	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3838	{
3839	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3840	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3841	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3842
3843	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3844	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3845	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3846
3847	RT_NOREF_PV(pVideoCmd);
3848	break;
3849
3850	}
3851
3852	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3853	{
3854	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3855	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3856	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3857	RT_NOREF_PV(pVideoCmd);
3858	break;
3859	}
3860
3861	default:
3862	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3863	break;
3864	}
3865	}
3866	else
3867	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3868
3869	break;
3870	}
3871	# ifdef VBOX_WITH_VMSVGA3D
3872	case SVGA_CMD_DEFINE_GMR2:
3873	{
3874	SVGAFifoCmdDefineGMR2 *pCmd;
3875	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3876	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3877	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3878
3879	/* Validate current GMR id. */
3880	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3881	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3882	RT_UNTRUSTED_VALIDATED_FENCE();
3883
3884	if (!pCmd->numPages)
3885	{
3886	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3887	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3888	}
3889	else
3890	{
3891	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3892	if (pGMR->cMaxPages)
3893	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3894
3895	/* Not sure if we should always free the descriptor, but for simplicity
3896	we do so if the new size is smaller than the current. */
3897	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3898	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3899	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3900
3901	pGMR->cMaxPages = pCmd->numPages;
3902	/* The rest is done by the REMAP_GMR2 command. */
3903	}
3904	break;
3905	}
3906
3907	case SVGA_CMD_REMAP_GMR2:
3908	{
3909	/* Followed by page descriptors or guest ptr. */
3910	SVGAFifoCmdRemapGMR2 *pCmd;
3911	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3912	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3913
3914	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3915	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3916	RT_UNTRUSTED_VALIDATED_FENCE();
3917
3918	/* Calculate the size of what comes after next and fetch it. */
3919	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3920	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3921	cbCmd += sizeof(SVGAGuestPtr);
3922	else
3923	{
3924	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3925	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3926	{
3927	cbCmd += cbPageDesc;
3928	pCmd->numPages = 1;
3929	}
3930	else
3931	{
3932	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3933	cbCmd += cbPageDesc * pCmd->numPages;
3934	}
3935	}
3936	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3937
3938	/* Validate current GMR id and size. */
3939	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3940	RT_UNTRUSTED_VALIDATED_FENCE();
3941	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3942	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3943	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3944	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3945
3946	if (pCmd->numPages == 0)
3947	break;
3948
3949	/** @todo Move to a separate function vmsvgaGMRRemap() */
3950
3951	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3952	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3953
3954	/*
3955	* We flatten the existing descriptors into a page array, overwrite the
3956	* pages specified in this command and then recompress the descriptor.
3957	*/
3958	/** @todo Optimize the GMR remap algorithm! */
3959
3960	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3961	uint64_t *paNewPage64 = NULL;
3962	if (pGMR->paDesc)
3963	{
3964	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3965
3966	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3967	AssertBreak(paNewPage64);
3968
3969	uint32_t idxPage = 0;
3970	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3971	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3972	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3973	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3974	RT_UNTRUSTED_VALIDATED_FENCE();
3975	}
3976
3977	/* Free the old GMR if present. */
3978	if (pGMR->paDesc)
3979	RTMemFree(pGMR->paDesc);
3980
3981	/* Allocate the maximum amount possible (everything non-continuous) */
3982	PVMSVGAGMRDESCRIPTOR paDescs;
3983	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3984	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3985
3986	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3987	{
3988	/** @todo */
3989	AssertFailed();
3990	pGMR->numDescriptors = 0;
3991	}
3992	else
3993	{
3994	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3995	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3996	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3997
3998	if (paNewPage64)
3999	{
4000	/* Overwrite the old page array with the new page values. */
4001	if (fGCPhys64)
4002	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4003	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4004	else
4005	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4006	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4007
4008	/* Use the updated page array instead of the command data. */
4009	fGCPhys64 = true;
4010	paPages64 = paNewPage64;
4011	pCmd->numPages = cNewTotalPages;
4012	}
4013
4014	/* The first page. */
4015	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4016	* applied to paNewPage64. */
4017	RTGCPHYS GCPhys;
4018	if (fGCPhys64)
4019	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4020	else
4021	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4022	paDescs[0].GCPhys = GCPhys;
4023	paDescs[0].numPages = 1;
4024
4025	/* Subsequent pages. */
4026	uint32_t iDescriptor = 0;
4027	for (uint32_t i = 1; i < pCmd->numPages; i++)
4028	{
4029	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4030	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4031	else
4032	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4033
4034	/* Continuous physical memory? */
4035	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4036	{
4037	Assert(paDescs[iDescriptor].numPages);
4038	paDescs[iDescriptor].numPages++;
4039	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4040	}
4041	else
4042	{
4043	iDescriptor++;
4044	paDescs[iDescriptor].GCPhys = GCPhys;
4045	paDescs[iDescriptor].numPages = 1;
4046	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4047	}
4048	}
4049
4050	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4051	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4052	pGMR->numDescriptors = iDescriptor + 1;
4053	}
4054
4055	if (paNewPage64)
4056	RTMemFree(paNewPage64);
4057
4058	# ifdef DEBUG_GMR_ACCESS
4059	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4060	# endif
4061	break;
4062	}
4063	# endif // VBOX_WITH_VMSVGA3D
4064	case SVGA_CMD_DEFINE_SCREEN:
4065	{
4066	/* The size of this command is specified by the guest and depends on capabilities. */
4067	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4068
4069	SVGAFifoCmdDefineScreen *pCmd;
4070	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4071	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4072	RT_UNTRUSTED_VALIDATED_FENCE();
4073
4074	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4075	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4076	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4077
4078	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4079	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4080	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4081
4082	uint32_t const idScreen = pCmd->screen.id;
4083	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4084
4085	uint32_t const uWidth = pCmd->screen.size.width;
4086	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4087
4088	uint32_t const uHeight = pCmd->screen.size.height;
4089	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4090
4091	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4092	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4093	AssertBreak(cbWidth <= cbPitch);
4094
4095	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4096	AssertBreak(uScreenOffset < pThis->vram_size);
4097
4098	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4099	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4100	AssertBreak( (uHeight == 0 && cbPitch == 0)
4101	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4102	RT_UNTRUSTED_VALIDATED_FENCE();
4103
4104	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4105
4106	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4107
4108	pScreen->fDefined = true;
4109	pScreen->fModified = true;
4110	pScreen->fuScreen = pCmd->screen.flags;
4111	pScreen->idScreen = idScreen;
4112	if (!fBlank)
4113	{
4114	AssertBreak(uWidth > 0 && uHeight > 0);
4115
4116	pScreen->xOrigin = pCmd->screen.root.x;
4117	pScreen->yOrigin = pCmd->screen.root.y;
4118	pScreen->cWidth = uWidth;
4119	pScreen->cHeight = uHeight;
4120	pScreen->offVRAM = uScreenOffset;
4121	pScreen->cbPitch = cbPitch;
4122	pScreen->cBpp = 32;
4123	}
4124	else
4125	{
4126	/* Keep old values. */
4127	}
4128
4129	pThis->svga.fGFBRegisters = false;
4130	vmsvgaR3ChangeMode(pThis, pThisCC);
4131	break;
4132	}
4133
4134	case SVGA_CMD_DESTROY_SCREEN:
4135	{
4136	SVGAFifoCmdDestroyScreen *pCmd;
4137	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4138	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4139
4140	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4141
4142	uint32_t const idScreen = pCmd->screenId;
4143	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4144	RT_UNTRUSTED_VALIDATED_FENCE();
4145
4146	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4147	pScreen->fModified = true;
4148	pScreen->fDefined = false;
4149	pScreen->idScreen = idScreen;
4150
4151	vmsvgaR3ChangeMode(pThis, pThisCC);
4152	break;
4153	}
4154
4155	case SVGA_CMD_DEFINE_GMRFB:
4156	{
4157	SVGAFifoCmdDefineGMRFB *pCmd;
4158	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4159	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4160
4161	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4162	pSVGAState->GMRFB.ptr = pCmd->ptr;
4163	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4164	pSVGAState->GMRFB.format = pCmd->format;
4165	break;
4166	}
4167
4168	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4169	{
4170	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4171	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4172	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4173
4174	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4175	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4176
4177	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4178	RT_UNTRUSTED_VALIDATED_FENCE();
4179
4180	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4181	AssertBreak(pScreen);
4182
4183	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4184	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4185
4186	/* Clip destRect to the screen dimensions. */
4187	SVGASignedRect screenRect;
4188	screenRect.left = 0;
4189	screenRect.top = 0;
4190	screenRect.right = pScreen->cWidth;
4191	screenRect.bottom = pScreen->cHeight;
4192	SVGASignedRect clipRect = pCmd->destRect;
4193	vmsvgaR3ClipRect(&screenRect, &clipRect);
4194	RT_UNTRUSTED_VALIDATED_FENCE();
4195
4196	uint32_t const width = clipRect.right - clipRect.left;
4197	uint32_t const height = clipRect.bottom - clipRect.top;
4198
4199	if ( width == 0
4200	\|\| height == 0)
4201	break; /* Nothing to do. */
4202
4203	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4204	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4205
4206	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4207	* Prepare parameters for vmsvgaR3GmrTransfer.
4208	*/
4209	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4210
4211	/* Destination: host buffer which describes the screen 0 VRAM.
4212	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4213	*/
4214	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4215	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4216	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4217	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4218	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4219	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4220	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4221	+ cbScanline * clipRect.top;
4222	int32_t const cbHstPitch = cbScanline;
4223
4224	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4225	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4226	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4227	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4228	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4229
4230	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4231	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4232	gstPtr, offGst, cbGstPitch,
4233	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4234	AssertRC(rc);
4235	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4236	break;
4237	}
4238
4239	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4240	{
4241	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4242	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4243	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4244
4245	/* Note! This can fetch 3d render results as well!! */
4246	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4247	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4248
4249	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4250	RT_UNTRUSTED_VALIDATED_FENCE();
4251
4252	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4253	AssertBreak(pScreen);
4254
4255	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4256	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4257
4258	/* Clip destRect to the screen dimensions. */
4259	SVGASignedRect screenRect;
4260	screenRect.left = 0;
4261	screenRect.top = 0;
4262	screenRect.right = pScreen->cWidth;
4263	screenRect.bottom = pScreen->cHeight;
4264	SVGASignedRect clipRect = pCmd->srcRect;
4265	vmsvgaR3ClipRect(&screenRect, &clipRect);
4266	RT_UNTRUSTED_VALIDATED_FENCE();
4267
4268	uint32_t const width = clipRect.right - clipRect.left;
4269	uint32_t const height = clipRect.bottom - clipRect.top;
4270
4271	if ( width == 0
4272	\|\| height == 0)
4273	break; /* Nothing to do. */
4274
4275	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4276	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4277
4278	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4279	* Prepare parameters for vmsvgaR3GmrTransfer.
4280	*/
4281	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4282
4283	/* Source: host buffer which describes the screen 0 VRAM.
4284	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4285	*/
4286	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4287	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4288	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4289	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4290	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4291	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4292	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4293	+ cbScanline * clipRect.top;
4294	int32_t const cbHstPitch = cbScanline;
4295
4296	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4297	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4298	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4299	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4300	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4301
4302	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4303	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4304	gstPtr, offGst, cbGstPitch,
4305	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4306	AssertRC(rc);
4307	break;
4308	}
4309
4310	case SVGA_CMD_ANNOTATION_FILL:
4311	{
4312	SVGAFifoCmdAnnotationFill *pCmd;
4313	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4314	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4315
4316	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4317	pSVGAState->colorAnnotation = pCmd->color;
4318	break;
4319	}
4320
4321	case SVGA_CMD_ANNOTATION_COPY:
4322	{
4323	SVGAFifoCmdAnnotationCopy *pCmd;
4324	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4325	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4326
4327	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4328	AssertFailed();
4329	break;
4330	}
4331
4332	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4333
4334	default:
4335	# ifdef VBOX_WITH_VMSVGA3D
4336	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4337	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4338	{
4339	RT_UNTRUSTED_VALIDATED_FENCE();
4340
4341	/* All 3d commands start with a common header, which defines the size of the command. */
4342	SVGA3dCmdHeader *pHdr;
4343	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4344	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4345	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4346	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4347
4348	if (RT_LIKELY(pThis->svga.f3DEnabled))
4349	{ /* likely */ }
4350	else
4351	{
4352	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4353	break;
4354	}
4355
4356	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4357	* Check that the 3D command has at least a_cbMin of payload bytes after the
4358	* header. Will break out of the switch if it doesn't.
4359	*/
4360	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4361	if (1) { \
4362	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4363	RT_UNTRUSTED_VALIDATED_FENCE(); \
4364	} else do {} while (0)
4365	switch ((int)enmCmdId)
4366	{
4367	case SVGA_3D_CMD_SURFACE_DEFINE:
4368	{
4369	uint32_t cMipLevels;
4370	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4371	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4372	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4373
4374	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4375	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4376	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4377	# ifdef DEBUG_GMR_ACCESS
4378	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4379	# endif
4380	break;
4381	}
4382
4383	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4384	{
4385	uint32_t cMipLevels;
4386	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4387	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4388	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4389
4390	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4391	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4392	pCmd->multisampleCount, pCmd->autogenFilter,
4393	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4394	break;
4395	}
4396
4397	case SVGA_3D_CMD_SURFACE_DESTROY:
4398	{
4399	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4400	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4401	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4402	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4403	break;
4404	}
4405
4406	case SVGA_3D_CMD_SURFACE_COPY:
4407	{
4408	uint32_t cCopyBoxes;
4409	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4410	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4411	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4412
4413	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4414	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4415	break;
4416	}
4417
4418	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4419	{
4420	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4421	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4422	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4423
4424	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4425	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4426	break;
4427	}
4428
4429	case SVGA_3D_CMD_SURFACE_DMA:
4430	{
4431	uint32_t cCopyBoxes;
4432	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4433	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4434	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4435
4436	uint64_t u64NanoTS = 0;
4437	if (LogRelIs3Enabled())
4438	u64NanoTS = RTTimeNanoTS();
4439	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4440	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4441	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4442	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4443	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4444	if (LogRelIs3Enabled())
4445	{
4446	if (cCopyBoxes)
4447	{
4448	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4449	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4450	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4451	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4452	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4453	}
4454	}
4455	break;
4456	}
4457
4458	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4459	{
4460	uint32_t cRects;
4461	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4462	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4463	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4464
4465	uint64_t u64NanoTS = 0;
4466	if (LogRelIs3Enabled())
4467	u64NanoTS = RTTimeNanoTS();
4468	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4469	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4470	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4471	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4472	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4473	if (LogRelIs3Enabled())
4474	{
4475	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4476	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4477	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4478	pFirstRect->left, pFirstRect->top,
4479	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4480	}
4481	break;
4482	}
4483
4484	case SVGA_3D_CMD_CONTEXT_DEFINE:
4485	{
4486	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4487	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4488	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4489
4490	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4491	break;
4492	}
4493
4494	case SVGA_3D_CMD_CONTEXT_DESTROY:
4495	{
4496	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4497	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4498	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4499
4500	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4501	break;
4502	}
4503
4504	case SVGA_3D_CMD_SETTRANSFORM:
4505	{
4506	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4507	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4508	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4509
4510	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4511	break;
4512	}
4513
4514	case SVGA_3D_CMD_SETZRANGE:
4515	{
4516	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4517	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4518	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4519
4520	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4521	break;
4522	}
4523
4524	case SVGA_3D_CMD_SETRENDERSTATE:
4525	{
4526	uint32_t cRenderStates;
4527	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4528	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4529	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4530
4531	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4532	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4533	break;
4534	}
4535
4536	case SVGA_3D_CMD_SETRENDERTARGET:
4537	{
4538	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4539	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4540	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4541
4542	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4543	break;
4544	}
4545
4546	case SVGA_3D_CMD_SETTEXTURESTATE:
4547	{
4548	uint32_t cTextureStates;
4549	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4550	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4551	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4552
4553	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4554	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4555	break;
4556	}
4557
4558	case SVGA_3D_CMD_SETMATERIAL:
4559	{
4560	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4561	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4562	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4563
4564	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4565	break;
4566	}
4567
4568	case SVGA_3D_CMD_SETLIGHTDATA:
4569	{
4570	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4571	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4572	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4573
4574	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4575	break;
4576	}
4577
4578	case SVGA_3D_CMD_SETLIGHTENABLED:
4579	{
4580	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4581	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4582	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4583
4584	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4585	break;
4586	}
4587
4588	case SVGA_3D_CMD_SETVIEWPORT:
4589	{
4590	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4591	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4592	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4593
4594	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4595	break;
4596	}
4597
4598	case SVGA_3D_CMD_SETCLIPPLANE:
4599	{
4600	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4601	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4602	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4603
4604	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4605	break;
4606	}
4607
4608	case SVGA_3D_CMD_CLEAR:
4609	{
4610	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4611	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4612	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4613
4614	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4615	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4616	break;
4617	}
4618
4619	case SVGA_3D_CMD_PRESENT:
4620	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4621	{
4622	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4623	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4624	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4625	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4626	else
4627	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4628
4629	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4630
4631	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4632	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4633	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4634	break;
4635	}
4636
4637	case SVGA_3D_CMD_SHADER_DEFINE:
4638	{
4639	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4640	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4641	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4642
4643	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4644	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4645	break;
4646	}
4647
4648	case SVGA_3D_CMD_SHADER_DESTROY:
4649	{
4650	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4651	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4652	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4653
4654	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4655	break;
4656	}
4657
4658	case SVGA_3D_CMD_SET_SHADER:
4659	{
4660	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4661	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4662	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4663
4664	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4665	break;
4666	}
4667
4668	case SVGA_3D_CMD_SET_SHADER_CONST:
4669	{
4670	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4671	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4672	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4673
4674	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4675	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4676	break;
4677	}
4678
4679	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4680	{
4681	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4682	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4683	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4684
4685	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4686	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4687	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4688	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4689	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4690
4691	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4692	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4693
4694	RT_UNTRUSTED_VALIDATED_FENCE();
4695
4696	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4697	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4698	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4699
4700	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4701	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4702	pNumRange, cVertexDivisor, pVertexDivisor);
4703	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4704	break;
4705	}
4706
4707	case SVGA_3D_CMD_SETSCISSORRECT:
4708	{
4709	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4710	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4711	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4712
4713	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4714	break;
4715	}
4716
4717	case SVGA_3D_CMD_BEGIN_QUERY:
4718	{
4719	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4720	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4721	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4722
4723	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4724	break;
4725	}
4726
4727	case SVGA_3D_CMD_END_QUERY:
4728	{
4729	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4730	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4731	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4732
4733	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4734	break;
4735	}
4736
4737	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4738	{
4739	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4740	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4741	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4742
4743	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4744	break;
4745	}
4746
4747	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4748	{
4749	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4750	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4751	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4752
4753	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4754	break;
4755	}
4756
4757	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4758	/* context id + surface id? */
4759	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4760	break;
4761	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4762	/* context id + surface id? */
4763	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4764	break;
4765
4766	default:
4767	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4768	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4769	break;
4770	}
4771	}
4772	else
4773	# endif // VBOX_WITH_VMSVGA3D
4774	{
4775	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4776	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4777	}
4778	}
4779
4780	/* Go to the next slot */
4781	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4782	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4783	if (offCurrentCmd >= offFifoMax)
4784	{
4785	offCurrentCmd -= offFifoMax - offFifoMin;
4786	Assert(offCurrentCmd >= offFifoMin);
4787	Assert(offCurrentCmd < offFifoMax);
4788	}
4789	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4790	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4791
4792	/*
4793	* Raise IRQ if required. Must enter the critical section here
4794	* before making final decisions here, otherwise cubebench and
4795	* others may end up waiting forever.
4796	*/
4797	if ( u32IrqStatus
4798	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4799	{
4800	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4801	AssertRC(rc2);
4802
4803	/* FIFO progress might trigger an interrupt. */
4804	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4805	{
4806	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4807	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4808	}
4809
4810	/* Unmasked IRQ pending? */
4811	if (pThis->svga.u32IrqMask & u32IrqStatus)
4812	{
4813	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4814	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4815	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4816	}
4817
4818	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4819	}
4820	}
4821
4822	/* If really done, clear the busy flag. */
4823	if (fDone)
4824	{
4825	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4826	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4827	}
4828	}
4829
4830	/*
4831	* Free the bounce buffer. (There are no returns above!)
4832	*/
4833	RTMemFree(pbBounceBuf);
4834
4835	return VINF_SUCCESS;
4836	}
4837
4838	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4839	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4840	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4841
4842	#ifdef VBOX_WITH_VMSVGA3D
4843	/**
4844	* Free the specified GMR
4845	*
4846	* @param pThisCC The VGA/VMSVGA state for ring-3.
4847	* @param idGMR GMR id
4848	*/
4849	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4850	{
4851	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4852
4853	/* Free the old descriptor if present. */
4854	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4855	if ( pGMR->numDescriptors
4856	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4857	{
4858	# ifdef DEBUG_GMR_ACCESS
4859	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4860	# endif
4861
4862	Assert(pGMR->paDesc);
4863	RTMemFree(pGMR->paDesc);
4864	pGMR->paDesc = NULL;
4865	pGMR->numDescriptors = 0;
4866	pGMR->cbTotal = 0;
4867	pGMR->cMaxPages = 0;
4868	}
4869	Assert(!pGMR->cMaxPages);
4870	Assert(!pGMR->cbTotal);
4871	}
4872	#endif /* VBOX_WITH_VMSVGA3D */
4873
4874	/**
4875	* Copy between a GMR and a host memory buffer.
4876	*
4877	* @returns VBox status code.
4878	* @param pThis The shared VGA/VMSVGA instance data.
4879	* @param pThisCC The VGA/VMSVGA state for ring-3.
4880	* @param enmTransferType Transfer type (read/write)
4881	* @param pbHstBuf Host buffer pointer (valid)
4882	* @param cbHstBuf Size of host buffer (valid)
4883	* @param offHst Host buffer offset of the first scanline
4884	* @param cbHstPitch Destination buffer pitch
4885	* @param gstPtr GMR description
4886	* @param offGst Guest buffer offset of the first scanline
4887	* @param cbGstPitch Guest buffer pitch
4888	* @param cbWidth Width in bytes to copy
4889	* @param cHeight Number of scanllines to copy
4890	*/
4891	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4892	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4893	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4894	uint32_t cbWidth, uint32_t cHeight)
4895	{
4896	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4897	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4898	int rc;
4899
4900	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4901	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4902	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4903	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4904	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4905
4906	PGMR pGMR;
4907	uint32_t cbGmr; /* The GMR size in bytes. */
4908	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4909	{
4910	pGMR = NULL;
4911	cbGmr = pThis->vram_size;
4912	}
4913	else
4914	{
4915	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4916	RT_UNTRUSTED_VALIDATED_FENCE();
4917	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4918	cbGmr = pGMR->cbTotal;
4919	}
4920
4921	/*
4922	* GMR
4923	*/
4924	/* Calculate GMR offset of the data to be copied. */
4925	AssertMsgReturn(gstPtr.offset < cbGmr,
4926	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4927	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4928	VERR_INVALID_PARAMETER);
4929	RT_UNTRUSTED_VALIDATED_FENCE();
4930	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4931	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4932	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4933	VERR_INVALID_PARAMETER);
4934	RT_UNTRUSTED_VALIDATED_FENCE();
4935	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4936
4937	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4938	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4939	AssertMsgReturn(cbGmrScanline != 0,
4940	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4941	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4942	VERR_INVALID_PARAMETER);
4943	RT_UNTRUSTED_VALIDATED_FENCE();
4944	AssertMsgReturn(cbWidth <= cbGmrScanline,
4945	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4946	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4947	VERR_INVALID_PARAMETER);
4948	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4949	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4950	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4951	VERR_INVALID_PARAMETER);
4952	RT_UNTRUSTED_VALIDATED_FENCE();
4953
4954	/* How many bytes are available for the data in the GMR. */
4955	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4956
4957	/* How many scanlines would fit into the available data. */
4958	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4959	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4960	if (cbWidth <= cbGmrLastScanline)
4961	++cGmrScanlines;
4962
4963	if (cHeight > cGmrScanlines)
4964	cHeight = cGmrScanlines;
4965
4966	AssertMsgReturn(cHeight > 0,
4967	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4968	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4969	VERR_INVALID_PARAMETER);
4970	RT_UNTRUSTED_VALIDATED_FENCE();
4971
4972	/*
4973	* Host buffer.
4974	*/
4975	AssertMsgReturn(offHst < cbHstBuf,
4976	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4977	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4978	VERR_INVALID_PARAMETER);
4979
4980	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4981	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4982	AssertMsgReturn(cbHstScanline != 0,
4983	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4984	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4985	VERR_INVALID_PARAMETER);
4986	AssertMsgReturn(cbWidth <= cbHstScanline,
4987	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4988	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4989	VERR_INVALID_PARAMETER);
4990	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4991	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4992	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4993	VERR_INVALID_PARAMETER);
4994
4995	/* How many bytes are available for the data in the buffer. */
4996	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4997
4998	/* How many scanlines would fit into the available data. */
4999	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5000	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5001	if (cbWidth <= cbHstLastScanline)
5002	++cHstScanlines;
5003
5004	if (cHeight > cHstScanlines)
5005	cHeight = cHstScanlines;
5006
5007	AssertMsgReturn(cHeight > 0,
5008	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5009	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5010	VERR_INVALID_PARAMETER);
5011
5012	uint8_t *pbHst = pbHstBuf + offHst;
5013
5014	/* Shortcut for the framebuffer. */
5015	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5016	{
5017	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5018
5019	uint8_t const *pbSrc;
5020	int32_t cbSrcPitch;
5021	uint8_t *pbDst;
5022	int32_t cbDstPitch;
5023
5024	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5025	{
5026	pbSrc = pbHst;
5027	cbSrcPitch = cbHstPitch;
5028	pbDst = pbGst;
5029	cbDstPitch = cbGstPitch;
5030	}
5031	else
5032	{
5033	pbSrc = pbGst;
5034	cbSrcPitch = cbGstPitch;
5035	pbDst = pbHst;
5036	cbDstPitch = cbHstPitch;
5037	}
5038
5039	if ( cbWidth == (uint32_t)cbGstPitch
5040	&& cbGstPitch == cbHstPitch)
5041	{
5042	/* Entire scanlines, positive pitch. */
5043	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5044	}
5045	else
5046	{
5047	for (uint32_t i = 0; i < cHeight; ++i)
5048	{
5049	memcpy(pbDst, pbSrc, cbWidth);
5050
5051	pbDst += cbDstPitch;
5052	pbSrc += cbSrcPitch;
5053	}
5054	}
5055	return VINF_SUCCESS;
5056	}
5057
5058	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5059	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5060
5061	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5062	uint32_t iDesc = 0; /* Index in the descriptor array. */
5063	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5064	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5065	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5066	for (uint32_t i = 0; i < cHeight; ++i)
5067	{
5068	uint32_t cbCurrentWidth = cbWidth;
5069	uint32_t offGmrCurrent = offGmrScanline;
5070	uint8_t *pbCurrentHost = pbHstScanline;
5071
5072	/* Find the right descriptor */
5073	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5074	{
5075	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5076	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5077	++iDesc;
5078	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5079	}
5080
5081	while (cbCurrentWidth)
5082	{
5083	uint32_t cbToCopy;
5084
5085	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5086	{
5087	cbToCopy = cbCurrentWidth;
5088	}
5089	else
5090	{
5091	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5092	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5093	}
5094
5095	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5096
5097	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5098
5099	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5100	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5101	else
5102	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5103	AssertRCBreak(rc);
5104
5105	cbCurrentWidth -= cbToCopy;
5106	offGmrCurrent += cbToCopy;
5107	pbCurrentHost += cbToCopy;
5108
5109	/* Go to the next descriptor if there's anything left. */
5110	if (cbCurrentWidth)
5111	{
5112	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5113	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5114	++iDesc;
5115	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5116	}
5117	}
5118
5119	offGmrScanline += cbGstPitch;
5120	pbHstScanline += cbHstPitch;
5121	}
5122
5123	return VINF_SUCCESS;
5124	}
5125
5126
5127	/**
5128	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5129	*
5130	* @param pSizeSrc Source surface dimensions.
5131	* @param pSizeDest Destination surface dimensions.
5132	* @param pBox Coordinates to be clipped.
5133	*/
5134	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5135	{
5136	/* Src x, w */
5137	if (pBox->srcx > pSizeSrc->width)
5138	pBox->srcx = pSizeSrc->width;
5139	if (pBox->w > pSizeSrc->width - pBox->srcx)
5140	pBox->w = pSizeSrc->width - pBox->srcx;
5141
5142	/* Src y, h */
5143	if (pBox->srcy > pSizeSrc->height)
5144	pBox->srcy = pSizeSrc->height;
5145	if (pBox->h > pSizeSrc->height - pBox->srcy)
5146	pBox->h = pSizeSrc->height - pBox->srcy;
5147
5148	/* Src z, d */
5149	if (pBox->srcz > pSizeSrc->depth)
5150	pBox->srcz = pSizeSrc->depth;
5151	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5152	pBox->d = pSizeSrc->depth - pBox->srcz;
5153
5154	/* Dest x, w */
5155	if (pBox->x > pSizeDest->width)
5156	pBox->x = pSizeDest->width;
5157	if (pBox->w > pSizeDest->width - pBox->x)
5158	pBox->w = pSizeDest->width - pBox->x;
5159
5160	/* Dest y, h */
5161	if (pBox->y > pSizeDest->height)
5162	pBox->y = pSizeDest->height;
5163	if (pBox->h > pSizeDest->height - pBox->y)
5164	pBox->h = pSizeDest->height - pBox->y;
5165
5166	/* Dest z, d */
5167	if (pBox->z > pSizeDest->depth)
5168	pBox->z = pSizeDest->depth;
5169	if (pBox->d > pSizeDest->depth - pBox->z)
5170	pBox->d = pSizeDest->depth - pBox->z;
5171	}
5172
5173	/**
5174	* Unsigned coordinates in pBox. Clip to [0; pSize).
5175	*
5176	* @param pSize Source surface dimensions.
5177	* @param pBox Coordinates to be clipped.
5178	*/
5179	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5180	{
5181	/* x, w */
5182	if (pBox->x > pSize->width)
5183	pBox->x = pSize->width;
5184	if (pBox->w > pSize->width - pBox->x)
5185	pBox->w = pSize->width - pBox->x;
5186
5187	/* y, h */
5188	if (pBox->y > pSize->height)
5189	pBox->y = pSize->height;
5190	if (pBox->h > pSize->height - pBox->y)
5191	pBox->h = pSize->height - pBox->y;
5192
5193	/* z, d */
5194	if (pBox->z > pSize->depth)
5195	pBox->z = pSize->depth;
5196	if (pBox->d > pSize->depth - pBox->z)
5197	pBox->d = pSize->depth - pBox->z;
5198	}
5199
5200	/**
5201	* Clip.
5202	*
5203	* @param pBound Bounding rectangle.
5204	* @param pRect Rectangle to be clipped.
5205	*/
5206	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5207	{
5208	int32_t left;
5209	int32_t top;
5210	int32_t right;
5211	int32_t bottom;
5212
5213	/* Right order. */
5214	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5215	if (pRect->left < pRect->right)
5216	{
5217	left = pRect->left;
5218	right = pRect->right;
5219	}
5220	else
5221	{
5222	left = pRect->right;
5223	right = pRect->left;
5224	}
5225	if (pRect->top < pRect->bottom)
5226	{
5227	top = pRect->top;
5228	bottom = pRect->bottom;
5229	}
5230	else
5231	{
5232	top = pRect->bottom;
5233	bottom = pRect->top;
5234	}
5235
5236	if (left < pBound->left)
5237	left = pBound->left;
5238	if (right < pBound->left)
5239	right = pBound->left;
5240
5241	if (left > pBound->right)
5242	left = pBound->right;
5243	if (right > pBound->right)
5244	right = pBound->right;
5245
5246	if (top < pBound->top)
5247	top = pBound->top;
5248	if (bottom < pBound->top)
5249	bottom = pBound->top;
5250
5251	if (top > pBound->bottom)
5252	top = pBound->bottom;
5253	if (bottom > pBound->bottom)
5254	bottom = pBound->bottom;
5255
5256	pRect->left = left;
5257	pRect->right = right;
5258	pRect->top = top;
5259	pRect->bottom = bottom;
5260	}
5261
5262	/**
5263	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5264	* Unblock the FIFO I/O thread so it can respond to a state change.}
5265	*/
5266	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5267	{
5268	RT_NOREF(pDevIns);
5269	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5270	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5271	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5272	}
5273
5274	/**
5275	* Enables or disables dirty page tracking for the framebuffer
5276	*
5277	* @param pDevIns The device instance.
5278	* @param pThis The shared VGA/VMSVGA instance data.
5279	* @param fTraces Enable/disable traces
5280	*/
5281	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5282	{
5283	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5284	&& !fTraces)
5285	{
5286	//Assert(pThis->svga.fTraces);
5287	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5288	return;
5289	}
5290
5291	pThis->svga.fTraces = fTraces;
5292	if (pThis->svga.fTraces)
5293	{
5294	unsigned cbFrameBuffer = pThis->vram_size;
5295
5296	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5297	/** @todo How does this work with screens? */
5298	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5299	{
5300	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5301	Assert(pThis->svga.cbScanline);
5302	# endif
5303	/* Hardware enabled; return real framebuffer size .*/
5304	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5305	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5306	}
5307
5308	if (!pThis->svga.fVRAMTracking)
5309	{
5310	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5311	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5312	pThis->svga.fVRAMTracking = true;
5313	}
5314	}
5315	else
5316	{
5317	if (pThis->svga.fVRAMTracking)
5318	{
5319	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5320	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5321	pThis->svga.fVRAMTracking = false;
5322	}
5323	}
5324	}
5325
5326	/**
5327	* @callback_method_impl{FNPCIIOREGIONMAP}
5328	*/
5329	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5330	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5331	{
5332	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5333	int rc;
5334	RT_NOREF(pPciDev);
5335	Assert(pPciDev == pDevIns->apPciDevs[0]);
5336
5337	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5338	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5339	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5340	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5341	, VERR_INTERNAL_ERROR);
5342	if (GCPhysAddress != NIL_RTGCPHYS)
5343	{
5344	/*
5345	* Mapping the FIFO RAM.
5346	*/
5347	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5348	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5349	AssertRC(rc);
5350
5351	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5352	if (RT_SUCCESS(rc))
5353	{
5354	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5355	# ifdef DEBUG_FIFO_ACCESS
5356	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5357	# else
5358	GCPhysAddress + PAGE_SIZE - 1,
5359	# endif
5360	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5361	"VMSVGA FIFO");
5362	AssertRC(rc);
5363	}
5364	# endif
5365	if (RT_SUCCESS(rc))
5366	{
5367	pThis->svga.GCPhysFIFO = GCPhysAddress;
5368	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5369	}
5370	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5371	}
5372	else
5373	{
5374	Assert(pThis->svga.GCPhysFIFO);
5375	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5376	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5377	AssertRC(rc);
5378	# else
5379	rc = VINF_SUCCESS;
5380	# endif
5381	pThis->svga.GCPhysFIFO = 0;
5382	}
5383	return rc;
5384	}
5385
5386	# ifdef VBOX_WITH_VMSVGA3D
5387
5388	/**
5389	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5390	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5391	*
5392	* @param pDevIns The device instance.
5393	* @param pThis The The shared VGA/VMSVGA instance data.
5394	* @param pThisCC The VGA/VMSVGA state for ring-3.
5395	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5396	* UINT32_MAX is used, all surfaces are processed.
5397	*/
5398	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5399	{
5400	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5401	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5402	}
5403
5404
5405	/**
5406	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5407	*/
5408	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5409	{
5410	/* There might be a specific surface ID at the start of the
5411	arguments, if not show all surfaces. */
5412	uint32_t sid = UINT32_MAX;
5413	if (pszArgs)
5414	pszArgs = RTStrStripL(pszArgs);
5415	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5416	sid = RTStrToUInt32(pszArgs);
5417
5418	/* Verbose or terse display, we default to verbose. */
5419	bool fVerbose = true;
5420	if (RTStrIStr(pszArgs, "terse"))
5421	fVerbose = false;
5422
5423	/* The size of the ascii art (x direction, y is 3/4 of x). */
5424	uint32_t cxAscii = 80;
5425	if (RTStrIStr(pszArgs, "gigantic"))
5426	cxAscii = 300;
5427	else if (RTStrIStr(pszArgs, "huge"))
5428	cxAscii = 180;
5429	else if (RTStrIStr(pszArgs, "big"))
5430	cxAscii = 132;
5431	else if (RTStrIStr(pszArgs, "normal"))
5432	cxAscii = 80;
5433	else if (RTStrIStr(pszArgs, "medium"))
5434	cxAscii = 64;
5435	else if (RTStrIStr(pszArgs, "small"))
5436	cxAscii = 48;
5437	else if (RTStrIStr(pszArgs, "tiny"))
5438	cxAscii = 24;
5439
5440	/* Y invert the image when producing the ASCII art. */
5441	bool fInvY = false;
5442	if (RTStrIStr(pszArgs, "invy"))
5443	fInvY = true;
5444
5445	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5446	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5447	}
5448
5449
5450	/**
5451	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5452	*/
5453	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5454	{
5455	/* pszArg = "sid[>dir]"
5456	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5457	*/
5458	char *pszBitmapPath = NULL;
5459	uint32_t sid = UINT32_MAX;
5460	if (pszArgs)
5461	pszArgs = RTStrStripL(pszArgs);
5462	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5463	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5464	if ( pszBitmapPath
5465	&& *pszBitmapPath == '>')
5466	++pszBitmapPath;
5467
5468	const bool fVerbose = true;
5469	const uint32_t cxAscii = 0; /* No ASCII */
5470	const bool fInvY = false; /* Do not invert. */
5471	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5472	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5473	}
5474
5475	/**
5476	* Used to update screen offsets (positions) since appearently vmwgfx fails to pass correct offsets thru FIFO.
5477	*
5478	* @param pInterface The device instance.
5479	* @param cPosition The size of the pPosition array
5480	* @param pPosition Monitor positions. We assume for the disable monitors the positions is (-1, -1)
5481	*/
5482	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PRTPOINT pPosition)
5483	{
5484	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5485	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
5486
5487
5488	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5489	size_t cScreenCount = RT_ELEMENTS(pSVGAState->aScreens);
5490
5491	VMSVGASCREENOBJECT *pScreens = pSVGAState->aScreens;
5492	/* We assume cPositions is the # of outputs Xserver reports and pPosition is (-1, -1) for disabled monitors. */
5493	for (unsigned i = 0; i < cPositions; ++i)
5494	{
5495	/* Stop walking the array once we go thru all the monitors. */
5496	if (i >= cScreenCount)
5497	break;
5498	if ( pScreens[i].xOrigin == -1
5499	\|\| pScreens[i].yOrigin == -1)
5500	continue;
5501	if ( pScreens[i].xOrigin == pPosition[i].x
5502	&& pScreens[i].yOrigin == pPosition[i].y)
5503	continue;
5504	pScreens[i].xOrigin = pPosition[i].x;
5505	pScreens[i].yOrigin = pPosition[i].y;
5506	pScreens[i].fModified = true;
5507	}
5508	vmsvgaR3VBVAResize(pThis, pThisCC);
5509	}
5510
5511	/**
5512	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5513	*/
5514	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5515	{
5516	/* There might be a specific surface ID at the start of the
5517	arguments, if not show all contexts. */
5518	uint32_t sid = UINT32_MAX;
5519	if (pszArgs)
5520	pszArgs = RTStrStripL(pszArgs);
5521	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5522	sid = RTStrToUInt32(pszArgs);
5523
5524	/* Verbose or terse display, we default to verbose. */
5525	bool fVerbose = true;
5526	if (RTStrIStr(pszArgs, "terse"))
5527	fVerbose = false;
5528
5529	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5530	}
5531
5532	# endif /* VBOX_WITH_VMSVGA3D */
5533
5534	/**
5535	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5536	*/
5537	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5538	{
5539	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5540	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5541	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5542	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5543	RT_NOREF(pszArgs);
5544
5545	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5546	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5547	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5548	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5549	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5550	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5551	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5552	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5553	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5554	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5555	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5556	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5557	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5558	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5559	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5560	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5561	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5562	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5563	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5564	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5565	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5566	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5567	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5568	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5569	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5570
5571	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5572	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5573	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5574	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5575
5576	# ifdef VBOX_WITH_VMSVGA3D
5577	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5578	# endif
5579	if (pThisCC->pDrv)
5580	{
5581	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5582	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5583	}
5584
5585	/* Dump screen information. */
5586	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5587	{
5588	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5589	if (pScreen)
5590	{
5591	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5592	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5593	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5594	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5595	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5596	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5597	{
5598	pHlp->pfnPrintf(pHlp, " (");
5599	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5600	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5601	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5602	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5603	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5604	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5605	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5606	pHlp->pfnPrintf(pHlp, " BLANKING");
5607	pHlp->pfnPrintf(pHlp, " )");
5608	}
5609	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5610	}
5611	}
5612
5613	}
5614
5615	/**
5616	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5617	*/
5618	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5619	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5620	{
5621	RT_NOREF(uPass);
5622
5623	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5624	int rc;
5625
5626	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5627	{
5628	uint32_t cScreens = 0;
5629	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5630	AssertRCReturn(rc, rc);
5631	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5632	("cScreens=%#x\n", cScreens),
5633	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5634
5635	for (uint32_t i = 0; i < cScreens; ++i)
5636	{
5637	VMSVGASCREENOBJECT screen;
5638	RT_ZERO(screen);
5639
5640	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5641	AssertLogRelRCReturn(rc, rc);
5642
5643	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5644	{
5645	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5646	*pScreen = screen;
5647	pScreen->fModified = true;
5648	}
5649	else
5650	{
5651	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5652	}
5653	}
5654	}
5655	else
5656	{
5657	/* Try to setup at least the first screen. */
5658	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5659	pScreen->fDefined = true;
5660	pScreen->fModified = true;
5661	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5662	pScreen->idScreen = 0;
5663	pScreen->xOrigin = 0;
5664	pScreen->yOrigin = 0;
5665	pScreen->offVRAM = pThis->svga.uScreenOffset;
5666	pScreen->cbPitch = pThis->svga.cbScanline;
5667	pScreen->cWidth = pThis->svga.uWidth;
5668	pScreen->cHeight = pThis->svga.uHeight;
5669	pScreen->cBpp = pThis->svga.uBpp;
5670	}
5671
5672	return VINF_SUCCESS;
5673	}
5674
5675	/**
5676	* @copydoc FNSSMDEVLOADEXEC
5677	*/
5678	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5679	{
5680	RT_NOREF(uPass);
5681	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5682	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5683	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5684	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5685	int rc;
5686
5687	/* Load our part of the VGAState */
5688	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5689	AssertRCReturn(rc, rc);
5690
5691	/* Load the VGA framebuffer. */
5692	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5693	uint32_t cbVgaFramebuffer = _32K;
5694	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5695	{
5696	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5697	AssertRCReturn(rc, rc);
5698	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5699	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5700	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5701	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5702	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5703	}
5704	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5705	AssertRCReturn(rc, rc);
5706	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5707	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5708	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5709	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5710
5711	/* Load the VMSVGA state. */
5712	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5713	AssertRCReturn(rc, rc);
5714
5715	/* Load the active cursor bitmaps. */
5716	if (pSVGAState->Cursor.fActive)
5717	{
5718	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5719	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5720
5721	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5722	AssertRCReturn(rc, rc);
5723	}
5724
5725	/* Load the GMR state. */
5726	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5727	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5728	{
5729	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5730	AssertRCReturn(rc, rc);
5731	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5732	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5733	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5734	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5735	}
5736
5737	if (pThis->svga.cGMR != cGMR)
5738	{
5739	/* Reallocate GMR array. */
5740	Assert(pSVGAState->paGMR != NULL);
5741	RTMemFree(pSVGAState->paGMR);
5742	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5743	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5744	pThis->svga.cGMR = cGMR;
5745	}
5746
5747	for (uint32_t i = 0; i < cGMR; ++i)
5748	{
5749	PGMR pGMR = &pSVGAState->paGMR[i];
5750
5751	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5752	AssertRCReturn(rc, rc);
5753
5754	if (pGMR->numDescriptors)
5755	{
5756	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5757	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5758	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5759
5760	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5761	{
5762	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5763	AssertRCReturn(rc, rc);
5764	}
5765	}
5766	}
5767
5768	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5769	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5770	# endif
5771
5772	VMSVGA_STATE_LOAD LoadState;
5773	LoadState.pSSM = pSSM;
5774	LoadState.uVersion = uVersion;
5775	LoadState.uPass = uPass;
5776	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5777	AssertLogRelRCReturn(rc, rc);
5778
5779	return VINF_SUCCESS;
5780	}
5781
5782	/**
5783	* Reinit the video mode after the state has been loaded.
5784	*/
5785	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5786	{
5787	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5788	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5789	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5790
5791	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5792
5793	/* Set the active cursor. */
5794	if (pSVGAState->Cursor.fActive)
5795	{
5796	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5797	true /fVisible/,
5798	true /fAlpha/,
5799	pSVGAState->Cursor.xHotspot,
5800	pSVGAState->Cursor.yHotspot,
5801	pSVGAState->Cursor.width,
5802	pSVGAState->Cursor.height,
5803	pSVGAState->Cursor.pData);
5804	AssertRC(rc);
5805	}
5806	return VINF_SUCCESS;
5807	}
5808
5809	/**
5810	* Portion of SVGA state which must be saved in the FIFO thread.
5811	*/
5812	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5813	{
5814	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5815	int rc;
5816
5817	/* Save the screen objects. */
5818	/* Count defined screen object. */
5819	uint32_t cScreens = 0;
5820	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5821	{
5822	if (pSVGAState->aScreens[i].fDefined)
5823	++cScreens;
5824	}
5825
5826	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5827	AssertLogRelRCReturn(rc, rc);
5828
5829	for (uint32_t i = 0; i < cScreens; ++i)
5830	{
5831	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5832
5833	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5834	AssertLogRelRCReturn(rc, rc);
5835	}
5836	return VINF_SUCCESS;
5837	}
5838
5839	/**
5840	* @copydoc FNSSMDEVSAVEEXEC
5841	*/
5842	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5843	{
5844	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5845	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5846	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5847	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5848	int rc;
5849
5850	/* Save our part of the VGAState */
5851	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5852	AssertLogRelRCReturn(rc, rc);
5853
5854	/* Save the framebuffer backup. */
5855	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5856	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5857	AssertLogRelRCReturn(rc, rc);
5858
5859	/* Save the VMSVGA state. */
5860	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5861	AssertLogRelRCReturn(rc, rc);
5862
5863	/* Save the active cursor bitmaps. */
5864	if (pSVGAState->Cursor.fActive)
5865	{
5866	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5867	AssertLogRelRCReturn(rc, rc);
5868	}
5869
5870	/* Save the GMR state */
5871	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5872	AssertLogRelRCReturn(rc, rc);
5873	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5874	{
5875	PGMR pGMR = &pSVGAState->paGMR[i];
5876
5877	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5878	AssertLogRelRCReturn(rc, rc);
5879
5880	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5881	{
5882	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5883	AssertLogRelRCReturn(rc, rc);
5884	}
5885	}
5886
5887	/*
5888	* Must save some state (3D in particular) in the FIFO thread.
5889	*/
5890	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5891	AssertLogRelRCReturn(rc, rc);
5892
5893	return VINF_SUCCESS;
5894	}
5895
5896	/**
5897	* Destructor for PVMSVGAR3STATE structure.
5898	*
5899	* @param pThis The shared VGA/VMSVGA instance data.
5900	* @param pSVGAState Pointer to the structure. It is not deallocated.
5901	*/
5902	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5903	{
5904	# ifndef VMSVGA_USE_EMT_HALT_CODE
5905	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5906	{
5907	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5908	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5909	}
5910	# endif
5911
5912	if (pSVGAState->Cursor.fActive)
5913	{
5914	RTMemFree(pSVGAState->Cursor.pData);
5915	pSVGAState->Cursor.pData = NULL;
5916	pSVGAState->Cursor.fActive = false;
5917	}
5918
5919	if (pSVGAState->paGMR)
5920	{
5921	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5922	if (pSVGAState->paGMR[i].paDesc)
5923	RTMemFree(pSVGAState->paGMR[i].paDesc);
5924
5925	RTMemFree(pSVGAState->paGMR);
5926	pSVGAState->paGMR = NULL;
5927	}
5928	}
5929
5930	/**
5931	* Constructor for PVMSVGAR3STATE structure.
5932	*
5933	* @returns VBox status code.
5934	* @param pThis The shared VGA/VMSVGA instance data.
5935	* @param pSVGAState Pointer to the structure. It is already allocated.
5936	*/
5937	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5938	{
5939	int rc = VINF_SUCCESS;
5940	RT_ZERO(*pSVGAState);
5941
5942	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5943	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5944
5945	# ifndef VMSVGA_USE_EMT_HALT_CODE
5946	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5947	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5948	AssertRCReturn(rc, rc);
5949	# endif
5950
5951	return rc;
5952	}
5953
5954	/**
5955	* Initializes the host capabilities: registers and FIFO.
5956	*
5957	* @returns VBox status code.
5958	* @param pThis The shared VGA/VMSVGA instance data.
5959	* @param pThisCC The VGA/VMSVGA state for ring-3.
5960	*/
5961	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5962	{
5963	/* Register caps. */
5964	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5965	\| SVGA_CAP_GMR2
5966	\| SVGA_CAP_CURSOR
5967	\| SVGA_CAP_CURSOR_BYPASS_2
5968	\| SVGA_CAP_EXTENDED_FIFO
5969	\| SVGA_CAP_IRQMASK
5970	\| SVGA_CAP_PITCHLOCK
5971	\| SVGA_CAP_TRACES
5972	\| SVGA_CAP_SCREEN_OBJECT_2
5973	\| SVGA_CAP_ALPHA_CURSOR;
5974	# ifdef VBOX_WITH_VMSVGA3D
5975	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5976	# endif
5977
5978	/* Clear the FIFO. */
5979	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5980
5981	/* Setup FIFO capabilities. */
5982	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5983	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5984	\| SVGA_FIFO_CAP_GMR2
5985	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5986	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5987	\| SVGA_FIFO_CAP_RESERVE
5988	\| SVGA_FIFO_CAP_PITCHLOCK;
5989
5990	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5991	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5992	}
5993
5994	# ifdef VBOX_WITH_VMSVGA3D
5995	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5996	static const char * const g_apszVmSvgaDevCapNames[] =
5997	{
5998	"x3D", /* = 0 */
5999	"xMAX_LIGHTS",
6000	"xMAX_TEXTURES",
6001	"xMAX_CLIP_PLANES",
6002	"xVERTEX_SHADER_VERSION",
6003	"xVERTEX_SHADER",
6004	"xFRAGMENT_SHADER_VERSION",
6005	"xFRAGMENT_SHADER",
6006	"xMAX_RENDER_TARGETS",
6007	"xS23E8_TEXTURES",
6008	"xS10E5_TEXTURES",
6009	"xMAX_FIXED_VERTEXBLEND",
6010	"xD16_BUFFER_FORMAT",
6011	"xD24S8_BUFFER_FORMAT",
6012	"xD24X8_BUFFER_FORMAT",
6013	"xQUERY_TYPES",
6014	"xTEXTURE_GRADIENT_SAMPLING",
6015	"rMAX_POINT_SIZE",
6016	"xMAX_SHADER_TEXTURES",
6017	"xMAX_TEXTURE_WIDTH",
6018	"xMAX_TEXTURE_HEIGHT",
6019	"xMAX_VOLUME_EXTENT",
6020	"xMAX_TEXTURE_REPEAT",
6021	"xMAX_TEXTURE_ASPECT_RATIO",
6022	"xMAX_TEXTURE_ANISOTROPY",
6023	"xMAX_PRIMITIVE_COUNT",
6024	"xMAX_VERTEX_INDEX",
6025	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6026	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6027	"xMAX_VERTEX_SHADER_TEMPS",
6028	"xMAX_FRAGMENT_SHADER_TEMPS",
6029	"xTEXTURE_OPS",
6030	"xSURFACEFMT_X8R8G8B8",
6031	"xSURFACEFMT_A8R8G8B8",
6032	"xSURFACEFMT_A2R10G10B10",
6033	"xSURFACEFMT_X1R5G5B5",
6034	"xSURFACEFMT_A1R5G5B5",
6035	"xSURFACEFMT_A4R4G4B4",
6036	"xSURFACEFMT_R5G6B5",
6037	"xSURFACEFMT_LUMINANCE16",
6038	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6039	"xSURFACEFMT_ALPHA8",
6040	"xSURFACEFMT_LUMINANCE8",
6041	"xSURFACEFMT_Z_D16",
6042	"xSURFACEFMT_Z_D24S8",
6043	"xSURFACEFMT_Z_D24X8",
6044	"xSURFACEFMT_DXT1",
6045	"xSURFACEFMT_DXT2",
6046	"xSURFACEFMT_DXT3",
6047	"xSURFACEFMT_DXT4",
6048	"xSURFACEFMT_DXT5",
6049	"xSURFACEFMT_BUMPX8L8V8U8",
6050	"xSURFACEFMT_A2W10V10U10",
6051	"xSURFACEFMT_BUMPU8V8",
6052	"xSURFACEFMT_Q8W8V8U8",
6053	"xSURFACEFMT_CxV8U8",
6054	"xSURFACEFMT_R_S10E5",
6055	"xSURFACEFMT_R_S23E8",
6056	"xSURFACEFMT_RG_S10E5",
6057	"xSURFACEFMT_RG_S23E8",
6058	"xSURFACEFMT_ARGB_S10E5",
6059	"xSURFACEFMT_ARGB_S23E8",
6060	"xMISSING62",
6061	"xMAX_VERTEX_SHADER_TEXTURES",
6062	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6063	"xSURFACEFMT_V16U16",
6064	"xSURFACEFMT_G16R16",
6065	"xSURFACEFMT_A16B16G16R16",
6066	"xSURFACEFMT_UYVY",
6067	"xSURFACEFMT_YUY2",
6068	"xMULTISAMPLE_NONMASKABLESAMPLES",
6069	"xMULTISAMPLE_MASKABLESAMPLES",
6070	"xALPHATOCOVERAGE",
6071	"xSUPERSAMPLE",
6072	"xAUTOGENMIPMAPS",
6073	"xSURFACEFMT_NV12",
6074	"xSURFACEFMT_AYUV",
6075	"xMAX_CONTEXT_IDS",
6076	"xMAX_SURFACE_IDS",
6077	"xSURFACEFMT_Z_DF16",
6078	"xSURFACEFMT_Z_DF24",
6079	"xSURFACEFMT_Z_D24S8_INT",
6080	"xSURFACEFMT_BC4_UNORM",
6081	"xSURFACEFMT_BC5_UNORM", /* 83 */
6082	};
6083
6084	/**
6085	* Initializes the host 3D capabilities in FIFO.
6086	*
6087	* @returns VBox status code.
6088	* @param pThis The shared VGA/VMSVGA instance data.
6089	* @param pThisCC The VGA/VMSVGA state for ring-3.
6090	*/
6091	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6092	{
6093	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6094	bool fSavedBuffering = RTLogRelSetBuffering(true);
6095	SVGA3dCapsRecord *pCaps;
6096	SVGA3dCapPair *pData;
6097	uint32_t idxCap = 0;
6098
6099	/* 3d hardware version; latest and greatest */
6100	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6101	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6102
6103	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6104	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6105	pData = (SVGA3dCapPair *)&pCaps->data;
6106
6107	/* Fill out all 3d capabilities. */
6108	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6109	{
6110	uint32_t val = 0;
6111
6112	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6113	if (RT_SUCCESS(rc))
6114	{
6115	pData[idxCap][0] = i;
6116	pData[idxCap][1] = val;
6117	idxCap++;
6118	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6119	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6120	else
6121	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6122	&g_apszVmSvgaDevCapNames[i][1]));
6123	}
6124	else
6125	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6126	}
6127	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6128	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6129
6130	/* Mark end of record array. */
6131	pCaps->header.length = 0;
6132
6133	RTLogRelSetBuffering(fSavedBuffering);
6134	}
6135
6136	# endif
6137
6138	/**
6139	* Resets the SVGA hardware state
6140	*
6141	* @returns VBox status code.
6142	* @param pDevIns The device instance.
6143	*/
6144	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6145	{
6146	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6147	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6148	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6149
6150	/* Reset before init? */
6151	if (!pSVGAState)
6152	return VINF_SUCCESS;
6153
6154	Log(("vmsvgaR3Reset\n"));
6155
6156	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6157	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6158	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6159
6160	/* Reset other stuff. */
6161	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6162	RT_ZERO(pThis->svga.au32ScratchRegion);
6163
6164	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6165	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6166
6167	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6168
6169	/* Initialize FIFO and register capabilities. */
6170	vmsvgaR3InitCaps(pThis, pThisCC);
6171
6172	# ifdef VBOX_WITH_VMSVGA3D
6173	if (pThis->svga.f3DEnabled)
6174	vmsvgaR3InitFifo3DCaps(pThisCC);
6175	# endif
6176
6177	/* VRAM tracking is enabled by default during bootup. */
6178	pThis->svga.fVRAMTracking = true;
6179	pThis->svga.fEnabled = false;
6180
6181	/* Invalidate current settings. */
6182	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6183	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6184	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6185	pThis->svga.cbScanline = 0;
6186	pThis->svga.u32PitchLock = 0;
6187
6188	return rc;
6189	}
6190
6191	/**
6192	* Cleans up the SVGA hardware state
6193	*
6194	* @returns VBox status code.
6195	* @param pDevIns The device instance.
6196	*/
6197	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6198	{
6199	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6200	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6201
6202	/*
6203	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6204	*/
6205	if (pThisCC->svga.pFIFOIOThread)
6206	{
6207	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6208	NULL /pvParam/, 30000 /ms/);
6209	AssertLogRelRC(rc);
6210
6211	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6212	AssertLogRelRC(rc);
6213	pThisCC->svga.pFIFOIOThread = NULL;
6214	}
6215
6216	/*
6217	* Destroy the special SVGA state.
6218	*/
6219	if (pThisCC->svga.pSvgaR3State)
6220	{
6221	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6222
6223	RTMemFree(pThisCC->svga.pSvgaR3State);
6224	pThisCC->svga.pSvgaR3State = NULL;
6225	}
6226
6227	/*
6228	* Free our resources residing in the VGA state.
6229	*/
6230	if (pThisCC->svga.pbVgaFrameBufferR3)
6231	{
6232	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6233	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6234	}
6235	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6236	{
6237	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6238	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6239	}
6240	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6241	{
6242	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6243	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6244	}
6245
6246	return VINF_SUCCESS;
6247	}
6248
6249	/**
6250	* Initialize the SVGA hardware state
6251	*
6252	* @returns VBox status code.
6253	* @param pDevIns The device instance.
6254	*/
6255	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6256	{
6257	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6258	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6259	PVMSVGAR3STATE pSVGAState;
6260	int rc;
6261
6262	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6263	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6264
6265	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6266
6267	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6268	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6269	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6270
6271	/* Create event semaphore. */
6272	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6273	AssertRCReturn(rc, rc);
6274
6275	/* Create event semaphore. */
6276	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6277	AssertRCReturn(rc, rc);
6278
6279	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6280	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6281
6282	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6283	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6284
6285	pSVGAState = pThisCC->svga.pSvgaR3State;
6286
6287	/* Initialize FIFO and register capabilities. */
6288	vmsvgaR3InitCaps(pThis, pThisCC);
6289
6290	# ifdef VBOX_WITH_VMSVGA3D
6291	if (pThis->svga.f3DEnabled)
6292	{
6293	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6294	if (RT_FAILURE(rc))
6295	{
6296	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6297	pThis->svga.f3DEnabled = false;
6298	}
6299	}
6300	# endif
6301	/* VRAM tracking is enabled by default during bootup. */
6302	pThis->svga.fVRAMTracking = true;
6303
6304	/* Invalidate current settings. */
6305	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6306	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6307	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6308	pThis->svga.cbScanline = 0;
6309
6310	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6311	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6312	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6313	{
6314	pThis->svga.u32MaxWidth -= 256;
6315	pThis->svga.u32MaxHeight -= 256;
6316	}
6317	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6318
6319	# ifdef DEBUG_GMR_ACCESS
6320	/* Register the GMR access handler type. */
6321	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6322	vmsvgaR3GmrAccessHandler,
6323	NULL, NULL, NULL,
6324	NULL, NULL, NULL,
6325	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6326	AssertRCReturn(rc, rc);
6327	# endif
6328
6329	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6330	/* Register the FIFO access handler type. In addition to
6331	debugging FIFO access, this is also used to facilitate
6332	extended fifo thread sleeps. */
6333	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6334	# ifdef DEBUG_FIFO_ACCESS
6335	PGMPHYSHANDLERKIND_ALL,
6336	# else
6337	PGMPHYSHANDLERKIND_WRITE,
6338	# endif
6339	vmsvgaR3FifoAccessHandler,
6340	NULL, NULL, NULL,
6341	NULL, NULL, NULL,
6342	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6343	AssertRCReturn(rc, rc);
6344	# endif
6345
6346	/* Create the async IO thread. */
6347	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6348	RTTHREADTYPE_IO, "VMSVGA FIFO");
6349	if (RT_FAILURE(rc))
6350	{
6351	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6352	return rc;
6353	}
6354
6355	/*
6356	* Statistics.
6357	*/
6358	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6359	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6360	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6361	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6362	# ifdef VBOX_WITH_STATISTICS
6363	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6364	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6365	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6366	# endif
6367	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6368	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6369	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6370	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6371	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6372	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6373	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6374	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6375	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6376	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6377	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6378	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6379	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6380	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6381	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6382	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6383	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6384	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6385	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6386	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6387	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6388	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6389	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6390	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6391	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6392	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6393	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6394	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6395	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6396	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6397	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6398	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6399	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6400	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6401	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6402	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6403	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6404	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6405	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6406	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6407	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6408	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6409	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6410	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6411	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6412	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6413	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6414	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6415	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6416	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6417	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6418	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6419	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6420	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6421
6422	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6423	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6424	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6425	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6426	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6427	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6428	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6429	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6430	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6431	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6432	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6433	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6434	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6435	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6436	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6437	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6438	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6439	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6440	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6441	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6442	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6443	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6444	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6445	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6446	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6447	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6448	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6449	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6450	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6451	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6452	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6453	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6454
6455	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6456	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6457	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6458	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6459	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6460	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6461	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6462	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6463	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6464	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6465	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6466	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6467	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6468	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6469	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6470	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6471	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6472	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6473	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6474	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6475	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6476	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6477	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6478	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6479	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6480	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6481	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6482	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6483	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6484	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6485	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6486	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6487	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6488	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6489	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6490	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6491	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6492	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6493	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6494	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6495	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6496	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6497	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6498	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6499	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6500	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6501	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6502	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6503	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6504
6505	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6506	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6507	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6508	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6509	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6510	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6511	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6512	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6513	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6514	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6515	# endif
6516	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6517	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6518	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6519	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6520	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6521
6522	# undef REG_CNT
6523	# undef REG_PRF
6524
6525	/*
6526	* Info handlers.
6527	*/
6528	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6529	# ifdef VBOX_WITH_VMSVGA3D
6530	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6531	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6532	"VMSVGA 3d surface details. "
6533	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6534	vmsvgaR3Info3dSurface);
6535	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6536	"VMSVGA 3d surface details and bitmap: "
6537	"sid[>dir]",
6538	vmsvgaR3Info3dSurfaceBmp);
6539	# endif
6540
6541	return VINF_SUCCESS;
6542	}
6543
6544	/**
6545	* Power On notification.
6546	*
6547	* @returns VBox status code.
6548	* @param pDevIns The device instance data.
6549	*
6550	* @remarks Caller enters the device critical section.
6551	*/
6552	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6553	{
6554	# ifdef VBOX_WITH_VMSVGA3D
6555	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6556	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6557	if (pThis->svga.f3DEnabled)
6558	{
6559	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6560
6561	if (RT_SUCCESS(rc))
6562	{
6563	/* Initialize FIFO 3D capabilities. */
6564	vmsvgaR3InitFifo3DCaps(pThisCC);
6565	}
6566	}
6567	# else /* !VBOX_WITH_VMSVGA3D */
6568	RT_NOREF(pDevIns);
6569	# endif /* !VBOX_WITH_VMSVGA3D */
6570	}
6571
6572	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 83142

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