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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82409

Last change on this file since 82409 was 82409, checked in by vboxsync, 4 years ago
Devices/Graphics: optional release logging
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 293.6 KB

Line
1	/* $Id: DevVGA-SVGA.cpp 82409 2019-12-05 11:43:34Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2019 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdEscape;
271	STAMCOUNTER StatR3CmdDefineScreen;
272	STAMCOUNTER StatR3CmdDestroyScreen;
273	STAMCOUNTER StatR3CmdDefineGmrFb;
274	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
275	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
276	STAMCOUNTER StatR3CmdAnnotationFill;
277	STAMCOUNTER StatR3CmdAnnotationCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
279	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
280	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
281	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
282	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
283	STAMCOUNTER StatR3Cmd3dSurfaceDma;
284	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
285	STAMCOUNTER StatR3Cmd3dContextDefine;
286	STAMCOUNTER StatR3Cmd3dContextDestroy;
287	STAMCOUNTER StatR3Cmd3dSetTransform;
288	STAMCOUNTER StatR3Cmd3dSetZRange;
289	STAMCOUNTER StatR3Cmd3dSetRenderState;
290	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
291	STAMCOUNTER StatR3Cmd3dSetTextureState;
292	STAMCOUNTER StatR3Cmd3dSetMaterial;
293	STAMCOUNTER StatR3Cmd3dSetLightData;
294	STAMCOUNTER StatR3Cmd3dSetLightEnable;
295	STAMCOUNTER StatR3Cmd3dSetViewPort;
296	STAMCOUNTER StatR3Cmd3dSetClipPlane;
297	STAMCOUNTER StatR3Cmd3dClear;
298	STAMCOUNTER StatR3Cmd3dPresent;
299	STAMCOUNTER StatR3Cmd3dPresentReadBack;
300	STAMCOUNTER StatR3Cmd3dShaderDefine;
301	STAMCOUNTER StatR3Cmd3dShaderDestroy;
302	STAMCOUNTER StatR3Cmd3dSetShader;
303	STAMCOUNTER StatR3Cmd3dSetShaderConst;
304	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
305	STAMCOUNTER StatR3Cmd3dSetScissorRect;
306	STAMCOUNTER StatR3Cmd3dBeginQuery;
307	STAMCOUNTER StatR3Cmd3dEndQuery;
308	STAMCOUNTER StatR3Cmd3dWaitForQuery;
309	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
310	STAMCOUNTER StatR3Cmd3dActivateSurface;
311	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
312
313	STAMCOUNTER StatR3RegConfigDoneWr;
314	STAMCOUNTER StatR3RegGmrDescriptorWr;
315	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
316	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
317
318	STAMCOUNTER StatFifoCommands;
319	STAMCOUNTER StatFifoErrors;
320	STAMCOUNTER StatFifoUnkCmds;
321	STAMCOUNTER StatFifoTodoTimeout;
322	STAMCOUNTER StatFifoTodoWoken;
323	STAMPROFILE StatFifoStalls;
324	STAMPROFILE StatFifoExtendedSleep;
325	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
326	STAMCOUNTER StatFifoAccessHandler;
327	# endif
328	STAMCOUNTER StatFifoCursorFetchAgain;
329	STAMCOUNTER StatFifoCursorNoChange;
330	STAMCOUNTER StatFifoCursorPosition;
331	STAMCOUNTER StatFifoCursorVisiblity;
332	STAMCOUNTER StatFifoWatchdogWakeUps;
333	} VMSVGAR3STATE, *PVMSVGAR3STATE;
334	#endif /* IN_RING3 */
335
336
337	/*********************************************************************************************************************************
338	* Internal Functions *
339	*********************************************************************************************************************************/
340	#ifdef IN_RING3
341	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
342	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
343	# endif
344	# ifdef DEBUG_GMR_ACCESS
345	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
346	# endif
347	#endif
348
349
350	/*********************************************************************************************************************************
351	* Global Variables *
352	*********************************************************************************************************************************/
353	#ifdef IN_RING3
354
355	/**
356	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
357	*/
358	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
359	{
360	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
361	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
362	SSMFIELD_ENTRY_TERM()
363	};
364
365	/**
366	* SSM descriptor table for the GMR structure.
367	*/
368	static SSMFIELD const g_aGMRFields[] =
369	{
370	SSMFIELD_ENTRY( GMR, cMaxPages),
371	SSMFIELD_ENTRY( GMR, cbTotal),
372	SSMFIELD_ENTRY( GMR, numDescriptors),
373	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
374	SSMFIELD_ENTRY_TERM()
375	};
376
377	/**
378	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
379	*/
380	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
381	{
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
393	SSMFIELD_ENTRY_TERM()
394	};
395
396	/**
397	* SSM descriptor table for the VMSVGAR3STATE structure.
398	*/
399	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
400	{
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
409	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
412	#ifdef VMSVGA_USE_EMT_HALT_CODE
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
414	#else
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
416	#endif
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
480
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
488	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
490	# endif
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
495
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	/**
500	* SSM descriptor table for the VGAState.svga structure.
501	*/
502	static SSMFIELD const g_aVGAStateSVGAFields[] =
503	{
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
524	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
525	SSMFIELD_ENTRY( VMSVGAState, uWidth),
526	SSMFIELD_ENTRY( VMSVGAState, uHeight),
527	SSMFIELD_ENTRY( VMSVGAState, uBpp),
528	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
529	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
530	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
531	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
532	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
533	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
534	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
535	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
536	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
537	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
538	SSMFIELD_ENTRY_TERM()
539	};
540	#endif /* IN_RING3 */
541
542
543	/*********************************************************************************************************************************
544	* Internal Functions *
545	*********************************************************************************************************************************/
546	#ifdef IN_RING3
547	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
548	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
549	uint32_t uVersion, uint32_t uPass);
550	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
551	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
552	#endif /* IN_RING3 */
553
554
555
556	#ifdef IN_RING3
557	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
558	{
559	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
560	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
561	&& pSVGAState
562	&& pSVGAState->aScreens[idScreen].fDefined)
563	{
564	return &pSVGAState->aScreens[idScreen];
565	}
566	return NULL;
567	}
568	#endif /* IN_RING3 */
569
570	#ifdef LOG_ENABLED
571
572	/**
573	* Index register string name lookup
574	*
575	* @returns Index register string or "UNKNOWN"
576	* @param pThis The shared VGA/VMSVGA state.
577	* @param idxReg The index register.
578	*/
579	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
580	{
581	switch (idxReg)
582	{
583	case SVGA_REG_ID: return "SVGA_REG_ID";
584	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
585	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
586	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
587	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
588	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
589	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
590	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
591	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
592	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
593	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
594	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
595	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
596	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
597	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
598	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
599	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
600	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
601	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
602	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
603	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
604	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
605	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
606	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
607	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
608	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
609	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
610	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
611	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
612	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
613	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
614	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
615	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
616	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
617	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
618	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
619	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
620	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
621	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
622	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
623	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
624	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
625	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
626	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
627	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
628	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
629	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
630	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
631	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
632	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
633
634	default:
635	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
636	return "SVGA_SCRATCH_BASE reg";
637	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
638	return "SVGA_PALETTE_BASE reg";
639	return "UNKNOWN";
640	}
641	}
642
643	#ifdef IN_RING3
644	/**
645	* FIFO command name lookup
646	*
647	* @returns FIFO command string or "UNKNOWN"
648	* @param u32Cmd FIFO command
649	*/
650	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
651	{
652	switch (u32Cmd)
653	{
654	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
655	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
656	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
657	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
658	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
659	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
660	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
661	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
662	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
663	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
664	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
665	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
666	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
667	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
668	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
669	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
670	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
671	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
672	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
673	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
674	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
675	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
676	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
677	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
678	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
679	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
680	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
681	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
682	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
683	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
684	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
685	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
686	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
687	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
688	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
689	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
690	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
691	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
692	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
693	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
694	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
695	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
696	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
697	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
698	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
699	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
700	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
701	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
702	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
703	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
704	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
705	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
706	default: return "UNKNOWN";
707	}
708	}
709	# endif /* IN_RING3 */
710
711	#endif /* LOG_ENABLED */
712
713	#ifdef IN_RING3
714	/**
715	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
716	*/
717	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
718	{
719	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
720	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
721
722	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
723	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
724
725	/** @todo Test how it interacts with multiple screen objects. */
726	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
727	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
728	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
729
730	if (x < uWidth)
731	{
732	pThis->svga.viewport.x = x;
733	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
734	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
735	}
736	else
737	{
738	pThis->svga.viewport.x = uWidth;
739	pThis->svga.viewport.cx = 0;
740	pThis->svga.viewport.xRight = uWidth;
741	}
742	if (y < uHeight)
743	{
744	pThis->svga.viewport.y = y;
745	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
746	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
747	pThis->svga.viewport.yHighWC = uHeight - y;
748	}
749	else
750	{
751	pThis->svga.viewport.y = uHeight;
752	pThis->svga.viewport.cy = 0;
753	pThis->svga.viewport.yLowWC = 0;
754	pThis->svga.viewport.yHighWC = 0;
755	}
756
757	# ifdef VBOX_WITH_VMSVGA3D
758	/*
759	* Now inform the 3D backend.
760	*/
761	if (pThis->svga.f3DEnabled)
762	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
763	# else
764	RT_NOREF(OldViewport);
765	# endif
766	}
767	#endif /* IN_RING3 */
768
769	/**
770	* Read port register
771	*
772	* @returns VBox status code.
773	* @param pDevIns The device instance.
774	* @param pThis The shared VGA/VMSVGA state.
775	* @param pu32 Where to store the read value
776	*/
777	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
778	{
779	#ifdef IN_RING3
780	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
781	#endif
782	int rc = VINF_SUCCESS;
783	*pu32 = 0;
784
785	/* Rough index register validation. */
786	uint32_t idxReg = pThis->svga.u32IndexReg;
787	#if !defined(IN_RING3) && defined(VBOX_STRICT)
788	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
789	VINF_IOM_R3_IOPORT_READ);
790	#else
791	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
792	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
793	VINF_SUCCESS);
794	#endif
795	RT_UNTRUSTED_VALIDATED_FENCE();
796
797	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
798	if ( idxReg >= SVGA_REG_CAPABILITIES
799	&& pThis->svga.u32SVGAId == SVGA_ID_0)
800	{
801	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
802	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
803	}
804
805	switch (idxReg)
806	{
807	case SVGA_REG_ID:
808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
809	*pu32 = pThis->svga.u32SVGAId;
810	break;
811
812	case SVGA_REG_ENABLE:
813	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
814	*pu32 = pThis->svga.fEnabled;
815	break;
816
817	case SVGA_REG_WIDTH:
818	{
819	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
820	if ( pThis->svga.fEnabled
821	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
822	*pu32 = pThis->svga.uWidth;
823	else
824	{
825	#ifndef IN_RING3
826	rc = VINF_IOM_R3_IOPORT_READ;
827	#else
828	*pu32 = pThisCC->pDrv->cx;
829	#endif
830	}
831	break;
832	}
833
834	case SVGA_REG_HEIGHT:
835	{
836	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
837	if ( pThis->svga.fEnabled
838	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
839	*pu32 = pThis->svga.uHeight;
840	else
841	{
842	#ifndef IN_RING3
843	rc = VINF_IOM_R3_IOPORT_READ;
844	#else
845	*pu32 = pThisCC->pDrv->cy;
846	#endif
847	}
848	break;
849	}
850
851	case SVGA_REG_MAX_WIDTH:
852	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
853	*pu32 = pThis->svga.u32MaxWidth;
854	break;
855
856	case SVGA_REG_MAX_HEIGHT:
857	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
858	*pu32 = pThis->svga.u32MaxHeight;
859	break;
860
861	case SVGA_REG_DEPTH:
862	/* This returns the color depth of the current mode. */
863	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
864	switch (pThis->svga.uBpp)
865	{
866	case 15:
867	case 16:
868	case 24:
869	*pu32 = pThis->svga.uBpp;
870	break;
871
872	default:
873	case 32:
874	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
875	break;
876	}
877	break;
878
879	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
880	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
881	if ( pThis->svga.fEnabled
882	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
883	*pu32 = pThis->svga.uBpp;
884	else
885	{
886	#ifndef IN_RING3
887	rc = VINF_IOM_R3_IOPORT_READ;
888	#else
889	*pu32 = pThisCC->pDrv->cBits;
890	#endif
891	}
892	break;
893
894	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
895	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
896	if ( pThis->svga.fEnabled
897	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
898	*pu32 = (pThis->svga.uBpp + 7) & ~7;
899	else
900	{
901	#ifndef IN_RING3
902	rc = VINF_IOM_R3_IOPORT_READ;
903	#else
904	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
905	#endif
906	}
907	break;
908
909	case SVGA_REG_PSEUDOCOLOR:
910	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
911	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
912	break;
913
914	case SVGA_REG_RED_MASK:
915	case SVGA_REG_GREEN_MASK:
916	case SVGA_REG_BLUE_MASK:
917	{
918	uint32_t uBpp;
919
920	if ( pThis->svga.fEnabled
921	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
922	{
923	uBpp = pThis->svga.uBpp;
924	}
925	else
926	{
927	#ifndef IN_RING3
928	rc = VINF_IOM_R3_IOPORT_READ;
929	break;
930	#else
931	uBpp = pThisCC->pDrv->cBits;
932	#endif
933	}
934	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
935	switch (uBpp)
936	{
937	case 8:
938	u32RedMask = 0x07;
939	u32GreenMask = 0x38;
940	u32BlueMask = 0xc0;
941	break;
942
943	case 15:
944	u32RedMask = 0x0000001f;
945	u32GreenMask = 0x000003e0;
946	u32BlueMask = 0x00007c00;
947	break;
948
949	case 16:
950	u32RedMask = 0x0000001f;
951	u32GreenMask = 0x000007e0;
952	u32BlueMask = 0x0000f800;
953	break;
954
955	case 24:
956	case 32:
957	default:
958	u32RedMask = 0x00ff0000;
959	u32GreenMask = 0x0000ff00;
960	u32BlueMask = 0x000000ff;
961	break;
962	}
963	switch (idxReg)
964	{
965	case SVGA_REG_RED_MASK:
966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
967	*pu32 = u32RedMask;
968	break;
969
970	case SVGA_REG_GREEN_MASK:
971	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
972	*pu32 = u32GreenMask;
973	break;
974
975	case SVGA_REG_BLUE_MASK:
976	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
977	*pu32 = u32BlueMask;
978	break;
979	}
980	break;
981	}
982
983	case SVGA_REG_BYTES_PER_LINE:
984	{
985	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
986	if ( pThis->svga.fEnabled
987	&& pThis->svga.cbScanline)
988	*pu32 = pThis->svga.cbScanline;
989	else
990	{
991	#ifndef IN_RING3
992	rc = VINF_IOM_R3_IOPORT_READ;
993	#else
994	*pu32 = pThisCC->pDrv->cbScanline;
995	#endif
996	}
997	break;
998	}
999
1000	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1002	*pu32 = pThis->vram_size;
1003	break;
1004
1005	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1007	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1008	*pu32 = pThis->GCPhysVRAM;
1009	break;
1010
1011	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1013	/* Always zero in our case. */
1014	*pu32 = 0;
1015	break;
1016
1017	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1018	{
1019	#ifndef IN_RING3
1020	rc = VINF_IOM_R3_IOPORT_READ;
1021	#else
1022	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1023
1024	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1025	if ( pThis->svga.fEnabled
1026	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1027	{
1028	/* Hardware enabled; return real framebuffer size .*/
1029	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1030	}
1031	else
1032	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1033
1034	pu32 = RT_MIN(pThis->vram_size, pu32);
1035	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1036	#endif
1037	break;
1038	}
1039
1040	case SVGA_REG_CAPABILITIES:
1041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1042	*pu32 = pThis->svga.u32RegCaps;
1043	break;
1044
1045	case SVGA_REG_MEM_START: /* FIFO start */
1046	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1047	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1048	*pu32 = pThis->svga.GCPhysFIFO;
1049	break;
1050
1051	case SVGA_REG_MEM_SIZE: /* FIFO size */
1052	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1053	*pu32 = pThis->svga.cbFIFO;
1054	break;
1055
1056	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1057	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1058	*pu32 = pThis->svga.fConfigured;
1059	break;
1060
1061	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1063	*pu32 = 0;
1064	break;
1065
1066	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1067	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1068	if (pThis->svga.fBusy)
1069	{
1070	#ifndef IN_RING3
1071	/* Go to ring-3 and halt the CPU. */
1072	rc = VINF_IOM_R3_IOPORT_READ;
1073	RT_NOREF(pDevIns);
1074	break;
1075	#else
1076	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1077	/* The guest is basically doing a HLT via the device here, but with
1078	a special wake up condition on FIFO completion. */
1079	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1080	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1081	PVM pVM = PDMDevHlpGetVM(pDevIns);
1082	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1083	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1084	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1085	if (pThis->svga.fBusy)
1086	{
1087	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1088	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1089	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1090	}
1091	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1092	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1093	# else
1094
1095	/* Delay the EMT a bit so the FIFO and others can get some work done.
1096	This used to be a crude 50 ms sleep. The current code tries to be
1097	more efficient, but the consept is still very crude. */
1098	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1099	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1100	RTThreadYield();
1101	if (pThis->svga.fBusy)
1102	{
1103	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1104
1105	if (pThis->svga.fBusy && cRefs == 1)
1106	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1107	if (pThis->svga.fBusy)
1108	{
1109	/** @todo If this code is going to stay, we need to call into the halt/wait
1110	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1111	* suffer when the guest is polling on a busy FIFO. */
1112	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1113	if (cNsMaxWait >= RT_NS_100US)
1114	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1115	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1116	RT_MIN(cNsMaxWait, RT_NS_10MS));
1117	}
1118
1119	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1120	}
1121	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1122	# endif
1123	*pu32 = pThis->svga.fBusy != 0;
1124	#endif
1125	}
1126	else
1127	*pu32 = false;
1128	break;
1129
1130	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1131	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1132	*pu32 = pThis->svga.u32GuestId;
1133	break;
1134
1135	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1136	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1137	*pu32 = pThis->svga.cScratchRegion;
1138	break;
1139
1140	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1142	*pu32 = SVGA_FIFO_NUM_REGS;
1143	break;
1144
1145	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1146	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1147	*pu32 = pThis->svga.u32PitchLock;
1148	break;
1149
1150	case SVGA_REG_IRQMASK: /* Interrupt mask */
1151	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1152	*pu32 = pThis->svga.u32IrqMask;
1153	break;
1154
1155	/* See "Guest memory regions" below. */
1156	case SVGA_REG_GMR_ID:
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1158	*pu32 = pThis->svga.u32CurrentGMRId;
1159	break;
1160
1161	case SVGA_REG_GMR_DESCRIPTOR:
1162	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1163	/* Write only */
1164	*pu32 = 0;
1165	break;
1166
1167	case SVGA_REG_GMR_MAX_IDS:
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1169	*pu32 = pThis->svga.cGMR;
1170	break;
1171
1172	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1174	*pu32 = VMSVGA_MAX_GMR_PAGES;
1175	break;
1176
1177	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1179	*pu32 = pThis->svga.fTraces;
1180	break;
1181
1182	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1183	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1184	*pu32 = VMSVGA_MAX_GMR_PAGES;
1185	break;
1186
1187	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1189	*pu32 = VMSVGA_SURFACE_SIZE;
1190	break;
1191
1192	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1194	break;
1195
1196	/* Mouse cursor support. */
1197	case SVGA_REG_CURSOR_ID:
1198	case SVGA_REG_CURSOR_X:
1199	case SVGA_REG_CURSOR_Y:
1200	case SVGA_REG_CURSOR_ON:
1201	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1202	break;
1203
1204	/* Legacy multi-monitor support */
1205	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1207	*pu32 = 1;
1208	break;
1209
1210	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1211	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1212	*pu32 = 0;
1213	break;
1214
1215	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1216	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1217	*pu32 = 0;
1218	break;
1219
1220	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1221	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1222	*pu32 = 0;
1223	break;
1224
1225	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1226	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1227	*pu32 = 0;
1228	break;
1229
1230	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1231	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1232	*pu32 = pThis->svga.uWidth;
1233	break;
1234
1235	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1236	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1237	*pu32 = pThis->svga.uHeight;
1238	break;
1239
1240	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1241	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1242	/* We must return something sensible here otherwise the Linux driver
1243	will take a legacy code path without 3d support. This number also
1244	limits how many screens Linux guests will allow. */
1245	*pu32 = pThis->cMonitors;
1246	break;
1247
1248	default:
1249	{
1250	uint32_t offReg;
1251	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1252	{
1253	RT_UNTRUSTED_VALIDATED_FENCE();
1254	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1255	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1256	}
1257	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1258	{
1259	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1260	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1261	RT_UNTRUSTED_VALIDATED_FENCE();
1262	uint32_t u32 = pThis->last_palette[offReg / 3];
1263	switch (offReg % 3)
1264	{
1265	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1266	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1267	case 2: pu32 = u32 & 0xff; break; / blue */
1268	}
1269	}
1270	else
1271	{
1272	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1273	rc = VINF_IOM_R3_IOPORT_READ;
1274	#else
1275	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1276
1277	/* Do not assert. The guest might be reading all registers. */
1278	LogFunc(("Unknown reg=%#x\n", idxReg));
1279	#endif
1280	}
1281	break;
1282	}
1283	}
1284	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1285	return rc;
1286	}
1287
1288	#ifdef IN_RING3
1289	/**
1290	* Apply the current resolution settings to change the video mode.
1291	*
1292	* @returns VBox status code.
1293	* @param pThis The shared VGA state.
1294	* @param pThisCC The ring-3 VGA state.
1295	*/
1296	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1297	{
1298	int rc;
1299
1300	/* Always do changemode on FIFO thread. */
1301	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1302
1303	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1304
1305	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1306
1307	if (pThis->svga.fGFBRegisters)
1308	{
1309	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1310	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1311	* deletes all screens other than screen #0, and redefines screen
1312	* #0 according to the specified mode. Drivers that use
1313	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1314	*/
1315
1316	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1317	pScreen->fDefined = true;
1318	pScreen->fModified = true;
1319	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1320	pScreen->idScreen = 0;
1321	pScreen->xOrigin = 0;
1322	pScreen->yOrigin = 0;
1323	pScreen->offVRAM = 0;
1324	pScreen->cbPitch = pThis->svga.cbScanline;
1325	pScreen->cWidth = pThis->svga.uWidth;
1326	pScreen->cHeight = pThis->svga.uHeight;
1327	pScreen->cBpp = pThis->svga.uBpp;
1328
1329	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1330	{
1331	/* Delete screen. */
1332	pScreen = &pSVGAState->aScreens[iScreen];
1333	if (pScreen->fDefined)
1334	{
1335	pScreen->fModified = true;
1336	pScreen->fDefined = false;
1337	}
1338	}
1339	}
1340	else
1341	{
1342	/* "If Screen Objects are supported, they can be used to fully
1343	* replace the functionality provided by the framebuffer registers
1344	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1345	*/
1346	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1347	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1348	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1349	}
1350
1351	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1352	{
1353	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1354	if (!pScreen->fModified)
1355	continue;
1356
1357	pScreen->fModified = false;
1358
1359	VBVAINFOVIEW view;
1360	RT_ZERO(view);
1361	view.u32ViewIndex = pScreen->idScreen;
1362	// view.u32ViewOffset = 0;
1363	view.u32ViewSize = pThis->vram_size;
1364	view.u32MaxScreenSize = pThis->vram_size;
1365
1366	VBVAINFOSCREEN screen;
1367	RT_ZERO(screen);
1368	screen.u32ViewIndex = pScreen->idScreen;
1369
1370	if (pScreen->fDefined)
1371	{
1372	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1373	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1374	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1375	{
1376	Assert(pThis->svga.fGFBRegisters);
1377	continue;
1378	}
1379
1380	screen.i32OriginX = pScreen->xOrigin;
1381	screen.i32OriginY = pScreen->yOrigin;
1382	screen.u32StartOffset = pScreen->offVRAM;
1383	screen.u32LineSize = pScreen->cbPitch;
1384	screen.u32Width = pScreen->cWidth;
1385	screen.u32Height = pScreen->cHeight;
1386	screen.u16BitsPerPixel = pScreen->cBpp;
1387	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1388	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1389	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1390	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1391	}
1392	else
1393	{
1394	/* Screen is destroyed. */
1395	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1396	}
1397
1398	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1399	AssertRC(rc);
1400	}
1401
1402	/* Last stuff. For the VGA device screenshot. */
1403	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1404	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1405	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1406	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1407	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1408
1409	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1410	if ( pThis->svga.viewport.cx == 0
1411	&& pThis->svga.viewport.cy == 0)
1412	{
1413	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1414	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1415	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1416	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1417	pThis->svga.viewport.yLowWC = 0;
1418	}
1419
1420	return VINF_SUCCESS;
1421	}
1422
1423	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1424	{
1425	VBVACMDHDR cmd;
1426	cmd.x = (int16_t)(pScreen->xOrigin + x);
1427	cmd.y = (int16_t)(pScreen->yOrigin + y);
1428	cmd.w = (uint16_t)w;
1429	cmd.h = (uint16_t)h;
1430
1431	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1432	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1433	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1434	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1435
1436	return VINF_SUCCESS;
1437	}
1438
1439	#endif /* IN_RING3 */
1440	#if defined(IN_RING0) \|\| defined(IN_RING3)
1441
1442	/**
1443	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1444	*
1445	* @param pThis The shared VGA/VMSVGA instance data.
1446	* @param pThisCC The VGA/VMSVGA state for the current context.
1447	* @param fState The busy state.
1448	*/
1449	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1450	{
1451	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1452
1453	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1454	{
1455	/* Race / unfortunately scheduling. Highly unlikly. */
1456	uint32_t cLoops = 64;
1457	do
1458	{
1459	ASMNopPause();
1460	fState = (pThis->svga.fBusy != 0);
1461	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1462	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1463	}
1464	}
1465
1466
1467	/**
1468	* Update the scanline pitch in response to the guest changing mode
1469	* width/bpp.
1470	*
1471	* @param pThis The shared VGA/VMSVGA state.
1472	* @param pThisCC The VGA/VMSVGA state for the current context.
1473	*/
1474	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1475	{
1476	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1477	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1478	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1479	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1480
1481	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1482	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1483	* location but it has a different meaning.
1484	*/
1485	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1486	uFifoPitchLock = 0;
1487
1488	/* Sanitize values. */
1489	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1490	uFifoPitchLock = 0;
1491	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1492	uRegPitchLock = 0;
1493
1494	/* Prefer the register value to the FIFO value.*/
1495	if (uRegPitchLock)
1496	pThis->svga.cbScanline = uRegPitchLock;
1497	else if (uFifoPitchLock)
1498	pThis->svga.cbScanline = uFifoPitchLock;
1499	else
1500	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1501
1502	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1503	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1504	}
1505
1506	#endif /* IN_RING0 \|\| IN_RING3 */
1507
1508
1509	/**
1510	* Write port register
1511	*
1512	* @returns Strict VBox status code.
1513	* @param pDevIns The device instance.
1514	* @param pThis The shared VGA/VMSVGA state.
1515	* @param pThisCC The VGA/VMSVGA state for the current context.
1516	* @param u32 Value to write
1517	*/
1518	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1519	{
1520	#ifdef IN_RING3
1521	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1522	#endif
1523	VBOXSTRICTRC rc = VINF_SUCCESS;
1524	RT_NOREF(pThisCC);
1525
1526	/* Rough index register validation. */
1527	uint32_t idxReg = pThis->svga.u32IndexReg;
1528	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1529	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1530	VINF_IOM_R3_IOPORT_WRITE);
1531	#else
1532	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1533	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1534	VINF_SUCCESS);
1535	#endif
1536	RT_UNTRUSTED_VALIDATED_FENCE();
1537
1538	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1539	if ( idxReg >= SVGA_REG_CAPABILITIES
1540	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1541	{
1542	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1543	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1544	}
1545	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1546	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1547	switch (idxReg)
1548	{
1549	case SVGA_REG_WIDTH:
1550	case SVGA_REG_HEIGHT:
1551	case SVGA_REG_PITCHLOCK:
1552	case SVGA_REG_BITS_PER_PIXEL:
1553	pThis->svga.fGFBRegisters = true;
1554	break;
1555	default:
1556	break;
1557	}
1558
1559	switch (idxReg)
1560	{
1561	case SVGA_REG_ID:
1562	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1563	if ( u32 == SVGA_ID_0
1564	\|\| u32 == SVGA_ID_1
1565	\|\| u32 == SVGA_ID_2)
1566	pThis->svga.u32SVGAId = u32;
1567	else
1568	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1569	break;
1570
1571	case SVGA_REG_ENABLE:
1572	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1573	#ifdef IN_RING3
1574	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1575	&& pThis->svga.fEnabled == false)
1576	{
1577	/* Make a backup copy of the first 512kb in order to save font data etc. */
1578	/** @todo should probably swap here, rather than copy + zero */
1579	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1580	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1581	}
1582
1583	pThis->svga.fEnabled = u32;
1584	if (pThis->svga.fEnabled)
1585	{
1586	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1587	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1588	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1589	{
1590	/* Keep the current mode. */
1591	pThis->svga.uWidth = pThisCC->pDrv->cx;
1592	pThis->svga.uHeight = pThisCC->pDrv->cy;
1593	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1594	}
1595
1596	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1597	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1598	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1599	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1600	# ifdef LOG_ENABLED
1601	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1602	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1603	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1604	# endif
1605
1606	/* Disable or enable dirty page tracking according to the current fTraces value. */
1607	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1608
1609	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1610	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1611	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1612	}
1613	else
1614	{
1615	/* Restore the text mode backup. */
1616	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1617
1618	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1619
1620	/* Enable dirty page tracking again when going into legacy mode. */
1621	vmsvgaR3SetTraces(pDevIns, pThis, true);
1622
1623	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1624	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1625	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1626
1627	/* Clear the pitch lock. */
1628	pThis->svga.u32PitchLock = 0;
1629	}
1630	#else /* !IN_RING3 */
1631	rc = VINF_IOM_R3_IOPORT_WRITE;
1632	#endif /* !IN_RING3 */
1633	break;
1634
1635	case SVGA_REG_WIDTH:
1636	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1637	if (pThis->svga.uWidth != u32)
1638	{
1639	#if defined(IN_RING3) \|\| defined(IN_RING0)
1640	pThis->svga.uWidth = u32;
1641	vmsvgaHCUpdatePitch(pThis, pThisCC);
1642	if (pThis->svga.fEnabled)
1643	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1644	#else
1645	rc = VINF_IOM_R3_IOPORT_WRITE;
1646	#endif
1647	}
1648	/* else: nop */
1649	break;
1650
1651	case SVGA_REG_HEIGHT:
1652	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1653	if (pThis->svga.uHeight != u32)
1654	{
1655	pThis->svga.uHeight = u32;
1656	if (pThis->svga.fEnabled)
1657	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1658	}
1659	/* else: nop */
1660	break;
1661
1662	case SVGA_REG_DEPTH:
1663	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1664	/** @todo read-only?? */
1665	break;
1666
1667	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1668	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1669	if (pThis->svga.uBpp != u32)
1670	{
1671	#if defined(IN_RING3) \|\| defined(IN_RING0)
1672	pThis->svga.uBpp = u32;
1673	vmsvgaHCUpdatePitch(pThis, pThisCC);
1674	if (pThis->svga.fEnabled)
1675	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1676	#else
1677	rc = VINF_IOM_R3_IOPORT_WRITE;
1678	#endif
1679	}
1680	/* else: nop */
1681	break;
1682
1683	case SVGA_REG_PSEUDOCOLOR:
1684	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1685	break;
1686
1687	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1688	#ifdef IN_RING3
1689	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1690	pThis->svga.fConfigured = u32;
1691	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1692	if (!pThis->svga.fConfigured)
1693	pThis->svga.fTraces = true;
1694	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1695	#else
1696	rc = VINF_IOM_R3_IOPORT_WRITE;
1697	#endif
1698	break;
1699
1700	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1701	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1702	if ( pThis->svga.fEnabled
1703	&& pThis->svga.fConfigured)
1704	{
1705	#if defined(IN_RING3) \|\| defined(IN_RING0)
1706	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1707	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1708	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1709	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1710
1711	/* Kick the FIFO thread to start processing commands again. */
1712	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1713	#else
1714	rc = VINF_IOM_R3_IOPORT_WRITE;
1715	#endif
1716	}
1717	/* else nothing to do. */
1718	else
1719	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1720
1721	break;
1722
1723	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1724	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1725	break;
1726
1727	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1728	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1729	pThis->svga.u32GuestId = u32;
1730	break;
1731
1732	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1733	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1734	pThis->svga.u32PitchLock = u32;
1735	/* Should this also update the FIFO pitch lock? Unclear. */
1736	break;
1737
1738	case SVGA_REG_IRQMASK: /* Interrupt mask */
1739	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1740	pThis->svga.u32IrqMask = u32;
1741
1742	/* Irq pending after the above change? */
1743	if (pThis->svga.u32IrqStatus & u32)
1744	{
1745	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1746	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1747	}
1748	else
1749	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1750	break;
1751
1752	/* Mouse cursor support */
1753	case SVGA_REG_CURSOR_ID:
1754	case SVGA_REG_CURSOR_X:
1755	case SVGA_REG_CURSOR_Y:
1756	case SVGA_REG_CURSOR_ON:
1757	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1758	break;
1759
1760	/* Legacy multi-monitor support */
1761	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1762	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1763	break;
1764	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1765	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1766	break;
1767	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1768	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1769	break;
1770	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1771	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1772	break;
1773	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1774	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1775	break;
1776	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1777	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1778	break;
1779	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1781	break;
1782	#ifdef VBOX_WITH_VMSVGA3D
1783	/* See "Guest memory regions" below. */
1784	case SVGA_REG_GMR_ID:
1785	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1786	pThis->svga.u32CurrentGMRId = u32;
1787	break;
1788
1789	case SVGA_REG_GMR_DESCRIPTOR:
1790	# ifndef IN_RING3
1791	rc = VINF_IOM_R3_IOPORT_WRITE;
1792	break;
1793	# else /* IN_RING3 */
1794	{
1795	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1796
1797	/* Validate current GMR id. */
1798	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1799	AssertBreak(idGMR < pThis->svga.cGMR);
1800	RT_UNTRUSTED_VALIDATED_FENCE();
1801
1802	/* Free the old GMR if present. */
1803	vmsvgaR3GmrFree(pThisCC, idGMR);
1804
1805	/* Just undefine the GMR? */
1806	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1807	if (GCPhys == 0)
1808	{
1809	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1810	break;
1811	}
1812
1813
1814	/* Never cross a page boundary automatically. */
1815	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1816	uint32_t cPagesTotal = 0;
1817	uint32_t iDesc = 0;
1818	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1819	uint32_t cLoops = 0;
1820	RTGCPHYS GCPhysBase = GCPhys;
1821	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1822	{
1823	/* Read descriptor. */
1824	SVGAGuestMemDescriptor desc;
1825	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1826	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1827
1828	if (desc.numPages != 0)
1829	{
1830	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1831	cPagesTotal += desc.numPages;
1832	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1833
1834	if ((iDesc & 15) == 0)
1835	{
1836	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1837	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1838	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1839	}
1840
1841	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1842	paDescs[iDesc++].numPages = desc.numPages;
1843
1844	/* Continue with the next descriptor. */
1845	GCPhys += sizeof(desc);
1846	}
1847	else if (desc.ppn == 0)
1848	break; /* terminator */
1849	else /* Pointer to the next physical page of descriptors. */
1850	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1851
1852	cLoops++;
1853	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1854	}
1855
1856	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1857	if (RT_SUCCESS(rc))
1858	{
1859	/* Commit the GMR. */
1860	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1861	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1862	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1863	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1864	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1865	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1866	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1867	}
1868	else
1869	{
1870	RTMemFree(paDescs);
1871	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1872	}
1873	break;
1874	}
1875	# endif /* IN_RING3 */
1876	#endif // VBOX_WITH_VMSVGA3D
1877
1878	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1879	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1880	if (pThis->svga.fTraces == u32)
1881	break; /* nothing to do */
1882
1883	#ifdef IN_RING3
1884	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1885	#else
1886	rc = VINF_IOM_R3_IOPORT_WRITE;
1887	#endif
1888	break;
1889
1890	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1892	break;
1893
1894	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1895	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1896	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1897	break;
1898
1899	case SVGA_REG_FB_START:
1900	case SVGA_REG_MEM_START:
1901	case SVGA_REG_HOST_BITS_PER_PIXEL:
1902	case SVGA_REG_MAX_WIDTH:
1903	case SVGA_REG_MAX_HEIGHT:
1904	case SVGA_REG_VRAM_SIZE:
1905	case SVGA_REG_FB_SIZE:
1906	case SVGA_REG_CAPABILITIES:
1907	case SVGA_REG_MEM_SIZE:
1908	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1909	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1910	case SVGA_REG_BYTES_PER_LINE:
1911	case SVGA_REG_FB_OFFSET:
1912	case SVGA_REG_RED_MASK:
1913	case SVGA_REG_GREEN_MASK:
1914	case SVGA_REG_BLUE_MASK:
1915	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1916	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1917	case SVGA_REG_GMR_MAX_IDS:
1918	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1919	/* Read only - ignore. */
1920	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1921	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1922	break;
1923
1924	default:
1925	{
1926	uint32_t offReg;
1927	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1928	{
1929	RT_UNTRUSTED_VALIDATED_FENCE();
1930	pThis->svga.au32ScratchRegion[offReg] = u32;
1931	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1932	}
1933	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1934	{
1935	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1936	Btw, see rgb_to_pixel32. */
1937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1938	u32 &= 0xff;
1939	RT_UNTRUSTED_VALIDATED_FENCE();
1940	uint32_t uRgb = pThis->last_palette[offReg / 3];
1941	switch (offReg % 3)
1942	{
1943	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1944	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1945	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1946	}
1947	pThis->last_palette[offReg / 3] = uRgb;
1948	}
1949	else
1950	{
1951	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1952	rc = VINF_IOM_R3_IOPORT_WRITE;
1953	#else
1954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1955	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1956	#endif
1957	}
1958	break;
1959	}
1960	}
1961	return rc;
1962	}
1963
1964	/**
1965	* @callback_method_impl{FNIOMIOPORTNEWIN}
1966	*/
1967	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1968	{
1969	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
1970	RT_NOREF_PV(pvUser);
1971
1972	/* Only dword accesses. */
1973	if (cb == 4)
1974	{
1975	switch (offPort)
1976	{
1977	case SVGA_INDEX_PORT:
1978	*pu32 = pThis->svga.u32IndexReg;
1979	break;
1980
1981	case SVGA_VALUE_PORT:
1982	return vmsvgaReadPort(pDevIns, pThis, pu32);
1983
1984	case SVGA_BIOS_PORT:
1985	Log(("Ignoring BIOS port read\n"));
1986	*pu32 = 0;
1987	break;
1988
1989	case SVGA_IRQSTATUS_PORT:
1990	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1991	*pu32 = pThis->svga.u32IrqStatus;
1992	break;
1993
1994	default:
1995	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1996	*pu32 = UINT32_MAX;
1997	break;
1998	}
1999	}
2000	else
2001	{
2002	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2003	*pu32 = UINT32_MAX;
2004	}
2005	return VINF_SUCCESS;
2006	}
2007
2008	/**
2009	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2010	*/
2011	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2012	{
2013	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2014	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2015	RT_NOREF_PV(pvUser);
2016
2017	/* Only dword accesses. */
2018	if (cb == 4)
2019	switch (offPort)
2020	{
2021	case SVGA_INDEX_PORT:
2022	pThis->svga.u32IndexReg = u32;
2023	break;
2024
2025	case SVGA_VALUE_PORT:
2026	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2027
2028	case SVGA_BIOS_PORT:
2029	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2030	break;
2031
2032	case SVGA_IRQSTATUS_PORT:
2033	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2034	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2035	/* Clear the irq in case all events have been cleared. */
2036	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2037	{
2038	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2039	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2040	}
2041	break;
2042
2043	default:
2044	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2045	break;
2046	}
2047	else
2048	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2049
2050	return VINF_SUCCESS;
2051	}
2052
2053	#ifdef IN_RING3
2054
2055	# ifdef DEBUG_FIFO_ACCESS
2056	/**
2057	* Handle FIFO memory access.
2058	* @returns VBox status code.
2059	* @param pVM VM handle.
2060	* @param pThis The shared VGA/VMSVGA instance data.
2061	* @param GCPhys The access physical address.
2062	* @param fWriteAccess Read or write access
2063	*/
2064	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2065	{
2066	RT_NOREF(pVM);
2067	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2068	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2069
2070	switch (GCPhysOffset >> 2)
2071	{
2072	case SVGA_FIFO_MIN:
2073	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2074	break;
2075	case SVGA_FIFO_MAX:
2076	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2077	break;
2078	case SVGA_FIFO_NEXT_CMD:
2079	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2080	break;
2081	case SVGA_FIFO_STOP:
2082	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2083	break;
2084	case SVGA_FIFO_CAPABILITIES:
2085	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2086	break;
2087	case SVGA_FIFO_FLAGS:
2088	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2089	break;
2090	case SVGA_FIFO_FENCE:
2091	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2092	break;
2093	case SVGA_FIFO_3D_HWVERSION:
2094	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2095	break;
2096	case SVGA_FIFO_PITCHLOCK:
2097	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2098	break;
2099	case SVGA_FIFO_CURSOR_ON:
2100	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2101	break;
2102	case SVGA_FIFO_CURSOR_X:
2103	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2104	break;
2105	case SVGA_FIFO_CURSOR_Y:
2106	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2107	break;
2108	case SVGA_FIFO_CURSOR_COUNT:
2109	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2110	break;
2111	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2112	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2113	break;
2114	case SVGA_FIFO_RESERVED:
2115	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2116	break;
2117	case SVGA_FIFO_CURSOR_SCREEN_ID:
2118	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2119	break;
2120	case SVGA_FIFO_DEAD:
2121	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2122	break;
2123	case SVGA_FIFO_3D_HWVERSION_REVISED:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS_LAST:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_GUEST_3D_HWVERSION:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_FENCE_GOAL:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_BUSY:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	default:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	}
2391
2392	return VINF_EM_RAW_EMULATE_INSTR;
2393	}
2394	# endif /* DEBUG_FIFO_ACCESS */
2395
2396	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2397	/**
2398	* HC access handler for the FIFO.
2399	*
2400	* @returns VINF_SUCCESS if the handler have carried out the operation.
2401	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2402	* @param pVM VM Handle.
2403	* @param pVCpu The cross context CPU structure for the calling EMT.
2404	* @param GCPhys The physical address the guest is writing to.
2405	* @param pvPhys The HC mapping of that address.
2406	* @param pvBuf What the guest is reading/writing.
2407	* @param cbBuf How much it's reading/writing.
2408	* @param enmAccessType The access type.
2409	* @param enmOrigin Who is making the access.
2410	* @param pvUser User argument.
2411	*/
2412	static DECLCALLBACK(VBOXSTRICTRC)
2413	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2414	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2415	{
2416	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2417	PVGASTATE pThis = (PVGASTATE)pvUser;
2418	AssertPtr(pThis);
2419
2420	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2421	/*
2422	* Wake up the FIFO thread as it might have work to do now.
2423	*/
2424	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2425	AssertLogRelRC(rc);
2426	# endif
2427
2428	# ifdef DEBUG_FIFO_ACCESS
2429	/*
2430	* When in debug-fifo-access mode, we do not disable the access handler,
2431	* but leave it on as we wish to catch all access.
2432	*/
2433	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2434	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2435	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2436	/*
2437	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2438	*/
2439	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2440	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2441	# endif
2442	if (RT_SUCCESS(rc))
2443	return VINF_PGM_HANDLER_DO_DEFAULT;
2444	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2445	return rc;
2446	}
2447	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2448
2449	#endif /* IN_RING3 */
2450
2451	#ifdef DEBUG_GMR_ACCESS
2452	# ifdef IN_RING3
2453
2454	/**
2455	* HC access handler for the FIFO.
2456	*
2457	* @returns VINF_SUCCESS if the handler have carried out the operation.
2458	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2459	* @param pVM VM Handle.
2460	* @param pVCpu The cross context CPU structure for the calling EMT.
2461	* @param GCPhys The physical address the guest is writing to.
2462	* @param pvPhys The HC mapping of that address.
2463	* @param pvBuf What the guest is reading/writing.
2464	* @param cbBuf How much it's reading/writing.
2465	* @param enmAccessType The access type.
2466	* @param enmOrigin Who is making the access.
2467	* @param pvUser User argument.
2468	*/
2469	static DECLCALLBACK(VBOXSTRICTRC)
2470	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2471	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2472	{
2473	PVGASTATE pThis = (PVGASTATE)pvUser;
2474	Assert(pThis);
2475	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2476	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2477
2478	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2479
2480	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2481	{
2482	PGMR pGMR = &pSVGAState->paGMR[i];
2483
2484	if (pGMR->numDescriptors)
2485	{
2486	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2487	{
2488	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2489	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2490	{
2491	/*
2492	* Turn off the write handler for this particular page and make it R/W.
2493	* Then return telling the caller to restart the guest instruction.
2494	*/
2495	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2496	AssertRC(rc);
2497	return VINF_PGM_HANDLER_DO_DEFAULT;
2498	}
2499	}
2500	}
2501	}
2502
2503	return VINF_PGM_HANDLER_DO_DEFAULT;
2504	}
2505
2506	/** Callback handler for VMR3ReqCallWaitU */
2507	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2508	{
2509	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2510	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2511	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2512	int rc;
2513
2514	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2515	{
2516	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2517	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2518	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2519	AssertRC(rc);
2520	}
2521	return VINF_SUCCESS;
2522	}
2523
2524	/** Callback handler for VMR3ReqCallWaitU */
2525	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2526	{
2527	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2528	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2529	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2530
2531	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2532	{
2533	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2534	AssertRC(rc);
2535	}
2536	return VINF_SUCCESS;
2537	}
2538
2539	/** Callback handler for VMR3ReqCallWaitU */
2540	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2541	{
2542	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2543
2544	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2545	{
2546	PGMR pGMR = &pSVGAState->paGMR[i];
2547
2548	if (pGMR->numDescriptors)
2549	{
2550	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2551	{
2552	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2553	AssertRC(rc);
2554	}
2555	}
2556	}
2557	return VINF_SUCCESS;
2558	}
2559
2560	# endif /* IN_RING3 */
2561	#endif /* DEBUG_GMR_ACCESS */
2562
2563	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2564
2565	#ifdef IN_RING3
2566
2567
2568	/**
2569	* Common worker for changing the pointer shape.
2570	*
2571	* @param pThisCC The VGA/VMSVGA state for ring-3.
2572	* @param pSVGAState The VMSVGA ring-3 instance data.
2573	* @param fAlpha Whether there is alpha or not.
2574	* @param xHot Hotspot x coordinate.
2575	* @param yHot Hotspot y coordinate.
2576	* @param cx Width.
2577	* @param cy Height.
2578	* @param pbData Heap copy of the cursor data. Consumed.
2579	* @param cbData The size of the data.
2580	*/
2581	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2582	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2583	{
2584	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2585	# ifdef LOG_ENABLED
2586	if (LogIs2Enabled())
2587	{
2588	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2589	if (!fAlpha)
2590	{
2591	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2592	for (uint32_t y = 0; y < cy; y++)
2593	{
2594	Log2(("%3u:", y));
2595	uint8_t const pbLine = &pbData[y cbAndLine];
2596	for (uint32_t x = 0; x < cx; x += 8)
2597	{
2598	uint8_t b = pbLine[x / 8];
2599	char szByte[12];
2600	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2601	szByte[1] = b & 0x40 ? '*' : ' ';
2602	szByte[2] = b & 0x20 ? '*' : ' ';
2603	szByte[3] = b & 0x10 ? '*' : ' ';
2604	szByte[4] = b & 0x08 ? '*' : ' ';
2605	szByte[5] = b & 0x04 ? '*' : ' ';
2606	szByte[6] = b & 0x02 ? '*' : ' ';
2607	szByte[7] = b & 0x01 ? '*' : ' ';
2608	szByte[8] = '\0';
2609	Log2(("%s", szByte));
2610	}
2611	Log2(("\n"));
2612	}
2613	}
2614
2615	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2616	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2617	for (uint32_t y = 0; y < cy; y++)
2618	{
2619	Log2(("%3u:", y));
2620	uint32_t const pu32Line = &pu32Xor[y cx];
2621	for (uint32_t x = 0; x < cx; x++)
2622	Log2((" %08x", pu32Line[x]));
2623	Log2(("\n"));
2624	}
2625	}
2626	# endif
2627
2628	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2629	AssertRC(rc);
2630
2631	if (pSVGAState->Cursor.fActive)
2632	RTMemFree(pSVGAState->Cursor.pData);
2633
2634	pSVGAState->Cursor.fActive = true;
2635	pSVGAState->Cursor.xHotspot = xHot;
2636	pSVGAState->Cursor.yHotspot = yHot;
2637	pSVGAState->Cursor.width = cx;
2638	pSVGAState->Cursor.height = cy;
2639	pSVGAState->Cursor.cbData = cbData;
2640	pSVGAState->Cursor.pData = pbData;
2641	}
2642
2643
2644	/**
2645	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2646	*
2647	* @param pThis The shared VGA/VMSVGA state.
2648	* @param pThisCC The VGA/VMSVGA state for ring-3.
2649	* @param pSVGAState The VMSVGA ring-3 instance data.
2650	* @param pCursor The cursor.
2651	* @param pbSrcAndMask The AND mask.
2652	* @param cbSrcAndLine The scanline length of the AND mask.
2653	* @param pbSrcXorMask The XOR mask.
2654	* @param cbSrcXorLine The scanline length of the XOR mask.
2655	*/
2656	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2657	SVGAFifoCmdDefineCursor const *pCursor,
2658	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2659	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2660	{
2661	uint32_t const cx = pCursor->width;
2662	uint32_t const cy = pCursor->height;
2663
2664	/*
2665	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2666	* The AND data uses 8-bit aligned scanlines.
2667	* The XOR data must be starting on a 32-bit boundrary.
2668	*/
2669	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2670	uint32_t cbDstAndMask = cbDstAndLine * cy;
2671	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2672	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2673
2674	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2675	AssertReturnVoid(pbCopy);
2676
2677	/* Convert the AND mask. */
2678	uint8_t *pbDst = pbCopy;
2679	uint8_t const *pbSrc = pbSrcAndMask;
2680	switch (pCursor->andMaskDepth)
2681	{
2682	case 1:
2683	if (cbSrcAndLine == cbDstAndLine)
2684	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2685	else
2686	{
2687	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2688	for (uint32_t y = 0; y < cy; y++)
2689	{
2690	memcpy(pbDst, pbSrc, cbDstAndLine);
2691	pbDst += cbDstAndLine;
2692	pbSrc += cbSrcAndLine;
2693	}
2694	}
2695	break;
2696	/* Should take the XOR mask into account for the multi-bit AND mask. */
2697	case 8:
2698	for (uint32_t y = 0; y < cy; y++)
2699	{
2700	for (uint32_t x = 0; x < cx; )
2701	{
2702	uint8_t bDst = 0;
2703	uint8_t fBit = 1;
2704	do
2705	{
2706	uintptr_t const idxPal = pbSrc[x] * 3;
2707	if ((( pThis->last_palette[idxPal]
2708	\| (pThis->last_palette[idxPal] >> 8)
2709	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2710	bDst \|= fBit;
2711	fBit <<= 1;
2712	x++;
2713	} while (x < cx && (x & 7));
2714	pbDst[(x - 1) / 8] = bDst;
2715	}
2716	pbDst += cbDstAndLine;
2717	pbSrc += cbSrcAndLine;
2718	}
2719	break;
2720	case 15:
2721	for (uint32_t y = 0; y < cy; y++)
2722	{
2723	for (uint32_t x = 0; x < cx; )
2724	{
2725	uint8_t bDst = 0;
2726	uint8_t fBit = 1;
2727	do
2728	{
2729	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2730	bDst \|= fBit;
2731	fBit <<= 1;
2732	x++;
2733	} while (x < cx && (x & 7));
2734	pbDst[(x - 1) / 8] = bDst;
2735	}
2736	pbDst += cbDstAndLine;
2737	pbSrc += cbSrcAndLine;
2738	}
2739	break;
2740	case 16:
2741	for (uint32_t y = 0; y < cy; y++)
2742	{
2743	for (uint32_t x = 0; x < cx; )
2744	{
2745	uint8_t bDst = 0;
2746	uint8_t fBit = 1;
2747	do
2748	{
2749	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2750	bDst \|= fBit;
2751	fBit <<= 1;
2752	x++;
2753	} while (x < cx && (x & 7));
2754	pbDst[(x - 1) / 8] = bDst;
2755	}
2756	pbDst += cbDstAndLine;
2757	pbSrc += cbSrcAndLine;
2758	}
2759	break;
2760	case 24:
2761	for (uint32_t y = 0; y < cy; y++)
2762	{
2763	for (uint32_t x = 0; x < cx; )
2764	{
2765	uint8_t bDst = 0;
2766	uint8_t fBit = 1;
2767	do
2768	{
2769	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2770	bDst \|= fBit;
2771	fBit <<= 1;
2772	x++;
2773	} while (x < cx && (x & 7));
2774	pbDst[(x - 1) / 8] = bDst;
2775	}
2776	pbDst += cbDstAndLine;
2777	pbSrc += cbSrcAndLine;
2778	}
2779	break;
2780	case 32:
2781	for (uint32_t y = 0; y < cy; y++)
2782	{
2783	for (uint32_t x = 0; x < cx; )
2784	{
2785	uint8_t bDst = 0;
2786	uint8_t fBit = 1;
2787	do
2788	{
2789	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2790	bDst \|= fBit;
2791	fBit <<= 1;
2792	x++;
2793	} while (x < cx && (x & 7));
2794	pbDst[(x - 1) / 8] = bDst;
2795	}
2796	pbDst += cbDstAndLine;
2797	pbSrc += cbSrcAndLine;
2798	}
2799	break;
2800	default:
2801	RTMemFree(pbCopy);
2802	AssertFailedReturnVoid();
2803	}
2804
2805	/* Convert the XOR mask. */
2806	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2807	pbSrc = pbSrcXorMask;
2808	switch (pCursor->xorMaskDepth)
2809	{
2810	case 1:
2811	for (uint32_t y = 0; y < cy; y++)
2812	{
2813	for (uint32_t x = 0; x < cx; )
2814	{
2815	/* most significant bit is the left most one. */
2816	uint8_t bSrc = pbSrc[x / 8];
2817	do
2818	{
2819	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2820	bSrc <<= 1;
2821	x++;
2822	} while ((x & 7) && x < cx);
2823	}
2824	pbSrc += cbSrcXorLine;
2825	}
2826	break;
2827	case 8:
2828	for (uint32_t y = 0; y < cy; y++)
2829	{
2830	for (uint32_t x = 0; x < cx; x++)
2831	{
2832	uint32_t u = pThis->last_palette[pbSrc[x]];
2833	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2834	}
2835	pbSrc += cbSrcXorLine;
2836	}
2837	break;
2838	case 15: /* Src: RGB-5-5-5 */
2839	for (uint32_t y = 0; y < cy; y++)
2840	{
2841	for (uint32_t x = 0; x < cx; x++)
2842	{
2843	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2844	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2845	((uValue >> 5) & 0x1f) << 3,
2846	((uValue >> 10) & 0x1f) << 3, 0);
2847	}
2848	pbSrc += cbSrcXorLine;
2849	}
2850	break;
2851	case 16: /* Src: RGB-5-6-5 */
2852	for (uint32_t y = 0; y < cy; y++)
2853	{
2854	for (uint32_t x = 0; x < cx; x++)
2855	{
2856	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2857	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2858	((uValue >> 5) & 0x3f) << 2,
2859	((uValue >> 11) & 0x1f) << 3, 0);
2860	}
2861	pbSrc += cbSrcXorLine;
2862	}
2863	break;
2864	case 24:
2865	for (uint32_t y = 0; y < cy; y++)
2866	{
2867	for (uint32_t x = 0; x < cx; x++)
2868	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2869	pbSrc += cbSrcXorLine;
2870	}
2871	break;
2872	case 32:
2873	for (uint32_t y = 0; y < cy; y++)
2874	{
2875	for (uint32_t x = 0; x < cx; x++)
2876	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2877	pbSrc += cbSrcXorLine;
2878	}
2879	break;
2880	default:
2881	RTMemFree(pbCopy);
2882	AssertFailedReturnVoid();
2883	}
2884
2885	/*
2886	* Pass it to the frontend/whatever.
2887	*/
2888	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2889	}
2890
2891
2892	/**
2893	* Worker for vmsvgaR3FifoThread that handles an external command.
2894	*
2895	* @param pDevIns The device instance.
2896	* @param pThis The shared VGA/VMSVGA instance data.
2897	* @param pThisCC The VGA/VMSVGA state for ring-3.
2898	*/
2899	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2900	{
2901	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2902	switch (pThis->svga.u8FIFOExtCommand)
2903	{
2904	case VMSVGA_FIFO_EXTCMD_RESET:
2905	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2906	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2907	# ifdef VBOX_WITH_VMSVGA3D
2908	if (pThis->svga.f3DEnabled)
2909	{
2910	/* The 3d subsystem must be reset from the fifo thread. */
2911	vmsvga3dReset(pThisCC);
2912	}
2913	# endif
2914	break;
2915
2916	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2917	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2918	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2919	# ifdef VBOX_WITH_VMSVGA3D
2920	if (pThis->svga.f3DEnabled)
2921	{
2922	/* The 3d subsystem must be shut down from the fifo thread. */
2923	vmsvga3dTerminate(pThisCC);
2924	}
2925	# endif
2926	break;
2927
2928	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2929	{
2930	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2931	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
2932	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2933	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
2934	# ifdef VBOX_WITH_VMSVGA3D
2935	if (pThis->svga.f3DEnabled)
2936	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
2937	# endif
2938	break;
2939	}
2940
2941	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2942	{
2943	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2944	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
2945	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2946	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2947	# ifdef VBOX_WITH_VMSVGA3D
2948	if (pThis->svga.f3DEnabled)
2949	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2950	# endif
2951	break;
2952	}
2953
2954	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2955	{
2956	# ifdef VBOX_WITH_VMSVGA3D
2957	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
2958	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2959	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
2960	# endif
2961	break;
2962	}
2963
2964
2965	default:
2966	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
2967	break;
2968	}
2969
2970	/*
2971	* Signal the end of the external command.
2972	*/
2973	pThisCC->svga.pvFIFOExtCmdParam = NULL;
2974	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2975	ASMMemoryFence(); /* paranoia^2 */
2976	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
2977	AssertLogRelRC(rc);
2978	}
2979
2980	/**
2981	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2982	* doing a job on the FIFO thread (even when it's officially suspended).
2983	*
2984	* @returns VBox status code (fully asserted).
2985	* @param pDevIns The device instance.
2986	* @param pThis The shared VGA/VMSVGA instance data.
2987	* @param pThisCC The VGA/VMSVGA state for ring-3.
2988	* @param uExtCmd The command to execute on the FIFO thread.
2989	* @param pvParam Pointer to command parameters.
2990	* @param cMsWait The time to wait for the command, given in
2991	* milliseconds.
2992	*/
2993	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
2994	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2995	{
2996	Assert(cMsWait >= RT_MS_1SEC * 5);
2997	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2998	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2999
3000	int rc;
3001	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3002	PDMTHREADSTATE enmState = pThread->enmState;
3003	if (enmState == PDMTHREADSTATE_SUSPENDED)
3004	{
3005	/*
3006	* The thread is suspended, we have to temporarily wake it up so it can
3007	* perform the task.
3008	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3009	*/
3010	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3011	/* Post the request. */
3012	pThis->svga.fFifoExtCommandWakeup = true;
3013	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3014	pThis->svga.u8FIFOExtCommand = uExtCmd;
3015	ASMMemoryFence(); /* paranoia^3 */
3016
3017	/* Resume the thread. */
3018	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3019	AssertLogRelRC(rc);
3020	if (RT_SUCCESS(rc))
3021	{
3022	/* Wait. Take care in case the semaphore was already posted (same as below). */
3023	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3024	if ( rc == VINF_SUCCESS
3025	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3026	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3027	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3028	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3029
3030	/* suspend the thread */
3031	pThis->svga.fFifoExtCommandWakeup = false;
3032	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3033	AssertLogRelRC(rc2);
3034	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3035	rc = rc2;
3036	}
3037	pThis->svga.fFifoExtCommandWakeup = false;
3038	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3039	}
3040	else if (enmState == PDMTHREADSTATE_RUNNING)
3041	{
3042	/*
3043	* The thread is running, should only happen during reset and vmsvga3dsfc.
3044	* We ASSUME not racing code here, both wrt thread state and ext commands.
3045	*/
3046	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3047	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3048
3049	/* Post the request. */
3050	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3051	pThis->svga.u8FIFOExtCommand = uExtCmd;
3052	ASMMemoryFence(); /* paranoia^2 */
3053	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3054	AssertLogRelRC(rc);
3055
3056	/* Wait. Take care in case the semaphore was already posted (same as above). */
3057	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3058	if ( rc == VINF_SUCCESS
3059	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3060	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3061	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3062	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3063
3064	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3065	}
3066	else
3067	{
3068	/*
3069	* Something is wrong with the thread!
3070	*/
3071	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3072	rc = VERR_INVALID_STATE;
3073	}
3074	return rc;
3075	}
3076
3077
3078	/**
3079	* Marks the FIFO non-busy, notifying any waiting EMTs.
3080	*
3081	* @param pDevIns The device instance.
3082	* @param pThis The shared VGA/VMSVGA instance data.
3083	* @param pThisCC The VGA/VMSVGA state for ring-3.
3084	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3085	* @param offFifoMin The start byte offset of the command FIFO.
3086	*/
3087	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3088	{
3089	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3090	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3091	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3092
3093	/* Wake up any waiting EMTs. */
3094	if (pSVGAState->cBusyDelayedEmts > 0)
3095	{
3096	# ifdef VMSVGA_USE_EMT_HALT_CODE
3097	PVM pVM = PDMDevHlpGetVM(pDevIns);
3098	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3099	if (idCpu != NIL_VMCPUID)
3100	{
3101	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3102	while (idCpu-- > 0)
3103	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3104	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3105	}
3106	# else
3107	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3108	AssertRC(rc2);
3109	# endif
3110	}
3111	}
3112
3113	/**
3114	* Reads (more) payload into the command buffer.
3115	*
3116	* @returns pbBounceBuf on success
3117	* @retval (void *)1 if the thread was requested to stop.
3118	* @retval NULL on FIFO error.
3119	*
3120	* @param cbPayloadReq The number of bytes of payload requested.
3121	* @param pFIFO The FIFO.
3122	* @param offCurrentCmd The FIFO byte offset of the current command.
3123	* @param offFifoMin The start byte offset of the command FIFO.
3124	* @param offFifoMax The end byte offset of the command FIFO.
3125	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3126	* always sufficient size.
3127	* @param pcbAlreadyRead How much payload we've already read into the bounce
3128	* buffer. (We will NEVER re-read anything.)
3129	* @param pThread The calling PDM thread handle.
3130	* @param pThis The shared VGA/VMSVGA instance data.
3131	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3132	* statistics collection.
3133	* @param pDevIns The device instance.
3134	*/
3135	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3136	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3137	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3138	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3139	{
3140	Assert(pbBounceBuf);
3141	Assert(pcbAlreadyRead);
3142	Assert(offFifoMin < offFifoMax);
3143	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3144	Assert(offFifoMax <= pThis->svga.cbFIFO);
3145
3146	/*
3147	* Check if the requested payload size has already been satisfied .
3148	* .
3149	* When called to read more, the caller is responsible for making sure the .
3150	* new command size (cbRequsted) never is smaller than what has already .
3151	* been read.
3152	*/
3153	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3154	if (cbPayloadReq <= cbAlreadyRead)
3155	{
3156	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3157	return pbBounceBuf;
3158	}
3159
3160	/*
3161	* Commands bigger than the fifo buffer are invalid.
3162	*/
3163	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3164	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3165	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3166	NULL);
3167
3168	/*
3169	* Move offCurrentCmd past the command dword.
3170	*/
3171	offCurrentCmd += sizeof(uint32_t);
3172	if (offCurrentCmd >= offFifoMax)
3173	offCurrentCmd = offFifoMin;
3174
3175	/*
3176	* Do we have sufficient payload data available already?
3177	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3178	*/
3179	uint32_t cbAfter, cbBefore;
3180	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3181	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3182	if (offNextCmd >= offCurrentCmd)
3183	{
3184	if (RT_LIKELY(offNextCmd < offFifoMax))
3185	cbAfter = offNextCmd - offCurrentCmd;
3186	else
3187	{
3188	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3189	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3190	offNextCmd, offFifoMin, offFifoMax));
3191	cbAfter = offFifoMax - offCurrentCmd;
3192	}
3193	cbBefore = 0;
3194	}
3195	else
3196	{
3197	cbAfter = offFifoMax - offCurrentCmd;
3198	if (offNextCmd >= offFifoMin)
3199	cbBefore = offNextCmd - offFifoMin;
3200	else
3201	{
3202	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3203	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3204	offNextCmd, offFifoMin, offFifoMax));
3205	cbBefore = 0;
3206	}
3207	}
3208	if (cbAfter + cbBefore < cbPayloadReq)
3209	{
3210	/*
3211	* Insufficient, must wait for it to arrive.
3212	*/
3213	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3214	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3215	for (uint32_t i = 0;; i++)
3216	{
3217	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3218	{
3219	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3220	return (void *)(uintptr_t)1;
3221	}
3222	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3223	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3224
3225	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3226
3227	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3228	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3229	if (offNextCmd >= offCurrentCmd)
3230	{
3231	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3232	cbBefore = 0;
3233	}
3234	else
3235	{
3236	cbAfter = offFifoMax - offCurrentCmd;
3237	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3238	}
3239
3240	if (cbAfter + cbBefore >= cbPayloadReq)
3241	break;
3242	}
3243	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3244	}
3245
3246	/*
3247	* Copy out the memory and update what pcbAlreadyRead points to.
3248	*/
3249	if (cbAfter >= cbPayloadReq)
3250	memcpy(pbBounceBuf + cbAlreadyRead,
3251	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3252	cbPayloadReq - cbAlreadyRead);
3253	else
3254	{
3255	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3256	if (cbAlreadyRead < cbAfter)
3257	{
3258	memcpy(pbBounceBuf + cbAlreadyRead,
3259	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3260	cbAfter - cbAlreadyRead);
3261	cbAlreadyRead = cbAfter;
3262	}
3263	memcpy(pbBounceBuf + cbAlreadyRead,
3264	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3265	cbPayloadReq - cbAlreadyRead);
3266	}
3267	*pcbAlreadyRead = cbPayloadReq;
3268	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3269	return pbBounceBuf;
3270	}
3271
3272
3273	/**
3274	* Sends cursor position and visibility information from the FIFO to the front-end.
3275	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3276	*/
3277	static uint32_t
3278	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3279	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3280	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3281	{
3282	/*
3283	* Check if the cursor update counter has changed and try get a stable
3284	* set of values if it has. This is race-prone, especially consindering
3285	* the screen ID, but little we can do about that.
3286	*/
3287	uint32_t x, y, fVisible, idScreen;
3288	for (uint32_t i = 0; ; i++)
3289	{
3290	x = pFIFO[SVGA_FIFO_CURSOR_X];
3291	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3292	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3293	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3294	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3295	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3296	\|\| i > 3)
3297	break;
3298	if (i == 0)
3299	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3300	ASMNopPause();
3301	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3302	}
3303
3304	/*
3305	* Check if anything has changed, as calling into pDrv is not light-weight.
3306	*/
3307	if ( *pxLast == x
3308	&& *pyLast == y
3309	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3310	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3311	else
3312	{
3313	/*
3314	* Detected changes.
3315	*
3316	* We handle global, not per-screen visibility information by sending
3317	* pfnVBVAMousePointerShape without shape data.
3318	*/
3319	*pxLast = x;
3320	*pyLast = y;
3321	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3322	if (idScreen != SVGA_ID_INVALID)
3323	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3324	else if (*pfLastVisible != fVisible)
3325	{
3326	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3327	*pfLastVisible = fVisible;
3328	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3329	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3330	}
3331	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3332	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3333	}
3334
3335	/*
3336	* Update done. Signal this to the guest.
3337	*/
3338	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3339
3340	return uCursorUpdateCount;
3341	}
3342
3343
3344	/**
3345	* Checks if there is work to be done, either cursor updating or FIFO commands.
3346	*
3347	* @returns true if pending work, false if not.
3348	* @param pFIFO The FIFO to examine.
3349	* @param uLastCursorCount The last cursor update counter value.
3350	*/
3351	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3352	{
3353	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3354	return true;
3355
3356	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3357	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3358	return true;
3359
3360	return false;
3361	}
3362
3363
3364	/**
3365	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3366	*
3367	* @param pDevIns The device instance.
3368	* @param pThis The shared VGA/VMSVGA instance data.
3369	* @param pThisCC The VGA/VMSVGA state for ring-3.
3370	*/
3371	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3372	{
3373	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3374	to recheck it before doing the signalling. */
3375	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3376	AssertReturnVoid(pFIFO);
3377	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3378	&& pThis->svga.fFIFOThreadSleeping)
3379	{
3380	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3381	AssertRC(rc);
3382	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3383	}
3384	}
3385
3386
3387	/*
3388	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3389	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3390	*/
3391	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3392	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3393	*
3394	* Will break out of the switch on failure.
3395	* Will restart and quit the loop if the thread was requested to stop.
3396	*
3397	* @param a_PtrVar Request variable pointer.
3398	* @param a_Type Request typedef (not pointer) for casting.
3399	* @param a_cbPayloadReq How much payload to fetch.
3400	* @remarks Accesses a bunch of variables in the current scope!
3401	*/
3402	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3403	if (1) { \
3404	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3405	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3406	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3407	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3408	} else do {} while (0)
3409	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3410	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3411	* buffer after figuring out the actual command size.
3412	*
3413	* Will break out of the switch on failure.
3414	*
3415	* @param a_PtrVar Request variable pointer.
3416	* @param a_Type Request typedef (not pointer) for casting.
3417	* @param a_cbPayloadReq How much payload to fetch.
3418	* @remarks Accesses a bunch of variables in the current scope!
3419	*/
3420	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3421	if (1) { \
3422	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3423	} else do {} while (0)
3424
3425	/**
3426	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3427	*/
3428	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3429	{
3430	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3431	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3432	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3433	int rc;
3434
3435	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3436	return VINF_SUCCESS;
3437
3438	/*
3439	* Special mode where we only execute an external command and the go back
3440	* to being suspended. Currently, all ext cmds ends up here, with the reset
3441	* one also being eligble for runtime execution further down as well.
3442	*/
3443	if (pThis->svga.fFifoExtCommandWakeup)
3444	{
3445	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3446	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3447	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3448	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3449	else
3450	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3451	return VINF_SUCCESS;
3452	}
3453
3454
3455	/*
3456	* Signal the semaphore to make sure we don't wait for 250ms after a
3457	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3458	*/
3459	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3460
3461	/*
3462	* Allocate a bounce buffer for command we get from the FIFO.
3463	* (All code must return via the end of the function to free this buffer.)
3464	*/
3465	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3466	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3467
3468	/*
3469	* Polling/sleep interval config.
3470	*
3471	* We wait for an a short interval if the guest has recently given us work
3472	* to do, but the interval increases the longer we're kept idle. Once we've
3473	* reached the refresh timer interval, we'll switch to extended waits,
3474	* depending on it or the guest to kick us into action when needed.
3475	*
3476	* Should the refresh time go fishing, we'll just continue increasing the
3477	* sleep length till we reaches the 250 ms max after about 16 seconds.
3478	*/
3479	RTMSINTERVAL const cMsMinSleep = 16;
3480	RTMSINTERVAL const cMsIncSleep = 2;
3481	RTMSINTERVAL const cMsMaxSleep = 250;
3482	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3483	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3484
3485	/*
3486	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3487	*
3488	* Initialize with values that will detect an update from the guest.
3489	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3490	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3491	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3492	*/
3493	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3494	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3495	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3496	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3497	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3498
3499	/*
3500	* The FIFO loop.
3501	*/
3502	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3503	bool fBadOrDisabledFifo = false;
3504	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3505	{
3506	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3507	/*
3508	* Should service the run loop every so often.
3509	*/
3510	if (pThis->svga.f3DEnabled)
3511	vmsvga3dCocoaServiceRunLoop();
3512	# endif
3513
3514	/*
3515	* Unless there's already work pending, go to sleep for a short while.
3516	* (See polling/sleep interval config above.)
3517	*/
3518	if ( fBadOrDisabledFifo
3519	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3520	{
3521	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3522	Assert(pThis->cMilliesRefreshInterval > 0);
3523	if (cMsSleep < pThis->cMilliesRefreshInterval)
3524	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3525	else
3526	{
3527	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3528	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3529	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3530	# endif
3531	if ( !fBadOrDisabledFifo
3532	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3533	rc = VINF_SUCCESS;
3534	else
3535	{
3536	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3537	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3538	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3539	}
3540	}
3541	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3542	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3543	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3544	{
3545	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3546	break;
3547	}
3548	}
3549	else
3550	rc = VINF_SUCCESS;
3551	fBadOrDisabledFifo = false;
3552	if (rc == VERR_TIMEOUT)
3553	{
3554	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3555	{
3556	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3557	continue;
3558	}
3559	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3560
3561	Log(("vmsvgaR3FifoLoop: timeout\n"));
3562	}
3563	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3564	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3565	cMsSleep = cMsMinSleep;
3566
3567	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3568	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3569	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3570
3571	/*
3572	* Handle external commands (currently only reset).
3573	*/
3574	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3575	{
3576	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3577	continue;
3578	}
3579
3580	/*
3581	* The device must be enabled and configured.
3582	*/
3583	if ( !pThis->svga.fEnabled
3584	\|\| !pThis->svga.fConfigured)
3585	{
3586	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3587	fBadOrDisabledFifo = true;
3588	cMsSleep = cMsMaxSleep; /* cheat */
3589	continue;
3590	}
3591
3592	/*
3593	* Get and check the min/max values. We ASSUME that they will remain
3594	* unchanged while we process requests. A further ASSUMPTION is that
3595	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3596	* we don't read it back while in the loop.
3597	*/
3598	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3599	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3600	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3601	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3602	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3603	\|\| offFifoMax <= offFifoMin
3604	\|\| offFifoMax > pThis->svga.cbFIFO
3605	\|\| (offFifoMax & 3) != 0
3606	\|\| (offFifoMin & 3) != 0
3607	\|\| offCurrentCmd < offFifoMin
3608	\|\| offCurrentCmd > offFifoMax))
3609	{
3610	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3611	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3612	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3613	fBadOrDisabledFifo = true;
3614	continue;
3615	}
3616	RT_UNTRUSTED_VALIDATED_FENCE();
3617	if (RT_UNLIKELY(offCurrentCmd & 3))
3618	{
3619	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3620	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3621	offCurrentCmd &= ~UINT32_C(3);
3622	}
3623
3624	/*
3625	* Update the cursor position before we start on the FIFO commands.
3626	*/
3627	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3628	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3629	{
3630	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3631	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3632	{ /* halfways likely */ }
3633	else
3634	{
3635	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3636	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3637	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3638	}
3639	}
3640
3641	/*
3642	* Mark the FIFO as busy.
3643	*/
3644	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3645	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3646	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3647
3648	/*
3649	* Execute all queued FIFO commands.
3650	* Quit if pending external command or changes in the thread state.
3651	*/
3652	bool fDone = false;
3653	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3654	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3655	{
3656	uint32_t cbPayload = 0;
3657	uint32_t u32IrqStatus = 0;
3658
3659	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3660
3661	/* First check any pending actions. */
3662	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3663	{
3664	vmsvgaR3ChangeMode(pThis, pThisCC);
3665	# ifdef VBOX_WITH_VMSVGA3D
3666	if (pThisCC->svga.p3dState != NULL)
3667	vmsvga3dChangeMode(pThisCC);
3668	# endif
3669	}
3670
3671	/* Check for pending external commands (reset). */
3672	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3673	break;
3674
3675	/*
3676	* Process the command.
3677	*/
3678	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3679	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3680	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3681	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3682	switch (enmCmdId)
3683	{
3684	case SVGA_CMD_INVALID_CMD:
3685	/* Nothing to do. */
3686	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3687	break;
3688
3689	case SVGA_CMD_FENCE:
3690	{
3691	SVGAFifoCmdFence *pCmdFence;
3692	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3693	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3694	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3695	{
3696	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3697	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3698
3699	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3700	{
3701	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3702	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3703	}
3704	else
3705	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3706	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3707	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3708	{
3709	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3710	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3711	}
3712	}
3713	else
3714	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3715	break;
3716	}
3717	case SVGA_CMD_UPDATE:
3718	case SVGA_CMD_UPDATE_VERBOSE:
3719	{
3720	SVGAFifoCmdUpdate *pUpdate;
3721	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3722	if (enmCmdId == SVGA_CMD_UPDATE)
3723	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3724	else
3725	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3726	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3727	/** @todo Multiple screens? */
3728	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3729	AssertBreak(pScreen);
3730	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3731	break;
3732	}
3733
3734	case SVGA_CMD_DEFINE_CURSOR:
3735	{
3736	/* Followed by bitmap data. */
3737	SVGAFifoCmdDefineCursor *pCursor;
3738	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3739	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3740
3741	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3742	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3743	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3744	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3745	AssertBreak(pCursor->andMaskDepth <= 32);
3746	AssertBreak(pCursor->xorMaskDepth <= 32);
3747	RT_UNTRUSTED_VALIDATED_FENCE();
3748
3749	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3750	uint32_t cbAndMask = cbAndLine * pCursor->height;
3751	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3752	uint32_t cbXorMask = cbXorLine * pCursor->height;
3753	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3754
3755	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3756	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3757	break;
3758	}
3759
3760	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3761	{
3762	/* Followed by bitmap data. */
3763	uint32_t cbCursorShape, cbAndMask;
3764	uint8_t *pCursorCopy;
3765	uint32_t cbCmd;
3766
3767	SVGAFifoCmdDefineAlphaCursor *pCursor;
3768	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3769	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3770
3771	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3772
3773	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3774	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3775	RT_UNTRUSTED_VALIDATED_FENCE();
3776
3777	/* Refetch the bitmap data as well. */
3778	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3779	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3780	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3781
3782	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3783	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3784	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3785	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3786
3787	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3788	AssertBreak(pCursorCopy);
3789
3790	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3791	memset(pCursorCopy, 0xff, cbAndMask);
3792	/* Colour data */
3793	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3794
3795	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3796	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3797	break;
3798	}
3799
3800	case SVGA_CMD_ESCAPE:
3801	{
3802	/* Followed by nsize bytes of data. */
3803	SVGAFifoCmdEscape *pEscape;
3804	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3805	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3806
3807	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3808	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3809	RT_UNTRUSTED_VALIDATED_FENCE();
3810	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3811	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3812
3813	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3814	{
3815	AssertBreak(pEscape->size >= sizeof(uint32_t));
3816	RT_UNTRUSTED_VALIDATED_FENCE();
3817	uint32_t cmd = (uint32_t )(pEscape + 1);
3818	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3819
3820	switch (cmd)
3821	{
3822	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3823	{
3824	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3825	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3826	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3827
3828	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3829	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3830	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3831
3832	RT_NOREF_PV(pVideoCmd);
3833	break;
3834
3835	}
3836
3837	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3838	{
3839	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3840	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3841	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3842	RT_NOREF_PV(pVideoCmd);
3843	break;
3844	}
3845
3846	default:
3847	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3848	break;
3849	}
3850	}
3851	else
3852	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3853
3854	break;
3855	}
3856	# ifdef VBOX_WITH_VMSVGA3D
3857	case SVGA_CMD_DEFINE_GMR2:
3858	{
3859	SVGAFifoCmdDefineGMR2 *pCmd;
3860	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3861	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3862	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3863
3864	/* Validate current GMR id. */
3865	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3866	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3867	RT_UNTRUSTED_VALIDATED_FENCE();
3868
3869	if (!pCmd->numPages)
3870	{
3871	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3872	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3873	}
3874	else
3875	{
3876	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3877	if (pGMR->cMaxPages)
3878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3879
3880	/* Not sure if we should always free the descriptor, but for simplicity
3881	we do so if the new size is smaller than the current. */
3882	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3883	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3884	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3885
3886	pGMR->cMaxPages = pCmd->numPages;
3887	/* The rest is done by the REMAP_GMR2 command. */
3888	}
3889	break;
3890	}
3891
3892	case SVGA_CMD_REMAP_GMR2:
3893	{
3894	/* Followed by page descriptors or guest ptr. */
3895	SVGAFifoCmdRemapGMR2 *pCmd;
3896	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3897	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3898
3899	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3900	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3901	RT_UNTRUSTED_VALIDATED_FENCE();
3902
3903	/* Calculate the size of what comes after next and fetch it. */
3904	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3905	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3906	cbCmd += sizeof(SVGAGuestPtr);
3907	else
3908	{
3909	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3910	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3911	{
3912	cbCmd += cbPageDesc;
3913	pCmd->numPages = 1;
3914	}
3915	else
3916	{
3917	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3918	cbCmd += cbPageDesc * pCmd->numPages;
3919	}
3920	}
3921	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3922
3923	/* Validate current GMR id and size. */
3924	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3925	RT_UNTRUSTED_VALIDATED_FENCE();
3926	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3927	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3928	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3929	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3930
3931	if (pCmd->numPages == 0)
3932	break;
3933
3934	/** @todo Move to a separate function vmsvgaGMRRemap() */
3935
3936	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3937	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3938
3939	/*
3940	* We flatten the existing descriptors into a page array, overwrite the
3941	* pages specified in this command and then recompress the descriptor.
3942	*/
3943	/** @todo Optimize the GMR remap algorithm! */
3944
3945	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3946	uint64_t *paNewPage64 = NULL;
3947	if (pGMR->paDesc)
3948	{
3949	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3950
3951	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3952	AssertBreak(paNewPage64);
3953
3954	uint32_t idxPage = 0;
3955	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3956	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3957	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3958	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3959	RT_UNTRUSTED_VALIDATED_FENCE();
3960	}
3961
3962	/* Free the old GMR if present. */
3963	if (pGMR->paDesc)
3964	RTMemFree(pGMR->paDesc);
3965
3966	/* Allocate the maximum amount possible (everything non-continuous) */
3967	PVMSVGAGMRDESCRIPTOR paDescs;
3968	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3969	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3970
3971	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3972	{
3973	/** @todo */
3974	AssertFailed();
3975	pGMR->numDescriptors = 0;
3976	}
3977	else
3978	{
3979	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3980	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3981	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3982
3983	if (paNewPage64)
3984	{
3985	/* Overwrite the old page array with the new page values. */
3986	if (fGCPhys64)
3987	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3988	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3989	else
3990	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3991	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3992
3993	/* Use the updated page array instead of the command data. */
3994	fGCPhys64 = true;
3995	paPages64 = paNewPage64;
3996	pCmd->numPages = cNewTotalPages;
3997	}
3998
3999	/* The first page. */
4000	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4001	* applied to paNewPage64. */
4002	RTGCPHYS GCPhys;
4003	if (fGCPhys64)
4004	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4005	else
4006	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4007	paDescs[0].GCPhys = GCPhys;
4008	paDescs[0].numPages = 1;
4009
4010	/* Subsequent pages. */
4011	uint32_t iDescriptor = 0;
4012	for (uint32_t i = 1; i < pCmd->numPages; i++)
4013	{
4014	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4015	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4016	else
4017	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4018
4019	/* Continuous physical memory? */
4020	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4021	{
4022	Assert(paDescs[iDescriptor].numPages);
4023	paDescs[iDescriptor].numPages++;
4024	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4025	}
4026	else
4027	{
4028	iDescriptor++;
4029	paDescs[iDescriptor].GCPhys = GCPhys;
4030	paDescs[iDescriptor].numPages = 1;
4031	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4032	}
4033	}
4034
4035	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4036	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4037	pGMR->numDescriptors = iDescriptor + 1;
4038	}
4039
4040	if (paNewPage64)
4041	RTMemFree(paNewPage64);
4042
4043	# ifdef DEBUG_GMR_ACCESS
4044	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4045	# endif
4046	break;
4047	}
4048	# endif // VBOX_WITH_VMSVGA3D
4049	case SVGA_CMD_DEFINE_SCREEN:
4050	{
4051	/* The size of this command is specified by the guest and depends on capabilities. */
4052	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4053
4054	SVGAFifoCmdDefineScreen *pCmd;
4055	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4056	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4057	RT_UNTRUSTED_VALIDATED_FENCE();
4058
4059	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4060	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4061	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4062
4063	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4064	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4065	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4066
4067	uint32_t const idScreen = pCmd->screen.id;
4068	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4069
4070	uint32_t const uWidth = pCmd->screen.size.width;
4071	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4072
4073	uint32_t const uHeight = pCmd->screen.size.height;
4074	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4075
4076	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4077	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4078	AssertBreak(cbWidth <= cbPitch);
4079
4080	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4081	AssertBreak(uScreenOffset < pThis->vram_size);
4082
4083	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4084	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4085	AssertBreak( (uHeight == 0 && cbPitch == 0)
4086	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4087	RT_UNTRUSTED_VALIDATED_FENCE();
4088
4089	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4090
4091	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4092
4093	pScreen->fDefined = true;
4094	pScreen->fModified = true;
4095	pScreen->fuScreen = pCmd->screen.flags;
4096	pScreen->idScreen = idScreen;
4097	if (!fBlank)
4098	{
4099	AssertBreak(uWidth > 0 && uHeight > 0);
4100
4101	pScreen->xOrigin = pCmd->screen.root.x;
4102	pScreen->yOrigin = pCmd->screen.root.y;
4103	pScreen->cWidth = uWidth;
4104	pScreen->cHeight = uHeight;
4105	pScreen->offVRAM = uScreenOffset;
4106	pScreen->cbPitch = cbPitch;
4107	pScreen->cBpp = 32;
4108	}
4109	else
4110	{
4111	/* Keep old values. */
4112	}
4113
4114	pThis->svga.fGFBRegisters = false;
4115	vmsvgaR3ChangeMode(pThis, pThisCC);
4116	break;
4117	}
4118
4119	case SVGA_CMD_DESTROY_SCREEN:
4120	{
4121	SVGAFifoCmdDestroyScreen *pCmd;
4122	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4123	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4124
4125	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4126
4127	uint32_t const idScreen = pCmd->screenId;
4128	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4129	RT_UNTRUSTED_VALIDATED_FENCE();
4130
4131	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4132	pScreen->fModified = true;
4133	pScreen->fDefined = false;
4134	pScreen->idScreen = idScreen;
4135
4136	vmsvgaR3ChangeMode(pThis, pThisCC);
4137	break;
4138	}
4139
4140	case SVGA_CMD_DEFINE_GMRFB:
4141	{
4142	SVGAFifoCmdDefineGMRFB *pCmd;
4143	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4144	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4145
4146	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4147	pSVGAState->GMRFB.ptr = pCmd->ptr;
4148	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4149	pSVGAState->GMRFB.format = pCmd->format;
4150	break;
4151	}
4152
4153	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4154	{
4155	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4156	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4157	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4158
4159	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4160	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4161
4162	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4163	RT_UNTRUSTED_VALIDATED_FENCE();
4164
4165	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4166	AssertBreak(pScreen);
4167
4168	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4169	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4170
4171	/* Clip destRect to the screen dimensions. */
4172	SVGASignedRect screenRect;
4173	screenRect.left = 0;
4174	screenRect.top = 0;
4175	screenRect.right = pScreen->cWidth;
4176	screenRect.bottom = pScreen->cHeight;
4177	SVGASignedRect clipRect = pCmd->destRect;
4178	vmsvgaR3ClipRect(&screenRect, &clipRect);
4179	RT_UNTRUSTED_VALIDATED_FENCE();
4180
4181	uint32_t const width = clipRect.right - clipRect.left;
4182	uint32_t const height = clipRect.bottom - clipRect.top;
4183
4184	if ( width == 0
4185	\|\| height == 0)
4186	break; /* Nothing to do. */
4187
4188	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4189	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4190
4191	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4192	* Prepare parameters for vmsvgaR3GmrTransfer.
4193	*/
4194	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4195
4196	/* Destination: host buffer which describes the screen 0 VRAM.
4197	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4198	*/
4199	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4200	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4201	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4202	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4203	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4204	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4205	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4206	+ cbScanline * clipRect.top;
4207	int32_t const cbHstPitch = cbScanline;
4208
4209	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4210	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4211	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4212	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4213	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4214
4215	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4216	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4217	gstPtr, offGst, cbGstPitch,
4218	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4219	AssertRC(rc);
4220	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4221	break;
4222	}
4223
4224	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4225	{
4226	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4227	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4228	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4229
4230	/* Note! This can fetch 3d render results as well!! */
4231	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4232	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4233
4234	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4235	RT_UNTRUSTED_VALIDATED_FENCE();
4236
4237	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4238	AssertBreak(pScreen);
4239
4240	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4241	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4242
4243	/* Clip destRect to the screen dimensions. */
4244	SVGASignedRect screenRect;
4245	screenRect.left = 0;
4246	screenRect.top = 0;
4247	screenRect.right = pScreen->cWidth;
4248	screenRect.bottom = pScreen->cHeight;
4249	SVGASignedRect clipRect = pCmd->srcRect;
4250	vmsvgaR3ClipRect(&screenRect, &clipRect);
4251	RT_UNTRUSTED_VALIDATED_FENCE();
4252
4253	uint32_t const width = clipRect.right - clipRect.left;
4254	uint32_t const height = clipRect.bottom - clipRect.top;
4255
4256	if ( width == 0
4257	\|\| height == 0)
4258	break; /* Nothing to do. */
4259
4260	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4261	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4262
4263	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4264	* Prepare parameters for vmsvgaR3GmrTransfer.
4265	*/
4266	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4267
4268	/* Source: host buffer which describes the screen 0 VRAM.
4269	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4270	*/
4271	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4272	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4273	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4274	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4275	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4276	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4277	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4278	+ cbScanline * clipRect.top;
4279	int32_t const cbHstPitch = cbScanline;
4280
4281	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4282	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4283	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4284	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4285	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4286
4287	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4288	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4289	gstPtr, offGst, cbGstPitch,
4290	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4291	AssertRC(rc);
4292	break;
4293	}
4294
4295	case SVGA_CMD_ANNOTATION_FILL:
4296	{
4297	SVGAFifoCmdAnnotationFill *pCmd;
4298	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4299	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4300
4301	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4302	pSVGAState->colorAnnotation = pCmd->color;
4303	break;
4304	}
4305
4306	case SVGA_CMD_ANNOTATION_COPY:
4307	{
4308	SVGAFifoCmdAnnotationCopy *pCmd;
4309	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4310	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4311
4312	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4313	AssertFailed();
4314	break;
4315	}
4316
4317	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4318
4319	default:
4320	# ifdef VBOX_WITH_VMSVGA3D
4321	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4322	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4323	{
4324	RT_UNTRUSTED_VALIDATED_FENCE();
4325
4326	/* All 3d commands start with a common header, which defines the size of the command. */
4327	SVGA3dCmdHeader *pHdr;
4328	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4329	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4330	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4331	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4332
4333	if (RT_LIKELY(pThis->svga.f3DEnabled))
4334	{ /* likely */ }
4335	else
4336	{
4337	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4338	break;
4339	}
4340
4341	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4342	* Check that the 3D command has at least a_cbMin of payload bytes after the
4343	* header. Will break out of the switch if it doesn't.
4344	*/
4345	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4346	if (1) { \
4347	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4348	RT_UNTRUSTED_VALIDATED_FENCE(); \
4349	} else do {} while (0)
4350	switch ((int)enmCmdId)
4351	{
4352	case SVGA_3D_CMD_SURFACE_DEFINE:
4353	{
4354	uint32_t cMipLevels;
4355	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4356	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4357	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4358
4359	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4360	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4361	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4362	# ifdef DEBUG_GMR_ACCESS
4363	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4364	# endif
4365	break;
4366	}
4367
4368	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4369	{
4370	uint32_t cMipLevels;
4371	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4372	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4373	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4374
4375	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4376	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4377	pCmd->multisampleCount, pCmd->autogenFilter,
4378	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4379	break;
4380	}
4381
4382	case SVGA_3D_CMD_SURFACE_DESTROY:
4383	{
4384	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4385	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4386	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4387	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4388	break;
4389	}
4390
4391	case SVGA_3D_CMD_SURFACE_COPY:
4392	{
4393	uint32_t cCopyBoxes;
4394	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4395	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4396	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4397
4398	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4399	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4400	break;
4401	}
4402
4403	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4404	{
4405	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4406	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4407	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4408
4409	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4410	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4411	break;
4412	}
4413
4414	case SVGA_3D_CMD_SURFACE_DMA:
4415	{
4416	uint32_t cCopyBoxes;
4417	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4418	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4419	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4420
4421	uint64_t u64NanoTS = 0;
4422	if (LogRelIs3Enabled())
4423	u64NanoTS = RTTimeNanoTS();
4424	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4425	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4426	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4427	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4428	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4429	if (LogRelIs3Enabled())
4430	{
4431	if (cCopyBoxes)
4432	{
4433	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4434	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4435	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4436	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4437	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4438	}
4439	}
4440	break;
4441	}
4442
4443	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4444	{
4445	uint32_t cRects;
4446	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4447	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4448	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4449
4450	uint64_t u64NanoTS = 0;
4451	if (LogRelIs3Enabled())
4452	u64NanoTS = RTTimeNanoTS();
4453	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4454	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4455	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4456	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4457	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4458	if (LogRelIs3Enabled())
4459	{
4460	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4461	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4462	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4463	pFirstRect->left, pFirstRect->top,
4464	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4465	}
4466	break;
4467	}
4468
4469	case SVGA_3D_CMD_CONTEXT_DEFINE:
4470	{
4471	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4472	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4473	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4474
4475	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4476	break;
4477	}
4478
4479	case SVGA_3D_CMD_CONTEXT_DESTROY:
4480	{
4481	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4482	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4483	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4484
4485	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4486	break;
4487	}
4488
4489	case SVGA_3D_CMD_SETTRANSFORM:
4490	{
4491	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4492	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4493	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4494
4495	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4496	break;
4497	}
4498
4499	case SVGA_3D_CMD_SETZRANGE:
4500	{
4501	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4502	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4503	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4504
4505	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4506	break;
4507	}
4508
4509	case SVGA_3D_CMD_SETRENDERSTATE:
4510	{
4511	uint32_t cRenderStates;
4512	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4513	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4514	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4515
4516	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4517	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4518	break;
4519	}
4520
4521	case SVGA_3D_CMD_SETRENDERTARGET:
4522	{
4523	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4524	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4525	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4526
4527	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4528	break;
4529	}
4530
4531	case SVGA_3D_CMD_SETTEXTURESTATE:
4532	{
4533	uint32_t cTextureStates;
4534	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4535	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4536	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4537
4538	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4539	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4540	break;
4541	}
4542
4543	case SVGA_3D_CMD_SETMATERIAL:
4544	{
4545	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4546	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4547	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4548
4549	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4550	break;
4551	}
4552
4553	case SVGA_3D_CMD_SETLIGHTDATA:
4554	{
4555	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4556	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4557	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4558
4559	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4560	break;
4561	}
4562
4563	case SVGA_3D_CMD_SETLIGHTENABLED:
4564	{
4565	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4566	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4567	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4568
4569	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4570	break;
4571	}
4572
4573	case SVGA_3D_CMD_SETVIEWPORT:
4574	{
4575	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4576	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4578
4579	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4580	break;
4581	}
4582
4583	case SVGA_3D_CMD_SETCLIPPLANE:
4584	{
4585	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4586	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4587	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4588
4589	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4590	break;
4591	}
4592
4593	case SVGA_3D_CMD_CLEAR:
4594	{
4595	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4596	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4597	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4598
4599	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4600	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4601	break;
4602	}
4603
4604	case SVGA_3D_CMD_PRESENT:
4605	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4606	{
4607	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4608	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4609	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4610	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4611	else
4612	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4613
4614	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4615
4616	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4617	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4618	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4619	break;
4620	}
4621
4622	case SVGA_3D_CMD_SHADER_DEFINE:
4623	{
4624	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4625	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4626	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4627
4628	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4629	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4630	break;
4631	}
4632
4633	case SVGA_3D_CMD_SHADER_DESTROY:
4634	{
4635	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4636	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4637	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4638
4639	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4640	break;
4641	}
4642
4643	case SVGA_3D_CMD_SET_SHADER:
4644	{
4645	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4646	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4647	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4648
4649	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4650	break;
4651	}
4652
4653	case SVGA_3D_CMD_SET_SHADER_CONST:
4654	{
4655	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4656	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4657	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4658
4659	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4660	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4661	break;
4662	}
4663
4664	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4665	{
4666	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4667	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4668	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4669
4670	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4671	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4672	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4673	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4674	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4675
4676	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4677	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4678
4679	RT_UNTRUSTED_VALIDATED_FENCE();
4680
4681	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4682	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4683	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4684
4685	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4686	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4687	pNumRange, cVertexDivisor, pVertexDivisor);
4688	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4689	break;
4690	}
4691
4692	case SVGA_3D_CMD_SETSCISSORRECT:
4693	{
4694	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4695	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4696	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4697
4698	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4699	break;
4700	}
4701
4702	case SVGA_3D_CMD_BEGIN_QUERY:
4703	{
4704	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4705	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4706	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4707
4708	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4709	break;
4710	}
4711
4712	case SVGA_3D_CMD_END_QUERY:
4713	{
4714	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4715	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4716	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4717
4718	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4719	break;
4720	}
4721
4722	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4723	{
4724	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4725	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4726	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4727
4728	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4729	break;
4730	}
4731
4732	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4733	{
4734	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4735	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4736	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4737
4738	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4739	break;
4740	}
4741
4742	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4743	/* context id + surface id? */
4744	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4745	break;
4746	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4747	/* context id + surface id? */
4748	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4749	break;
4750
4751	default:
4752	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4753	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4754	break;
4755	}
4756	}
4757	else
4758	# endif // VBOX_WITH_VMSVGA3D
4759	{
4760	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4761	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4762	}
4763	}
4764
4765	/* Go to the next slot */
4766	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4767	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4768	if (offCurrentCmd >= offFifoMax)
4769	{
4770	offCurrentCmd -= offFifoMax - offFifoMin;
4771	Assert(offCurrentCmd >= offFifoMin);
4772	Assert(offCurrentCmd < offFifoMax);
4773	}
4774	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4775	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4776
4777	/*
4778	* Raise IRQ if required. Must enter the critical section here
4779	* before making final decisions here, otherwise cubebench and
4780	* others may end up waiting forever.
4781	*/
4782	if ( u32IrqStatus
4783	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4784	{
4785	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4786	AssertRC(rc2);
4787
4788	/* FIFO progress might trigger an interrupt. */
4789	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4790	{
4791	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4792	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4793	}
4794
4795	/* Unmasked IRQ pending? */
4796	if (pThis->svga.u32IrqMask & u32IrqStatus)
4797	{
4798	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4799	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4800	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4801	}
4802
4803	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4804	}
4805	}
4806
4807	/* If really done, clear the busy flag. */
4808	if (fDone)
4809	{
4810	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4811	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4812	}
4813	}
4814
4815	/*
4816	* Free the bounce buffer. (There are no returns above!)
4817	*/
4818	RTMemFree(pbBounceBuf);
4819
4820	return VINF_SUCCESS;
4821	}
4822
4823	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4824	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4825	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4826
4827	/**
4828	* Free the specified GMR
4829	*
4830	* @param pThisCC The VGA/VMSVGA state for ring-3.
4831	* @param idGMR GMR id
4832	*/
4833	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4834	{
4835	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4836
4837	/* Free the old descriptor if present. */
4838	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4839	if ( pGMR->numDescriptors
4840	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4841	{
4842	# ifdef DEBUG_GMR_ACCESS
4843	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4844	# endif
4845
4846	Assert(pGMR->paDesc);
4847	RTMemFree(pGMR->paDesc);
4848	pGMR->paDesc = NULL;
4849	pGMR->numDescriptors = 0;
4850	pGMR->cbTotal = 0;
4851	pGMR->cMaxPages = 0;
4852	}
4853	Assert(!pGMR->cMaxPages);
4854	Assert(!pGMR->cbTotal);
4855	}
4856
4857	/**
4858	* Copy between a GMR and a host memory buffer.
4859	*
4860	* @returns VBox status code.
4861	* @param pThis The shared VGA/VMSVGA instance data.
4862	* @param pThisCC The VGA/VMSVGA state for ring-3.
4863	* @param enmTransferType Transfer type (read/write)
4864	* @param pbHstBuf Host buffer pointer (valid)
4865	* @param cbHstBuf Size of host buffer (valid)
4866	* @param offHst Host buffer offset of the first scanline
4867	* @param cbHstPitch Destination buffer pitch
4868	* @param gstPtr GMR description
4869	* @param offGst Guest buffer offset of the first scanline
4870	* @param cbGstPitch Guest buffer pitch
4871	* @param cbWidth Width in bytes to copy
4872	* @param cHeight Number of scanllines to copy
4873	*/
4874	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4875	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4876	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4877	uint32_t cbWidth, uint32_t cHeight)
4878	{
4879	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4880	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4881	int rc;
4882
4883	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4884	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4885	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4886	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4887	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4888
4889	PGMR pGMR;
4890	uint32_t cbGmr; /* The GMR size in bytes. */
4891	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4892	{
4893	pGMR = NULL;
4894	cbGmr = pThis->vram_size;
4895	}
4896	else
4897	{
4898	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4899	RT_UNTRUSTED_VALIDATED_FENCE();
4900	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4901	cbGmr = pGMR->cbTotal;
4902	}
4903
4904	/*
4905	* GMR
4906	*/
4907	/* Calculate GMR offset of the data to be copied. */
4908	AssertMsgReturn(gstPtr.offset < cbGmr,
4909	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4910	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4911	VERR_INVALID_PARAMETER);
4912	RT_UNTRUSTED_VALIDATED_FENCE();
4913	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4914	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4915	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4916	VERR_INVALID_PARAMETER);
4917	RT_UNTRUSTED_VALIDATED_FENCE();
4918	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4919
4920	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4921	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4922	AssertMsgReturn(cbGmrScanline != 0,
4923	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4924	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4925	VERR_INVALID_PARAMETER);
4926	RT_UNTRUSTED_VALIDATED_FENCE();
4927	AssertMsgReturn(cbWidth <= cbGmrScanline,
4928	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4929	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4930	VERR_INVALID_PARAMETER);
4931	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4932	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4933	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4934	VERR_INVALID_PARAMETER);
4935	RT_UNTRUSTED_VALIDATED_FENCE();
4936
4937	/* How many bytes are available for the data in the GMR. */
4938	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4939
4940	/* How many scanlines would fit into the available data. */
4941	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4942	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4943	if (cbWidth <= cbGmrLastScanline)
4944	++cGmrScanlines;
4945
4946	if (cHeight > cGmrScanlines)
4947	cHeight = cGmrScanlines;
4948
4949	AssertMsgReturn(cHeight > 0,
4950	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4951	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4952	VERR_INVALID_PARAMETER);
4953	RT_UNTRUSTED_VALIDATED_FENCE();
4954
4955	/*
4956	* Host buffer.
4957	*/
4958	AssertMsgReturn(offHst < cbHstBuf,
4959	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4960	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4961	VERR_INVALID_PARAMETER);
4962
4963	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4964	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4965	AssertMsgReturn(cbHstScanline != 0,
4966	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4967	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4968	VERR_INVALID_PARAMETER);
4969	AssertMsgReturn(cbWidth <= cbHstScanline,
4970	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4971	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4972	VERR_INVALID_PARAMETER);
4973	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4974	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4975	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4976	VERR_INVALID_PARAMETER);
4977
4978	/* How many bytes are available for the data in the buffer. */
4979	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4980
4981	/* How many scanlines would fit into the available data. */
4982	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4983	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4984	if (cbWidth <= cbHstLastScanline)
4985	++cHstScanlines;
4986
4987	if (cHeight > cHstScanlines)
4988	cHeight = cHstScanlines;
4989
4990	AssertMsgReturn(cHeight > 0,
4991	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4992	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4993	VERR_INVALID_PARAMETER);
4994
4995	uint8_t *pbHst = pbHstBuf + offHst;
4996
4997	/* Shortcut for the framebuffer. */
4998	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4999	{
5000	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5001
5002	uint8_t const *pbSrc;
5003	int32_t cbSrcPitch;
5004	uint8_t *pbDst;
5005	int32_t cbDstPitch;
5006
5007	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5008	{
5009	pbSrc = pbHst;
5010	cbSrcPitch = cbHstPitch;
5011	pbDst = pbGst;
5012	cbDstPitch = cbGstPitch;
5013	}
5014	else
5015	{
5016	pbSrc = pbGst;
5017	cbSrcPitch = cbGstPitch;
5018	pbDst = pbHst;
5019	cbDstPitch = cbHstPitch;
5020	}
5021
5022	if ( cbWidth == (uint32_t)cbGstPitch
5023	&& cbGstPitch == cbHstPitch)
5024	{
5025	/* Entire scanlines, positive pitch. */
5026	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5027	}
5028	else
5029	{
5030	for (uint32_t i = 0; i < cHeight; ++i)
5031	{
5032	memcpy(pbDst, pbSrc, cbWidth);
5033
5034	pbDst += cbDstPitch;
5035	pbSrc += cbSrcPitch;
5036	}
5037	}
5038	return VINF_SUCCESS;
5039	}
5040
5041	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5042	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5043
5044	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5045	uint32_t iDesc = 0; /* Index in the descriptor array. */
5046	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5047	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5048	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5049	for (uint32_t i = 0; i < cHeight; ++i)
5050	{
5051	uint32_t cbCurrentWidth = cbWidth;
5052	uint32_t offGmrCurrent = offGmrScanline;
5053	uint8_t *pbCurrentHost = pbHstScanline;
5054
5055	/* Find the right descriptor */
5056	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5057	{
5058	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5059	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5060	++iDesc;
5061	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5062	}
5063
5064	while (cbCurrentWidth)
5065	{
5066	uint32_t cbToCopy;
5067
5068	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5069	{
5070	cbToCopy = cbCurrentWidth;
5071	}
5072	else
5073	{
5074	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5075	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5076	}
5077
5078	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5079
5080	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5081
5082	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5083	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5084	else
5085	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5086	AssertRCBreak(rc);
5087
5088	cbCurrentWidth -= cbToCopy;
5089	offGmrCurrent += cbToCopy;
5090	pbCurrentHost += cbToCopy;
5091
5092	/* Go to the next descriptor if there's anything left. */
5093	if (cbCurrentWidth)
5094	{
5095	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5096	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5097	++iDesc;
5098	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5099	}
5100	}
5101
5102	offGmrScanline += cbGstPitch;
5103	pbHstScanline += cbHstPitch;
5104	}
5105
5106	return VINF_SUCCESS;
5107	}
5108
5109
5110	/**
5111	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5112	*
5113	* @param pSizeSrc Source surface dimensions.
5114	* @param pSizeDest Destination surface dimensions.
5115	* @param pBox Coordinates to be clipped.
5116	*/
5117	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5118	{
5119	/* Src x, w */
5120	if (pBox->srcx > pSizeSrc->width)
5121	pBox->srcx = pSizeSrc->width;
5122	if (pBox->w > pSizeSrc->width - pBox->srcx)
5123	pBox->w = pSizeSrc->width - pBox->srcx;
5124
5125	/* Src y, h */
5126	if (pBox->srcy > pSizeSrc->height)
5127	pBox->srcy = pSizeSrc->height;
5128	if (pBox->h > pSizeSrc->height - pBox->srcy)
5129	pBox->h = pSizeSrc->height - pBox->srcy;
5130
5131	/* Src z, d */
5132	if (pBox->srcz > pSizeSrc->depth)
5133	pBox->srcz = pSizeSrc->depth;
5134	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5135	pBox->d = pSizeSrc->depth - pBox->srcz;
5136
5137	/* Dest x, w */
5138	if (pBox->x > pSizeDest->width)
5139	pBox->x = pSizeDest->width;
5140	if (pBox->w > pSizeDest->width - pBox->x)
5141	pBox->w = pSizeDest->width - pBox->x;
5142
5143	/* Dest y, h */
5144	if (pBox->y > pSizeDest->height)
5145	pBox->y = pSizeDest->height;
5146	if (pBox->h > pSizeDest->height - pBox->y)
5147	pBox->h = pSizeDest->height - pBox->y;
5148
5149	/* Dest z, d */
5150	if (pBox->z > pSizeDest->depth)
5151	pBox->z = pSizeDest->depth;
5152	if (pBox->d > pSizeDest->depth - pBox->z)
5153	pBox->d = pSizeDest->depth - pBox->z;
5154	}
5155
5156	/**
5157	* Unsigned coordinates in pBox. Clip to [0; pSize).
5158	*
5159	* @param pSize Source surface dimensions.
5160	* @param pBox Coordinates to be clipped.
5161	*/
5162	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5163	{
5164	/* x, w */
5165	if (pBox->x > pSize->width)
5166	pBox->x = pSize->width;
5167	if (pBox->w > pSize->width - pBox->x)
5168	pBox->w = pSize->width - pBox->x;
5169
5170	/* y, h */
5171	if (pBox->y > pSize->height)
5172	pBox->y = pSize->height;
5173	if (pBox->h > pSize->height - pBox->y)
5174	pBox->h = pSize->height - pBox->y;
5175
5176	/* z, d */
5177	if (pBox->z > pSize->depth)
5178	pBox->z = pSize->depth;
5179	if (pBox->d > pSize->depth - pBox->z)
5180	pBox->d = pSize->depth - pBox->z;
5181	}
5182
5183	/**
5184	* Clip.
5185	*
5186	* @param pBound Bounding rectangle.
5187	* @param pRect Rectangle to be clipped.
5188	*/
5189	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5190	{
5191	int32_t left;
5192	int32_t top;
5193	int32_t right;
5194	int32_t bottom;
5195
5196	/* Right order. */
5197	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5198	if (pRect->left < pRect->right)
5199	{
5200	left = pRect->left;
5201	right = pRect->right;
5202	}
5203	else
5204	{
5205	left = pRect->right;
5206	right = pRect->left;
5207	}
5208	if (pRect->top < pRect->bottom)
5209	{
5210	top = pRect->top;
5211	bottom = pRect->bottom;
5212	}
5213	else
5214	{
5215	top = pRect->bottom;
5216	bottom = pRect->top;
5217	}
5218
5219	if (left < pBound->left)
5220	left = pBound->left;
5221	if (right < pBound->left)
5222	right = pBound->left;
5223
5224	if (left > pBound->right)
5225	left = pBound->right;
5226	if (right > pBound->right)
5227	right = pBound->right;
5228
5229	if (top < pBound->top)
5230	top = pBound->top;
5231	if (bottom < pBound->top)
5232	bottom = pBound->top;
5233
5234	if (top > pBound->bottom)
5235	top = pBound->bottom;
5236	if (bottom > pBound->bottom)
5237	bottom = pBound->bottom;
5238
5239	pRect->left = left;
5240	pRect->right = right;
5241	pRect->top = top;
5242	pRect->bottom = bottom;
5243	}
5244
5245	/**
5246	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5247	* Unblock the FIFO I/O thread so it can respond to a state change.}
5248	*/
5249	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5250	{
5251	RT_NOREF(pDevIns);
5252	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5253	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5254	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5255	}
5256
5257	/**
5258	* Enables or disables dirty page tracking for the framebuffer
5259	*
5260	* @param pDevIns The device instance.
5261	* @param pThis The shared VGA/VMSVGA instance data.
5262	* @param fTraces Enable/disable traces
5263	*/
5264	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5265	{
5266	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5267	&& !fTraces)
5268	{
5269	//Assert(pThis->svga.fTraces);
5270	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5271	return;
5272	}
5273
5274	pThis->svga.fTraces = fTraces;
5275	if (pThis->svga.fTraces)
5276	{
5277	unsigned cbFrameBuffer = pThis->vram_size;
5278
5279	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5280	/** @todo How does this work with screens? */
5281	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5282	{
5283	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5284	Assert(pThis->svga.cbScanline);
5285	# endif
5286	/* Hardware enabled; return real framebuffer size .*/
5287	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5288	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5289	}
5290
5291	if (!pThis->svga.fVRAMTracking)
5292	{
5293	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5294	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5295	pThis->svga.fVRAMTracking = true;
5296	}
5297	}
5298	else
5299	{
5300	if (pThis->svga.fVRAMTracking)
5301	{
5302	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5303	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5304	pThis->svga.fVRAMTracking = false;
5305	}
5306	}
5307	}
5308
5309	/**
5310	* @callback_method_impl{FNPCIIOREGIONMAP}
5311	*/
5312	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5313	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5314	{
5315	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5316	int rc;
5317	RT_NOREF(pPciDev);
5318	Assert(pPciDev == pDevIns->apPciDevs[0]);
5319
5320	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5321	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5322	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5323	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5324	, VERR_INTERNAL_ERROR);
5325	if (GCPhysAddress != NIL_RTGCPHYS)
5326	{
5327	/*
5328	* Mapping the FIFO RAM.
5329	*/
5330	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5331	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5332	AssertRC(rc);
5333
5334	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5335	if (RT_SUCCESS(rc))
5336	{
5337	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5338	# ifdef DEBUG_FIFO_ACCESS
5339	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5340	# else
5341	GCPhysAddress + PAGE_SIZE - 1,
5342	# endif
5343	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5344	"VMSVGA FIFO");
5345	AssertRC(rc);
5346	}
5347	# endif
5348	if (RT_SUCCESS(rc))
5349	{
5350	pThis->svga.GCPhysFIFO = GCPhysAddress;
5351	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5352	}
5353	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5354	}
5355	else
5356	{
5357	Assert(pThis->svga.GCPhysFIFO);
5358	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5359	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5360	AssertRC(rc);
5361	# else
5362	rc = VINF_SUCCESS;
5363	# endif
5364	pThis->svga.GCPhysFIFO = 0;
5365	}
5366	return rc;
5367	}
5368
5369	# ifdef VBOX_WITH_VMSVGA3D
5370
5371	/**
5372	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5373	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5374	*
5375	* @param pDevIns The device instance.
5376	* @param pThis The The shared VGA/VMSVGA instance data.
5377	* @param pThisCC The VGA/VMSVGA state for ring-3.
5378	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5379	* UINT32_MAX is used, all surfaces are processed.
5380	*/
5381	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5382	{
5383	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5384	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5385	}
5386
5387
5388	/**
5389	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5390	*/
5391	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5392	{
5393	/* There might be a specific surface ID at the start of the
5394	arguments, if not show all surfaces. */
5395	uint32_t sid = UINT32_MAX;
5396	if (pszArgs)
5397	pszArgs = RTStrStripL(pszArgs);
5398	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5399	sid = RTStrToUInt32(pszArgs);
5400
5401	/* Verbose or terse display, we default to verbose. */
5402	bool fVerbose = true;
5403	if (RTStrIStr(pszArgs, "terse"))
5404	fVerbose = false;
5405
5406	/* The size of the ascii art (x direction, y is 3/4 of x). */
5407	uint32_t cxAscii = 80;
5408	if (RTStrIStr(pszArgs, "gigantic"))
5409	cxAscii = 300;
5410	else if (RTStrIStr(pszArgs, "huge"))
5411	cxAscii = 180;
5412	else if (RTStrIStr(pszArgs, "big"))
5413	cxAscii = 132;
5414	else if (RTStrIStr(pszArgs, "normal"))
5415	cxAscii = 80;
5416	else if (RTStrIStr(pszArgs, "medium"))
5417	cxAscii = 64;
5418	else if (RTStrIStr(pszArgs, "small"))
5419	cxAscii = 48;
5420	else if (RTStrIStr(pszArgs, "tiny"))
5421	cxAscii = 24;
5422
5423	/* Y invert the image when producing the ASCII art. */
5424	bool fInvY = false;
5425	if (RTStrIStr(pszArgs, "invy"))
5426	fInvY = true;
5427
5428	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5429	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5430	}
5431
5432
5433	/**
5434	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5435	*/
5436	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5437	{
5438	/* pszArg = "sid[>dir]"
5439	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5440	*/
5441	char *pszBitmapPath = NULL;
5442	uint32_t sid = UINT32_MAX;
5443	if (pszArgs)
5444	pszArgs = RTStrStripL(pszArgs);
5445	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5446	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5447	if ( pszBitmapPath
5448	&& *pszBitmapPath == '>')
5449	++pszBitmapPath;
5450
5451	const bool fVerbose = true;
5452	const uint32_t cxAscii = 0; /* No ASCII */
5453	const bool fInvY = false; /* Do not invert. */
5454	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5455	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5456	}
5457
5458
5459	/**
5460	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5461	*/
5462	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5463	{
5464	/* There might be a specific surface ID at the start of the
5465	arguments, if not show all contexts. */
5466	uint32_t sid = UINT32_MAX;
5467	if (pszArgs)
5468	pszArgs = RTStrStripL(pszArgs);
5469	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5470	sid = RTStrToUInt32(pszArgs);
5471
5472	/* Verbose or terse display, we default to verbose. */
5473	bool fVerbose = true;
5474	if (RTStrIStr(pszArgs, "terse"))
5475	fVerbose = false;
5476
5477	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5478	}
5479
5480	# endif /* VBOX_WITH_VMSVGA3D */
5481
5482	/**
5483	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5484	*/
5485	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5486	{
5487	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5488	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5489	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5490	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5491	RT_NOREF(pszArgs);
5492
5493	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5494	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5495	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5496	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5497	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5498	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5499	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5500	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5501	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5502	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5503	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5504	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5505	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5506	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5507	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5508	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5509	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5510	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5511	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5512	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5513	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5514	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5515	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5516	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5517	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5518
5519	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5520	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5521	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5522	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5523
5524	# ifdef VBOX_WITH_VMSVGA3D
5525	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5526	# endif
5527	if (pThisCC->pDrv)
5528	{
5529	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5530	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5531	}
5532	}
5533
5534	/**
5535	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5536	*/
5537	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5538	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5539	{
5540	RT_NOREF(uPass);
5541
5542	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5543	int rc;
5544
5545	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5546	{
5547	uint32_t cScreens = 0;
5548	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5549	AssertRCReturn(rc, rc);
5550	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5551	("cScreens=%#x\n", cScreens),
5552	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5553
5554	for (uint32_t i = 0; i < cScreens; ++i)
5555	{
5556	VMSVGASCREENOBJECT screen;
5557	RT_ZERO(screen);
5558
5559	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5560	AssertLogRelRCReturn(rc, rc);
5561
5562	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5563	{
5564	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5565	*pScreen = screen;
5566	pScreen->fModified = true;
5567	}
5568	else
5569	{
5570	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5571	}
5572	}
5573	}
5574	else
5575	{
5576	/* Try to setup at least the first screen. */
5577	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5578	pScreen->fDefined = true;
5579	pScreen->fModified = true;
5580	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5581	pScreen->idScreen = 0;
5582	pScreen->xOrigin = 0;
5583	pScreen->yOrigin = 0;
5584	pScreen->offVRAM = pThis->svga.uScreenOffset;
5585	pScreen->cbPitch = pThis->svga.cbScanline;
5586	pScreen->cWidth = pThis->svga.uWidth;
5587	pScreen->cHeight = pThis->svga.uHeight;
5588	pScreen->cBpp = pThis->svga.uBpp;
5589	}
5590
5591	return VINF_SUCCESS;
5592	}
5593
5594	/**
5595	* @copydoc FNSSMDEVLOADEXEC
5596	*/
5597	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5598	{
5599	RT_NOREF(uPass);
5600	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5601	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5602	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5603	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5604	int rc;
5605
5606	/* Load our part of the VGAState */
5607	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5608	AssertRCReturn(rc, rc);
5609
5610	/* Load the VGA framebuffer. */
5611	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5612	uint32_t cbVgaFramebuffer = _32K;
5613	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5614	{
5615	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5616	AssertRCReturn(rc, rc);
5617	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5618	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5619	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5620	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5621	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5622	}
5623	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5624	AssertRCReturn(rc, rc);
5625	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5626	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5627	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5628	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5629
5630	/* Load the VMSVGA state. */
5631	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5632	AssertRCReturn(rc, rc);
5633
5634	/* Load the active cursor bitmaps. */
5635	if (pSVGAState->Cursor.fActive)
5636	{
5637	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5638	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5639
5640	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5641	AssertRCReturn(rc, rc);
5642	}
5643
5644	/* Load the GMR state. */
5645	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5646	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5647	{
5648	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5649	AssertRCReturn(rc, rc);
5650	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5651	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5652	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5653	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5654	}
5655
5656	if (pThis->svga.cGMR != cGMR)
5657	{
5658	/* Reallocate GMR array. */
5659	Assert(pSVGAState->paGMR != NULL);
5660	RTMemFree(pSVGAState->paGMR);
5661	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5662	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5663	pThis->svga.cGMR = cGMR;
5664	}
5665
5666	for (uint32_t i = 0; i < cGMR; ++i)
5667	{
5668	PGMR pGMR = &pSVGAState->paGMR[i];
5669
5670	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5671	AssertRCReturn(rc, rc);
5672
5673	if (pGMR->numDescriptors)
5674	{
5675	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5676	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5677	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5678
5679	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5680	{
5681	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5682	AssertRCReturn(rc, rc);
5683	}
5684	}
5685	}
5686
5687	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5688	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5689	# endif
5690
5691	VMSVGA_STATE_LOAD LoadState;
5692	LoadState.pSSM = pSSM;
5693	LoadState.uVersion = uVersion;
5694	LoadState.uPass = uPass;
5695	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5696	AssertLogRelRCReturn(rc, rc);
5697
5698	return VINF_SUCCESS;
5699	}
5700
5701	/**
5702	* Reinit the video mode after the state has been loaded.
5703	*/
5704	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5705	{
5706	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5707	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5708	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5709
5710	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5711
5712	/* Set the active cursor. */
5713	if (pSVGAState->Cursor.fActive)
5714	{
5715	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5716	true /fVisible/,
5717	true /fAlpha/,
5718	pSVGAState->Cursor.xHotspot,
5719	pSVGAState->Cursor.yHotspot,
5720	pSVGAState->Cursor.width,
5721	pSVGAState->Cursor.height,
5722	pSVGAState->Cursor.pData);
5723	AssertRC(rc);
5724	}
5725	return VINF_SUCCESS;
5726	}
5727
5728	/**
5729	* Portion of SVGA state which must be saved in the FIFO thread.
5730	*/
5731	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5732	{
5733	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5734	int rc;
5735
5736	/* Save the screen objects. */
5737	/* Count defined screen object. */
5738	uint32_t cScreens = 0;
5739	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5740	{
5741	if (pSVGAState->aScreens[i].fDefined)
5742	++cScreens;
5743	}
5744
5745	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5746	AssertLogRelRCReturn(rc, rc);
5747
5748	for (uint32_t i = 0; i < cScreens; ++i)
5749	{
5750	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5751
5752	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5753	AssertLogRelRCReturn(rc, rc);
5754	}
5755	return VINF_SUCCESS;
5756	}
5757
5758	/**
5759	* @copydoc FNSSMDEVSAVEEXEC
5760	*/
5761	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5762	{
5763	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5764	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5765	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5766	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5767	int rc;
5768
5769	/* Save our part of the VGAState */
5770	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5771	AssertLogRelRCReturn(rc, rc);
5772
5773	/* Save the framebuffer backup. */
5774	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5775	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5776	AssertLogRelRCReturn(rc, rc);
5777
5778	/* Save the VMSVGA state. */
5779	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5780	AssertLogRelRCReturn(rc, rc);
5781
5782	/* Save the active cursor bitmaps. */
5783	if (pSVGAState->Cursor.fActive)
5784	{
5785	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5786	AssertLogRelRCReturn(rc, rc);
5787	}
5788
5789	/* Save the GMR state */
5790	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5791	AssertLogRelRCReturn(rc, rc);
5792	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5793	{
5794	PGMR pGMR = &pSVGAState->paGMR[i];
5795
5796	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5797	AssertLogRelRCReturn(rc, rc);
5798
5799	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5800	{
5801	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5802	AssertLogRelRCReturn(rc, rc);
5803	}
5804	}
5805
5806	/*
5807	* Must save some state (3D in particular) in the FIFO thread.
5808	*/
5809	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5810	AssertLogRelRCReturn(rc, rc);
5811
5812	return VINF_SUCCESS;
5813	}
5814
5815	/**
5816	* Destructor for PVMSVGAR3STATE structure.
5817	*
5818	* @param pThis The shared VGA/VMSVGA instance data.
5819	* @param pSVGAState Pointer to the structure. It is not deallocated.
5820	*/
5821	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5822	{
5823	# ifndef VMSVGA_USE_EMT_HALT_CODE
5824	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5825	{
5826	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5827	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5828	}
5829	# endif
5830
5831	if (pSVGAState->Cursor.fActive)
5832	{
5833	RTMemFree(pSVGAState->Cursor.pData);
5834	pSVGAState->Cursor.pData = NULL;
5835	pSVGAState->Cursor.fActive = false;
5836	}
5837
5838	if (pSVGAState->paGMR)
5839	{
5840	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5841	if (pSVGAState->paGMR[i].paDesc)
5842	RTMemFree(pSVGAState->paGMR[i].paDesc);
5843
5844	RTMemFree(pSVGAState->paGMR);
5845	pSVGAState->paGMR = NULL;
5846	}
5847	}
5848
5849	/**
5850	* Constructor for PVMSVGAR3STATE structure.
5851	*
5852	* @returns VBox status code.
5853	* @param pThis The shared VGA/VMSVGA instance data.
5854	* @param pSVGAState Pointer to the structure. It is already allocated.
5855	*/
5856	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5857	{
5858	int rc = VINF_SUCCESS;
5859	RT_ZERO(*pSVGAState);
5860
5861	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5862	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5863
5864	# ifndef VMSVGA_USE_EMT_HALT_CODE
5865	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5866	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5867	AssertRCReturn(rc, rc);
5868	# endif
5869
5870	return rc;
5871	}
5872
5873	/**
5874	* Initializes the host capabilities: registers and FIFO.
5875	*
5876	* @returns VBox status code.
5877	* @param pThis The shared VGA/VMSVGA instance data.
5878	* @param pThisCC The VGA/VMSVGA state for ring-3.
5879	*/
5880	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5881	{
5882	/* Register caps. */
5883	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5884	\| SVGA_CAP_GMR2
5885	\| SVGA_CAP_CURSOR
5886	\| SVGA_CAP_CURSOR_BYPASS_2
5887	\| SVGA_CAP_EXTENDED_FIFO
5888	\| SVGA_CAP_IRQMASK
5889	\| SVGA_CAP_PITCHLOCK
5890	\| SVGA_CAP_TRACES
5891	\| SVGA_CAP_SCREEN_OBJECT_2
5892	\| SVGA_CAP_ALPHA_CURSOR;
5893	# ifdef VBOX_WITH_VMSVGA3D
5894	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5895	# endif
5896
5897	/* Clear the FIFO. */
5898	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5899
5900	/* Setup FIFO capabilities. */
5901	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5902	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5903	\| SVGA_FIFO_CAP_GMR2
5904	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5905	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5906	\| SVGA_FIFO_CAP_RESERVE
5907	\| SVGA_FIFO_CAP_PITCHLOCK;
5908
5909	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5910	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5911	}
5912
5913	# ifdef VBOX_WITH_VMSVGA3D
5914	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5915	static const char * const g_apszVmSvgaDevCapNames[] =
5916	{
5917	"x3D", /* = 0 */
5918	"xMAX_LIGHTS",
5919	"xMAX_TEXTURES",
5920	"xMAX_CLIP_PLANES",
5921	"xVERTEX_SHADER_VERSION",
5922	"xVERTEX_SHADER",
5923	"xFRAGMENT_SHADER_VERSION",
5924	"xFRAGMENT_SHADER",
5925	"xMAX_RENDER_TARGETS",
5926	"xS23E8_TEXTURES",
5927	"xS10E5_TEXTURES",
5928	"xMAX_FIXED_VERTEXBLEND",
5929	"xD16_BUFFER_FORMAT",
5930	"xD24S8_BUFFER_FORMAT",
5931	"xD24X8_BUFFER_FORMAT",
5932	"xQUERY_TYPES",
5933	"xTEXTURE_GRADIENT_SAMPLING",
5934	"rMAX_POINT_SIZE",
5935	"xMAX_SHADER_TEXTURES",
5936	"xMAX_TEXTURE_WIDTH",
5937	"xMAX_TEXTURE_HEIGHT",
5938	"xMAX_VOLUME_EXTENT",
5939	"xMAX_TEXTURE_REPEAT",
5940	"xMAX_TEXTURE_ASPECT_RATIO",
5941	"xMAX_TEXTURE_ANISOTROPY",
5942	"xMAX_PRIMITIVE_COUNT",
5943	"xMAX_VERTEX_INDEX",
5944	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5945	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5946	"xMAX_VERTEX_SHADER_TEMPS",
5947	"xMAX_FRAGMENT_SHADER_TEMPS",
5948	"xTEXTURE_OPS",
5949	"xSURFACEFMT_X8R8G8B8",
5950	"xSURFACEFMT_A8R8G8B8",
5951	"xSURFACEFMT_A2R10G10B10",
5952	"xSURFACEFMT_X1R5G5B5",
5953	"xSURFACEFMT_A1R5G5B5",
5954	"xSURFACEFMT_A4R4G4B4",
5955	"xSURFACEFMT_R5G6B5",
5956	"xSURFACEFMT_LUMINANCE16",
5957	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5958	"xSURFACEFMT_ALPHA8",
5959	"xSURFACEFMT_LUMINANCE8",
5960	"xSURFACEFMT_Z_D16",
5961	"xSURFACEFMT_Z_D24S8",
5962	"xSURFACEFMT_Z_D24X8",
5963	"xSURFACEFMT_DXT1",
5964	"xSURFACEFMT_DXT2",
5965	"xSURFACEFMT_DXT3",
5966	"xSURFACEFMT_DXT4",
5967	"xSURFACEFMT_DXT5",
5968	"xSURFACEFMT_BUMPX8L8V8U8",
5969	"xSURFACEFMT_A2W10V10U10",
5970	"xSURFACEFMT_BUMPU8V8",
5971	"xSURFACEFMT_Q8W8V8U8",
5972	"xSURFACEFMT_CxV8U8",
5973	"xSURFACEFMT_R_S10E5",
5974	"xSURFACEFMT_R_S23E8",
5975	"xSURFACEFMT_RG_S10E5",
5976	"xSURFACEFMT_RG_S23E8",
5977	"xSURFACEFMT_ARGB_S10E5",
5978	"xSURFACEFMT_ARGB_S23E8",
5979	"xMISSING62",
5980	"xMAX_VERTEX_SHADER_TEXTURES",
5981	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5982	"xSURFACEFMT_V16U16",
5983	"xSURFACEFMT_G16R16",
5984	"xSURFACEFMT_A16B16G16R16",
5985	"xSURFACEFMT_UYVY",
5986	"xSURFACEFMT_YUY2",
5987	"xMULTISAMPLE_NONMASKABLESAMPLES",
5988	"xMULTISAMPLE_MASKABLESAMPLES",
5989	"xALPHATOCOVERAGE",
5990	"xSUPERSAMPLE",
5991	"xAUTOGENMIPMAPS",
5992	"xSURFACEFMT_NV12",
5993	"xSURFACEFMT_AYUV",
5994	"xMAX_CONTEXT_IDS",
5995	"xMAX_SURFACE_IDS",
5996	"xSURFACEFMT_Z_DF16",
5997	"xSURFACEFMT_Z_DF24",
5998	"xSURFACEFMT_Z_D24S8_INT",
5999	"xSURFACEFMT_BC4_UNORM",
6000	"xSURFACEFMT_BC5_UNORM", /* 83 */
6001	};
6002
6003	/**
6004	* Initializes the host 3D capabilities in FIFO.
6005	*
6006	* @returns VBox status code.
6007	* @param pThis The shared VGA/VMSVGA instance data.
6008	* @param pThisCC The VGA/VMSVGA state for ring-3.
6009	*/
6010	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6011	{
6012	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6013	bool fSavedBuffering = RTLogRelSetBuffering(true);
6014	SVGA3dCapsRecord *pCaps;
6015	SVGA3dCapPair *pData;
6016	uint32_t idxCap = 0;
6017
6018	/* 3d hardware version; latest and greatest */
6019	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6020	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6021
6022	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6023	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6024	pData = (SVGA3dCapPair *)&pCaps->data;
6025
6026	/* Fill out all 3d capabilities. */
6027	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6028	{
6029	uint32_t val = 0;
6030
6031	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6032	if (RT_SUCCESS(rc))
6033	{
6034	pData[idxCap][0] = i;
6035	pData[idxCap][1] = val;
6036	idxCap++;
6037	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6038	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6039	else
6040	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6041	&g_apszVmSvgaDevCapNames[i][1]));
6042	}
6043	else
6044	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6045	}
6046	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6047	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6048
6049	/* Mark end of record array. */
6050	pCaps->header.length = 0;
6051
6052	RTLogRelSetBuffering(fSavedBuffering);
6053	}
6054
6055	# endif
6056
6057	/**
6058	* Resets the SVGA hardware state
6059	*
6060	* @returns VBox status code.
6061	* @param pDevIns The device instance.
6062	*/
6063	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6064	{
6065	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6066	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6067	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6068
6069	/* Reset before init? */
6070	if (!pSVGAState)
6071	return VINF_SUCCESS;
6072
6073	Log(("vmsvgaR3Reset\n"));
6074
6075	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6076	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6077	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6078
6079	/* Reset other stuff. */
6080	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6081	RT_ZERO(pThis->svga.au32ScratchRegion);
6082
6083	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6084	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6085
6086	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6087
6088	/* Initialize FIFO and register capabilities. */
6089	vmsvgaR3InitCaps(pThis, pThisCC);
6090
6091	# ifdef VBOX_WITH_VMSVGA3D
6092	if (pThis->svga.f3DEnabled)
6093	vmsvgaR3InitFifo3DCaps(pThisCC);
6094	# endif
6095
6096	/* VRAM tracking is enabled by default during bootup. */
6097	pThis->svga.fVRAMTracking = true;
6098	pThis->svga.fEnabled = false;
6099
6100	/* Invalidate current settings. */
6101	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6102	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6103	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6104	pThis->svga.cbScanline = 0;
6105	pThis->svga.u32PitchLock = 0;
6106
6107	return rc;
6108	}
6109
6110	/**
6111	* Cleans up the SVGA hardware state
6112	*
6113	* @returns VBox status code.
6114	* @param pDevIns The device instance.
6115	*/
6116	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6117	{
6118	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6119	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6120
6121	/*
6122	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6123	*/
6124	if (pThisCC->svga.pFIFOIOThread)
6125	{
6126	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6127	NULL /pvParam/, 30000 /ms/);
6128	AssertLogRelRC(rc);
6129
6130	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6131	AssertLogRelRC(rc);
6132	pThisCC->svga.pFIFOIOThread = NULL;
6133	}
6134
6135	/*
6136	* Destroy the special SVGA state.
6137	*/
6138	if (pThisCC->svga.pSvgaR3State)
6139	{
6140	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6141
6142	RTMemFree(pThisCC->svga.pSvgaR3State);
6143	pThisCC->svga.pSvgaR3State = NULL;
6144	}
6145
6146	/*
6147	* Free our resources residing in the VGA state.
6148	*/
6149	if (pThisCC->svga.pbVgaFrameBufferR3)
6150	{
6151	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6152	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6153	}
6154	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6155	{
6156	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6157	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6158	}
6159	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6160	{
6161	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6162	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6163	}
6164
6165	return VINF_SUCCESS;
6166	}
6167
6168	/**
6169	* Initialize the SVGA hardware state
6170	*
6171	* @returns VBox status code.
6172	* @param pDevIns The device instance.
6173	*/
6174	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6175	{
6176	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6177	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6178	PVMSVGAR3STATE pSVGAState;
6179	int rc;
6180
6181	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6182	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6183
6184	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6185
6186	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6187	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6188	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6189
6190	/* Create event semaphore. */
6191	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6192	AssertRCReturn(rc, rc);
6193
6194	/* Create event semaphore. */
6195	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6196	AssertRCReturn(rc, rc);
6197
6198	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6199	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6200
6201	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6202	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6203
6204	pSVGAState = pThisCC->svga.pSvgaR3State;
6205
6206	/* Initialize FIFO and register capabilities. */
6207	vmsvgaR3InitCaps(pThis, pThisCC);
6208
6209	# ifdef VBOX_WITH_VMSVGA3D
6210	if (pThis->svga.f3DEnabled)
6211	{
6212	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6213	if (RT_FAILURE(rc))
6214	{
6215	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6216	pThis->svga.f3DEnabled = false;
6217	}
6218	}
6219	# endif
6220	/* VRAM tracking is enabled by default during bootup. */
6221	pThis->svga.fVRAMTracking = true;
6222
6223	/* Invalidate current settings. */
6224	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6225	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6226	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6227	pThis->svga.cbScanline = 0;
6228
6229	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6230	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6231	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6232	{
6233	pThis->svga.u32MaxWidth -= 256;
6234	pThis->svga.u32MaxHeight -= 256;
6235	}
6236	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6237
6238	# ifdef DEBUG_GMR_ACCESS
6239	/* Register the GMR access handler type. */
6240	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6241	vmsvgaR3GmrAccessHandler,
6242	NULL, NULL, NULL,
6243	NULL, NULL, NULL,
6244	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6245	AssertRCReturn(rc, rc);
6246	# endif
6247
6248	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6249	/* Register the FIFO access handler type. In addition to
6250	debugging FIFO access, this is also used to facilitate
6251	extended fifo thread sleeps. */
6252	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6253	# ifdef DEBUG_FIFO_ACCESS
6254	PGMPHYSHANDLERKIND_ALL,
6255	# else
6256	PGMPHYSHANDLERKIND_WRITE,
6257	# endif
6258	vmsvgaR3FifoAccessHandler,
6259	NULL, NULL, NULL,
6260	NULL, NULL, NULL,
6261	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6262	AssertRCReturn(rc, rc);
6263	# endif
6264
6265	/* Create the async IO thread. */
6266	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6267	RTTHREADTYPE_IO, "VMSVGA FIFO");
6268	if (RT_FAILURE(rc))
6269	{
6270	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6271	return rc;
6272	}
6273
6274	/*
6275	* Statistics.
6276	*/
6277	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6278	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6279	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6280	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6281	# ifdef VBOX_WITH_STATISTICS
6282	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6283	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6284	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6285	# endif
6286	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6287	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6288	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6289	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6290	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6291	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6292	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6293	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6294	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6295	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6296	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6297	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6298	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6299	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6300	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6301	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6302	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6303	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6304	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6305	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6306	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6307	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6308	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6309	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6310	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6311	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6312	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6313	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6314	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6315	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6316	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6317	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6318	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6319	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6320	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6321	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6322	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6323	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6324	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6325	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6326	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6327	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6328	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6329	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6330	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6331	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6332	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6333	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6334	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6335	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6336	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6337	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6338	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6339	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6340
6341	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6342	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6343	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6344	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6345	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6346	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6347	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6348	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6349	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6350	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6351	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6352	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6353	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6354	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6355	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6356	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6357	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6358	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6359	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6360	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6361	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6362	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6363	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6364	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6365	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6366	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6367	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6368	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6369	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6370	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6371	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6372	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6373
6374	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6375	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6376	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6377	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6378	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6379	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6380	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6381	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6382	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6383	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6384	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6385	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6386	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6387	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6388	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6389	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6390	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6391	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6392	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6393	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6394	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6395	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6396	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6397	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6398	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6399	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6400	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6401	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6402	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6403	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6404	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6405	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6406	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6407	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6408	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6409	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6410	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6411	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6412	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6413	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6414	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6415	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6416	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6417	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6418	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6419	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6420	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6421	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6422	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6423
6424	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6425	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6426	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6427	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6428	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6429	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6430	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6431	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6432	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6433	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6434	# endif
6435	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6436	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6437	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6438	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6439	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6440
6441	# undef REG_CNT
6442	# undef REG_PRF
6443
6444	/*
6445	* Info handlers.
6446	*/
6447	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6448	# ifdef VBOX_WITH_VMSVGA3D
6449	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6450	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6451	"VMSVGA 3d surface details. "
6452	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6453	vmsvgaR3Info3dSurface);
6454	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6455	"VMSVGA 3d surface details and bitmap: "
6456	"sid[>dir]",
6457	vmsvgaR3Info3dSurfaceBmp);
6458	# endif
6459
6460	return VINF_SUCCESS;
6461	}
6462
6463	/**
6464	* Power On notification.
6465	*
6466	* @returns VBox status code.
6467	* @param pDevIns The device instance data.
6468	*
6469	* @remarks Caller enters the device critical section.
6470	*/
6471	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6472	{
6473	# ifdef VBOX_WITH_VMSVGA3D
6474	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6475	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6476	if (pThis->svga.f3DEnabled)
6477	{
6478	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6479
6480	if (RT_SUCCESS(rc))
6481	{
6482	/* Initialize FIFO 3D capabilities. */
6483	vmsvgaR3InitFifo3DCaps(pThisCC);
6484	}
6485	}
6486	# else /* !VBOX_WITH_VMSVGA3D */
6487	RT_NOREF(pDevIns);
6488	# endif /* !VBOX_WITH_VMSVGA3D */
6489	}
6490
6491	#endif /* IN_RING3 */
6492

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