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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82088

Last change on this file since 82088 was 82088, checked in by vboxsync, 5 years ago
DevVGA: Mark functions with R3 where appropriate, adding docs and doing other minor cleaning up. bugref:9218
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 287.0 KB

Line
1	/* $Id: DevVGA-SVGA.cpp 82088 2019-11-21 21:59:57Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
500	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
501	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
502	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
503	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pbVgaFrameBufferR3),
504	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
505	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
508	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
509	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
510	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
511	SSMFIELD_ENTRY( VMSVGAState, fBusy),
512	SSMFIELD_ENTRY( VMSVGAState, fTraces),
513	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
514	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
517	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
518	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
519	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
520	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
521	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFOExtCmdSem),
524	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
527	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
528	SSMFIELD_ENTRY( VMSVGAState, uWidth),
529	SSMFIELD_ENTRY( VMSVGAState, uHeight),
530	SSMFIELD_ENTRY( VMSVGAState, uBpp),
531	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
532	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
533	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
534	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
535	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
536	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
537	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
538	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
540	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
541	SSMFIELD_ENTRY_TERM()
542	};
543
544	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
545	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
546	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM);
547
548	VMSVGASCREENOBJECT *vmsvgaGetScreenObject(PVGASTATE pThis, uint32_t idScreen)
549	{
550	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
551	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
552	&& pSVGAState
553	&& pSVGAState->aScreens[idScreen].fDefined)
554	{
555	return &pSVGAState->aScreens[idScreen];
556	}
557	return NULL;
558	}
559
560	#endif /* IN_RING3 */
561
562	#ifdef LOG_ENABLED
563
564	/**
565	* Index register string name lookup
566	*
567	* @returns Index register string or "UNKNOWN"
568	* @param pThis VMSVGA State
569	* @param idxReg The index register.
570	*/
571	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
572	{
573	switch (idxReg)
574	{
575	case SVGA_REG_ID: return "SVGA_REG_ID";
576	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
577	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
578	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
579	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
580	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
581	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
582	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
583	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
584	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
585	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
586	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
587	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
588	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
589	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
590	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
591	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
592	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
593	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
594	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
595	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
596	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
597	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
598	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
599	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
600	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
601	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
602	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
603	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
604	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
605	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
606	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
607	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
608	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
609	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
610	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
611	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
612	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
613	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
614	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
615	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
616	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
617	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
618	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
619	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
620	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
621	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
622	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
623	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
624	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
625
626	default:
627	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
628	return "SVGA_SCRATCH_BASE reg";
629	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
630	return "SVGA_PALETTE_BASE reg";
631	return "UNKNOWN";
632	}
633	}
634
635	#ifdef IN_RING3
636	/**
637	* FIFO command name lookup
638	*
639	* @returns FIFO command string or "UNKNOWN"
640	* @param u32Cmd FIFO command
641	*/
642	static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
643	{
644	switch (u32Cmd)
645	{
646	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
647	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
648	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
649	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
650	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
651	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
652	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
653	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
654	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
655	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
656	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
657	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
658	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
659	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
660	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
661	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
662	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
663	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
664	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
665	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
666	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
667	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
668	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
669	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
670	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
671	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
672	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
673	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
674	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
675	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
676	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
677	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
678	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
679	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
680	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
681	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
682	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
683	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
684	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
685	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
686	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
687	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
688	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
689	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
690	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
691	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
692	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
693	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
694	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
695	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
696	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
697	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
698	default: return "UNKNOWN";
699	}
700	}
701	# endif /* IN_RING3 */
702
703	#endif /* LOG_ENABLED */
704
705	#ifdef IN_RING3
706	/**
707	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
708	*/
709	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
710	{
711	PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
712
713	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
714	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
715
716	/** @todo Test how it interacts with multiple screen objects. */
717	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, idScreen);
718	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
719	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
720
721	if (x < uWidth)
722	{
723	pThis->svga.viewport.x = x;
724	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
725	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
726	}
727	else
728	{
729	pThis->svga.viewport.x = uWidth;
730	pThis->svga.viewport.cx = 0;
731	pThis->svga.viewport.xRight = uWidth;
732	}
733	if (y < uHeight)
734	{
735	pThis->svga.viewport.y = y;
736	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
737	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
738	pThis->svga.viewport.yHighWC = uHeight - y;
739	}
740	else
741	{
742	pThis->svga.viewport.y = uHeight;
743	pThis->svga.viewport.cy = 0;
744	pThis->svga.viewport.yLowWC = 0;
745	pThis->svga.viewport.yHighWC = 0;
746	}
747
748	# ifdef VBOX_WITH_VMSVGA3D
749	/*
750	* Now inform the 3D backend.
751	*/
752	if (pThis->svga.f3DEnabled)
753	vmsvga3dUpdateHostScreenViewport(pThis, idScreen, &OldViewport);
754	# else
755	RT_NOREF(OldViewport);
756	# endif
757	}
758	#endif /* IN_RING3 */
759
760	/**
761	* Read port register
762	*
763	* @returns VBox status code.
764	* @param pDevIns The device instance.
765	* @param pThis VMSVGA State
766	* @param pu32 Where to store the read value
767	*/
768	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
769	{
770	int rc = VINF_SUCCESS;
771	*pu32 = 0;
772
773	/* Rough index register validation. */
774	uint32_t idxReg = pThis->svga.u32IndexReg;
775	#if !defined(IN_RING3) && defined(VBOX_STRICT)
776	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
777	VINF_IOM_R3_IOPORT_READ);
778	#else
779	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
781	VINF_SUCCESS);
782	#endif
783	RT_UNTRUSTED_VALIDATED_FENCE();
784
785	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
786	if ( idxReg >= SVGA_REG_CAPABILITIES
787	&& pThis->svga.u32SVGAId == SVGA_ID_0)
788	{
789	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
790	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
791	}
792
793	switch (idxReg)
794	{
795	case SVGA_REG_ID:
796	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
797	*pu32 = pThis->svga.u32SVGAId;
798	break;
799
800	case SVGA_REG_ENABLE:
801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
802	*pu32 = pThis->svga.fEnabled;
803	break;
804
805	case SVGA_REG_WIDTH:
806	{
807	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
808	if ( pThis->svga.fEnabled
809	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
810	*pu32 = pThis->svga.uWidth;
811	else
812	{
813	#ifndef IN_RING3
814	rc = VINF_IOM_R3_IOPORT_READ;
815	#else
816	*pu32 = pThis->pDrv->cx;
817	#endif
818	}
819	break;
820	}
821
822	case SVGA_REG_HEIGHT:
823	{
824	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
825	if ( pThis->svga.fEnabled
826	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
827	*pu32 = pThis->svga.uHeight;
828	else
829	{
830	#ifndef IN_RING3
831	rc = VINF_IOM_R3_IOPORT_READ;
832	#else
833	*pu32 = pThis->pDrv->cy;
834	#endif
835	}
836	break;
837	}
838
839	case SVGA_REG_MAX_WIDTH:
840	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
841	*pu32 = pThis->svga.u32MaxWidth;
842	break;
843
844	case SVGA_REG_MAX_HEIGHT:
845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
846	*pu32 = pThis->svga.u32MaxHeight;
847	break;
848
849	case SVGA_REG_DEPTH:
850	/* This returns the color depth of the current mode. */
851	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
852	switch (pThis->svga.uBpp)
853	{
854	case 15:
855	case 16:
856	case 24:
857	*pu32 = pThis->svga.uBpp;
858	break;
859
860	default:
861	case 32:
862	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
863	break;
864	}
865	break;
866
867	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
868	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
869	if ( pThis->svga.fEnabled
870	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
871	*pu32 = pThis->svga.uBpp;
872	else
873	{
874	#ifndef IN_RING3
875	rc = VINF_IOM_R3_IOPORT_READ;
876	#else
877	*pu32 = pThis->pDrv->cBits;
878	#endif
879	}
880	break;
881
882	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
883	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
884	if ( pThis->svga.fEnabled
885	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
886	*pu32 = (pThis->svga.uBpp + 7) & ~7;
887	else
888	{
889	#ifndef IN_RING3
890	rc = VINF_IOM_R3_IOPORT_READ;
891	#else
892	*pu32 = (pThis->pDrv->cBits + 7) & ~7;
893	#endif
894	}
895	break;
896
897	case SVGA_REG_PSEUDOCOLOR:
898	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
899	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
900	break;
901
902	case SVGA_REG_RED_MASK:
903	case SVGA_REG_GREEN_MASK:
904	case SVGA_REG_BLUE_MASK:
905	{
906	uint32_t uBpp;
907
908	if ( pThis->svga.fEnabled
909	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
910	{
911	uBpp = pThis->svga.uBpp;
912	}
913	else
914	{
915	#ifndef IN_RING3
916	rc = VINF_IOM_R3_IOPORT_READ;
917	break;
918	#else
919	uBpp = pThis->pDrv->cBits;
920	#endif
921	}
922	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
923	switch (uBpp)
924	{
925	case 8:
926	u32RedMask = 0x07;
927	u32GreenMask = 0x38;
928	u32BlueMask = 0xc0;
929	break;
930
931	case 15:
932	u32RedMask = 0x0000001f;
933	u32GreenMask = 0x000003e0;
934	u32BlueMask = 0x00007c00;
935	break;
936
937	case 16:
938	u32RedMask = 0x0000001f;
939	u32GreenMask = 0x000007e0;
940	u32BlueMask = 0x0000f800;
941	break;
942
943	case 24:
944	case 32:
945	default:
946	u32RedMask = 0x00ff0000;
947	u32GreenMask = 0x0000ff00;
948	u32BlueMask = 0x000000ff;
949	break;
950	}
951	switch (idxReg)
952	{
953	case SVGA_REG_RED_MASK:
954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
955	*pu32 = u32RedMask;
956	break;
957
958	case SVGA_REG_GREEN_MASK:
959	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
960	*pu32 = u32GreenMask;
961	break;
962
963	case SVGA_REG_BLUE_MASK:
964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
965	*pu32 = u32BlueMask;
966	break;
967	}
968	break;
969	}
970
971	case SVGA_REG_BYTES_PER_LINE:
972	{
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
974	if ( pThis->svga.fEnabled
975	&& pThis->svga.cbScanline)
976	*pu32 = pThis->svga.cbScanline;
977	else
978	{
979	#ifndef IN_RING3
980	rc = VINF_IOM_R3_IOPORT_READ;
981	#else
982	*pu32 = pThis->pDrv->cbScanline;
983	#endif
984	}
985	break;
986	}
987
988	case SVGA_REG_VRAM_SIZE: /* VRAM size */
989	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
990	*pu32 = pThis->vram_size;
991	break;
992
993	case SVGA_REG_FB_START: /* Frame buffer physical address. */
994	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
995	Assert(pThis->GCPhysVRAM <= 0xffffffff);
996	*pu32 = pThis->GCPhysVRAM;
997	break;
998
999	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1001	/* Always zero in our case. */
1002	*pu32 = 0;
1003	break;
1004
1005	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1006	{
1007	#ifndef IN_RING3
1008	rc = VINF_IOM_R3_IOPORT_READ;
1009	#else
1010	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1011
1012	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1013	if ( pThis->svga.fEnabled
1014	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1015	{
1016	/* Hardware enabled; return real framebuffer size .*/
1017	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1018	}
1019	else
1020	pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy pThis->pDrv->cbScanline);
1021
1022	pu32 = RT_MIN(pThis->vram_size, pu32);
1023	Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
1024	#endif
1025	break;
1026	}
1027
1028	case SVGA_REG_CAPABILITIES:
1029	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1030	*pu32 = pThis->svga.u32RegCaps;
1031	break;
1032
1033	case SVGA_REG_MEM_START: /* FIFO start */
1034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1035	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1036	*pu32 = pThis->svga.GCPhysFIFO;
1037	break;
1038
1039	case SVGA_REG_MEM_SIZE: /* FIFO size */
1040	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1041	*pu32 = pThis->svga.cbFIFO;
1042	break;
1043
1044	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1046	*pu32 = pThis->svga.fConfigured;
1047	break;
1048
1049	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1051	*pu32 = 0;
1052	break;
1053
1054	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1055	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1056	if (pThis->svga.fBusy)
1057	{
1058	#ifndef IN_RING3
1059	/* Go to ring-3 and halt the CPU. */
1060	rc = VINF_IOM_R3_IOPORT_READ;
1061	RT_NOREF(pDevIns);
1062	break;
1063	#else
1064	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1065	/* The guest is basically doing a HLT via the device here, but with
1066	a special wake up condition on FIFO completion. */
1067	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1068	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1069	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
1070	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
1071	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1072	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1073	if (pThis->svga.fBusy)
1074	{
1075	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1076	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1077	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1078	}
1079	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1080	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1081	# else
1082
1083	/* Delay the EMT a bit so the FIFO and others can get some work done.
1084	This used to be a crude 50 ms sleep. The current code tries to be
1085	more efficient, but the consept is still very crude. */
1086	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1087	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1088	RTThreadYield();
1089	if (pThis->svga.fBusy)
1090	{
1091	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1092
1093	if (pThis->svga.fBusy && cRefs == 1)
1094	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1095	if (pThis->svga.fBusy)
1096	{
1097	/** @todo If this code is going to stay, we need to call into the halt/wait
1098	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1099	* suffer when the guest is polling on a busy FIFO. */
1100	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
1101	if (cNsMaxWait >= RT_NS_100US)
1102	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1103	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1104	RT_MIN(cNsMaxWait, RT_NS_10MS));
1105	}
1106
1107	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1108	}
1109	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1110	# endif
1111	*pu32 = pThis->svga.fBusy != 0;
1112	#endif
1113	}
1114	else
1115	*pu32 = false;
1116	break;
1117
1118	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1119	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1120	*pu32 = pThis->svga.u32GuestId;
1121	break;
1122
1123	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1125	*pu32 = pThis->svga.cScratchRegion;
1126	break;
1127
1128	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1130	*pu32 = SVGA_FIFO_NUM_REGS;
1131	break;
1132
1133	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1135	*pu32 = pThis->svga.u32PitchLock;
1136	break;
1137
1138	case SVGA_REG_IRQMASK: /* Interrupt mask */
1139	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1140	*pu32 = pThis->svga.u32IrqMask;
1141	break;
1142
1143	/* See "Guest memory regions" below. */
1144	case SVGA_REG_GMR_ID:
1145	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1146	*pu32 = pThis->svga.u32CurrentGMRId;
1147	break;
1148
1149	case SVGA_REG_GMR_DESCRIPTOR:
1150	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1151	/* Write only */
1152	*pu32 = 0;
1153	break;
1154
1155	case SVGA_REG_GMR_MAX_IDS:
1156	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1157	*pu32 = pThis->svga.cGMR;
1158	break;
1159
1160	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1162	*pu32 = VMSVGA_MAX_GMR_PAGES;
1163	break;
1164
1165	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1166	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1167	*pu32 = pThis->svga.fTraces;
1168	break;
1169
1170	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1171	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1172	*pu32 = VMSVGA_MAX_GMR_PAGES;
1173	break;
1174
1175	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1177	*pu32 = VMSVGA_SURFACE_SIZE;
1178	break;
1179
1180	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1181	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1182	break;
1183
1184	/* Mouse cursor support. */
1185	case SVGA_REG_CURSOR_ID:
1186	case SVGA_REG_CURSOR_X:
1187	case SVGA_REG_CURSOR_Y:
1188	case SVGA_REG_CURSOR_ON:
1189	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1190	break;
1191
1192	/* Legacy multi-monitor support */
1193	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1195	*pu32 = 1;
1196	break;
1197
1198	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1199	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1200	*pu32 = 0;
1201	break;
1202
1203	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1204	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1205	*pu32 = 0;
1206	break;
1207
1208	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1210	*pu32 = 0;
1211	break;
1212
1213	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1214	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1215	*pu32 = 0;
1216	break;
1217
1218	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1220	*pu32 = pThis->svga.uWidth;
1221	break;
1222
1223	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1225	*pu32 = pThis->svga.uHeight;
1226	break;
1227
1228	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1230	/* We must return something sensible here otherwise the Linux driver
1231	will take a legacy code path without 3d support. This number also
1232	limits how many screens Linux guests will allow. */
1233	*pu32 = pThis->cMonitors;
1234	break;
1235
1236	default:
1237	{
1238	uint32_t offReg;
1239	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1240	{
1241	RT_UNTRUSTED_VALIDATED_FENCE();
1242	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1244	}
1245	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1246	{
1247	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1249	RT_UNTRUSTED_VALIDATED_FENCE();
1250	uint32_t u32 = pThis->last_palette[offReg / 3];
1251	switch (offReg % 3)
1252	{
1253	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1254	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1255	case 2: pu32 = u32 & 0xff; break; / blue */
1256	}
1257	}
1258	else
1259	{
1260	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1261	rc = VINF_IOM_R3_IOPORT_READ;
1262	#else
1263	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1264
1265	/* Do not assert. The guest might be reading all registers. */
1266	LogFunc(("Unknown reg=%#x\n", idxReg));
1267	#endif
1268	}
1269	break;
1270	}
1271	}
1272	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1273	return rc;
1274	}
1275
1276	#ifdef IN_RING3
1277	/**
1278	* Apply the current resolution settings to change the video mode.
1279	*
1280	* @returns VBox status code.
1281	* @param pThis VMSVGA State
1282	*/
1283	static int vmsvgaChangeMode(PVGASTATE pThis)
1284	{
1285	int rc;
1286
1287	/* Always do changemode on FIFO thread. */
1288	Assert(RTThreadSelf() == pThis->svga.pFIFOIOThread->Thread);
1289
1290	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1291
1292	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1293
1294	if (pThis->svga.fGFBRegisters)
1295	{
1296	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1297	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1298	* deletes all screens other than screen #0, and redefines screen
1299	* #0 according to the specified mode. Drivers that use
1300	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1301	*/
1302
1303	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1304	pScreen->fDefined = true;
1305	pScreen->fModified = true;
1306	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1307	pScreen->idScreen = 0;
1308	pScreen->xOrigin = 0;
1309	pScreen->yOrigin = 0;
1310	pScreen->offVRAM = 0;
1311	pScreen->cbPitch = pThis->svga.cbScanline;
1312	pScreen->cWidth = pThis->svga.uWidth;
1313	pScreen->cHeight = pThis->svga.uHeight;
1314	pScreen->cBpp = pThis->svga.uBpp;
1315
1316	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1317	{
1318	/* Delete screen. */
1319	pScreen = &pSVGAState->aScreens[iScreen];
1320	if (pScreen->fDefined)
1321	{
1322	pScreen->fModified = true;
1323	pScreen->fDefined = false;
1324	}
1325	}
1326	}
1327	else
1328	{
1329	/* "If Screen Objects are supported, they can be used to fully
1330	* replace the functionality provided by the framebuffer registers
1331	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1332	*/
1333	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1334	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1335	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1336	}
1337
1338	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1339	{
1340	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1341	if (!pScreen->fModified)
1342	continue;
1343
1344	pScreen->fModified = false;
1345
1346	VBVAINFOVIEW view;
1347	RT_ZERO(view);
1348	view.u32ViewIndex = pScreen->idScreen;
1349	// view.u32ViewOffset = 0;
1350	view.u32ViewSize = pThis->vram_size;
1351	view.u32MaxScreenSize = pThis->vram_size;
1352
1353	VBVAINFOSCREEN screen;
1354	RT_ZERO(screen);
1355	screen.u32ViewIndex = pScreen->idScreen;
1356
1357	if (pScreen->fDefined)
1358	{
1359	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1360	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1361	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1362	{
1363	Assert(pThis->svga.fGFBRegisters);
1364	continue;
1365	}
1366
1367	screen.i32OriginX = pScreen->xOrigin;
1368	screen.i32OriginY = pScreen->yOrigin;
1369	screen.u32StartOffset = pScreen->offVRAM;
1370	screen.u32LineSize = pScreen->cbPitch;
1371	screen.u32Width = pScreen->cWidth;
1372	screen.u32Height = pScreen->cHeight;
1373	screen.u16BitsPerPixel = pScreen->cBpp;
1374	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1375	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1376	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1377	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1378	}
1379	else
1380	{
1381	/* Screen is destroyed. */
1382	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1383	}
1384
1385	rc = pThis->pDrv->pfnVBVAResize(pThis->pDrv, &view, &screen, pThis->CTX_SUFF(vram_ptr), /fResetInputMapping=/ true);
1386	AssertRC(rc);
1387	}
1388
1389	/* Last stuff. For the VGA device screenshot. */
1390	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1391	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1392	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1393	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1394	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1395
1396	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1397	if ( pThis->svga.viewport.cx == 0
1398	&& pThis->svga.viewport.cy == 0)
1399	{
1400	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1401	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1402	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1403	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1404	pThis->svga.viewport.yLowWC = 0;
1405	}
1406
1407	return VINF_SUCCESS;
1408	}
1409
1410	int vmsvgaUpdateScreen(PVGASTATE pThis, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1411	{
1412	VBVACMDHDR cmd;
1413	cmd.x = (int16_t)(pScreen->xOrigin + x);
1414	cmd.y = (int16_t)(pScreen->yOrigin + y);
1415	cmd.w = (uint16_t)w;
1416	cmd.h = (uint16_t)h;
1417
1418	pThis->pDrv->pfnVBVAUpdateBegin(pThis->pDrv, pScreen->idScreen);
1419	pThis->pDrv->pfnVBVAUpdateProcess(pThis->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1420	pThis->pDrv->pfnVBVAUpdateEnd(pThis->pDrv, pScreen->idScreen,
1421	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1422
1423	return VINF_SUCCESS;
1424	}
1425
1426	#endif /* IN_RING3 */
1427	#if defined(IN_RING0) \|\| defined(IN_RING3)
1428
1429	/**
1430	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1431	*
1432	* @param pThis The VMSVGA state.
1433	* @param fState The busy state.
1434	*/
1435	DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1436	{
1437	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1438
1439	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1440	{
1441	/* Race / unfortunately scheduling. Highly unlikly. */
1442	uint32_t cLoops = 64;
1443	do
1444	{
1445	ASMNopPause();
1446	fState = (pThis->svga.fBusy != 0);
1447	ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1448	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1449	}
1450	}
1451
1452
1453	/**
1454	* Update the scanline pitch in response to the guest changing mode
1455	* width/bpp.
1456	*
1457	* @param pThis VMSVGA State
1458	*/
1459	DECLINLINE(void) vmsvgaUpdatePitch(PVGASTATE pThis)
1460	{
1461	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.CTX_SUFF(pFIFO);
1462	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1463	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1464	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1465
1466	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1467	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1468	* location but it has a different meaning.
1469	*/
1470	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1471	uFifoPitchLock = 0;
1472
1473	/* Sanitize values. */
1474	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1475	uFifoPitchLock = 0;
1476	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1477	uRegPitchLock = 0;
1478
1479	/* Prefer the register value to the FIFO value.*/
1480	if (uRegPitchLock)
1481	pThis->svga.cbScanline = uRegPitchLock;
1482	else if (uFifoPitchLock)
1483	pThis->svga.cbScanline = uFifoPitchLock;
1484	else
1485	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1486
1487	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1488	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1489	}
1490
1491	#endif /* IN_RING0 \|\| IN_RING3 */
1492
1493
1494	/**
1495	* Write port register
1496	*
1497	* @returns Strict VBox status code.
1498	* @param pThis VMSVGA State
1499	* @param u32 Value to write
1500	*/
1501	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32)
1502	{
1503	#ifdef IN_RING3
1504	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1505	#endif
1506	VBOXSTRICTRC rc = VINF_SUCCESS;
1507
1508	/* Rough index register validation. */
1509	uint32_t idxReg = pThis->svga.u32IndexReg;
1510	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1511	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1512	VINF_IOM_R3_IOPORT_WRITE);
1513	#else
1514	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1515	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1516	VINF_SUCCESS);
1517	#endif
1518	RT_UNTRUSTED_VALIDATED_FENCE();
1519
1520	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1521	if ( idxReg >= SVGA_REG_CAPABILITIES
1522	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1523	{
1524	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1525	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1526	}
1527	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1528	/* Check if the guest uses legacy registers. See vmsvgaChangeMode */
1529	switch (idxReg)
1530	{
1531	case SVGA_REG_WIDTH:
1532	case SVGA_REG_HEIGHT:
1533	case SVGA_REG_PITCHLOCK:
1534	case SVGA_REG_BITS_PER_PIXEL:
1535	pThis->svga.fGFBRegisters = true;
1536	break;
1537	default:
1538	break;
1539	}
1540
1541	switch (idxReg)
1542	{
1543	case SVGA_REG_ID:
1544	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1545	if ( u32 == SVGA_ID_0
1546	\|\| u32 == SVGA_ID_1
1547	\|\| u32 == SVGA_ID_2)
1548	pThis->svga.u32SVGAId = u32;
1549	else
1550	PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1551	break;
1552
1553	case SVGA_REG_ENABLE:
1554	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1555	#ifdef IN_RING3
1556	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1557	&& pThis->svga.fEnabled == false)
1558	{
1559	/* Make a backup copy of the first 512kb in order to save font data etc. */
1560	/** @todo should probably swap here, rather than copy + zero */
1561	memcpy(pThis->svga.pbVgaFrameBufferR3, pThis->vram_ptrR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1562	memset(pThis->vram_ptrR3, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1563	}
1564
1565	pThis->svga.fEnabled = u32;
1566	if (pThis->svga.fEnabled)
1567	{
1568	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1569	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1570	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1571	{
1572	/* Keep the current mode. */
1573	pThis->svga.uWidth = pThis->pDrv->cx;
1574	pThis->svga.uHeight = pThis->pDrv->cy;
1575	pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1576	}
1577
1578	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1579	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1580	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1581	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1582	# ifdef LOG_ENABLED
1583	uint32_t *pFIFO = pThis->svga.pFIFOR3;
1584	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1585	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1586	# endif
1587
1588	/* Disable or enable dirty page tracking according to the current fTraces value. */
1589	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1590
1591	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1592	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1593	pThis->pDrv->pfnVBVAEnable(pThis->pDrv, idScreen, NULL /pHostFlags/);
1594	}
1595	else
1596	{
1597	/* Restore the text mode backup. */
1598	memcpy(pThis->vram_ptrR3, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1599
1600	pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1601
1602	/* Enable dirty page tracking again when going into legacy mode. */
1603	vmsvgaSetTraces(pThis, true);
1604
1605	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1606	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1607	pThis->pDrv->pfnVBVADisable(pThis->pDrv, idScreen);
1608
1609	/* Clear the pitch lock. */
1610	pThis->svga.u32PitchLock = 0;
1611	}
1612	#else /* !IN_RING3 */
1613	rc = VINF_IOM_R3_IOPORT_WRITE;
1614	#endif /* !IN_RING3 */
1615	break;
1616
1617	case SVGA_REG_WIDTH:
1618	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1619	if (pThis->svga.uWidth != u32)
1620	{
1621	#if defined(IN_RING3) \|\| defined(IN_RING0)
1622	pThis->svga.uWidth = u32;
1623	vmsvgaUpdatePitch(pThis);
1624	if (pThis->svga.fEnabled)
1625	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1626	#else
1627	rc = VINF_IOM_R3_IOPORT_WRITE;
1628	#endif
1629	}
1630	/* else: nop */
1631	break;
1632
1633	case SVGA_REG_HEIGHT:
1634	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1635	if (pThis->svga.uHeight != u32)
1636	{
1637	pThis->svga.uHeight = u32;
1638	if (pThis->svga.fEnabled)
1639	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1640	}
1641	/* else: nop */
1642	break;
1643
1644	case SVGA_REG_DEPTH:
1645	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1646	/** @todo read-only?? */
1647	break;
1648
1649	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1650	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1651	if (pThis->svga.uBpp != u32)
1652	{
1653	#if defined(IN_RING3) \|\| defined(IN_RING0)
1654	pThis->svga.uBpp = u32;
1655	vmsvgaUpdatePitch(pThis);
1656	if (pThis->svga.fEnabled)
1657	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1658	#else
1659	rc = VINF_IOM_R3_IOPORT_WRITE;
1660	#endif
1661	}
1662	/* else: nop */
1663	break;
1664
1665	case SVGA_REG_PSEUDOCOLOR:
1666	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1667	break;
1668
1669	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1670	#ifdef IN_RING3
1671	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1672	pThis->svga.fConfigured = u32;
1673	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1674	if (!pThis->svga.fConfigured)
1675	pThis->svga.fTraces = true;
1676	vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1677	#else
1678	rc = VINF_IOM_R3_IOPORT_WRITE;
1679	#endif
1680	break;
1681
1682	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1683	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1684	if ( pThis->svga.fEnabled
1685	&& pThis->svga.fConfigured)
1686	{
1687	#if defined(IN_RING3) \|\| defined(IN_RING0)
1688	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1689	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1690	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1691	vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1692
1693	/* Kick the FIFO thread to start processing commands again. */
1694	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1695	#else
1696	rc = VINF_IOM_R3_IOPORT_WRITE;
1697	#endif
1698	}
1699	/* else nothing to do. */
1700	else
1701	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1702
1703	break;
1704
1705	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1706	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1707	break;
1708
1709	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1710	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1711	pThis->svga.u32GuestId = u32;
1712	break;
1713
1714	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1715	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1716	pThis->svga.u32PitchLock = u32;
1717	/* Should this also update the FIFO pitch lock? Unclear. */
1718	break;
1719
1720	case SVGA_REG_IRQMASK: /* Interrupt mask */
1721	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1722	pThis->svga.u32IrqMask = u32;
1723
1724	/* Irq pending after the above change? */
1725	if (pThis->svga.u32IrqStatus & u32)
1726	{
1727	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1728	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1729	}
1730	else
1731	PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1732	break;
1733
1734	/* Mouse cursor support */
1735	case SVGA_REG_CURSOR_ID:
1736	case SVGA_REG_CURSOR_X:
1737	case SVGA_REG_CURSOR_Y:
1738	case SVGA_REG_CURSOR_ON:
1739	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1740	break;
1741
1742	/* Legacy multi-monitor support */
1743	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1744	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1745	break;
1746	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1747	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1748	break;
1749	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1750	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1751	break;
1752	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1753	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1754	break;
1755	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1756	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1757	break;
1758	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1759	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1760	break;
1761	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1762	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1763	break;
1764	#ifdef VBOX_WITH_VMSVGA3D
1765	/* See "Guest memory regions" below. */
1766	case SVGA_REG_GMR_ID:
1767	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1768	pThis->svga.u32CurrentGMRId = u32;
1769	break;
1770
1771	case SVGA_REG_GMR_DESCRIPTOR:
1772	# ifndef IN_RING3
1773	rc = VINF_IOM_R3_IOPORT_WRITE;
1774	break;
1775	# else /* IN_RING3 */
1776	{
1777	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1778
1779	/* Validate current GMR id. */
1780	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1781	AssertBreak(idGMR < pThis->svga.cGMR);
1782	RT_UNTRUSTED_VALIDATED_FENCE();
1783
1784	/* Free the old GMR if present. */
1785	vmsvgaGMRFree(pThis, idGMR);
1786
1787	/* Just undefine the GMR? */
1788	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1789	if (GCPhys == 0)
1790	{
1791	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1792	break;
1793	}
1794
1795
1796	/* Never cross a page boundary automatically. */
1797	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1798	uint32_t cPagesTotal = 0;
1799	uint32_t iDesc = 0;
1800	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1801	uint32_t cLoops = 0;
1802	RTGCPHYS GCPhysBase = GCPhys;
1803	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1804	{
1805	/* Read descriptor. */
1806	SVGAGuestMemDescriptor desc;
1807	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1808	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1809
1810	if (desc.numPages != 0)
1811	{
1812	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1813	cPagesTotal += desc.numPages;
1814	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1815
1816	if ((iDesc & 15) == 0)
1817	{
1818	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1819	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1820	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1821	}
1822
1823	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1824	paDescs[iDesc++].numPages = desc.numPages;
1825
1826	/* Continue with the next descriptor. */
1827	GCPhys += sizeof(desc);
1828	}
1829	else if (desc.ppn == 0)
1830	break; /* terminator */
1831	else /* Pointer to the next physical page of descriptors. */
1832	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1833
1834	cLoops++;
1835	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1836	}
1837
1838	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1839	if (RT_SUCCESS(rc))
1840	{
1841	/* Commit the GMR. */
1842	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1843	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1844	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1845	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1846	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1847	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1848	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1849	}
1850	else
1851	{
1852	RTMemFree(paDescs);
1853	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1854	}
1855	break;
1856	}
1857	# endif /* IN_RING3 */
1858	#endif // VBOX_WITH_VMSVGA3D
1859
1860	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1861	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1862	if (pThis->svga.fTraces == u32)
1863	break; /* nothing to do */
1864
1865	#ifdef IN_RING3
1866	vmsvgaSetTraces(pThis, !!u32);
1867	#else
1868	rc = VINF_IOM_R3_IOPORT_WRITE;
1869	#endif
1870	break;
1871
1872	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1873	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1874	break;
1875
1876	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1877	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1878	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1879	break;
1880
1881	case SVGA_REG_FB_START:
1882	case SVGA_REG_MEM_START:
1883	case SVGA_REG_HOST_BITS_PER_PIXEL:
1884	case SVGA_REG_MAX_WIDTH:
1885	case SVGA_REG_MAX_HEIGHT:
1886	case SVGA_REG_VRAM_SIZE:
1887	case SVGA_REG_FB_SIZE:
1888	case SVGA_REG_CAPABILITIES:
1889	case SVGA_REG_MEM_SIZE:
1890	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1891	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1892	case SVGA_REG_BYTES_PER_LINE:
1893	case SVGA_REG_FB_OFFSET:
1894	case SVGA_REG_RED_MASK:
1895	case SVGA_REG_GREEN_MASK:
1896	case SVGA_REG_BLUE_MASK:
1897	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1898	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1899	case SVGA_REG_GMR_MAX_IDS:
1900	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1901	/* Read only - ignore. */
1902	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1903	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1904	break;
1905
1906	default:
1907	{
1908	uint32_t offReg;
1909	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1910	{
1911	RT_UNTRUSTED_VALIDATED_FENCE();
1912	pThis->svga.au32ScratchRegion[offReg] = u32;
1913	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1914	}
1915	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1916	{
1917	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1918	Btw, see rgb_to_pixel32. */
1919	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1920	u32 &= 0xff;
1921	RT_UNTRUSTED_VALIDATED_FENCE();
1922	uint32_t uRgb = pThis->last_palette[offReg / 3];
1923	switch (offReg % 3)
1924	{
1925	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1926	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1927	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1928	}
1929	pThis->last_palette[offReg / 3] = uRgb;
1930	}
1931	else
1932	{
1933	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1934	rc = VINF_IOM_R3_IOPORT_WRITE;
1935	#else
1936	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1937	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1938	#endif
1939	}
1940	break;
1941	}
1942	}
1943	return rc;
1944	}
1945
1946	/**
1947	* @callback_method_impl{FNIOMIOPORTNEWIN}
1948	*/
1949	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1950	{
1951	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1952	RT_NOREF_PV(pvUser);
1953
1954	/* Only dword accesses. */
1955	if (cb == 4)
1956	{
1957	switch (offPort)
1958	{
1959	case SVGA_INDEX_PORT:
1960	*pu32 = pThis->svga.u32IndexReg;
1961	break;
1962
1963	case SVGA_VALUE_PORT:
1964	return vmsvgaReadPort(pDevIns, pThis, pu32);
1965
1966	case SVGA_BIOS_PORT:
1967	Log(("Ignoring BIOS port read\n"));
1968	*pu32 = 0;
1969	break;
1970
1971	case SVGA_IRQSTATUS_PORT:
1972	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1973	*pu32 = pThis->svga.u32IrqStatus;
1974	break;
1975
1976	default:
1977	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1978	*pu32 = UINT32_MAX;
1979	break;
1980	}
1981	}
1982	else
1983	{
1984	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
1985	*pu32 = UINT32_MAX;
1986	}
1987	return VINF_SUCCESS;
1988	}
1989
1990	/**
1991	* @callback_method_impl{FNIOMIOPORTNEWOUT}
1992	*/
1993	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1994	{
1995	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1996	RT_NOREF_PV(pvUser);
1997
1998	/* Only dword accesses. */
1999	if (cb == 4)
2000	switch (offPort)
2001	{
2002	case SVGA_INDEX_PORT:
2003	pThis->svga.u32IndexReg = u32;
2004	break;
2005
2006	case SVGA_VALUE_PORT:
2007	return vmsvgaWritePort(pDevIns, pThis, u32);
2008
2009	case SVGA_BIOS_PORT:
2010	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2011	break;
2012
2013	case SVGA_IRQSTATUS_PORT:
2014	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2015	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2016	/* Clear the irq in case all events have been cleared. */
2017	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2018	{
2019	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2020	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2021	}
2022	break;
2023
2024	default:
2025	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2026	break;
2027	}
2028	else
2029	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2030
2031	return VINF_SUCCESS;
2032	}
2033
2034	#ifdef IN_RING3
2035
2036	# ifdef DEBUG_FIFO_ACCESS
2037	/**
2038	* Handle FIFO memory access.
2039	* @returns VBox status code.
2040	* @param pVM VM handle.
2041	* @param pThis VGA device instance data.
2042	* @param GCPhys The access physical address.
2043	* @param fWriteAccess Read or write access
2044	*/
2045	static int vmsvgaDebugFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2046	{
2047	RT_NOREF(pVM);
2048	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2049	uint32_t *pFIFO = pThis->svga.pFIFOR3;
2050
2051	switch (GCPhysOffset >> 2)
2052	{
2053	case SVGA_FIFO_MIN:
2054	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2055	break;
2056	case SVGA_FIFO_MAX:
2057	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2058	break;
2059	case SVGA_FIFO_NEXT_CMD:
2060	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2061	break;
2062	case SVGA_FIFO_STOP:
2063	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2064	break;
2065	case SVGA_FIFO_CAPABILITIES:
2066	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2067	break;
2068	case SVGA_FIFO_FLAGS:
2069	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2070	break;
2071	case SVGA_FIFO_FENCE:
2072	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2073	break;
2074	case SVGA_FIFO_3D_HWVERSION:
2075	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2076	break;
2077	case SVGA_FIFO_PITCHLOCK:
2078	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2079	break;
2080	case SVGA_FIFO_CURSOR_ON:
2081	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2082	break;
2083	case SVGA_FIFO_CURSOR_X:
2084	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2085	break;
2086	case SVGA_FIFO_CURSOR_Y:
2087	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2088	break;
2089	case SVGA_FIFO_CURSOR_COUNT:
2090	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2091	break;
2092	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2093	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2094	break;
2095	case SVGA_FIFO_RESERVED:
2096	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2097	break;
2098	case SVGA_FIFO_CURSOR_SCREEN_ID:
2099	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2100	break;
2101	case SVGA_FIFO_DEAD:
2102	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2103	break;
2104	case SVGA_FIFO_3D_HWVERSION_REVISED:
2105	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2106	break;
2107	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2108	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2109	break;
2110	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2111	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2112	break;
2113	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2114	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2115	break;
2116	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2117	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2118	break;
2119	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2120	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2121	break;
2122	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2123	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2124	break;
2125	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2126	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2127	break;
2128	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2129	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2130	break;
2131	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2132	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2133	break;
2134	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2135	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2136	break;
2137	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2138	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2139	break;
2140	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2141	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2142	break;
2143	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2144	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2145	break;
2146	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2147	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2148	break;
2149	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2150	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2151	break;
2152	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2153	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2154	break;
2155	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2156	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2157	break;
2158	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2159	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2160	break;
2161	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2162	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2163	break;
2164	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2165	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2166	break;
2167	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2168	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2169	break;
2170	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2171	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2172	break;
2173	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2174	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2175	break;
2176	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS_LAST:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_GUEST_3D_HWVERSION:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_FENCE_GOAL:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_BUSY:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	default:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	}
2372
2373	return VINF_EM_RAW_EMULATE_INSTR;
2374	}
2375	# endif /* DEBUG_FIFO_ACCESS */
2376
2377	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2378	/**
2379	* HC access handler for the FIFO.
2380	*
2381	* @returns VINF_SUCCESS if the handler have carried out the operation.
2382	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2383	* @param pVM VM Handle.
2384	* @param pVCpu The cross context CPU structure for the calling EMT.
2385	* @param GCPhys The physical address the guest is writing to.
2386	* @param pvPhys The HC mapping of that address.
2387	* @param pvBuf What the guest is reading/writing.
2388	* @param cbBuf How much it's reading/writing.
2389	* @param enmAccessType The access type.
2390	* @param enmOrigin Who is making the access.
2391	* @param pvUser User argument.
2392	*/
2393	static DECLCALLBACK(VBOXSTRICTRC)
2394	vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2395	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2396	{
2397	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2398	PVGASTATE pThis = (PVGASTATE)pvUser;
2399	AssertPtr(pThis);
2400
2401	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2402	/*
2403	* Wake up the FIFO thread as it might have work to do now.
2404	*/
2405	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2406	AssertLogRelRC(rc);
2407	# endif
2408
2409	# ifdef DEBUG_FIFO_ACCESS
2410	/*
2411	* When in debug-fifo-access mode, we do not disable the access handler,
2412	* but leave it on as we wish to catch all access.
2413	*/
2414	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2415	rc = vmsvgaDebugFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2416	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2417	/*
2418	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2419	*/
2420	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoAccessHandler);
2421	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2422	# endif
2423	if (RT_SUCCESS(rc))
2424	return VINF_PGM_HANDLER_DO_DEFAULT;
2425	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2426	return rc;
2427	}
2428	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2429
2430	#endif /* IN_RING3 */
2431
2432	#ifdef DEBUG_GMR_ACCESS
2433	# ifdef IN_RING3
2434
2435	/**
2436	* HC access handler for the FIFO.
2437	*
2438	* @returns VINF_SUCCESS if the handler have carried out the operation.
2439	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2440	* @param pVM VM Handle.
2441	* @param pVCpu The cross context CPU structure for the calling EMT.
2442	* @param GCPhys The physical address the guest is writing to.
2443	* @param pvPhys The HC mapping of that address.
2444	* @param pvBuf What the guest is reading/writing.
2445	* @param cbBuf How much it's reading/writing.
2446	* @param enmAccessType The access type.
2447	* @param enmOrigin Who is making the access.
2448	* @param pvUser User argument.
2449	*/
2450	static DECLCALLBACK(VBOXSTRICTRC)
2451	vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2452	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2453	{
2454	PVGASTATE pThis = (PVGASTATE)pvUser;
2455	Assert(pThis);
2456	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2457	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2458
2459	Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
2460
2461	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2462	{
2463	PGMR pGMR = &pSVGAState->paGMR[i];
2464
2465	if (pGMR->numDescriptors)
2466	{
2467	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2468	{
2469	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2470	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2471	{
2472	/*
2473	* Turn off the write handler for this particular page and make it R/W.
2474	* Then return telling the caller to restart the guest instruction.
2475	*/
2476	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2477	AssertRC(rc);
2478	goto end;
2479	}
2480	}
2481	}
2482	}
2483	end:
2484	return VINF_PGM_HANDLER_DO_DEFAULT;
2485	}
2486
2487	/* Callback handler for VMR3ReqCallWaitU */
2488	static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2489	{
2490	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2491	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2492	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2493	int rc;
2494
2495	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2496	{
2497	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
2498	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2499	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2500	AssertRC(rc);
2501	}
2502	return VINF_SUCCESS;
2503	}
2504
2505	/* Callback handler for VMR3ReqCallWaitU */
2506	static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2507	{
2508	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2509	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2510	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2511
2512	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2513	{
2514	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2515	AssertRC(rc);
2516	}
2517	return VINF_SUCCESS;
2518	}
2519
2520	/* Callback handler for VMR3ReqCallWaitU */
2521	static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2522	{
2523	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2524
2525	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2526	{
2527	PGMR pGMR = &pSVGAState->paGMR[i];
2528
2529	if (pGMR->numDescriptors)
2530	{
2531	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2532	{
2533	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2534	AssertRC(rc);
2535	}
2536	}
2537	}
2538	return VINF_SUCCESS;
2539	}
2540
2541	# endif /* IN_RING3 */
2542	#endif /* DEBUG_GMR_ACCESS */
2543
2544	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2545
2546	#ifdef IN_RING3
2547
2548
2549	/**
2550	* Common worker for changing the pointer shape.
2551	*
2552	* @param pThis The VGA instance data.
2553	* @param pSVGAState The VMSVGA ring-3 instance data.
2554	* @param fAlpha Whether there is alpha or not.
2555	* @param xHot Hotspot x coordinate.
2556	* @param yHot Hotspot y coordinate.
2557	* @param cx Width.
2558	* @param cy Height.
2559	* @param pbData Heap copy of the cursor data. Consumed.
2560	* @param cbData The size of the data.
2561	*/
2562	static void vmsvgaR3InstallNewCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2563	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2564	{
2565	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2566	#ifdef LOG_ENABLED
2567	if (LogIs2Enabled())
2568	{
2569	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2570	if (!fAlpha)
2571	{
2572	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2573	for (uint32_t y = 0; y < cy; y++)
2574	{
2575	Log2(("%3u:", y));
2576	uint8_t const pbLine = &pbData[y cbAndLine];
2577	for (uint32_t x = 0; x < cx; x += 8)
2578	{
2579	uint8_t b = pbLine[x / 8];
2580	char szByte[12];
2581	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2582	szByte[1] = b & 0x40 ? '*' : ' ';
2583	szByte[2] = b & 0x20 ? '*' : ' ';
2584	szByte[3] = b & 0x10 ? '*' : ' ';
2585	szByte[4] = b & 0x08 ? '*' : ' ';
2586	szByte[5] = b & 0x04 ? '*' : ' ';
2587	szByte[6] = b & 0x02 ? '*' : ' ';
2588	szByte[7] = b & 0x01 ? '*' : ' ';
2589	szByte[8] = '\0';
2590	Log2(("%s", szByte));
2591	}
2592	Log2(("\n"));
2593	}
2594	}
2595
2596	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2597	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2598	for (uint32_t y = 0; y < cy; y++)
2599	{
2600	Log2(("%3u:", y));
2601	uint32_t const pu32Line = &pu32Xor[y cx];
2602	for (uint32_t x = 0; x < cx; x++)
2603	Log2((" %08x", pu32Line[x]));
2604	Log2(("\n"));
2605	}
2606	}
2607	#endif
2608
2609	int rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2610	AssertRC(rc);
2611
2612	if (pSVGAState->Cursor.fActive)
2613	RTMemFree(pSVGAState->Cursor.pData);
2614
2615	pSVGAState->Cursor.fActive = true;
2616	pSVGAState->Cursor.xHotspot = xHot;
2617	pSVGAState->Cursor.yHotspot = yHot;
2618	pSVGAState->Cursor.width = cx;
2619	pSVGAState->Cursor.height = cy;
2620	pSVGAState->Cursor.cbData = cbData;
2621	pSVGAState->Cursor.pData = pbData;
2622	}
2623
2624
2625	/**
2626	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2627	*
2628	* @param pThis The VGA instance data.
2629	* @param pSVGAState The VMSVGA ring-3 instance data.
2630	* @param pCursor The cursor.
2631	* @param pbSrcAndMask The AND mask.
2632	* @param cbSrcAndLine The scanline length of the AND mask.
2633	* @param pbSrcXorMask The XOR mask.
2634	* @param cbSrcXorLine The scanline length of the XOR mask.
2635	*/
2636	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, SVGAFifoCmdDefineCursor const *pCursor,
2637	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2638	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2639	{
2640	uint32_t const cx = pCursor->width;
2641	uint32_t const cy = pCursor->height;
2642
2643	/*
2644	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2645	* The AND data uses 8-bit aligned scanlines.
2646	* The XOR data must be starting on a 32-bit boundrary.
2647	*/
2648	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2649	uint32_t cbDstAndMask = cbDstAndLine * cy;
2650	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2651	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2652
2653	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2654	AssertReturnVoid(pbCopy);
2655
2656	/* Convert the AND mask. */
2657	uint8_t *pbDst = pbCopy;
2658	uint8_t const *pbSrc = pbSrcAndMask;
2659	switch (pCursor->andMaskDepth)
2660	{
2661	case 1:
2662	if (cbSrcAndLine == cbDstAndLine)
2663	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2664	else
2665	{
2666	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2667	for (uint32_t y = 0; y < cy; y++)
2668	{
2669	memcpy(pbDst, pbSrc, cbDstAndLine);
2670	pbDst += cbDstAndLine;
2671	pbSrc += cbSrcAndLine;
2672	}
2673	}
2674	break;
2675	/* Should take the XOR mask into account for the multi-bit AND mask. */
2676	case 8:
2677	for (uint32_t y = 0; y < cy; y++)
2678	{
2679	for (uint32_t x = 0; x < cx; )
2680	{
2681	uint8_t bDst = 0;
2682	uint8_t fBit = 1;
2683	do
2684	{
2685	uintptr_t const idxPal = pbSrc[x] * 3;
2686	if ((( pThis->last_palette[idxPal]
2687	\| (pThis->last_palette[idxPal] >> 8)
2688	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2689	bDst \|= fBit;
2690	fBit <<= 1;
2691	x++;
2692	} while (x < cx && (x & 7));
2693	pbDst[(x - 1) / 8] = bDst;
2694	}
2695	pbDst += cbDstAndLine;
2696	pbSrc += cbSrcAndLine;
2697	}
2698	break;
2699	case 15:
2700	for (uint32_t y = 0; y < cy; y++)
2701	{
2702	for (uint32_t x = 0; x < cx; )
2703	{
2704	uint8_t bDst = 0;
2705	uint8_t fBit = 1;
2706	do
2707	{
2708	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2709	bDst \|= fBit;
2710	fBit <<= 1;
2711	x++;
2712	} while (x < cx && (x & 7));
2713	pbDst[(x - 1) / 8] = bDst;
2714	}
2715	pbDst += cbDstAndLine;
2716	pbSrc += cbSrcAndLine;
2717	}
2718	break;
2719	case 16:
2720	for (uint32_t y = 0; y < cy; y++)
2721	{
2722	for (uint32_t x = 0; x < cx; )
2723	{
2724	uint8_t bDst = 0;
2725	uint8_t fBit = 1;
2726	do
2727	{
2728	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2729	bDst \|= fBit;
2730	fBit <<= 1;
2731	x++;
2732	} while (x < cx && (x & 7));
2733	pbDst[(x - 1) / 8] = bDst;
2734	}
2735	pbDst += cbDstAndLine;
2736	pbSrc += cbSrcAndLine;
2737	}
2738	break;
2739	case 24:
2740	for (uint32_t y = 0; y < cy; y++)
2741	{
2742	for (uint32_t x = 0; x < cx; )
2743	{
2744	uint8_t bDst = 0;
2745	uint8_t fBit = 1;
2746	do
2747	{
2748	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2749	bDst \|= fBit;
2750	fBit <<= 1;
2751	x++;
2752	} while (x < cx && (x & 7));
2753	pbDst[(x - 1) / 8] = bDst;
2754	}
2755	pbDst += cbDstAndLine;
2756	pbSrc += cbSrcAndLine;
2757	}
2758	break;
2759	case 32:
2760	for (uint32_t y = 0; y < cy; y++)
2761	{
2762	for (uint32_t x = 0; x < cx; )
2763	{
2764	uint8_t bDst = 0;
2765	uint8_t fBit = 1;
2766	do
2767	{
2768	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2769	bDst \|= fBit;
2770	fBit <<= 1;
2771	x++;
2772	} while (x < cx && (x & 7));
2773	pbDst[(x - 1) / 8] = bDst;
2774	}
2775	pbDst += cbDstAndLine;
2776	pbSrc += cbSrcAndLine;
2777	}
2778	break;
2779	default:
2780	RTMemFree(pbCopy);
2781	AssertFailedReturnVoid();
2782	}
2783
2784	/* Convert the XOR mask. */
2785	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2786	pbSrc = pbSrcXorMask;
2787	switch (pCursor->xorMaskDepth)
2788	{
2789	case 1:
2790	for (uint32_t y = 0; y < cy; y++)
2791	{
2792	for (uint32_t x = 0; x < cx; )
2793	{
2794	/* most significant bit is the left most one. */
2795	uint8_t bSrc = pbSrc[x / 8];
2796	do
2797	{
2798	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2799	bSrc <<= 1;
2800	x++;
2801	} while ((x & 7) && x < cx);
2802	}
2803	pbSrc += cbSrcXorLine;
2804	}
2805	break;
2806	case 8:
2807	for (uint32_t y = 0; y < cy; y++)
2808	{
2809	for (uint32_t x = 0; x < cx; x++)
2810	{
2811	uint32_t u = pThis->last_palette[pbSrc[x]];
2812	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2813	}
2814	pbSrc += cbSrcXorLine;
2815	}
2816	break;
2817	case 15: /* Src: RGB-5-5-5 */
2818	for (uint32_t y = 0; y < cy; y++)
2819	{
2820	for (uint32_t x = 0; x < cx; x++)
2821	{
2822	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2823	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2824	((uValue >> 5) & 0x1f) << 3,
2825	((uValue >> 10) & 0x1f) << 3, 0);
2826	}
2827	pbSrc += cbSrcXorLine;
2828	}
2829	break;
2830	case 16: /* Src: RGB-5-6-5 */
2831	for (uint32_t y = 0; y < cy; y++)
2832	{
2833	for (uint32_t x = 0; x < cx; x++)
2834	{
2835	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2836	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2837	((uValue >> 5) & 0x3f) << 2,
2838	((uValue >> 11) & 0x1f) << 3, 0);
2839	}
2840	pbSrc += cbSrcXorLine;
2841	}
2842	break;
2843	case 24:
2844	for (uint32_t y = 0; y < cy; y++)
2845	{
2846	for (uint32_t x = 0; x < cx; x++)
2847	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2848	pbSrc += cbSrcXorLine;
2849	}
2850	break;
2851	case 32:
2852	for (uint32_t y = 0; y < cy; y++)
2853	{
2854	for (uint32_t x = 0; x < cx; x++)
2855	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2856	pbSrc += cbSrcXorLine;
2857	}
2858	break;
2859	default:
2860	RTMemFree(pbCopy);
2861	AssertFailedReturnVoid();
2862	}
2863
2864	/*
2865	* Pass it to the frontend/whatever.
2866	*/
2867	vmsvgaR3InstallNewCursor(pThis, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2868	}
2869
2870
2871	/**
2872	* Worker for vmsvgaR3FifoThread that handles an external command.
2873	*
2874	* @param pThis VGA device instance data.
2875	*/
2876	static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2877	{
2878	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2879	switch (pThis->svga.u8FIFOExtCommand)
2880	{
2881	case VMSVGA_FIFO_EXTCMD_RESET:
2882	Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2883	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2884	# ifdef VBOX_WITH_VMSVGA3D
2885	if (pThis->svga.f3DEnabled)
2886	{
2887	/* The 3d subsystem must be reset from the fifo thread. */
2888	vmsvga3dReset(pThis);
2889	}
2890	# endif
2891	break;
2892
2893	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2894	Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2895	Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2896	# ifdef VBOX_WITH_VMSVGA3D
2897	if (pThis->svga.f3DEnabled)
2898	{
2899	/* The 3d subsystem must be shut down from the fifo thread. */
2900	vmsvga3dTerminate(pThis);
2901	}
2902	# endif
2903	break;
2904
2905	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2906	{
2907	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2908	PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2909	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2910	vmsvgaSaveExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pSSM);
2911	# ifdef VBOX_WITH_VMSVGA3D
2912	if (pThis->svga.f3DEnabled)
2913	vmsvga3dSaveExec(pThis->pDevInsR3, pThis, pSSM);
2914	# endif
2915	break;
2916	}
2917
2918	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2919	{
2920	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2921	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2922	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2923	vmsvgaLoadExecFifo(pThis->pDevInsR3->pHlpR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2924	# ifdef VBOX_WITH_VMSVGA3D
2925	if (pThis->svga.f3DEnabled)
2926	vmsvga3dLoadExec(pThis->pDevInsR3, pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2927	# endif
2928	break;
2929	}
2930
2931	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2932	{
2933	# ifdef VBOX_WITH_VMSVGA3D
2934	uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2935	Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2936	vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2937	# endif
2938	break;
2939	}
2940
2941
2942	default:
2943	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2944	break;
2945	}
2946
2947	/*
2948	* Signal the end of the external command.
2949	*/
2950	pThis->svga.pvFIFOExtCmdParam = NULL;
2951	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2952	ASMMemoryFence(); /* paranoia^2 */
2953	int rc = RTSemEventSignal(pThis->svga.hFIFOExtCmdSem);
2954	AssertLogRelRC(rc);
2955	}
2956
2957	/**
2958	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2959	* doing a job on the FIFO thread (even when it's officially suspended).
2960	*
2961	* @returns VBox status code (fully asserted).
2962	* @param pDevIns The device instance.
2963	* @param pThis VGA device instance data.
2964	* @param uExtCmd The command to execute on the FIFO thread.
2965	* @param pvParam Pointer to command parameters.
2966	* @param cMsWait The time to wait for the command, given in
2967	* milliseconds.
2968	*/
2969	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2970	{
2971	Assert(cMsWait >= RT_MS_1SEC * 5);
2972	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2973	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2974
2975	int rc;
2976	PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2977	PDMTHREADSTATE enmState = pThread->enmState;
2978	if (enmState == PDMTHREADSTATE_SUSPENDED)
2979	{
2980	/*
2981	* The thread is suspended, we have to temporarily wake it up so it can
2982	* perform the task.
2983	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
2984	*/
2985	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2986	/* Post the request. */
2987	pThis->svga.fFifoExtCommandWakeup = true;
2988	pThis->svga.pvFIFOExtCmdParam = pvParam;
2989	pThis->svga.u8FIFOExtCommand = uExtCmd;
2990	ASMMemoryFence(); /* paranoia^3 */
2991
2992	/* Resume the thread. */
2993	rc = PDMDevHlpThreadResume(pDevIns, pThread);
2994	AssertLogRelRC(rc);
2995	if (RT_SUCCESS(rc))
2996	{
2997	/* Wait. Take care in case the semaphore was already posted (same as below). */
2998	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
2999	if ( rc == VINF_SUCCESS
3000	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3001	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3002	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3003	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3004
3005	/* suspend the thread */
3006	pThis->svga.fFifoExtCommandWakeup = false;
3007	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3008	AssertLogRelRC(rc2);
3009	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3010	rc = rc2;
3011	}
3012	pThis->svga.fFifoExtCommandWakeup = false;
3013	pThis->svga.pvFIFOExtCmdParam = NULL;
3014	}
3015	else if (enmState == PDMTHREADSTATE_RUNNING)
3016	{
3017	/*
3018	* The thread is running, should only happen during reset and vmsvga3dsfc.
3019	* We ASSUME not racing code here, both wrt thread state and ext commands.
3020	*/
3021	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3022	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3023
3024	/* Post the request. */
3025	pThis->svga.pvFIFOExtCmdParam = pvParam;
3026	pThis->svga.u8FIFOExtCommand = uExtCmd;
3027	ASMMemoryFence(); /* paranoia^2 */
3028	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3029	AssertLogRelRC(rc);
3030
3031	/* Wait. Take care in case the semaphore was already posted (same as above). */
3032	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait);
3033	if ( rc == VINF_SUCCESS
3034	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3035	rc = RTSemEventWait(pThis->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3036	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3037	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3038
3039	pThis->svga.pvFIFOExtCmdParam = NULL;
3040	}
3041	else
3042	{
3043	/*
3044	* Something is wrong with the thread!
3045	*/
3046	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3047	rc = VERR_INVALID_STATE;
3048	}
3049	return rc;
3050	}
3051
3052
3053	/**
3054	* Marks the FIFO non-busy, notifying any waiting EMTs.
3055	*
3056	* @param pThis The VGA state.
3057	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3058	* @param offFifoMin The start byte offset of the command FIFO.
3059	*/
3060	static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3061	{
3062	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3063	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3064	vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
3065
3066	/* Wake up any waiting EMTs. */
3067	if (pSVGAState->cBusyDelayedEmts > 0)
3068	{
3069	#ifdef VMSVGA_USE_EMT_HALT_CODE
3070	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3071	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3072	if (idCpu != NIL_VMCPUID)
3073	{
3074	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3075	while (idCpu-- > 0)
3076	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3077	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3078	}
3079	#else
3080	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3081	AssertRC(rc2);
3082	#endif
3083	}
3084	}
3085
3086	/**
3087	* Reads (more) payload into the command buffer.
3088	*
3089	* @returns pbBounceBuf on success
3090	* @retval (void *)1 if the thread was requested to stop.
3091	* @retval NULL on FIFO error.
3092	*
3093	* @param cbPayloadReq The number of bytes of payload requested.
3094	* @param pFIFO The FIFO.
3095	* @param offCurrentCmd The FIFO byte offset of the current command.
3096	* @param offFifoMin The start byte offset of the command FIFO.
3097	* @param offFifoMax The end byte offset of the command FIFO.
3098	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3099	* always sufficient size.
3100	* @param pcbAlreadyRead How much payload we've already read into the bounce
3101	* buffer. (We will NEVER re-read anything.)
3102	* @param pThread The calling PDM thread handle.
3103	* @param pThis The VGA state.
3104	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3105	* statistics collection.
3106	*/
3107	static void vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3108	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3109	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3110	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3111	{
3112	Assert(pbBounceBuf);
3113	Assert(pcbAlreadyRead);
3114	Assert(offFifoMin < offFifoMax);
3115	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3116	Assert(offFifoMax <= pThis->svga.cbFIFO);
3117
3118	/*
3119	* Check if the requested payload size has already been satisfied .
3120	* .
3121	* When called to read more, the caller is responsible for making sure the .
3122	* new command size (cbRequsted) never is smaller than what has already .
3123	* been read.
3124	*/
3125	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3126	if (cbPayloadReq <= cbAlreadyRead)
3127	{
3128	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3129	return pbBounceBuf;
3130	}
3131
3132	/*
3133	* Commands bigger than the fifo buffer are invalid.
3134	*/
3135	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3136	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3137	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3138	NULL);
3139
3140	/*
3141	* Move offCurrentCmd past the command dword.
3142	*/
3143	offCurrentCmd += sizeof(uint32_t);
3144	if (offCurrentCmd >= offFifoMax)
3145	offCurrentCmd = offFifoMin;
3146
3147	/*
3148	* Do we have sufficient payload data available already?
3149	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3150	*/
3151	uint32_t cbAfter, cbBefore;
3152	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3153	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3154	if (offNextCmd >= offCurrentCmd)
3155	{
3156	if (RT_LIKELY(offNextCmd < offFifoMax))
3157	cbAfter = offNextCmd - offCurrentCmd;
3158	else
3159	{
3160	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3161	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3162	offNextCmd, offFifoMin, offFifoMax));
3163	cbAfter = offFifoMax - offCurrentCmd;
3164	}
3165	cbBefore = 0;
3166	}
3167	else
3168	{
3169	cbAfter = offFifoMax - offCurrentCmd;
3170	if (offNextCmd >= offFifoMin)
3171	cbBefore = offNextCmd - offFifoMin;
3172	else
3173	{
3174	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3175	LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3176	offNextCmd, offFifoMin, offFifoMax));
3177	cbBefore = 0;
3178	}
3179	}
3180	if (cbAfter + cbBefore < cbPayloadReq)
3181	{
3182	/*
3183	* Insufficient, must wait for it to arrive.
3184	*/
3185	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3186	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3187	for (uint32_t i = 0;; i++)
3188	{
3189	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3190	{
3191	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3192	return (void *)(uintptr_t)1;
3193	}
3194	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3195	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3196
3197	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3198
3199	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3200	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3201	if (offNextCmd >= offCurrentCmd)
3202	{
3203	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3204	cbBefore = 0;
3205	}
3206	else
3207	{
3208	cbAfter = offFifoMax - offCurrentCmd;
3209	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3210	}
3211
3212	if (cbAfter + cbBefore >= cbPayloadReq)
3213	break;
3214	}
3215	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3216	}
3217
3218	/*
3219	* Copy out the memory and update what pcbAlreadyRead points to.
3220	*/
3221	if (cbAfter >= cbPayloadReq)
3222	memcpy(pbBounceBuf + cbAlreadyRead,
3223	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3224	cbPayloadReq - cbAlreadyRead);
3225	else
3226	{
3227	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3228	if (cbAlreadyRead < cbAfter)
3229	{
3230	memcpy(pbBounceBuf + cbAlreadyRead,
3231	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3232	cbAfter - cbAlreadyRead);
3233	cbAlreadyRead = cbAfter;
3234	}
3235	memcpy(pbBounceBuf + cbAlreadyRead,
3236	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3237	cbPayloadReq - cbAlreadyRead);
3238	}
3239	*pcbAlreadyRead = cbPayloadReq;
3240	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3241	return pbBounceBuf;
3242	}
3243
3244
3245	/**
3246	* Sends cursor position and visibility information from the FIFO to the front-end.
3247	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3248	*/
3249	static uint32_t
3250	vmsvgaFIFOUpdateCursor(PVGASTATE pVGAState, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3251	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3252	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3253	{
3254	/*
3255	* Check if the cursor update counter has changed and try get a stable
3256	* set of values if it has. This is race-prone, especially consindering
3257	* the screen ID, but little we can do about that.
3258	*/
3259	uint32_t x, y, fVisible, idScreen;
3260	for (uint32_t i = 0; ; i++)
3261	{
3262	x = pFIFO[SVGA_FIFO_CURSOR_X];
3263	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3264	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3265	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3266	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3267	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3268	\|\| i > 3)
3269	break;
3270	if (i == 0)
3271	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3272	ASMNopPause();
3273	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3274	}
3275
3276	/*
3277	* Check if anything has changed, as calling into pDrv is not light-weight.
3278	*/
3279	if ( *pxLast == x
3280	&& *pyLast == y
3281	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3282	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3283	else
3284	{
3285	/*
3286	* Detected changes.
3287	*
3288	* We handle global, not per-screen visibility information by sending
3289	* pfnVBVAMousePointerShape without shape data.
3290	*/
3291	*pxLast = x;
3292	*pyLast = y;
3293	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3294	if (idScreen != SVGA_ID_INVALID)
3295	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3296	else if (*pfLastVisible != fVisible)
3297	{
3298	LogRel2(("vmsvgaFIFOUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3299	*pfLastVisible = fVisible;
3300	pVGAState->pDrv->pfnVBVAMousePointerShape(pVGAState->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3301	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3302	}
3303	pVGAState->pDrv->pfnVBVAReportCursorPosition(pVGAState->pDrv, fFlags, idScreen, x, y);
3304	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3305	}
3306
3307	/*
3308	* Update done. Signal this to the guest.
3309	*/
3310	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3311
3312	return uCursorUpdateCount;
3313	}
3314
3315
3316	/**
3317	* Checks if there is work to be done, either cursor updating or FIFO commands.
3318	*
3319	* @returns true if pending work, false if not.
3320	* @param pFIFO The FIFO to examine.
3321	* @param uLastCursorCount The last cursor update counter value.
3322	*/
3323	DECLINLINE(bool) vmsvgaFIFOHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3324	{
3325	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3326	return true;
3327
3328	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3329	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3330	return true;
3331
3332	return false;
3333	}
3334
3335
3336	/**
3337	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3338	*
3339	* @param pThis The VGA state.
3340	*/
3341	void vmsvgaFIFOWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis)
3342	{
3343	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3344	to recheck it before doing the signalling. */
3345	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3346	AssertReturnVoid(pFIFO);
3347	if ( vmsvgaFIFOHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3348	&& pThis->svga.fFIFOThreadSleeping)
3349	{
3350	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3351	AssertRC(rc);
3352	STAM_REL_COUNTER_INC(&pThis->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3353	}
3354	}
3355
3356
3357	/* The async FIFO handling thread. */
3358	static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3359	{
3360	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3361	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3362	int rc;
3363
3364	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3365	return VINF_SUCCESS;
3366
3367	/*
3368	* Special mode where we only execute an external command and the go back
3369	* to being suspended. Currently, all ext cmds ends up here, with the reset
3370	* one also being eligble for runtime execution further down as well.
3371	*/
3372	if (pThis->svga.fFifoExtCommandWakeup)
3373	{
3374	vmsvgaR3FifoHandleExtCmd(pThis);
3375	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3376	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3377	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3378	else
3379	vmsvgaR3FifoHandleExtCmd(pThis);
3380	return VINF_SUCCESS;
3381	}
3382
3383
3384	/*
3385	* Signal the semaphore to make sure we don't wait for 250ms after a
3386	* suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
3387	*/
3388	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3389
3390	/*
3391	* Allocate a bounce buffer for command we get from the FIFO.
3392	* (All code must return via the end of the function to free this buffer.)
3393	*/
3394	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3395	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3396
3397	/*
3398	* Polling/sleep interval config.
3399	*
3400	* We wait for an a short interval if the guest has recently given us work
3401	* to do, but the interval increases the longer we're kept idle. Once we've
3402	* reached the refresh timer interval, we'll switch to extended waits,
3403	* depending on it or the guest to kick us into action when needed.
3404	*
3405	* Should the refresh time go fishing, we'll just continue increasing the
3406	* sleep length till we reaches the 250 ms max after about 16 seconds.
3407	*/
3408	RTMSINTERVAL const cMsMinSleep = 16;
3409	RTMSINTERVAL const cMsIncSleep = 2;
3410	RTMSINTERVAL const cMsMaxSleep = 250;
3411	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3412	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3413
3414	/*
3415	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3416	*
3417	* Initialize with values that will detect an update from the guest.
3418	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3419	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3420	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3421	*/
3422	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThis->svga.pFIFOR3;
3423	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3424	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3425	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3426	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3427
3428	/*
3429	* The FIFO loop.
3430	*/
3431	LogFlow(("vmsvgaFIFOLoop: started loop\n"));
3432	bool fBadOrDisabledFifo = false;
3433	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3434	{
3435	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3436	/*
3437	* Should service the run loop every so often.
3438	*/
3439	if (pThis->svga.f3DEnabled)
3440	vmsvga3dCocoaServiceRunLoop();
3441	# endif
3442
3443	/*
3444	* Unless there's already work pending, go to sleep for a short while.
3445	* (See polling/sleep interval config above.)
3446	*/
3447	if ( fBadOrDisabledFifo
3448	\|\| !vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3449	{
3450	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3451	Assert(pThis->cMilliesRefreshInterval > 0);
3452	if (cMsSleep < pThis->cMilliesRefreshInterval)
3453	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3454	else
3455	{
3456	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3457	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3458	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3459	# endif
3460	if ( !fBadOrDisabledFifo
3461	&& vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3462	rc = VINF_SUCCESS;
3463	else
3464	{
3465	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3466	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3467	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3468	}
3469	}
3470	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3471	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3472	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3473	{
3474	LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
3475	break;
3476	}
3477	}
3478	else
3479	rc = VINF_SUCCESS;
3480	fBadOrDisabledFifo = false;
3481	if (rc == VERR_TIMEOUT)
3482	{
3483	if (!vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3484	{
3485	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3486	continue;
3487	}
3488	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3489
3490	Log(("vmsvgaFIFOLoop: timeout\n"));
3491	}
3492	else if (vmsvgaFIFOHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3493	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3494	cMsSleep = cMsMinSleep;
3495
3496	Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3497	Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3498	Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3499
3500	/*
3501	* Handle external commands (currently only reset).
3502	*/
3503	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3504	{
3505	vmsvgaR3FifoHandleExtCmd(pThis);
3506	continue;
3507	}
3508
3509	/*
3510	* The device must be enabled and configured.
3511	*/
3512	if ( !pThis->svga.fEnabled
3513	\|\| !pThis->svga.fConfigured)
3514	{
3515	vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3516	fBadOrDisabledFifo = true;
3517	cMsSleep = cMsMaxSleep; /* cheat */
3518	continue;
3519	}
3520
3521	/*
3522	* Get and check the min/max values. We ASSUME that they will remain
3523	* unchanged while we process requests. A further ASSUMPTION is that
3524	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3525	* we don't read it back while in the loop.
3526	*/
3527	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3528	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3529	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3530	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3531	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3532	\|\| offFifoMax <= offFifoMin
3533	\|\| offFifoMax > pThis->svga.cbFIFO
3534	\|\| (offFifoMax & 3) != 0
3535	\|\| (offFifoMin & 3) != 0
3536	\|\| offCurrentCmd < offFifoMin
3537	\|\| offCurrentCmd > offFifoMax))
3538	{
3539	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3540	LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3541	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3542	fBadOrDisabledFifo = true;
3543	continue;
3544	}
3545	RT_UNTRUSTED_VALIDATED_FENCE();
3546	if (RT_UNLIKELY(offCurrentCmd & 3))
3547	{
3548	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3549	LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3550	offCurrentCmd &= ~UINT32_C(3);
3551	}
3552
3553	/*
3554	* Update the cursor position before we start on the FIFO commands.
3555	*/
3556	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3557	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3558	{
3559	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3560	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3561	{ /* halfways likely */ }
3562	else
3563	{
3564	uint32_t const uLastCursorCount = vmsvgaFIFOUpdateCursor(pThis, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3565	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3566	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uLastCursorCount);
3567	}
3568	}
3569
3570	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3571	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
3572	*
3573	* Will break out of the switch on failure.
3574	* Will restart and quit the loop if the thread was requested to stop.
3575	*
3576	* @param a_PtrVar Request variable pointer.
3577	* @param a_Type Request typedef (not pointer) for casting.
3578	* @param a_cbPayloadReq How much payload to fetch.
3579	* @remarks Accesses a bunch of variables in the current scope!
3580	*/
3581	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3582	if (1) { \
3583	(a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3584	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3585	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3586	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3587	} else do {} while (0)
3588	/** @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3589	* Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
3590	* buffer after figuring out the actual command size.
3591	*
3592	* Will break out of the switch on failure.
3593	*
3594	* @param a_PtrVar Request variable pointer.
3595	* @param a_Type Request typedef (not pointer) for casting.
3596	* @param a_cbPayloadReq How much payload to fetch.
3597	* @remarks Accesses a bunch of variables in the current scope!
3598	*/
3599	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3600	if (1) { \
3601	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3602	} else do {} while (0)
3603
3604	/*
3605	* Mark the FIFO as busy.
3606	*/
3607	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3608	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3609	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3610
3611	/*
3612	* Execute all queued FIFO commands.
3613	* Quit if pending external command or changes in the thread state.
3614	*/
3615	bool fDone = false;
3616	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3617	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3618	{
3619	uint32_t cbPayload = 0;
3620	uint32_t u32IrqStatus = 0;
3621
3622	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3623
3624	/* First check any pending actions. */
3625	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3626	{
3627	vmsvgaChangeMode(pThis);
3628	# ifdef VBOX_WITH_VMSVGA3D
3629	if (pThis->svga.p3dState != NULL)
3630	vmsvga3dChangeMode(pThis);
3631	# endif
3632	}
3633
3634	/* Check for pending external commands (reset). */
3635	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3636	break;
3637
3638	/*
3639	* Process the command.
3640	*/
3641	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3642	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3643	LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3644	offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
3645	switch (enmCmdId)
3646	{
3647	case SVGA_CMD_INVALID_CMD:
3648	/* Nothing to do. */
3649	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3650	break;
3651
3652	case SVGA_CMD_FENCE:
3653	{
3654	SVGAFifoCmdFence *pCmdFence;
3655	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3656	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3657	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3658	{
3659	Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3660	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3661
3662	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3663	{
3664	Log(("vmsvgaFIFOLoop: any fence irq\n"));
3665	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3666	}
3667	else
3668	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3669	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3670	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3671	{
3672	Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3673	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3674	}
3675	}
3676	else
3677	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3678	break;
3679	}
3680	case SVGA_CMD_UPDATE:
3681	case SVGA_CMD_UPDATE_VERBOSE:
3682	{
3683	SVGAFifoCmdUpdate *pUpdate;
3684	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3685	if (enmCmdId == SVGA_CMD_UPDATE)
3686	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3687	else
3688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3689	Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3690	/** @todo Multiple screens? */
3691	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, 0);
3692	AssertBreak(pScreen);
3693	vmsvgaUpdateScreen(pThis, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3694	break;
3695	}
3696
3697	case SVGA_CMD_DEFINE_CURSOR:
3698	{
3699	/* Followed by bitmap data. */
3700	SVGAFifoCmdDefineCursor *pCursor;
3701	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3702	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3703
3704	Log(("vmsvgaFIFOLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3705	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3706	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3707	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3708	AssertBreak(pCursor->andMaskDepth <= 32);
3709	AssertBreak(pCursor->xorMaskDepth <= 32);
3710	RT_UNTRUSTED_VALIDATED_FENCE();
3711
3712	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3713	uint32_t cbAndMask = cbAndLine * pCursor->height;
3714	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3715	uint32_t cbXorMask = cbXorLine * pCursor->height;
3716	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3717
3718	vmsvgaR3CmdDefineCursor(pThis, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3719	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3720	break;
3721	}
3722
3723	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3724	{
3725	/* Followed by bitmap data. */
3726	uint32_t cbCursorShape, cbAndMask;
3727	uint8_t *pCursorCopy;
3728	uint32_t cbCmd;
3729
3730	SVGAFifoCmdDefineAlphaCursor *pCursor;
3731	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3732	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3733
3734	Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3735
3736	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3737	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3738	RT_UNTRUSTED_VALIDATED_FENCE();
3739
3740	/* Refetch the bitmap data as well. */
3741	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3742	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3743	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3744
3745	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3746	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3747	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3748	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3749
3750	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3751	AssertBreak(pCursorCopy);
3752
3753	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3754	memset(pCursorCopy, 0xff, cbAndMask);
3755	/* Colour data */
3756	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3757
3758	vmsvgaR3InstallNewCursor(pThis, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3759	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3760	break;
3761	}
3762
3763	case SVGA_CMD_ESCAPE:
3764	{
3765	/* Followed by nsize bytes of data. */
3766	SVGAFifoCmdEscape *pEscape;
3767	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3768	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3769
3770	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3771	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3772	RT_UNTRUSTED_VALIDATED_FENCE();
3773	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3774	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3775
3776	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3777	{
3778	AssertBreak(pEscape->size >= sizeof(uint32_t));
3779	RT_UNTRUSTED_VALIDATED_FENCE();
3780	uint32_t cmd = (uint32_t )(pEscape + 1);
3781	Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3782
3783	switch (cmd)
3784	{
3785	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3786	{
3787	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3788	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3789	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3790
3791	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3792	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3793	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3794
3795	RT_NOREF_PV(pVideoCmd);
3796	break;
3797
3798	}
3799
3800	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3801	{
3802	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3803	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3804	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3805	RT_NOREF_PV(pVideoCmd);
3806	break;
3807	}
3808
3809	default:
3810	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3811	break;
3812	}
3813	}
3814	else
3815	Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3816
3817	break;
3818	}
3819	# ifdef VBOX_WITH_VMSVGA3D
3820	case SVGA_CMD_DEFINE_GMR2:
3821	{
3822	SVGAFifoCmdDefineGMR2 *pCmd;
3823	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3824	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3825	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3826
3827	/* Validate current GMR id. */
3828	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3829	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3830	RT_UNTRUSTED_VALIDATED_FENCE();
3831
3832	if (!pCmd->numPages)
3833	{
3834	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3835	vmsvgaGMRFree(pThis, pCmd->gmrId);
3836	}
3837	else
3838	{
3839	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3840	if (pGMR->cMaxPages)
3841	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3842
3843	/* Not sure if we should always free the descriptor, but for simplicity
3844	we do so if the new size is smaller than the current. */
3845	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3846	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3847	vmsvgaGMRFree(pThis, pCmd->gmrId);
3848
3849	pGMR->cMaxPages = pCmd->numPages;
3850	/* The rest is done by the REMAP_GMR2 command. */
3851	}
3852	break;
3853	}
3854
3855	case SVGA_CMD_REMAP_GMR2:
3856	{
3857	/* Followed by page descriptors or guest ptr. */
3858	SVGAFifoCmdRemapGMR2 *pCmd;
3859	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3860	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3861
3862	Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3863	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3864	RT_UNTRUSTED_VALIDATED_FENCE();
3865
3866	/* Calculate the size of what comes after next and fetch it. */
3867	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3868	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3869	cbCmd += sizeof(SVGAGuestPtr);
3870	else
3871	{
3872	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3873	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3874	{
3875	cbCmd += cbPageDesc;
3876	pCmd->numPages = 1;
3877	}
3878	else
3879	{
3880	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3881	cbCmd += cbPageDesc * pCmd->numPages;
3882	}
3883	}
3884	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3885
3886	/* Validate current GMR id and size. */
3887	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3888	RT_UNTRUSTED_VALIDATED_FENCE();
3889	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3890	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3891	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3892	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3893
3894	if (pCmd->numPages == 0)
3895	break;
3896
3897	/** @todo Move to a separate function vmsvgaGMRRemap() */
3898
3899	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3900	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3901
3902	/*
3903	* We flatten the existing descriptors into a page array, overwrite the
3904	* pages specified in this command and then recompress the descriptor.
3905	*/
3906	/** @todo Optimize the GMR remap algorithm! */
3907
3908	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3909	uint64_t *paNewPage64 = NULL;
3910	if (pGMR->paDesc)
3911	{
3912	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3913
3914	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3915	AssertBreak(paNewPage64);
3916
3917	uint32_t idxPage = 0;
3918	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3919	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3920	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3921	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3922	RT_UNTRUSTED_VALIDATED_FENCE();
3923	}
3924
3925	/* Free the old GMR if present. */
3926	if (pGMR->paDesc)
3927	RTMemFree(pGMR->paDesc);
3928
3929	/* Allocate the maximum amount possible (everything non-continuous) */
3930	PVMSVGAGMRDESCRIPTOR paDescs;
3931	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3932	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3933
3934	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3935	{
3936	/** @todo */
3937	AssertFailed();
3938	pGMR->numDescriptors = 0;
3939	}
3940	else
3941	{
3942	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3943	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3944	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3945
3946	if (paNewPage64)
3947	{
3948	/* Overwrite the old page array with the new page values. */
3949	if (fGCPhys64)
3950	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3951	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3952	else
3953	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3954	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3955
3956	/* Use the updated page array instead of the command data. */
3957	fGCPhys64 = true;
3958	paPages64 = paNewPage64;
3959	pCmd->numPages = cNewTotalPages;
3960	}
3961
3962	/* The first page. */
3963	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3964	* applied to paNewPage64. */
3965	RTGCPHYS GCPhys;
3966	if (fGCPhys64)
3967	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3968	else
3969	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
3970	paDescs[0].GCPhys = GCPhys;
3971	paDescs[0].numPages = 1;
3972
3973	/* Subsequent pages. */
3974	uint32_t iDescriptor = 0;
3975	for (uint32_t i = 1; i < pCmd->numPages; i++)
3976	{
3977	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
3978	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
3979	else
3980	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
3981
3982	/* Continuous physical memory? */
3983	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
3984	{
3985	Assert(paDescs[iDescriptor].numPages);
3986	paDescs[iDescriptor].numPages++;
3987	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
3988	}
3989	else
3990	{
3991	iDescriptor++;
3992	paDescs[iDescriptor].GCPhys = GCPhys;
3993	paDescs[iDescriptor].numPages = 1;
3994	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
3995	}
3996	}
3997
3998	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
3999	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4000	pGMR->numDescriptors = iDescriptor + 1;
4001	}
4002
4003	if (paNewPage64)
4004	RTMemFree(paNewPage64);
4005
4006	# ifdef DEBUG_GMR_ACCESS
4007	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
4008	# endif
4009	break;
4010	}
4011	# endif // VBOX_WITH_VMSVGA3D
4012	case SVGA_CMD_DEFINE_SCREEN:
4013	{
4014	/* The size of this command is specified by the guest and depends on capabilities. */
4015	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4016
4017	SVGAFifoCmdDefineScreen *pCmd;
4018	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4019	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4020	RT_UNTRUSTED_VALIDATED_FENCE();
4021
4022	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4023	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4024	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4025
4026	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4027	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4028	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4029
4030	uint32_t const idScreen = pCmd->screen.id;
4031	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4032
4033	uint32_t const uWidth = pCmd->screen.size.width;
4034	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4035
4036	uint32_t const uHeight = pCmd->screen.size.height;
4037	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4038
4039	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4040	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4041	AssertBreak(cbWidth <= cbPitch);
4042
4043	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4044	AssertBreak(uScreenOffset < pThis->vram_size);
4045
4046	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4047	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4048	AssertBreak( (uHeight == 0 && cbPitch == 0)
4049	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4050	RT_UNTRUSTED_VALIDATED_FENCE();
4051
4052	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4053
4054	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4055
4056	pScreen->fDefined = true;
4057	pScreen->fModified = true;
4058	pScreen->fuScreen = pCmd->screen.flags;
4059	pScreen->idScreen = idScreen;
4060	if (!fBlank)
4061	{
4062	AssertBreak(uWidth > 0 && uHeight > 0);
4063
4064	pScreen->xOrigin = pCmd->screen.root.x;
4065	pScreen->yOrigin = pCmd->screen.root.y;
4066	pScreen->cWidth = uWidth;
4067	pScreen->cHeight = uHeight;
4068	pScreen->offVRAM = uScreenOffset;
4069	pScreen->cbPitch = cbPitch;
4070	pScreen->cBpp = 32;
4071	}
4072	else
4073	{
4074	/* Keep old values. */
4075	}
4076
4077	pThis->svga.fGFBRegisters = false;
4078	vmsvgaChangeMode(pThis);
4079	break;
4080	}
4081
4082	case SVGA_CMD_DESTROY_SCREEN:
4083	{
4084	SVGAFifoCmdDestroyScreen *pCmd;
4085	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4086	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4087
4088	Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4089
4090	uint32_t const idScreen = pCmd->screenId;
4091	AssertBreak(idScreen < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4092	RT_UNTRUSTED_VALIDATED_FENCE();
4093
4094	VMSVGASCREENOBJECT *pScreen = &pThis->svga.pSvgaR3State->aScreens[idScreen];
4095	pScreen->fModified = true;
4096	pScreen->fDefined = false;
4097	pScreen->idScreen = idScreen;
4098
4099	vmsvgaChangeMode(pThis);
4100	break;
4101	}
4102
4103	case SVGA_CMD_DEFINE_GMRFB:
4104	{
4105	SVGAFifoCmdDefineGMRFB *pCmd;
4106	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4107	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4108
4109	Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4110	pSVGAState->GMRFB.ptr = pCmd->ptr;
4111	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4112	pSVGAState->GMRFB.format = pCmd->format;
4113	break;
4114	}
4115
4116	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4117	{
4118	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4119	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4120	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4121
4122	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4123	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4124
4125	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4126	RT_UNTRUSTED_VALIDATED_FENCE();
4127
4128	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->destScreenId);
4129	AssertBreak(pScreen);
4130
4131	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4132	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4133
4134	/* Clip destRect to the screen dimensions. */
4135	SVGASignedRect screenRect;
4136	screenRect.left = 0;
4137	screenRect.top = 0;
4138	screenRect.right = pScreen->cWidth;
4139	screenRect.bottom = pScreen->cHeight;
4140	SVGASignedRect clipRect = pCmd->destRect;
4141	vmsvgaClipRect(&screenRect, &clipRect);
4142	RT_UNTRUSTED_VALIDATED_FENCE();
4143
4144	uint32_t const width = clipRect.right - clipRect.left;
4145	uint32_t const height = clipRect.bottom - clipRect.top;
4146
4147	if ( width == 0
4148	\|\| height == 0)
4149	break; /* Nothing to do. */
4150
4151	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4152	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4153
4154	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4155	* Prepare parameters for vmsvgaGMRTransfer.
4156	*/
4157	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4158
4159	/* Destination: host buffer which describes the screen 0 VRAM.
4160	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4161	*/
4162	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4163	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4164	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4165	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4166	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4167	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4168	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4169	+ cbScanline * clipRect.top;
4170	int32_t const cbHstPitch = cbScanline;
4171
4172	/* Source: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4173	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4174	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4175	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4176	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4177
4178	rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM,
4179	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4180	gstPtr, offGst, cbGstPitch,
4181	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4182	AssertRC(rc);
4183	vmsvgaUpdateScreen(pThis, pScreen, clipRect.left, clipRect.top, width, height);
4184	break;
4185	}
4186
4187	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4188	{
4189	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4190	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4191	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4192
4193	/* Note! This can fetch 3d render results as well!! */
4194	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4195	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4196
4197	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThis->svga.pSvgaR3State->aScreens));
4198	RT_UNTRUSTED_VALIDATED_FENCE();
4199
4200	VMSVGASCREENOBJECT *pScreen = vmsvgaGetScreenObject(pThis, pCmd->srcScreenId);
4201	AssertBreak(pScreen);
4202
4203	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4204	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4205
4206	/* Clip destRect to the screen dimensions. */
4207	SVGASignedRect screenRect;
4208	screenRect.left = 0;
4209	screenRect.top = 0;
4210	screenRect.right = pScreen->cWidth;
4211	screenRect.bottom = pScreen->cHeight;
4212	SVGASignedRect clipRect = pCmd->srcRect;
4213	vmsvgaClipRect(&screenRect, &clipRect);
4214	RT_UNTRUSTED_VALIDATED_FENCE();
4215
4216	uint32_t const width = clipRect.right - clipRect.left;
4217	uint32_t const height = clipRect.bottom - clipRect.top;
4218
4219	if ( width == 0
4220	\|\| height == 0)
4221	break; /* Nothing to do. */
4222
4223	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4224	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4225
4226	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4227	* Prepare parameters for vmsvgaGMRTransfer.
4228	*/
4229	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4230
4231	/* Source: host buffer which describes the screen 0 VRAM.
4232	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaGMRTransfer.
4233	*/
4234	uint8_t * const pbHstBuf = (uint8_t *)pThis->CTX_SUFF(vram_ptr) + pScreen->offVRAM;
4235	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4236	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4237	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4238	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4239	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4240	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4241	+ cbScanline * clipRect.top;
4242	int32_t const cbHstPitch = cbScanline;
4243
4244	/* Destination: GMRFB. vmsvgaGMRTransfer ensures that no memory outside the GMR is read. */
4245	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4246	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4247	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4248	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4249
4250	rc = vmsvgaGMRTransfer(pThis, SVGA3D_READ_HOST_VRAM,
4251	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4252	gstPtr, offGst, cbGstPitch,
4253	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4254	AssertRC(rc);
4255	break;
4256	}
4257
4258	case SVGA_CMD_ANNOTATION_FILL:
4259	{
4260	SVGAFifoCmdAnnotationFill *pCmd;
4261	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4262	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4263
4264	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4265	pSVGAState->colorAnnotation = pCmd->color;
4266	break;
4267	}
4268
4269	case SVGA_CMD_ANNOTATION_COPY:
4270	{
4271	SVGAFifoCmdAnnotationCopy *pCmd;
4272	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4273	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4274
4275	Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4276	AssertFailed();
4277	break;
4278	}
4279
4280	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4281
4282	default:
4283	# ifdef VBOX_WITH_VMSVGA3D
4284	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4285	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4286	{
4287	RT_UNTRUSTED_VALIDATED_FENCE();
4288
4289	/* All 3d commands start with a common header, which defines the size of the command. */
4290	SVGA3dCmdHeader *pHdr;
4291	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4292	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4293	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4294	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4295
4296	if (RT_LIKELY(pThis->svga.f3DEnabled))
4297	{ /* likely */ }
4298	else
4299	{
4300	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4301	break;
4302	}
4303
4304	/**
4305	* Check that the 3D command has at least a_cbMin of payload bytes after the
4306	* header. Will break out of the switch if it doesn't.
4307	*/
4308	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4309	if (1) { \
4310	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4311	RT_UNTRUSTED_VALIDATED_FENCE(); \
4312	} else do {} while (0)
4313	switch ((int)enmCmdId)
4314	{
4315	case SVGA_3D_CMD_SURFACE_DEFINE:
4316	{
4317	uint32_t cMipLevels;
4318	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4319	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4320	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4321
4322	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4323	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4324	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4325	# ifdef DEBUG_GMR_ACCESS
4326	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
4327	# endif
4328	break;
4329	}
4330
4331	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4332	{
4333	uint32_t cMipLevels;
4334	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4335	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4336	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4337
4338	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4339	rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4340	pCmd->multisampleCount, pCmd->autogenFilter,
4341	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4342	break;
4343	}
4344
4345	case SVGA_3D_CMD_SURFACE_DESTROY:
4346	{
4347	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4348	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4349	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4350	rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
4351	break;
4352	}
4353
4354	case SVGA_3D_CMD_SURFACE_COPY:
4355	{
4356	uint32_t cCopyBoxes;
4357	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4358	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4359	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4360
4361	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4362	rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4363	break;
4364	}
4365
4366	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4367	{
4368	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4369	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4370	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4371
4372	rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4373	break;
4374	}
4375
4376	case SVGA_3D_CMD_SURFACE_DMA:
4377	{
4378	uint32_t cCopyBoxes;
4379	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4380	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4381	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4382
4383	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4384	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4385	rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4386	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4387	break;
4388	}
4389
4390	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4391	{
4392	uint32_t cRects;
4393	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4394	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4395	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4396
4397	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4398	rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4399	break;
4400	}
4401
4402	case SVGA_3D_CMD_CONTEXT_DEFINE:
4403	{
4404	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4405	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4406	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4407
4408	rc = vmsvga3dContextDefine(pThis, pCmd->cid);
4409	break;
4410	}
4411
4412	case SVGA_3D_CMD_CONTEXT_DESTROY:
4413	{
4414	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4415	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4416	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4417
4418	rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
4419	break;
4420	}
4421
4422	case SVGA_3D_CMD_SETTRANSFORM:
4423	{
4424	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4425	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4426	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4427
4428	rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
4429	break;
4430	}
4431
4432	case SVGA_3D_CMD_SETZRANGE:
4433	{
4434	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4435	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4436	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4437
4438	rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
4439	break;
4440	}
4441
4442	case SVGA_3D_CMD_SETRENDERSTATE:
4443	{
4444	uint32_t cRenderStates;
4445	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4448
4449	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4450	rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4451	break;
4452	}
4453
4454	case SVGA_3D_CMD_SETRENDERTARGET:
4455	{
4456	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4457	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4458	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4459
4460	rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
4461	break;
4462	}
4463
4464	case SVGA_3D_CMD_SETTEXTURESTATE:
4465	{
4466	uint32_t cTextureStates;
4467	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4468	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4469	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4470
4471	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4472	rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4473	break;
4474	}
4475
4476	case SVGA_3D_CMD_SETMATERIAL:
4477	{
4478	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4479	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4480	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4481
4482	rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
4483	break;
4484	}
4485
4486	case SVGA_3D_CMD_SETLIGHTDATA:
4487	{
4488	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4489	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4490	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4491
4492	rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
4493	break;
4494	}
4495
4496	case SVGA_3D_CMD_SETLIGHTENABLED:
4497	{
4498	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4499	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4500	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4501
4502	rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
4503	break;
4504	}
4505
4506	case SVGA_3D_CMD_SETVIEWPORT:
4507	{
4508	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4509	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4510	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4511
4512	rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
4513	break;
4514	}
4515
4516	case SVGA_3D_CMD_SETCLIPPLANE:
4517	{
4518	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4519	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4520	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4521
4522	rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
4523	break;
4524	}
4525
4526	case SVGA_3D_CMD_CLEAR:
4527	{
4528	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4529	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4530	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4531
4532	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4533	rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4534	break;
4535	}
4536
4537	case SVGA_3D_CMD_PRESENT:
4538	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4539	{
4540	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4541	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4542	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4543	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4544	else
4545	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4546
4547	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4548
4549	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4550	rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4551	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4552	break;
4553	}
4554
4555	case SVGA_3D_CMD_SHADER_DEFINE:
4556	{
4557	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4558	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4559	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4560
4561	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4562	rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4563	break;
4564	}
4565
4566	case SVGA_3D_CMD_SHADER_DESTROY:
4567	{
4568	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4569	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4570	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4571
4572	rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
4573	break;
4574	}
4575
4576	case SVGA_3D_CMD_SET_SHADER:
4577	{
4578	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4579	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4580	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4581
4582	rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4583	break;
4584	}
4585
4586	case SVGA_3D_CMD_SET_SHADER_CONST:
4587	{
4588	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4589	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4590	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4591
4592	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4593	rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4594	break;
4595	}
4596
4597	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4598	{
4599	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4600	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4601	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4602
4603	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4604	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4605	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4606	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4607	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4608
4609	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4610	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4611
4612	RT_UNTRUSTED_VALIDATED_FENCE();
4613
4614	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4615	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4616	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4617
4618	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4619	rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4620	pNumRange, cVertexDivisor, pVertexDivisor);
4621	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4622	break;
4623	}
4624
4625	case SVGA_3D_CMD_SETSCISSORRECT:
4626	{
4627	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4628	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4629	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4630
4631	rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
4632	break;
4633	}
4634
4635	case SVGA_3D_CMD_BEGIN_QUERY:
4636	{
4637	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4638	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4639	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4640
4641	rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
4642	break;
4643	}
4644
4645	case SVGA_3D_CMD_END_QUERY:
4646	{
4647	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4648	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4649	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4650
4651	rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4652	break;
4653	}
4654
4655	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4656	{
4657	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4658	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4659	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4660
4661	rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
4662	break;
4663	}
4664
4665	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4666	{
4667	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4668	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4669	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4670
4671	rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
4672	break;
4673	}
4674
4675	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4676	/* context id + surface id? */
4677	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4678	break;
4679	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4680	/* context id + surface id? */
4681	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4682	break;
4683
4684	default:
4685	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4686	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4687	break;
4688	}
4689	}
4690	else
4691	# endif // VBOX_WITH_VMSVGA3D
4692	{
4693	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4694	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4695	}
4696	}
4697
4698	/* Go to the next slot */
4699	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4700	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4701	if (offCurrentCmd >= offFifoMax)
4702	{
4703	offCurrentCmd -= offFifoMax - offFifoMin;
4704	Assert(offCurrentCmd >= offFifoMin);
4705	Assert(offCurrentCmd < offFifoMax);
4706	}
4707	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4709
4710	/*
4711	* Raise IRQ if required. Must enter the critical section here
4712	* before making final decisions here, otherwise cubebench and
4713	* others may end up waiting forever.
4714	*/
4715	if ( u32IrqStatus
4716	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4717	{
4718	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4719	AssertRC(rc2);
4720
4721	/* FIFO progress might trigger an interrupt. */
4722	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4723	{
4724	Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
4725	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4726	}
4727
4728	/* Unmasked IRQ pending? */
4729	if (pThis->svga.u32IrqMask & u32IrqStatus)
4730	{
4731	Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4732	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4733	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4734	}
4735
4736	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4737	}
4738	}
4739
4740	/* If really done, clear the busy flag. */
4741	if (fDone)
4742	{
4743	Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4744	vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
4745	}
4746	}
4747
4748	/*
4749	* Free the bounce buffer. (There are no returns above!)
4750	*/
4751	RTMemFree(pbBounceBuf);
4752
4753	return VINF_SUCCESS;
4754	}
4755
4756	/**
4757	* Free the specified GMR
4758	*
4759	* @param pThis VGA device instance data.
4760	* @param idGMR GMR id
4761	*/
4762	void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
4763	{
4764	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4765
4766	/* Free the old descriptor if present. */
4767	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4768	if ( pGMR->numDescriptors
4769	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4770	{
4771	# ifdef DEBUG_GMR_ACCESS
4772	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
4773	# endif
4774
4775	Assert(pGMR->paDesc);
4776	RTMemFree(pGMR->paDesc);
4777	pGMR->paDesc = NULL;
4778	pGMR->numDescriptors = 0;
4779	pGMR->cbTotal = 0;
4780	pGMR->cMaxPages = 0;
4781	}
4782	Assert(!pGMR->cMaxPages);
4783	Assert(!pGMR->cbTotal);
4784	}
4785
4786	/**
4787	* Copy between a GMR and a host memory buffer.
4788	*
4789	* @returns VBox status code.
4790	* @param pThis VGA device instance data.
4791	* @param enmTransferType Transfer type (read/write)
4792	* @param pbHstBuf Host buffer pointer (valid)
4793	* @param cbHstBuf Size of host buffer (valid)
4794	* @param offHst Host buffer offset of the first scanline
4795	* @param cbHstPitch Destination buffer pitch
4796	* @param gstPtr GMR description
4797	* @param offGst Guest buffer offset of the first scanline
4798	* @param cbGstPitch Guest buffer pitch
4799	* @param cbWidth Width in bytes to copy
4800	* @param cHeight Number of scanllines to copy
4801	*/
4802	int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType,
4803	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4804	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4805	uint32_t cbWidth, uint32_t cHeight)
4806	{
4807	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4808	int rc;
4809
4810	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4811	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4812	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4813	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4814	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4815
4816	PGMR pGMR;
4817	uint32_t cbGmr; /* The GMR size in bytes. */
4818	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4819	{
4820	pGMR = NULL;
4821	cbGmr = pThis->vram_size;
4822	}
4823	else
4824	{
4825	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4826	RT_UNTRUSTED_VALIDATED_FENCE();
4827	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4828	cbGmr = pGMR->cbTotal;
4829	}
4830
4831	/*
4832	* GMR
4833	*/
4834	/* Calculate GMR offset of the data to be copied. */
4835	AssertMsgReturn(gstPtr.offset < cbGmr,
4836	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4837	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4838	VERR_INVALID_PARAMETER);
4839	RT_UNTRUSTED_VALIDATED_FENCE();
4840	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4841	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4842	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4843	VERR_INVALID_PARAMETER);
4844	RT_UNTRUSTED_VALIDATED_FENCE();
4845	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4846
4847	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4848	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4849	AssertMsgReturn(cbGmrScanline != 0,
4850	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4851	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4852	VERR_INVALID_PARAMETER);
4853	RT_UNTRUSTED_VALIDATED_FENCE();
4854	AssertMsgReturn(cbWidth <= cbGmrScanline,
4855	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4856	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4857	VERR_INVALID_PARAMETER);
4858	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4859	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4860	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4861	VERR_INVALID_PARAMETER);
4862	RT_UNTRUSTED_VALIDATED_FENCE();
4863
4864	/* How many bytes are available for the data in the GMR. */
4865	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4866
4867	/* How many scanlines would fit into the available data. */
4868	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4869	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4870	if (cbWidth <= cbGmrLastScanline)
4871	++cGmrScanlines;
4872
4873	if (cHeight > cGmrScanlines)
4874	cHeight = cGmrScanlines;
4875
4876	AssertMsgReturn(cHeight > 0,
4877	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4878	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4879	VERR_INVALID_PARAMETER);
4880	RT_UNTRUSTED_VALIDATED_FENCE();
4881
4882	/*
4883	* Host buffer.
4884	*/
4885	AssertMsgReturn(offHst < cbHstBuf,
4886	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4887	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4888	VERR_INVALID_PARAMETER);
4889
4890	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4891	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4892	AssertMsgReturn(cbHstScanline != 0,
4893	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4894	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4895	VERR_INVALID_PARAMETER);
4896	AssertMsgReturn(cbWidth <= cbHstScanline,
4897	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4898	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4899	VERR_INVALID_PARAMETER);
4900	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4901	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4902	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4903	VERR_INVALID_PARAMETER);
4904
4905	/* How many bytes are available for the data in the buffer. */
4906	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4907
4908	/* How many scanlines would fit into the available data. */
4909	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4910	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4911	if (cbWidth <= cbHstLastScanline)
4912	++cHstScanlines;
4913
4914	if (cHeight > cHstScanlines)
4915	cHeight = cHstScanlines;
4916
4917	AssertMsgReturn(cHeight > 0,
4918	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4919	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4920	VERR_INVALID_PARAMETER);
4921
4922	uint8_t *pbHst = pbHstBuf + offHst;
4923
4924	/* Shortcut for the framebuffer. */
4925	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4926	{
4927	uint8_t *pbGst = pThis->CTX_SUFF(vram_ptr) + offGmr;
4928
4929	uint8_t const *pbSrc;
4930	int32_t cbSrcPitch;
4931	uint8_t *pbDst;
4932	int32_t cbDstPitch;
4933
4934	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4935	{
4936	pbSrc = pbHst;
4937	cbSrcPitch = cbHstPitch;
4938	pbDst = pbGst;
4939	cbDstPitch = cbGstPitch;
4940	}
4941	else
4942	{
4943	pbSrc = pbGst;
4944	cbSrcPitch = cbGstPitch;
4945	pbDst = pbHst;
4946	cbDstPitch = cbHstPitch;
4947	}
4948
4949	if ( cbWidth == (uint32_t)cbGstPitch
4950	&& cbGstPitch == cbHstPitch)
4951	{
4952	/* Entire scanlines, positive pitch. */
4953	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4954	}
4955	else
4956	{
4957	for (uint32_t i = 0; i < cHeight; ++i)
4958	{
4959	memcpy(pbDst, pbSrc, cbWidth);
4960
4961	pbDst += cbDstPitch;
4962	pbSrc += cbSrcPitch;
4963	}
4964	}
4965	return VINF_SUCCESS;
4966	}
4967
4968	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
4969	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
4970
4971	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
4972	uint32_t iDesc = 0; /* Index in the descriptor array. */
4973	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
4974	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
4975	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
4976	for (uint32_t i = 0; i < cHeight; ++i)
4977	{
4978	uint32_t cbCurrentWidth = cbWidth;
4979	uint32_t offGmrCurrent = offGmrScanline;
4980	uint8_t *pbCurrentHost = pbHstScanline;
4981
4982	/* Find the right descriptor */
4983	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
4984	{
4985	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
4986	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
4987	++iDesc;
4988	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
4989	}
4990
4991	while (cbCurrentWidth)
4992	{
4993	uint32_t cbToCopy;
4994
4995	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
4996	{
4997	cbToCopy = cbCurrentWidth;
4998	}
4999	else
5000	{
5001	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5002	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5003	}
5004
5005	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5006
5007	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5008
5009	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5010	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5011	else
5012	rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pbCurrentHost, cbToCopy);
5013	AssertRCBreak(rc);
5014
5015	cbCurrentWidth -= cbToCopy;
5016	offGmrCurrent += cbToCopy;
5017	pbCurrentHost += cbToCopy;
5018
5019	/* Go to the next descriptor if there's anything left. */
5020	if (cbCurrentWidth)
5021	{
5022	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5023	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5024	++iDesc;
5025	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5026	}
5027	}
5028
5029	offGmrScanline += cbGstPitch;
5030	pbHstScanline += cbHstPitch;
5031	}
5032
5033	return VINF_SUCCESS;
5034	}
5035
5036
5037	/**
5038	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5039	*
5040	* @param pSizeSrc Source surface dimensions.
5041	* @param pSizeDest Destination surface dimensions.
5042	* @param pBox Coordinates to be clipped.
5043	*/
5044	void vmsvgaClipCopyBox(const SVGA3dSize *pSizeSrc,
5045	const SVGA3dSize *pSizeDest,
5046	SVGA3dCopyBox *pBox)
5047	{
5048	/* Src x, w */
5049	if (pBox->srcx > pSizeSrc->width)
5050	pBox->srcx = pSizeSrc->width;
5051	if (pBox->w > pSizeSrc->width - pBox->srcx)
5052	pBox->w = pSizeSrc->width - pBox->srcx;
5053
5054	/* Src y, h */
5055	if (pBox->srcy > pSizeSrc->height)
5056	pBox->srcy = pSizeSrc->height;
5057	if (pBox->h > pSizeSrc->height - pBox->srcy)
5058	pBox->h = pSizeSrc->height - pBox->srcy;
5059
5060	/* Src z, d */
5061	if (pBox->srcz > pSizeSrc->depth)
5062	pBox->srcz = pSizeSrc->depth;
5063	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5064	pBox->d = pSizeSrc->depth - pBox->srcz;
5065
5066	/* Dest x, w */
5067	if (pBox->x > pSizeDest->width)
5068	pBox->x = pSizeDest->width;
5069	if (pBox->w > pSizeDest->width - pBox->x)
5070	pBox->w = pSizeDest->width - pBox->x;
5071
5072	/* Dest y, h */
5073	if (pBox->y > pSizeDest->height)
5074	pBox->y = pSizeDest->height;
5075	if (pBox->h > pSizeDest->height - pBox->y)
5076	pBox->h = pSizeDest->height - pBox->y;
5077
5078	/* Dest z, d */
5079	if (pBox->z > pSizeDest->depth)
5080	pBox->z = pSizeDest->depth;
5081	if (pBox->d > pSizeDest->depth - pBox->z)
5082	pBox->d = pSizeDest->depth - pBox->z;
5083	}
5084
5085	/**
5086	* Unsigned coordinates in pBox. Clip to [0; pSize).
5087	*
5088	* @param pSize Source surface dimensions.
5089	* @param pBox Coordinates to be clipped.
5090	*/
5091	void vmsvgaClipBox(const SVGA3dSize *pSize,
5092	SVGA3dBox *pBox)
5093	{
5094	/* x, w */
5095	if (pBox->x > pSize->width)
5096	pBox->x = pSize->width;
5097	if (pBox->w > pSize->width - pBox->x)
5098	pBox->w = pSize->width - pBox->x;
5099
5100	/* y, h */
5101	if (pBox->y > pSize->height)
5102	pBox->y = pSize->height;
5103	if (pBox->h > pSize->height - pBox->y)
5104	pBox->h = pSize->height - pBox->y;
5105
5106	/* z, d */
5107	if (pBox->z > pSize->depth)
5108	pBox->z = pSize->depth;
5109	if (pBox->d > pSize->depth - pBox->z)
5110	pBox->d = pSize->depth - pBox->z;
5111	}
5112
5113	/**
5114	* Clip.
5115	*
5116	* @param pBound Bounding rectangle.
5117	* @param pRect Rectangle to be clipped.
5118	*/
5119	void vmsvgaClipRect(SVGASignedRect const *pBound,
5120	SVGASignedRect *pRect)
5121	{
5122	int32_t left;
5123	int32_t top;
5124	int32_t right;
5125	int32_t bottom;
5126
5127	/* Right order. */
5128	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5129	if (pRect->left < pRect->right)
5130	{
5131	left = pRect->left;
5132	right = pRect->right;
5133	}
5134	else
5135	{
5136	left = pRect->right;
5137	right = pRect->left;
5138	}
5139	if (pRect->top < pRect->bottom)
5140	{
5141	top = pRect->top;
5142	bottom = pRect->bottom;
5143	}
5144	else
5145	{
5146	top = pRect->bottom;
5147	bottom = pRect->top;
5148	}
5149
5150	if (left < pBound->left)
5151	left = pBound->left;
5152	if (right < pBound->left)
5153	right = pBound->left;
5154
5155	if (left > pBound->right)
5156	left = pBound->right;
5157	if (right > pBound->right)
5158	right = pBound->right;
5159
5160	if (top < pBound->top)
5161	top = pBound->top;
5162	if (bottom < pBound->top)
5163	bottom = pBound->top;
5164
5165	if (top > pBound->bottom)
5166	top = pBound->bottom;
5167	if (bottom > pBound->bottom)
5168	bottom = pBound->bottom;
5169
5170	pRect->left = left;
5171	pRect->right = right;
5172	pRect->top = top;
5173	pRect->bottom = bottom;
5174	}
5175
5176	/**
5177	* Unblock the FIFO I/O thread so it can respond to a state change.
5178	*
5179	* @returns VBox status code.
5180	* @param pDevIns The VGA device instance.
5181	* @param pThread The send thread.
5182	*/
5183	static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5184	{
5185	RT_NOREF(pDevIns);
5186	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5187	Log(("vmsvgaFIFOLoopWakeUp\n"));
5188	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5189	}
5190
5191	/**
5192	* Enables or disables dirty page tracking for the framebuffer
5193	*
5194	* @param pThis VGA device instance data.
5195	* @param fTraces Enable/disable traces
5196	*/
5197	static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
5198	{
5199	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5200	&& !fTraces)
5201	{
5202	//Assert(pThis->svga.fTraces);
5203	Log(("vmsvgaSetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5204	return;
5205	}
5206
5207	pThis->svga.fTraces = fTraces;
5208	if (pThis->svga.fTraces)
5209	{
5210	unsigned cbFrameBuffer = pThis->vram_size;
5211
5212	Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5213	/** @todo How does this work with screens? */
5214	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5215	{
5216	#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5217	Assert(pThis->svga.cbScanline);
5218	#endif
5219	/* Hardware enabled; return real framebuffer size .*/
5220	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5221	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5222	}
5223
5224	if (!pThis->svga.fVRAMTracking)
5225	{
5226	Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5227	vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
5228	pThis->svga.fVRAMTracking = true;
5229	}
5230	}
5231	else
5232	{
5233	if (pThis->svga.fVRAMTracking)
5234	{
5235	Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
5236	vgaR3UnregisterVRAMHandler(pThis);
5237	pThis->svga.fVRAMTracking = false;
5238	}
5239	}
5240	}
5241
5242	/**
5243	* @callback_method_impl{FNPCIIOREGIONMAP}
5244	*/
5245	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5246	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5247	{
5248	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5249	int rc;
5250	RT_NOREF(pPciDev);
5251	Assert(pPciDev == pDevIns->apPciDevs[0]);
5252
5253	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5254	AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5255	if (GCPhysAddress != NIL_RTGCPHYS)
5256	{
5257	/*
5258	* Mapping the FIFO RAM.
5259	*/
5260	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5261	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5262	AssertRC(rc);
5263
5264	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5265	if (RT_SUCCESS(rc))
5266	{
5267	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5268	# ifdef DEBUG_FIFO_ACCESS
5269	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5270	# else
5271	GCPhysAddress + PAGE_SIZE - 1,
5272	# endif
5273	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5274	"VMSVGA FIFO");
5275	AssertRC(rc);
5276	}
5277	# endif
5278	if (RT_SUCCESS(rc))
5279	{
5280	pThis->svga.GCPhysFIFO = GCPhysAddress;
5281	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5282	}
5283	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5284	}
5285	else
5286	{
5287	Assert(pThis->svga.GCPhysFIFO);
5288	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5289	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5290	AssertRC(rc);
5291	# else
5292	rc = VINF_SUCCESS;
5293	# endif
5294	pThis->svga.GCPhysFIFO = 0;
5295	}
5296	return rc;
5297	}
5298
5299	# ifdef VBOX_WITH_VMSVGA3D
5300
5301	/**
5302	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5303	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5304	*
5305	* @param pDevIns The device instance.
5306	* @param pThis The VGA device instance data.
5307	* @param sid Either UINT32_MAX or the ID of a specific
5308	* surface. If UINT32_MAX is used, all surfaces
5309	* are processed.
5310	*/
5311	void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t sid)
5312	{
5313	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5314	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5315	}
5316
5317
5318	/**
5319	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5320	*/
5321	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5322	{
5323	/* There might be a specific surface ID at the start of the
5324	arguments, if not show all surfaces. */
5325	uint32_t sid = UINT32_MAX;
5326	if (pszArgs)
5327	pszArgs = RTStrStripL(pszArgs);
5328	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5329	sid = RTStrToUInt32(pszArgs);
5330
5331	/* Verbose or terse display, we default to verbose. */
5332	bool fVerbose = true;
5333	if (RTStrIStr(pszArgs, "terse"))
5334	fVerbose = false;
5335
5336	/* The size of the ascii art (x direction, y is 3/4 of x). */
5337	uint32_t cxAscii = 80;
5338	if (RTStrIStr(pszArgs, "gigantic"))
5339	cxAscii = 300;
5340	else if (RTStrIStr(pszArgs, "huge"))
5341	cxAscii = 180;
5342	else if (RTStrIStr(pszArgs, "big"))
5343	cxAscii = 132;
5344	else if (RTStrIStr(pszArgs, "normal"))
5345	cxAscii = 80;
5346	else if (RTStrIStr(pszArgs, "medium"))
5347	cxAscii = 64;
5348	else if (RTStrIStr(pszArgs, "small"))
5349	cxAscii = 48;
5350	else if (RTStrIStr(pszArgs, "tiny"))
5351	cxAscii = 24;
5352
5353	/* Y invert the image when producing the ASCII art. */
5354	bool fInvY = false;
5355	if (RTStrIStr(pszArgs, "invy"))
5356	fInvY = true;
5357
5358	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5359	}
5360
5361
5362	/**
5363	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5364	*/
5365	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5366	{
5367	/* pszArg = "sid[>dir]"
5368	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5369	*/
5370	char *pszBitmapPath = NULL;
5371	uint32_t sid = UINT32_MAX;
5372	if (pszArgs)
5373	pszArgs = RTStrStripL(pszArgs);
5374	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5375	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5376	if ( pszBitmapPath
5377	&& *pszBitmapPath == '>')
5378	++pszBitmapPath;
5379
5380	const bool fVerbose = true;
5381	const uint32_t cxAscii = 0; /* No ASCII */
5382	const bool fInvY = false; /* Do not invert. */
5383	vmsvga3dInfoSurfaceWorker(pDevIns, PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5384	}
5385
5386
5387	/**
5388	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5389	*/
5390	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5391	{
5392	/* There might be a specific surface ID at the start of the
5393	arguments, if not show all contexts. */
5394	uint32_t sid = UINT32_MAX;
5395	if (pszArgs)
5396	pszArgs = RTStrStripL(pszArgs);
5397	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5398	sid = RTStrToUInt32(pszArgs);
5399
5400	/* Verbose or terse display, we default to verbose. */
5401	bool fVerbose = true;
5402	if (RTStrIStr(pszArgs, "terse"))
5403	fVerbose = false;
5404
5405	vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
5406	}
5407
5408	# endif /* VBOX_WITH_VMSVGA3D */
5409
5410	/**
5411	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5412	*/
5413	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5414	{
5415	RT_NOREF(pszArgs);
5416	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5417	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5418	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThis->svga.pFIFOR3;
5419
5420	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5421	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5422	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5423	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5424	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5425	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5426	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5427	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5428	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5429	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5430	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5431	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5432	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5433	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5434	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5435	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5436	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5437	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5438	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5439	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5440	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5441	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5442	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5443	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5444	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5445
5446	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5447	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5448	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5449	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5450
5451	# ifdef VBOX_WITH_VMSVGA3D
5452	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5453	# endif
5454	if (pThis->pDrv)
5455	{
5456	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThis->pDrv->cx, pThis->pDrv->cy, pThis->pDrv->cBits);
5457	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThis->pDrv->cbScanline, pThis->pDrv->cbScanline);
5458	}
5459	}
5460
5461	/** Portion of VMSVGA state which must be loaded oin the FIFO thread.
5462	*/
5463	static int vmsvgaLoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5464	{
5465	RT_NOREF(uPass);
5466
5467	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5468	int rc;
5469
5470	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5471	{
5472	uint32_t cScreens = 0;
5473	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5474	AssertRCReturn(rc, rc);
5475	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5476	("cScreens=%#x\n", cScreens),
5477	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5478
5479	for (uint32_t i = 0; i < cScreens; ++i)
5480	{
5481	VMSVGASCREENOBJECT screen;
5482	RT_ZERO(screen);
5483
5484	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5485	AssertLogRelRCReturn(rc, rc);
5486
5487	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5488	{
5489	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5490	*pScreen = screen;
5491	pScreen->fModified = true;
5492	}
5493	else
5494	{
5495	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5496	}
5497	}
5498	}
5499	else
5500	{
5501	/* Try to setup at least the first screen. */
5502	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5503	pScreen->fDefined = true;
5504	pScreen->fModified = true;
5505	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5506	pScreen->idScreen = 0;
5507	pScreen->xOrigin = 0;
5508	pScreen->yOrigin = 0;
5509	pScreen->offVRAM = pThis->svga.uScreenOffset;
5510	pScreen->cbPitch = pThis->svga.cbScanline;
5511	pScreen->cWidth = pThis->svga.uWidth;
5512	pScreen->cHeight = pThis->svga.uHeight;
5513	pScreen->cBpp = pThis->svga.uBpp;
5514	}
5515
5516	return VINF_SUCCESS;
5517	}
5518
5519	/**
5520	* @copydoc FNSSMDEVLOADEXEC
5521	*/
5522	int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5523	{
5524	RT_NOREF(uPass);
5525	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5526	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5527	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5528	int rc;
5529
5530	/* Load our part of the VGAState */
5531	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5532	AssertRCReturn(rc, rc);
5533
5534	/* Load the VGA framebuffer. */
5535	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5536	uint32_t cbVgaFramebuffer = _32K;
5537	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5538	{
5539	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5540	AssertRCReturn(rc, rc);
5541	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5542	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5543	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5544	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5545	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5546	}
5547	rc = pHlp->pfnSSMGetMem(pSSM, pThis->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5548	AssertRCReturn(rc, rc);
5549	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5550	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5551	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5552	RT_BZERO(&pThis->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5553
5554	/* Load the VMSVGA state. */
5555	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5556	AssertRCReturn(rc, rc);
5557
5558	/* Load the active cursor bitmaps. */
5559	if (pSVGAState->Cursor.fActive)
5560	{
5561	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5562	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5563
5564	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5565	AssertRCReturn(rc, rc);
5566	}
5567
5568	/* Load the GMR state. */
5569	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5570	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5571	{
5572	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5573	AssertRCReturn(rc, rc);
5574	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5575	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5576	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5577	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5578	}
5579
5580	if (pThis->svga.cGMR != cGMR)
5581	{
5582	/* Reallocate GMR array. */
5583	Assert(pSVGAState->paGMR != NULL);
5584	RTMemFree(pSVGAState->paGMR);
5585	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5586	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5587	pThis->svga.cGMR = cGMR;
5588	}
5589
5590	for (uint32_t i = 0; i < cGMR; ++i)
5591	{
5592	PGMR pGMR = &pSVGAState->paGMR[i];
5593
5594	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5595	AssertRCReturn(rc, rc);
5596
5597	if (pGMR->numDescriptors)
5598	{
5599	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5600	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5601	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5602
5603	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5604	{
5605	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5606	AssertRCReturn(rc, rc);
5607	}
5608	}
5609	}
5610
5611	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5612	vmsvga3dPowerOn(pThis);
5613	# endif
5614
5615	VMSVGA_STATE_LOAD LoadState;
5616	LoadState.pSSM = pSSM;
5617	LoadState.uVersion = uVersion;
5618	LoadState.uPass = uPass;
5619	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5620	AssertLogRelRCReturn(rc, rc);
5621
5622	return VINF_SUCCESS;
5623	}
5624
5625	/**
5626	* Reinit the video mode after the state has been loaded.
5627	*/
5628	int vmsvgaLoadDone(PPDMDEVINS pDevIns)
5629	{
5630	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5631	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5632
5633	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5634
5635	/* Set the active cursor. */
5636	if (pSVGAState->Cursor.fActive)
5637	{
5638	int rc;
5639
5640	rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
5641	true,
5642	true,
5643	pSVGAState->Cursor.xHotspot,
5644	pSVGAState->Cursor.yHotspot,
5645	pSVGAState->Cursor.width,
5646	pSVGAState->Cursor.height,
5647	pSVGAState->Cursor.pData);
5648	AssertRC(rc);
5649	}
5650	return VINF_SUCCESS;
5651	}
5652
5653	/**
5654	* Portion of SVGA state which must be saved in the FIFO thread.
5655	*/
5656	static int vmsvgaSaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5657	{
5658	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5659	int rc;
5660
5661	/* Save the screen objects. */
5662	/* Count defined screen object. */
5663	uint32_t cScreens = 0;
5664	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5665	{
5666	if (pSVGAState->aScreens[i].fDefined)
5667	++cScreens;
5668	}
5669
5670	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5671	AssertLogRelRCReturn(rc, rc);
5672
5673	for (uint32_t i = 0; i < cScreens; ++i)
5674	{
5675	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5676
5677	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5678	AssertLogRelRCReturn(rc, rc);
5679	}
5680	return VINF_SUCCESS;
5681	}
5682
5683	/**
5684	* @copydoc FNSSMDEVSAVEEXEC
5685	*/
5686	int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5687	{
5688	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5689	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5690	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5691	int rc;
5692
5693	/* Save our part of the VGAState */
5694	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5695	AssertLogRelRCReturn(rc, rc);
5696
5697	/* Save the framebuffer backup. */
5698	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5699	rc = pHlp->pfnSSMPutMem(pSSM, pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5700	AssertLogRelRCReturn(rc, rc);
5701
5702	/* Save the VMSVGA state. */
5703	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5704	AssertLogRelRCReturn(rc, rc);
5705
5706	/* Save the active cursor bitmaps. */
5707	if (pSVGAState->Cursor.fActive)
5708	{
5709	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5710	AssertLogRelRCReturn(rc, rc);
5711	}
5712
5713	/* Save the GMR state */
5714	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5715	AssertLogRelRCReturn(rc, rc);
5716	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5717	{
5718	PGMR pGMR = &pSVGAState->paGMR[i];
5719
5720	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5721	AssertLogRelRCReturn(rc, rc);
5722
5723	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5724	{
5725	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5726	AssertLogRelRCReturn(rc, rc);
5727	}
5728	}
5729
5730	/*
5731	* Must save some state (3D in particular) in the FIFO thread.
5732	*/
5733	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5734	AssertLogRelRCReturn(rc, rc);
5735
5736	return VINF_SUCCESS;
5737	}
5738
5739	/**
5740	* Destructor for PVMSVGAR3STATE structure.
5741	*
5742	* @param pThis The VGA instance.
5743	* @param pSVGAState Pointer to the structure. It is not deallocated.
5744	*/
5745	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5746	{
5747	#ifndef VMSVGA_USE_EMT_HALT_CODE
5748	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5749	{
5750	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5751	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5752	}
5753	#endif
5754
5755	if (pSVGAState->Cursor.fActive)
5756	{
5757	RTMemFree(pSVGAState->Cursor.pData);
5758	pSVGAState->Cursor.pData = NULL;
5759	pSVGAState->Cursor.fActive = false;
5760	}
5761
5762	if (pSVGAState->paGMR)
5763	{
5764	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5765	if (pSVGAState->paGMR[i].paDesc)
5766	RTMemFree(pSVGAState->paGMR[i].paDesc);
5767
5768	RTMemFree(pSVGAState->paGMR);
5769	pSVGAState->paGMR = NULL;
5770	}
5771	}
5772
5773	/**
5774	* Constructor for PVMSVGAR3STATE structure.
5775	*
5776	* @returns VBox status code.
5777	* @param pThis The VGA instance.
5778	* @param pSVGAState Pointer to the structure. It is already allocated.
5779	*/
5780	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5781	{
5782	int rc = VINF_SUCCESS;
5783	RT_ZERO(*pSVGAState);
5784
5785	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5786	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5787
5788	#ifndef VMSVGA_USE_EMT_HALT_CODE
5789	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5790	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5791	AssertRCReturn(rc, rc);
5792	#endif
5793
5794	return rc;
5795	}
5796
5797	/**
5798	* Initializes the host capabilities: registers and FIFO.
5799	*
5800	* @returns VBox status code.
5801	* @param pThis The VGA instance.
5802	*/
5803	static void vmsvgaInitCaps(PVGASTATE pThis)
5804	{
5805	/* Register caps. */
5806	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5807	\| SVGA_CAP_GMR2
5808	\| SVGA_CAP_CURSOR
5809	\| SVGA_CAP_CURSOR_BYPASS_2
5810	\| SVGA_CAP_EXTENDED_FIFO
5811	\| SVGA_CAP_IRQMASK
5812	\| SVGA_CAP_PITCHLOCK
5813	\| SVGA_CAP_TRACES
5814	\| SVGA_CAP_SCREEN_OBJECT_2
5815	\| SVGA_CAP_ALPHA_CURSOR;
5816	# ifdef VBOX_WITH_VMSVGA3D
5817	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5818	# endif
5819
5820	/* Clear the FIFO. */
5821	RT_BZERO(pThis->svga.pFIFOR3, pThis->svga.cbFIFO);
5822
5823	/* Setup FIFO capabilities. */
5824	pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5825	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5826	\| SVGA_FIFO_CAP_GMR2
5827	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5828	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5829	\| SVGA_FIFO_CAP_RESERVE
5830	\| SVGA_FIFO_CAP_PITCHLOCK;
5831
5832	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5833	pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5834	}
5835
5836	# ifdef VBOX_WITH_VMSVGA3D
5837	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5838	static const char * const g_apszVmSvgaDevCapNames[] =
5839	{
5840	"x3D", /* = 0 */
5841	"xMAX_LIGHTS",
5842	"xMAX_TEXTURES",
5843	"xMAX_CLIP_PLANES",
5844	"xVERTEX_SHADER_VERSION",
5845	"xVERTEX_SHADER",
5846	"xFRAGMENT_SHADER_VERSION",
5847	"xFRAGMENT_SHADER",
5848	"xMAX_RENDER_TARGETS",
5849	"xS23E8_TEXTURES",
5850	"xS10E5_TEXTURES",
5851	"xMAX_FIXED_VERTEXBLEND",
5852	"xD16_BUFFER_FORMAT",
5853	"xD24S8_BUFFER_FORMAT",
5854	"xD24X8_BUFFER_FORMAT",
5855	"xQUERY_TYPES",
5856	"xTEXTURE_GRADIENT_SAMPLING",
5857	"rMAX_POINT_SIZE",
5858	"xMAX_SHADER_TEXTURES",
5859	"xMAX_TEXTURE_WIDTH",
5860	"xMAX_TEXTURE_HEIGHT",
5861	"xMAX_VOLUME_EXTENT",
5862	"xMAX_TEXTURE_REPEAT",
5863	"xMAX_TEXTURE_ASPECT_RATIO",
5864	"xMAX_TEXTURE_ANISOTROPY",
5865	"xMAX_PRIMITIVE_COUNT",
5866	"xMAX_VERTEX_INDEX",
5867	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5868	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5869	"xMAX_VERTEX_SHADER_TEMPS",
5870	"xMAX_FRAGMENT_SHADER_TEMPS",
5871	"xTEXTURE_OPS",
5872	"xSURFACEFMT_X8R8G8B8",
5873	"xSURFACEFMT_A8R8G8B8",
5874	"xSURFACEFMT_A2R10G10B10",
5875	"xSURFACEFMT_X1R5G5B5",
5876	"xSURFACEFMT_A1R5G5B5",
5877	"xSURFACEFMT_A4R4G4B4",
5878	"xSURFACEFMT_R5G6B5",
5879	"xSURFACEFMT_LUMINANCE16",
5880	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5881	"xSURFACEFMT_ALPHA8",
5882	"xSURFACEFMT_LUMINANCE8",
5883	"xSURFACEFMT_Z_D16",
5884	"xSURFACEFMT_Z_D24S8",
5885	"xSURFACEFMT_Z_D24X8",
5886	"xSURFACEFMT_DXT1",
5887	"xSURFACEFMT_DXT2",
5888	"xSURFACEFMT_DXT3",
5889	"xSURFACEFMT_DXT4",
5890	"xSURFACEFMT_DXT5",
5891	"xSURFACEFMT_BUMPX8L8V8U8",
5892	"xSURFACEFMT_A2W10V10U10",
5893	"xSURFACEFMT_BUMPU8V8",
5894	"xSURFACEFMT_Q8W8V8U8",
5895	"xSURFACEFMT_CxV8U8",
5896	"xSURFACEFMT_R_S10E5",
5897	"xSURFACEFMT_R_S23E8",
5898	"xSURFACEFMT_RG_S10E5",
5899	"xSURFACEFMT_RG_S23E8",
5900	"xSURFACEFMT_ARGB_S10E5",
5901	"xSURFACEFMT_ARGB_S23E8",
5902	"xMISSING62",
5903	"xMAX_VERTEX_SHADER_TEXTURES",
5904	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5905	"xSURFACEFMT_V16U16",
5906	"xSURFACEFMT_G16R16",
5907	"xSURFACEFMT_A16B16G16R16",
5908	"xSURFACEFMT_UYVY",
5909	"xSURFACEFMT_YUY2",
5910	"xMULTISAMPLE_NONMASKABLESAMPLES",
5911	"xMULTISAMPLE_MASKABLESAMPLES",
5912	"xALPHATOCOVERAGE",
5913	"xSUPERSAMPLE",
5914	"xAUTOGENMIPMAPS",
5915	"xSURFACEFMT_NV12",
5916	"xSURFACEFMT_AYUV",
5917	"xMAX_CONTEXT_IDS",
5918	"xMAX_SURFACE_IDS",
5919	"xSURFACEFMT_Z_DF16",
5920	"xSURFACEFMT_Z_DF24",
5921	"xSURFACEFMT_Z_D24S8_INT",
5922	"xSURFACEFMT_BC4_UNORM",
5923	"xSURFACEFMT_BC5_UNORM", /* 83 */
5924	};
5925
5926	/**
5927	* Initializes the host 3D capabilities in FIFO.
5928	*
5929	* @returns VBox status code.
5930	* @param pThis The VGA instance.
5931	*/
5932	static void vmsvgaInitFifo3DCaps(PVGASTATE pThis)
5933	{
5934	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5935	bool fSavedBuffering = RTLogRelSetBuffering(true);
5936	SVGA3dCapsRecord *pCaps;
5937	SVGA3dCapPair *pData;
5938	uint32_t idxCap = 0;
5939
5940	/* 3d hardware version; latest and greatest */
5941	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5942	pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5943
5944	pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
5945	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5946	pData = (SVGA3dCapPair *)&pCaps->data;
5947
5948	/* Fill out all 3d capabilities. */
5949	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5950	{
5951	uint32_t val = 0;
5952
5953	int rc = vmsvga3dQueryCaps(pThis, i, &val);
5954	if (RT_SUCCESS(rc))
5955	{
5956	pData[idxCap][0] = i;
5957	pData[idxCap][1] = val;
5958	idxCap++;
5959	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
5960	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
5961	else
5962	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
5963	&g_apszVmSvgaDevCapNames[i][1]));
5964	}
5965	else
5966	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
5967	}
5968	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5969	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5970
5971	/* Mark end of record array. */
5972	pCaps->header.length = 0;
5973
5974	RTLogRelSetBuffering(fSavedBuffering);
5975	}
5976
5977	# endif
5978
5979	/**
5980	* Resets the SVGA hardware state
5981	*
5982	* @returns VBox status code.
5983	* @param pDevIns The device instance.
5984	*/
5985	int vmsvgaReset(PPDMDEVINS pDevIns)
5986	{
5987	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
5988	PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
5989
5990	/* Reset before init? */
5991	if (!pSVGAState)
5992	return VINF_SUCCESS;
5993
5994	Log(("vmsvgaReset\n"));
5995
5996	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5997	pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5998	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5999
6000	/* Reset other stuff. */
6001	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6002	RT_ZERO(pThis->svga.au32ScratchRegion);
6003
6004	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6005	vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6006
6007	RT_BZERO(pThis->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6008
6009	/* Initialize FIFO and register capabilities. */
6010	vmsvgaInitCaps(pThis);
6011
6012	# ifdef VBOX_WITH_VMSVGA3D
6013	if (pThis->svga.f3DEnabled)
6014	vmsvgaInitFifo3DCaps(pThis);
6015	# endif
6016
6017	/* VRAM tracking is enabled by default during bootup. */
6018	pThis->svga.fVRAMTracking = true;
6019	pThis->svga.fEnabled = false;
6020
6021	/* Invalidate current settings. */
6022	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6023	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6024	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6025	pThis->svga.cbScanline = 0;
6026	pThis->svga.u32PitchLock = 0;
6027
6028	return rc;
6029	}
6030
6031	/**
6032	* Cleans up the SVGA hardware state
6033	*
6034	* @returns VBox status code.
6035	* @param pDevIns The device instance.
6036	*/
6037	int vmsvgaDestruct(PPDMDEVINS pDevIns)
6038	{
6039	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6040
6041	/*
6042	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6043	*/
6044	if (pThis->svga.pFIFOIOThread)
6045	{
6046	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /pvParam/, 30000 /ms/);
6047	AssertLogRelRC(rc);
6048
6049	rc = PDMDevHlpThreadDestroy(pDevIns, pThis->svga.pFIFOIOThread, NULL);
6050	AssertLogRelRC(rc);
6051	pThis->svga.pFIFOIOThread = NULL;
6052	}
6053
6054	/*
6055	* Destroy the special SVGA state.
6056	*/
6057	if (pThis->svga.pSvgaR3State)
6058	{
6059	vmsvgaR3StateTerm(pThis, pThis->svga.pSvgaR3State);
6060
6061	RTMemFree(pThis->svga.pSvgaR3State);
6062	pThis->svga.pSvgaR3State = NULL;
6063	}
6064
6065	/*
6066	* Free our resources residing in the VGA state.
6067	*/
6068	if (pThis->svga.pbVgaFrameBufferR3)
6069	{
6070	RTMemFree(pThis->svga.pbVgaFrameBufferR3);
6071	pThis->svga.pbVgaFrameBufferR3 = NULL;
6072	}
6073	if (pThis->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6074	{
6075	RTSemEventDestroy(pThis->svga.hFIFOExtCmdSem);
6076	pThis->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6077	}
6078	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6079	{
6080	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6081	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6082	}
6083
6084	return VINF_SUCCESS;
6085	}
6086
6087	/**
6088	* Initialize the SVGA hardware state
6089	*
6090	* @returns VBox status code.
6091	* @param pDevIns The device instance.
6092	*/
6093	int vmsvgaInit(PPDMDEVINS pDevIns)
6094	{
6095	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6096	PVMSVGAR3STATE pSVGAState;
6097	int rc;
6098
6099	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6100	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6101
6102	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6103
6104	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6105	pThis->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6106	AssertReturn(pThis->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6107
6108	/* Create event semaphore. */
6109	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6110	AssertRCReturn(rc, rc);
6111
6112	/* Create event semaphore. */
6113	rc = RTSemEventCreate(&pThis->svga.hFIFOExtCmdSem);
6114	AssertRCReturn(rc, rc);
6115
6116	pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6117	AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
6118
6119	rc = vmsvgaR3StateInit(pThis, pThis->svga.pSvgaR3State);
6120	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6121
6122	pSVGAState = pThis->svga.pSvgaR3State;
6123
6124	/* Initialize FIFO and register capabilities. */
6125	vmsvgaInitCaps(pThis);
6126
6127	# ifdef VBOX_WITH_VMSVGA3D
6128	if (pThis->svga.f3DEnabled)
6129	{
6130	rc = vmsvga3dInit(pThis);
6131	if (RT_FAILURE(rc))
6132	{
6133	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6134	pThis->svga.f3DEnabled = false;
6135	}
6136	}
6137	# endif
6138	/* VRAM tracking is enabled by default during bootup. */
6139	pThis->svga.fVRAMTracking = true;
6140
6141	/* Invalidate current settings. */
6142	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6143	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6144	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6145	pThis->svga.cbScanline = 0;
6146
6147	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6148	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6149	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6150	{
6151	pThis->svga.u32MaxWidth -= 256;
6152	pThis->svga.u32MaxHeight -= 256;
6153	}
6154	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6155
6156	# ifdef DEBUG_GMR_ACCESS
6157	/* Register the GMR access handler type. */
6158	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
6159	vmsvgaR3GMRAccessHandler,
6160	NULL, NULL, NULL,
6161	NULL, NULL, NULL,
6162	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6163	AssertRCReturn(rc, rc);
6164	# endif
6165
6166	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6167	/* Register the FIFO access handler type. In addition to
6168	debugging FIFO access, this is also used to facilitate
6169	extended fifo thread sleeps. */
6170	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
6171	# ifdef DEBUG_FIFO_ACCESS
6172	PGMPHYSHANDLERKIND_ALL,
6173	# else
6174	PGMPHYSHANDLERKIND_WRITE,
6175	# endif
6176	vmsvgaR3FIFOAccessHandler,
6177	NULL, NULL, NULL,
6178	NULL, NULL, NULL,
6179	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6180	AssertRCReturn(rc, rc);
6181	# endif
6182
6183	/* Create the async IO thread. */
6184	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
6185	RTTHREADTYPE_IO, "VMSVGA FIFO");
6186	if (RT_FAILURE(rc))
6187	{
6188	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6189	return rc;
6190	}
6191
6192	/*
6193	* Statistics.
6194	*/
6195	#define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6196	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6197	#define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6198	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6199	#ifdef VBOX_WITH_STATISTICS
6200	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6201	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6202	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6203	#endif
6204	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6205	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6206	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6207	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6208	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6209	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6210	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6211	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6212	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6213	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6214	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6215	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6216	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6217	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6218	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6219	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6220	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6221	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6222	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6223	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6224	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6225	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6226	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6227	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6228	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6229	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6230	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6231	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6232	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6233	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6234	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6235	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6236	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6237	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6238	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6239	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6240	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6241	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6242	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6243	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6244	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6245	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6246	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6247	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6248	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6249	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6250	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6251	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6252	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6253	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6254	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6255	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6256	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6257
6258	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6259	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6260	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6261	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6262	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6263	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6264	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6265	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6266	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6267	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6268	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6269	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6270	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6271	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6272	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6273	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6274	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6275	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6276	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6277	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6278	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6279	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6280	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6281	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6282	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6283	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6284	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6285	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6286	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6287	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6288	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6289	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6290
6291	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6292	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6293	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6294	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6295	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6296	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6297	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6298	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6299	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6300	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6301	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6302	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6303	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6304	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6305	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6306	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6307	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6308	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6309	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6310	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6311	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6312	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6313	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6314	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6315	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6316	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6317	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6318	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6319	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6320	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6321	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6322	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6323	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6324	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6325	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6326	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6327	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6328	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6329	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6330	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6331	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6332	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6333	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6334	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6335	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6336	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6337	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6338	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6339	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6340
6341	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6342	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6343	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6344	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6345	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6346	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6347	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6348	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6349	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6350	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6351	# endif
6352	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6353	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6354	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6355	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6356	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6357
6358	#undef REG_CNT
6359	#undef REG_PRF
6360
6361	/*
6362	* Info handlers.
6363	*/
6364	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6365	# ifdef VBOX_WITH_VMSVGA3D
6366	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6367	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6368	"VMSVGA 3d surface details. "
6369	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6370	vmsvgaR3Info3dSurface);
6371	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6372	"VMSVGA 3d surface details and bitmap: "
6373	"sid[>dir]",
6374	vmsvgaR3Info3dSurfaceBmp);
6375	# endif
6376
6377	return VINF_SUCCESS;
6378	}
6379
6380	/**
6381	* Power On notification.
6382	*
6383	* @returns VBox status code.
6384	* @param pDevIns The device instance data.
6385	*
6386	* @remarks Caller enters the device critical section.
6387	*/
6388	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6389	{
6390	# ifdef VBOX_WITH_VMSVGA3D
6391	PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
6392	if (pThis->svga.f3DEnabled)
6393	{
6394	int rc = vmsvga3dPowerOn(pThis);
6395
6396	if (RT_SUCCESS(rc))
6397	{
6398	/* Initialize FIFO 3D capabilities. */
6399	vmsvgaInitFifo3DCaps(pThis);
6400	}
6401	}
6402	# else /* !VBOX_WITH_VMSVGA3D */
6403	RT_NOREF(pDevIns);
6404	# endif /* !VBOX_WITH_VMSVGA3D */
6405	}
6406
6407	#endif /* IN_RING3 */
6408

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