DevVGA-SVGA.cpp@ 103914

Last change on this file since 103914 was 102520, checked in by vboxsync, 10 months ago
Devices/Graphics: planar textures; video commands. bugref:10529
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1	/* $Id: DevVGA-SVGA.cpp 102520 2023-12-07 12:06:26Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - Log8 for content of constant and vertex buffers.
15	* - LogRel for the usual important stuff.
16	* - LogRel2 for cursor.
17	* - LogRel3 for 3D performance data.
18	* - LogRel4 for HW accelerated graphics output.
19	*/
20
21	/*
22	* Copyright (C) 2013-2023 Oracle and/or its affiliates.
23	*
24	* This file is part of VirtualBox base platform packages, as
25	* available from https://www.virtualbox.org.
26	*
27	* This program is free software; you can redistribute it and/or
28	* modify it under the terms of the GNU General Public License
29	* as published by the Free Software Foundation, in version 3 of the
30	* License.
31	*
32	* This program is distributed in the hope that it will be useful, but
33	* WITHOUT ANY WARRANTY; without even the implied warranty of
34	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35	* General Public License for more details.
36	*
37	* You should have received a copy of the GNU General Public License
38	* along with this program; if not, see <https://www.gnu.org/licenses>.
39	*
40	* SPDX-License-Identifier: GPL-3.0-only
41	*/
42
43
44	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
45	*
46	* This device emulation was contributed by trivirt AG. It offers an
47	* alternative to our Bochs based VGA graphics and 3d emulations. This is
48	* valuable for Xorg based guests, as there is driver support shipping with Xorg
49	* since it forked from XFree86.
50	*
51	*
52	* @section sec_dev_vmsvga_sdk The VMware SDK
53	*
54	* This is officially deprecated now, however it's still quite useful,
55	* especially for getting the old features working:
56	* http://vmware-svga.sourceforge.net/
57	*
58	* They currently point developers at the following resources.
59	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
60	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
61	* - http://cgit.freedesktop.org/mesa/vmwgfx/
62	*
63	* @subsection subsec_dev_vmsvga_sdk_results Test results
64	*
65	* Test results:
66	* - 2dmark.img:
67	* + todo
68	* - backdoor-tclo.img:
69	* + todo
70	* - blit-cube.img:
71	* + todo
72	* - bunnies.img:
73	* + todo
74	* - cube.img:
75	* + todo
76	* - cubemark.img:
77	* + todo
78	* - dynamic-vertex-stress.img:
79	* + todo
80	* - dynamic-vertex.img:
81	* + todo
82	* - fence-stress.img:
83	* + todo
84	* - gmr-test.img:
85	* + todo
86	* - half-float-test.img:
87	* + todo
88	* - noscreen-cursor.img:
89	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
90	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
91	* visible though.)
92	* - Cursor animation via the palette doesn't work.
93	* - During debugging, it turns out that the framebuffer content seems to
94	* be halfways ignore or something (memset(fb, 0xcc, lots)).
95	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
96	* grow it 0x10 fold (128KB -> 2MB like in WS10).
97	* - null.img:
98	* + todo
99	* - pong.img:
100	* + todo
101	* - presentReadback.img:
102	* + todo
103	* - resolution-set.img:
104	* + todo
105	* - rt-gamma-test.img:
106	* + todo
107	* - screen-annotation.img:
108	* + todo
109	* - screen-cursor.img:
110	* + todo
111	* - screen-dma-coalesce.img:
112	* + todo
113	* - screen-gmr-discontig.img:
114	* + todo
115	* - screen-gmr-remap.img:
116	* + todo
117	* - screen-multimon.img:
118	* + todo
119	* - screen-present-clip.img:
120	* + todo
121	* - screen-render-test.img:
122	* + todo
123	* - screen-simple.img:
124	* + todo
125	* - screen-text.img:
126	* + todo
127	* - simple-shaders.img:
128	* + todo
129	* - simple_blit.img:
130	* + todo
131	* - tiny-2d-updates.img:
132	* + todo
133	* - video-formats.img:
134	* + todo
135	* - video-sync.img:
136	* + todo
137	*
138	*/
139
140
141	/*********************************************************************************************************************************
142	* Header Files *
143	*********************************************************************************************************************************/
144	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
145	#include <VBox/vmm/pdmdev.h>
146	#include <VBox/version.h>
147	#include <VBox/err.h>
148	#include <VBox/log.h>
149	#include <VBox/vmm/pgm.h>
150	#include <VBox/sup.h>
151
152	#include <iprt/assert.h>
153	#include <iprt/semaphore.h>
154	#include <iprt/uuid.h>
155	#ifdef IN_RING3
156	# include <iprt/ctype.h>
157	# include <iprt/mem.h>
158	# ifdef VBOX_STRICT
159	# include <iprt/time.h>
160	# endif
161	#endif
162
163	#include <VBox/AssertGuest.h>
164	#include <VBox/VMMDev.h>
165	#include <VBoxVideo.h>
166	#include <VBox/bioslogo.h>
167
168	#ifdef LOG_ENABLED
169	#include "svgadump/svga_dump.h"
170	#endif
171
172	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
173	#include "DevVGA.h"
174
175	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
176	#ifdef VBOX_WITH_VMSVGA3D
177	# include "DevVGA-SVGA3d.h"
178	# ifdef RT_OS_DARWIN
179	# include "DevVGA-SVGA3d-cocoa.h"
180	# endif
181	# ifdef RT_OS_LINUX
182	# ifdef IN_RING3
183	# include "DevVGA-SVGA3d-glLdr.h"
184	# endif
185	# endif
186	#endif
187	#ifdef IN_RING3
188	#include "DevVGA-SVGA-internal.h"
189	#endif
190
191
192	/*********************************************************************************************************************************
193	* Defined Constants And Macros *
194	*********************************************************************************************************************************/
195	/**
196	* Macro for checking if a fixed FIFO register is valid according to the
197	* current FIFO configuration.
198	*
199	* @returns true / false.
200	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
201	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
202	*/
203	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
204
205
206	/*********************************************************************************************************************************
207	* Structures and Typedefs *
208	*********************************************************************************************************************************/
209
210
211	/*********************************************************************************************************************************
212	* Internal Functions *
213	*********************************************************************************************************************************/
214	#ifdef IN_RING3
215	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
216	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
217	# endif
218	# ifdef DEBUG_GMR_ACCESS
219	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
220	# endif
221	#endif
222
223
224	/*********************************************************************************************************************************
225	* Global Variables *
226	*********************************************************************************************************************************/
227	#ifdef IN_RING3
228
229	/**
230	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
231	*/
232	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
233	{
234	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
235	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
236	SSMFIELD_ENTRY_TERM()
237	};
238
239	/**
240	* SSM descriptor table for the GMR structure.
241	*/
242	static SSMFIELD const g_aGMRFields[] =
243	{
244	SSMFIELD_ENTRY( GMR, cMaxPages),
245	SSMFIELD_ENTRY( GMR, cbTotal),
246	SSMFIELD_ENTRY( GMR, numDescriptors),
247	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
248	SSMFIELD_ENTRY_TERM()
249	};
250
251	/**
252	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
253	*/
254	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
255	{
256	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
257	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
258	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
259	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
260	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
261	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
262	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
263	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
264	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
265	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
266	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
267	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
268	SSMFIELD_ENTRY_TERM()
269	};
270
271	/**
272	* SSM descriptor table for the VMSVGAR3STATE structure.
273	*/
274	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
275	{
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
277	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
278	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
279	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
280	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
281	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
282	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
283	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
284	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
285	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
287	#ifdef VMSVGA_USE_EMT_HALT_CODE
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
289	#else
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
291	#endif
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
355
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
359	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
360
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
364	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
365	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
366	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
367	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
368	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
369	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
370	# endif
371	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
372	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
375
376	SSMFIELD_ENTRY_TERM()
377	};
378
379	/**
380	* SSM descriptor table for the VGAState.svga structure.
381	*/
382	static SSMFIELD const g_aVGAStateSVGAFields[] =
383	{
384	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
387	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
388	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
389	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
390	SSMFIELD_ENTRY( VMSVGAState, fBusy),
391	SSMFIELD_ENTRY( VMSVGAState, fTraces),
392	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
393	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
394	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
395	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
396	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
397	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
398	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
399	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
400	SSMFIELD_ENTRY_VER( VMSVGAState, u32DeviceCaps2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
401	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverId, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
402	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer1, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
403	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
404	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer3, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
405	SSMFIELD_ENTRY_VER( VMSVGAState, u32FenceLast, VGA_SAVEDSTATE_VERSION_VMSVGA_SVGA3),
406	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
410	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
411	SSMFIELD_ENTRY( VMSVGAState, uWidth),
412	SSMFIELD_ENTRY( VMSVGAState, uHeight),
413	SSMFIELD_ENTRY( VMSVGAState, uBpp),
414	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
415	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
416	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
417	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
418	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
419	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
420	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
421	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
422	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
423	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
424	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
428	SSMFIELD_ENTRY_VER( VMSVGAState, au32DevCaps, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
429	SSMFIELD_ENTRY_VER( VMSVGAState, u32DevCapIndex, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
430	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandLow, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
431	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandHigh, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
432
433	SSMFIELD_ENTRY_TERM()
434	};
435	#endif /* IN_RING3 */
436
437
438	/*********************************************************************************************************************************
439	* Internal Functions *
440	*********************************************************************************************************************************/
441	#ifdef IN_RING3
442	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
443	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
444	uint32_t uVersion, uint32_t uPass);
445	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
446	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
447	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState);
448	#endif /* IN_RING3 */
449
450
451	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
452	#if defined(LOG_ENABLED)
453	/**
454	* Index register string name lookup
455	*
456	* @returns Index register string or "UNKNOWN"
457	* @param pThis The shared VGA/VMSVGA state.
458	* @param idxReg The index register.
459	*/
460	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
461	{
462	AssertCompile(SVGA_REG_TOP == 84); /* Ensure that the correct headers are used. */
463	switch (idxReg)
464	{
465	SVGA_CASE_ID2STR(SVGA_REG_ID);
466	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
467	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
468	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
469	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
470	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
471	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
472	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
473	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
474	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
475	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
476	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
477	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
478	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
479	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
480	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
481	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
482
483	/* ID 0 implementation only had the above registers, then the palette */
484	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
485	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
486	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
487	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
488	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
489	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
490	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
491	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
492	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
493	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
494	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
495	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
496	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
497	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
498	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
499	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
500	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
501
502	/* Legacy multi-monitor support */
503	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
504	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
505	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
506	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
507	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
508	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
509	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
510
511	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
512	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
513	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
514	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
515
516	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
517	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
518	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
519	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
520	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
521	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
522	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
523	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
524	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
525	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
526	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
527	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
528	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
529	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
530	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
531	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
532	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
533	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
534	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
535	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
536	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
537	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
538	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
539	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
540	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
541	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
542	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
543	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
544	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
545	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
546	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
547	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
548	SVGA_CASE_ID2STR(SVGA_REG_REGS_START_HIGH32);
549	SVGA_CASE_ID2STR(SVGA_REG_REGS_START_LOW32);
550	SVGA_CASE_ID2STR(SVGA_REG_FB_START_HIGH32);
551	SVGA_CASE_ID2STR(SVGA_REG_FB_START_LOW32);
552	SVGA_CASE_ID2STR(SVGA_REG_MSHINT);
553	SVGA_CASE_ID2STR(SVGA_REG_IRQ_STATUS);
554	SVGA_CASE_ID2STR(SVGA_REG_DIRTY_TRACKING);
555	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
556
557	default:
558	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
559	return "SVGA_SCRATCH_BASE reg";
560	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
561	return "SVGA_PALETTE_BASE reg";
562	return "UNKNOWN";
563	}
564	}
565	#endif /* LOG_ENABLED */
566
567	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
568	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
569	{
570	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
571	switch (idxDevCap)
572	{
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
804	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
806	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
807	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
808	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
809	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
810	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
811	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
812	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
813	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
814	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
815	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
816	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
817	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
818	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
819	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
820	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
821	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
822	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
823	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
824	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
825	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
826	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
827	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
828	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
829	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
830	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
831	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
832	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
833	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
834
835	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
836
837	default:
838	break;
839	}
840	return "UNKNOWN";
841	}
842	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
843	#undef SVGA_CASE_ID2STR
844
845
846	#ifdef IN_RING3
847
848	/**
849	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
850	*/
851	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
852	{
853	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
854	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
855
856	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
857	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
858
859	/** @todo Test how it interacts with multiple screen objects. */
860	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
861	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
862	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
863
864	if (x < uWidth)
865	{
866	pThis->svga.viewport.x = x;
867	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
868	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
869	}
870	else
871	{
872	pThis->svga.viewport.x = uWidth;
873	pThis->svga.viewport.cx = 0;
874	pThis->svga.viewport.xRight = uWidth;
875	}
876	if (y < uHeight)
877	{
878	pThis->svga.viewport.y = y;
879	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
880	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
881	pThis->svga.viewport.yHighWC = uHeight - y;
882	}
883	else
884	{
885	pThis->svga.viewport.y = uHeight;
886	pThis->svga.viewport.cy = 0;
887	pThis->svga.viewport.yLowWC = 0;
888	pThis->svga.viewport.yHighWC = 0;
889	}
890
891	# ifdef VBOX_WITH_VMSVGA3D
892	/*
893	* Now inform the 3D backend.
894	*/
895	if (pThis->svga.f3DEnabled)
896	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
897	# else
898	RT_NOREF(OldViewport);
899	# endif
900	}
901
902
903	/**
904	* Updating screen information in API
905	*
906	* @param pThis The The shared VGA/VMSVGA instance data.
907	* @param pThisCC The VGA/VMSVGA state for ring-3.
908	*/
909	static void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
910	{
911	int rc;
912
913	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
914
915	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
916	{
917	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
918	if (!pScreen->fModified)
919	continue;
920
921	pScreen->fModified = false;
922
923	VBVAINFOVIEW view;
924	RT_ZERO(view);
925	view.u32ViewIndex = pScreen->idScreen;
926	// view.u32ViewOffset = 0;
927	view.u32ViewSize = pThis->vram_size;
928	view.u32MaxScreenSize = pThis->vram_size;
929
930	VBVAINFOSCREEN screen;
931	RT_ZERO(screen);
932	screen.u32ViewIndex = pScreen->idScreen;
933
934	if (pScreen->fDefined)
935	{
936	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
937	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
938	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
939	{
940	Assert(pThis->svga.fGFBRegisters);
941	continue;
942	}
943
944	screen.i32OriginX = pScreen->xOrigin;
945	screen.i32OriginY = pScreen->yOrigin;
946	screen.u32StartOffset = pScreen->offVRAM;
947	screen.u32LineSize = pScreen->cbPitch;
948	screen.u32Width = pScreen->cWidth;
949	screen.u32Height = pScreen->cHeight;
950	screen.u16BitsPerPixel = pScreen->cBpp;
951	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
952	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
953	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
954	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
955	}
956	else
957	{
958	/* Screen is destroyed. */
959	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
960	}
961
962	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
963	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
964	AssertRC(rc);
965	}
966	}
967
968
969	/**
970	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
971	*
972	* Used to update screen offsets (positions) since appearently vmwgfx fails to
973	* pass correct offsets thru FIFO.
974	*/
975	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
976	{
977	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
978	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
979	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
980
981	AssertReturnVoid(pSVGAState);
982
983	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
984	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
985	for (uint32_t i = 0; i < cPositions; ++i)
986	{
987	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
988	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
989	continue;
990
991	if (paPositions[i].x == -1)
992	continue;
993	if (paPositions[i].y == -1)
994	continue;
995
996	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
997	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
998	pSVGAState->aScreens[i].fModified = true;
999	}
1000
1001	vmsvgaR3VBVAResize(pThis, pThisCC);
1002	}
1003
1004	#endif /* IN_RING3 */
1005
1006	/**
1007	* Read port register
1008	*
1009	* @returns VBox status code.
1010	* @param pDevIns The device instance.
1011	* @param pThis The shared VGA/VMSVGA state.
1012	* @param idxReg The register index being read.
1013	* @param pu32 Where to store the read value
1014	*/
1015	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t idxReg, uint32_t *pu32)
1016	{
1017	#ifdef IN_RING3
1018	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1019	#endif
1020	int rc = VINF_SUCCESS;
1021	*pu32 = 0;
1022
1023	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1024	if ( idxReg >= SVGA_REG_ID_0_TOP
1025	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1026	{
1027	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1028	Log(("vmsvgaReadPort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1029	}
1030
1031	switch (idxReg)
1032	{
1033	case SVGA_REG_ID:
1034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1035	*pu32 = pThis->svga.u32SVGAId;
1036	break;
1037
1038	case SVGA_REG_ENABLE:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1040	*pu32 = pThis->svga.fEnabled;
1041	break;
1042
1043	case SVGA_REG_WIDTH:
1044	{
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1046	if ( pThis->svga.fEnabled
1047	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1048	*pu32 = pThis->svga.uWidth;
1049	else
1050	{
1051	#ifndef IN_RING3
1052	rc = VINF_IOM_R3_IOPORT_READ;
1053	#else
1054	*pu32 = pThisCC->pDrv->cx;
1055	#endif
1056	}
1057	break;
1058	}
1059
1060	case SVGA_REG_HEIGHT:
1061	{
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1063	if ( pThis->svga.fEnabled
1064	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1065	*pu32 = pThis->svga.uHeight;
1066	else
1067	{
1068	#ifndef IN_RING3
1069	rc = VINF_IOM_R3_IOPORT_READ;
1070	#else
1071	*pu32 = pThisCC->pDrv->cy;
1072	#endif
1073	}
1074	break;
1075	}
1076
1077	case SVGA_REG_MAX_WIDTH:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1079	*pu32 = pThis->svga.u32MaxWidth;
1080	break;
1081
1082	case SVGA_REG_MAX_HEIGHT:
1083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1084	*pu32 = pThis->svga.u32MaxHeight;
1085	break;
1086
1087	case SVGA_REG_DEPTH:
1088	/* This returns the color depth of the current mode. */
1089	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1090	switch (pThis->svga.uBpp)
1091	{
1092	case 15:
1093	case 16:
1094	case 24:
1095	*pu32 = pThis->svga.uBpp;
1096	break;
1097
1098	default:
1099	case 32:
1100	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1101	break;
1102	}
1103	break;
1104
1105	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1106	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1107	*pu32 = pThis->svga.uHostBpp;
1108	break;
1109
1110	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1111	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1112	*pu32 = pThis->svga.uBpp;
1113	break;
1114
1115	case SVGA_REG_PSEUDOCOLOR:
1116	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1117	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1118	break;
1119
1120	case SVGA_REG_RED_MASK:
1121	case SVGA_REG_GREEN_MASK:
1122	case SVGA_REG_BLUE_MASK:
1123	{
1124	uint32_t uBpp;
1125
1126	if (pThis->svga.fEnabled)
1127	uBpp = pThis->svga.uBpp;
1128	else
1129	uBpp = pThis->svga.uHostBpp;
1130
1131	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1132	switch (uBpp)
1133	{
1134	case 8:
1135	u32RedMask = 0x07;
1136	u32GreenMask = 0x38;
1137	u32BlueMask = 0xc0;
1138	break;
1139
1140	case 15:
1141	u32RedMask = 0x0000001f;
1142	u32GreenMask = 0x000003e0;
1143	u32BlueMask = 0x00007c00;
1144	break;
1145
1146	case 16:
1147	u32RedMask = 0x0000001f;
1148	u32GreenMask = 0x000007e0;
1149	u32BlueMask = 0x0000f800;
1150	break;
1151
1152	case 24:
1153	case 32:
1154	default:
1155	u32RedMask = 0x00ff0000;
1156	u32GreenMask = 0x0000ff00;
1157	u32BlueMask = 0x000000ff;
1158	break;
1159	}
1160	switch (idxReg)
1161	{
1162	case SVGA_REG_RED_MASK:
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1164	*pu32 = u32RedMask;
1165	break;
1166
1167	case SVGA_REG_GREEN_MASK:
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1169	*pu32 = u32GreenMask;
1170	break;
1171
1172	case SVGA_REG_BLUE_MASK:
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1174	*pu32 = u32BlueMask;
1175	break;
1176	}
1177	break;
1178	}
1179
1180	case SVGA_REG_BYTES_PER_LINE:
1181	{
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1183	if ( pThis->svga.fEnabled
1184	&& pThis->svga.cbScanline)
1185	*pu32 = pThis->svga.cbScanline;
1186	else
1187	{
1188	#ifndef IN_RING3
1189	rc = VINF_IOM_R3_IOPORT_READ;
1190	#else
1191	*pu32 = pThisCC->pDrv->cbScanline;
1192	#endif
1193	}
1194	break;
1195	}
1196
1197	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1199	*pu32 = pThis->vram_size;
1200	break;
1201
1202	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1204	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1205	*pu32 = pThis->GCPhysVRAM;
1206	break;
1207
1208	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1210	/* Always zero in our case. */
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1215	{
1216	#ifndef IN_RING3
1217	rc = VINF_IOM_R3_IOPORT_READ;
1218	#else
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1220
1221	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1222	if ( pThis->svga.fEnabled
1223	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1224	{
1225	/* Hardware enabled; return real framebuffer size .*/
1226	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1227	}
1228	else
1229	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1230
1231	pu32 = RT_MIN(pThis->vram_size, pu32);
1232	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1233	#endif
1234	break;
1235	}
1236
1237	case SVGA_REG_CAPABILITIES:
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1239	*pu32 = pThis->svga.u32DeviceCaps;
1240	break;
1241
1242	case SVGA_REG_MEM_START: /* FIFO start */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1244	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1245	*pu32 = pThis->svga.GCPhysFIFO;
1246	break;
1247
1248	case SVGA_REG_MEM_SIZE: /* FIFO size */
1249	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1250	*pu32 = pThis->svga.cbFIFO;
1251	break;
1252
1253	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1255	*pu32 = pThis->svga.fConfigured;
1256	break;
1257
1258	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1260	*pu32 = 0;
1261	break;
1262
1263	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1264	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1265	if (pThis->svga.fBusy)
1266	{
1267	#ifndef IN_RING3
1268	/* Go to ring-3 and halt the CPU. */
1269	rc = VINF_IOM_R3_IOPORT_READ;
1270	RT_NOREF(pDevIns);
1271	break;
1272	#else /* IN_RING3 */
1273	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1274	/* The guest is basically doing a HLT via the device here, but with
1275	a special wake up condition on FIFO completion. */
1276	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1277	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1278	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1279	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1280	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1281	if (pThis->svga.fBusy)
1282	{
1283	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1284	rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1285	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1286	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1287	}
1288	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1289	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1290	# else
1291
1292	/* Delay the EMT a bit so the FIFO and others can get some work done.
1293	This used to be a crude 50 ms sleep. The current code tries to be
1294	more efficient, but the consept is still very crude. */
1295	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1296	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1297	RTThreadYield();
1298	if (pThis->svga.fBusy)
1299	{
1300	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1301
1302	if (pThis->svga.fBusy && cRefs == 1)
1303	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1304	if (pThis->svga.fBusy)
1305	{
1306	/** @todo If this code is going to stay, we need to call into the halt/wait
1307	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1308	* suffer when the guest is polling on a busy FIFO. */
1309	uint64_t uIgnored1, uIgnored2;
1310	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1311	if (cNsMaxWait >= RT_NS_100US)
1312	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1313	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1314	RT_MIN(cNsMaxWait, RT_NS_10MS));
1315	}
1316
1317	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1318	}
1319	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1320	# endif
1321	*pu32 = pThis->svga.fBusy != 0;
1322	#endif /* IN_RING3 */
1323	}
1324	else
1325	*pu32 = false;
1326	break;
1327
1328	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1329	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1330	*pu32 = pThis->svga.u32GuestId;
1331	break;
1332
1333	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1335	*pu32 = pThis->svga.cScratchRegion;
1336	break;
1337
1338	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1339	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1340	*pu32 = SVGA_FIFO_NUM_REGS;
1341	break;
1342
1343	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1344	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1345	*pu32 = pThis->svga.u32PitchLock;
1346	break;
1347
1348	case SVGA_REG_IRQMASK: /* Interrupt mask */
1349	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1350	*pu32 = pThis->svga.u32IrqMask;
1351	break;
1352
1353	/* See "Guest memory regions" below. */
1354	case SVGA_REG_GMR_ID:
1355	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1356	*pu32 = pThis->svga.u32CurrentGMRId;
1357	break;
1358
1359	case SVGA_REG_GMR_DESCRIPTOR:
1360	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1361	/* Write only */
1362	*pu32 = 0;
1363	break;
1364
1365	case SVGA_REG_GMR_MAX_IDS:
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1367	*pu32 = pThis->svga.cGMR;
1368	break;
1369
1370	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1372	*pu32 = VMSVGA_MAX_GMR_PAGES;
1373	break;
1374
1375	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1376	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1377	*pu32 = pThis->svga.fTraces;
1378	break;
1379
1380	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1381	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1382	*pu32 = VMSVGA_MAX_GMR_PAGES;
1383	break;
1384
1385	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1386	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1387	*pu32 = VMSVGA_SURFACE_SIZE;
1388	break;
1389
1390	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1391	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1392	break;
1393
1394	/* Mouse cursor support. */
1395	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1396	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1397	*pu32 = pThis->svga.uCursorID;
1398	break;
1399
1400	case SVGA_REG_CURSOR_X:
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1402	*pu32 = pThis->svga.uCursorX;
1403	break;
1404
1405	case SVGA_REG_CURSOR_Y:
1406	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1407	*pu32 = pThis->svga.uCursorY;
1408	break;
1409
1410	case SVGA_REG_CURSOR_ON:
1411	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1412	*pu32 = pThis->svga.uCursorOn;
1413	break;
1414
1415	/* Legacy multi-monitor support */
1416	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1417	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1418	*pu32 = 1;
1419	break;
1420
1421	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1422	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1423	*pu32 = 0;
1424	break;
1425
1426	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1427	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1428	*pu32 = 0;
1429	break;
1430
1431	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1432	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1433	*pu32 = 0;
1434	break;
1435
1436	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1437	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1438	*pu32 = 0;
1439	break;
1440
1441	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1442	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1443	*pu32 = pThis->svga.uWidth;
1444	break;
1445
1446	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1447	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1448	*pu32 = pThis->svga.uHeight;
1449	break;
1450
1451	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1452	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1453	/* We must return something sensible here otherwise the Linux driver
1454	will take a legacy code path without 3d support. This number also
1455	limits how many screens Linux guests will allow. */
1456	*pu32 = pThis->cMonitors;
1457	break;
1458
1459	/*
1460	* SVGA_CAP_GBOBJECTS+ registers.
1461	*/
1462	case SVGA_REG_COMMAND_LOW:
1463	/* Lower 32 bits of command buffer physical address. */
1464	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1465	*pu32 = pThis->svga.u32RegCommandLow;
1466	break;
1467
1468	case SVGA_REG_COMMAND_HIGH:
1469	/* Upper 32 bits of command buffer PA. */
1470	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1471	*pu32 = pThis->svga.u32RegCommandHigh;
1472	break;
1473
1474	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1475	/* Max primary (screen) memory. */
1476	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1477	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1478	break;
1479
1480	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1481	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1482	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1483	*pu32 = pThis->vram_size / 1024;
1484	break;
1485
1486	case SVGA_REG_DEV_CAP:
1487	/* Write dev cap index, read value */
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1489	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1490	{
1491	RT_UNTRUSTED_VALIDATED_FENCE();
1492	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1493	}
1494	else
1495	*pu32 = 0;
1496	break;
1497
1498	case SVGA_REG_CMD_PREPEND_LOW:
1499	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1500	pu32 = 0; / Not supported. */
1501	break;
1502
1503	case SVGA_REG_CMD_PREPEND_HIGH:
1504	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1505	pu32 = 0; / Not supported. */
1506	break;
1507
1508	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1509	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1510	*pu32 = pThis->svga.u32MaxWidth;
1511	break;
1512
1513	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1514	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1515	*pu32 = pThis->svga.u32MaxHeight;
1516	break;
1517
1518	case SVGA_REG_MOB_MAX_SIZE:
1519	/* Essentially the max texture size */
1520	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1521	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1522	break;
1523
1524	case SVGA_REG_BLANK_SCREEN_TARGETS:
1525	/// @todo STAM_REL_COUNTER_INC(&pThis->svga.aStatRegRd[idxReg]);
1526	pu32 = 0; / Not supported. */
1527	break;
1528
1529	case SVGA_REG_CAP2:
1530	*pu32 = pThis->svga.u32DeviceCaps2;
1531	break;
1532
1533	case SVGA_REG_DEVEL_CAP:
1534	pu32 = 0; / Not supported. */
1535	break;
1536
1537	/*
1538	* SVGA_REG_GUEST_DRIVER_* registers require SVGA_CAP2_DX2.
1539	*/
1540	case SVGA_REG_GUEST_DRIVER_ID:
1541	*pu32 = pThis->svga.u32GuestDriverId;
1542	break;
1543
1544	case SVGA_REG_GUEST_DRIVER_VERSION1:
1545	*pu32 = pThis->svga.u32GuestDriverVer1;
1546	break;
1547
1548	case SVGA_REG_GUEST_DRIVER_VERSION2:
1549	*pu32 = pThis->svga.u32GuestDriverVer2;
1550	break;
1551
1552	case SVGA_REG_GUEST_DRIVER_VERSION3:
1553	*pu32 = pThis->svga.u32GuestDriverVer3;
1554	break;
1555
1556	/*
1557	* SVGA_REG_CURSOR_ registers require SVGA_CAP2_CURSOR_MOB which the device does not support currently.
1558	*/
1559	case SVGA_REG_CURSOR_MOBID:
1560	*pu32 = SVGA_ID_INVALID;
1561	break;
1562
1563	case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
1564	*pu32 = 0;
1565	break;
1566
1567	case SVGA_REG_CURSOR_MAX_DIMENSION:
1568	*pu32 = 0;
1569	break;
1570
1571	case SVGA_REG_FIFO_CAPS:
1572	{
1573	if (pThis->fVmSvga3)
1574	*pu32 = SVGA_FIFO_CAP_FENCE
1575	\| SVGA_FIFO_CAP_PITCHLOCK
1576	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
1577	\| SVGA_FIFO_CAP_RESERVE
1578	\| SVGA_FIFO_CAP_GMR2
1579	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
1580	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
1581	else
1582	*pu32 = 0;
1583	break;
1584	}
1585	case SVGA_REG_FENCE:
1586	{
1587	if (pThis->fVmSvga3)
1588	*pu32 = pThis->svga.u32FenceLast;
1589	else
1590	*pu32 = 0;
1591	break;
1592	}
1593
1594	case SVGA_REG_RESERVED1: /* SVGA_REG_RESERVED* correspond to SVGA_REG_CURSOR4_. Require SVGA_CAP2_EXTRA_REGS. /
1595	case SVGA_REG_RESERVED2:
1596	case SVGA_REG_RESERVED3:
1597	case SVGA_REG_RESERVED4:
1598	case SVGA_REG_RESERVED5:
1599	case SVGA_REG_SCREENDMA:
1600	pu32 = 0; / Not supported. */
1601	break;
1602
1603	case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
1604	/** @todo "The maximum amount of guest-backed objects that the device can have resident at a time" */
1605	*pu32 = _1G / _1K;
1606	break;
1607
1608	case SVGA_REG_IRQ_STATUS:
1609	{
1610	if (pThis->fVmSvga3)
1611	*pu32 = pThis->svga.u32IrqStatus;
1612	else
1613	*pu32 = 0;
1614	break;
1615	}
1616
1617	default:
1618	{
1619	uint32_t offReg;
1620	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1621	{
1622	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1623	RT_UNTRUSTED_VALIDATED_FENCE();
1624	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1625	}
1626	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1627	{
1628	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1629	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1630	RT_UNTRUSTED_VALIDATED_FENCE();
1631	uint32_t u32 = pThis->last_palette[offReg / 3];
1632	switch (offReg % 3)
1633	{
1634	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1635	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1636	case 2: pu32 = u32 & 0xff; break; / blue */
1637	}
1638	}
1639	else
1640	{
1641	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1642	rc = VINF_IOM_R3_IOPORT_READ;
1643	#else
1644	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1645
1646	/* Do not assert. The guest might be reading all registers. */
1647	LogFunc(("Unknown reg=%#x\n", idxReg));
1648	#endif
1649	}
1650	break;
1651	}
1652	}
1653	LogFlow(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1654	return rc;
1655	}
1656
1657	#ifdef IN_RING3
1658	/**
1659	* Apply the current resolution settings to change the video mode.
1660	*
1661	* @returns VBox status code.
1662	* @param pThis The shared VGA state.
1663	* @param pThisCC The ring-3 VGA state.
1664	*/
1665	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1666	{
1667	/* Always do changemode on FIFO thread. */
1668	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1669
1670	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1671
1672	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1673
1674	if (pThis->svga.fGFBRegisters)
1675	{
1676	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1677	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1678	* deletes all screens other than screen #0, and redefines screen
1679	* #0 according to the specified mode. Drivers that use
1680	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1681	*/
1682
1683	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1684	Assert(pScreen->idScreen == 0);
1685	pScreen->fDefined = true;
1686	pScreen->fModified = true;
1687	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1688	pScreen->xOrigin = 0;
1689	pScreen->yOrigin = 0;
1690	pScreen->offVRAM = 0;
1691	pScreen->cbPitch = pThis->svga.cbScanline;
1692	pScreen->cWidth = pThis->svga.uWidth;
1693	pScreen->cHeight = pThis->svga.uHeight;
1694	pScreen->cBpp = pThis->svga.uBpp;
1695
1696	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1697	{
1698	/* Delete screen. */
1699	pScreen = &pSVGAState->aScreens[iScreen];
1700	if (pScreen->fDefined)
1701	{
1702	pScreen->fModified = true;
1703	pScreen->fDefined = false;
1704	}
1705	}
1706	}
1707	else
1708	{
1709	/* "If Screen Objects are supported, they can be used to fully
1710	* replace the functionality provided by the framebuffer registers
1711	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1712	*/
1713	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1714	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1715	pThis->svga.uBpp = pThis->svga.uHostBpp;
1716	}
1717
1718	vmsvgaR3VBVAResize(pThis, pThisCC);
1719
1720	/* Last stuff. For the VGA device screenshot. */
1721	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1722	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1723	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1724	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1725	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1726
1727	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1728	if ( pThis->svga.viewport.cx == 0
1729	&& pThis->svga.viewport.cy == 0)
1730	{
1731	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1732	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1733	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1734	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1735	pThis->svga.viewport.yLowWC = 0;
1736	}
1737
1738	return VINF_SUCCESS;
1739	}
1740
1741	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1742	{
1743	ASSERT_GUEST_LOGREL_MSG_RETURN(w > 0 && h > 0,
1744	("vmsvgaR3UpdateScreen: screen %d (%d,%d) %dx%d: Invalid height and/or width supplied.\n",
1745	pScreen->idScreen, x, y, w, h),
1746	VERR_INVALID_PARAMETER);
1747
1748	VBVACMDHDR cmd;
1749	cmd.x = (int16_t)(pScreen->xOrigin + x);
1750	cmd.y = (int16_t)(pScreen->yOrigin + y);
1751	cmd.w = (uint16_t)w;
1752	cmd.h = (uint16_t)h;
1753
1754	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1755	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1756	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1757	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762	#endif /* IN_RING3 */
1763	#if defined(IN_RING0) \|\| defined(IN_RING3)
1764
1765	/**
1766	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1767	*
1768	* @param pThis The shared VGA/VMSVGA instance data.
1769	* @param pThisCC The VGA/VMSVGA state for the current context.
1770	* @param fState The busy state.
1771	*/
1772	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1773	{
1774	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1775
1776	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1777	{
1778	/* Race / unfortunately scheduling. Highly unlikly. */
1779	uint32_t cLoops = 64;
1780	do
1781	{
1782	ASMNopPause();
1783	fState = (pThis->svga.fBusy != 0);
1784	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1785	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1786	}
1787	}
1788
1789
1790	/**
1791	* Update the scanline pitch in response to the guest changing mode
1792	* width/bpp.
1793	*
1794	* @param pThis The shared VGA/VMSVGA state.
1795	* @param pThisCC The VGA/VMSVGA state for the current context.
1796	*/
1797	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1798	{
1799	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1800	uint32_t uFifoPitchLock = pThis->fVmSvga3 ? 0 : pFIFO[SVGA_FIFO_PITCHLOCK];
1801	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1802	uint32_t uFifoMin = pThis->fVmSvga3 ? 0 : pFIFO[SVGA_FIFO_MIN];
1803
1804	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1805	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1806	* location but it has a different meaning.
1807	*/
1808	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1809	uFifoPitchLock = 0;
1810
1811	/* Sanitize values. */
1812	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1813	uFifoPitchLock = 0;
1814	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1815	uRegPitchLock = 0;
1816
1817	/* Prefer the register value to the FIFO value.*/
1818	if (uRegPitchLock)
1819	pThis->svga.cbScanline = uRegPitchLock;
1820	else if (uFifoPitchLock)
1821	pThis->svga.cbScanline = uFifoPitchLock;
1822	else
1823	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1824
1825	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1826	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1827	}
1828
1829	#endif /* IN_RING0 \|\| IN_RING3 */
1830
1831	#ifdef IN_RING3
1832
1833	/**
1834	* Sends cursor position and visibility information from legacy
1835	* SVGA registers to the front-end.
1836	*/
1837	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1838	{
1839	/*
1840	* Writing the X/Y/ID registers does not trigger changes; only writing the
1841	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1842	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1843	* register if they don't have to.
1844	*/
1845	uint32_t x, y, idScreen;
1846	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1847
1848	x = pThis->svga.uCursorX;
1849	y = pThis->svga.uCursorY;
1850	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1851
1852	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1853	* were extended as follows:
1854	*
1855	* SVGA_CURSOR_ON_HIDE 0
1856	* SVGA_CURSOR_ON_SHOW 1
1857	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1858	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1859	*
1860	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1861	* distinguish between the non-zero values but still remember them.
1862	*/
1863	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1864	{
1865	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1866	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1867	}
1868	pThis->svga.uCursorOn = uCursorOn;
1869	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1870	}
1871
1872	#endif /* IN_RING3 */
1873
1874
1875	/**
1876	* Write port register
1877	*
1878	* @returns Strict VBox status code.
1879	* @param pDevIns The device instance.
1880	* @param pThis The shared VGA/VMSVGA state.
1881	* @param pThisCC The VGA/VMSVGA state for the current context.
1882	* @param idxReg Rge register index being written.
1883	* @param u32 Value to write
1884	*/
1885	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idxReg, uint32_t u32)
1886	{
1887	#ifdef IN_RING3
1888	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1889	#endif
1890	VBOXSTRICTRC rc = VINF_SUCCESS;
1891	RT_NOREF(pThisCC);
1892
1893	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1894	if ( idxReg >= SVGA_REG_ID_0_TOP
1895	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1896	{
1897	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1898	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1899	}
1900	#ifdef LOG_ENABLED
1901	if (idxReg != SVGA_REG_DEV_CAP)
1902	LogFlow(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1903	else
1904	LogFlow(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1905	#endif
1906	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1907	switch (idxReg)
1908	{
1909	case SVGA_REG_WIDTH:
1910	case SVGA_REG_HEIGHT:
1911	case SVGA_REG_PITCHLOCK:
1912	case SVGA_REG_BITS_PER_PIXEL:
1913	pThis->svga.fGFBRegisters = true;
1914	break;
1915	default:
1916	break;
1917	}
1918
1919	switch (idxReg)
1920	{
1921	case SVGA_REG_ID:
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1923	if ( u32 == SVGA_ID_0
1924	\|\| u32 == SVGA_ID_1
1925	\|\| u32 == SVGA_ID_2
1926	\|\| u32 == SVGA_ID_3)
1927	pThis->svga.u32SVGAId = u32;
1928	else
1929	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1930	break;
1931
1932	case SVGA_REG_ENABLE:
1933	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1934	#ifdef IN_RING3
1935	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1936	&& pThis->svga.fEnabled == false)
1937	{
1938	/* Make a backup copy of the first 512kb in order to save font data etc. */
1939	/** @todo should probably swap here, rather than copy + zero */
1940	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1941	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1942	}
1943
1944	pThis->svga.fEnabled = u32;
1945	if (pThis->svga.fEnabled)
1946	{
1947	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1948	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1949	{
1950	/* Keep the current mode. */
1951	pThis->svga.uWidth = pThisCC->pDrv->cx;
1952	pThis->svga.uHeight = pThisCC->pDrv->cy;
1953	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1954	vmsvgaHCUpdatePitch(pThis, pThisCC);
1955	}
1956
1957	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1958	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1959	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1960	# ifdef LOG_ENABLED
1961	if (!pThis->fVmSvga3)
1962	{
1963	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1964	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1965	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1966	}
1967	# endif
1968
1969	/* Disable or enable dirty page tracking according to the current fTraces value. */
1970	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1971
1972	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1973	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1974	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1975
1976	/* Make the cursor visible again as needed. */
1977	if (pSVGAState->Cursor.fActive)
1978	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1979	}
1980	else
1981	{
1982	/* Make sure the cursor is off. */
1983	if (pSVGAState->Cursor.fActive)
1984	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1985
1986	/* Restore the text mode backup. */
1987	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1988
1989	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1990
1991	/* Enable dirty page tracking again when going into legacy mode. */
1992	vmsvgaR3SetTraces(pDevIns, pThis, true);
1993
1994	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1995	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1996	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1997
1998	/* Clear the pitch lock. */
1999	pThis->svga.u32PitchLock = 0;
2000	}
2001	#else /* !IN_RING3 */
2002	rc = VINF_IOM_R3_IOPORT_WRITE;
2003	#endif /* !IN_RING3 */
2004	break;
2005
2006	case SVGA_REG_WIDTH:
2007	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
2008	if (u32 != pThis->svga.uWidth)
2009	{
2010	if (u32 <= pThis->svga.u32MaxWidth)
2011	{
2012	#if defined(IN_RING3) \|\| defined(IN_RING0)
2013	pThis->svga.uWidth = u32;
2014	vmsvgaHCUpdatePitch(pThis, pThisCC);
2015	if (pThis->svga.fEnabled)
2016	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2017	#else
2018	rc = VINF_IOM_R3_IOPORT_WRITE;
2019	#endif
2020	}
2021	else
2022	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
2023	}
2024	/* else: nop */
2025	break;
2026
2027	case SVGA_REG_HEIGHT:
2028	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
2029	if (u32 != pThis->svga.uHeight)
2030	{
2031	if (u32 <= pThis->svga.u32MaxHeight)
2032	{
2033	pThis->svga.uHeight = u32;
2034	if (pThis->svga.fEnabled)
2035	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2036	}
2037	else
2038	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
2039	}
2040	/* else: nop */
2041	break;
2042
2043	case SVGA_REG_DEPTH:
2044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
2045	/** @todo read-only?? */
2046	break;
2047
2048	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
2049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
2050	if (pThis->svga.uBpp != u32)
2051	{
2052	if (u32 <= 32)
2053	{
2054	#if defined(IN_RING3) \|\| defined(IN_RING0)
2055	pThis->svga.uBpp = u32;
2056	vmsvgaHCUpdatePitch(pThis, pThisCC);
2057	if (pThis->svga.fEnabled)
2058	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2059	#else
2060	rc = VINF_IOM_R3_IOPORT_WRITE;
2061	#endif
2062	}
2063	else
2064	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
2065	}
2066	/* else: nop */
2067	break;
2068
2069	case SVGA_REG_PSEUDOCOLOR:
2070	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
2071	break;
2072
2073	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
2074	#ifdef IN_RING3
2075	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
2076	pThis->svga.fConfigured = u32;
2077	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
2078	if (!pThis->svga.fConfigured)
2079	pThis->svga.fTraces = true;
2080	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2081	#else
2082	rc = VINF_IOM_R3_IOPORT_WRITE;
2083	#endif
2084	break;
2085
2086	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
2087	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
2088	if ( pThis->svga.fEnabled
2089	&& pThis->svga.fConfigured)
2090	{
2091	#if defined(IN_RING3) \|\| defined(IN_RING0)
2092	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
2093	/*
2094	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2095	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2096	*/
2097	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
2098	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2099	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2100
2101	/* Kick the FIFO thread to start processing commands again. */
2102	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2103	#else
2104	rc = VINF_IOM_R3_IOPORT_WRITE;
2105	#endif
2106	}
2107	/* else nothing to do. */
2108	else
2109	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2110
2111	break;
2112
2113	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2114	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2115	break;
2116
2117	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2119	pThis->svga.u32GuestId = u32;
2120	break;
2121
2122	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2123	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2124	pThis->svga.u32PitchLock = u32;
2125	/* Should this also update the FIFO pitch lock? Unclear. */
2126	break;
2127
2128	case SVGA_REG_IRQMASK: /* Interrupt mask */
2129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2130	pThis->svga.u32IrqMask = u32;
2131
2132	/* Irq pending after the above change? */
2133	if (pThis->svga.u32IrqStatus & u32)
2134	{
2135	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2136	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2137	}
2138	else
2139	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2140	break;
2141
2142	/* Mouse cursor support */
2143	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2145	pThis->svga.uCursorID = u32;
2146	break;
2147
2148	case SVGA_REG_CURSOR_X:
2149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2150	pThis->svga.uCursorX = u32;
2151	break;
2152
2153	case SVGA_REG_CURSOR_Y:
2154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2155	pThis->svga.uCursorY = u32;
2156	break;
2157
2158	case SVGA_REG_CURSOR_ON:
2159	#ifdef IN_RING3
2160	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2162	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2163	#else
2164	rc = VINF_IOM_R3_IOPORT_WRITE;
2165	#endif
2166	break;
2167
2168	/* Legacy multi-monitor support */
2169	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2171	break;
2172	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2174	break;
2175	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2177	break;
2178	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2180	break;
2181	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2183	break;
2184	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2186	break;
2187	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2189	break;
2190	#ifdef VBOX_WITH_VMSVGA3D
2191	/* See "Guest memory regions" below. */
2192	case SVGA_REG_GMR_ID:
2193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2194	pThis->svga.u32CurrentGMRId = u32;
2195	break;
2196
2197	case SVGA_REG_GMR_DESCRIPTOR:
2198	# ifndef IN_RING3
2199	rc = VINF_IOM_R3_IOPORT_WRITE;
2200	break;
2201	# else /* IN_RING3 */
2202	{
2203	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2204
2205	/* Validate current GMR id. */
2206	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2207	AssertBreak(idGMR < pThis->svga.cGMR);
2208	RT_UNTRUSTED_VALIDATED_FENCE();
2209
2210	/* Free the old GMR if present. */
2211	vmsvgaR3GmrFree(pThisCC, idGMR);
2212
2213	/* Just undefine the GMR? */
2214	RTGCPHYS GCPhys = (RTGCPHYS)u32 << GUEST_PAGE_SHIFT;
2215	if (GCPhys == 0)
2216	{
2217	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2218	break;
2219	}
2220
2221
2222	/* Never cross a page boundary automatically. */
2223	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2224	uint32_t cPagesTotal = 0;
2225	uint32_t iDesc = 0;
2226	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2227	uint32_t cLoops = 0;
2228	RTGCPHYS GCPhysBase = GCPhys;
2229	while ((GCPhys >> GUEST_PAGE_SHIFT) == (GCPhysBase >> GUEST_PAGE_SHIFT))
2230	{
2231	/* Read descriptor. */
2232	SVGAGuestMemDescriptor desc;
2233	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2234	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2235
2236	if (desc.numPages != 0)
2237	{
2238	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2239	cPagesTotal += desc.numPages;
2240	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2241
2242	if ((iDesc & 15) == 0)
2243	{
2244	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2245	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2246	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2247	}
2248
2249	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2250	paDescs[iDesc++].numPages = desc.numPages;
2251
2252	/* Continue with the next descriptor. */
2253	GCPhys += sizeof(desc);
2254	}
2255	else if (desc.ppn == 0)
2256	break; /* terminator */
2257	else /* Pointer to the next physical page of descriptors. */
2258	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2259
2260	cLoops++;
2261	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2262	}
2263
2264	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2265	if (RT_SUCCESS(rc))
2266	{
2267	/* Commit the GMR. */
2268	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2269	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2270	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2271	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * GUEST_PAGE_SIZE;
2272	Assert((pSVGAState->paGMR[idGMR].cbTotal >> GUEST_PAGE_SHIFT) == cPagesTotal);
2273	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2274	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2275	}
2276	else
2277	{
2278	RTMemFree(paDescs);
2279	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2280	}
2281	break;
2282	}
2283	# endif /* IN_RING3 */
2284	#endif // VBOX_WITH_VMSVGA3D
2285
2286	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2287	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2288	if (pThis->svga.fTraces == u32)
2289	break; /* nothing to do */
2290
2291	#ifdef IN_RING3
2292	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2293	#else
2294	rc = VINF_IOM_R3_IOPORT_WRITE;
2295	#endif
2296	break;
2297
2298	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2299	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2300	break;
2301
2302	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2304	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2305	break;
2306
2307	/*
2308	* SVGA_CAP_GBOBJECTS+ registers.
2309	*/
2310	case SVGA_REG_COMMAND_LOW:
2311	{
2312	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2313	#ifdef IN_RING3
2314	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2315	pThis->svga.u32RegCommandLow = u32;
2316
2317	/* "lower 6 bits are used for the SVGACBContext" */
2318	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2319	GCPhysCB <<= 32;
2320	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2321	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2322	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2323	#else
2324	rc = VINF_IOM_R3_IOPORT_WRITE;
2325	#endif
2326	break;
2327	}
2328
2329	case SVGA_REG_COMMAND_HIGH:
2330	/* Upper 32 bits of command buffer PA. */
2331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2332	pThis->svga.u32RegCommandHigh = u32;
2333	break;
2334
2335	case SVGA_REG_DEV_CAP:
2336	/* Write dev cap index, read value */
2337	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2338	pThis->svga.u32DevCapIndex = u32;
2339	break;
2340
2341	case SVGA_REG_CMD_PREPEND_LOW:
2342	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2343	/* Not supported. */
2344	break;
2345
2346	case SVGA_REG_CMD_PREPEND_HIGH:
2347	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2348	/* Not supported. */
2349	break;
2350
2351	case SVGA_REG_GUEST_DRIVER_ID:
2352	if (u32 != SVGA_REG_GUEST_DRIVER_ID_SUBMIT)
2353	pThis->svga.u32GuestDriverId = u32;
2354	break;
2355
2356	case SVGA_REG_GUEST_DRIVER_VERSION1:
2357	pThis->svga.u32GuestDriverVer1 = u32;
2358	break;
2359
2360	case SVGA_REG_GUEST_DRIVER_VERSION2:
2361	pThis->svga.u32GuestDriverVer2 = u32;
2362	break;
2363
2364	case SVGA_REG_GUEST_DRIVER_VERSION3:
2365	pThis->svga.u32GuestDriverVer3 = u32;
2366	break;
2367
2368	case SVGA_REG_CURSOR_MOBID:
2369	/* Not supported, ignore. See correspondent comments in vmsvgaReadPort. */
2370	break;
2371
2372	case SVGA_REG_FB_START:
2373	case SVGA_REG_MEM_START:
2374	case SVGA_REG_HOST_BITS_PER_PIXEL:
2375	case SVGA_REG_MAX_WIDTH:
2376	case SVGA_REG_MAX_HEIGHT:
2377	case SVGA_REG_VRAM_SIZE:
2378	case SVGA_REG_FB_SIZE:
2379	case SVGA_REG_CAPABILITIES:
2380	case SVGA_REG_MEM_SIZE:
2381	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2382	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2383	case SVGA_REG_BYTES_PER_LINE:
2384	case SVGA_REG_FB_OFFSET:
2385	case SVGA_REG_RED_MASK:
2386	case SVGA_REG_GREEN_MASK:
2387	case SVGA_REG_BLUE_MASK:
2388	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2389	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2390	case SVGA_REG_GMR_MAX_IDS:
2391	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2392	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2393	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2394	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2395	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2396	case SVGA_REG_MOB_MAX_SIZE:
2397	case SVGA_REG_BLANK_SCREEN_TARGETS:
2398	case SVGA_REG_CAP2:
2399	case SVGA_REG_DEVEL_CAP:
2400	case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
2401	case SVGA_REG_CURSOR_MAX_DIMENSION:
2402	case SVGA_REG_FIFO_CAPS:
2403	case SVGA_REG_FENCE:
2404	case SVGA_REG_RESERVED1:
2405	case SVGA_REG_RESERVED2:
2406	case SVGA_REG_RESERVED3:
2407	case SVGA_REG_RESERVED4:
2408	case SVGA_REG_RESERVED5:
2409	case SVGA_REG_SCREENDMA:
2410	case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
2411	/* Read only - ignore. */
2412	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2413	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2414	break;
2415
2416	case SVGA_REG_IRQ_STATUS:
2417	{
2418	if (pThis->fVmSvga3)
2419	{
2420	LogFlow(("vmsvga3MmioWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2421	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2422	/* Clear the irq in case all events have been cleared. */
2423	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2424	{
2425	Log(("vmsvga3MmioWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2426	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2427	}
2428	}
2429	break;
2430	}
2431
2432	default:
2433	{
2434	uint32_t offReg;
2435	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2436	{
2437	RT_UNTRUSTED_VALIDATED_FENCE();
2438	pThis->svga.au32ScratchRegion[offReg] = u32;
2439	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2440	}
2441	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2442	{
2443	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2444	Btw, see rgb_to_pixel32. */
2445	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2446	u32 &= 0xff;
2447	RT_UNTRUSTED_VALIDATED_FENCE();
2448	uint32_t uRgb = pThis->last_palette[offReg / 3];
2449	switch (offReg % 3)
2450	{
2451	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2452	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2453	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2454	}
2455	pThis->last_palette[offReg / 3] = uRgb;
2456	}
2457	else
2458	{
2459	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2460	rc = VINF_IOM_R3_IOPORT_WRITE;
2461	#else
2462	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2463	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2464	#endif
2465	}
2466	break;
2467	}
2468	}
2469	return rc;
2470	}
2471
2472	/**
2473	* @callback_method_impl{FNIOMIOPORTNEWIN}
2474	*/
2475	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2476	{
2477	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2478	RT_NOREF_PV(pvUser);
2479
2480	/* Only dword accesses. */
2481	if (cb == 4)
2482	{
2483	switch (offPort)
2484	{
2485	case SVGA_INDEX_PORT:
2486	*pu32 = pThis->svga.u32IndexReg;
2487	break;
2488
2489	case SVGA_VALUE_PORT:
2490	{
2491	/* Rough index register validation. */
2492	uint32_t idxReg = pThis->svga.u32IndexReg;
2493	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2494	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2495	VINF_IOM_R3_IOPORT_READ);
2496	#else
2497	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2498	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
2499	VINF_SUCCESS);
2500	#endif
2501	RT_UNTRUSTED_VALIDATED_FENCE();
2502
2503	return vmsvgaReadPort(pDevIns, pThis, idxReg, pu32);
2504	}
2505
2506	case SVGA_BIOS_PORT:
2507	Log(("Ignoring BIOS port read\n"));
2508	*pu32 = 0;
2509	break;
2510
2511	case SVGA_IRQSTATUS_PORT:
2512	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2513	*pu32 = pThis->svga.u32IrqStatus;
2514	break;
2515
2516	default:
2517	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2518	*pu32 = UINT32_MAX;
2519	break;
2520	}
2521	}
2522	else
2523	{
2524	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2525	*pu32 = UINT32_MAX;
2526	}
2527	return VINF_SUCCESS;
2528	}
2529
2530	/**
2531	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2532	*/
2533	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2534	{
2535	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2536	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2537	RT_NOREF_PV(pvUser);
2538
2539	/* Only dword accesses. */
2540	if (cb == 4)
2541	switch (offPort)
2542	{
2543	case SVGA_INDEX_PORT:
2544	pThis->svga.u32IndexReg = u32;
2545	break;
2546
2547	case SVGA_VALUE_PORT:
2548	{
2549	/* Rough index register validation. */
2550	uint32_t idxReg = pThis->svga.u32IndexReg;
2551	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2552	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2553	VINF_IOM_R3_IOPORT_WRITE);
2554	#else
2555	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2556	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
2557	VINF_SUCCESS);
2558	#endif
2559	RT_UNTRUSTED_VALIDATED_FENCE();
2560
2561	return vmsvgaWritePort(pDevIns, pThis, pThisCC, idxReg, u32);
2562	}
2563
2564	case SVGA_BIOS_PORT:
2565	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2566	break;
2567
2568	case SVGA_IRQSTATUS_PORT:
2569	LogFlow(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2570	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2571	/* Clear the irq in case all events have been cleared. */
2572	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2573	{
2574	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2575	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2576	}
2577	break;
2578
2579	default:
2580	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2581	break;
2582	}
2583	else
2584	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2585
2586	return VINF_SUCCESS;
2587	}
2588
2589	/**
2590	* @callback_method_impl{FNIOMMMIONEWREAD}
2591	*/
2592	DECLCALLBACK(VBOXSTRICTRC) vmsvga3MmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
2593	{
2594	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2595	RT_NOREF_PV(pvUser);
2596
2597	/* Only dword accesses. */
2598	VBOXSTRICTRC rcStrict;
2599	if (cb == sizeof(uint32_t))
2600	{
2601	rcStrict = vmsvgaReadPort(pDevIns, pThis, (uint32_t)(off / sizeof(uint32_t)), (uint32_t *)pv);
2602	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
2603	rcStrict = VINF_IOM_R3_MMIO_READ;
2604	}
2605	else
2606	{
2607	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", off, cb));
2608	rcStrict = VINF_IOM_MMIO_UNUSED_00;
2609	}
2610	return rcStrict;
2611	}
2612
2613	/**
2614	* @callback_method_impl{FNIOMMMIONEWWRITE}
2615	*/
2616	DECLCALLBACK(VBOXSTRICTRC) vmsvga3MmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
2617	{
2618	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2619	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2620	RT_NOREF_PV(pvUser);
2621
2622	/* Only dword accesses. */
2623	VBOXSTRICTRC rcStrict;
2624	if (cb == sizeof(uint32_t))
2625	{
2626	rcStrict = vmsvgaWritePort(pDevIns, pThis, pThisCC, (uint32_t)(off / sizeof(uint32_t)), (uint32_t )pv);
2627	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
2628	rcStrict = VINF_IOM_R3_MMIO_WRITE;
2629	}
2630	else
2631	{
2632	Log(("Ignoring non-dword write at %x cb=%d\n", off, cb));
2633	rcStrict = VINF_SUCCESS;
2634	}
2635
2636	return rcStrict;
2637	}
2638
2639	#ifdef IN_RING3
2640
2641	# ifdef DEBUG_FIFO_ACCESS
2642	/**
2643	* Handle FIFO memory access.
2644	* @returns VBox status code.
2645	* @param pVM VM handle.
2646	* @param pThis The shared VGA/VMSVGA instance data.
2647	* @param GCPhys The access physical address.
2648	* @param fWriteAccess Read or write access
2649	*/
2650	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2651	{
2652	RT_NOREF(pVM);
2653	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2654	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2655
2656	switch (GCPhysOffset >> 2)
2657	{
2658	case SVGA_FIFO_MIN:
2659	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660	break;
2661	case SVGA_FIFO_MAX:
2662	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663	break;
2664	case SVGA_FIFO_NEXT_CMD:
2665	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666	break;
2667	case SVGA_FIFO_STOP:
2668	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669	break;
2670	case SVGA_FIFO_CAPABILITIES:
2671	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672	break;
2673	case SVGA_FIFO_FLAGS:
2674	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675	break;
2676	case SVGA_FIFO_FENCE:
2677	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678	break;
2679	case SVGA_FIFO_3D_HWVERSION:
2680	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681	break;
2682	case SVGA_FIFO_PITCHLOCK:
2683	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684	break;
2685	case SVGA_FIFO_CURSOR_ON:
2686	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687	break;
2688	case SVGA_FIFO_CURSOR_X:
2689	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690	break;
2691	case SVGA_FIFO_CURSOR_Y:
2692	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693	break;
2694	case SVGA_FIFO_CURSOR_COUNT:
2695	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696	break;
2697	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2698	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699	break;
2700	case SVGA_FIFO_RESERVED:
2701	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702	break;
2703	case SVGA_FIFO_CURSOR_SCREEN_ID:
2704	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705	break;
2706	case SVGA_FIFO_DEAD:
2707	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708	break;
2709	case SVGA_FIFO_3D_HWVERSION_REVISED:
2710	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711	break;
2712	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2713	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2714	break;
2715	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2716	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2717	break;
2718	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2719	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2720	break;
2721	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2722	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2723	break;
2724	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2725	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2726	break;
2727	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2728	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2729	break;
2730	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2731	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2732	break;
2733	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2734	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2735	break;
2736	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2737	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2738	break;
2739	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2740	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2741	break;
2742	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2743	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2744	break;
2745	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2746	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2747	break;
2748	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2749	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2750	break;
2751	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2752	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2753	break;
2754	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2755	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2756	break;
2757	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2758	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2759	break;
2760	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2761	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2762	break;
2763	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2764	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2765	break;
2766	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2767	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2768	break;
2769	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2770	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2771	break;
2772	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2773	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2774	break;
2775	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2776	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2777	break;
2778	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2779	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2780	break;
2781	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2782	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2783	break;
2784	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2785	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2786	break;
2787	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2788	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2789	break;
2790	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2791	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2792	break;
2793	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2794	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2795	break;
2796	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2797	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2798	break;
2799	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2800	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2801	break;
2802	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2803	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2804	break;
2805	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2806	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2807	break;
2808	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2809	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2810	break;
2811	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2812	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2813	break;
2814	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2815	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2816	break;
2817	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2818	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2819	break;
2820	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2821	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2822	break;
2823	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2824	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2825	break;
2826	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2827	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2828	break;
2829	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2830	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2831	break;
2832	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2833	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2834	break;
2835	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2836	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2837	break;
2838	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2839	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2840	break;
2841	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2842	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2843	break;
2844	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2845	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2846	break;
2847	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2848	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2849	break;
2850	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2851	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2852	break;
2853	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2854	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2855	break;
2856	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2857	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2858	break;
2859	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2860	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2861	break;
2862	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2863	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2864	break;
2865	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2866	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2867	break;
2868	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2869	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2870	break;
2871	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2872	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2873	break;
2874	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2875	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2876	break;
2877	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2878	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2879	break;
2880	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2881	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2882	break;
2883	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2884	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2885	break;
2886	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2887	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2888	break;
2889	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2890	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2891	break;
2892	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2893	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2894	break;
2895	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2896	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2897	break;
2898	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2899	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2900	break;
2901	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2902	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2903	break;
2904	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2905	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2906	break;
2907	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2908	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2909	break;
2910	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2911	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2912	break;
2913	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2914	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2915	break;
2916	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2917	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2918	break;
2919	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2920	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2921	break;
2922	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2923	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2924	break;
2925	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2926	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2927	break;
2928	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2929	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2930	break;
2931	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2932	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2933	break;
2934	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2935	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2936	break;
2937	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2938	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2939	break;
2940	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2941	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2942	break;
2943	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2944	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2945	break;
2946	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2947	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2948	break;
2949	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2950	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2951	break;
2952	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2953	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2954	break;
2955	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2956	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2957	break;
2958	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2959	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2960	break;
2961	case SVGA_FIFO_3D_CAPS_LAST:
2962	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2963	break;
2964	case SVGA_FIFO_GUEST_3D_HWVERSION:
2965	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2966	break;
2967	case SVGA_FIFO_FENCE_GOAL:
2968	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2969	break;
2970	case SVGA_FIFO_BUSY:
2971	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2972	break;
2973	default:
2974	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2975	break;
2976	}
2977
2978	return VINF_EM_RAW_EMULATE_INSTR;
2979	}
2980	# endif /* DEBUG_FIFO_ACCESS */
2981
2982	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2983	/**
2984	* HC access handler for the FIFO.
2985	*
2986	* @returns VINF_SUCCESS if the handler have carried out the operation.
2987	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2988	* @param pVM VM Handle.
2989	* @param pVCpu The cross context CPU structure for the calling EMT.
2990	* @param GCPhys The physical address the guest is writing to.
2991	* @param pvPhys The HC mapping of that address.
2992	* @param pvBuf What the guest is reading/writing.
2993	* @param cbBuf How much it's reading/writing.
2994	* @param enmAccessType The access type.
2995	* @param enmOrigin Who is making the access.
2996	* @param pvUser User argument.
2997	*/
2998	static DECLCALLBACK(VBOXSTRICTRC)
2999	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3000	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3001	{
3002	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
3003	PVGASTATE pThis = (PVGASTATE)pvUser;
3004	AssertPtr(pThis);
3005
3006	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3007	/*
3008	* Wake up the FIFO thread as it might have work to do now.
3009	*/
3010	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3011	AssertLogRelRC(rc);
3012	# endif
3013
3014	# ifdef DEBUG_FIFO_ACCESS
3015	/*
3016	* When in debug-fifo-access mode, we do not disable the access handler,
3017	* but leave it on as we wish to catch all access.
3018	*/
3019	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
3020	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
3021	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
3022	/*
3023	* Temporarily disable the access handler now that we've kicked the FIFO thread.
3024	*/
3025	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
3026	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
3027	# endif
3028	if (RT_SUCCESS(rc))
3029	return VINF_PGM_HANDLER_DO_DEFAULT;
3030	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
3031	return rc;
3032	}
3033	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
3034
3035	#endif /* IN_RING3 */
3036
3037	#ifdef DEBUG_GMR_ACCESS
3038	# ifdef IN_RING3
3039
3040	/**
3041	* HC access handler for GMRs.
3042	*
3043	* @returns VINF_SUCCESS if the handler have carried out the operation.
3044	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3045	* @param pVM VM Handle.
3046	* @param pVCpu The cross context CPU structure for the calling EMT.
3047	* @param GCPhys The physical address the guest is writing to.
3048	* @param pvPhys The HC mapping of that address.
3049	* @param pvBuf What the guest is reading/writing.
3050	* @param cbBuf How much it's reading/writing.
3051	* @param enmAccessType The access type.
3052	* @param enmOrigin Who is making the access.
3053	* @param pvUser User argument.
3054	*/
3055	static DECLCALLBACK(VBOXSTRICTRC)
3056	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3057	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3058	{
3059	PVGASTATE pThis = (PVGASTATE)pvUser;
3060	Assert(pThis);
3061	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3062	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
3063
3064	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
3065
3066	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3067	{
3068	PGMR pGMR = &pSVGAState->paGMR[i];
3069
3070	if (pGMR->numDescriptors)
3071	{
3072	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3073	{
3074	if ( GCPhys >= pGMR->paDesc[j].GCPhys
3075	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * GUEST_PAGE_SIZE)
3076	{
3077	/*
3078	* Turn off the write handler for this particular page and make it R/W.
3079	* Then return telling the caller to restart the guest instruction.
3080	*/
3081	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
3082	AssertRC(rc);
3083	return VINF_PGM_HANDLER_DO_DEFAULT;
3084	}
3085	}
3086	}
3087	}
3088
3089	return VINF_PGM_HANDLER_DO_DEFAULT;
3090	}
3091
3092	/** Callback handler for VMR3ReqCallWaitU */
3093	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3094	{
3095	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3096	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3097	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3098	int rc;
3099
3100	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3101	{
3102	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, pGMR->paDesc[i].GCPhys,
3103	pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * GUEST_PAGE_SIZE - 1,
3104	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
3105	AssertRC(rc);
3106	}
3107	return VINF_SUCCESS;
3108	}
3109
3110	/** Callback handler for VMR3ReqCallWaitU */
3111	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3112	{
3113	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3114	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3115	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3116
3117	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3118	{
3119	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
3120	AssertRC(rc);
3121	}
3122	return VINF_SUCCESS;
3123	}
3124
3125	/** Callback handler for VMR3ReqCallWaitU */
3126	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
3127	{
3128	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3129
3130	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3131	{
3132	PGMR pGMR = &pSVGAState->paGMR[i];
3133
3134	if (pGMR->numDescriptors)
3135	{
3136	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3137	{
3138	int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
3139	AssertRC(rc);
3140	}
3141	}
3142	}
3143	return VINF_SUCCESS;
3144	}
3145
3146	# endif /* IN_RING3 */
3147	#endif /* DEBUG_GMR_ACCESS */
3148
3149	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3150
3151	#ifdef IN_RING3
3152
3153
3154	/*
3155	*
3156	* Command buffer submission.
3157	*
3158	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
3159	*
3160	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
3161	* and wakes up the FIFO thread.
3162	*
3163	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
3164	* the buffer header back to the guest memory.
3165	*
3166	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
3167	*
3168	*/
3169
3170
3171	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
3172	*
3173	* @param pDevIns The device instance.
3174	* @param GCPhysCB Guest physical address of the command buffer header.
3175	* @param status Command buffer status (SVGA_CB_STATUS_*).
3176	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
3177	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
3178	* @thread FIFO or EMT.
3179	*/
3180	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
3181	{
3182	SVGACBHeader hdr;
3183	hdr.status = status;
3184	hdr.errorOffset = errorOffset;
3185	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
3186	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
3187	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
3188	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
3189	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
3190	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
3191	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
3192	}
3193
3194
3195	/** Raise an IRQ.
3196	*
3197	* @param pDevIns The device instance.
3198	* @param pThis The shared VGA/VMSVGA state.
3199	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
3200	* @thread FIFO or EMT.
3201	*/
3202	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
3203	{
3204	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
3205	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
3206
3207	if (pThis->svga.u32IrqMask & u32IrqStatus)
3208	{
3209	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
3210	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3211	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3212	}
3213
3214	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3215	}
3216
3217
3218	/** Allocate a command buffer structure.
3219	*
3220	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
3221	* @return Pointer to the allocated command buffer structure.
3222	*/
3223	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
3224	{
3225	if (!pCmdBufCtx)
3226	return NULL;
3227
3228	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
3229	if (pCmdBuf)
3230	{
3231	// RT_ZERO(pCmdBuf->nodeBuffer);
3232	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
3233	// pCmdBuf->GCPhysCB = 0;
3234	// RT_ZERO(pCmdBuf->hdr);
3235	// pCmdBuf->pvCommands = NULL;
3236	}
3237
3238	return pCmdBuf;
3239	}
3240
3241
3242	/** Free a command buffer structure.
3243	*
3244	* @param pCmdBuf The command buffer pointer.
3245	*/
3246	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3247	{
3248	if (pCmdBuf)
3249	RTMemFree(pCmdBuf->pvCommands);
3250	RTMemFree(pCmdBuf);
3251	}
3252
3253
3254	/** Initialize a command buffer context.
3255	*
3256	* @param pCmdBufCtx The command buffer context.
3257	*/
3258	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3259	{
3260	RTListInit(&pCmdBufCtx->listSubmitted);
3261	pCmdBufCtx->cSubmitted = 0;
3262	}
3263
3264
3265	/** Destroy a command buffer context.
3266	*
3267	* @param pCmdBufCtx The command buffer context pointer.
3268	*/
3269	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3270	{
3271	if (!pCmdBufCtx)
3272	return;
3273
3274	if (pCmdBufCtx->listSubmitted.pNext)
3275	{
3276	/* If the list has been initialized. */
3277	PVMSVGACMDBUF pIter, pNext;
3278	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3279	{
3280	RTListNodeRemove(&pIter->nodeBuffer);
3281	--pCmdBufCtx->cSubmitted;
3282	vmsvgaR3CmdBufFree(pIter);
3283	}
3284	}
3285	Assert(pCmdBufCtx->cSubmitted == 0);
3286	pCmdBufCtx->cSubmitted = 0;
3287	}
3288
3289
3290	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3291	*
3292	* @param pSvgaR3State VMSVGA R3 state.
3293	* @param pCmd The command data.
3294	* @return SVGACBStatus code.
3295	* @thread EMT
3296	*/
3297	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3298	{
3299	/* Create or destroy a regular command buffer context. */
3300	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3301	return SVGA_CB_STATUS_COMMAND_ERROR;
3302	RT_UNTRUSTED_VALIDATED_FENCE();
3303
3304	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3305
3306	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3307	AssertRC(rc);
3308	if (pCmd->enable)
3309	{
3310	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3311	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3312	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3313	else
3314	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3315	}
3316	else
3317	{
3318	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3319	RTMemFree(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3320	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3321	}
3322	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3323
3324	return CBStatus;
3325	}
3326
3327
3328	/** Handles SVGA_DC_CMD_PREEMPT command.
3329	*
3330	* @param pDevIns The device instance.
3331	* @param pSvgaR3State VMSVGA R3 state.
3332	* @param pCmd The command data.
3333	* @return SVGACBStatus code.
3334	* @thread EMT
3335	*/
3336	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3337	{
3338	/* Remove buffers from the processing queue of the specified context. */
3339	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3340	return SVGA_CB_STATUS_COMMAND_ERROR;
3341	RT_UNTRUSTED_VALIDATED_FENCE();
3342
3343	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3344	RTLISTANCHOR listPreempted;
3345
3346	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3347	AssertRC(rc);
3348	if (pCmd->ignoreIDZero)
3349	{
3350	RTListInit(&listPreempted);
3351
3352	PVMSVGACMDBUF pIter, pNext;
3353	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3354	{
3355	if (pIter->hdr.id == 0)
3356	continue;
3357
3358	RTListNodeRemove(&pIter->nodeBuffer);
3359	--pCmdBufCtx->cSubmitted;
3360	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3361	}
3362	}
3363	else
3364	{
3365	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3366	pCmdBufCtx->cSubmitted = 0;
3367	}
3368	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3369
3370	PVMSVGACMDBUF pIter, pNext;
3371	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3372	{
3373	RTListNodeRemove(&pIter->nodeBuffer);
3374	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3375	LogFunc(("Preempted %RX64\n", pIter->GCPhysCB));
3376	vmsvgaR3CmdBufFree(pIter);
3377	}
3378
3379	return SVGA_CB_STATUS_COMPLETED;
3380	}
3381
3382
3383	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3384	* Increments the size of the command cbCmd by a_cbMore.
3385	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3386	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3387	*/
3388	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3389	if (1) { \
3390	cbCmd += (a_cbMore); \
3391	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3392	RT_UNTRUSTED_VALIDATED_FENCE(); \
3393	} else do {} while (0)
3394
3395
3396	/** Processes Device Context command buffer.
3397	*
3398	* @param pDevIns The device instance.
3399	* @param pSvgaR3State VMSVGA R3 state.
3400	* @param pvCommands Pointer to the command buffer.
3401	* @param cbCommands Size of the command buffer.
3402	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3403	* @return SVGACBStatus code.
3404	* @thread EMT
3405	*/
3406	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3407	{
3408	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3409
3410	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3411	uint32_t cbRemain = cbCommands;
3412	while (cbRemain)
3413	{
3414	/* Command identifier is a 32 bit value. */
3415	if (cbRemain < sizeof(uint32_t))
3416	{
3417	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3418	break;
3419	}
3420
3421	/* Fetch the command id. */
3422	uint32_t const cmdId = (uint32_t )pu8Cmd;
3423	uint32_t cbCmd = sizeof(uint32_t);
3424	switch (cmdId)
3425	{
3426	case SVGA_DC_CMD_NOP:
3427	{
3428	/* NOP */
3429	break;
3430	}
3431
3432	case SVGA_DC_CMD_START_STOP_CONTEXT:
3433	{
3434	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3435	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3436	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3437	break;
3438	}
3439
3440	case SVGA_DC_CMD_PREEMPT:
3441	{
3442	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3443	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3444	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3445	break;
3446	}
3447
3448	default:
3449	{
3450	/* Unsupported command. */
3451	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3452	break;
3453	}
3454	}
3455
3456	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3457	break;
3458
3459	pu8Cmd += cbCmd;
3460	cbRemain -= cbCmd;
3461	}
3462
3463	Assert(cbRemain <= cbCommands);
3464	*poffNextCmd = cbCommands - cbRemain;
3465	return CBstatus;
3466	}
3467
3468
3469	/** Submits a device context command buffer for synchronous processing.
3470	*
3471	* @param pDevIns The device instance.
3472	* @param pThisCC The VGA/VMSVGA state for the current context.
3473	* @param ppCmdBuf Pointer to the command buffer pointer.
3474	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3475	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3476	* @return SVGACBStatus code.
3477	* @thread EMT
3478	*/
3479	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3480	{
3481	/* Synchronously process the device context commands. */
3482	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3483	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3484	}
3485
3486	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3487	*
3488	* @param pDevIns The device instance.
3489	* @param pThis The shared VGA/VMSVGA state.
3490	* @param pThisCC The VGA/VMSVGA state for the current context.
3491	* @param ppCmdBuf Pointer to the command buffer pointer.
3492	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3493	* @return SVGACBStatus code.
3494	* @thread EMT
3495	*/
3496	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3497	{
3498	/* Command buffer submission. */
3499	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3500
3501	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3502
3503	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3504	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3505
3506	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3507	AssertRC(rc);
3508
3509	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3510	{
3511	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3512	++pCmdBufCtx->cSubmitted;
3513	ppCmdBuf = NULL; / Consume the buffer. */
3514	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3515	}
3516	else
3517	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3518
3519	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3520
3521	/* Inform the FIFO thread. */
3522	if (*ppCmdBuf == NULL)
3523	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3524
3525	return CBstatus;
3526	}
3527
3528
3529	/** SVGA_REG_COMMAND_LOW write handler.
3530	* Submits a command buffer to the FIFO thread or processes a device context command.
3531	*
3532	* @param pDevIns The device instance.
3533	* @param pThis The shared VGA/VMSVGA state.
3534	* @param pThisCC The VGA/VMSVGA state for the current context.
3535	* @param GCPhysCB Guest physical address of the command buffer header.
3536	* @param CBCtx Context the command buffer is submitted to.
3537	* @thread EMT
3538	*/
3539	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3540	{
3541	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3542
3543	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3544	uint32_t offNextCmd = 0;
3545	uint32_t fIRQ = 0;
3546
3547	/* Get the context if the device has the capability. */
3548	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3549	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3550	{
3551	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3552	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3553	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3554	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3555	RT_UNTRUSTED_VALIDATED_FENCE();
3556	}
3557
3558	/* Allocate a new command buffer. */
3559	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3560	if (RT_LIKELY(pCmdBuf))
3561	{
3562	pCmdBuf->GCPhysCB = GCPhysCB;
3563
3564	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3565	if (RT_SUCCESS(rc))
3566	{
3567	LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3568	pCmdBuf->hdr.status,
3569	pCmdBuf->hdr.errorOffset,
3570	pCmdBuf->hdr.id,
3571	pCmdBuf->hdr.flags,
3572	pCmdBuf->hdr.length,
3573	pCmdBuf->hdr.ptr.pa,
3574	pCmdBuf->hdr.offset,
3575	pCmdBuf->hdr.dxContext,
3576	pCmdBuf->hdr.mustBeZero[0],
3577	pCmdBuf->hdr.mustBeZero[1],
3578	pCmdBuf->hdr.mustBeZero[2],
3579	pCmdBuf->hdr.mustBeZero[3],
3580	pCmdBuf->hdr.mustBeZero[4],
3581	pCmdBuf->hdr.mustBeZero[5]));
3582
3583	/* Verify the command buffer header. */
3584	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3585	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3586	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3587	{
3588	RT_UNTRUSTED_VALIDATED_FENCE();
3589
3590	/* Read the command buffer content. */
3591	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3592	if (pCmdBuf->pvCommands)
3593	{
3594	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3595	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3596	if (RT_SUCCESS(rc))
3597	{
3598	/* Submit the buffer. Device context buffers will be processed synchronously. */
3599	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3600	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3601	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3602	else
3603	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3604	}
3605	else
3606	{
3607	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3608	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3609	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3610	}
3611	}
3612	else
3613	{
3614	/* No memory for commands. */
3615	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3616	}
3617	}
3618	else
3619	{
3620	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3621	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3622	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3623	}
3624	}
3625	else
3626	{
3627	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3628	ASSERT_GUEST_FAILED();
3629	/* Do not attempt to write the status. */
3630	}
3631
3632	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3633	vmsvgaR3CmdBufFree(pCmdBuf);
3634	}
3635	else
3636	{
3637	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3638	AssertFailed();
3639	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3640	}
3641
3642	if (CBstatus != SVGA_CB_STATUS_NONE)
3643	{
3644	LogFunc(("Write status %#x, offNextCmd %#x, fIRQ %#x\n", CBstatus, offNextCmd, fIRQ));
3645	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3646	if (fIRQ)
3647	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3648	}
3649	}
3650
3651
3652	/** Checks if there are some buffers to be processed.
3653	*
3654	* @param pThisCC The VGA/VMSVGA state for the current context.
3655	* @return true if buffers must be processed.
3656	* @thread FIFO
3657	*/
3658	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3659	{
3660	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3661	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3662	}
3663
3664
3665	/** Processes a command buffer.
3666	*
3667	* @param pDevIns The device instance.
3668	* @param pThis The shared VGA/VMSVGA state.
3669	* @param pThisCC The VGA/VMSVGA state for the current context.
3670	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3671	* @param pvCommands Pointer to the command buffer.
3672	* @param cbCommands Size of the command buffer.
3673	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3674	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3675	* @return SVGACBStatus code.
3676	* @thread FIFO
3677	*/
3678	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3679	{
3680	# ifndef VBOX_WITH_VMSVGA3D
3681	RT_NOREF(idDXContext);
3682	# endif
3683	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3684	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3685
3686	# ifdef VBOX_WITH_VMSVGA3D
3687	# ifdef VMSVGA3D_DX
3688	/* Commands submitted for the SVGA3D_INVALID_ID context do not affect pipeline. So ignore them. */
3689	if (idDXContext != SVGA3D_INVALID_ID)
3690	{
3691	if (pSvgaR3State->idDXContextCurrent != idDXContext)
3692	{
3693	LogFlow(("DXCTX: buffer %d->%d\n", pSvgaR3State->idDXContextCurrent, idDXContext));
3694	vmsvga3dDXSwitchContext(pThisCC, idDXContext);
3695	pSvgaR3State->idDXContextCurrent = idDXContext;
3696	}
3697	}
3698	# endif
3699	# endif
3700
3701	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3702
3703	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3704	uint32_t cbRemain = cbCommands;
3705	while (cbRemain)
3706	{
3707	/* Command identifier is a 32 bit value. */
3708	if (cbRemain < sizeof(uint32_t))
3709	{
3710	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3711	break;
3712	}
3713
3714	/* Fetch the command id.
3715	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3716	* warning. Because we support some obsolete and deprecated commands, which are not included in
3717	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3718	*/
3719	uint32_t const cmdId = (uint32_t )pu8Cmd;
3720	uint32_t cbCmd = sizeof(uint32_t);
3721
3722	LogFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3723	# ifdef LOG_ENABLED
3724	# ifdef VBOX_WITH_VMSVGA3D
3725	if ( (cmdId >= SVGA_3D_CMD_BASE && cmdId < SVGA_3D_CMD_MAX)
3726	\|\| (cmdId >= VBSVGA_3D_CMD_BASE && cmdId < VBSVGA_3D_CMD_MAX))
3727	{
3728	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3729	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3730	}
3731	else if (cmdId == SVGA_CMD_FENCE)
3732	{
3733	Log7(("\tSVGA_CMD_FENCE\n"));
3734	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3735	}
3736	# endif
3737	# endif
3738
3739	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3740	* I.e. pu8Cmd + cbCmd must point to the next command.
3741	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3742	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3743	*/
3744	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3745	LogFlow(("cmdId=%u\n", cmdId));
3746	switch (cmdId)
3747	{
3748	case SVGA_CMD_INVALID_CMD:
3749	{
3750	/* Nothing to do. */
3751	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3752	break;
3753	}
3754
3755	case SVGA_CMD_FENCE:
3756	{
3757	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3758	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3759	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3760	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3761
3762	if (pThis->fVmSvga3)
3763	{
3764	pThis->svga.u32FenceLast = pCmd->fence;
3765
3766	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3767	{
3768	Log(("any fence irq\n"));
3769	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3770	}
3771	else if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3772	{
3773	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3774	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3775	}
3776	}
3777	else
3778	{
3779	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3780	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3781	{
3782	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3783
3784	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3785	{
3786	Log(("any fence irq\n"));
3787	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3788	}
3789	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3790	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3791	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3792	{
3793	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3794	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3795	}
3796	}
3797	else
3798	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3799	}
3800	break;
3801	}
3802
3803	case SVGA_CMD_UPDATE:
3804	{
3805	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3806	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3807	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3808	break;
3809	}
3810
3811	case SVGA_CMD_UPDATE_VERBOSE:
3812	{
3813	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3814	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3815	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3816	break;
3817	}
3818
3819	case SVGA_CMD_DEFINE_CURSOR:
3820	{
3821	/* Followed by bitmap data. */
3822	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3823	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3824
3825	/* Figure out the size of the bitmap data. */
3826	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3827	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3828	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3829	RT_UNTRUSTED_VALIDATED_FENCE();
3830
3831	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3832	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3833	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3834	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3835
3836	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3837	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3838	break;
3839	}
3840
3841	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3842	{
3843	/* Followed by bitmap data. */
3844	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3845	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3846
3847	/* Figure out the size of the bitmap data. */
3848	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3849
3850	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3851	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3852	break;
3853	}
3854
3855	case SVGA_CMD_MOVE_CURSOR:
3856	{
3857	/* Deprecated; there should be no driver which requires this command. However, if
3858	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3859	* alignment.
3860	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3861	*/
3862	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3863	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3864	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3865	break;
3866	}
3867
3868	case SVGA_CMD_DISPLAY_CURSOR:
3869	{
3870	/* Deprecated; there should be no driver which requires this command. However, if
3871	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3872	* alignment.
3873	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3874	*/
3875	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3876	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3877	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3878	break;
3879	}
3880
3881	case SVGA_CMD_RECT_FILL:
3882	{
3883	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3884	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3885	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3886	break;
3887	}
3888
3889	case SVGA_CMD_RECT_COPY:
3890	{
3891	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3892	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3893	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3894	break;
3895	}
3896
3897	case SVGA_CMD_RECT_ROP_COPY:
3898	{
3899	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3900	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3901	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3902	break;
3903	}
3904
3905	case SVGA_CMD_ESCAPE:
3906	{
3907	/* Followed by 'size' bytes of data. */
3908	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3909	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3910
3911	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3912	RT_UNTRUSTED_VALIDATED_FENCE();
3913
3914	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3915	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3916	break;
3917	}
3918	# ifdef VBOX_WITH_VMSVGA3D
3919	case SVGA_CMD_DEFINE_GMR2:
3920	{
3921	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3922	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3923	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3924	break;
3925	}
3926
3927	case SVGA_CMD_REMAP_GMR2:
3928	{
3929	/* Followed by page descriptors or guest ptr. */
3930	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3931	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3932
3933	/* Calculate the size of what comes after next and fetch it. */
3934	uint32_t cbMore = 0;
3935	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3936	cbMore = sizeof(SVGAGuestPtr);
3937	else
3938	{
3939	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3940	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3941	{
3942	cbMore = cbPageDesc;
3943	pCmd->numPages = 1;
3944	}
3945	else
3946	{
3947	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3948	cbMore = cbPageDesc * pCmd->numPages;
3949	}
3950	}
3951	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3952	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3953	# ifdef DEBUG_GMR_ACCESS
3954	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3955	# endif
3956	break;
3957	}
3958	# endif /* VBOX_WITH_VMSVGA3D */
3959	case SVGA_CMD_DEFINE_SCREEN:
3960	{
3961	/* The size of this command is specified by the guest and depends on capabilities. */
3962	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3963	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3964	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3965	RT_UNTRUSTED_VALIDATED_FENCE();
3966
3967	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3968	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3969	break;
3970	}
3971
3972	case SVGA_CMD_DESTROY_SCREEN:
3973	{
3974	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3975	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3976	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3977	break;
3978	}
3979
3980	case SVGA_CMD_DEFINE_GMRFB:
3981	{
3982	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3983	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3984	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3985	break;
3986	}
3987
3988	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3989	{
3990	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3991	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3992	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3993	break;
3994	}
3995
3996	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3997	{
3998	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3999	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4000	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4001	break;
4002	}
4003
4004	case SVGA_CMD_ANNOTATION_FILL:
4005	{
4006	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
4007	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4008	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4009	break;
4010	}
4011
4012	case SVGA_CMD_ANNOTATION_COPY:
4013	{
4014	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
4015	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4016	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4017	break;
4018	}
4019
4020	default:
4021	{
4022	# ifdef VBOX_WITH_VMSVGA3D
4023	if ( (cmdId >= SVGA_3D_CMD_BASE && cmdId < SVGA_3D_CMD_MAX)
4024	\|\| ( pThis->svga.fVBoxExtensions
4025	&& (cmdId >= VBSVGA_3D_CMD_BASE && cmdId < VBSVGA_3D_CMD_MAX)))
4026	{
4027	RT_UNTRUSTED_VALIDATED_FENCE();
4028
4029	/* All 3d commands start with a common header, which defines the identifier and the size
4030	* of the command. The identifier has been already read. Fetch the size.
4031	*/
4032	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
4033	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
4034	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
4035	if (RT_LIKELY(pThis->svga.f3DEnabled))
4036	{ /* likely */ }
4037	else
4038	{
4039	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
4040	break;
4041	}
4042
4043	/* Command data begins after the 32 bit command length. */
4044	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
4045	if (RT_SUCCESS(rc))
4046	{ /* likely */ }
4047	else
4048	{
4049	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4050	break;
4051	}
4052	}
4053	else
4054	# endif /* VBOX_WITH_VMSVGA3D */
4055	{
4056	/* Unsupported command. */
4057	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
4058	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
4059	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
4060	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4061	break;
4062	}
4063	}
4064	}
4065
4066	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
4067	break;
4068
4069	pu8Cmd += cbCmd;
4070	cbRemain -= cbCmd;
4071
4072	/* If this is not the last command in the buffer, then generate IRQ, if required.
4073	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
4074	* in the buffer (usually the case).
4075	*/
4076	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
4077	{ /* likely */ }
4078	else
4079	{
4080	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
4081	*pu32IrqStatus = 0;
4082	}
4083	}
4084
4085	Assert(cbRemain <= cbCommands);
4086	*poffNextCmd = cbCommands - cbRemain;
4087	return CBstatus;
4088	}
4089
4090
4091	/** Process command buffers.
4092	*
4093	* @param pDevIns The device instance.
4094	* @param pThis The shared VGA/VMSVGA state.
4095	* @param pThisCC The VGA/VMSVGA state for the current context.
4096	* @param pThread Handle of the FIFO thread.
4097	* @thread FIFO
4098	*/
4099	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
4100	{
4101	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4102
4103	for (;;)
4104	{
4105	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4106	break;
4107
4108	/* See if there is a submitted buffer. */
4109	PVMSVGACMDBUF pCmdBuf = NULL;
4110
4111	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
4112	AssertRC(rc);
4113
4114	/* It seems that a higher queue index has a higher priority.
4115	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
4116	*/
4117	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
4118	{
4119	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
4120	if (pCmdBufCtx)
4121	{
4122	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
4123	if (pCmdBuf)
4124	{
4125	Assert(pCmdBufCtx->cSubmitted > 0);
4126	--pCmdBufCtx->cSubmitted;
4127	break;
4128	}
4129	}
4130	}
4131
4132	if (!pCmdBuf)
4133	{
4134	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
4135	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4136	break;
4137	}
4138
4139	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4140
4141	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
4142	uint32_t offNextCmd = 0;
4143	uint32_t u32IrqStatus = 0;
4144	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
4145	? pCmdBuf->hdr.dxContext
4146	: SVGA3D_INVALID_ID;
4147	/* Process one buffer. */
4148	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
4149
4150	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
4151	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
4152	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
4153	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
4154
4155	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
4156	if (u32IrqStatus)
4157	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
4158
4159	vmsvgaR3CmdBufFree(pCmdBuf);
4160	}
4161	}
4162
4163
4164	/**
4165	* Worker for vmsvgaR3FifoThread that handles an external command.
4166	*
4167	* @param pDevIns The device instance.
4168	* @param pThis The shared VGA/VMSVGA instance data.
4169	* @param pThisCC The VGA/VMSVGA state for ring-3.
4170	*/
4171	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4172	{
4173	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
4174	switch (pThis->svga.u8FIFOExtCommand)
4175	{
4176	case VMSVGA_FIFO_EXTCMD_RESET:
4177	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
4178	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4179
4180	vmsvgaR3ResetScreens(pThis, pThisCC);
4181	# ifdef VBOX_WITH_VMSVGA3D
4182	/* The 3d subsystem must be reset from the fifo thread. */
4183	if (pThis->svga.f3DEnabled)
4184	vmsvga3dReset(pThisCC);
4185	# endif
4186	vmsvgaR3ResetSvgaState(pThis, pThisCC);
4187	break;
4188
4189	case VMSVGA_FIFO_EXTCMD_POWEROFF:
4190	Log(("vmsvgaR3FifoLoop: power off.\n"));
4191	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4192
4193	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
4194	vmsvgaR3ResetScreens(pThis, pThisCC);
4195	break;
4196
4197	case VMSVGA_FIFO_EXTCMD_TERMINATE:
4198	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
4199	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4200
4201	# ifdef VBOX_WITH_VMSVGA3D
4202	/* The 3d subsystem must be shut down from the fifo thread. */
4203	if (pThis->svga.f3DEnabled)
4204	vmsvga3dTerminate(pThisCC);
4205	# endif
4206	vmsvgaR3TerminateSvgaState(pThis, pThisCC);
4207	break;
4208
4209	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
4210	{
4211	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
4212	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
4213	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
4214	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
4215	# ifdef VBOX_WITH_VMSVGA3D
4216	if (pThis->svga.f3DEnabled)
4217	{
4218	if (vmsvga3dIsLegacyBackend(pThisCC))
4219	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
4220	# ifdef VMSVGA3D_DX
4221	else
4222	vmsvga3dDXSaveExec(pDevIns, pThisCC, pSSM);
4223	# endif
4224	}
4225	# endif
4226	break;
4227	}
4228
4229	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
4230	{
4231	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
4232	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
4233	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
4234	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4235	# ifdef VBOX_WITH_VMSVGA3D
4236	if (pThis->svga.f3DEnabled)
4237	{
4238	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
4239	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
4240	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
4241	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
4242	# endif
4243
4244	if (vmsvga3dIsLegacyBackend(pThisCC))
4245	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4246	# ifdef VMSVGA3D_DX
4247	else
4248	vmsvga3dDXLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4249	# endif
4250	}
4251	# endif
4252	break;
4253	}
4254
4255	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
4256	{
4257	# ifdef VBOX_WITH_VMSVGA3D
4258	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
4259	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
4260	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
4261	# endif
4262	break;
4263	}
4264
4265
4266	default:
4267	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
4268	break;
4269	}
4270
4271	/*
4272	* Signal the end of the external command.
4273	*/
4274	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4275	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
4276	ASMMemoryFence(); /* paranoia^2 */
4277	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
4278	AssertLogRelRC(rc);
4279	}
4280
4281	/**
4282	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
4283	* doing a job on the FIFO thread (even when it's officially suspended).
4284	*
4285	* @returns VBox status code (fully asserted).
4286	* @param pDevIns The device instance.
4287	* @param pThis The shared VGA/VMSVGA instance data.
4288	* @param pThisCC The VGA/VMSVGA state for ring-3.
4289	* @param uExtCmd The command to execute on the FIFO thread.
4290	* @param pvParam Pointer to command parameters.
4291	* @param cMsWait The time to wait for the command, given in
4292	* milliseconds.
4293	*/
4294	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4295	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4296	{
4297	Assert(cMsWait >= RT_MS_1SEC * 5);
4298	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4299	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4300
4301	int rc;
4302	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4303	PDMTHREADSTATE enmState = pThread->enmState;
4304	if (enmState == PDMTHREADSTATE_SUSPENDED)
4305	{
4306	/*
4307	* The thread is suspended, we have to temporarily wake it up so it can
4308	* perform the task.
4309	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4310	*/
4311	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4312	/* Post the request. */
4313	pThis->svga.fFifoExtCommandWakeup = true;
4314	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4315	pThis->svga.u8FIFOExtCommand = uExtCmd;
4316	ASMMemoryFence(); /* paranoia^3 */
4317
4318	/* Resume the thread. */
4319	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4320	AssertLogRelRC(rc);
4321	if (RT_SUCCESS(rc))
4322	{
4323	/* Wait. Take care in case the semaphore was already posted (same as below). */
4324	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4325	if ( rc == VINF_SUCCESS
4326	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4327	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4328	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4329	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4330
4331	/* suspend the thread */
4332	pThis->svga.fFifoExtCommandWakeup = false;
4333	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4334	AssertLogRelRC(rc2);
4335	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4336	rc = rc2;
4337	}
4338	pThis->svga.fFifoExtCommandWakeup = false;
4339	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4340	}
4341	else if (enmState == PDMTHREADSTATE_RUNNING)
4342	{
4343	/*
4344	* The thread is running, should only happen during reset and vmsvga3dsfc.
4345	* We ASSUME not racing code here, both wrt thread state and ext commands.
4346	*/
4347	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4348	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4349
4350	/* Post the request. */
4351	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4352	pThis->svga.u8FIFOExtCommand = uExtCmd;
4353	ASMMemoryFence(); /* paranoia^2 */
4354	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4355	AssertLogRelRC(rc);
4356
4357	/* Wait. Take care in case the semaphore was already posted (same as above). */
4358	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4359	if ( rc == VINF_SUCCESS
4360	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4361	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4362	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4363	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4364
4365	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4366	}
4367	else
4368	{
4369	/*
4370	* Something is wrong with the thread!
4371	*/
4372	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4373	rc = VERR_INVALID_STATE;
4374	}
4375	return rc;
4376	}
4377
4378
4379	/**
4380	* Marks the FIFO non-busy, notifying any waiting EMTs.
4381	*
4382	* @param pDevIns The device instance.
4383	* @param pThis The shared VGA/VMSVGA instance data.
4384	* @param pThisCC The VGA/VMSVGA state for ring-3.
4385	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4386	* @param offFifoMin The start byte offset of the command FIFO.
4387	*/
4388	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4389	{
4390	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4391	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4392	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4393
4394	/* Wake up any waiting EMTs. */
4395	if (pSVGAState->cBusyDelayedEmts > 0)
4396	{
4397	# ifdef VMSVGA_USE_EMT_HALT_CODE
4398	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4399	if (idCpu != NIL_VMCPUID)
4400	{
4401	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4402	while (idCpu-- > 0)
4403	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4404	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4405	}
4406	# else
4407	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4408	AssertRC(rc2);
4409	# endif
4410	}
4411	}
4412
4413	/**
4414	* Reads (more) payload into the command buffer.
4415	*
4416	* @returns pbBounceBuf on success
4417	* @retval (void *)1 if the thread was requested to stop.
4418	* @retval NULL on FIFO error.
4419	*
4420	* @param cbPayloadReq The number of bytes of payload requested.
4421	* @param pFIFO The FIFO.
4422	* @param offCurrentCmd The FIFO byte offset of the current command.
4423	* @param offFifoMin The start byte offset of the command FIFO.
4424	* @param offFifoMax The end byte offset of the command FIFO.
4425	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4426	* always sufficient size.
4427	* @param pcbAlreadyRead How much payload we've already read into the bounce
4428	* buffer. (We will NEVER re-read anything.)
4429	* @param pThread The calling PDM thread handle.
4430	* @param pThis The shared VGA/VMSVGA instance data.
4431	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4432	* statistics collection.
4433	* @param pDevIns The device instance.
4434	*/
4435	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4436	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4437	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4438	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4439	{
4440	Assert(pbBounceBuf);
4441	Assert(pcbAlreadyRead);
4442	Assert(offFifoMin < offFifoMax);
4443	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4444	Assert(offFifoMax <= pThis->svga.cbFIFO);
4445
4446	/*
4447	* Check if the requested payload size has already been satisfied .
4448	* .
4449	* When called to read more, the caller is responsible for making sure the .
4450	* new command size (cbRequsted) never is smaller than what has already .
4451	* been read.
4452	*/
4453	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4454	if (cbPayloadReq <= cbAlreadyRead)
4455	{
4456	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4457	return pbBounceBuf;
4458	}
4459
4460	/*
4461	* Commands bigger than the fifo buffer are invalid.
4462	*/
4463	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4464	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4465	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4466	NULL);
4467
4468	/*
4469	* Move offCurrentCmd past the command dword.
4470	*/
4471	offCurrentCmd += sizeof(uint32_t);
4472	if (offCurrentCmd >= offFifoMax)
4473	offCurrentCmd = offFifoMin;
4474
4475	/*
4476	* Do we have sufficient payload data available already?
4477	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4478	*/
4479	uint32_t cbAfter, cbBefore;
4480	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4481	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4482	if (offNextCmd >= offCurrentCmd)
4483	{
4484	if (RT_LIKELY(offNextCmd < offFifoMax))
4485	cbAfter = offNextCmd - offCurrentCmd;
4486	else
4487	{
4488	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4489	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4490	offNextCmd, offFifoMin, offFifoMax));
4491	cbAfter = offFifoMax - offCurrentCmd;
4492	}
4493	cbBefore = 0;
4494	}
4495	else
4496	{
4497	cbAfter = offFifoMax - offCurrentCmd;
4498	if (offNextCmd >= offFifoMin)
4499	cbBefore = offNextCmd - offFifoMin;
4500	else
4501	{
4502	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4503	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4504	offNextCmd, offFifoMin, offFifoMax));
4505	cbBefore = 0;
4506	}
4507	}
4508	if (cbAfter + cbBefore < cbPayloadReq)
4509	{
4510	/*
4511	* Insufficient, must wait for it to arrive.
4512	*/
4513	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4514	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4515	for (uint32_t i = 0;; i++)
4516	{
4517	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4518	{
4519	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4520	return (void *)(uintptr_t)1;
4521	}
4522	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4523	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4524
4525	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4526
4527	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4528	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4529	if (offNextCmd >= offCurrentCmd)
4530	{
4531	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4532	cbBefore = 0;
4533	}
4534	else
4535	{
4536	cbAfter = offFifoMax - offCurrentCmd;
4537	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4538	}
4539
4540	if (cbAfter + cbBefore >= cbPayloadReq)
4541	break;
4542	}
4543	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4544	}
4545
4546	/*
4547	* Copy out the memory and update what pcbAlreadyRead points to.
4548	*/
4549	if (cbAfter >= cbPayloadReq)
4550	memcpy(pbBounceBuf + cbAlreadyRead,
4551	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4552	cbPayloadReq - cbAlreadyRead);
4553	else
4554	{
4555	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4556	if (cbAlreadyRead < cbAfter)
4557	{
4558	memcpy(pbBounceBuf + cbAlreadyRead,
4559	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4560	cbAfter - cbAlreadyRead);
4561	cbAlreadyRead = cbAfter;
4562	}
4563	memcpy(pbBounceBuf + cbAlreadyRead,
4564	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4565	cbPayloadReq - cbAlreadyRead);
4566	}
4567	*pcbAlreadyRead = cbPayloadReq;
4568	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4569	return pbBounceBuf;
4570	}
4571
4572
4573	/**
4574	* Sends cursor position and visibility information from the FIFO to the front-end.
4575	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4576	*/
4577	static uint32_t
4578	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4579	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4580	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4581	{
4582	/*
4583	* Check if the cursor update counter has changed and try get a stable
4584	* set of values if it has. This is race-prone, especially consindering
4585	* the screen ID, but little we can do about that.
4586	*/
4587	uint32_t x, y, fVisible, idScreen;
4588	for (uint32_t i = 0; ; i++)
4589	{
4590	x = pFIFO[SVGA_FIFO_CURSOR_X];
4591	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4592	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4593	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4594	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4595	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4596	\|\| i > 3)
4597	break;
4598	if (i == 0)
4599	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4600	ASMNopPause();
4601	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4602	}
4603
4604	/*
4605	* Check if anything has changed, as calling into pDrv is not light-weight.
4606	*/
4607	if ( *pxLast == x
4608	&& *pyLast == y
4609	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4610	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4611	else
4612	{
4613	/*
4614	* Detected changes.
4615	*
4616	* We handle global, not per-screen visibility information by sending
4617	* pfnVBVAMousePointerShape without shape data.
4618	*/
4619	*pxLast = x;
4620	*pyLast = y;
4621	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4622	if (idScreen != SVGA_ID_INVALID)
4623	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4624	else if (*pfLastVisible != fVisible)
4625	{
4626	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4627	*pfLastVisible = fVisible;
4628	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4629	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4630	}
4631	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4632	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4633	}
4634
4635	/*
4636	* Update done. Signal this to the guest.
4637	*/
4638	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4639
4640	return uCursorUpdateCount;
4641	}
4642
4643
4644	/**
4645	* Checks if there is work to be done, either cursor updating or FIFO commands.
4646	*
4647	* @returns true if pending work, false if not.
4648	* @param pThisCC The VGA/VMSVGA state for ring-3.
4649	* @param uLastCursorCount The last cursor update counter value.
4650	*/
4651	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4652	{
4653	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4654	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4655	AssertReturn(pFIFO, false);
4656
4657	if (vmsvgaR3CmdBufHasWork(pThisCC))
4658	return true;
4659
4660	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4661	return true;
4662
4663	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4664	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4665	return true;
4666
4667	return false;
4668	}
4669
4670
4671	/**
4672	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4673	*
4674	* @param pDevIns The device instance.
4675	* @param pThis The shared VGA/VMSVGA instance data.
4676	* @param pThisCC The VGA/VMSVGA state for ring-3.
4677	*/
4678	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4679	{
4680	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4681	to recheck it before doing the signalling. */
4682	if ( (pThis->fVmSvga3 \|\| vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount)))
4683	&& pThis->svga.fFIFOThreadSleeping
4684	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4685	{
4686	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4687	AssertRC(rc);
4688	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4689	}
4690	}
4691
4692
4693	/**
4694	* Called by the FIFO thread to process pending actions.
4695	*
4696	* @param pDevIns The device instance.
4697	* @param pThis The shared VGA/VMSVGA instance data.
4698	* @param pThisCC The VGA/VMSVGA state for ring-3.
4699	*/
4700	static void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4701	{
4702	RT_NOREF(pDevIns);
4703
4704	/* Currently just mode changes. */
4705	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4706	{
4707	vmsvgaR3ChangeMode(pThis, pThisCC);
4708	# ifdef VBOX_WITH_VMSVGA3D
4709	if (pThisCC->svga.p3dState != NULL)
4710	vmsvga3dChangeMode(pThisCC);
4711	# endif
4712	}
4713	}
4714
4715
4716	/*
4717	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4718	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4719	*/
4720	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4721	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4722	*
4723	* Will break out of the switch on failure.
4724	* Will restart and quit the loop if the thread was requested to stop.
4725	*
4726	* @param a_PtrVar Request variable pointer.
4727	* @param a_Type Request typedef (not pointer) for casting.
4728	* @param a_cbPayloadReq How much payload to fetch.
4729	* @remarks Accesses a bunch of variables in the current scope!
4730	*/
4731	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4732	if (1) { \
4733	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4734	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4735	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4736	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4737	} else do {} while (0)
4738	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4739	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4740	* buffer after figuring out the actual command size.
4741	*
4742	* Will break out of the switch on failure.
4743	*
4744	* @param a_PtrVar Request variable pointer.
4745	* @param a_Type Request typedef (not pointer) for casting.
4746	* @param a_cbPayloadReq How much payload to fetch.
4747	* @remarks Accesses a bunch of variables in the current scope!
4748	*/
4749	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4750	if (1) { \
4751	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4752	} else do {} while (0)
4753
4754	/**
4755	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4756	*/
4757	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4758	{
4759	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4760	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4761	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4762	int rc;
4763
4764	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4765	return VINF_SUCCESS;
4766
4767	/*
4768	* Special mode where we only execute an external command and the go back
4769	* to being suspended. Currently, all ext cmds ends up here, with the reset
4770	* one also being eligble for runtime execution further down as well.
4771	*/
4772	if (pThis->svga.fFifoExtCommandWakeup)
4773	{
4774	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4775	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4776	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4777	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4778	else
4779	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4780	return VINF_SUCCESS;
4781	}
4782
4783
4784	/*
4785	* Signal the semaphore to make sure we don't wait for 250ms after a
4786	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4787	*/
4788	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4789
4790	/*
4791	* Allocate a bounce buffer for command we get from the FIFO.
4792	* (All code must return via the end of the function to free this buffer.)
4793	*/
4794	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4795	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4796
4797	/*
4798	* Polling/sleep interval config.
4799	*
4800	* We wait for an a short interval if the guest has recently given us work
4801	* to do, but the interval increases the longer we're kept idle. Once we've
4802	* reached the refresh timer interval, we'll switch to extended waits,
4803	* depending on it or the guest to kick us into action when needed.
4804	*
4805	* Should the refresh time go fishing, we'll just continue increasing the
4806	* sleep length till we reaches the 250 ms max after about 16 seconds.
4807	*/
4808	RTMSINTERVAL const cMsMinSleep = 16;
4809	RTMSINTERVAL const cMsIncSleep = 2;
4810	RTMSINTERVAL const cMsMaxSleep = 250;
4811	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4812	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4813
4814	/*
4815	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4816	*
4817	* Initialize with values that will detect an update from the guest.
4818	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4819	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4820	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4821	*/
4822	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4823	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4824	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4825	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4826	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4827
4828	/*
4829	* The FIFO loop.
4830	*/
4831	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4832	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4833	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4834	{
4835	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4836	/*
4837	* Should service the run loop every so often.
4838	*/
4839	if (pThis->svga.f3DEnabled)
4840	vmsvga3dCocoaServiceRunLoop();
4841	# endif
4842
4843	/* First check any pending actions. */
4844	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4845
4846	/*
4847	* Unless there's already work pending, go to sleep for a short while.
4848	* (See polling/sleep interval config above.)
4849	*/
4850	if ( fBadOrDisabledFifo
4851	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4852	{
4853	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4854	Assert(pThis->cMilliesRefreshInterval > 0);
4855	if (cMsSleep < pThis->cMilliesRefreshInterval)
4856	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4857	else
4858	{
4859	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4860	int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4861	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4862	# endif
4863	if ( !fBadOrDisabledFifo
4864	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4865	rc = VINF_SUCCESS;
4866	else
4867	{
4868	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4869	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4870	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4871	}
4872	}
4873	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4874	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4875	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4876	{
4877	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4878	break;
4879	}
4880	}
4881	else
4882	rc = VINF_SUCCESS;
4883	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4884	if (rc == VERR_TIMEOUT)
4885	{
4886	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4887	{
4888	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4889	continue;
4890	}
4891	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4892
4893	Log(("vmsvgaR3FifoLoop: timeout\n"));
4894	}
4895	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4896	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4897	cMsSleep = cMsMinSleep;
4898
4899	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4900	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4901	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4902
4903	/*
4904	* Handle external commands (currently only reset).
4905	*/
4906	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4907	{
4908	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4909	continue;
4910	}
4911
4912	/*
4913	* If guest misbehaves, then do nothing.
4914	*/
4915	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4916	{
4917	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4918	cMsSleep = cMsExtendedSleep;
4919	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4920	continue;
4921	}
4922
4923	/*
4924	* The device must be enabled and configured.
4925	*/
4926	if ( !pThis->svga.fEnabled
4927	\|\| !pThis->svga.fConfigured)
4928	{
4929	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4930	fBadOrDisabledFifo = true;
4931	cMsSleep = cMsMaxSleep; /* cheat */
4932	continue;
4933	}
4934
4935	/*
4936	* Get and check the min/max values. We ASSUME that they will remain
4937	* unchanged while we process requests. A further ASSUMPTION is that
4938	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4939	* we don't read it back while in the loop.
4940	*/
4941	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4942	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4943	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4944	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4945	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4946	\|\| offFifoMax <= offFifoMin
4947	\|\| offFifoMax > pThis->svga.cbFIFO
4948	\|\| (offFifoMax & 3) != 0
4949	\|\| (offFifoMin & 3) != 0
4950	\|\| offCurrentCmd < offFifoMin
4951	\|\| offCurrentCmd > offFifoMax))
4952	{
4953	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4954	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4955	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4956	fBadOrDisabledFifo = true;
4957	continue;
4958	}
4959	RT_UNTRUSTED_VALIDATED_FENCE();
4960	if (RT_UNLIKELY(offCurrentCmd & 3))
4961	{
4962	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4963	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n",<