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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 100757

Last change on this file since 100757 was 100757, checked in by vboxsync, 10 months ago
Devices/Graphics/DevVGA-SVGA: Fix for saved state loading, bugref:10458
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 322.8 KB

Line
1	/* $Id: DevVGA-SVGA.cpp 100757 2023-07-31 14:32:09Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - Log6 for DX shaders.
13	* - Log7 for SVGA command dump.
14	* - Log8 for content of constant and vertex buffers.
15	* - LogRel for the usual important stuff.
16	* - LogRel2 for cursor.
17	* - LogRel3 for 3D performance data.
18	* - LogRel4 for HW accelerated graphics output.
19	*/
20
21	/*
22	* Copyright (C) 2013-2023 Oracle and/or its affiliates.
23	*
24	* This file is part of VirtualBox base platform packages, as
25	* available from https://www.virtualbox.org.
26	*
27	* This program is free software; you can redistribute it and/or
28	* modify it under the terms of the GNU General Public License
29	* as published by the Free Software Foundation, in version 3 of the
30	* License.
31	*
32	* This program is distributed in the hope that it will be useful, but
33	* WITHOUT ANY WARRANTY; without even the implied warranty of
34	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35	* General Public License for more details.
36	*
37	* You should have received a copy of the GNU General Public License
38	* along with this program; if not, see <https://www.gnu.org/licenses>.
39	*
40	* SPDX-License-Identifier: GPL-3.0-only
41	*/
42
43
44	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
45	*
46	* This device emulation was contributed by trivirt AG. It offers an
47	* alternative to our Bochs based VGA graphics and 3d emulations. This is
48	* valuable for Xorg based guests, as there is driver support shipping with Xorg
49	* since it forked from XFree86.
50	*
51	*
52	* @section sec_dev_vmsvga_sdk The VMware SDK
53	*
54	* This is officially deprecated now, however it's still quite useful,
55	* especially for getting the old features working:
56	* http://vmware-svga.sourceforge.net/
57	*
58	* They currently point developers at the following resources.
59	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
60	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
61	* - http://cgit.freedesktop.org/mesa/vmwgfx/
62	*
63	* @subsection subsec_dev_vmsvga_sdk_results Test results
64	*
65	* Test results:
66	* - 2dmark.img:
67	* + todo
68	* - backdoor-tclo.img:
69	* + todo
70	* - blit-cube.img:
71	* + todo
72	* - bunnies.img:
73	* + todo
74	* - cube.img:
75	* + todo
76	* - cubemark.img:
77	* + todo
78	* - dynamic-vertex-stress.img:
79	* + todo
80	* - dynamic-vertex.img:
81	* + todo
82	* - fence-stress.img:
83	* + todo
84	* - gmr-test.img:
85	* + todo
86	* - half-float-test.img:
87	* + todo
88	* - noscreen-cursor.img:
89	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
90	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
91	* visible though.)
92	* - Cursor animation via the palette doesn't work.
93	* - During debugging, it turns out that the framebuffer content seems to
94	* be halfways ignore or something (memset(fb, 0xcc, lots)).
95	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
96	* grow it 0x10 fold (128KB -> 2MB like in WS10).
97	* - null.img:
98	* + todo
99	* - pong.img:
100	* + todo
101	* - presentReadback.img:
102	* + todo
103	* - resolution-set.img:
104	* + todo
105	* - rt-gamma-test.img:
106	* + todo
107	* - screen-annotation.img:
108	* + todo
109	* - screen-cursor.img:
110	* + todo
111	* - screen-dma-coalesce.img:
112	* + todo
113	* - screen-gmr-discontig.img:
114	* + todo
115	* - screen-gmr-remap.img:
116	* + todo
117	* - screen-multimon.img:
118	* + todo
119	* - screen-present-clip.img:
120	* + todo
121	* - screen-render-test.img:
122	* + todo
123	* - screen-simple.img:
124	* + todo
125	* - screen-text.img:
126	* + todo
127	* - simple-shaders.img:
128	* + todo
129	* - simple_blit.img:
130	* + todo
131	* - tiny-2d-updates.img:
132	* + todo
133	* - video-formats.img:
134	* + todo
135	* - video-sync.img:
136	* + todo
137	*
138	*/
139
140
141	/*********************************************************************************************************************************
142	* Header Files *
143	*********************************************************************************************************************************/
144	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
145	#include <VBox/vmm/pdmdev.h>
146	#include <VBox/version.h>
147	#include <VBox/err.h>
148	#include <VBox/log.h>
149	#include <VBox/vmm/pgm.h>
150	#include <VBox/sup.h>
151
152	#include <iprt/assert.h>
153	#include <iprt/semaphore.h>
154	#include <iprt/uuid.h>
155	#ifdef IN_RING3
156	# include <iprt/ctype.h>
157	# include <iprt/mem.h>
158	# ifdef VBOX_STRICT
159	# include <iprt/time.h>
160	# endif
161	#endif
162
163	#include <VBox/AssertGuest.h>
164	#include <VBox/VMMDev.h>
165	#include <VBoxVideo.h>
166	#include <VBox/bioslogo.h>
167
168	#ifdef LOG_ENABLED
169	#include "svgadump/svga_dump.h"
170	#endif
171
172	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
173	#include "DevVGA.h"
174
175	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
176	#ifdef VBOX_WITH_VMSVGA3D
177	# include "DevVGA-SVGA3d.h"
178	# ifdef RT_OS_DARWIN
179	# include "DevVGA-SVGA3d-cocoa.h"
180	# endif
181	# ifdef RT_OS_LINUX
182	# ifdef IN_RING3
183	# include "DevVGA-SVGA3d-glLdr.h"
184	# endif
185	# endif
186	#endif
187	#ifdef IN_RING3
188	#include "DevVGA-SVGA-internal.h"
189	#endif
190
191
192	/*********************************************************************************************************************************
193	* Defined Constants And Macros *
194	*********************************************************************************************************************************/
195	/**
196	* Macro for checking if a fixed FIFO register is valid according to the
197	* current FIFO configuration.
198	*
199	* @returns true / false.
200	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
201	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
202	*/
203	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
204
205
206	/*********************************************************************************************************************************
207	* Structures and Typedefs *
208	*********************************************************************************************************************************/
209
210
211	/*********************************************************************************************************************************
212	* Internal Functions *
213	*********************************************************************************************************************************/
214	#ifdef IN_RING3
215	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
216	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
217	# endif
218	# ifdef DEBUG_GMR_ACCESS
219	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
220	# endif
221	#endif
222
223
224	/*********************************************************************************************************************************
225	* Global Variables *
226	*********************************************************************************************************************************/
227	#ifdef IN_RING3
228
229	/**
230	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
231	*/
232	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
233	{
234	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
235	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
236	SSMFIELD_ENTRY_TERM()
237	};
238
239	/**
240	* SSM descriptor table for the GMR structure.
241	*/
242	static SSMFIELD const g_aGMRFields[] =
243	{
244	SSMFIELD_ENTRY( GMR, cMaxPages),
245	SSMFIELD_ENTRY( GMR, cbTotal),
246	SSMFIELD_ENTRY( GMR, numDescriptors),
247	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
248	SSMFIELD_ENTRY_TERM()
249	};
250
251	/**
252	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
253	*/
254	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
255	{
256	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
257	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
258	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
259	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
260	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
261	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
262	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
263	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
264	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
265	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
266	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
267	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
268	SSMFIELD_ENTRY_TERM()
269	};
270
271	/**
272	* SSM descriptor table for the VMSVGAR3STATE structure.
273	*/
274	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
275	{
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
277	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
278	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
279	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
280	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
281	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
282	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
283	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
284	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
285	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
287	#ifdef VMSVGA_USE_EMT_HALT_CODE
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
289	#else
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
291	#endif
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
338	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
343	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
351	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
353	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
355
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
358	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
359	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
360
361	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
362	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
363	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
364	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
365	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
366	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
367	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
368	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
369	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
370	# endif
371	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
372	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
373	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
374	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
375
376	SSMFIELD_ENTRY_TERM()
377	};
378
379	/**
380	* SSM descriptor table for the VGAState.svga structure.
381	*/
382	static SSMFIELD const g_aVGAStateSVGAFields[] =
383	{
384	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
387	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
388	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
389	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
390	SSMFIELD_ENTRY( VMSVGAState, fBusy),
391	SSMFIELD_ENTRY( VMSVGAState, fTraces),
392	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
393	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
394	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
395	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
396	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
397	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
398	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
399	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
400	SSMFIELD_ENTRY_VER( VMSVGAState, u32DeviceCaps2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
401	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverId, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
402	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer1, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
403	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
404	SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer3, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
405	SSMFIELD_ENTRY_VER( VMSVGAState, u32FenceLast, VGA_SAVEDSTATE_VERSION_VMSVGA_SVGA3),
406	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
408	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
409	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
410	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
411	SSMFIELD_ENTRY( VMSVGAState, uWidth),
412	SSMFIELD_ENTRY( VMSVGAState, uHeight),
413	SSMFIELD_ENTRY( VMSVGAState, uBpp),
414	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
415	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
416	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
417	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
418	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
419	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
420	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
421	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
422	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
423	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
424	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
428	SSMFIELD_ENTRY_VER( VMSVGAState, au32DevCaps, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
429	SSMFIELD_ENTRY_VER( VMSVGAState, u32DevCapIndex, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
430	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandLow, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
431	SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandHigh, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
432
433	SSMFIELD_ENTRY_TERM()
434	};
435	#endif /* IN_RING3 */
436
437
438	/*********************************************************************************************************************************
439	* Internal Functions *
440	*********************************************************************************************************************************/
441	#ifdef IN_RING3
442	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
443	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
444	uint32_t uVersion, uint32_t uPass);
445	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
446	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
447	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState);
448	#endif /* IN_RING3 */
449
450
451	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
452	#if defined(LOG_ENABLED)
453	/**
454	* Index register string name lookup
455	*
456	* @returns Index register string or "UNKNOWN"
457	* @param pThis The shared VGA/VMSVGA state.
458	* @param idxReg The index register.
459	*/
460	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
461	{
462	AssertCompile(SVGA_REG_TOP == 84); /* Ensure that the correct headers are used. */
463	switch (idxReg)
464	{
465	SVGA_CASE_ID2STR(SVGA_REG_ID);
466	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
467	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
468	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
469	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
470	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
471	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
472	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
473	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
474	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
475	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
476	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
477	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
478	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
479	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
480	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
481	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
482
483	/* ID 0 implementation only had the above registers, then the palette */
484	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
485	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
486	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
487	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
488	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
489	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
490	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
491	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
492	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
493	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
494	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
495	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
496	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
497	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
498	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
499	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
500	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
501
502	/* Legacy multi-monitor support */
503	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
504	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
505	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
506	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
507	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
508	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
509	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
510
511	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
512	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
513	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
514	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
515
516	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
517	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
518	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
519	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
520	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
521	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
522	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
523	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
524	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
525	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
526	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
527	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
528	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
529	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
530	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
531	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
532	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
533	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
534	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
535	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
536	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
537	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
538	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
539	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
540	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
541	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
542	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
543	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
544	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
545	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
546	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
547	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
548	SVGA_CASE_ID2STR(SVGA_REG_REGS_START_HIGH32);
549	SVGA_CASE_ID2STR(SVGA_REG_REGS_START_LOW32);
550	SVGA_CASE_ID2STR(SVGA_REG_FB_START_HIGH32);
551	SVGA_CASE_ID2STR(SVGA_REG_FB_START_LOW32);
552	SVGA_CASE_ID2STR(SVGA_REG_MSHINT);
553	SVGA_CASE_ID2STR(SVGA_REG_IRQ_STATUS);
554	SVGA_CASE_ID2STR(SVGA_REG_DIRTY_TRACKING);
555	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
556
557	default:
558	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
559	return "SVGA_SCRATCH_BASE reg";
560	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
561	return "SVGA_PALETTE_BASE reg";
562	return "UNKNOWN";
563	}
564	}
565	#endif /* LOG_ENABLED */
566
567	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
568	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
569	{
570	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
571	switch (idxDevCap)
572	{
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
798	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
800	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
801	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
802	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
803	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
804	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
805	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
806	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
807	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
808	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
809	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
810	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
811	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
812	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
813	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
814	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
815	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
816	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
817	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
818	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
819	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
820	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
821	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
822	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
823	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
824	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
825	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
826	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
827	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
828	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
829	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
830	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
831	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
832	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
833	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
834
835	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
836
837	default:
838	break;
839	}
840	return "UNKNOWN";
841	}
842	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
843	#undef SVGA_CASE_ID2STR
844
845
846	#ifdef IN_RING3
847
848	/**
849	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
850	*/
851	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
852	{
853	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
854	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
855
856	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
857	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
858
859	/** @todo Test how it interacts with multiple screen objects. */
860	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
861	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
862	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
863
864	if (x < uWidth)
865	{
866	pThis->svga.viewport.x = x;
867	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
868	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
869	}
870	else
871	{
872	pThis->svga.viewport.x = uWidth;
873	pThis->svga.viewport.cx = 0;
874	pThis->svga.viewport.xRight = uWidth;
875	}
876	if (y < uHeight)
877	{
878	pThis->svga.viewport.y = y;
879	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
880	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
881	pThis->svga.viewport.yHighWC = uHeight - y;
882	}
883	else
884	{
885	pThis->svga.viewport.y = uHeight;
886	pThis->svga.viewport.cy = 0;
887	pThis->svga.viewport.yLowWC = 0;
888	pThis->svga.viewport.yHighWC = 0;
889	}
890
891	# ifdef VBOX_WITH_VMSVGA3D
892	/*
893	* Now inform the 3D backend.
894	*/
895	if (pThis->svga.f3DEnabled)
896	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
897	# else
898	RT_NOREF(OldViewport);
899	# endif
900	}
901
902
903	/**
904	* Updating screen information in API
905	*
906	* @param pThis The The shared VGA/VMSVGA instance data.
907	* @param pThisCC The VGA/VMSVGA state for ring-3.
908	*/
909	static void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
910	{
911	int rc;
912
913	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
914
915	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
916	{
917	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
918	if (!pScreen->fModified)
919	continue;
920
921	pScreen->fModified = false;
922
923	VBVAINFOVIEW view;
924	RT_ZERO(view);
925	view.u32ViewIndex = pScreen->idScreen;
926	// view.u32ViewOffset = 0;
927	view.u32ViewSize = pThis->vram_size;
928	view.u32MaxScreenSize = pThis->vram_size;
929
930	VBVAINFOSCREEN screen;
931	RT_ZERO(screen);
932	screen.u32ViewIndex = pScreen->idScreen;
933
934	if (pScreen->fDefined)
935	{
936	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
937	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
938	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
939	{
940	Assert(pThis->svga.fGFBRegisters);
941	continue;
942	}
943
944	screen.i32OriginX = pScreen->xOrigin;
945	screen.i32OriginY = pScreen->yOrigin;
946	screen.u32StartOffset = pScreen->offVRAM;
947	screen.u32LineSize = pScreen->cbPitch;
948	screen.u32Width = pScreen->cWidth;
949	screen.u32Height = pScreen->cHeight;
950	screen.u16BitsPerPixel = pScreen->cBpp;
951	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
952	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
953	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
954	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
955	}
956	else
957	{
958	/* Screen is destroyed. */
959	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
960	}
961
962	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
963	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
964	AssertRC(rc);
965	}
966	}
967
968
969	/**
970	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
971	*
972	* Used to update screen offsets (positions) since appearently vmwgfx fails to
973	* pass correct offsets thru FIFO.
974	*/
975	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
976	{
977	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
978	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
979	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
980
981	AssertReturnVoid(pSVGAState);
982
983	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
984	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
985	for (uint32_t i = 0; i < cPositions; ++i)
986	{
987	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
988	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
989	continue;
990
991	if (paPositions[i].x == -1)
992	continue;
993	if (paPositions[i].y == -1)
994	continue;
995
996	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
997	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
998	pSVGAState->aScreens[i].fModified = true;
999	}
1000
1001	vmsvgaR3VBVAResize(pThis, pThisCC);
1002	}
1003
1004	#endif /* IN_RING3 */
1005
1006	/**
1007	* Read port register
1008	*
1009	* @returns VBox status code.
1010	* @param pDevIns The device instance.
1011	* @param pThis The shared VGA/VMSVGA state.
1012	* @param idxReg The register index being read.
1013	* @param pu32 Where to store the read value
1014	*/
1015	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t idxReg, uint32_t *pu32)
1016	{
1017	#ifdef IN_RING3
1018	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1019	#endif
1020	int rc = VINF_SUCCESS;
1021	*pu32 = 0;
1022
1023	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1024	if ( idxReg >= SVGA_REG_ID_0_TOP
1025	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1026	{
1027	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1028	Log(("vmsvgaReadPort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1029	}
1030
1031	switch (idxReg)
1032	{
1033	case SVGA_REG_ID:
1034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1035	*pu32 = pThis->svga.u32SVGAId;
1036	break;
1037
1038	case SVGA_REG_ENABLE:
1039	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1040	*pu32 = pThis->svga.fEnabled;
1041	break;
1042
1043	case SVGA_REG_WIDTH:
1044	{
1045	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1046	if ( pThis->svga.fEnabled
1047	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1048	*pu32 = pThis->svga.uWidth;
1049	else
1050	{
1051	#ifndef IN_RING3
1052	rc = VINF_IOM_R3_IOPORT_READ;
1053	#else
1054	*pu32 = pThisCC->pDrv->cx;
1055	#endif
1056	}
1057	break;
1058	}
1059
1060	case SVGA_REG_HEIGHT:
1061	{
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1063	if ( pThis->svga.fEnabled
1064	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1065	*pu32 = pThis->svga.uHeight;
1066	else
1067	{
1068	#ifndef IN_RING3
1069	rc = VINF_IOM_R3_IOPORT_READ;
1070	#else
1071	*pu32 = pThisCC->pDrv->cy;
1072	#endif
1073	}
1074	break;
1075	}
1076
1077	case SVGA_REG_MAX_WIDTH:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1079	*pu32 = pThis->svga.u32MaxWidth;
1080	break;
1081
1082	case SVGA_REG_MAX_HEIGHT:
1083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1084	*pu32 = pThis->svga.u32MaxHeight;
1085	break;
1086
1087	case SVGA_REG_DEPTH:
1088	/* This returns the color depth of the current mode. */
1089	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1090	switch (pThis->svga.uBpp)
1091	{
1092	case 15:
1093	case 16:
1094	case 24:
1095	*pu32 = pThis->svga.uBpp;
1096	break;
1097
1098	default:
1099	case 32:
1100	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1101	break;
1102	}
1103	break;
1104
1105	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1106	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1107	*pu32 = pThis->svga.uHostBpp;
1108	break;
1109
1110	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1111	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1112	*pu32 = pThis->svga.uBpp;
1113	break;
1114
1115	case SVGA_REG_PSEUDOCOLOR:
1116	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1117	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1118	break;
1119
1120	case SVGA_REG_RED_MASK:
1121	case SVGA_REG_GREEN_MASK:
1122	case SVGA_REG_BLUE_MASK:
1123	{
1124	uint32_t uBpp;
1125
1126	if (pThis->svga.fEnabled)
1127	uBpp = pThis->svga.uBpp;
1128	else
1129	uBpp = pThis->svga.uHostBpp;
1130
1131	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1132	switch (uBpp)
1133	{
1134	case 8:
1135	u32RedMask = 0x07;
1136	u32GreenMask = 0x38;
1137	u32BlueMask = 0xc0;
1138	break;
1139
1140	case 15:
1141	u32RedMask = 0x0000001f;
1142	u32GreenMask = 0x000003e0;
1143	u32BlueMask = 0x00007c00;
1144	break;
1145
1146	case 16:
1147	u32RedMask = 0x0000001f;
1148	u32GreenMask = 0x000007e0;
1149	u32BlueMask = 0x0000f800;
1150	break;
1151
1152	case 24:
1153	case 32:
1154	default:
1155	u32RedMask = 0x00ff0000;
1156	u32GreenMask = 0x0000ff00;
1157	u32BlueMask = 0x000000ff;
1158	break;
1159	}
1160	switch (idxReg)
1161	{
1162	case SVGA_REG_RED_MASK:
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1164	*pu32 = u32RedMask;
1165	break;
1166
1167	case SVGA_REG_GREEN_MASK:
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1169	*pu32 = u32GreenMask;
1170	break;
1171
1172	case SVGA_REG_BLUE_MASK:
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1174	*pu32 = u32BlueMask;
1175	break;
1176	}
1177	break;
1178	}
1179
1180	case SVGA_REG_BYTES_PER_LINE:
1181	{
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1183	if ( pThis->svga.fEnabled
1184	&& pThis->svga.cbScanline)
1185	*pu32 = pThis->svga.cbScanline;
1186	else
1187	{
1188	#ifndef IN_RING3
1189	rc = VINF_IOM_R3_IOPORT_READ;
1190	#else
1191	*pu32 = pThisCC->pDrv->cbScanline;
1192	#endif
1193	}
1194	break;
1195	}
1196
1197	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1198	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1199	*pu32 = pThis->vram_size;
1200	break;
1201
1202	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1203	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1204	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1205	*pu32 = pThis->GCPhysVRAM;
1206	break;
1207
1208	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1209	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1210	/* Always zero in our case. */
1211	*pu32 = 0;
1212	break;
1213
1214	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1215	{
1216	#ifndef IN_RING3
1217	rc = VINF_IOM_R3_IOPORT_READ;
1218	#else
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1220
1221	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1222	if ( pThis->svga.fEnabled
1223	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1224	{
1225	/* Hardware enabled; return real framebuffer size .*/
1226	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1227	}
1228	else
1229	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1230
1231	pu32 = RT_MIN(pThis->vram_size, pu32);
1232	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1233	#endif
1234	break;
1235	}
1236
1237	case SVGA_REG_CAPABILITIES:
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1239	*pu32 = pThis->svga.u32DeviceCaps;
1240	break;
1241
1242	case SVGA_REG_MEM_START: /* FIFO start */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1244	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1245	*pu32 = pThis->svga.GCPhysFIFO;
1246	break;
1247
1248	case SVGA_REG_MEM_SIZE: /* FIFO size */
1249	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1250	*pu32 = pThis->svga.cbFIFO;
1251	break;
1252
1253	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1255	*pu32 = pThis->svga.fConfigured;
1256	break;
1257
1258	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1260	*pu32 = 0;
1261	break;
1262
1263	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1264	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1265	if (pThis->svga.fBusy)
1266	{
1267	#ifndef IN_RING3
1268	/* Go to ring-3 and halt the CPU. */
1269	rc = VINF_IOM_R3_IOPORT_READ;
1270	RT_NOREF(pDevIns);
1271	break;
1272	#else /* IN_RING3 */
1273	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1274	/* The guest is basically doing a HLT via the device here, but with
1275	a special wake up condition on FIFO completion. */
1276	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1277	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1278	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1279	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1280	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1281	if (pThis->svga.fBusy)
1282	{
1283	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1284	rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1285	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1286	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1287	}
1288	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1289	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1290	# else
1291
1292	/* Delay the EMT a bit so the FIFO and others can get some work done.
1293	This used to be a crude 50 ms sleep. The current code tries to be
1294	more efficient, but the consept is still very crude. */
1295	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1296	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1297	RTThreadYield();
1298	if (pThis->svga.fBusy)
1299	{
1300	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1301
1302	if (pThis->svga.fBusy && cRefs == 1)
1303	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1304	if (pThis->svga.fBusy)
1305	{
1306	/** @todo If this code is going to stay, we need to call into the halt/wait
1307	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1308	* suffer when the guest is polling on a busy FIFO. */
1309	uint64_t uIgnored1, uIgnored2;
1310	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1311	if (cNsMaxWait >= RT_NS_100US)
1312	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1313	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1314	RT_MIN(cNsMaxWait, RT_NS_10MS));
1315	}
1316
1317	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1318	}
1319	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1320	# endif
1321	*pu32 = pThis->svga.fBusy != 0;
1322	#endif /* IN_RING3 */
1323	}
1324	else
1325	*pu32 = false;
1326	break;
1327
1328	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1329	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1330	*pu32 = pThis->svga.u32GuestId;
1331	break;
1332
1333	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1335	*pu32 = pThis->svga.cScratchRegion;
1336	break;
1337
1338	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1339	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1340	*pu32 = SVGA_FIFO_NUM_REGS;
1341	break;
1342
1343	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1344	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1345	*pu32 = pThis->svga.u32PitchLock;
1346	break;
1347
1348	case SVGA_REG_IRQMASK: /* Interrupt mask */
1349	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1350	*pu32 = pThis->svga.u32IrqMask;
1351	break;
1352
1353	/* See "Guest memory regions" below. */
1354	case SVGA_REG_GMR_ID:
1355	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1356	*pu32 = pThis->svga.u32CurrentGMRId;
1357	break;
1358
1359	case SVGA_REG_GMR_DESCRIPTOR:
1360	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1361	/* Write only */
1362	*pu32 = 0;
1363	break;
1364
1365	case SVGA_REG_GMR_MAX_IDS:
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1367	*pu32 = pThis->svga.cGMR;
1368	break;
1369
1370	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1372	*pu32 = VMSVGA_MAX_GMR_PAGES;
1373	break;
1374
1375	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1376	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1377	*pu32 = pThis->svga.fTraces;
1378	break;
1379
1380	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1381	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1382	*pu32 = VMSVGA_MAX_GMR_PAGES;
1383	break;
1384
1385	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1386	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1387	*pu32 = VMSVGA_SURFACE_SIZE;
1388	break;
1389
1390	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1391	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1392	break;
1393
1394	/* Mouse cursor support. */
1395	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1396	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1397	*pu32 = pThis->svga.uCursorID;
1398	break;
1399
1400	case SVGA_REG_CURSOR_X:
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1402	*pu32 = pThis->svga.uCursorX;
1403	break;
1404
1405	case SVGA_REG_CURSOR_Y:
1406	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1407	*pu32 = pThis->svga.uCursorY;
1408	break;
1409
1410	case SVGA_REG_CURSOR_ON:
1411	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1412	*pu32 = pThis->svga.uCursorOn;
1413	break;
1414
1415	/* Legacy multi-monitor support */
1416	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1417	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1418	*pu32 = 1;
1419	break;
1420
1421	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1422	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1423	*pu32 = 0;
1424	break;
1425
1426	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1427	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1428	*pu32 = 0;
1429	break;
1430
1431	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1432	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1433	*pu32 = 0;
1434	break;
1435
1436	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1437	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1438	*pu32 = 0;
1439	break;
1440
1441	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1442	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1443	*pu32 = pThis->svga.uWidth;
1444	break;
1445
1446	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1447	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1448	*pu32 = pThis->svga.uHeight;
1449	break;
1450
1451	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1452	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1453	/* We must return something sensible here otherwise the Linux driver
1454	will take a legacy code path without 3d support. This number also
1455	limits how many screens Linux guests will allow. */
1456	*pu32 = pThis->cMonitors;
1457	break;
1458
1459	/*
1460	* SVGA_CAP_GBOBJECTS+ registers.
1461	*/
1462	case SVGA_REG_COMMAND_LOW:
1463	/* Lower 32 bits of command buffer physical address. */
1464	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1465	*pu32 = pThis->svga.u32RegCommandLow;
1466	break;
1467
1468	case SVGA_REG_COMMAND_HIGH:
1469	/* Upper 32 bits of command buffer PA. */
1470	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1471	*pu32 = pThis->svga.u32RegCommandHigh;
1472	break;
1473
1474	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1475	/* Max primary (screen) memory. */
1476	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1477	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1478	break;
1479
1480	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1481	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1482	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1483	*pu32 = pThis->vram_size / 1024;
1484	break;
1485
1486	case SVGA_REG_DEV_CAP:
1487	/* Write dev cap index, read value */
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1489	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1490	{
1491	RT_UNTRUSTED_VALIDATED_FENCE();
1492	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1493	}
1494	else
1495	*pu32 = 0;
1496	break;
1497
1498	case SVGA_REG_CMD_PREPEND_LOW:
1499	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1500	pu32 = 0; / Not supported. */
1501	break;
1502
1503	case SVGA_REG_CMD_PREPEND_HIGH:
1504	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1505	pu32 = 0; / Not supported. */
1506	break;
1507
1508	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1509	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1510	*pu32 = pThis->svga.u32MaxWidth;
1511	break;
1512
1513	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1514	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1515	*pu32 = pThis->svga.u32MaxHeight;
1516	break;
1517
1518	case SVGA_REG_MOB_MAX_SIZE:
1519	/* Essentially the max texture size */
1520	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1521	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1522	break;
1523
1524	case SVGA_REG_BLANK_SCREEN_TARGETS:
1525	/// @todo STAM_REL_COUNTER_INC(&pThis->svga.aStatRegRd[idxReg]);
1526	pu32 = 0; / Not supported. */
1527	break;
1528
1529	case SVGA_REG_CAP2:
1530	*pu32 = pThis->svga.u32DeviceCaps2;
1531	break;
1532
1533	case SVGA_REG_DEVEL_CAP:
1534	pu32 = 0; / Not supported. */
1535	break;
1536
1537	/*
1538	* SVGA_REG_GUEST_DRIVER_* registers require SVGA_CAP2_DX2.
1539	*/
1540	case SVGA_REG_GUEST_DRIVER_ID:
1541	*pu32 = pThis->svga.u32GuestDriverId;
1542	break;
1543
1544	case SVGA_REG_GUEST_DRIVER_VERSION1:
1545	*pu32 = pThis->svga.u32GuestDriverVer1;
1546	break;
1547
1548	case SVGA_REG_GUEST_DRIVER_VERSION2:
1549	*pu32 = pThis->svga.u32GuestDriverVer2;
1550	break;
1551
1552	case SVGA_REG_GUEST_DRIVER_VERSION3:
1553	*pu32 = pThis->svga.u32GuestDriverVer3;
1554	break;
1555
1556	/*
1557	* SVGA_REG_CURSOR_ registers require SVGA_CAP2_CURSOR_MOB which the device does not support currently.
1558	*/
1559	case SVGA_REG_CURSOR_MOBID:
1560	*pu32 = SVGA_ID_INVALID;
1561	break;
1562
1563	case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
1564	*pu32 = 0;
1565	break;
1566
1567	case SVGA_REG_CURSOR_MAX_DIMENSION:
1568	*pu32 = 0;
1569	break;
1570
1571	case SVGA_REG_FIFO_CAPS:
1572	{
1573	if (pThis->fVmSvga3)
1574	*pu32 = SVGA_FIFO_CAP_FENCE
1575	\| SVGA_FIFO_CAP_PITCHLOCK
1576	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
1577	\| SVGA_FIFO_CAP_RESERVE
1578	\| SVGA_FIFO_CAP_GMR2
1579	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
1580	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
1581	else
1582	*pu32 = 0;
1583	break;
1584	}
1585	case SVGA_REG_FENCE:
1586	{
1587	if (pThis->fVmSvga3)
1588	*pu32 = pThis->svga.u32FenceLast;
1589	else
1590	*pu32 = 0;
1591	break;
1592	}
1593
1594	case SVGA_REG_RESERVED1: /* SVGA_REG_RESERVED* correspond to SVGA_REG_CURSOR4_. Require SVGA_CAP2_EXTRA_REGS. /
1595	case SVGA_REG_RESERVED2:
1596	case SVGA_REG_RESERVED3:
1597	case SVGA_REG_RESERVED4:
1598	case SVGA_REG_RESERVED5:
1599	case SVGA_REG_SCREENDMA:
1600	pu32 = 0; / Not supported. */
1601	break;
1602
1603	case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
1604	/** @todo "The maximum amount of guest-backed objects that the device can have resident at a time" */
1605	*pu32 = _1G / _1K;
1606	break;
1607
1608	case SVGA_REG_IRQ_STATUS:
1609	{
1610	if (pThis->fVmSvga3)
1611	*pu32 = pThis->svga.u32IrqStatus;
1612	else
1613	*pu32 = 0;
1614	break;
1615	}
1616
1617	default:
1618	{
1619	uint32_t offReg;
1620	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1621	{
1622	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1623	RT_UNTRUSTED_VALIDATED_FENCE();
1624	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1625	}
1626	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1627	{
1628	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1629	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1630	RT_UNTRUSTED_VALIDATED_FENCE();
1631	uint32_t u32 = pThis->last_palette[offReg / 3];
1632	switch (offReg % 3)
1633	{
1634	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1635	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1636	case 2: pu32 = u32 & 0xff; break; / blue */
1637	}
1638	}
1639	else
1640	{
1641	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1642	rc = VINF_IOM_R3_IOPORT_READ;
1643	#else
1644	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1645
1646	/* Do not assert. The guest might be reading all registers. */
1647	LogFunc(("Unknown reg=%#x\n", idxReg));
1648	#endif
1649	}
1650	break;
1651	}
1652	}
1653	LogFlow(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1654	return rc;
1655	}
1656
1657	#ifdef IN_RING3
1658	/**
1659	* Apply the current resolution settings to change the video mode.
1660	*
1661	* @returns VBox status code.
1662	* @param pThis The shared VGA state.
1663	* @param pThisCC The ring-3 VGA state.
1664	*/
1665	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1666	{
1667	/* Always do changemode on FIFO thread. */
1668	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1669
1670	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1671
1672	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1673
1674	if (pThis->svga.fGFBRegisters)
1675	{
1676	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1677	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1678	* deletes all screens other than screen #0, and redefines screen
1679	* #0 according to the specified mode. Drivers that use
1680	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1681	*/
1682
1683	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1684	Assert(pScreen->idScreen == 0);
1685	pScreen->fDefined = true;
1686	pScreen->fModified = true;
1687	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1688	pScreen->xOrigin = 0;
1689	pScreen->yOrigin = 0;
1690	pScreen->offVRAM = 0;
1691	pScreen->cbPitch = pThis->svga.cbScanline;
1692	pScreen->cWidth = pThis->svga.uWidth;
1693	pScreen->cHeight = pThis->svga.uHeight;
1694	pScreen->cBpp = pThis->svga.uBpp;
1695
1696	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1697	{
1698	/* Delete screen. */
1699	pScreen = &pSVGAState->aScreens[iScreen];
1700	if (pScreen->fDefined)
1701	{
1702	pScreen->fModified = true;
1703	pScreen->fDefined = false;
1704	}
1705	}
1706	}
1707	else
1708	{
1709	/* "If Screen Objects are supported, they can be used to fully
1710	* replace the functionality provided by the framebuffer registers
1711	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1712	*/
1713	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1714	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1715	pThis->svga.uBpp = pThis->svga.uHostBpp;
1716	}
1717
1718	vmsvgaR3VBVAResize(pThis, pThisCC);
1719
1720	/* Last stuff. For the VGA device screenshot. */
1721	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1722	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1723	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1724	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1725	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1726
1727	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1728	if ( pThis->svga.viewport.cx == 0
1729	&& pThis->svga.viewport.cy == 0)
1730	{
1731	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1732	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1733	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1734	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1735	pThis->svga.viewport.yLowWC = 0;
1736	}
1737
1738	return VINF_SUCCESS;
1739	}
1740
1741	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1742	{
1743	ASSERT_GUEST_LOGREL_MSG_RETURN(w > 0 && h > 0,
1744	("vmsvgaR3UpdateScreen: screen %d (%d,%d) %dx%d: Invalid height and/or width supplied.\n",
1745	pScreen->idScreen, x, y, w, h),
1746	VERR_INVALID_PARAMETER);
1747
1748	VBVACMDHDR cmd;
1749	cmd.x = (int16_t)(pScreen->xOrigin + x);
1750	cmd.y = (int16_t)(pScreen->yOrigin + y);
1751	cmd.w = (uint16_t)w;
1752	cmd.h = (uint16_t)h;
1753
1754	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1755	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1756	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1757	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762	#endif /* IN_RING3 */
1763	#if defined(IN_RING0) \|\| defined(IN_RING3)
1764
1765	/**
1766	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1767	*
1768	* @param pThis The shared VGA/VMSVGA instance data.
1769	* @param pThisCC The VGA/VMSVGA state for the current context.
1770	* @param fState The busy state.
1771	*/
1772	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1773	{
1774	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1775
1776	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1777	{
1778	/* Race / unfortunately scheduling. Highly unlikly. */
1779	uint32_t cLoops = 64;
1780	do
1781	{
1782	ASMNopPause();
1783	fState = (pThis->svga.fBusy != 0);
1784	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1785	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1786	}
1787	}
1788
1789
1790	/**
1791	* Update the scanline pitch in response to the guest changing mode
1792	* width/bpp.
1793	*
1794	* @param pThis The shared VGA/VMSVGA state.
1795	* @param pThisCC The VGA/VMSVGA state for the current context.
1796	*/
1797	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1798	{
1799	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1800	uint32_t uFifoPitchLock = pThis->fVmSvga3 ? 0 : pFIFO[SVGA_FIFO_PITCHLOCK];
1801	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1802	uint32_t uFifoMin = pThis->fVmSvga3 ? 0 : pFIFO[SVGA_FIFO_MIN];
1803
1804	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1805	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1806	* location but it has a different meaning.
1807	*/
1808	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1809	uFifoPitchLock = 0;
1810
1811	/* Sanitize values. */
1812	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1813	uFifoPitchLock = 0;
1814	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1815	uRegPitchLock = 0;
1816
1817	/* Prefer the register value to the FIFO value.*/
1818	if (uRegPitchLock)
1819	pThis->svga.cbScanline = uRegPitchLock;
1820	else if (uFifoPitchLock)
1821	pThis->svga.cbScanline = uFifoPitchLock;
1822	else
1823	pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1824
1825	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1826	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1827	}
1828
1829	#endif /* IN_RING0 \|\| IN_RING3 */
1830
1831	#ifdef IN_RING3
1832
1833	/**
1834	* Sends cursor position and visibility information from legacy
1835	* SVGA registers to the front-end.
1836	*/
1837	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1838	{
1839	/*
1840	* Writing the X/Y/ID registers does not trigger changes; only writing the
1841	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1842	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1843	* register if they don't have to.
1844	*/
1845	uint32_t x, y, idScreen;
1846	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1847
1848	x = pThis->svga.uCursorX;
1849	y = pThis->svga.uCursorY;
1850	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1851
1852	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1853	* were extended as follows:
1854	*
1855	* SVGA_CURSOR_ON_HIDE 0
1856	* SVGA_CURSOR_ON_SHOW 1
1857	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1858	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1859	*
1860	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1861	* distinguish between the non-zero values but still remember them.
1862	*/
1863	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1864	{
1865	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1866	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1867	}
1868	pThis->svga.uCursorOn = uCursorOn;
1869	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1870	}
1871
1872	#endif /* IN_RING3 */
1873
1874
1875	/**
1876	* Write port register
1877	*
1878	* @returns Strict VBox status code.
1879	* @param pDevIns The device instance.
1880	* @param pThis The shared VGA/VMSVGA state.
1881	* @param pThisCC The VGA/VMSVGA state for the current context.
1882	* @param idxReg Rge register index being written.
1883	* @param u32 Value to write
1884	*/
1885	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idxReg, uint32_t u32)
1886	{
1887	#ifdef IN_RING3
1888	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1889	#endif
1890	VBOXSTRICTRC rc = VINF_SUCCESS;
1891	RT_NOREF(pThisCC);
1892
1893	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1894	if ( idxReg >= SVGA_REG_ID_0_TOP
1895	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1896	{
1897	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1898	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1899	}
1900	#ifdef LOG_ENABLED
1901	if (idxReg != SVGA_REG_DEV_CAP)
1902	LogFlow(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1903	else
1904	LogFlow(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1905	#endif
1906	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1907	switch (idxReg)
1908	{
1909	case SVGA_REG_WIDTH:
1910	case SVGA_REG_HEIGHT:
1911	case SVGA_REG_PITCHLOCK:
1912	case SVGA_REG_BITS_PER_PIXEL:
1913	pThis->svga.fGFBRegisters = true;
1914	break;
1915	default:
1916	break;
1917	}
1918
1919	switch (idxReg)
1920	{
1921	case SVGA_REG_ID:
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1923	if ( u32 == SVGA_ID_0
1924	\|\| u32 == SVGA_ID_1
1925	\|\| u32 == SVGA_ID_2
1926	\|\| u32 == SVGA_ID_3)
1927	pThis->svga.u32SVGAId = u32;
1928	else
1929	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1930	break;
1931
1932	case SVGA_REG_ENABLE:
1933	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1934	#ifdef IN_RING3
1935	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1936	&& pThis->svga.fEnabled == false)
1937	{
1938	/* Make a backup copy of the first 512kb in order to save font data etc. */
1939	/** @todo should probably swap here, rather than copy + zero */
1940	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1941	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1942	}
1943
1944	pThis->svga.fEnabled = u32;
1945	if (pThis->svga.fEnabled)
1946	{
1947	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1948	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1949	{
1950	/* Keep the current mode. */
1951	pThis->svga.uWidth = pThisCC->pDrv->cx;
1952	pThis->svga.uHeight = pThisCC->pDrv->cy;
1953	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1954	vmsvgaHCUpdatePitch(pThis, pThisCC);
1955	}
1956
1957	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1958	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1959	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1960	# ifdef LOG_ENABLED
1961	if (!pThis->fVmSvga3)
1962	{
1963	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1964	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1965	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1966	}
1967	# endif
1968
1969	/* Disable or enable dirty page tracking according to the current fTraces value. */
1970	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1971
1972	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1973	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1974	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1975
1976	/* Make the cursor visible again as needed. */
1977	if (pSVGAState->Cursor.fActive)
1978	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1979	}
1980	else
1981	{
1982	/* Make sure the cursor is off. */
1983	if (pSVGAState->Cursor.fActive)
1984	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1985
1986	/* Restore the text mode backup. */
1987	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1988
1989	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1990
1991	/* Enable dirty page tracking again when going into legacy mode. */
1992	vmsvgaR3SetTraces(pDevIns, pThis, true);
1993
1994	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1995	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1996	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1997
1998	/* Clear the pitch lock. */
1999	pThis->svga.u32PitchLock = 0;
2000	}
2001	#else /* !IN_RING3 */
2002	rc = VINF_IOM_R3_IOPORT_WRITE;
2003	#endif /* !IN_RING3 */
2004	break;
2005
2006	case SVGA_REG_WIDTH:
2007	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
2008	if (u32 != pThis->svga.uWidth)
2009	{
2010	if (u32 <= pThis->svga.u32MaxWidth)
2011	{
2012	#if defined(IN_RING3) \|\| defined(IN_RING0)
2013	pThis->svga.uWidth = u32;
2014	vmsvgaHCUpdatePitch(pThis, pThisCC);
2015	if (pThis->svga.fEnabled)
2016	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2017	#else
2018	rc = VINF_IOM_R3_IOPORT_WRITE;
2019	#endif
2020	}
2021	else
2022	Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
2023	}
2024	/* else: nop */
2025	break;
2026
2027	case SVGA_REG_HEIGHT:
2028	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
2029	if (u32 != pThis->svga.uHeight)
2030	{
2031	if (u32 <= pThis->svga.u32MaxHeight)
2032	{
2033	pThis->svga.uHeight = u32;
2034	if (pThis->svga.fEnabled)
2035	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2036	}
2037	else
2038	Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
2039	}
2040	/* else: nop */
2041	break;
2042
2043	case SVGA_REG_DEPTH:
2044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
2045	/** @todo read-only?? */
2046	break;
2047
2048	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
2049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
2050	if (pThis->svga.uBpp != u32)
2051	{
2052	if (u32 <= 32)
2053	{
2054	#if defined(IN_RING3) \|\| defined(IN_RING0)
2055	pThis->svga.uBpp = u32;
2056	vmsvgaHCUpdatePitch(pThis, pThisCC);
2057	if (pThis->svga.fEnabled)
2058	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2059	#else
2060	rc = VINF_IOM_R3_IOPORT_WRITE;
2061	#endif
2062	}
2063	else
2064	Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
2065	}
2066	/* else: nop */
2067	break;
2068
2069	case SVGA_REG_PSEUDOCOLOR:
2070	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
2071	break;
2072
2073	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
2074	#ifdef IN_RING3
2075	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
2076	pThis->svga.fConfigured = u32;
2077	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
2078	if (!pThis->svga.fConfigured)
2079	pThis->svga.fTraces = true;
2080	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2081	#else
2082	rc = VINF_IOM_R3_IOPORT_WRITE;
2083	#endif
2084	break;
2085
2086	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
2087	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
2088	if ( pThis->svga.fEnabled
2089	&& pThis->svga.fConfigured)
2090	{
2091	#if defined(IN_RING3) \|\| defined(IN_RING0)
2092	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
2093	/*
2094	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2095	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2096	*/
2097	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
2098	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2099	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2100
2101	/* Kick the FIFO thread to start processing commands again. */
2102	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2103	#else
2104	rc = VINF_IOM_R3_IOPORT_WRITE;
2105	#endif
2106	}
2107	/* else nothing to do. */
2108	else
2109	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2110
2111	break;
2112
2113	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2114	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2115	break;
2116
2117	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2119	pThis->svga.u32GuestId = u32;
2120	break;
2121
2122	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2123	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2124	pThis->svga.u32PitchLock = u32;
2125	/* Should this also update the FIFO pitch lock? Unclear. */
2126	break;
2127
2128	case SVGA_REG_IRQMASK: /* Interrupt mask */
2129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2130	pThis->svga.u32IrqMask = u32;
2131
2132	/* Irq pending after the above change? */
2133	if (pThis->svga.u32IrqStatus & u32)
2134	{
2135	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2136	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2137	}
2138	else
2139	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2140	break;
2141
2142	/* Mouse cursor support */
2143	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2145	pThis->svga.uCursorID = u32;
2146	break;
2147
2148	case SVGA_REG_CURSOR_X:
2149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2150	pThis->svga.uCursorX = u32;
2151	break;
2152
2153	case SVGA_REG_CURSOR_Y:
2154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2155	pThis->svga.uCursorY = u32;
2156	break;
2157
2158	case SVGA_REG_CURSOR_ON:
2159	#ifdef IN_RING3
2160	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2162	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2163	#else
2164	rc = VINF_IOM_R3_IOPORT_WRITE;
2165	#endif
2166	break;
2167
2168	/* Legacy multi-monitor support */
2169	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2170	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2171	break;
2172	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2174	break;
2175	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2177	break;
2178	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2180	break;
2181	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2183	break;
2184	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2185	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2186	break;
2187	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2189	break;
2190	#ifdef VBOX_WITH_VMSVGA3D
2191	/* See "Guest memory regions" below. */
2192	case SVGA_REG_GMR_ID:
2193	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2194	pThis->svga.u32CurrentGMRId = u32;
2195	break;
2196
2197	case SVGA_REG_GMR_DESCRIPTOR:
2198	# ifndef IN_RING3
2199	rc = VINF_IOM_R3_IOPORT_WRITE;
2200	break;
2201	# else /* IN_RING3 */
2202	{
2203	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2204
2205	/* Validate current GMR id. */
2206	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2207	AssertBreak(idGMR < pThis->svga.cGMR);
2208	RT_UNTRUSTED_VALIDATED_FENCE();
2209
2210	/* Free the old GMR if present. */
2211	vmsvgaR3GmrFree(pThisCC, idGMR);
2212
2213	/* Just undefine the GMR? */
2214	RTGCPHYS GCPhys = (RTGCPHYS)u32 << GUEST_PAGE_SHIFT;
2215	if (GCPhys == 0)
2216	{
2217	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2218	break;
2219	}
2220
2221
2222	/* Never cross a page boundary automatically. */
2223	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2224	uint32_t cPagesTotal = 0;
2225	uint32_t iDesc = 0;
2226	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2227	uint32_t cLoops = 0;
2228	RTGCPHYS GCPhysBase = GCPhys;
2229	while ((GCPhys >> GUEST_PAGE_SHIFT) == (GCPhysBase >> GUEST_PAGE_SHIFT))
2230	{
2231	/* Read descriptor. */
2232	SVGAGuestMemDescriptor desc;
2233	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2234	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2235
2236	if (desc.numPages != 0)
2237	{
2238	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2239	cPagesTotal += desc.numPages;
2240	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2241
2242	if ((iDesc & 15) == 0)
2243	{
2244	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2245	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2246	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2247	}
2248
2249	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2250	paDescs[iDesc++].numPages = desc.numPages;
2251
2252	/* Continue with the next descriptor. */
2253	GCPhys += sizeof(desc);
2254	}
2255	else if (desc.ppn == 0)
2256	break; /* terminator */
2257	else /* Pointer to the next physical page of descriptors. */
2258	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2259
2260	cLoops++;
2261	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2262	}
2263
2264	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2265	if (RT_SUCCESS(rc))
2266	{
2267	/* Commit the GMR. */
2268	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2269	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2270	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2271	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * GUEST_PAGE_SIZE;
2272	Assert((pSVGAState->paGMR[idGMR].cbTotal >> GUEST_PAGE_SHIFT) == cPagesTotal);
2273	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2274	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2275	}
2276	else
2277	{
2278	RTMemFree(paDescs);
2279	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2280	}
2281	break;
2282	}
2283	# endif /* IN_RING3 */
2284	#endif // VBOX_WITH_VMSVGA3D
2285
2286	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2287	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2288	if (pThis->svga.fTraces == u32)
2289	break; /* nothing to do */
2290
2291	#ifdef IN_RING3
2292	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2293	#else
2294	rc = VINF_IOM_R3_IOPORT_WRITE;
2295	#endif
2296	break;
2297
2298	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2299	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2300	break;
2301
2302	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2304	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2305	break;
2306
2307	/*
2308	* SVGA_CAP_GBOBJECTS+ registers.
2309	*/
2310	case SVGA_REG_COMMAND_LOW:
2311	{
2312	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2313	#ifdef IN_RING3
2314	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2315	pThis->svga.u32RegCommandLow = u32;
2316
2317	/* "lower 6 bits are used for the SVGACBContext" */
2318	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2319	GCPhysCB <<= 32;
2320	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2321	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2322	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2323	#else
2324	rc = VINF_IOM_R3_IOPORT_WRITE;
2325	#endif
2326	break;
2327	}
2328
2329	case SVGA_REG_COMMAND_HIGH:
2330	/* Upper 32 bits of command buffer PA. */
2331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2332	pThis->svga.u32RegCommandHigh = u32;
2333	break;
2334
2335	case SVGA_REG_DEV_CAP:
2336	/* Write dev cap index, read value */
2337	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2338	pThis->svga.u32DevCapIndex = u32;
2339	break;
2340
2341	case SVGA_REG_CMD_PREPEND_LOW:
2342	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2343	/* Not supported. */
2344	break;
2345
2346	case SVGA_REG_CMD_PREPEND_HIGH:
2347	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2348	/* Not supported. */
2349	break;
2350
2351	case SVGA_REG_GUEST_DRIVER_ID:
2352	if (u32 != SVGA_REG_GUEST_DRIVER_ID_SUBMIT)
2353	pThis->svga.u32GuestDriverId = u32;
2354	break;
2355
2356	case SVGA_REG_GUEST_DRIVER_VERSION1:
2357	pThis->svga.u32GuestDriverVer1 = u32;
2358	break;
2359
2360	case SVGA_REG_GUEST_DRIVER_VERSION2:
2361	pThis->svga.u32GuestDriverVer2 = u32;
2362	break;
2363
2364	case SVGA_REG_GUEST_DRIVER_VERSION3:
2365	pThis->svga.u32GuestDriverVer3 = u32;
2366	break;
2367
2368	case SVGA_REG_CURSOR_MOBID:
2369	/* Not supported, ignore. See correspondent comments in vmsvgaReadPort. */
2370	break;
2371
2372	case SVGA_REG_FB_START:
2373	case SVGA_REG_MEM_START:
2374	case SVGA_REG_HOST_BITS_PER_PIXEL:
2375	case SVGA_REG_MAX_WIDTH:
2376	case SVGA_REG_MAX_HEIGHT:
2377	case SVGA_REG_VRAM_SIZE:
2378	case SVGA_REG_FB_SIZE:
2379	case SVGA_REG_CAPABILITIES:
2380	case SVGA_REG_MEM_SIZE:
2381	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2382	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2383	case SVGA_REG_BYTES_PER_LINE:
2384	case SVGA_REG_FB_OFFSET:
2385	case SVGA_REG_RED_MASK:
2386	case SVGA_REG_GREEN_MASK:
2387	case SVGA_REG_BLUE_MASK:
2388	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2389	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2390	case SVGA_REG_GMR_MAX_IDS:
2391	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2392	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2393	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2394	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2395	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2396	case SVGA_REG_MOB_MAX_SIZE:
2397	case SVGA_REG_BLANK_SCREEN_TARGETS:
2398	case SVGA_REG_CAP2:
2399	case SVGA_REG_DEVEL_CAP:
2400	case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
2401	case SVGA_REG_CURSOR_MAX_DIMENSION:
2402	case SVGA_REG_FIFO_CAPS:
2403	case SVGA_REG_FENCE:
2404	case SVGA_REG_RESERVED1:
2405	case SVGA_REG_RESERVED2:
2406	case SVGA_REG_RESERVED3:
2407	case SVGA_REG_RESERVED4:
2408	case SVGA_REG_RESERVED5:
2409	case SVGA_REG_SCREENDMA:
2410	case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
2411	/* Read only - ignore. */
2412	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2413	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2414	break;
2415
2416	case SVGA_REG_IRQ_STATUS:
2417	{
2418	if (pThis->fVmSvga3)
2419	{
2420	LogFlow(("vmsvga3MmioWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2421	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2422	/* Clear the irq in case all events have been cleared. */
2423	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2424	{
2425	Log(("vmsvga3MmioWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2426	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2427	}
2428	}
2429	break;
2430	}
2431
2432	default:
2433	{
2434	uint32_t offReg;
2435	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2436	{
2437	RT_UNTRUSTED_VALIDATED_FENCE();
2438	pThis->svga.au32ScratchRegion[offReg] = u32;
2439	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2440	}
2441	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2442	{
2443	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2444	Btw, see rgb_to_pixel32. */
2445	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2446	u32 &= 0xff;
2447	RT_UNTRUSTED_VALIDATED_FENCE();
2448	uint32_t uRgb = pThis->last_palette[offReg / 3];
2449	switch (offReg % 3)
2450	{
2451	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2452	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2453	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2454	}
2455	pThis->last_palette[offReg / 3] = uRgb;
2456	}
2457	else
2458	{
2459	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2460	rc = VINF_IOM_R3_IOPORT_WRITE;
2461	#else
2462	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2463	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2464	#endif
2465	}
2466	break;
2467	}
2468	}
2469	return rc;
2470	}
2471
2472	/**
2473	* @callback_method_impl{FNIOMIOPORTNEWIN}
2474	*/
2475	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2476	{
2477	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2478	RT_NOREF_PV(pvUser);
2479
2480	/* Only dword accesses. */
2481	if (cb == 4)
2482	{
2483	switch (offPort)
2484	{
2485	case SVGA_INDEX_PORT:
2486	*pu32 = pThis->svga.u32IndexReg;
2487	break;
2488
2489	case SVGA_VALUE_PORT:
2490	{
2491	/* Rough index register validation. */
2492	uint32_t idxReg = pThis->svga.u32IndexReg;
2493	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2494	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2495	VINF_IOM_R3_IOPORT_READ);
2496	#else
2497	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2498	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
2499	VINF_SUCCESS);
2500	#endif
2501	RT_UNTRUSTED_VALIDATED_FENCE();
2502
2503	return vmsvgaReadPort(pDevIns, pThis, idxReg, pu32);
2504	}
2505
2506	case SVGA_BIOS_PORT:
2507	Log(("Ignoring BIOS port read\n"));
2508	*pu32 = 0;
2509	break;
2510
2511	case SVGA_IRQSTATUS_PORT:
2512	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2513	*pu32 = pThis->svga.u32IrqStatus;
2514	break;
2515
2516	default:
2517	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2518	*pu32 = UINT32_MAX;
2519	break;
2520	}
2521	}
2522	else
2523	{
2524	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2525	*pu32 = UINT32_MAX;
2526	}
2527	return VINF_SUCCESS;
2528	}
2529
2530	/**
2531	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2532	*/
2533	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2534	{
2535	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2536	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2537	RT_NOREF_PV(pvUser);
2538
2539	/* Only dword accesses. */
2540	if (cb == 4)
2541	switch (offPort)
2542	{
2543	case SVGA_INDEX_PORT:
2544	pThis->svga.u32IndexReg = u32;
2545	break;
2546
2547	case SVGA_VALUE_PORT:
2548	{
2549	/* Rough index register validation. */
2550	uint32_t idxReg = pThis->svga.u32IndexReg;
2551	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2552	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2553	VINF_IOM_R3_IOPORT_WRITE);
2554	#else
2555	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
2556	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
2557	VINF_SUCCESS);
2558	#endif
2559	RT_UNTRUSTED_VALIDATED_FENCE();
2560
2561	return vmsvgaWritePort(pDevIns, pThis, pThisCC, idxReg, u32);
2562	}
2563
2564	case SVGA_BIOS_PORT:
2565	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2566	break;
2567
2568	case SVGA_IRQSTATUS_PORT:
2569	LogFlow(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2570	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2571	/* Clear the irq in case all events have been cleared. */
2572	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2573	{
2574	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2575	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2576	}
2577	break;
2578
2579	default:
2580	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2581	break;
2582	}
2583	else
2584	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2585
2586	return VINF_SUCCESS;
2587	}
2588
2589	/**
2590	* @callback_method_impl{FNIOMMMIONEWREAD}
2591	*/
2592	DECLCALLBACK(VBOXSTRICTRC) vmsvga3MmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
2593	{
2594	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2595	RT_NOREF_PV(pvUser);
2596
2597	/* Only dword accesses. */
2598	VBOXSTRICTRC rcStrict;
2599	if (cb == sizeof(uint32_t))
2600	{
2601	rcStrict = vmsvgaReadPort(pDevIns, pThis, (uint32_t)(off / sizeof(uint32_t)), (uint32_t *)pv);
2602	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
2603	rcStrict = VINF_IOM_R3_MMIO_READ;
2604	}
2605	else
2606	{
2607	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", off, cb));
2608	rcStrict = VINF_IOM_MMIO_UNUSED_00;
2609	}
2610	return rcStrict;
2611	}
2612
2613	/**
2614	* @callback_method_impl{FNIOMMMIONEWWRITE}
2615	*/
2616	DECLCALLBACK(VBOXSTRICTRC) vmsvga3MmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
2617	{
2618	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2619	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2620	RT_NOREF_PV(pvUser);
2621
2622	/* Only dword accesses. */
2623	VBOXSTRICTRC rcStrict;
2624	if (cb == sizeof(uint32_t))
2625	{
2626	rcStrict = vmsvgaWritePort(pDevIns, pThis, pThisCC, (uint32_t)(off / sizeof(uint32_t)), (uint32_t )pv);
2627	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
2628	rcStrict = VINF_IOM_R3_MMIO_WRITE;
2629	}
2630	else
2631	{
2632	Log(("Ignoring non-dword write at %x cb=%d\n", off, cb));
2633	rcStrict = VINF_SUCCESS;
2634	}
2635
2636	return rcStrict;
2637	}
2638
2639	#ifdef IN_RING3
2640
2641	# ifdef DEBUG_FIFO_ACCESS
2642	/**
2643	* Handle FIFO memory access.
2644	* @returns VBox status code.
2645	* @param pVM VM handle.
2646	* @param pThis The shared VGA/VMSVGA instance data.
2647	* @param GCPhys The access physical address.
2648	* @param fWriteAccess Read or write access
2649	*/
2650	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2651	{
2652	RT_NOREF(pVM);
2653	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2654	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2655
2656	switch (GCPhysOffset >> 2)
2657	{
2658	case SVGA_FIFO_MIN:
2659	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660	break;
2661	case SVGA_FIFO_MAX:
2662	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663	break;
2664	case SVGA_FIFO_NEXT_CMD:
2665	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666	break;
2667	case SVGA_FIFO_STOP:
2668	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669	break;
2670	case SVGA_FIFO_CAPABILITIES:
2671	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672	break;
2673	case SVGA_FIFO_FLAGS:
2674	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675	break;
2676	case SVGA_FIFO_FENCE:
2677	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678	break;
2679	case SVGA_FIFO_3D_HWVERSION:
2680	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681	break;
2682	case SVGA_FIFO_PITCHLOCK:
2683	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684	break;
2685	case SVGA_FIFO_CURSOR_ON:
2686	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687	break;
2688	case SVGA_FIFO_CURSOR_X:
2689	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690	break;
2691	case SVGA_FIFO_CURSOR_Y:
2692	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693	break;
2694	case SVGA_FIFO_CURSOR_COUNT:
2695	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696	break;
2697	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2698	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699	break;
2700	case SVGA_FIFO_RESERVED:
2701	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702	break;
2703	case SVGA_FIFO_CURSOR_SCREEN_ID:
2704	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705	break;
2706	case SVGA_FIFO_DEAD:
2707	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708	break;
2709	case SVGA_FIFO_3D_HWVERSION_REVISED:
2710	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711	break;
2712	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2713	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2714	break;
2715	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2716	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2717	break;
2718	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2719	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2720	break;
2721	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2722	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2723	break;
2724	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2725	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2726	break;
2727	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2728	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2729	break;
2730	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2731	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2732	break;
2733	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2734	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2735	break;
2736	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2737	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2738	break;
2739	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2740	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2741	break;
2742	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2743	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2744	break;
2745	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2746	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2747	break;
2748	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2749	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2750	break;
2751	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2752	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2753	break;
2754	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2755	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2756	break;
2757	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2758	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2759	break;
2760	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2761	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2762	break;
2763	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2764	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2765	break;
2766	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2767	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2768	break;
2769	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2770	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2771	break;
2772	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2773	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2774	break;
2775	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2776	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2777	break;
2778	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2779	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2780	break;
2781	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2782	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2783	break;
2784	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2785	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2786	break;
2787	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2788	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2789	break;
2790	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2791	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2792	break;
2793	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2794	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2795	break;
2796	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2797	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2798	break;
2799	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2800	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2801	break;
2802	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2803	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2804	break;
2805	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2806	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2807	break;
2808	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2809	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2810	break;
2811	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2812	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2813	break;
2814	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2815	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2816	break;
2817	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2818	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2819	break;
2820	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2821	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2822	break;
2823	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2824	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2825	break;
2826	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2827	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2828	break;
2829	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2830	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2831	break;
2832	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2833	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2834	break;
2835	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2836	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2837	break;
2838	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2839	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2840	break;
2841	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2842	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2843	break;
2844	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2845	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2846	break;
2847	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2848	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2849	break;
2850	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2851	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2852	break;
2853	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2854	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2855	break;
2856	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2857	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2858	break;
2859	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2860	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2861	break;
2862	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2863	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2864	break;
2865	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2866	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2867	break;
2868	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2869	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2870	break;
2871	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2872	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2873	break;
2874	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2875	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2876	break;
2877	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2878	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2879	break;
2880	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2881	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2882	break;
2883	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2884	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2885	break;
2886	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2887	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2888	break;
2889	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2890	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2891	break;
2892	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2893	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2894	break;
2895	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2896	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2897	break;
2898	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2899	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2900	break;
2901	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2902	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2903	break;
2904	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2905	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2906	break;
2907	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2908	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2909	break;
2910	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2911	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2912	break;
2913	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2914	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2915	break;
2916	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2917	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2918	break;
2919	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2920	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2921	break;
2922	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2923	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2924	break;
2925	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2926	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2927	break;
2928	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2929	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2930	break;
2931	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2932	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2933	break;
2934	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2935	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2936	break;
2937	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2938	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2939	break;
2940	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2941	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2942	break;
2943	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2944	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2945	break;
2946	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2947	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2948	break;
2949	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2950	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2951	break;
2952	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2953	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2954	break;
2955	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2956	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2957	break;
2958	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2959	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2960	break;
2961	case SVGA_FIFO_3D_CAPS_LAST:
2962	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2963	break;
2964	case SVGA_FIFO_GUEST_3D_HWVERSION:
2965	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2966	break;
2967	case SVGA_FIFO_FENCE_GOAL:
2968	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2969	break;
2970	case SVGA_FIFO_BUSY:
2971	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2972	break;
2973	default:
2974	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2975	break;
2976	}
2977
2978	return VINF_EM_RAW_EMULATE_INSTR;
2979	}
2980	# endif /* DEBUG_FIFO_ACCESS */
2981
2982	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2983	/**
2984	* HC access handler for the FIFO.
2985	*
2986	* @returns VINF_SUCCESS if the handler have carried out the operation.
2987	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2988	* @param pVM VM Handle.
2989	* @param pVCpu The cross context CPU structure for the calling EMT.
2990	* @param GCPhys The physical address the guest is writing to.
2991	* @param pvPhys The HC mapping of that address.
2992	* @param pvBuf What the guest is reading/writing.
2993	* @param cbBuf How much it's reading/writing.
2994	* @param enmAccessType The access type.
2995	* @param enmOrigin Who is making the access.
2996	* @param pvUser User argument.
2997	*/
2998	static DECLCALLBACK(VBOXSTRICTRC)
2999	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3000	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3001	{
3002	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
3003	PVGASTATE pThis = (PVGASTATE)pvUser;
3004	AssertPtr(pThis);
3005
3006	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3007	/*
3008	* Wake up the FIFO thread as it might have work to do now.
3009	*/
3010	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3011	AssertLogRelRC(rc);
3012	# endif
3013
3014	# ifdef DEBUG_FIFO_ACCESS
3015	/*
3016	* When in debug-fifo-access mode, we do not disable the access handler,
3017	* but leave it on as we wish to catch all access.
3018	*/
3019	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
3020	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
3021	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
3022	/*
3023	* Temporarily disable the access handler now that we've kicked the FIFO thread.
3024	*/
3025	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
3026	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
3027	# endif
3028	if (RT_SUCCESS(rc))
3029	return VINF_PGM_HANDLER_DO_DEFAULT;
3030	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
3031	return rc;
3032	}
3033	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
3034
3035	#endif /* IN_RING3 */
3036
3037	#ifdef DEBUG_GMR_ACCESS
3038	# ifdef IN_RING3
3039
3040	/**
3041	* HC access handler for GMRs.
3042	*
3043	* @returns VINF_SUCCESS if the handler have carried out the operation.
3044	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3045	* @param pVM VM Handle.
3046	* @param pVCpu The cross context CPU structure for the calling EMT.
3047	* @param GCPhys The physical address the guest is writing to.
3048	* @param pvPhys The HC mapping of that address.
3049	* @param pvBuf What the guest is reading/writing.
3050	* @param cbBuf How much it's reading/writing.
3051	* @param enmAccessType The access type.
3052	* @param enmOrigin Who is making the access.
3053	* @param pvUser User argument.
3054	*/
3055	static DECLCALLBACK(VBOXSTRICTRC)
3056	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
3057	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
3058	{
3059	PVGASTATE pThis = (PVGASTATE)pvUser;
3060	Assert(pThis);
3061	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3062	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
3063
3064	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
3065
3066	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3067	{
3068	PGMR pGMR = &pSVGAState->paGMR[i];
3069
3070	if (pGMR->numDescriptors)
3071	{
3072	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3073	{
3074	if ( GCPhys >= pGMR->paDesc[j].GCPhys
3075	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * GUEST_PAGE_SIZE)
3076	{
3077	/*
3078	* Turn off the write handler for this particular page and make it R/W.
3079	* Then return telling the caller to restart the guest instruction.
3080	*/
3081	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
3082	AssertRC(rc);
3083	return VINF_PGM_HANDLER_DO_DEFAULT;
3084	}
3085	}
3086	}
3087	}
3088
3089	return VINF_PGM_HANDLER_DO_DEFAULT;
3090	}
3091
3092	/** Callback handler for VMR3ReqCallWaitU */
3093	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3094	{
3095	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3096	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3097	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3098	int rc;
3099
3100	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3101	{
3102	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, pGMR->paDesc[i].GCPhys,
3103	pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * GUEST_PAGE_SIZE - 1,
3104	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
3105	AssertRC(rc);
3106	}
3107	return VINF_SUCCESS;
3108	}
3109
3110	/** Callback handler for VMR3ReqCallWaitU */
3111	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
3112	{
3113	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3114	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3115	PGMR pGMR = &pSVGAState->paGMR[gmrId];
3116
3117	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3118	{
3119	int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
3120	AssertRC(rc);
3121	}
3122	return VINF_SUCCESS;
3123	}
3124
3125	/** Callback handler for VMR3ReqCallWaitU */
3126	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
3127	{
3128	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3129
3130	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3131	{
3132	PGMR pGMR = &pSVGAState->paGMR[i];
3133
3134	if (pGMR->numDescriptors)
3135	{
3136	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3137	{
3138	int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
3139	AssertRC(rc);
3140	}
3141	}
3142	}
3143	return VINF_SUCCESS;
3144	}
3145
3146	# endif /* IN_RING3 */
3147	#endif /* DEBUG_GMR_ACCESS */
3148
3149	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3150
3151	#ifdef IN_RING3
3152
3153
3154	/*
3155	*
3156	* Command buffer submission.
3157	*
3158	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
3159	*
3160	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
3161	* and wakes up the FIFO thread.
3162	*
3163	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
3164	* the buffer header back to the guest memory.
3165	*
3166	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
3167	*
3168	*/
3169
3170
3171	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
3172	*
3173	* @param pDevIns The device instance.
3174	* @param GCPhysCB Guest physical address of the command buffer header.
3175	* @param status Command buffer status (SVGA_CB_STATUS_*).
3176	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
3177	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
3178	* @thread FIFO or EMT.
3179	*/
3180	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
3181	{
3182	SVGACBHeader hdr;
3183	hdr.status = status;
3184	hdr.errorOffset = errorOffset;
3185	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
3186	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
3187	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
3188	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
3189	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
3190	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
3191	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
3192	}
3193
3194
3195	/** Raise an IRQ.
3196	*
3197	* @param pDevIns The device instance.
3198	* @param pThis The shared VGA/VMSVGA state.
3199	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
3200	* @thread FIFO or EMT.
3201	*/
3202	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
3203	{
3204	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
3205	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
3206
3207	if (pThis->svga.u32IrqMask & u32IrqStatus)
3208	{
3209	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
3210	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3211	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3212	}
3213
3214	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3215	}
3216
3217
3218	/** Allocate a command buffer structure.
3219	*
3220	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
3221	* @return Pointer to the allocated command buffer structure.
3222	*/
3223	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
3224	{
3225	if (!pCmdBufCtx)
3226	return NULL;
3227
3228	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
3229	if (pCmdBuf)
3230	{
3231	// RT_ZERO(pCmdBuf->nodeBuffer);
3232	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
3233	// pCmdBuf->GCPhysCB = 0;
3234	// RT_ZERO(pCmdBuf->hdr);
3235	// pCmdBuf->pvCommands = NULL;
3236	}
3237
3238	return pCmdBuf;
3239	}
3240
3241
3242	/** Free a command buffer structure.
3243	*
3244	* @param pCmdBuf The command buffer pointer.
3245	*/
3246	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3247	{
3248	if (pCmdBuf)
3249	RTMemFree(pCmdBuf->pvCommands);
3250	RTMemFree(pCmdBuf);
3251	}
3252
3253
3254	/** Initialize a command buffer context.
3255	*
3256	* @param pCmdBufCtx The command buffer context.
3257	*/
3258	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3259	{
3260	RTListInit(&pCmdBufCtx->listSubmitted);
3261	pCmdBufCtx->cSubmitted = 0;
3262	}
3263
3264
3265	/** Destroy a command buffer context.
3266	*
3267	* @param pCmdBufCtx The command buffer context pointer.
3268	*/
3269	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3270	{
3271	if (!pCmdBufCtx)
3272	return;
3273
3274	if (pCmdBufCtx->listSubmitted.pNext)
3275	{
3276	/* If the list has been initialized. */
3277	PVMSVGACMDBUF pIter, pNext;
3278	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3279	{
3280	RTListNodeRemove(&pIter->nodeBuffer);
3281	--pCmdBufCtx->cSubmitted;
3282	vmsvgaR3CmdBufFree(pIter);
3283	}
3284	}
3285	Assert(pCmdBufCtx->cSubmitted == 0);
3286	pCmdBufCtx->cSubmitted = 0;
3287	}
3288
3289
3290	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3291	*
3292	* @param pSvgaR3State VMSVGA R3 state.
3293	* @param pCmd The command data.
3294	* @return SVGACBStatus code.
3295	* @thread EMT
3296	*/
3297	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3298	{
3299	/* Create or destroy a regular command buffer context. */
3300	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3301	return SVGA_CB_STATUS_COMMAND_ERROR;
3302	RT_UNTRUSTED_VALIDATED_FENCE();
3303
3304	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3305
3306	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3307	AssertRC(rc);
3308	if (pCmd->enable)
3309	{
3310	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3311	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3312	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3313	else
3314	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3315	}
3316	else
3317	{
3318	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3319	RTMemFree(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3320	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3321	}
3322	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3323
3324	return CBStatus;
3325	}
3326
3327
3328	/** Handles SVGA_DC_CMD_PREEMPT command.
3329	*
3330	* @param pDevIns The device instance.
3331	* @param pSvgaR3State VMSVGA R3 state.
3332	* @param pCmd The command data.
3333	* @return SVGACBStatus code.
3334	* @thread EMT
3335	*/
3336	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3337	{
3338	/* Remove buffers from the processing queue of the specified context. */
3339	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3340	return SVGA_CB_STATUS_COMMAND_ERROR;
3341	RT_UNTRUSTED_VALIDATED_FENCE();
3342
3343	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3344	RTLISTANCHOR listPreempted;
3345
3346	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3347	AssertRC(rc);
3348	if (pCmd->ignoreIDZero)
3349	{
3350	RTListInit(&listPreempted);
3351
3352	PVMSVGACMDBUF pIter, pNext;
3353	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3354	{
3355	if (pIter->hdr.id == 0)
3356	continue;
3357
3358	RTListNodeRemove(&pIter->nodeBuffer);
3359	--pCmdBufCtx->cSubmitted;
3360	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3361	}
3362	}
3363	else
3364	{
3365	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3366	pCmdBufCtx->cSubmitted = 0;
3367	}
3368	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3369
3370	PVMSVGACMDBUF pIter, pNext;
3371	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3372	{
3373	RTListNodeRemove(&pIter->nodeBuffer);
3374	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3375	LogFunc(("Preempted %RX64\n", pIter->GCPhysCB));
3376	vmsvgaR3CmdBufFree(pIter);
3377	}
3378
3379	return SVGA_CB_STATUS_COMPLETED;
3380	}
3381
3382
3383	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3384	* Increments the size of the command cbCmd by a_cbMore.
3385	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3386	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3387	*/
3388	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3389	if (1) { \
3390	cbCmd += (a_cbMore); \
3391	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3392	RT_UNTRUSTED_VALIDATED_FENCE(); \
3393	} else do {} while (0)
3394
3395
3396	/** Processes Device Context command buffer.
3397	*
3398	* @param pDevIns The device instance.
3399	* @param pSvgaR3State VMSVGA R3 state.
3400	* @param pvCommands Pointer to the command buffer.
3401	* @param cbCommands Size of the command buffer.
3402	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3403	* @return SVGACBStatus code.
3404	* @thread EMT
3405	*/
3406	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3407	{
3408	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3409
3410	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3411	uint32_t cbRemain = cbCommands;
3412	while (cbRemain)
3413	{
3414	/* Command identifier is a 32 bit value. */
3415	if (cbRemain < sizeof(uint32_t))
3416	{
3417	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3418	break;
3419	}
3420
3421	/* Fetch the command id. */
3422	uint32_t const cmdId = (uint32_t )pu8Cmd;
3423	uint32_t cbCmd = sizeof(uint32_t);
3424	switch (cmdId)
3425	{
3426	case SVGA_DC_CMD_NOP:
3427	{
3428	/* NOP */
3429	break;
3430	}
3431
3432	case SVGA_DC_CMD_START_STOP_CONTEXT:
3433	{
3434	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3435	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3436	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3437	break;
3438	}
3439
3440	case SVGA_DC_CMD_PREEMPT:
3441	{
3442	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3443	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3444	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3445	break;
3446	}
3447
3448	default:
3449	{
3450	/* Unsupported command. */
3451	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3452	break;
3453	}
3454	}
3455
3456	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3457	break;
3458
3459	pu8Cmd += cbCmd;
3460	cbRemain -= cbCmd;
3461	}
3462
3463	Assert(cbRemain <= cbCommands);
3464	*poffNextCmd = cbCommands - cbRemain;
3465	return CBstatus;
3466	}
3467
3468
3469	/** Submits a device context command buffer for synchronous processing.
3470	*
3471	* @param pDevIns The device instance.
3472	* @param pThisCC The VGA/VMSVGA state for the current context.
3473	* @param ppCmdBuf Pointer to the command buffer pointer.
3474	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3475	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3476	* @return SVGACBStatus code.
3477	* @thread EMT
3478	*/
3479	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3480	{
3481	/* Synchronously process the device context commands. */
3482	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3483	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3484	}
3485
3486	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3487	*
3488	* @param pDevIns The device instance.
3489	* @param pThis The shared VGA/VMSVGA state.
3490	* @param pThisCC The VGA/VMSVGA state for the current context.
3491	* @param ppCmdBuf Pointer to the command buffer pointer.
3492	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3493	* @return SVGACBStatus code.
3494	* @thread EMT
3495	*/
3496	static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3497	{
3498	/* Command buffer submission. */
3499	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3500
3501	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3502
3503	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3504	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3505
3506	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3507	AssertRC(rc);
3508
3509	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3510	{
3511	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3512	++pCmdBufCtx->cSubmitted;
3513	ppCmdBuf = NULL; / Consume the buffer. */
3514	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3515	}
3516	else
3517	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3518
3519	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3520
3521	/* Inform the FIFO thread. */
3522	if (*ppCmdBuf == NULL)
3523	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3524
3525	return CBstatus;
3526	}
3527
3528
3529	/** SVGA_REG_COMMAND_LOW write handler.
3530	* Submits a command buffer to the FIFO thread or processes a device context command.
3531	*
3532	* @param pDevIns The device instance.
3533	* @param pThis The shared VGA/VMSVGA state.
3534	* @param pThisCC The VGA/VMSVGA state for the current context.
3535	* @param GCPhysCB Guest physical address of the command buffer header.
3536	* @param CBCtx Context the command buffer is submitted to.
3537	* @thread EMT
3538	*/
3539	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3540	{
3541	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3542
3543	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3544	uint32_t offNextCmd = 0;
3545	uint32_t fIRQ = 0;
3546
3547	/* Get the context if the device has the capability. */
3548	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3549	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3550	{
3551	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3552	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3553	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3554	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3555	RT_UNTRUSTED_VALIDATED_FENCE();
3556	}
3557
3558	/* Allocate a new command buffer. */
3559	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3560	if (RT_LIKELY(pCmdBuf))
3561	{
3562	pCmdBuf->GCPhysCB = GCPhysCB;
3563
3564	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3565	if (RT_SUCCESS(rc))
3566	{
3567	LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3568	pCmdBuf->hdr.status,
3569	pCmdBuf->hdr.errorOffset,
3570	pCmdBuf->hdr.id,
3571	pCmdBuf->hdr.flags,
3572	pCmdBuf->hdr.length,
3573	pCmdBuf->hdr.ptr.pa,
3574	pCmdBuf->hdr.offset,
3575	pCmdBuf->hdr.dxContext,
3576	pCmdBuf->hdr.mustBeZero[0],
3577	pCmdBuf->hdr.mustBeZero[1],
3578	pCmdBuf->hdr.mustBeZero[2],
3579	pCmdBuf->hdr.mustBeZero[3],
3580	pCmdBuf->hdr.mustBeZero[4],
3581	pCmdBuf->hdr.mustBeZero[5]));
3582
3583	/* Verify the command buffer header. */
3584	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3585	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ \| SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3586	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3587	{
3588	RT_UNTRUSTED_VALIDATED_FENCE();
3589
3590	/* Read the command buffer content. */
3591	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3592	if (pCmdBuf->pvCommands)
3593	{
3594	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3595	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3596	if (RT_SUCCESS(rc))
3597	{
3598	/* Submit the buffer. Device context buffers will be processed synchronously. */
3599	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3600	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3601	CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3602	else
3603	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3604	}
3605	else
3606	{
3607	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3608	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3609	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3610	}
3611	}
3612	else
3613	{
3614	/* No memory for commands. */
3615	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3616	}
3617	}
3618	else
3619	{
3620	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3621	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3622	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3623	}
3624	}
3625	else
3626	{
3627	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3628	ASSERT_GUEST_FAILED();
3629	/* Do not attempt to write the status. */
3630	}
3631
3632	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3633	vmsvgaR3CmdBufFree(pCmdBuf);
3634	}
3635	else
3636	{
3637	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3638	AssertFailed();
3639	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3640	}
3641
3642	if (CBstatus != SVGA_CB_STATUS_NONE)
3643	{
3644	LogFunc(("Write status %#x, offNextCmd %#x, fIRQ %#x\n", CBstatus, offNextCmd, fIRQ));
3645	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3646	if (fIRQ)
3647	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3648	}
3649	}
3650
3651
3652	/** Checks if there are some buffers to be processed.
3653	*
3654	* @param pThisCC The VGA/VMSVGA state for the current context.
3655	* @return true if buffers must be processed.
3656	* @thread FIFO
3657	*/
3658	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3659	{
3660	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3661	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3662	}
3663
3664
3665	/** Processes a command buffer.
3666	*
3667	* @param pDevIns The device instance.
3668	* @param pThis The shared VGA/VMSVGA state.
3669	* @param pThisCC The VGA/VMSVGA state for the current context.
3670	* @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3671	* @param pvCommands Pointer to the command buffer.
3672	* @param cbCommands Size of the command buffer.
3673	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3674	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3675	* @return SVGACBStatus code.
3676	* @thread FIFO
3677	*/
3678	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3679	{
3680	# ifndef VBOX_WITH_VMSVGA3D
3681	RT_NOREF(idDXContext);
3682	# endif
3683	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3684	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3685
3686	# ifdef VBOX_WITH_VMSVGA3D
3687	# ifdef VMSVGA3D_DX
3688	/* Commands submitted for the SVGA3D_INVALID_ID context do not affect pipeline. So ignore them. */
3689	if (idDXContext != SVGA3D_INVALID_ID)
3690	{
3691	if (pSvgaR3State->idDXContextCurrent != idDXContext)
3692	{
3693	LogFlow(("DXCTX: buffer %d->%d\n", pSvgaR3State->idDXContextCurrent, idDXContext));
3694	vmsvga3dDXSwitchContext(pThisCC, idDXContext);
3695	pSvgaR3State->idDXContextCurrent = idDXContext;
3696	}
3697	}
3698	# endif
3699	# endif
3700
3701	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3702
3703	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3704	uint32_t cbRemain = cbCommands;
3705	while (cbRemain)
3706	{
3707	/* Command identifier is a 32 bit value. */
3708	if (cbRemain < sizeof(uint32_t))
3709	{
3710	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3711	break;
3712	}
3713
3714	/* Fetch the command id.
3715	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3716	* warning. Because we support some obsolete and deprecated commands, which are not included in
3717	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3718	*/
3719	uint32_t const cmdId = (uint32_t )pu8Cmd;
3720	uint32_t cbCmd = sizeof(uint32_t);
3721
3722	LogFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3723	# ifdef LOG_ENABLED
3724	# ifdef VBOX_WITH_VMSVGA3D
3725	if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3726	{
3727	SVGA3dCmdHeader const header = (SVGA3dCmdHeader )pu8Cmd;
3728	svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3729	}
3730	else if (cmdId == SVGA_CMD_FENCE)
3731	{
3732	Log7(("\tSVGA_CMD_FENCE\n"));
3733	Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3734	}
3735	# endif
3736	# endif
3737
3738	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3739	* I.e. pu8Cmd + cbCmd must point to the next command.
3740	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3741	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3742	*/
3743	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3744	LogFlow(("cmdId=%u\n", cmdId));
3745	switch (cmdId)
3746	{
3747	case SVGA_CMD_INVALID_CMD:
3748	{
3749	/* Nothing to do. */
3750	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3751	break;
3752	}
3753
3754	case SVGA_CMD_FENCE:
3755	{
3756	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3757	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3758	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3759	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3760
3761	if (pThis->fVmSvga3)
3762	{
3763	pThis->svga.u32FenceLast = pCmd->fence;
3764
3765	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3766	{
3767	Log(("any fence irq\n"));
3768	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3769	}
3770	else if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3771	{
3772	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3773	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3774	}
3775	}
3776	else
3777	{
3778	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3779	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3780	{
3781	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3782
3783	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3784	{
3785	Log(("any fence irq\n"));
3786	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3787	}
3788	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3789	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3790	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3791	{
3792	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3793	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3794	}
3795	}
3796	else
3797	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3798	}
3799	break;
3800	}
3801
3802	case SVGA_CMD_UPDATE:
3803	{
3804	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3805	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3806	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3807	break;
3808	}
3809
3810	case SVGA_CMD_UPDATE_VERBOSE:
3811	{
3812	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3813	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3814	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3815	break;
3816	}
3817
3818	case SVGA_CMD_DEFINE_CURSOR:
3819	{
3820	/* Followed by bitmap data. */
3821	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3822	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3823
3824	/* Figure out the size of the bitmap data. */
3825	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3826	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3827	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3828	RT_UNTRUSTED_VALIDATED_FENCE();
3829
3830	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3831	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3832	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3833	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3834
3835	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3836	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3837	break;
3838	}
3839
3840	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3841	{
3842	/* Followed by bitmap data. */
3843	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3844	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3845
3846	/* Figure out the size of the bitmap data. */
3847	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3848
3849	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3850	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3851	break;
3852	}
3853
3854	case SVGA_CMD_MOVE_CURSOR:
3855	{
3856	/* Deprecated; there should be no driver which requires this command. However, if
3857	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3858	* alignment.
3859	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3860	*/
3861	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3862	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3863	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3864	break;
3865	}
3866
3867	case SVGA_CMD_DISPLAY_CURSOR:
3868	{
3869	/* Deprecated; there should be no driver which requires this command. However, if
3870	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3871	* alignment.
3872	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3873	*/
3874	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3875	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3876	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3877	break;
3878	}
3879
3880	case SVGA_CMD_RECT_FILL:
3881	{
3882	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3883	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3884	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3885	break;
3886	}
3887
3888	case SVGA_CMD_RECT_COPY:
3889	{
3890	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3891	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3892	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3893	break;
3894	}
3895
3896	case SVGA_CMD_RECT_ROP_COPY:
3897	{
3898	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3899	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3900	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3901	break;
3902	}
3903
3904	case SVGA_CMD_ESCAPE:
3905	{
3906	/* Followed by 'size' bytes of data. */
3907	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3908	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3909
3910	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3911	RT_UNTRUSTED_VALIDATED_FENCE();
3912
3913	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3914	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3915	break;
3916	}
3917	# ifdef VBOX_WITH_VMSVGA3D
3918	case SVGA_CMD_DEFINE_GMR2:
3919	{
3920	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3921	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3922	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3923	break;
3924	}
3925
3926	case SVGA_CMD_REMAP_GMR2:
3927	{
3928	/* Followed by page descriptors or guest ptr. */
3929	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3930	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3931
3932	/* Calculate the size of what comes after next and fetch it. */
3933	uint32_t cbMore = 0;
3934	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3935	cbMore = sizeof(SVGAGuestPtr);
3936	else
3937	{
3938	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3939	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3940	{
3941	cbMore = cbPageDesc;
3942	pCmd->numPages = 1;
3943	}
3944	else
3945	{
3946	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3947	cbMore = cbPageDesc * pCmd->numPages;
3948	}
3949	}
3950	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3951	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3952	# ifdef DEBUG_GMR_ACCESS
3953	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3954	# endif
3955	break;
3956	}
3957	# endif /* VBOX_WITH_VMSVGA3D */
3958	case SVGA_CMD_DEFINE_SCREEN:
3959	{
3960	/* The size of this command is specified by the guest and depends on capabilities. */
3961	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3962	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3963	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3964	RT_UNTRUSTED_VALIDATED_FENCE();
3965
3966	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3967	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3968	break;
3969	}
3970
3971	case SVGA_CMD_DESTROY_SCREEN:
3972	{
3973	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3974	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3975	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3976	break;
3977	}
3978
3979	case SVGA_CMD_DEFINE_GMRFB:
3980	{
3981	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3982	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3983	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3984	break;
3985	}
3986
3987	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3988	{
3989	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3990	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3991	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3992	break;
3993	}
3994
3995	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3996	{
3997	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3998	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3999	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4000	break;
4001	}
4002
4003	case SVGA_CMD_ANNOTATION_FILL:
4004	{
4005	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
4006	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4007	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4008	break;
4009	}
4010
4011	case SVGA_CMD_ANNOTATION_COPY:
4012	{
4013	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
4014	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
4015	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4016	break;
4017	}
4018
4019	default:
4020	{
4021	# ifdef VBOX_WITH_VMSVGA3D
4022	if ( cmdId >= SVGA_3D_CMD_BASE
4023	&& cmdId < SVGA_3D_CMD_MAX)
4024	{
4025	RT_UNTRUSTED_VALIDATED_FENCE();
4026
4027	/* All 3d commands start with a common header, which defines the identifier and the size
4028	* of the command. The identifier has been already read. Fetch the size.
4029	*/
4030	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
4031	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
4032	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
4033	if (RT_LIKELY(pThis->svga.f3DEnabled))
4034	{ /* likely */ }
4035	else
4036	{
4037	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
4038	break;
4039	}
4040
4041	/* Command data begins after the 32 bit command length. */
4042	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
4043	if (RT_SUCCESS(rc))
4044	{ /* likely */ }
4045	else
4046	{
4047	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4048	break;
4049	}
4050	}
4051	else
4052	# endif /* VBOX_WITH_VMSVGA3D */
4053	{
4054	/* Unsupported command. */
4055	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
4056	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
4057	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
4058	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
4059	break;
4060	}
4061	}
4062	}
4063
4064	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
4065	break;
4066
4067	pu8Cmd += cbCmd;
4068	cbRemain -= cbCmd;
4069
4070	/* If this is not the last command in the buffer, then generate IRQ, if required.
4071	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
4072	* in the buffer (usually the case).
4073	*/
4074	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
4075	{ /* likely */ }
4076	else
4077	{
4078	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
4079	*pu32IrqStatus = 0;
4080	}
4081	}
4082
4083	Assert(cbRemain <= cbCommands);
4084	*poffNextCmd = cbCommands - cbRemain;
4085	return CBstatus;
4086	}
4087
4088
4089	/** Process command buffers.
4090	*
4091	* @param pDevIns The device instance.
4092	* @param pThis The shared VGA/VMSVGA state.
4093	* @param pThisCC The VGA/VMSVGA state for the current context.
4094	* @param pThread Handle of the FIFO thread.
4095	* @thread FIFO
4096	*/
4097	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
4098	{
4099	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4100
4101	for (;;)
4102	{
4103	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4104	break;
4105
4106	/* See if there is a submitted buffer. */
4107	PVMSVGACMDBUF pCmdBuf = NULL;
4108
4109	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
4110	AssertRC(rc);
4111
4112	/* It seems that a higher queue index has a higher priority.
4113	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
4114	*/
4115	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
4116	{
4117	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
4118	if (pCmdBufCtx)
4119	{
4120	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
4121	if (pCmdBuf)
4122	{
4123	Assert(pCmdBufCtx->cSubmitted > 0);
4124	--pCmdBufCtx->cSubmitted;
4125	break;
4126	}
4127	}
4128	}
4129
4130	if (!pCmdBuf)
4131	{
4132	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
4133	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4134	break;
4135	}
4136
4137	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4138
4139	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
4140	uint32_t offNextCmd = 0;
4141	uint32_t u32IrqStatus = 0;
4142	uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
4143	? pCmdBuf->hdr.dxContext
4144	: SVGA3D_INVALID_ID;
4145	/* Process one buffer. */
4146	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
4147
4148	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
4149	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
4150	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
4151	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
4152
4153	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
4154	if (u32IrqStatus)
4155	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
4156
4157	vmsvgaR3CmdBufFree(pCmdBuf);
4158	}
4159	}
4160
4161
4162	/**
4163	* Worker for vmsvgaR3FifoThread that handles an external command.
4164	*
4165	* @param pDevIns The device instance.
4166	* @param pThis The shared VGA/VMSVGA instance data.
4167	* @param pThisCC The VGA/VMSVGA state for ring-3.
4168	*/
4169	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4170	{
4171	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
4172	switch (pThis->svga.u8FIFOExtCommand)
4173	{
4174	case VMSVGA_FIFO_EXTCMD_RESET:
4175	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
4176	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4177
4178	vmsvgaR3ResetScreens(pThis, pThisCC);
4179	# ifdef VBOX_WITH_VMSVGA3D
4180	/* The 3d subsystem must be reset from the fifo thread. */
4181	if (pThis->svga.f3DEnabled)
4182	vmsvga3dReset(pThisCC);
4183	# endif
4184	vmsvgaR3ResetSvgaState(pThis, pThisCC);
4185	break;
4186
4187	case VMSVGA_FIFO_EXTCMD_POWEROFF:
4188	Log(("vmsvgaR3FifoLoop: power off.\n"));
4189	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4190
4191	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
4192	vmsvgaR3ResetScreens(pThis, pThisCC);
4193	break;
4194
4195	case VMSVGA_FIFO_EXTCMD_TERMINATE:
4196	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
4197	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4198
4199	# ifdef VBOX_WITH_VMSVGA3D
4200	/* The 3d subsystem must be shut down from the fifo thread. */
4201	if (pThis->svga.f3DEnabled)
4202	vmsvga3dTerminate(pThisCC);
4203	# endif
4204	vmsvgaR3TerminateSvgaState(pThis, pThisCC);
4205	break;
4206
4207	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
4208	{
4209	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
4210	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
4211	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
4212	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
4213	# ifdef VBOX_WITH_VMSVGA3D
4214	if (pThis->svga.f3DEnabled)
4215	{
4216	if (vmsvga3dIsLegacyBackend(pThisCC))
4217	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
4218	# ifdef VMSVGA3D_DX
4219	else
4220	vmsvga3dDXSaveExec(pDevIns, pThisCC, pSSM);
4221	# endif
4222	}
4223	# endif
4224	break;
4225	}
4226
4227	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
4228	{
4229	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
4230	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
4231	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
4232	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4233	# ifdef VBOX_WITH_VMSVGA3D
4234	if (pThis->svga.f3DEnabled)
4235	{
4236	/* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
4237	# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
4238	/* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
4239	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
4240	# endif
4241
4242	if (vmsvga3dIsLegacyBackend(pThisCC))
4243	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4244	# ifdef VMSVGA3D_DX
4245	else
4246	vmsvga3dDXLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4247	# endif
4248	}
4249	# endif
4250	break;
4251	}
4252
4253	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
4254	{
4255	# ifdef VBOX_WITH_VMSVGA3D
4256	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
4257	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
4258	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
4259	# endif
4260	break;
4261	}
4262
4263
4264	default:
4265	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
4266	break;
4267	}
4268
4269	/*
4270	* Signal the end of the external command.
4271	*/
4272	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4273	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
4274	ASMMemoryFence(); /* paranoia^2 */
4275	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
4276	AssertLogRelRC(rc);
4277	}
4278
4279	/**
4280	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
4281	* doing a job on the FIFO thread (even when it's officially suspended).
4282	*
4283	* @returns VBox status code (fully asserted).
4284	* @param pDevIns The device instance.
4285	* @param pThis The shared VGA/VMSVGA instance data.
4286	* @param pThisCC The VGA/VMSVGA state for ring-3.
4287	* @param uExtCmd The command to execute on the FIFO thread.
4288	* @param pvParam Pointer to command parameters.
4289	* @param cMsWait The time to wait for the command, given in
4290	* milliseconds.
4291	*/
4292	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4293	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4294	{
4295	Assert(cMsWait >= RT_MS_1SEC * 5);
4296	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4297	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4298
4299	int rc;
4300	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4301	PDMTHREADSTATE enmState = pThread->enmState;
4302	if (enmState == PDMTHREADSTATE_SUSPENDED)
4303	{
4304	/*
4305	* The thread is suspended, we have to temporarily wake it up so it can
4306	* perform the task.
4307	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
4308	*/
4309	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4310	/* Post the request. */
4311	pThis->svga.fFifoExtCommandWakeup = true;
4312	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4313	pThis->svga.u8FIFOExtCommand = uExtCmd;
4314	ASMMemoryFence(); /* paranoia^3 */
4315
4316	/* Resume the thread. */
4317	rc = PDMDevHlpThreadResume(pDevIns, pThread);
4318	AssertLogRelRC(rc);
4319	if (RT_SUCCESS(rc))
4320	{
4321	/* Wait. Take care in case the semaphore was already posted (same as below). */
4322	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4323	if ( rc == VINF_SUCCESS
4324	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4325	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4326	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4327	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4328
4329	/* suspend the thread */
4330	pThis->svga.fFifoExtCommandWakeup = false;
4331	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4332	AssertLogRelRC(rc2);
4333	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4334	rc = rc2;
4335	}
4336	pThis->svga.fFifoExtCommandWakeup = false;
4337	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4338	}
4339	else if (enmState == PDMTHREADSTATE_RUNNING)
4340	{
4341	/*
4342	* The thread is running, should only happen during reset and vmsvga3dsfc.
4343	* We ASSUME not racing code here, both wrt thread state and ext commands.
4344	*/
4345	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4346	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4347
4348	/* Post the request. */
4349	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4350	pThis->svga.u8FIFOExtCommand = uExtCmd;
4351	ASMMemoryFence(); /* paranoia^2 */
4352	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4353	AssertLogRelRC(rc);
4354
4355	/* Wait. Take care in case the semaphore was already posted (same as above). */
4356	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4357	if ( rc == VINF_SUCCESS
4358	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4359	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4360	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4361	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4362
4363	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4364	}
4365	else
4366	{
4367	/*
4368	* Something is wrong with the thread!
4369	*/
4370	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4371	rc = VERR_INVALID_STATE;
4372	}
4373	return rc;
4374	}
4375
4376
4377	/**
4378	* Marks the FIFO non-busy, notifying any waiting EMTs.
4379	*
4380	* @param pDevIns The device instance.
4381	* @param pThis The shared VGA/VMSVGA instance data.
4382	* @param pThisCC The VGA/VMSVGA state for ring-3.
4383	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4384	* @param offFifoMin The start byte offset of the command FIFO.
4385	*/
4386	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4387	{
4388	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4389	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4390	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4391
4392	/* Wake up any waiting EMTs. */
4393	if (pSVGAState->cBusyDelayedEmts > 0)
4394	{
4395	# ifdef VMSVGA_USE_EMT_HALT_CODE
4396	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4397	if (idCpu != NIL_VMCPUID)
4398	{
4399	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4400	while (idCpu-- > 0)
4401	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4402	PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4403	}
4404	# else
4405	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4406	AssertRC(rc2);
4407	# endif
4408	}
4409	}
4410
4411	/**
4412	* Reads (more) payload into the command buffer.
4413	*
4414	* @returns pbBounceBuf on success
4415	* @retval (void *)1 if the thread was requested to stop.
4416	* @retval NULL on FIFO error.
4417	*
4418	* @param cbPayloadReq The number of bytes of payload requested.
4419	* @param pFIFO The FIFO.
4420	* @param offCurrentCmd The FIFO byte offset of the current command.
4421	* @param offFifoMin The start byte offset of the command FIFO.
4422	* @param offFifoMax The end byte offset of the command FIFO.
4423	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4424	* always sufficient size.
4425	* @param pcbAlreadyRead How much payload we've already read into the bounce
4426	* buffer. (We will NEVER re-read anything.)
4427	* @param pThread The calling PDM thread handle.
4428	* @param pThis The shared VGA/VMSVGA instance data.
4429	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4430	* statistics collection.
4431	* @param pDevIns The device instance.
4432	*/
4433	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4434	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4435	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4436	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4437	{
4438	Assert(pbBounceBuf);
4439	Assert(pcbAlreadyRead);
4440	Assert(offFifoMin < offFifoMax);
4441	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4442	Assert(offFifoMax <= pThis->svga.cbFIFO);
4443
4444	/*
4445	* Check if the requested payload size has already been satisfied .
4446	* .
4447	* When called to read more, the caller is responsible for making sure the .
4448	* new command size (cbRequsted) never is smaller than what has already .
4449	* been read.
4450	*/
4451	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4452	if (cbPayloadReq <= cbAlreadyRead)
4453	{
4454	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4455	return pbBounceBuf;
4456	}
4457
4458	/*
4459	* Commands bigger than the fifo buffer are invalid.
4460	*/
4461	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4462	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4463	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4464	NULL);
4465
4466	/*
4467	* Move offCurrentCmd past the command dword.
4468	*/
4469	offCurrentCmd += sizeof(uint32_t);
4470	if (offCurrentCmd >= offFifoMax)
4471	offCurrentCmd = offFifoMin;
4472
4473	/*
4474	* Do we have sufficient payload data available already?
4475	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4476	*/
4477	uint32_t cbAfter, cbBefore;
4478	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4479	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4480	if (offNextCmd >= offCurrentCmd)
4481	{
4482	if (RT_LIKELY(offNextCmd < offFifoMax))
4483	cbAfter = offNextCmd - offCurrentCmd;
4484	else
4485	{
4486	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4487	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4488	offNextCmd, offFifoMin, offFifoMax));
4489	cbAfter = offFifoMax - offCurrentCmd;
4490	}
4491	cbBefore = 0;
4492	}
4493	else
4494	{
4495	cbAfter = offFifoMax - offCurrentCmd;
4496	if (offNextCmd >= offFifoMin)
4497	cbBefore = offNextCmd - offFifoMin;
4498	else
4499	{
4500	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4501	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4502	offNextCmd, offFifoMin, offFifoMax));
4503	cbBefore = 0;
4504	}
4505	}
4506	if (cbAfter + cbBefore < cbPayloadReq)
4507	{
4508	/*
4509	* Insufficient, must wait for it to arrive.
4510	*/
4511	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4512	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4513	for (uint32_t i = 0;; i++)
4514	{
4515	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4516	{
4517	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4518	return (void *)(uintptr_t)1;
4519	}
4520	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4521	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4522
4523	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4524
4525	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4526	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4527	if (offNextCmd >= offCurrentCmd)
4528	{
4529	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4530	cbBefore = 0;
4531	}
4532	else
4533	{
4534	cbAfter = offFifoMax - offCurrentCmd;
4535	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4536	}
4537
4538	if (cbAfter + cbBefore >= cbPayloadReq)
4539	break;
4540	}
4541	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4542	}
4543
4544	/*
4545	* Copy out the memory and update what pcbAlreadyRead points to.
4546	*/
4547	if (cbAfter >= cbPayloadReq)
4548	memcpy(pbBounceBuf + cbAlreadyRead,
4549	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4550	cbPayloadReq - cbAlreadyRead);
4551	else
4552	{
4553	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4554	if (cbAlreadyRead < cbAfter)
4555	{
4556	memcpy(pbBounceBuf + cbAlreadyRead,
4557	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4558	cbAfter - cbAlreadyRead);
4559	cbAlreadyRead = cbAfter;
4560	}
4561	memcpy(pbBounceBuf + cbAlreadyRead,
4562	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4563	cbPayloadReq - cbAlreadyRead);
4564	}
4565	*pcbAlreadyRead = cbPayloadReq;
4566	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4567	return pbBounceBuf;
4568	}
4569
4570
4571	/**
4572	* Sends cursor position and visibility information from the FIFO to the front-end.
4573	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4574	*/
4575	static uint32_t
4576	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4577	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4578	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4579	{
4580	/*
4581	* Check if the cursor update counter has changed and try get a stable
4582	* set of values if it has. This is race-prone, especially consindering
4583	* the screen ID, but little we can do about that.
4584	*/
4585	uint32_t x, y, fVisible, idScreen;
4586	for (uint32_t i = 0; ; i++)
4587	{
4588	x = pFIFO[SVGA_FIFO_CURSOR_X];
4589	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4590	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4591	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4592	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4593	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4594	\|\| i > 3)
4595	break;
4596	if (i == 0)
4597	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4598	ASMNopPause();
4599	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4600	}
4601
4602	/*
4603	* Check if anything has changed, as calling into pDrv is not light-weight.
4604	*/
4605	if ( *pxLast == x
4606	&& *pyLast == y
4607	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4608	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4609	else
4610	{
4611	/*
4612	* Detected changes.
4613	*
4614	* We handle global, not per-screen visibility information by sending
4615	* pfnVBVAMousePointerShape without shape data.
4616	*/
4617	*pxLast = x;
4618	*pyLast = y;
4619	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4620	if (idScreen != SVGA_ID_INVALID)
4621	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4622	else if (*pfLastVisible != fVisible)
4623	{
4624	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4625	*pfLastVisible = fVisible;
4626	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4627	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4628	}
4629	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4630	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4631	}
4632
4633	/*
4634	* Update done. Signal this to the guest.
4635	*/
4636	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4637
4638	return uCursorUpdateCount;
4639	}
4640
4641
4642	/**
4643	* Checks if there is work to be done, either cursor updating or FIFO commands.
4644	*
4645	* @returns true if pending work, false if not.
4646	* @param pThisCC The VGA/VMSVGA state for ring-3.
4647	* @param uLastCursorCount The last cursor update counter value.
4648	*/
4649	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4650	{
4651	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4652	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4653	AssertReturn(pFIFO, false);
4654
4655	if (vmsvgaR3CmdBufHasWork(pThisCC))
4656	return true;
4657
4658	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4659	return true;
4660
4661	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4662	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4663	return true;
4664
4665	return false;
4666	}
4667
4668
4669	/**
4670	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4671	*
4672	* @param pDevIns The device instance.
4673	* @param pThis The shared VGA/VMSVGA instance data.
4674	* @param pThisCC The VGA/VMSVGA state for ring-3.
4675	*/
4676	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4677	{
4678	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4679	to recheck it before doing the signalling. */
4680	if ( (pThis->fVmSvga3 \|\| vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount)))
4681	&& pThis->svga.fFIFOThreadSleeping
4682	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4683	{
4684	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4685	AssertRC(rc);
4686	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4687	}
4688	}
4689
4690
4691	/**
4692	* Called by the FIFO thread to process pending actions.
4693	*
4694	* @param pDevIns The device instance.
4695	* @param pThis The shared VGA/VMSVGA instance data.
4696	* @param pThisCC The VGA/VMSVGA state for ring-3.
4697	*/
4698	static void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4699	{
4700	RT_NOREF(pDevIns);
4701
4702	/* Currently just mode changes. */
4703	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4704	{
4705	vmsvgaR3ChangeMode(pThis, pThisCC);
4706	# ifdef VBOX_WITH_VMSVGA3D
4707	if (pThisCC->svga.p3dState != NULL)
4708	vmsvga3dChangeMode(pThisCC);
4709	# endif
4710	}
4711	}
4712
4713
4714	/*
4715	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4716	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4717	*/
4718	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4719	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4720	*
4721	* Will break out of the switch on failure.
4722	* Will restart and quit the loop if the thread was requested to stop.
4723	*
4724	* @param a_PtrVar Request variable pointer.
4725	* @param a_Type Request typedef (not pointer) for casting.
4726	* @param a_cbPayloadReq How much payload to fetch.
4727	* @remarks Accesses a bunch of variables in the current scope!
4728	*/
4729	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4730	if (1) { \
4731	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4732	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4733	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4734	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4735	} else do {} while (0)
4736	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4737	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4738	* buffer after figuring out the actual command size.
4739	*
4740	* Will break out of the switch on failure.
4741	*
4742	* @param a_PtrVar Request variable pointer.
4743	* @param a_Type Request typedef (not pointer) for casting.
4744	* @param a_cbPayloadReq How much payload to fetch.
4745	* @remarks Accesses a bunch of variables in the current scope!
4746	*/
4747	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4748	if (1) { \
4749	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4750	} else do {} while (0)
4751
4752	/**
4753	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4754	*/
4755	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4756	{
4757	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4758	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4759	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4760	int rc;
4761
4762	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4763	return VINF_SUCCESS;
4764
4765	/*
4766	* Special mode where we only execute an external command and the go back
4767	* to being suspended. Currently, all ext cmds ends up here, with the reset
4768	* one also being eligble for runtime execution further down as well.
4769	*/
4770	if (pThis->svga.fFifoExtCommandWakeup)
4771	{
4772	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4773	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4774	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4775	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4776	else
4777	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4778	return VINF_SUCCESS;
4779	}
4780
4781
4782	/*
4783	* Signal the semaphore to make sure we don't wait for 250ms after a
4784	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4785	*/
4786	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4787
4788	/*
4789	* Allocate a bounce buffer for command we get from the FIFO.
4790	* (All code must return via the end of the function to free this buffer.)
4791	*/
4792	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4793	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4794
4795	/*
4796	* Polling/sleep interval config.
4797	*
4798	* We wait for an a short interval if the guest has recently given us work
4799	* to do, but the interval increases the longer we're kept idle. Once we've
4800	* reached the refresh timer interval, we'll switch to extended waits,
4801	* depending on it or the guest to kick us into action when needed.
4802	*
4803	* Should the refresh time go fishing, we'll just continue increasing the
4804	* sleep length till we reaches the 250 ms max after about 16 seconds.
4805	*/
4806	RTMSINTERVAL const cMsMinSleep = 16;
4807	RTMSINTERVAL const cMsIncSleep = 2;
4808	RTMSINTERVAL const cMsMaxSleep = 250;
4809	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4810	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4811
4812	/*
4813	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4814	*
4815	* Initialize with values that will detect an update from the guest.
4816	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4817	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4818	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4819	*/
4820	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4821	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4822	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4823	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4824	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4825
4826	/*
4827	* The FIFO loop.
4828	*/
4829	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4830	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4831	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4832	{
4833	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4834	/*
4835	* Should service the run loop every so often.
4836	*/
4837	if (pThis->svga.f3DEnabled)
4838	vmsvga3dCocoaServiceRunLoop();
4839	# endif
4840
4841	/* First check any pending actions. */
4842	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4843
4844	/*
4845	* Unless there's already work pending, go to sleep for a short while.
4846	* (See polling/sleep interval config above.)
4847	*/
4848	if ( fBadOrDisabledFifo
4849	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4850	{
4851	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4852	Assert(pThis->cMilliesRefreshInterval > 0);
4853	if (cMsSleep < pThis->cMilliesRefreshInterval)
4854	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4855	else
4856	{
4857	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4858	int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4859	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4860	# endif
4861	if ( !fBadOrDisabledFifo
4862	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4863	rc = VINF_SUCCESS;
4864	else
4865	{
4866	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4867	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4868	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4869	}
4870	}
4871	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4872	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4873	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4874	{
4875	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4876	break;
4877	}
4878	}
4879	else
4880	rc = VINF_SUCCESS;
4881	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4882	if (rc == VERR_TIMEOUT)
4883	{
4884	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4885	{
4886	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4887	continue;
4888	}
4889	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4890
4891	Log(("vmsvgaR3FifoLoop: timeout\n"));
4892	}
4893	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4894	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4895	cMsSleep = cMsMinSleep;
4896
4897	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4898	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4899	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4900
4901	/*
4902	* Handle external commands (currently only reset).
4903	*/
4904	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4905	{
4906	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4907	continue;
4908	}
4909
4910	/*
4911	* If guest misbehaves, then do nothing.
4912	*/
4913	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4914	{
4915	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4916	cMsSleep = cMsExtendedSleep;
4917	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4918	continue;
4919	}
4920
4921	/*
4922	* The device must be enabled and configured.
4923	*/
4924	if ( !pThis->svga.fEnabled
4925	\|\| !pThis->svga.fConfigured)
4926	{
4927	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4928	fBadOrDisabledFifo = true;
4929	cMsSleep = cMsMaxSleep; /* cheat */
4930	continue;
4931	}
4932
4933	/*
4934	* Get and check the min/max values. We ASSUME that they will remain
4935	* unchanged while we process requests. A further ASSUMPTION is that
4936	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4937	* we don't read it back while in the loop.
4938	*/
4939	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4940	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4941	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4942	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4943	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4944	\|\| offFifoMax <= offFifoMin
4945	\|\| offFifoMax > pThis->svga.cbFIFO
4946	\|\| (offFifoMax & 3) != 0
4947	\|\| (offFifoMin & 3) != 0
4948	\|\| offCurrentCmd < offFifoMin
4949	\|\| offCurrentCmd > offFifoMax))
4950	{
4951	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4952	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4953	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4954	fBadOrDisabledFifo = true;
4955	continue;
4956	}
4957	RT_UNTRUSTED_VALIDATED_FENCE();
4958	if (RT_UNLIKELY(offCurrentCmd & 3))
4959	{
4960	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4961	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4962	offCurrentCmd &= ~UINT32_C(3);
4963	}
4964
4965	/*
4966	* Update the cursor position before we start on the FIFO commands.
4967	*/
4968	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4969	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4970	{
4971	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4972	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4973	{ /* halfways likely */ }
4974	else
4975	{
4976	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4977	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4978	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4979	}
4980	}
4981
4982	/*
4983	* Mark the FIFO as busy.
4984	*/
4985	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4986	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4987	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4988
4989	/*
4990	* Process all submitted command buffers.
4991	*/
4992	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4993
4994	/*
4995	* Execute all queued FIFO commands.
4996	* Quit if pending external command or changes in the thread state.
4997	*/
4998	bool fDone = false;
4999	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
5000	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
5001	{
5002	uint32_t cbPayload = 0;
5003	uint32_t u32IrqStatus = 0;
5004
5005	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
5006
5007	/* First check any pending actions. */
5008	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
5009
5010	/* Check for pending external commands (reset). */
5011	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
5012	break;
5013
5014	/*
5015	* Process the command.
5016	*/
5017	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
5018	* warning. Because we implement some obsolete and deprecated commands, which are not included in
5019	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
5020	*/
5021	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
5022	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
5023	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
5024	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
5025	switch (enmCmdId)
5026	{
5027	case SVGA_CMD_INVALID_CMD:
5028	/* Nothing to do. */
5029	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
5030	break;
5031
5032	case SVGA_CMD_FENCE:
5033	{
5034	SVGAFifoCmdFence *pCmdFence;
5035	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
5036	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
5037	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
5038	{
5039	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
5040	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
5041
5042	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
5043	{
5044	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
5045	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
5046	}
5047	else
5048	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
5049	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
5050	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
5051	{
5052	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
5053	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
5054	}
5055	}
5056	else
5057	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
5058	break;
5059	}
5060
5061	case SVGA_CMD_UPDATE:
5062	{
5063	SVGAFifoCmdUpdate *pCmd;
5064	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
5065	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
5066	break;
5067	}
5068
5069	case SVGA_CMD_UPDATE_VERBOSE:
5070	{
5071	SVGAFifoCmdUpdateVerbose *pCmd;
5072	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
5073	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
5074	break;
5075	}
5076
5077	case SVGA_CMD_DEFINE_CURSOR:
5078	{
5079	/* Followed by bitmap data. */
5080	SVGAFifoCmdDefineCursor *pCmd;
5081	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
5082
5083	/* Figure out the size of the bitmap data. */
5084	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
5085	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
5086	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
5087	RT_UNTRUSTED_VALIDATED_FENCE();
5088
5089	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
5090	uint32_t const cbAndMask = cbAndLine * pCmd->height;
5091	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
5092	uint32_t const cbXorMask = cbXorLine * pCmd->height;
5093
5094	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
5095	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
5096	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
5097	break;
5098	}
5099
5100	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
5101	{
5102	/* Followed by bitmap data. */
5103	SVGAFifoCmdDefineAlphaCursor *pCmd;
5104	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
5105
5106	/* Figure out the size of the bitmap data. */
5107	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
5108
5109	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
5110	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
5111	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
5112	break;
5113	}
5114
5115	case SVGA_CMD_MOVE_CURSOR:
5116	{
5117	/* Deprecated; there should be no driver which requires this command. However, if
5118	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
5119	* alignment.
5120	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5121	*/
5122	SVGAFifoCmdMoveCursor *pCmd;
5123	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
5124	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
5125	break;
5126	}
5127
5128	case SVGA_CMD_DISPLAY_CURSOR:
5129	{
5130	/* Deprecated; there should be no driver which requires this command. However, if
5131	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
5132	* alignment.
5133	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
5134	*/
5135	SVGAFifoCmdDisplayCursor *pCmd;
5136	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
5137	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
5138	break;
5139	}
5140
5141	case SVGA_CMD_RECT_FILL:
5142	{
5143	SVGAFifoCmdRectFill *pCmd;
5144	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
5145	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
5146	break;
5147	}
5148
5149	case SVGA_CMD_RECT_COPY:
5150	{
5151	SVGAFifoCmdRectCopy *pCmd;
5152	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
5153	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
5154	break;
5155	}
5156
5157	case SVGA_CMD_RECT_ROP_COPY:
5158	{
5159	SVGAFifoCmdRectRopCopy *pCmd;
5160	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
5161	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
5162	break;
5163	}
5164
5165	case SVGA_CMD_ESCAPE:
5166	{
5167	/* Followed by 'size' bytes of data. */
5168	SVGAFifoCmdEscape *pCmd;
5169	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
5170
5171	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
5172	RT_UNTRUSTED_VALIDATED_FENCE();
5173
5174	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
5175	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
5176	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
5177	break;
5178	}
5179	# ifdef VBOX_WITH_VMSVGA3D
5180	case SVGA_CMD_DEFINE_GMR2:
5181	{
5182	SVGAFifoCmdDefineGMR2 *pCmd;
5183	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
5184	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
5185	break;
5186	}
5187
5188	case SVGA_CMD_REMAP_GMR2:
5189	{
5190	/* Followed by page descriptors or guest ptr. */
5191	SVGAFifoCmdRemapGMR2 *pCmd;
5192	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
5193
5194	/* Calculate the size of what comes after next and fetch it. */
5195	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
5196	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
5197	cbCmd += sizeof(SVGAGuestPtr);
5198	else
5199	{
5200	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
5201	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
5202	{
5203	cbCmd += cbPageDesc;
5204	pCmd->numPages = 1;
5205	}
5206	else
5207	{
5208	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
5209	cbCmd += cbPageDesc * pCmd->numPages;
5210	}
5211	}
5212	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
5213	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
5214	# ifdef DEBUG_GMR_ACCESS
5215	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
5216	# endif
5217	break;
5218	}
5219	# endif // VBOX_WITH_VMSVGA3D
5220	case SVGA_CMD_DEFINE_SCREEN:
5221	{
5222	/* The size of this command is specified by the guest and depends on capabilities. */
5223	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
5224
5225	SVGAFifoCmdDefineScreen *pCmd;
5226	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
5227	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
5228	RT_UNTRUSTED_VALIDATED_FENCE();
5229
5230	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
5231	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
5232	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
5233	break;
5234	}
5235
5236	case SVGA_CMD_DESTROY_SCREEN:
5237	{
5238	SVGAFifoCmdDestroyScreen *pCmd;
5239	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
5240	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
5241	break;
5242	}
5243
5244	case SVGA_CMD_DEFINE_GMRFB:
5245	{
5246	SVGAFifoCmdDefineGMRFB *pCmd;
5247	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
5248	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
5249	break;
5250	}
5251
5252	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
5253	{
5254	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
5255	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
5256	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
5257	break;
5258	}
5259
5260	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
5261	{
5262	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
5263	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
5264	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
5265	break;
5266	}
5267
5268	case SVGA_CMD_ANNOTATION_FILL:
5269	{
5270	SVGAFifoCmdAnnotationFill *pCmd;
5271	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
5272	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
5273	break;
5274	}
5275
5276	case SVGA_CMD_ANNOTATION_COPY:
5277	{
5278	SVGAFifoCmdAnnotationCopy *pCmd;
5279	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
5280	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
5281	break;
5282	}
5283
5284	default:
5285	# ifdef VBOX_WITH_VMSVGA3D
5286	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
5287	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
5288	{
5289	RT_UNTRUSTED_VALIDATED_FENCE();
5290
5291	/* All 3d commands start with a common header, which defines the identifier and the size
5292	* of the command. The identifier has been already read from FIFO. Fetch the size.
5293	*/
5294	uint32_t *pcbCmd;
5295	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
5296	uint32_t const cbCmd = *pcbCmd;
5297	AssertBreak(cbCmd < pThis->svga.cbFIFO);
5298	uint32_t *pu32Cmd;
5299	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
5300	pu32Cmd++; /* Skip the command size. */
5301
5302	if (RT_LIKELY(pThis->svga.f3DEnabled))
5303	{ /* likely */ }
5304	else
5305	{
5306	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
5307	break;
5308	}
5309
5310	vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
5311	}
5312	else
5313	# endif // VBOX_WITH_VMSVGA3D
5314	{
5315	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5316	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5317	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
5318	}
5319	}
5320
5321	/* Go to the next slot */
5322	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5323	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5324	if (offCurrentCmd >= offFifoMax)
5325	{
5326	offCurrentCmd -= offFifoMax - offFifoMin;
5327	Assert(offCurrentCmd >= offFifoMin);
5328	Assert(offCurrentCmd < offFifoMax);
5329	}
5330	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5331	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5332
5333	/*
5334	* Raise IRQ if required. Must enter the critical section here
5335	* before making final decisions here, otherwise cubebench and
5336	* others may end up waiting forever.
5337	*/
5338	if ( u32IrqStatus
5339	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5340	{
5341	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5342	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
5343
5344	/* FIFO progress might trigger an interrupt. */
5345	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5346	{
5347	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5348	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5349	}
5350
5351	/* Unmasked IRQ pending? */
5352	if (pThis->svga.u32IrqMask & u32IrqStatus)
5353	{
5354	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5355	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5356	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5357	}
5358
5359	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5360	}
5361	}
5362
5363	/* If really done, clear the busy flag. */
5364	if (fDone)
5365	{
5366	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5367	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5368	}
5369	}
5370
5371	/*
5372	* Free the bounce buffer. (There are no returns above!)
5373	*/
5374	RTMemFree(pbBounceBuf);
5375
5376	return VINF_SUCCESS;
5377	}
5378
5379	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5380	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5381
5382	/**
5383	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
5384	*/
5385	static DECLCALLBACK(int) vmsvgaR3CmdBufLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5386	{
5387	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5388	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5389	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5390	int rc;
5391
5392	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5393	return VINF_SUCCESS;
5394
5395	/*
5396	* Special mode where we only execute an external command and the go back
5397	* to being suspended. Currently, all ext cmds ends up here, with the reset
5398	* one also being eligble for runtime execution further down as well.
5399	*/
5400	if (pThis->svga.fFifoExtCommandWakeup)
5401	{
5402	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
5403	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5404	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
5405	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
5406	else
5407	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
5408	return VINF_SUCCESS;
5409	}
5410
5411
5412	/*
5413	* Signal the semaphore to make sure we don't wait for 250ms after a
5414	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
5415	*/
5416	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5417
5418	/*
5419	* Polling/sleep interval config.
5420	*
5421	* We wait for an a short interval if the guest has recently given us work
5422	* to do, but the interval increases the longer we're kept idle. Once we've
5423	* reached the refresh timer interval, we'll switch to extended waits,
5424	* depending on it or the guest to kick us into action when needed.
5425	*
5426	* Should the refresh time go fishing, we'll just continue increasing the
5427	* sleep length till we reaches the 250 ms max after about 16 seconds.
5428	*/
5429	RTMSINTERVAL const cMsMinSleep = 16;
5430	RTMSINTERVAL const cMsMaxSleep = 250;
5431	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
5432	RTMSINTERVAL cMsSleep = cMsMaxSleep;
5433
5434	/*
5435	* The FIFO loop.
5436	*/
5437	LogFlow(("vmsvgaR3CmdBufLoop: started loop\n"));
5438	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
5439	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5440	{
5441	/* First check any pending actions. */
5442	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
5443
5444	/*
5445	* Unless there's already work pending, go to sleep for a short while.
5446	* (See polling/sleep interval config above.)
5447	*/
5448	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
5449	Assert(pThis->cMilliesRefreshInterval > 0);
5450	if (cMsSleep < pThis->cMilliesRefreshInterval)
5451	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
5452	else
5453	{
5454	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
5455	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
5456	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
5457	}
5458	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
5459	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
5460	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
5461	{
5462	LogFlow(("vmsvgaR3CmdBufLoop: thread state %x\n", pThread->enmState));
5463	break;
5464	}
5465
5466	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
5467	cMsSleep = cMsMinSleep;
5468
5469	Log(("vmsvgaR3CmdBufLoop: enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
5470
5471	/*
5472	* Handle external commands (currently only reset).
5473	*/
5474	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
5475	{
5476	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
5477	continue;
5478	}
5479
5480	/*
5481	* If guest misbehaves, then do nothing.
5482	*/
5483	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
5484	{
5485	cMsSleep = cMsExtendedSleep;
5486	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
5487	continue;
5488	}
5489
5490	/*
5491	* The device must be enabled and configured.
5492	*/
5493	if ( !pThis->svga.fEnabled
5494	\|\| !pThis->svga.fConfigured)
5495	{
5496	fBadOrDisabledFifo = true;
5497	cMsSleep = cMsMaxSleep; /* cheat */
5498	continue;
5499	}
5500
5501	/*
5502	* Process all submitted command buffers.
5503	*/
5504	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
5505	}
5506
5507	return VINF_SUCCESS;
5508	}
5509
5510
5511	/**
5512	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5513	* Unblock the FIFO I/O thread so it can respond to a state change.}
5514	*/
5515	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5516	{
5517	RT_NOREF(pDevIns);
5518	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5519	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5520	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5521	}
5522
5523	/**
5524	* Enables or disables dirty page tracking for the framebuffer
5525	*
5526	* @param pDevIns The device instance.
5527	* @param pThis The shared VGA/VMSVGA instance data.
5528	* @param fTraces Enable/disable traces
5529	*/
5530	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5531	{
5532	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5533	&& !fTraces)
5534	{
5535	//Assert(pThis->svga.fTraces);
5536	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5537	return;
5538	}
5539
5540	pThis->svga.fTraces = fTraces;
5541	if (pThis->svga.fTraces)
5542	{
5543	unsigned cbFrameBuffer = pThis->vram_size;
5544
5545	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5546	/** @todo How does this work with screens? */
5547	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5548	{
5549	# if 0 //ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5550	Assert(pThis->svga.cbScanline);
5551	# endif
5552	/* Hardware enabled; return real framebuffer size .*/
5553	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5554	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, GUEST_PAGE_SIZE);
5555	}
5556
5557	if (!pThis->svga.fVRAMTracking)
5558	{
5559	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5560	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5561	pThis->svga.fVRAMTracking = true;
5562	}
5563	}
5564	else
5565	{
5566	if (pThis->svga.fVRAMTracking)
5567	{
5568	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5569	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5570	pThis->svga.fVRAMTracking = false;
5571	}
5572	}
5573	}
5574
5575	/**
5576	* @callback_method_impl{FNPCIIOREGIONMAP}
5577	*/
5578	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5579	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5580	{
5581	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5582	int rc;
5583	RT_NOREF(pPciDev);
5584	Assert(pPciDev == pDevIns->apPciDevs[0]);
5585
5586	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5587	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5588	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5589	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5590	, VERR_INTERNAL_ERROR);
5591	if (GCPhysAddress != NIL_RTGCPHYS)
5592	{
5593	/*
5594	* Mapping the FIFO RAM.
5595	*/
5596	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5597	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5598	AssertRC(rc);
5599
5600	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5601	if (RT_SUCCESS(rc))
5602	{
5603	rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, GCPhysAddress,
5604	# ifdef DEBUG_FIFO_ACCESS
5605	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5606	# else
5607	GCPhysAddress + GUEST_PAGE_SIZE - 1,
5608	# endif
5609	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5610	"VMSVGA FIFO");
5611	AssertRC(rc);
5612	}
5613	# endif
5614	if (RT_SUCCESS(rc))
5615	{
5616	pThis->svga.GCPhysFIFO = GCPhysAddress;
5617	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5618	}
5619	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5620	}
5621	else
5622	{
5623	Assert(pThis->svga.GCPhysFIFO);
5624	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5625	rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pThis->svga.GCPhysFIFO);
5626	AssertRC(rc);
5627	# else
5628	rc = VINF_SUCCESS;
5629	# endif
5630	pThis->svga.GCPhysFIFO = 0;
5631	}
5632	return rc;
5633	}
5634
5635	# ifdef VBOX_WITH_VMSVGA3D
5636
5637	/**
5638	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5639	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5640	*
5641	* @param pDevIns The device instance.
5642	* @param pThis The The shared VGA/VMSVGA instance data.
5643	* @param pThisCC The VGA/VMSVGA state for ring-3.
5644	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5645	* UINT32_MAX is used, all surfaces are processed.
5646	*/
5647	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5648	{
5649	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5650	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5651	}
5652
5653
5654	/**
5655	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5656	*/
5657	static DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5658	{
5659	/* There might be a specific surface ID at the start of the
5660	arguments, if not show all surfaces. */
5661	uint32_t sid = UINT32_MAX;
5662	if (pszArgs)
5663	pszArgs = RTStrStripL(pszArgs);
5664	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5665	sid = RTStrToUInt32(pszArgs);
5666
5667	/* Verbose or terse display, we default to verbose. */
5668	bool fVerbose = true;
5669	if (RTStrIStr(pszArgs, "terse"))
5670	fVerbose = false;
5671
5672	/* The size of the ascii art (x direction, y is 3/4 of x). */
5673	uint32_t cxAscii = 80;
5674	if (RTStrIStr(pszArgs, "gigantic"))
5675	cxAscii = 300;
5676	else if (RTStrIStr(pszArgs, "huge"))
5677	cxAscii = 180;
5678	else if (RTStrIStr(pszArgs, "big"))
5679	cxAscii = 132;
5680	else if (RTStrIStr(pszArgs, "normal"))
5681	cxAscii = 80;
5682	else if (RTStrIStr(pszArgs, "medium"))
5683	cxAscii = 64;
5684	else if (RTStrIStr(pszArgs, "small"))
5685	cxAscii = 48;
5686	else if (RTStrIStr(pszArgs, "tiny"))
5687	cxAscii = 24;
5688
5689	/* Y invert the image when producing the ASCII art. */
5690	bool fInvY = false;
5691	if (RTStrIStr(pszArgs, "invy"))
5692	fInvY = true;
5693
5694	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5695	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5696	}
5697
5698
5699	/**
5700	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5701	*/
5702	static DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5703	{
5704	/* pszArg = "sid[>dir]"
5705	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5706	*/
5707	char *pszBitmapPath = NULL;
5708	uint32_t sid = UINT32_MAX;
5709	if (pszArgs)
5710	pszArgs = RTStrStripL(pszArgs);
5711	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5712	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5713	if ( pszBitmapPath
5714	&& *pszBitmapPath == '>')
5715	++pszBitmapPath;
5716
5717	const bool fVerbose = true;
5718	const uint32_t cxAscii = 0; /* No ASCII */
5719	const bool fInvY = false; /* Do not invert. */
5720	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5721	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5722	}
5723
5724	/**
5725	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5726	*/
5727	static DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5728	{
5729	/* There might be a specific surface ID at the start of the
5730	arguments, if not show all contexts. */
5731	uint32_t sid = UINT32_MAX;
5732	if (pszArgs)
5733	pszArgs = RTStrStripL(pszArgs);
5734	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5735	sid = RTStrToUInt32(pszArgs);
5736
5737	/* Verbose or terse display, we default to verbose. */
5738	bool fVerbose = true;
5739	if (RTStrIStr(pszArgs, "terse"))
5740	fVerbose = false;
5741
5742	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5743	}
5744	# endif /* VBOX_WITH_VMSVGA3D */
5745
5746	/**
5747	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5748	*/
5749	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5750	{
5751	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5752	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5753	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5754	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5755	RT_NOREF(pszArgs);
5756
5757	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5758	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5759	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5760	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5761	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5762	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5763	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5764	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5765	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5766	if (pFIFO)
5767	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5768	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5769	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5770	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5771	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5772	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5773	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO ? pFIFO[SVGA_FIFO_PITCHLOCK] : 0);
5774	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5775	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5776	pHlp->pfnPrintf(pHlp, "Device Cap2: %#x\n", pThis->svga.u32DeviceCaps2);
5777	pHlp->pfnPrintf(pHlp, "Guest driver id: %#x\n", pThis->svga.u32GuestDriverId);
5778	pHlp->pfnPrintf(pHlp, "Guest driver ver1: %#x\n", pThis->svga.u32GuestDriverVer1);
5779	pHlp->pfnPrintf(pHlp, "Guest driver ver2: %#x\n", pThis->svga.u32GuestDriverVer2);
5780	pHlp->pfnPrintf(pHlp, "Guest driver ver3: %#x\n", pThis->svga.u32GuestDriverVer3);
5781	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5782	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5783	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5784	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5785	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5786	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5787	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5788
5789	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5790	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5791	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5792	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5793	if (pFIFO)
5794	{
5795	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5796	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5797	}
5798	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5799	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5800
5801	# ifdef VBOX_WITH_VMSVGA3D
5802	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5803	# endif
5804	if (pThisCC->pDrv)
5805	{
5806	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5807	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5808	}
5809
5810	/* Dump screen information. */
5811	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5812	{
5813	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5814	if (pScreen)
5815	{
5816	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5817	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5818	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5819	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5820	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5821	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5822	{
5823	pHlp->pfnPrintf(pHlp, " (");
5824	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5825	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5826	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5827	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5828	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5829	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5830	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5831	pHlp->pfnPrintf(pHlp, " BLANKING");
5832	pHlp->pfnPrintf(pHlp, " )");
5833	}
5834	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5835	}
5836	}
5837
5838	}
5839
5840	static int vmsvgaR3LoadBufCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx, SVGACBContext CBCtx)
5841	{
5842	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5843	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5844
5845	uint32_t cSubmitted;
5846	int rc = pHlp->pfnSSMGetU32(pSSM, &cSubmitted);
5847	AssertLogRelRCReturn(rc, rc);
5848
5849	for (uint32_t i = 0; i < cSubmitted; ++i)
5850	{
5851	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pBufCtx);
5852	AssertPtrReturn(pCmdBuf, VERR_NO_MEMORY);
5853
5854	pHlp->pfnSSMGetGCPhys(pSSM, &pCmdBuf->GCPhysCB);
5855
5856	uint32_t u32;
5857	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5858	AssertRCReturn(rc, rc);
5859	AssertReturn(u32 == sizeof(SVGACBHeader), VERR_INVALID_STATE);
5860	pHlp->pfnSSMGetMem(pSSM, &pCmdBuf->hdr, sizeof(SVGACBHeader));
5861
5862	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5863	AssertRCReturn(rc, rc);
5864	AssertReturn(u32 == pCmdBuf->hdr.length, VERR_INVALID_STATE);
5865
5866	if (pCmdBuf->hdr.length)
5867	{
5868	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
5869	AssertPtrReturn(pCmdBuf->pvCommands, VERR_NO_MEMORY);
5870
5871	rc = pHlp->pfnSSMGetMem(pSSM, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
5872	AssertRCReturn(rc, rc);
5873	}
5874
5875	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
5876	{
5877	vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
5878	}
5879	else
5880	{
5881	uint32_t offNextCmd = 0;
5882	vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
5883	}
5884
5885	/* Free the buffer if CmdBufSubmit* did not consume it. */
5886	vmsvgaR3CmdBufFree(pCmdBuf);
5887	}
5888	return rc;
5889	}
5890
5891	static int vmsvgaR3LoadCommandBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5892	{
5893	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5894	PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
5895
5896	bool f;
5897	uint32_t u32;
5898
5899	/* Device context command buffers. */
5900	int rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, &pSvgaR3State->CmdBufCtxDC, SVGA_CB_CONTEXT_MAX);
5901	AssertLogRelRCReturn(rc, rc);
5902
5903	/* DX contexts command buffers. */
5904	uint32_t cBufCtx;
5905	rc = pHlp->pfnSSMGetU32(pSSM, &cBufCtx);
5906	AssertLogRelRCReturn(rc, rc);
5907	AssertReturn(cBufCtx == RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs), VERR_INVALID_STATE);
5908	for (uint32_t j = 0; j < cBufCtx; ++j)
5909	{
5910	rc = pHlp->pfnSSMGetBool(pSSM, &f);
5911	AssertLogRelRCReturn(rc, rc);
5912	if (f)
5913	{
5914	pSvgaR3State->apCmdBufCtxs[j] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
5915	AssertPtrReturn(pSvgaR3State->apCmdBufCtxs[j], VERR_NO_MEMORY);
5916	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[j]);
5917
5918	rc = vmsvgaR3LoadBufCtx(pDevIns, pThis, pThisCC, pSSM, pSvgaR3State->apCmdBufCtxs[j], (SVGACBContext)j);
5919	AssertLogRelRCReturn(rc, rc);
5920	}
5921	}
5922
5923	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5924	pSvgaR3State->fCmdBuf = u32;
5925	return rc;
5926	}
5927
5928	static int vmsvgaR3LoadGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
5929	{
5930	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5931
5932	int rc;
5933	pHlp->pfnSSMGetU32(pSSM, &pGbo->fGboFlags);
5934	pHlp->pfnSSMGetU32(pSSM, &pGbo->cTotalPages);
5935	pHlp->pfnSSMGetU32(pSSM, &pGbo->cbTotal);
5936	rc = pHlp->pfnSSMGetU32(pSSM, &pGbo->cDescriptors);
5937	AssertRCReturn(rc, rc);
5938
5939	if (pGbo->cDescriptors)
5940	{
5941	pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAllocZ(pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
5942	AssertPtrReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
5943	}
5944
5945	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
5946	{
5947	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
5948	pHlp->pfnSSMGetGCPhys(pSSM, &pDesc->GCPhys);
5949	rc = pHlp->pfnSSMGetU64(pSSM, &pDesc->cPages);
5950	}
5951
5952	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
5953	{
5954	pGbo->pvHost = RTMemAlloc(pGbo->cbTotal);
5955	AssertPtrReturn(pGbo->pvHost, VERR_NO_MEMORY);
5956	rc = pHlp->pfnSSMGetMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
5957	}
5958
5959	return rc;
5960	}
5961
5962	/**
5963	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5964	*/
5965	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5966	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5967	{
5968	RT_NOREF(uPass);
5969
5970	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5971	int rc;
5972
5973	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5974	{
5975	uint32_t cScreens = 0;
5976	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5977	AssertRCReturn(rc, rc);
5978	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5979	("cScreens=%#x\n", cScreens),
5980	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5981
5982	for (uint32_t i = 0; i < cScreens; ++i)
5983	{
5984	VMSVGASCREENOBJECT screen;
5985	RT_ZERO(screen);
5986
5987	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5988	AssertLogRelRCReturn(rc, rc);
5989
5990	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5991	{
5992	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5993	*pScreen = screen;
5994	pScreen->fModified = true;
5995
5996	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
5997	{
5998	uint32_t u32;
5999	pHlp->pfnSSMGetU32(pSSM, &u32); /* Size of screen bitmap. */
6000	AssertLogRelRCReturn(rc, rc);
6001	if (u32)
6002	{
6003	pScreen->pvScreenBitmap = RTMemAlloc(u32);
6004	AssertPtrReturn(pScreen->pvScreenBitmap, VERR_NO_MEMORY);
6005
6006	pHlp->pfnSSMGetMem(pSSM, pScreen->pvScreenBitmap, u32);
6007	}
6008	}
6009	}
6010	else
6011	{
6012	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
6013	}
6014	}
6015	}
6016	else
6017	{
6018	/* Try to setup at least the first screen. */
6019	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
6020	Assert(pScreen->idScreen == 0);
6021	pScreen->fDefined = true;
6022	pScreen->fModified = true;
6023	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
6024	pScreen->xOrigin = 0;
6025	pScreen->yOrigin = 0;
6026	pScreen->offVRAM = pThis->svga.uScreenOffset;
6027	pScreen->cbPitch = pThis->svga.cbScanline;
6028	pScreen->cWidth = pThis->svga.uWidth;
6029	pScreen->cHeight = pThis->svga.uHeight;
6030	pScreen->cBpp = pThis->svga.uBpp;
6031	}
6032
6033	return VINF_SUCCESS;
6034	}
6035
6036	/**
6037	* @copydoc FNSSMDEVLOADEXEC
6038	*/
6039	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6040	{
6041	RT_NOREF(uPass);
6042	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6043	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6044	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6045	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6046	int rc;
6047
6048	/* Load our part of the VGAState */
6049	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6050	AssertRCReturn(rc, rc);
6051
6052	/* Load the VGA framebuffer. */
6053	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
6054	uint32_t cbVgaFramebuffer = _32K;
6055	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
6056	{
6057	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
6058	AssertRCReturn(rc, rc);
6059	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
6060	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
6061	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6062	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
6063	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
6064	}
6065	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
6066	AssertRCReturn(rc, rc);
6067	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
6068	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
6069	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
6070	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
6071
6072	/* Load the VMSVGA state. */
6073	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6074	AssertRCReturn(rc, rc);
6075
6076	/* Load the active cursor bitmaps. */
6077	if (pSVGAState->Cursor.fActive)
6078	{
6079	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
6080	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
6081
6082	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6083	AssertRCReturn(rc, rc);
6084	}
6085
6086	/* Load the GMR state. */
6087	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
6088	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
6089	{
6090	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
6091	AssertRCReturn(rc, rc);
6092	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
6093	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
6094	("cGMR=%#x - expected 256B..1MB\n", cGMR),
6095	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6096	}
6097
6098	if (pThis->svga.cGMR != cGMR)
6099	{
6100	/* Reallocate GMR array. */
6101	Assert(pSVGAState->paGMR != NULL);
6102	RTMemFree(pSVGAState->paGMR);
6103	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
6104	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6105	pThis->svga.cGMR = cGMR;
6106	}
6107
6108	for (uint32_t i = 0; i < cGMR; ++i)
6109	{
6110	PGMR pGMR = &pSVGAState->paGMR[i];
6111
6112	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6113	AssertRCReturn(rc, rc);
6114
6115	if (pGMR->numDescriptors)
6116	{
6117	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6118	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6119	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6120
6121	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6122	{
6123	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6124	AssertRCReturn(rc, rc);
6125	}
6126	}
6127	}
6128
6129	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX)
6130	{
6131	bool f;
6132	uint32_t u32;
6133
6134	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_DX_CMDBUF)
6135	{
6136	/* Command buffers are saved independently from VGPU10. */
6137	rc = pHlp->pfnSSMGetBool(pSSM, &f);
6138	AssertLogRelRCReturn(rc, rc);
6139	if (f)
6140	{
6141	rc = vmsvgaR3LoadCommandBuffers(pDevIns, pThis, pThisCC, pSSM);
6142	AssertLogRelRCReturn(rc, rc);
6143	}
6144	}
6145
6146	rc = pHlp->pfnSSMGetBool(pSSM, &f);
6147	AssertLogRelRCReturn(rc, rc);
6148	pThis->fVMSVGA10 = f;
6149
6150	if (pThis->fVMSVGA10)
6151	{
6152	if (uVersion < VGA_SAVEDSTATE_VERSION_VMSVGA_DX_CMDBUF)
6153	{
6154	rc = vmsvgaR3LoadCommandBuffers(pDevIns, pThis, pThisCC, pSSM);
6155	AssertLogRelRCReturn(rc, rc);
6156	}
6157
6158	/*
6159	* OTables GBOs.
6160	*/
6161	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
6162	AssertLogRelRCReturn(rc, rc);
6163	AssertReturn(u32 == SVGA_OTABLE_MAX, VERR_INVALID_STATE);
6164	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
6165	{
6166	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
6167	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, pGbo);
6168	AssertRCReturn(rc, rc);
6169	}
6170
6171	/*
6172	* MOBs.
6173	*/
6174	for (;;)
6175	{
6176	rc = pHlp->pfnSSMGetU32(pSSM, &u32); /* MOB id. */
6177	AssertRCReturn(rc, rc);
6178	if (u32 == SVGA_ID_INVALID)
6179	break;
6180
6181	PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
6182	AssertPtrReturn(pMob, VERR_NO_MEMORY);
6183
6184	rc = vmsvgaR3LoadGbo(pDevIns, pSSM, &pMob->Gbo);
6185	AssertRCReturn(rc, rc);
6186
6187	pMob->Core.Key = u32;
6188	if (RTAvlU32Insert(&pSVGAState->MOBTree, &pMob->Core))
6189	RTListPrepend(&pSVGAState->MOBLRUList, &pMob->nodeLRU);
6190	else
6191	AssertFailedReturn(VERR_NO_MEMORY);
6192	}
6193
6194	# ifdef VMSVGA3D_DX
6195	if (pThis->svga.f3DEnabled)
6196	{
6197	pHlp->pfnSSMGetU32(pSSM, &pSVGAState->idDXContextCurrent);
6198	}
6199	# endif
6200	}
6201	}
6202
6203	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6204	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ true);
6205	# endif
6206
6207	VMSVGA_STATE_LOAD LoadState;
6208	LoadState.pSSM = pSSM;
6209	LoadState.uVersion = uVersion;
6210	LoadState.uPass = uPass;
6211	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6212	AssertLogRelRCReturn(rc, rc);
6213
6214	return VINF_SUCCESS;
6215	}
6216
6217	/**
6218	* Reinit the video mode after the state has been loaded.
6219	*/
6220	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6221	{
6222	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6223	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6224	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6225
6226	/* VMSVGA is working via VBVA interface, therefore it needs to be
6227	* enabled on saved state restore. See @bugref{10071#c7}. */
6228	if (pThis->svga.fEnabled)
6229	{
6230	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
6231	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
6232	}
6233
6234	/* Set the active cursor. */
6235	if (pSVGAState->Cursor.fActive)
6236	{
6237	/* We don't store the alpha flag, but we can take a guess that if
6238	* the old register interface was used, the cursor was B&W.
6239	*/
6240	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6241
6242	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6243	true /fVisible/,
6244	fAlpha,
6245	pSVGAState->Cursor.xHotspot,
6246	pSVGAState->Cursor.yHotspot,
6247	pSVGAState->Cursor.width,
6248	pSVGAState->Cursor.height,
6249	pSVGAState->Cursor.pData);
6250	AssertRC(rc);
6251
6252	if (pThis->svga.uCursorOn)
6253	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6254	}
6255
6256	/* If the VRAM handler should not be registered, we have to explicitly
6257	* unregister it here!
6258	*/
6259	if (!pThis->svga.fVRAMTracking)
6260	{
6261	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6262	}
6263
6264	/* Let the FIFO thread deal with changing the mode. */
6265	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6266
6267	return VINF_SUCCESS;
6268	}
6269
6270	static int vmsvgaR3SaveBufCtx(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PVMSVGACMDBUFCTX pBufCtx)
6271	{
6272	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6273
6274	int rc = pHlp->pfnSSMPutU32(pSSM, pBufCtx->cSubmitted);
6275	AssertLogRelRCReturn(rc, rc);
6276	if (pBufCtx->cSubmitted)
6277	{
6278	PVMSVGACMDBUF pIter;
6279	RTListForEach(&pBufCtx->listSubmitted, pIter, VMSVGACMDBUF, nodeBuffer)
6280	{
6281	pHlp->pfnSSMPutGCPhys(pSSM, pIter->GCPhysCB);
6282	pHlp->pfnSSMPutU32(pSSM, sizeof(SVGACBHeader));
6283	pHlp->pfnSSMPutMem(pSSM, &pIter->hdr, sizeof(SVGACBHeader));
6284	pHlp->pfnSSMPutU32(pSSM, pIter->hdr.length);
6285	if (pIter->hdr.length)
6286	rc = pHlp->pfnSSMPutMem(pSSM, pIter->pvCommands, pIter->hdr.length);
6287	AssertLogRelRCReturn(rc, rc);
6288	}
6289	}
6290	return rc;
6291	}
6292
6293	static int vmsvgaR3SaveGbo(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, VMSVGAGBO *pGbo)
6294	{
6295	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6296
6297	int rc;
6298	pHlp->pfnSSMPutU32(pSSM, pGbo->fGboFlags);
6299	pHlp->pfnSSMPutU32(pSSM, pGbo->cTotalPages);
6300	pHlp->pfnSSMPutU32(pSSM, pGbo->cbTotal);
6301	rc = pHlp->pfnSSMPutU32(pSSM, pGbo->cDescriptors);
6302	for (uint32_t iDesc = 0; iDesc < pGbo->cDescriptors; ++iDesc)
6303	{
6304	PVMSVGAGBODESCRIPTOR pDesc = &pGbo->paDescriptors[iDesc];
6305	pHlp->pfnSSMPutGCPhys(pSSM, pDesc->GCPhys);
6306	rc = pHlp->pfnSSMPutU64(pSSM, pDesc->cPages);
6307	}
6308	if (pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED)
6309	rc = pHlp->pfnSSMPutMem(pSSM, pGbo->pvHost, pGbo->cbTotal);
6310	return rc;
6311	}
6312
6313	/**
6314	* Portion of SVGA state which must be saved in the FIFO thread.
6315	*/
6316	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6317	{
6318	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6319	int rc;
6320
6321	/* Save the screen objects. */
6322	/* Count defined screen object. */
6323	uint32_t cScreens = 0;
6324	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6325	{
6326	if (pSVGAState->aScreens[i].fDefined)
6327	++cScreens;
6328	}
6329
6330	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6331	AssertLogRelRCReturn(rc, rc);
6332
6333	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6334	{
6335	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6336	if (!pScreen->fDefined)
6337	continue;
6338
6339	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6340	AssertLogRelRCReturn(rc, rc);
6341
6342	/*
6343	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX
6344	*/
6345	if (pScreen->pvScreenBitmap)
6346	{
6347	uint32_t const cbScreenBitmap = pScreen->cHeight * pScreen->cbPitch;
6348	pHlp->pfnSSMPutU32(pSSM, cbScreenBitmap);
6349	pHlp->pfnSSMPutMem(pSSM, pScreen->pvScreenBitmap, cbScreenBitmap);
6350	}
6351	else
6352	pHlp->pfnSSMPutU32(pSSM, 0);
6353	}
6354	return VINF_SUCCESS;
6355	}
6356
6357	/**
6358	* @copydoc FNSSMDEVSAVEEXEC
6359	*/
6360	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6361	{
6362	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6363	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6364	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6365	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6366	int rc;
6367
6368	/* Save our part of the VGAState */
6369	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6370	AssertLogRelRCReturn(rc, rc);
6371
6372	/* Save the framebuffer backup. */
6373	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6374	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6375	AssertLogRelRCReturn(rc, rc);
6376
6377	/* Save the VMSVGA state. */
6378	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6379	AssertLogRelRCReturn(rc, rc);
6380
6381	/* Save the active cursor bitmaps. */
6382	if (pSVGAState->Cursor.fActive)
6383	{
6384	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6385	AssertLogRelRCReturn(rc, rc);
6386	}
6387
6388	/* Save the GMR state */
6389	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6390	AssertLogRelRCReturn(rc, rc);
6391	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6392	{
6393	PGMR pGMR = &pSVGAState->paGMR[i];
6394
6395	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6396	AssertLogRelRCReturn(rc, rc);
6397
6398	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6399	{
6400	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6401	AssertLogRelRCReturn(rc, rc);
6402	}
6403	}
6404
6405	/*
6406	* VGA_SAVEDSTATE_VERSION_VMSVGA_DX+
6407	*/
6408	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
6409	{
6410	rc = pHlp->pfnSSMPutBool(pSSM, true);
6411	AssertLogRelRCReturn(rc, rc);
6412
6413	/* Device context command buffers. */
6414	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, &pSVGAState->CmdBufCtxDC);
6415	AssertRCReturn(rc, rc);
6416
6417	/* DX contexts command buffers. */
6418	rc = pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(pSVGAState->apCmdBufCtxs));
6419	AssertLogRelRCReturn(rc, rc);
6420	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6421	{
6422	if (pSVGAState->apCmdBufCtxs[i])
6423	{
6424	pHlp->pfnSSMPutBool(pSSM, true);
6425	rc = vmsvgaR3SaveBufCtx(pDevIns, pSSM, pSVGAState->apCmdBufCtxs[i]);
6426	AssertRCReturn(rc, rc);
6427	}
6428	else
6429	pHlp->pfnSSMPutBool(pSSM, false);
6430	}
6431
6432	rc = pHlp->pfnSSMPutU32(pSSM, pSVGAState->fCmdBuf);
6433	AssertRCReturn(rc, rc);
6434	}
6435	else
6436	{
6437	rc = pHlp->pfnSSMPutBool(pSSM, false);
6438	AssertLogRelRCReturn(rc, rc);
6439	}
6440
6441	rc = pHlp->pfnSSMPutBool(pSSM, pThis->fVMSVGA10);
6442	AssertLogRelRCReturn(rc, rc);
6443
6444	if (pThis->fVMSVGA10)
6445	{
6446	/*
6447	* OTables GBOs.
6448	*/
6449	pHlp->pfnSSMPutU32(pSSM, SVGA_OTABLE_MAX);
6450	for (int i = 0; i < SVGA_OTABLE_MAX; ++i)
6451	{
6452	VMSVGAGBO *pGbo = &pSVGAState->aGboOTables[i];
6453	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, pGbo);
6454	AssertRCReturn(rc, rc);
6455	}
6456
6457	/*
6458	* MOBs.
6459	*/
6460	PVMSVGAMOB pIter;
6461	RTListForEach(&pSVGAState->MOBLRUList, pIter, VMSVGAMOB, nodeLRU)
6462	{
6463	pHlp->pfnSSMPutU32(pSSM, pIter->Core.Key); /* MOB id. */
6464	rc = vmsvgaR3SaveGbo(pDevIns, pSSM, &pIter->Gbo);
6465	AssertRCReturn(rc, rc);
6466	}
6467
6468	pHlp->pfnSSMPutU32(pSSM, SVGA_ID_INVALID); /* End marker. */
6469
6470	# ifdef VMSVGA3D_DX
6471	if (pThis->svga.f3DEnabled)
6472	{
6473	pHlp->pfnSSMPutU32(pSSM, pSVGAState->idDXContextCurrent);
6474	}
6475	# endif
6476	}
6477
6478	/*
6479	* Must save some state (3D in particular) in the FIFO thread.
6480	*/
6481	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6482	AssertLogRelRCReturn(rc, rc);
6483
6484	return VINF_SUCCESS;
6485	}
6486
6487	/**
6488	* Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
6489	*
6490	* @param pThis The shared VGA/VMSVGA instance data.
6491	* @param pThisCC The device context.
6492	*/
6493	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
6494	{
6495	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6496
6497	# ifndef VMSVGA_USE_EMT_HALT_CODE
6498	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6499	{
6500	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6501	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6502	}
6503	# endif
6504
6505	if (pSVGAState->Cursor.fActive)
6506	{
6507	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6508	pSVGAState->Cursor.pData = NULL;
6509	pSVGAState->Cursor.fActive = false;
6510	}
6511
6512	if (pSVGAState->paGMR)
6513	{
6514	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6515	if (pSVGAState->paGMR[i].paDesc)
6516	RTMemFree(pSVGAState->paGMR[i].paDesc);
6517
6518	RTMemFree(pSVGAState->paGMR);
6519	pSVGAState->paGMR = NULL;
6520	}
6521
6522	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
6523	{
6524	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
6525	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
6526	{
6527	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
6528	RTMemFree(pSVGAState->apCmdBufCtxs[i]);
6529	pSVGAState->apCmdBufCtxs[i] = NULL;
6530	}
6531	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
6532	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
6533	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
6534	}
6535	}
6536
6537	/**
6538	* Constructor for PVMSVGAR3STATE structure.
6539	*
6540	* @returns VBox status code.
6541	* @param pDevIns The PDM device instance.
6542	* @param pThis The shared VGA/VMSVGA instance data.
6543	* @param pSVGAState Pointer to the structure. It is already allocated.
6544	*/
6545	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6546	{
6547	int rc = VINF_SUCCESS;
6548
6549	pSVGAState->pDevIns = pDevIns;
6550
6551	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6552	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6553
6554	# ifndef VMSVGA_USE_EMT_HALT_CODE
6555	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6556	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6557	AssertRCReturn(rc, rc);
6558	# endif
6559
6560	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
6561	AssertRCReturn(rc, rc);
6562
6563	/* Init screen ids which are constant and allow to use a pointer to aScreens element and know its index. */
6564	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6565	pSVGAState->aScreens[i].idScreen = i;
6566
6567	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
6568
6569	RTListInit(&pSVGAState->MOBLRUList);
6570	# ifdef VBOX_WITH_VMSVGA3D
6571	# ifdef VMSVGA3D_DX
6572	pSVGAState->idDXContextCurrent = SVGA3D_INVALID_ID;
6573	# endif
6574	# endif
6575	return rc;
6576	}
6577
6578	# ifdef VBOX_WITH_VMSVGA3D
6579	static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
6580	{
6581	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6582
6583	RTMemFree(pSVGAState->pFuncsMap);
6584	pSVGAState->pFuncsMap = NULL;
6585	RTMemFree(pSVGAState->pFuncsGBO);
6586	pSVGAState->pFuncsGBO = NULL;
6587	RTMemFree(pSVGAState->pFuncsDX);
6588	pSVGAState->pFuncsDX = NULL;
6589	RTMemFree(pSVGAState->pFuncsVGPU9);
6590	pSVGAState->pFuncsVGPU9 = NULL;
6591	RTMemFree(pSVGAState->pFuncs3D);
6592	pSVGAState->pFuncs3D = NULL;
6593	}
6594
6595	/* This structure is used only by vmsvgaR3Init3dInterfaces */
6596	typedef struct VMSVGA3DINTERFACE
6597	{
6598	char const *pcszName;
6599	uint32_t cbFuncs;
6600	void **ppvFuncs;
6601	} VMSVGA3DINTERFACE;
6602
6603	extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
6604	#if defined(VMSVGA3D_DX_BACKEND)
6605	extern VMSVGA3DBACKENDDESC const g_BackendDX;
6606	#endif
6607
6608	/**
6609	* Initializes the optional host 3D backend interfaces.
6610	*
6611	* @returns VBox status code.
6612	* @param pThisCC The VGA/VMSVGA state for ring-3.
6613	*/
6614	static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
6615	{
6616	#ifndef VMSVGA3D_DX
6617	RT_NOREF(pThis);
6618	#endif
6619
6620	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6621
6622	#define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
6623	VMSVGA3DINTERFACE a3dInterface[] =
6624	{
6625	ENTRY_3D_INTERFACE(3D, pFuncs3D),
6626	ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
6627	ENTRY_3D_INTERFACE(DX, pFuncsDX),
6628	ENTRY_3D_INTERFACE(MAP, pFuncsMap),
6629	ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
6630	};
6631	#undef ENTRY_3D_INTERFACE
6632
6633	VMSVGA3DBACKENDDESC const *pBackend = NULL;
6634	#if defined(VMSVGA3D_DX_BACKEND)
6635	if (pThis->fVMSVGA10)
6636	pBackend = &g_BackendDX;
6637	else
6638	#endif
6639	pBackend = &g_BackendLegacy;
6640
6641	int rc = VINF_SUCCESS;
6642	for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
6643	{
6644	VMSVGA3DINTERFACE *p = &a3dInterface[i];
6645
6646	int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
6647	if (RT_SUCCESS(rc2))
6648	{
6649	*p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
6650	AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
6651
6652	pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
6653	}
6654	}
6655
6656	if (RT_SUCCESS(rc))
6657	{
6658	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6659	if (RT_SUCCESS(rc))
6660	return VINF_SUCCESS;
6661	}
6662
6663	vmsvga3dR3Free3dInterfaces(pThisCC);
6664	return rc;
6665	}
6666	# endif /* VBOX_WITH_VMSVGA3D */
6667
6668	/**
6669	* Compute the host capabilities: device and FIFO.
6670	*
6671	* Depends on 3D backend initialization.
6672	*
6673	* @param pThis The shared VGA/VMSVGA instance data.
6674	* @param pThisCC The VGA/VMSVGA state for ring-3.
6675	* @param pu32DeviceCaps Device capabilities (SVGA_CAP_*).
6676	* @param pu32DeviceCaps2 Device capabilities (SVGA_CAP2_*).
6677	* @param pu32FIFOCaps FIFO capabilities (SVGA_FIFO_CAPS_*).
6678	*/
6679	static void vmsvgaR3GetCaps(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t pu32DeviceCaps, uint32_t pu32DeviceCaps2, uint32_t *pu32FIFOCaps)
6680	{
6681	#ifndef VBOX_WITH_VMSVGA3D
6682	RT_NOREF(pThisCC);
6683	#endif
6684
6685	/* Device caps. */
6686	*pu32DeviceCaps = SVGA_CAP_GMR
6687	\| SVGA_CAP_GMR2
6688	\| SVGA_CAP_CURSOR
6689	\| SVGA_CAP_CURSOR_BYPASS
6690	\| SVGA_CAP_CURSOR_BYPASS_2
6691	\| SVGA_CAP_EXTENDED_FIFO
6692	\| SVGA_CAP_IRQMASK
6693	\| SVGA_CAP_PITCHLOCK
6694	\| SVGA_CAP_RECT_COPY
6695	\| SVGA_CAP_TRACES
6696	\| SVGA_CAP_SCREEN_OBJECT_2
6697	\| SVGA_CAP_ALPHA_CURSOR;
6698
6699	pu32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS / Enable register based command buffer submission. */
6700	;
6701
6702	*pu32DeviceCaps2 = SVGA_CAP2_NONE;
6703
6704	/* VGPU10 capabilities. */
6705	if (pThis->fVMSVGA10)
6706	{
6707	# ifdef VBOX_WITH_VMSVGA3D
6708	if (pThisCC->svga.pSvgaR3State->pFuncsGBO)
6709	pu32DeviceCaps \|= SVGA_CAP_GBOBJECTS; / Enable guest-backed objects and surfaces. */
6710	if (pThisCC->svga.pSvgaR3State->pFuncsDX)
6711	{
6712	pu32DeviceCaps \|= SVGA_CAP_DX / DX commands, and command buffers in a mob. */
6713	\| SVGA_CAP_CAP2_REGISTER /* Extended capabilities. */
6714	;
6715
6716	if (*pu32DeviceCaps & SVGA_CAP_CAP2_REGISTER)
6717	pu32DeviceCaps2 \|= SVGA_CAP2_GROW_OTABLE / "Allow the GrowOTable/DXGrowCOTable commands" */
6718	\| SVGA_CAP2_INTRA_SURFACE_COPY /* "IntraSurfaceCopy command" */
6719	\| SVGA_CAP2_DX2 /* Shader Model 4.1.
6720	* "Allow the DefineGBSurface_v3, WholeSurfaceCopy, WriteZeroSurface, and
6721	* HintZeroSurface commands, and the SVGA_REG_GUEST_DRIVER_ID register."
6722	*/
6723	\| SVGA_CAP2_GB_MEMSIZE_2 /* "Allow the SVGA_REG_GBOBJECT_MEM_SIZE_KB register" */
6724	\| SVGA_CAP2_OTABLE_PTDEPTH_2
6725	\| SVGA_CAP2_DX3 /* Shader Model 5.
6726	* DefineGBSurface_v4, etc
6727	*/
6728	;
6729	}
6730	# endif
6731	}
6732
6733	# ifdef VBOX_WITH_VMSVGA3D
6734	if (pThisCC->svga.pSvgaR3State->pFuncs3D)
6735	*pu32DeviceCaps \|= SVGA_CAP_3D;
6736	# endif
6737
6738	/* FIFO capabilities. */
6739	if (!pThis->fVmSvga3)
6740	*pu32FIFOCaps = SVGA_FIFO_CAP_FENCE
6741	\| SVGA_FIFO_CAP_PITCHLOCK
6742	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6743	\| SVGA_FIFO_CAP_RESERVE
6744	\| SVGA_FIFO_CAP_GMR2
6745	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6746	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
6747	}
6748
6749	/** Initialize the FIFO on power on and reset.
6750	*
6751	* @param pThis The shared VGA/VMSVGA instance data.
6752	* @param pThisCC The VGA/VMSVGA state for ring-3.
6753	*/
6754	static void vmsvgaR3InitFIFO(PVGASTATE pThis, PVGASTATECC pThisCC)
6755	{
6756	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6757
6758	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6759	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6760	}
6761
6762	# ifdef VBOX_WITH_VMSVGA3D
6763	/**
6764	* Initializes the host 3D capabilities and writes them to FIFO memory.
6765	*
6766	* @returns VBox status code.
6767	* @param pThis The shared VGA/VMSVGA instance data.
6768	* @param pThisCC The VGA/VMSVGA state for ring-3.
6769	*/
6770	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6771	{
6772	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
6773	bool const fSavedBuffering = RTLogRelSetBuffering(true);
6774
6775	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
6776	{
6777	uint32_t val = 0;
6778	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
6779	if (RT_SUCCESS(rc))
6780	pThis->svga.au32DevCaps[i] = val;
6781	else
6782	pThis->svga.au32DevCaps[i] = 0;
6783
6784	/* LogRel the capability value. */
6785	if (i < SVGA3D_DEVCAP_MAX)
6786	{
6787	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
6788	if (RT_SUCCESS(rc))
6789	{
6790	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
6791	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
6792	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
6793	{
6794	float const fval = (float )&val;
6795	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
6796	}
6797	else
6798	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
6799	}
6800	else
6801	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
6802	}
6803	else
6804	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
6805	}
6806
6807	RTLogRelSetBuffering(fSavedBuffering);
6808
6809	/* 3d hardware version; latest and greatest */
6810	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6811	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6812
6813	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
6814	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
6815	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
6816	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
6817	*/
6818	SVGA3dCapsRecord *pCaps;
6819	SVGA3dCapPair *pData;
6820
6821	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6822	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6823	pData = (SVGA3dCapPair *)&pCaps->data;
6824
6825	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6826	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
6827	{
6828	pData[i][0] = i;
6829	pData[i][1] = pThis->svga.au32DevCaps[i];
6830	}
6831	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6832	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6833
6834	/* Mark end of record array (a zero word). */
6835	pCaps->header.length = 0;
6836	}
6837
6838	# endif
6839
6840	/**
6841	* Resets the SVGA hardware state
6842	*
6843	* @returns VBox status code.
6844	* @param pDevIns The device instance.
6845	*/
6846	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6847	{
6848	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6849	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6850	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6851
6852	/* Reset before init? */
6853	if (!pSVGAState)
6854	return VINF_SUCCESS;
6855
6856	Log(("vmsvgaR3Reset\n"));
6857
6858	if (!pThis->fVmSvga3)
6859	{
6860	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6861	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6862	}
6863
6864	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* Hack around lock order issue. FIFO thread might take the lock. */
6865
6866	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 60000 /ms/);
6867	AssertLogRelRC(rc);
6868
6869	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
6870	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
6871
6872	/* Reset other stuff. */
6873	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6874	RT_ZERO(pThis->svga.au32ScratchRegion);
6875
6876	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
6877
6878	vmsvgaR3StateTerm(pThis, pThisCC);
6879	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6880
6881	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6882
6883	if (!pThis->fVmSvga3)
6884	vmsvgaR3InitFIFO(pThis, pThisCC);
6885
6886	/* Initialize FIFO and register capabilities. */
6887	vmsvgaR3GetCaps(pThis, pThisCC, &pThis->svga.u32DeviceCaps, &pThis->svga.u32DeviceCaps2, &pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]);
6888
6889	# ifdef VBOX_WITH_VMSVGA3D
6890	if ( pThis->svga.f3DEnabled
6891	&& !pThis->fVmSvga3)
6892	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6893	# endif
6894
6895	/* VRAM tracking is enabled by default during bootup. */
6896	pThis->svga.fVRAMTracking = true;
6897	pThis->svga.fEnabled = false;
6898
6899	/* Invalidate current settings. */
6900	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6901	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6902	pThis->svga.uBpp = pThis->svga.uHostBpp;
6903	pThis->svga.cbScanline = 0;
6904	pThis->svga.u32PitchLock = 0;
6905
6906	return rc;
6907	}
6908
6909	/**
6910	* Cleans up the SVGA hardware state
6911	*
6912	* @returns VBox status code.
6913	* @param pDevIns The device instance.
6914	*/
6915	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6916	{
6917	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6918	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6919
6920	/*
6921	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6922	*/
6923	if (pThisCC->svga.pFIFOIOThread)
6924	{
6925	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6926	NULL /pvParam/, 30000 /ms/);
6927	AssertLogRelRC(rc);
6928
6929	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6930	AssertLogRelRC(rc);
6931	pThisCC->svga.pFIFOIOThread = NULL;
6932	}
6933
6934	/*
6935	* Destroy the special SVGA state.
6936	*/
6937	if (pThisCC->svga.pSvgaR3State)
6938	{
6939	vmsvgaR3StateTerm(pThis, pThisCC);
6940
6941	# ifdef VBOX_WITH_VMSVGA3D
6942	vmsvga3dR3Free3dInterfaces(pThisCC);
6943	# endif
6944
6945	RTMemFree(pThisCC->svga.pSvgaR3State);
6946	pThisCC->svga.pSvgaR3State = NULL;
6947	}
6948
6949	/*
6950	* Free our resources residing in the VGA state.
6951	*/
6952	if (pThisCC->svga.pbVgaFrameBufferR3)
6953	{
6954	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6955	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6956	}
6957	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6958	{
6959	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6960	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6961	}
6962	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6963	{
6964	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6965	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6966	}
6967
6968	return VINF_SUCCESS;
6969	}
6970
6971	static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
6972	const char pszType, void const pvValue,
6973	int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
6974	{
6975	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
6976	double const v = (double )&pvValue;
6977	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
6978	}
6979
6980	/**
6981	* Initialize the SVGA hardware state
6982	*
6983	* @returns VBox status code.
6984	* @param pDevIns The device instance.
6985	*/
6986	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6987	{
6988	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6989	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6990	PVMSVGAR3STATE pSVGAState;
6991	int rc;
6992
6993	rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
6994	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
6995
6996	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6997	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6998
6999	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
7000
7001	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
7002	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
7003	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
7004
7005	/* Create event semaphore. */
7006	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
7007	AssertRCReturn(rc, rc);
7008
7009	/* Create event semaphore. */
7010	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
7011	AssertRCReturn(rc, rc);
7012
7013	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
7014	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
7015
7016	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
7017	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
7018
7019	pSVGAState = pThisCC->svga.pSvgaR3State;
7020
7021	/* VRAM tracking is enabled by default during bootup. */
7022	pThis->svga.fVRAMTracking = true;
7023
7024	/* Set up the host bpp. This value is as a default for the programmable
7025	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
7026	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
7027	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
7028	*
7029	* NB: The driver cBits value is currently constant for the lifetime of the
7030	* VM. If that changes, the host bpp logic might need revisiting.
7031	*/
7032	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
7033
7034	/* Invalidate current settings. */
7035	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
7036	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
7037	pThis->svga.uBpp = pThis->svga.uHostBpp;
7038	pThis->svga.cbScanline = 0;
7039
7040	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
7041	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
7042	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
7043	{
7044	pThis->svga.u32MaxWidth -= 256;
7045	pThis->svga.u32MaxHeight -= 256;
7046	}
7047	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
7048
7049	# ifdef DEBUG_GMR_ACCESS
7050	/* Register the GMR access handler type. */
7051	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE, vmsvgaR3GmrAccessHandler,
7052	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
7053	AssertRCReturn(rc, rc);
7054	# endif
7055
7056	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
7057	/* Register the FIFO access handler type. In addition to debugging FIFO
7058	access, this is also used to facilitate extended fifo thread sleeps. */
7059	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns,
7060	# ifdef DEBUG_FIFO_ACCESS
7061	PGMPHYSHANDLERKIND_ALL,
7062	# else
7063	PGMPHYSHANDLERKIND_WRITE,
7064	# endif
7065	vmsvgaR3FifoAccessHandler,
7066	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
7067	AssertRCReturn(rc, rc);
7068	# endif
7069
7070	/* Create the async IO thread. */
7071	if (pThis->fVmSvga3)
7072	{
7073	/*
7074	* For SVGA 3 we use a different command processing loop because the standard FIFO loop would get riddled with
7075	* if (pThis->fVmsvga3) otherwise
7076	*/
7077	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3CmdBufLoop, vmsvgaR3FifoLoopWakeUp, 0,
7078	RTTHREADTYPE_IO, "VMSVGA CMD");
7079	}
7080	else
7081	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
7082	RTTHREADTYPE_IO, "VMSVGA FIFO");
7083	if (RT_FAILURE(rc))
7084	{
7085	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
7086	return rc;
7087	}
7088
7089	/*
7090	* Statistics.
7091	*/
7092	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
7093	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
7094	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
7095	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
7096	# ifdef VBOX_WITH_STATISTICS
7097	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
7098	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
7099	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
7100	# endif
7101	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
7102	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
7103	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
7104	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
7105	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
7106	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
7107	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
7108	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
7109	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
7110	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
7111	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
7112	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
7113	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
7114	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
7115	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
7116	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
7117	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
7118	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
7119	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
7120	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
7121	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
7122	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
7123	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
7124	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
7125	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
7126	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
7127	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
7128	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
7129	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
7130	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
7131	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
7132	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
7133	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
7134	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
7135	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
7136	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
7137	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
7138	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
7139	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
7140	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
7141	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
7142	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
7143	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
7144	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
7145	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
7146	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
7147	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
7148	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
7149	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
7150	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
7151	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
7152	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
7153	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
7154	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
7155	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
7156	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
7157	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
7158	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
7159	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
7160
7161	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
7162	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
7163	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
7164	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
7165	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
7166	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
7167	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
7168	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
7169	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
7170	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
7171	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
7172	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
7173	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
7174	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
7175	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
7176	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
7177	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
7178	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
7179	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
7180	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
7181	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
7182	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
7183	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
7184	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
7185	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
7186	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
7187	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
7188	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
7189	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
7190	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
7191	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
7192	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
7193	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
7194	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
7195	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
7196	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
7197	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
7198	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
7199	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
7200	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
7201
7202	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
7203	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
7204	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
7205	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
7206	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
7207	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
7208	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
7209	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
7210	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
7211	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
7212	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
7213	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
7214	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
7215	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
7216	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
7217	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
7218	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
7219	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
7220	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
7221	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
7222	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
7223	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
7224	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
7225	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
7226	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
7227	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
7228	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
7229	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
7230	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
7231	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
7232	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
7233	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
7234	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
7235	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
7236	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
7237	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
7238	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
7239	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
7240	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
7241	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
7242	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
7243	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
7244	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
7245	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
7246	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
7247	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
7248	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
7249	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
7250	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
7251	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
7252	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
7253	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
7254	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
7255	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
7256	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
7257	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
7258	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
7259	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
7260	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
7261	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
7262	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
7263	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
7264
7265	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
7266	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
7267	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
7268	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
7269	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
7270	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
7271	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
7272	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
7273	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
7274	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
7275	# endif
7276	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
7277	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
7278	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
7279	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
7280	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
7281
7282	# undef REG_CNT
7283	# undef REG_PRF
7284
7285	/*
7286	* Info handlers.
7287	*/
7288	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
7289	# ifdef VBOX_WITH_VMSVGA3D
7290	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
7291	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
7292	"VMSVGA 3d surface details. "
7293	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
7294	vmsvgaR3Info3dSurface);
7295	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
7296	"VMSVGA 3d surface details and bitmap: "
7297	"sid[>dir]",
7298	vmsvgaR3Info3dSurfaceBmp);
7299	# endif
7300
7301	return VINF_SUCCESS;
7302	}
7303
7304	/* Initialize 3D backend, set device capabilities and call pfnPowerOn callback of 3D backend.
7305	*
7306	* @param pDevIns The device instance.
7307	* @param pThis The shared VGA/VMSVGA instance data.
7308	* @param pThisCC The VGA/VMSVGA state for ring-3.
7309	* @param fLoadState Whether saved state is being loaded.
7310	*/
7311	static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState)
7312	{
7313	# ifdef VBOX_WITH_VMSVGA3D
7314	if (pThis->svga.f3DEnabled)
7315	{
7316	/* Load a 3D backend. */
7317	int rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
7318	if (RT_FAILURE(rc))
7319	{
7320	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
7321	pThis->svga.f3DEnabled = false;
7322	}
7323	}
7324	# endif
7325
7326	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
7327	if (pThis->svga.f3DEnabled)
7328	{
7329	/* The FIFO thread may use X API for accelerated screen output. */
7330	/* This must be done after backend initialization by vmsvgaR3Init3dInterfaces,
7331	* because it dynamically resolves XInitThreads.
7332	*/
7333	XInitThreads();
7334	}
7335	# endif
7336
7337	if (!fLoadState)
7338	{
7339	if (!pThis->fVmSvga3)
7340	vmsvgaR3InitFIFO(pThis, pThisCC);
7341	vmsvgaR3GetCaps(pThis, pThisCC, &pThis->svga.u32DeviceCaps, &pThis->svga.u32DeviceCaps2, &pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]);
7342	}
7343	# ifdef DEBUG
7344	else
7345	{
7346	/* If saved state is being loaded then FIFO and caps are already restored. */
7347	uint32_t u32DeviceCaps = 0;
7348	uint32_t u32DeviceCaps2 = 0;
7349	uint32_t u32FIFOCaps = 0;
7350	vmsvgaR3GetCaps(pThis, pThisCC, &u32DeviceCaps, &u32DeviceCaps2, &u32FIFOCaps);
7351
7352	/* Capabilities should not change normally.
7353	* However the saved state might have a subset of currently implemented caps.
7354	*/
7355	Assert( (pThis->svga.u32DeviceCaps & u32DeviceCaps) == pThis->svga.u32DeviceCaps
7356	&& (pThis->svga.u32DeviceCaps2 & u32DeviceCaps2) == pThis->svga.u32DeviceCaps2
7357	&& ( pThis->fVmSvga3
7358	\|\| (pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] & u32FIFOCaps) == pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES]));
7359	}
7360	#endif
7361
7362	# ifdef VBOX_WITH_VMSVGA3D
7363	if ( pThis->svga.f3DEnabled
7364	&& !pThis->fVmSvga3)
7365	{
7366	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
7367	int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
7368	if (RT_SUCCESS(rc))
7369	{
7370	/* Initialize FIFO 3D capabilities. */
7371	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
7372	}
7373	else
7374	{
7375	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
7376	pThis->svga.f3DEnabled = false;
7377	}
7378	}
7379	# else /* !VBOX_WITH_VMSVGA3D */
7380	RT_NOREF(pDevIns);
7381	# endif /* !VBOX_WITH_VMSVGA3D */
7382	}
7383
7384
7385	/**
7386	* Power On notification.
7387	*
7388	* @param pDevIns The device instance data.
7389	*
7390	* @remarks Caller enters the device critical section.
7391	*/
7392	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
7393	{
7394	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7395	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7396
7397	vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /fLoadState=/ false);
7398	}
7399
7400	/**
7401	* Power Off notification.
7402	*
7403	* @param pDevIns The device instance data.
7404	*
7405	* @remarks Caller enters the device critical section.
7406	*/
7407	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
7408	{
7409	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7410	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7411
7412	/*
7413	* Notify the FIFO thread.
7414	*/
7415	if (pThisCC->svga.pFIFOIOThread)
7416	{
7417	/* Hack around a deadlock:
7418	* - the caller holds the device critsect;
7419	* - FIFO thread may attempt to enter the critsect too (when raising an IRQ).
7420	*/
7421	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
7422
7423	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
7424	NULL /pvParam/, 30000 /ms/);
7425	AssertLogRelRC(rc);
7426
7427	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
7428	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
7429	}
7430	}
7431
7432	#endif /* IN_RING3 */

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