VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 100347

Last change on this file since 100347 was 100178, checked in by vboxsync, 20 months ago

Devices/Graphics: release device lock for FIFO thread reset. bugref:9830

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1/* $Id: DevVGA-SVGA.cpp 100178 2023-06-15 11:17:28Z vboxsync $ */
2/** @file
3 * VMware SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 * - Log5 for info about GMR pages.
12 * - Log6 for DX shaders.
13 * - Log7 for SVGA command dump.
14 * - Log8 for content of constant and vertex buffers.
15 * - LogRel for the usual important stuff.
16 * - LogRel2 for cursor.
17 * - LogRel3 for 3D performance data.
18 * - LogRel4 for HW accelerated graphics output.
19 */
20
21/*
22 * Copyright (C) 2013-2023 Oracle and/or its affiliates.
23 *
24 * This file is part of VirtualBox base platform packages, as
25 * available from https://www.virtualbox.org.
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License
29 * as published by the Free Software Foundation, in version 3 of the
30 * License.
31 *
32 * This program is distributed in the hope that it will be useful, but
33 * WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35 * General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, see <https://www.gnu.org/licenses>.
39 *
40 * SPDX-License-Identifier: GPL-3.0-only
41 */
42
43
44/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
45 *
46 * This device emulation was contributed by trivirt AG. It offers an
47 * alternative to our Bochs based VGA graphics and 3d emulations. This is
48 * valuable for Xorg based guests, as there is driver support shipping with Xorg
49 * since it forked from XFree86.
50 *
51 *
52 * @section sec_dev_vmsvga_sdk The VMware SDK
53 *
54 * This is officially deprecated now, however it's still quite useful,
55 * especially for getting the old features working:
56 * http://vmware-svga.sourceforge.net/
57 *
58 * They currently point developers at the following resources.
59 * - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
60 * - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
61 * - http://cgit.freedesktop.org/mesa/vmwgfx/
62 *
63 * @subsection subsec_dev_vmsvga_sdk_results Test results
64 *
65 * Test results:
66 * - 2dmark.img:
67 * + todo
68 * - backdoor-tclo.img:
69 * + todo
70 * - blit-cube.img:
71 * + todo
72 * - bunnies.img:
73 * + todo
74 * - cube.img:
75 * + todo
76 * - cubemark.img:
77 * + todo
78 * - dynamic-vertex-stress.img:
79 * + todo
80 * - dynamic-vertex.img:
81 * + todo
82 * - fence-stress.img:
83 * + todo
84 * - gmr-test.img:
85 * + todo
86 * - half-float-test.img:
87 * + todo
88 * - noscreen-cursor.img:
89 * - The CURSOR I/O and FIFO registers are not implemented, so the mouse
90 * cursor doesn't show. (Hacking the GUI a little, would make the cursor
91 * visible though.)
92 * - Cursor animation via the palette doesn't work.
93 * - During debugging, it turns out that the framebuffer content seems to
94 * be halfways ignore or something (memset(fb, 0xcc, lots)).
95 * - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
96 * grow it 0x10 fold (128KB -> 2MB like in WS10).
97 * - null.img:
98 * + todo
99 * - pong.img:
100 * + todo
101 * - presentReadback.img:
102 * + todo
103 * - resolution-set.img:
104 * + todo
105 * - rt-gamma-test.img:
106 * + todo
107 * - screen-annotation.img:
108 * + todo
109 * - screen-cursor.img:
110 * + todo
111 * - screen-dma-coalesce.img:
112 * + todo
113 * - screen-gmr-discontig.img:
114 * + todo
115 * - screen-gmr-remap.img:
116 * + todo
117 * - screen-multimon.img:
118 * + todo
119 * - screen-present-clip.img:
120 * + todo
121 * - screen-render-test.img:
122 * + todo
123 * - screen-simple.img:
124 * + todo
125 * - screen-text.img:
126 * + todo
127 * - simple-shaders.img:
128 * + todo
129 * - simple_blit.img:
130 * + todo
131 * - tiny-2d-updates.img:
132 * + todo
133 * - video-formats.img:
134 * + todo
135 * - video-sync.img:
136 * + todo
137 *
138 */
139
140
141/*********************************************************************************************************************************
142* Header Files *
143*********************************************************************************************************************************/
144#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
145#include <VBox/vmm/pdmdev.h>
146#include <VBox/version.h>
147#include <VBox/err.h>
148#include <VBox/log.h>
149#include <VBox/vmm/pgm.h>
150#include <VBox/sup.h>
151
152#include <iprt/assert.h>
153#include <iprt/semaphore.h>
154#include <iprt/uuid.h>
155#ifdef IN_RING3
156# include <iprt/ctype.h>
157# include <iprt/mem.h>
158# ifdef VBOX_STRICT
159# include <iprt/time.h>
160# endif
161#endif
162
163#include <VBox/AssertGuest.h>
164#include <VBox/VMMDev.h>
165#include <VBoxVideo.h>
166#include <VBox/bioslogo.h>
167
168#ifdef LOG_ENABLED
169#include "svgadump/svga_dump.h"
170#endif
171
172/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
173#include "DevVGA.h"
174
175/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
176#ifdef VBOX_WITH_VMSVGA3D
177# include "DevVGA-SVGA3d.h"
178# ifdef RT_OS_DARWIN
179# include "DevVGA-SVGA3d-cocoa.h"
180# endif
181# ifdef RT_OS_LINUX
182# ifdef IN_RING3
183# include "DevVGA-SVGA3d-glLdr.h"
184# endif
185# endif
186#endif
187#ifdef IN_RING3
188#include "DevVGA-SVGA-internal.h"
189#endif
190
191
192/*********************************************************************************************************************************
193* Defined Constants And Macros *
194*********************************************************************************************************************************/
195/**
196 * Macro for checking if a fixed FIFO register is valid according to the
197 * current FIFO configuration.
198 *
199 * @returns true / false.
200 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
201 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
202 */
203#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
204
205
206/*********************************************************************************************************************************
207* Structures and Typedefs *
208*********************************************************************************************************************************/
209
210
211/*********************************************************************************************************************************
212* Internal Functions *
213*********************************************************************************************************************************/
214#ifdef IN_RING3
215# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
216static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
217# endif
218# ifdef DEBUG_GMR_ACCESS
219static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
220# endif
221#endif
222
223
224/*********************************************************************************************************************************
225* Global Variables *
226*********************************************************************************************************************************/
227#ifdef IN_RING3
228
229/**
230 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
231 */
232static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
233{
234 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
235 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
236 SSMFIELD_ENTRY_TERM()
237};
238
239/**
240 * SSM descriptor table for the GMR structure.
241 */
242static SSMFIELD const g_aGMRFields[] =
243{
244 SSMFIELD_ENTRY( GMR, cMaxPages),
245 SSMFIELD_ENTRY( GMR, cbTotal),
246 SSMFIELD_ENTRY( GMR, numDescriptors),
247 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
248 SSMFIELD_ENTRY_TERM()
249};
250
251/**
252 * SSM descriptor table for the VMSVGASCREENOBJECT structure.
253 */
254static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
255{
256 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
257 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
258 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
259 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
260 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
261 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
262 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
263 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
264 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
265 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
266 SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
267 SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
268 SSMFIELD_ENTRY_TERM()
269};
270
271/**
272 * SSM descriptor table for the VMSVGAR3STATE structure.
273 */
274static SSMFIELD const g_aVMSVGAR3STATEFields[] =
275{
276 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
277 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
278 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
279 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
280 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
281 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
282 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
283 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
284 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
285 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
287#ifdef VMSVGA_USE_EMT_HALT_CODE
288 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
289#else
290 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
291#endif
292 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
293 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
294 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
295 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
296 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
297 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
298 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
299 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
300 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
301 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
302 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
303 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
304 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
305 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
306 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
307 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
308 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
309 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
310 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
311 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
312 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
313 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
314 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
315 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
316 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
317 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
318 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
319 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
320 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
321 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
322 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
323 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
324 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
325 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
326 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
327 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
328 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
329 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
330 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
331 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
332 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
333 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
334 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
335 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
336 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
337 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
338 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
339 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
340 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
341 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
342 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
343 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
344 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
345 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
346 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
347 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
348 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
349 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
350 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
351 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
352 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
353 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
354 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
355
356 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
357 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
358 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
359 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
360
361 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
362 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
363 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
364 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
365 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
366 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
367 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
368# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
369 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
370# endif
371 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
372 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
373 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
374 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
375
376 SSMFIELD_ENTRY_TERM()
377};
378
379/**
380 * SSM descriptor table for the VGAState.svga structure.
381 */
382static SSMFIELD const g_aVGAStateSVGAFields[] =
383{
384 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
385 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
386 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
387 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
388 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
389 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
390 SSMFIELD_ENTRY( VMSVGAState, fBusy),
391 SSMFIELD_ENTRY( VMSVGAState, fTraces),
392 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
393 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
394 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
395 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
396 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
397 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
398 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
399 SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
400 SSMFIELD_ENTRY_VER( VMSVGAState, u32DeviceCaps2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
401 SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverId, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
402 SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer1, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
403 SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer2, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
404 SSMFIELD_ENTRY_VER( VMSVGAState, u32GuestDriverVer3, VGA_SAVEDSTATE_VERSION_VMSVGA_REG_CAP2),
405 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
406 SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
407 SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
408 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
409 SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
410 SSMFIELD_ENTRY( VMSVGAState, uWidth),
411 SSMFIELD_ENTRY( VMSVGAState, uHeight),
412 SSMFIELD_ENTRY( VMSVGAState, uBpp),
413 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
414 SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
415 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
416 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
417 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
418 SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
419 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
420 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
421 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
422 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
423 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
424 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
425 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
426 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
427 SSMFIELD_ENTRY_VER( VMSVGAState, au32DevCaps, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
428 SSMFIELD_ENTRY_VER( VMSVGAState, u32DevCapIndex, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
429 SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandLow, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
430 SSMFIELD_ENTRY_VER( VMSVGAState, u32RegCommandHigh, VGA_SAVEDSTATE_VERSION_VMSVGA_DX),
431
432 SSMFIELD_ENTRY_TERM()
433};
434#endif /* IN_RING3 */
435
436
437/*********************************************************************************************************************************
438* Internal Functions *
439*********************************************************************************************************************************/
440#ifdef IN_RING3
441static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
442static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
443 uint32_t uVersion, uint32_t uPass);
444static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
445static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
446static void vmsvgaR3PowerOnDevice(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fLoadState);
447#endif /* IN_RING3 */
448
449
450#define SVGA_CASE_ID2STR(idx) case idx: return #idx
451#if defined(LOG_ENABLED)
452/**
453 * Index register string name lookup
454 *
455 * @returns Index register string or "UNKNOWN"
456 * @param pThis The shared VGA/VMSVGA state.
457 * @param idxReg The index register.
458 */
459static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
460{
461 AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
462 switch (idxReg)
463 {
464 SVGA_CASE_ID2STR(SVGA_REG_ID);
465 SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
466 SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
467 SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
468 SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
469 SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
470 SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
471 SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
472 SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
473 SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
474 SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
475 SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
476 SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
477 SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
478 SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
479 SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
480 SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
481
482 /* ID 0 implementation only had the above registers, then the palette */
483 SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
484 SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
485 SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
486 SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
487 SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
488 SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
489 SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
490 SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
491 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
492 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
493 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
494 SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
495 SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
496 SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
497 SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
498 SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
499 SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
500
501 /* Legacy multi-monitor support */
502 SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
503 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
504 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
505 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
506 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
507 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
508 SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
509
510 SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
511 SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
512 SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
513 SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
514
515 SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
516 SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
517 SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
518 SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
519 SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
520 SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
521 SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
522 SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
523 SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
524 SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
525 SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
526 SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
527 SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
528 SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
529 SVGA_CASE_ID2STR(SVGA_REG_CAP2);
530 SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
531 SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
532 SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
533 SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
534 SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
535 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
536 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
537 SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
538 SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
539 SVGA_CASE_ID2STR(SVGA_REG_FENCE);
540 SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
541 SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
542 SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
543 SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
544 SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
545 SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
546 SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
547 SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
548
549 default:
550 if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
551 return "SVGA_SCRATCH_BASE reg";
552 if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
553 return "SVGA_PALETTE_BASE reg";
554 return "UNKNOWN";
555 }
556}
557#endif /* LOG_ENABLED */
558
559#if defined(LOG_ENABLED) || (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
560static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
561{
562 AssertCompile(SVGA3D_DEVCAP_MAX == 260);
563 switch (idxDevCap)
564 {
565 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
566 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
567 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
568 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
569 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
570 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
571 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
572 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
573 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
574 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
575 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
576 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
577 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
578 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
579 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
580 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
581 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
582 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
583 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
584 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
585 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
586 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
587 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
588 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
589 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
590 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
591 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
592 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
593 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
594 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
595 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
596 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
597 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
598 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
599 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
600 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
601 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
602 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
603 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
604 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
605 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
606 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
607 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
608 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
609 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
610 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
611 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
612 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
613 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
614 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
615 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
616 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
617 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
618 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
619 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
620 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
621 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
622 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
623 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
624 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
625 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
626 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
627 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
628 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
629 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
630 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
631 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
632 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
633 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
634 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
635 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
636 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
637 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
638 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
639 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
640 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
641 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
642 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
643 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
644 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
645 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
646 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
647 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
648 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
649 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
650 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
651 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
652 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
653 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
654 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
655 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
656 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
657 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
658 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
659 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
660 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
661 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
662 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
663 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
664 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
665 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
666 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
667 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
668 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
669 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
670 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
671 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
672 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
673 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
674 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
675 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
676 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
677 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
678 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
679 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
680 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
681 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
682 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
683 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
684 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
685 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
686 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
687 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
688 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
689 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
690 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
691 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
692 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
693 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
694 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
695 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
696 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
697 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
698 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
699 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
700 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
701 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
702 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
703 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
704 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
705 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
706 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
707 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
708 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
709 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
710 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
711 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
712 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
713 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
714 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
715 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
716 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
717 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
718 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
719 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
720 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
721 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
722 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
723 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
724 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
725 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
726 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
727 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
728 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
729 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
730 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
731 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
732 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
733 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
734 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
735 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
736 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
737 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
738 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
739 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
740 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
741 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
742 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
743 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
744 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
745 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
746 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
747 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
748 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
749 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
750 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
751 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
752 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
753 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
754 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
755 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
756 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
757 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
758 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
759 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
760 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
761 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
762 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
763 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
764 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
765 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
766 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
767 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
768 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
769 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
770 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
771 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
772 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
773 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
774 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
775 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
776 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
777 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
778 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
779 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
780 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
781 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
782 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
783 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
784 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
785 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
786 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
787 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
788 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
789 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
790 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
791 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
792 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
793 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
794 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
795 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
796 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
797 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
798 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
799 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
800 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
801 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
802 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
803 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
804 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
805 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
806 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
807 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
808 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
809 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
810 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
811 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
812 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
813 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
814 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
815 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
816 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
817 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
818 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
819 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
820 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
821 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
822 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
823 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
824 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
825 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
826
827 SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
828
829 default:
830 break;
831 }
832 return "UNKNOWN";
833}
834#endif /* defined(LOG_ENABLED) || (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
835#undef SVGA_CASE_ID2STR
836
837
838#ifdef IN_RING3
839
840/**
841 * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
842 */
843DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
844{
845 PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
846 PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
847
848 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
849 VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
850
851 /** @todo Test how it interacts with multiple screen objects. */
852 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
853 uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
854 uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
855
856 if (x < uWidth)
857 {
858 pThis->svga.viewport.x = x;
859 pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
860 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
861 }
862 else
863 {
864 pThis->svga.viewport.x = uWidth;
865 pThis->svga.viewport.cx = 0;
866 pThis->svga.viewport.xRight = uWidth;
867 }
868 if (y < uHeight)
869 {
870 pThis->svga.viewport.y = y;
871 pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
872 pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
873 pThis->svga.viewport.yHighWC = uHeight - y;
874 }
875 else
876 {
877 pThis->svga.viewport.y = uHeight;
878 pThis->svga.viewport.cy = 0;
879 pThis->svga.viewport.yLowWC = 0;
880 pThis->svga.viewport.yHighWC = 0;
881 }
882
883# ifdef VBOX_WITH_VMSVGA3D
884 /*
885 * Now inform the 3D backend.
886 */
887 if (pThis->svga.f3DEnabled)
888 vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
889# else
890 RT_NOREF(OldViewport);
891# endif
892}
893
894
895/**
896 * Updating screen information in API
897 *
898 * @param pThis The The shared VGA/VMSVGA instance data.
899 * @param pThisCC The VGA/VMSVGA state for ring-3.
900 */
901static void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
902{
903 int rc;
904
905 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
906
907 for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
908 {
909 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
910 if (!pScreen->fModified)
911 continue;
912
913 pScreen->fModified = false;
914
915 VBVAINFOVIEW view;
916 RT_ZERO(view);
917 view.u32ViewIndex = pScreen->idScreen;
918 // view.u32ViewOffset = 0;
919 view.u32ViewSize = pThis->vram_size;
920 view.u32MaxScreenSize = pThis->vram_size;
921
922 VBVAINFOSCREEN screen;
923 RT_ZERO(screen);
924 screen.u32ViewIndex = pScreen->idScreen;
925
926 if (pScreen->fDefined)
927 {
928 if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
929 || pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
930 || pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
931 {
932 Assert(pThis->svga.fGFBRegisters);
933 continue;
934 }
935
936 screen.i32OriginX = pScreen->xOrigin;
937 screen.i32OriginY = pScreen->yOrigin;
938 screen.u32StartOffset = pScreen->offVRAM;
939 screen.u32LineSize = pScreen->cbPitch;
940 screen.u32Width = pScreen->cWidth;
941 screen.u32Height = pScreen->cHeight;
942 screen.u16BitsPerPixel = pScreen->cBpp;
943 if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
944 screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
945 if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
946 screen.u16Flags |= VBVA_SCREEN_F_BLANK2;
947 }
948 else
949 {
950 /* Screen is destroyed. */
951 screen.u16Flags = VBVA_SCREEN_F_DISABLED;
952 }
953
954 void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
955 rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /*fResetInputMapping=*/ true);
956 AssertRC(rc);
957 }
958}
959
960
961/**
962 * @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
963 *
964 * Used to update screen offsets (positions) since appearently vmwgfx fails to
965 * pass correct offsets thru FIFO.
966 */
967DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
968{
969 PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
970 PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
971 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
972
973 AssertReturnVoid(pSVGAState);
974
975 /* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
976 cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
977 for (uint32_t i = 0; i < cPositions; ++i)
978 {
979 if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
980 && pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
981 continue;
982
983 if (paPositions[i].x == -1)
984 continue;
985 if (paPositions[i].y == -1)
986 continue;
987
988 pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
989 pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
990 pSVGAState->aScreens[i].fModified = true;
991 }
992
993 vmsvgaR3VBVAResize(pThis, pThisCC);
994}
995
996#endif /* IN_RING3 */
997
998/**
999 * Read port register
1000 *
1001 * @returns VBox status code.
1002 * @param pDevIns The device instance.
1003 * @param pThis The shared VGA/VMSVGA state.
1004 * @param pu32 Where to store the read value
1005 */
1006static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
1007{
1008#ifdef IN_RING3
1009 PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
1010#endif
1011 int rc = VINF_SUCCESS;
1012 *pu32 = 0;
1013
1014 /* Rough index register validation. */
1015 uint32_t idxReg = pThis->svga.u32IndexReg;
1016#if !defined(IN_RING3) && defined(VBOX_STRICT)
1017 ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1018 VINF_IOM_R3_IOPORT_READ);
1019#else
1020 ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1021 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
1022 VINF_SUCCESS);
1023#endif
1024 RT_UNTRUSTED_VALIDATED_FENCE();
1025
1026 /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1027 if ( idxReg >= SVGA_REG_ID_0_TOP
1028 && pThis->svga.u32SVGAId == SVGA_ID_0)
1029 {
1030 idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1031 Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1032 }
1033
1034 switch (idxReg)
1035 {
1036 case SVGA_REG_ID:
1037 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1038 *pu32 = pThis->svga.u32SVGAId;
1039 break;
1040
1041 case SVGA_REG_ENABLE:
1042 STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1043 *pu32 = pThis->svga.fEnabled;
1044 break;
1045
1046 case SVGA_REG_WIDTH:
1047 {
1048 STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1049 if ( pThis->svga.fEnabled
1050 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1051 *pu32 = pThis->svga.uWidth;
1052 else
1053 {
1054#ifndef IN_RING3
1055 rc = VINF_IOM_R3_IOPORT_READ;
1056#else
1057 *pu32 = pThisCC->pDrv->cx;
1058#endif
1059 }
1060 break;
1061 }
1062
1063 case SVGA_REG_HEIGHT:
1064 {
1065 STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1066 if ( pThis->svga.fEnabled
1067 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1068 *pu32 = pThis->svga.uHeight;
1069 else
1070 {
1071#ifndef IN_RING3
1072 rc = VINF_IOM_R3_IOPORT_READ;
1073#else
1074 *pu32 = pThisCC->pDrv->cy;
1075#endif
1076 }
1077 break;
1078 }
1079
1080 case SVGA_REG_MAX_WIDTH:
1081 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1082 *pu32 = pThis->svga.u32MaxWidth;
1083 break;
1084
1085 case SVGA_REG_MAX_HEIGHT:
1086 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1087 *pu32 = pThis->svga.u32MaxHeight;
1088 break;
1089
1090 case SVGA_REG_DEPTH:
1091 /* This returns the color depth of the current mode. */
1092 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1093 switch (pThis->svga.uBpp)
1094 {
1095 case 15:
1096 case 16:
1097 case 24:
1098 *pu32 = pThis->svga.uBpp;
1099 break;
1100
1101 default:
1102 case 32:
1103 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
1104 break;
1105 }
1106 break;
1107
1108 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1109 STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1110 *pu32 = pThis->svga.uHostBpp;
1111 break;
1112
1113 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1114 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1115 *pu32 = pThis->svga.uBpp;
1116 break;
1117
1118 case SVGA_REG_PSEUDOCOLOR:
1119 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1120 *pu32 = pThis->svga.uBpp == 8; /* See section 6 "Pseudocolor" in svga_interface.txt. */
1121 break;
1122
1123 case SVGA_REG_RED_MASK:
1124 case SVGA_REG_GREEN_MASK:
1125 case SVGA_REG_BLUE_MASK:
1126 {
1127 uint32_t uBpp;
1128
1129 if (pThis->svga.fEnabled)
1130 uBpp = pThis->svga.uBpp;
1131 else
1132 uBpp = pThis->svga.uHostBpp;
1133
1134 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1135 switch (uBpp)
1136 {
1137 case 8:
1138 u32RedMask = 0x07;
1139 u32GreenMask = 0x38;
1140 u32BlueMask = 0xc0;
1141 break;
1142
1143 case 15:
1144 u32RedMask = 0x0000001f;
1145 u32GreenMask = 0x000003e0;
1146 u32BlueMask = 0x00007c00;
1147 break;
1148
1149 case 16:
1150 u32RedMask = 0x0000001f;
1151 u32GreenMask = 0x000007e0;
1152 u32BlueMask = 0x0000f800;
1153 break;
1154
1155 case 24:
1156 case 32:
1157 default:
1158 u32RedMask = 0x00ff0000;
1159 u32GreenMask = 0x0000ff00;
1160 u32BlueMask = 0x000000ff;
1161 break;
1162 }
1163 switch (idxReg)
1164 {
1165 case SVGA_REG_RED_MASK:
1166 STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1167 *pu32 = u32RedMask;
1168 break;
1169
1170 case SVGA_REG_GREEN_MASK:
1171 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1172 *pu32 = u32GreenMask;
1173 break;
1174
1175 case SVGA_REG_BLUE_MASK:
1176 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1177 *pu32 = u32BlueMask;
1178 break;
1179 }
1180 break;
1181 }
1182
1183 case SVGA_REG_BYTES_PER_LINE:
1184 {
1185 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1186 if ( pThis->svga.fEnabled
1187 && pThis->svga.cbScanline)
1188 *pu32 = pThis->svga.cbScanline;
1189 else
1190 {
1191#ifndef IN_RING3
1192 rc = VINF_IOM_R3_IOPORT_READ;
1193#else
1194 *pu32 = pThisCC->pDrv->cbScanline;
1195#endif
1196 }
1197 break;
1198 }
1199
1200 case SVGA_REG_VRAM_SIZE: /* VRAM size */
1201 STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1202 *pu32 = pThis->vram_size;
1203 break;
1204
1205 case SVGA_REG_FB_START: /* Frame buffer physical address. */
1206 STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1207 Assert(pThis->GCPhysVRAM <= 0xffffffff);
1208 *pu32 = pThis->GCPhysVRAM;
1209 break;
1210
1211 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1212 STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1213 /* Always zero in our case. */
1214 *pu32 = 0;
1215 break;
1216
1217 case SVGA_REG_FB_SIZE: /* Frame buffer size */
1218 {
1219#ifndef IN_RING3
1220 rc = VINF_IOM_R3_IOPORT_READ;
1221#else
1222 STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1223
1224 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1225 if ( pThis->svga.fEnabled
1226 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1227 {
1228 /* Hardware enabled; return real framebuffer size .*/
1229 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
1230 }
1231 else
1232 *pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy * pThisCC->pDrv->cbScanline);
1233
1234 *pu32 = RT_MIN(pThis->vram_size, *pu32);
1235 Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1236#endif
1237 break;
1238 }
1239
1240 case SVGA_REG_CAPABILITIES:
1241 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1242 *pu32 = pThis->svga.u32DeviceCaps;
1243 break;
1244
1245 case SVGA_REG_MEM_START: /* FIFO start */
1246 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1247 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1248 *pu32 = pThis->svga.GCPhysFIFO;
1249 break;
1250
1251 case SVGA_REG_MEM_SIZE: /* FIFO size */
1252 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1253 *pu32 = pThis->svga.cbFIFO;
1254 break;
1255
1256 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1257 STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1258 *pu32 = pThis->svga.fConfigured;
1259 break;
1260
1261 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1262 STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1263 *pu32 = 0;
1264 break;
1265
1266 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1267 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1268 if (pThis->svga.fBusy)
1269 {
1270#ifndef IN_RING3
1271 /* Go to ring-3 and halt the CPU. */
1272 rc = VINF_IOM_R3_IOPORT_READ;
1273 RT_NOREF(pDevIns);
1274 break;
1275#else /* IN_RING3 */
1276# if defined(VMSVGA_USE_EMT_HALT_CODE)
1277 /* The guest is basically doing a HLT via the device here, but with
1278 a special wake up condition on FIFO completion. */
1279 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1280 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1281 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1282 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1283 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1284 if (pThis->svga.fBusy)
1285 {
1286 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1287 rc = PDMDevHlpVMWaitForDeviceReady(pDevIns, idCpu);
1288 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1289 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1290 }
1291 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1292 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1293# else
1294
1295 /* Delay the EMT a bit so the FIFO and others can get some work done.
1296 This used to be a crude 50 ms sleep. The current code tries to be
1297 more efficient, but the consept is still very crude. */
1298 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1299 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1300 RTThreadYield();
1301 if (pThis->svga.fBusy)
1302 {
1303 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1304
1305 if (pThis->svga.fBusy && cRefs == 1)
1306 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1307 if (pThis->svga.fBusy)
1308 {
1309 /** @todo If this code is going to stay, we need to call into the halt/wait
1310 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1311 * suffer when the guest is polling on a busy FIFO. */
1312 uint64_t uIgnored1, uIgnored2;
1313 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1314 if (cNsMaxWait >= RT_NS_100US)
1315 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1316 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
1317 RT_MIN(cNsMaxWait, RT_NS_10MS));
1318 }
1319
1320 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1321 }
1322 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1323# endif
1324 *pu32 = pThis->svga.fBusy != 0;
1325#endif /* IN_RING3 */
1326 }
1327 else
1328 *pu32 = false;
1329 break;
1330
1331 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1332 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1333 *pu32 = pThis->svga.u32GuestId;
1334 break;
1335
1336 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1337 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1338 *pu32 = pThis->svga.cScratchRegion;
1339 break;
1340
1341 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1342 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1343 *pu32 = SVGA_FIFO_NUM_REGS;
1344 break;
1345
1346 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1347 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1348 *pu32 = pThis->svga.u32PitchLock;
1349 break;
1350
1351 case SVGA_REG_IRQMASK: /* Interrupt mask */
1352 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1353 *pu32 = pThis->svga.u32IrqMask;
1354 break;
1355
1356 /* See "Guest memory regions" below. */
1357 case SVGA_REG_GMR_ID:
1358 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1359 *pu32 = pThis->svga.u32CurrentGMRId;
1360 break;
1361
1362 case SVGA_REG_GMR_DESCRIPTOR:
1363 STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1364 /* Write only */
1365 *pu32 = 0;
1366 break;
1367
1368 case SVGA_REG_GMR_MAX_IDS:
1369 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1370 *pu32 = pThis->svga.cGMR;
1371 break;
1372
1373 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1374 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1375 *pu32 = VMSVGA_MAX_GMR_PAGES;
1376 break;
1377
1378 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1379 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1380 *pu32 = pThis->svga.fTraces;
1381 break;
1382
1383 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1384 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1385 *pu32 = VMSVGA_MAX_GMR_PAGES;
1386 break;
1387
1388 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1389 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1390 *pu32 = VMSVGA_SURFACE_SIZE;
1391 break;
1392
1393 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1394 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1395 break;
1396
1397 /* Mouse cursor support. */
1398 case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1399 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1400 *pu32 = pThis->svga.uCursorID;
1401 break;
1402
1403 case SVGA_REG_CURSOR_X:
1404 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1405 *pu32 = pThis->svga.uCursorX;
1406 break;
1407
1408 case SVGA_REG_CURSOR_Y:
1409 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1410 *pu32 = pThis->svga.uCursorY;
1411 break;
1412
1413 case SVGA_REG_CURSOR_ON:
1414 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1415 *pu32 = pThis->svga.uCursorOn;
1416 break;
1417
1418 /* Legacy multi-monitor support */
1419 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1420 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1421 *pu32 = 1;
1422 break;
1423
1424 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1425 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1426 *pu32 = 0;
1427 break;
1428
1429 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1430 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1431 *pu32 = 0;
1432 break;
1433
1434 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1435 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1436 *pu32 = 0;
1437 break;
1438
1439 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1440 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1441 *pu32 = 0;
1442 break;
1443
1444 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1445 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1446 *pu32 = pThis->svga.uWidth;
1447 break;
1448
1449 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1450 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1451 *pu32 = pThis->svga.uHeight;
1452 break;
1453
1454 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1455 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1456 /* We must return something sensible here otherwise the Linux driver
1457 will take a legacy code path without 3d support. This number also
1458 limits how many screens Linux guests will allow. */
1459 *pu32 = pThis->cMonitors;
1460 break;
1461
1462 /*
1463 * SVGA_CAP_GBOBJECTS+ registers.
1464 */
1465 case SVGA_REG_COMMAND_LOW:
1466 /* Lower 32 bits of command buffer physical address. */
1467 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1468 *pu32 = pThis->svga.u32RegCommandLow;
1469 break;
1470
1471 case SVGA_REG_COMMAND_HIGH:
1472 /* Upper 32 bits of command buffer PA. */
1473 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1474 *pu32 = pThis->svga.u32RegCommandHigh;
1475 break;
1476
1477 case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1478 /* Max primary (screen) memory. */
1479 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1480 *pu32 = pThis->vram_size; /** @todo Maybe half VRAM? */
1481 break;
1482
1483 case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1484 /* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1485 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1486 *pu32 = pThis->vram_size / 1024;
1487 break;
1488
1489 case SVGA_REG_DEV_CAP:
1490 /* Write dev cap index, read value */
1491 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1492 if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1493 {
1494 RT_UNTRUSTED_VALIDATED_FENCE();
1495 *pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1496 }
1497 else
1498 *pu32 = 0;
1499 break;
1500
1501 case SVGA_REG_CMD_PREPEND_LOW:
1502 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1503 *pu32 = 0; /* Not supported. */
1504 break;
1505
1506 case SVGA_REG_CMD_PREPEND_HIGH:
1507 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1508 *pu32 = 0; /* Not supported. */
1509 break;
1510
1511 case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1512 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1513 *pu32 = pThis->svga.u32MaxWidth;
1514 break;
1515
1516 case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1517 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1518 *pu32 = pThis->svga.u32MaxHeight;
1519 break;
1520
1521 case SVGA_REG_MOB_MAX_SIZE:
1522 /* Essentially the max texture size */
1523 STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1524 *pu32 = _128M; /** @todo Some actual value. Probably the mapped VRAM size. */
1525 break;
1526
1527 case SVGA_REG_BLANK_SCREEN_TARGETS:
1528 /// @todo STAM_REL_COUNTER_INC(&pThis->svga.aStatRegRd[idxReg]);
1529 *pu32 = 0; /* Not supported. */
1530 break;
1531
1532 case SVGA_REG_CAP2:
1533 *pu32 = pThis->svga.u32DeviceCaps2;
1534 break;
1535
1536 case SVGA_REG_DEVEL_CAP:
1537 *pu32 = 0; /* Not supported. */
1538 break;
1539
1540 /*
1541 * SVGA_REG_GUEST_DRIVER_* registers require SVGA_CAP2_DX2.
1542 */
1543 case SVGA_REG_GUEST_DRIVER_ID:
1544 *pu32 = pThis->svga.u32GuestDriverId;
1545 break;
1546
1547 case SVGA_REG_GUEST_DRIVER_VERSION1:
1548 *pu32 = pThis->svga.u32GuestDriverVer1;
1549 break;
1550
1551 case SVGA_REG_GUEST_DRIVER_VERSION2:
1552 *pu32 = pThis->svga.u32GuestDriverVer2;
1553 break;
1554
1555 case SVGA_REG_GUEST_DRIVER_VERSION3:
1556 *pu32 = pThis->svga.u32GuestDriverVer3;
1557 break;
1558
1559 /*
1560 * SVGA_REG_CURSOR_ registers require SVGA_CAP2_CURSOR_MOB which the device does not support currently.
1561 */
1562 case SVGA_REG_CURSOR_MOBID:
1563 *pu32 = SVGA_ID_INVALID;
1564 break;
1565
1566 case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
1567 *pu32 = 0;
1568 break;
1569
1570 case SVGA_REG_CURSOR_MAX_DIMENSION:
1571 *pu32 = 0;
1572 break;
1573
1574 case SVGA_REG_FIFO_CAPS:
1575 case SVGA_REG_FENCE: /* Same as SVGA_FIFO_FENCE for PCI_ID_SVGA3. Our device is PCI_ID_SVGA2 so not supported. */
1576 case SVGA_REG_RESERVED1: /* SVGA_REG_RESERVED* correspond to SVGA_REG_CURSOR4_*. Require SVGA_CAP2_EXTRA_REGS. */
1577 case SVGA_REG_RESERVED2:
1578 case SVGA_REG_RESERVED3:
1579 case SVGA_REG_RESERVED4:
1580 case SVGA_REG_RESERVED5:
1581 case SVGA_REG_SCREENDMA:
1582 *pu32 = 0; /* Not supported. */
1583 break;
1584
1585 case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
1586 /** @todo "The maximum amount of guest-backed objects that the device can have resident at a time" */
1587 *pu32 = _1G / _1K;
1588 break;
1589
1590 default:
1591 {
1592 uint32_t offReg;
1593 if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1594 {
1595 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1596 RT_UNTRUSTED_VALIDATED_FENCE();
1597 *pu32 = pThis->svga.au32ScratchRegion[offReg];
1598 }
1599 else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1600 {
1601 /* Note! Using last_palette rather than palette here to preserve the VGA one. */
1602 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1603 RT_UNTRUSTED_VALIDATED_FENCE();
1604 uint32_t u32 = pThis->last_palette[offReg / 3];
1605 switch (offReg % 3)
1606 {
1607 case 0: *pu32 = (u32 >> 16) & 0xff; break; /* red */
1608 case 1: *pu32 = (u32 >> 8) & 0xff; break; /* green */
1609 case 2: *pu32 = u32 & 0xff; break; /* blue */
1610 }
1611 }
1612 else
1613 {
1614#if !defined(IN_RING3) && defined(VBOX_STRICT)
1615 rc = VINF_IOM_R3_IOPORT_READ;
1616#else
1617 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1618
1619 /* Do not assert. The guest might be reading all registers. */
1620 LogFunc(("Unknown reg=%#x\n", idxReg));
1621#endif
1622 }
1623 break;
1624 }
1625 }
1626 LogFlow(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1627 return rc;
1628}
1629
1630#ifdef IN_RING3
1631/**
1632 * Apply the current resolution settings to change the video mode.
1633 *
1634 * @returns VBox status code.
1635 * @param pThis The shared VGA state.
1636 * @param pThisCC The ring-3 VGA state.
1637 */
1638int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1639{
1640 /* Always do changemode on FIFO thread. */
1641 Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1642
1643 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1644
1645 pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1646
1647 if (pThis->svga.fGFBRegisters)
1648 {
1649 /* "For backwards compatibility, when the GFB mode registers (WIDTH,
1650 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1651 * deletes all screens other than screen #0, and redefines screen
1652 * #0 according to the specified mode. Drivers that use
1653 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1654 */
1655
1656 VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1657 pScreen->fDefined = true;
1658 pScreen->fModified = true;
1659 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET | SVGA_SCREEN_IS_PRIMARY;
1660 pScreen->idScreen = 0;
1661 pScreen->xOrigin = 0;
1662 pScreen->yOrigin = 0;
1663 pScreen->offVRAM = 0;
1664 pScreen->cbPitch = pThis->svga.cbScanline;
1665 pScreen->cWidth = pThis->svga.uWidth;
1666 pScreen->cHeight = pThis->svga.uHeight;
1667 pScreen->cBpp = pThis->svga.uBpp;
1668
1669 for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1670 {
1671 /* Delete screen. */
1672 pScreen = &pSVGAState->aScreens[iScreen];
1673 if (pScreen->fDefined)
1674 {
1675 pScreen->fModified = true;
1676 pScreen->fDefined = false;
1677 }
1678 }
1679 }
1680 else
1681 {
1682 /* "If Screen Objects are supported, they can be used to fully
1683 * replace the functionality provided by the framebuffer registers
1684 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1685 */
1686 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1687 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1688 pThis->svga.uBpp = pThis->svga.uHostBpp;
1689 }
1690
1691 vmsvgaR3VBVAResize(pThis, pThisCC);
1692
1693 /* Last stuff. For the VGA device screenshot. */
1694 pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1695 pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1696 pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1697 pThis->last_width = pSVGAState->aScreens[0].cWidth;
1698 pThis->last_height = pSVGAState->aScreens[0].cHeight;
1699
1700 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1701 if ( pThis->svga.viewport.cx == 0
1702 && pThis->svga.viewport.cy == 0)
1703 {
1704 pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1705 pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1706 pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1707 pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1708 pThis->svga.viewport.yLowWC = 0;
1709 }
1710
1711 return VINF_SUCCESS;
1712}
1713
1714int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1715{
1716 ASSERT_GUEST_LOGREL_MSG_RETURN(w > 0 && h > 0,
1717 ("vmsvgaR3UpdateScreen: screen %d (%d,%d) %dx%d: Invalid height and/or width supplied.\n",
1718 pScreen->idScreen, x, y, w, h),
1719 VERR_INVALID_PARAMETER);
1720
1721 VBVACMDHDR cmd;
1722 cmd.x = (int16_t)(pScreen->xOrigin + x);
1723 cmd.y = (int16_t)(pScreen->yOrigin + y);
1724 cmd.w = (uint16_t)w;
1725 cmd.h = (uint16_t)h;
1726
1727 pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1728 pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1729 pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1730 pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1731
1732 return VINF_SUCCESS;
1733}
1734
1735#endif /* IN_RING3 */
1736#if defined(IN_RING0) || defined(IN_RING3)
1737
1738/**
1739 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1740 *
1741 * @param pThis The shared VGA/VMSVGA instance data.
1742 * @param pThisCC The VGA/VMSVGA state for the current context.
1743 * @param fState The busy state.
1744 */
1745DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1746{
1747 ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1748
1749 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1750 {
1751 /* Race / unfortunately scheduling. Highly unlikly. */
1752 uint32_t cLoops = 64;
1753 do
1754 {
1755 ASMNopPause();
1756 fState = (pThis->svga.fBusy != 0);
1757 ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1758 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1759 }
1760}
1761
1762
1763/**
1764 * Update the scanline pitch in response to the guest changing mode
1765 * width/bpp.
1766 *
1767 * @param pThis The shared VGA/VMSVGA state.
1768 * @param pThisCC The VGA/VMSVGA state for the current context.
1769 */
1770DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1771{
1772 uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1773 uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1774 uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1775 uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1776
1777 /* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1778 * it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1779 * location but it has a different meaning.
1780 */
1781 if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1782 uFifoPitchLock = 0;
1783
1784 /* Sanitize values. */
1785 if ((uFifoPitchLock < 200) || (uFifoPitchLock > 32768))
1786 uFifoPitchLock = 0;
1787 if ((uRegPitchLock < 200) || (uRegPitchLock > 32768))
1788 uRegPitchLock = 0;
1789
1790 /* Prefer the register value to the FIFO value.*/
1791 if (uRegPitchLock)
1792 pThis->svga.cbScanline = uRegPitchLock;
1793 else if (uFifoPitchLock)
1794 pThis->svga.cbScanline = uFifoPitchLock;
1795 else
1796 pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1797
1798 if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1799 pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1800}
1801
1802#endif /* IN_RING0 || IN_RING3 */
1803
1804#ifdef IN_RING3
1805
1806/**
1807 * Sends cursor position and visibility information from legacy
1808 * SVGA registers to the front-end.
1809 */
1810static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1811{
1812 /*
1813 * Writing the X/Y/ID registers does not trigger changes; only writing the
1814 * SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1815 * We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1816 * register if they don't have to.
1817 */
1818 uint32_t x, y, idScreen;
1819 uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1820
1821 x = pThis->svga.uCursorX;
1822 y = pThis->svga.uCursorY;
1823 idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1824
1825 /* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1826 * were extended as follows:
1827 *
1828 * SVGA_CURSOR_ON_HIDE 0
1829 * SVGA_CURSOR_ON_SHOW 1
1830 * SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1831 * SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1832 *
1833 * Since we never draw the cursor into the guest's framebuffer, we do not need to
1834 * distinguish between the non-zero values but still remember them.
1835 */
1836 if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1837 {
1838 LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1839 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1840 }
1841 pThis->svga.uCursorOn = uCursorOn;
1842 pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1843}
1844
1845#endif /* IN_RING3 */
1846
1847
1848/**
1849 * Write port register
1850 *
1851 * @returns Strict VBox status code.
1852 * @param pDevIns The device instance.
1853 * @param pThis The shared VGA/VMSVGA state.
1854 * @param pThisCC The VGA/VMSVGA state for the current context.
1855 * @param u32 Value to write
1856 */
1857static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1858{
1859#ifdef IN_RING3
1860 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1861#endif
1862 VBOXSTRICTRC rc = VINF_SUCCESS;
1863 RT_NOREF(pThisCC);
1864
1865 /* Rough index register validation. */
1866 uint32_t idxReg = pThis->svga.u32IndexReg;
1867#if !defined(IN_RING3) && defined(VBOX_STRICT)
1868 ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1869 VINF_IOM_R3_IOPORT_WRITE);
1870#else
1871 ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1872 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1873 VINF_SUCCESS);
1874#endif
1875 RT_UNTRUSTED_VALIDATED_FENCE();
1876
1877 /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1878 if ( idxReg >= SVGA_REG_ID_0_TOP
1879 && pThis->svga.u32SVGAId == SVGA_ID_0)
1880 {
1881 idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1882 Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1883 }
1884#ifdef LOG_ENABLED
1885 if (idxReg != SVGA_REG_DEV_CAP)
1886 LogFlow(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1887 else
1888 LogFlow(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1889#endif
1890 /* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1891 switch (idxReg)
1892 {
1893 case SVGA_REG_WIDTH:
1894 case SVGA_REG_HEIGHT:
1895 case SVGA_REG_PITCHLOCK:
1896 case SVGA_REG_BITS_PER_PIXEL:
1897 pThis->svga.fGFBRegisters = true;
1898 break;
1899 default:
1900 break;
1901 }
1902
1903 switch (idxReg)
1904 {
1905 case SVGA_REG_ID:
1906 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1907 if ( u32 == SVGA_ID_0
1908 || u32 == SVGA_ID_1
1909 || u32 == SVGA_ID_2)
1910 pThis->svga.u32SVGAId = u32;
1911 else
1912 PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1913 break;
1914
1915 case SVGA_REG_ENABLE:
1916 STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1917#ifdef IN_RING3
1918 if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1919 && pThis->svga.fEnabled == false)
1920 {
1921 /* Make a backup copy of the first 512kb in order to save font data etc. */
1922 /** @todo should probably swap here, rather than copy + zero */
1923 memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1924 memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1925 }
1926
1927 pThis->svga.fEnabled = u32;
1928 if (pThis->svga.fEnabled)
1929 {
1930 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1931 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1932 {
1933 /* Keep the current mode. */
1934 pThis->svga.uWidth = pThisCC->pDrv->cx;
1935 pThis->svga.uHeight = pThisCC->pDrv->cy;
1936 pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1937 vmsvgaHCUpdatePitch(pThis, pThisCC);
1938 }
1939
1940 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1941 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1942 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1943# ifdef LOG_ENABLED
1944 uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1945 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1946 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1947# endif
1948
1949 /* Disable or enable dirty page tracking according to the current fTraces value. */
1950 vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1951
1952 /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1953 for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1954 pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /*pHostFlags*/);
1955
1956 /* Make the cursor visible again as needed. */
1957 if (pSVGAState->Cursor.fActive)
1958 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, false, 0, 0, 0, 0, NULL);
1959 }
1960 else
1961 {
1962 /* Make sure the cursor is off. */
1963 if (pSVGAState->Cursor.fActive)
1964 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /*fVisible*/, false, 0, 0, 0, 0, NULL);
1965
1966 /* Restore the text mode backup. */
1967 memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1968
1969 pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1970
1971 /* Enable dirty page tracking again when going into legacy mode. */
1972 vmsvgaR3SetTraces(pDevIns, pThis, true);
1973
1974 /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1975 for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1976 pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1977
1978 /* Clear the pitch lock. */
1979 pThis->svga.u32PitchLock = 0;
1980 }
1981#else /* !IN_RING3 */
1982 rc = VINF_IOM_R3_IOPORT_WRITE;
1983#endif /* !IN_RING3 */
1984 break;
1985
1986 case SVGA_REG_WIDTH:
1987 STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1988 if (u32 != pThis->svga.uWidth)
1989 {
1990 if (u32 <= pThis->svga.u32MaxWidth)
1991 {
1992#if defined(IN_RING3) || defined(IN_RING0)
1993 pThis->svga.uWidth = u32;
1994 vmsvgaHCUpdatePitch(pThis, pThisCC);
1995 if (pThis->svga.fEnabled)
1996 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1997#else
1998 rc = VINF_IOM_R3_IOPORT_WRITE;
1999#endif
2000 }
2001 else
2002 Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
2003 }
2004 /* else: nop */
2005 break;
2006
2007 case SVGA_REG_HEIGHT:
2008 STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
2009 if (u32 != pThis->svga.uHeight)
2010 {
2011 if (u32 <= pThis->svga.u32MaxHeight)
2012 {
2013 pThis->svga.uHeight = u32;
2014 if (pThis->svga.fEnabled)
2015 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2016 }
2017 else
2018 Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
2019 }
2020 /* else: nop */
2021 break;
2022
2023 case SVGA_REG_DEPTH:
2024 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
2025 /** @todo read-only?? */
2026 break;
2027
2028 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
2029 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
2030 if (pThis->svga.uBpp != u32)
2031 {
2032 if (u32 <= 32)
2033 {
2034#if defined(IN_RING3) || defined(IN_RING0)
2035 pThis->svga.uBpp = u32;
2036 vmsvgaHCUpdatePitch(pThis, pThisCC);
2037 if (pThis->svga.fEnabled)
2038 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
2039#else
2040 rc = VINF_IOM_R3_IOPORT_WRITE;
2041#endif
2042 }
2043 else
2044 Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
2045 }
2046 /* else: nop */
2047 break;
2048
2049 case SVGA_REG_PSEUDOCOLOR:
2050 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
2051 break;
2052
2053 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
2054#ifdef IN_RING3
2055 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
2056 pThis->svga.fConfigured = u32;
2057 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
2058 if (!pThis->svga.fConfigured)
2059 pThis->svga.fTraces = true;
2060 vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
2061#else
2062 rc = VINF_IOM_R3_IOPORT_WRITE;
2063#endif
2064 break;
2065
2066 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
2067 STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
2068 if ( pThis->svga.fEnabled
2069 && pThis->svga.fConfigured)
2070 {
2071#if defined(IN_RING3) || defined(IN_RING0)
2072 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
2073 /*
2074 * The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
2075 * at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
2076 */
2077 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
2078 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
2079 vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
2080
2081 /* Kick the FIFO thread to start processing commands again. */
2082 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2083#else
2084 rc = VINF_IOM_R3_IOPORT_WRITE;
2085#endif
2086 }
2087 /* else nothing to do. */
2088 else
2089 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
2090
2091 break;
2092
2093 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
2094 STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
2095 break;
2096
2097 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
2098 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
2099 pThis->svga.u32GuestId = u32;
2100 break;
2101
2102 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
2103 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
2104 pThis->svga.u32PitchLock = u32;
2105 /* Should this also update the FIFO pitch lock? Unclear. */
2106 break;
2107
2108 case SVGA_REG_IRQMASK: /* Interrupt mask */
2109 STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
2110 pThis->svga.u32IrqMask = u32;
2111
2112 /* Irq pending after the above change? */
2113 if (pThis->svga.u32IrqStatus & u32)
2114 {
2115 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2116 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2117 }
2118 else
2119 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2120 break;
2121
2122 /* Mouse cursor support */
2123 case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2124 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2125 pThis->svga.uCursorID = u32;
2126 break;
2127
2128 case SVGA_REG_CURSOR_X:
2129 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2130 pThis->svga.uCursorX = u32;
2131 break;
2132
2133 case SVGA_REG_CURSOR_Y:
2134 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2135 pThis->svga.uCursorY = u32;
2136 break;
2137
2138 case SVGA_REG_CURSOR_ON:
2139#ifdef IN_RING3
2140 /* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2141 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2142 vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2143#else
2144 rc = VINF_IOM_R3_IOPORT_WRITE;
2145#endif
2146 break;
2147
2148 /* Legacy multi-monitor support */
2149 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2150 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2151 break;
2152 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2153 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2154 break;
2155 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2156 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2157 break;
2158 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2159 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2160 break;
2161 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2162 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2163 break;
2164 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2165 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2166 break;
2167 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2168 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2169 break;
2170#ifdef VBOX_WITH_VMSVGA3D
2171 /* See "Guest memory regions" below. */
2172 case SVGA_REG_GMR_ID:
2173 STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2174 pThis->svga.u32CurrentGMRId = u32;
2175 break;
2176
2177 case SVGA_REG_GMR_DESCRIPTOR:
2178# ifndef IN_RING3
2179 rc = VINF_IOM_R3_IOPORT_WRITE;
2180 break;
2181# else /* IN_RING3 */
2182 {
2183 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2184
2185 /* Validate current GMR id. */
2186 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2187 AssertBreak(idGMR < pThis->svga.cGMR);
2188 RT_UNTRUSTED_VALIDATED_FENCE();
2189
2190 /* Free the old GMR if present. */
2191 vmsvgaR3GmrFree(pThisCC, idGMR);
2192
2193 /* Just undefine the GMR? */
2194 RTGCPHYS GCPhys = (RTGCPHYS)u32 << GUEST_PAGE_SHIFT;
2195 if (GCPhys == 0)
2196 {
2197 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2198 break;
2199 }
2200
2201
2202 /* Never cross a page boundary automatically. */
2203 const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2204 uint32_t cPagesTotal = 0;
2205 uint32_t iDesc = 0;
2206 PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2207 uint32_t cLoops = 0;
2208 RTGCPHYS GCPhysBase = GCPhys;
2209 while ((GCPhys >> GUEST_PAGE_SHIFT) == (GCPhysBase >> GUEST_PAGE_SHIFT))
2210 {
2211 /* Read descriptor. */
2212 SVGAGuestMemDescriptor desc;
2213 rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2214 AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2215
2216 if (desc.numPages != 0)
2217 {
2218 AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2219 cPagesTotal += desc.numPages;
2220 AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2221
2222 if ((iDesc & 15) == 0)
2223 {
2224 void *pvNew = RTMemRealloc(paDescs, (iDesc + 16) * sizeof(VMSVGAGMRDESCRIPTOR));
2225 AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2226 paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2227 }
2228
2229 paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2230 paDescs[iDesc++].numPages = desc.numPages;
2231
2232 /* Continue with the next descriptor. */
2233 GCPhys += sizeof(desc);
2234 }
2235 else if (desc.ppn == 0)
2236 break; /* terminator */
2237 else /* Pointer to the next physical page of descriptors. */
2238 GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << GUEST_PAGE_SHIFT;
2239
2240 cLoops++;
2241 AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2242 }
2243
2244 AssertStmt(iDesc > 0 || RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2245 if (RT_SUCCESS(rc))
2246 {
2247 /* Commit the GMR. */
2248 pSVGAState->paGMR[idGMR].paDesc = paDescs;
2249 pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2250 pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2251 pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * GUEST_PAGE_SIZE;
2252 Assert((pSVGAState->paGMR[idGMR].cbTotal >> GUEST_PAGE_SHIFT) == cPagesTotal);
2253 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2254 idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2255 }
2256 else
2257 {
2258 RTMemFree(paDescs);
2259 STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2260 }
2261 break;
2262 }
2263# endif /* IN_RING3 */
2264#endif // VBOX_WITH_VMSVGA3D
2265
2266 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2267 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2268 if (pThis->svga.fTraces == u32)
2269 break; /* nothing to do */
2270
2271#ifdef IN_RING3
2272 vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2273#else
2274 rc = VINF_IOM_R3_IOPORT_WRITE;
2275#endif
2276 break;
2277
2278 case SVGA_REG_TOP: /* Must be 1 more than the last register */
2279 STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2280 break;
2281
2282 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2283 STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2284 Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2285 break;
2286
2287 /*
2288 * SVGA_CAP_GBOBJECTS+ registers.
2289 */
2290 case SVGA_REG_COMMAND_LOW:
2291 {
2292 /* Lower 32 bits of command buffer physical address and submit the command buffer. */
2293#ifdef IN_RING3
2294 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2295 pThis->svga.u32RegCommandLow = u32;
2296
2297 /* "lower 6 bits are used for the SVGACBContext" */
2298 RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2299 GCPhysCB <<= 32;
2300 GCPhysCB |= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2301 SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2302 vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2303#else
2304 rc = VINF_IOM_R3_IOPORT_WRITE;
2305#endif
2306 break;
2307 }
2308
2309 case SVGA_REG_COMMAND_HIGH:
2310 /* Upper 32 bits of command buffer PA. */
2311 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2312 pThis->svga.u32RegCommandHigh = u32;
2313 break;
2314
2315 case SVGA_REG_DEV_CAP:
2316 /* Write dev cap index, read value */
2317 STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2318 pThis->svga.u32DevCapIndex = u32;
2319 break;
2320
2321 case SVGA_REG_CMD_PREPEND_LOW:
2322 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2323 /* Not supported. */
2324 break;
2325
2326 case SVGA_REG_CMD_PREPEND_HIGH:
2327 STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2328 /* Not supported. */
2329 break;
2330
2331 case SVGA_REG_GUEST_DRIVER_ID:
2332 if (u32 != SVGA_REG_GUEST_DRIVER_ID_SUBMIT)
2333 pThis->svga.u32GuestDriverId = u32;
2334 break;
2335
2336 case SVGA_REG_GUEST_DRIVER_VERSION1:
2337 pThis->svga.u32GuestDriverVer1 = u32;
2338 break;
2339
2340 case SVGA_REG_GUEST_DRIVER_VERSION2:
2341 pThis->svga.u32GuestDriverVer2 = u32;
2342 break;
2343
2344 case SVGA_REG_GUEST_DRIVER_VERSION3:
2345 pThis->svga.u32GuestDriverVer3 = u32;
2346 break;
2347
2348 case SVGA_REG_CURSOR_MOBID:
2349 /* Not supported, ignore. See correspondent comments in vmsvgaReadPort. */
2350 break;
2351
2352 case SVGA_REG_FB_START:
2353 case SVGA_REG_MEM_START:
2354 case SVGA_REG_HOST_BITS_PER_PIXEL:
2355 case SVGA_REG_MAX_WIDTH:
2356 case SVGA_REG_MAX_HEIGHT:
2357 case SVGA_REG_VRAM_SIZE:
2358 case SVGA_REG_FB_SIZE:
2359 case SVGA_REG_CAPABILITIES:
2360 case SVGA_REG_MEM_SIZE:
2361 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2362 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2363 case SVGA_REG_BYTES_PER_LINE:
2364 case SVGA_REG_FB_OFFSET:
2365 case SVGA_REG_RED_MASK:
2366 case SVGA_REG_GREEN_MASK:
2367 case SVGA_REG_BLUE_MASK:
2368 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2369 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2370 case SVGA_REG_GMR_MAX_IDS:
2371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2372 case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2373 case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2374 case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2375 case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2376 case SVGA_REG_MOB_MAX_SIZE:
2377 case SVGA_REG_BLANK_SCREEN_TARGETS:
2378 case SVGA_REG_CAP2:
2379 case SVGA_REG_DEVEL_CAP:
2380 case SVGA_REG_CURSOR_MAX_BYTE_SIZE:
2381 case SVGA_REG_CURSOR_MAX_DIMENSION:
2382 case SVGA_REG_FIFO_CAPS:
2383 case SVGA_REG_FENCE:
2384 case SVGA_REG_RESERVED1:
2385 case SVGA_REG_RESERVED2:
2386 case SVGA_REG_RESERVED3:
2387 case SVGA_REG_RESERVED4:
2388 case SVGA_REG_RESERVED5:
2389 case SVGA_REG_SCREENDMA:
2390 case SVGA_REG_GBOBJECT_MEM_SIZE_KB:
2391 /* Read only - ignore. */
2392 Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2393 STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2394 break;
2395
2396 default:
2397 {
2398 uint32_t offReg;
2399 if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2400 {
2401 RT_UNTRUSTED_VALIDATED_FENCE();
2402 pThis->svga.au32ScratchRegion[offReg] = u32;
2403 STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2404 }
2405 else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2406 {
2407 /* Note! Using last_palette rather than palette here to preserve the VGA one.
2408 Btw, see rgb_to_pixel32. */
2409 STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2410 u32 &= 0xff;
2411 RT_UNTRUSTED_VALIDATED_FENCE();
2412 uint32_t uRgb = pThis->last_palette[offReg / 3];
2413 switch (offReg % 3)
2414 {
2415 case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) | (u32 << 16); break; /* red */
2416 case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) | (u32 << 8); break; /* green */
2417 case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) | u32 ; break; /* blue */
2418 }
2419 pThis->last_palette[offReg / 3] = uRgb;
2420 }
2421 else
2422 {
2423#if !defined(IN_RING3) && defined(VBOX_STRICT)
2424 rc = VINF_IOM_R3_IOPORT_WRITE;
2425#else
2426 STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2427 AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2428#endif
2429 }
2430 break;
2431 }
2432 }
2433 return rc;
2434}
2435
2436/**
2437 * @callback_method_impl{FNIOMIOPORTNEWIN}
2438 */
2439DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2440{
2441 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2442 RT_NOREF_PV(pvUser);
2443
2444 /* Only dword accesses. */
2445 if (cb == 4)
2446 {
2447 switch (offPort)
2448 {
2449 case SVGA_INDEX_PORT:
2450 *pu32 = pThis->svga.u32IndexReg;
2451 break;
2452
2453 case SVGA_VALUE_PORT:
2454 return vmsvgaReadPort(pDevIns, pThis, pu32);
2455
2456 case SVGA_BIOS_PORT:
2457 Log(("Ignoring BIOS port read\n"));
2458 *pu32 = 0;
2459 break;
2460
2461 case SVGA_IRQSTATUS_PORT:
2462 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2463 *pu32 = pThis->svga.u32IrqStatus;
2464 break;
2465
2466 default:
2467 ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2468 *pu32 = UINT32_MAX;
2469 break;
2470 }
2471 }
2472 else
2473 {
2474 Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2475 *pu32 = UINT32_MAX;
2476 }
2477 return VINF_SUCCESS;
2478}
2479
2480/**
2481 * @callback_method_impl{FNIOMIOPORTNEWOUT}
2482 */
2483DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2484{
2485 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2486 PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2487 RT_NOREF_PV(pvUser);
2488
2489 /* Only dword accesses. */
2490 if (cb == 4)
2491 switch (offPort)
2492 {
2493 case SVGA_INDEX_PORT:
2494 pThis->svga.u32IndexReg = u32;
2495 break;
2496
2497 case SVGA_VALUE_PORT:
2498 return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2499
2500 case SVGA_BIOS_PORT:
2501 Log(("Ignoring BIOS port write (val=%x)\n", u32));
2502 break;
2503
2504 case SVGA_IRQSTATUS_PORT:
2505 LogFlow(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2506 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2507 /* Clear the irq in case all events have been cleared. */
2508 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2509 {
2510 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2511 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2512 }
2513 break;
2514
2515 default:
2516 ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2517 break;
2518 }
2519 else
2520 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2521
2522 return VINF_SUCCESS;
2523}
2524
2525#ifdef IN_RING3
2526
2527# ifdef DEBUG_FIFO_ACCESS
2528/**
2529 * Handle FIFO memory access.
2530 * @returns VBox status code.
2531 * @param pVM VM handle.
2532 * @param pThis The shared VGA/VMSVGA instance data.
2533 * @param GCPhys The access physical address.
2534 * @param fWriteAccess Read or write access
2535 */
2536static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2537{
2538 RT_NOREF(pVM);
2539 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2540 uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2541
2542 switch (GCPhysOffset >> 2)
2543 {
2544 case SVGA_FIFO_MIN:
2545 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2546 break;
2547 case SVGA_FIFO_MAX:
2548 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2549 break;
2550 case SVGA_FIFO_NEXT_CMD:
2551 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2552 break;
2553 case SVGA_FIFO_STOP:
2554 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2555 break;
2556 case SVGA_FIFO_CAPABILITIES:
2557 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2558 break;
2559 case SVGA_FIFO_FLAGS:
2560 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2561 break;
2562 case SVGA_FIFO_FENCE:
2563 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2564 break;
2565 case SVGA_FIFO_3D_HWVERSION:
2566 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2567 break;
2568 case SVGA_FIFO_PITCHLOCK:
2569 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2570 break;
2571 case SVGA_FIFO_CURSOR_ON:
2572 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2573 break;
2574 case SVGA_FIFO_CURSOR_X:
2575 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2576 break;
2577 case SVGA_FIFO_CURSOR_Y:
2578 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2579 break;
2580 case SVGA_FIFO_CURSOR_COUNT:
2581 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2582 break;
2583 case SVGA_FIFO_CURSOR_LAST_UPDATED:
2584 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2585 break;
2586 case SVGA_FIFO_RESERVED:
2587 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2588 break;
2589 case SVGA_FIFO_CURSOR_SCREEN_ID:
2590 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2591 break;
2592 case SVGA_FIFO_DEAD:
2593 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2594 break;
2595 case SVGA_FIFO_3D_HWVERSION_REVISED:
2596 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2597 break;
2598 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2599 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2600 break;
2601 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2602 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2603 break;
2604 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2605 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2606 break;
2607 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2608 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2609 break;
2610 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2611 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2612 break;
2613 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2614 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2615 break;
2616 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2617 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2618 break;
2619 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2620 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2621 break;
2622 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2623 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2624 break;
2625 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2626 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2627 break;
2628 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2629 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2630 break;
2631 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2632 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2633 break;
2634 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2635 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2636 break;
2637 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2638 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2639 break;
2640 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2641 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2642 break;
2643 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2644 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2645 break;
2646 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2647 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2648 break;
2649 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2650 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2651 break;
2652 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2653 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2654 break;
2655 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2656 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2657 break;
2658 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2659 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660 break;
2661 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2662 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663 break;
2664 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2665 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666 break;
2667 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2668 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669 break;
2670 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2671 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672 break;
2673 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2674 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675 break;
2676 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2677 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678 break;
2679 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2680 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681 break;
2682 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2683 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684 break;
2685 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2686 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687 break;
2688 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2689 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690 break;
2691 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2692 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693 break;
2694 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2695 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696 break;
2697 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2698 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699 break;
2700 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2701 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702 break;
2703 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2704 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705 break;
2706 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2707 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708 break;
2709 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2710 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711 break;
2712 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2713 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2714 break;
2715 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2716 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2717 break;
2718 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2719 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2720 break;
2721 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2722 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2723 break;
2724 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2725 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2726 break;
2727 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2728 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2729 break;
2730 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2731 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2732 break;
2733 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2734 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2735 break;
2736 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2737 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2738 break;
2739 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2740 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2741 break;
2742 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2743 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2744 break;
2745 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2746 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2747 break;
2748 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2749 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2750 break;
2751 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2752 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2753 break;
2754 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2755 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2756 break;
2757 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2758 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2759 break;
2760 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2761 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2762 break;
2763 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2764 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2765 break;
2766 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2767 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2768 break;
2769 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2770 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2771 break;
2772 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2773 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2774 break;
2775 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2776 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2777 break;
2778 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2779 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2780 break;
2781 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2782 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2783 break;
2784 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2785 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2786 break;
2787 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2788 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2789 break;
2790 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2791 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2792 break;
2793 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2794 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2795 break;
2796 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2797 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2798 break;
2799 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2800 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2801 break;
2802 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2803 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2804 break;
2805 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2806 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2807 break;
2808 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2809 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2810 break;
2811 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2812 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2813 break;
2814 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2815 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2816 break;
2817 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2818 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2819 break;
2820 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2821 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2822 break;
2823 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2824 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2825 break;
2826 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2827 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2828 break;
2829 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2830 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2831 break;
2832 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2833 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2834 break;
2835 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2836 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2837 break;
2838 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2839 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2840 break;
2841 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2842 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2843 break;
2844 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2845 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2846 break;
2847 case SVGA_FIFO_3D_CAPS_LAST:
2848 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2849 break;
2850 case SVGA_FIFO_GUEST_3D_HWVERSION:
2851 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2852 break;
2853 case SVGA_FIFO_FENCE_GOAL:
2854 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2855 break;
2856 case SVGA_FIFO_BUSY:
2857 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2858 break;
2859 default:
2860 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2861 break;
2862 }
2863
2864 return VINF_EM_RAW_EMULATE_INSTR;
2865}
2866# endif /* DEBUG_FIFO_ACCESS */
2867
2868# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
2869/**
2870 * HC access handler for the FIFO.
2871 *
2872 * @returns VINF_SUCCESS if the handler have carried out the operation.
2873 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2874 * @param pVM VM Handle.
2875 * @param pVCpu The cross context CPU structure for the calling EMT.
2876 * @param GCPhys The physical address the guest is writing to.
2877 * @param pvPhys The HC mapping of that address.
2878 * @param pvBuf What the guest is reading/writing.
2879 * @param cbBuf How much it's reading/writing.
2880 * @param enmAccessType The access type.
2881 * @param enmOrigin Who is making the access.
2882 * @param pvUser User argument.
2883 */
2884static DECLCALLBACK(VBOXSTRICTRC)
2885vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
2886 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2887{
2888 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2889 PVGASTATE pThis = (PVGASTATE)pvUser;
2890 AssertPtr(pThis);
2891
2892# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2893 /*
2894 * Wake up the FIFO thread as it might have work to do now.
2895 */
2896 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2897 AssertLogRelRC(rc);
2898# endif
2899
2900# ifdef DEBUG_FIFO_ACCESS
2901 /*
2902 * When in debug-fifo-access mode, we do not disable the access handler,
2903 * but leave it on as we wish to catch all access.
2904 */
2905 Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2906 rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2907# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2908 /*
2909 * Temporarily disable the access handler now that we've kicked the FIFO thread.
2910 */
2911 STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2912 rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2913# endif
2914 if (RT_SUCCESS(rc))
2915 return VINF_PGM_HANDLER_DO_DEFAULT;
2916 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2917 return rc;
2918}
2919# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER || DEBUG_FIFO_ACCESS */
2920
2921#endif /* IN_RING3 */
2922
2923#ifdef DEBUG_GMR_ACCESS
2924# ifdef IN_RING3
2925
2926/**
2927 * HC access handler for GMRs.
2928 *
2929 * @returns VINF_SUCCESS if the handler have carried out the operation.
2930 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2931 * @param pVM VM Handle.
2932 * @param pVCpu The cross context CPU structure for the calling EMT.
2933 * @param GCPhys The physical address the guest is writing to.
2934 * @param pvPhys The HC mapping of that address.
2935 * @param pvBuf What the guest is reading/writing.
2936 * @param cbBuf How much it's reading/writing.
2937 * @param enmAccessType The access type.
2938 * @param enmOrigin Who is making the access.
2939 * @param pvUser User argument.
2940 */
2941static DECLCALLBACK(VBOXSTRICTRC)
2942vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
2943 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2944{
2945 PVGASTATE pThis = (PVGASTATE)pvUser;
2946 Assert(pThis);
2947 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2948 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2949
2950 Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2951
2952 for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2953 {
2954 PGMR pGMR = &pSVGAState->paGMR[i];
2955
2956 if (pGMR->numDescriptors)
2957 {
2958 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2959 {
2960 if ( GCPhys >= pGMR->paDesc[j].GCPhys
2961 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * GUEST_PAGE_SIZE)
2962 {
2963 /*
2964 * Turn off the write handler for this particular page and make it R/W.
2965 * Then return telling the caller to restart the guest instruction.
2966 */
2967 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2968 AssertRC(rc);
2969 return VINF_PGM_HANDLER_DO_DEFAULT;
2970 }
2971 }
2972 }
2973 }
2974
2975 return VINF_PGM_HANDLER_DO_DEFAULT;
2976}
2977
2978/** Callback handler for VMR3ReqCallWaitU */
2979static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2980{
2981 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2982 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2983 PGMR pGMR = &pSVGAState->paGMR[gmrId];
2984 int rc;
2985
2986 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2987 {
2988 rc = PDMDevHlpPGMHandlerPhysicalRegister(pDevIns, pGMR->paDesc[i].GCPhys,
2989 pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * GUEST_PAGE_SIZE - 1,
2990 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2991 AssertRC(rc);
2992 }
2993 return VINF_SUCCESS;
2994}
2995
2996/** Callback handler for VMR3ReqCallWaitU */
2997static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2998{
2999 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3000 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3001 PGMR pGMR = &pSVGAState->paGMR[gmrId];
3002
3003 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3004 {
3005 int rc = PDMDevHlpPGMHandlerPhysicalDeregister(pDevIns, pGMR->paDesc[i].GCPhys);
3006 AssertRC(rc);
3007 }
3008 return VINF_SUCCESS;
3009}
3010
3011/** Callback handler for VMR3ReqCallWaitU */
3012static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
3013{
3014 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3015
3016 for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
3017 {
3018 PGMR pGMR = &pSVGAState->paGMR[i];
3019
3020 if (pGMR->numDescriptors)
3021 {
3022 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3023 {
3024 int rc = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pGMR->paDesc[j].GCPhys);
3025 AssertRC(rc);
3026 }
3027 }
3028 }
3029 return VINF_SUCCESS;
3030}
3031
3032# endif /* IN_RING3 */
3033#endif /* DEBUG_GMR_ACCESS */
3034
3035/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3036
3037#ifdef IN_RING3
3038
3039
3040/*
3041 *
3042 * Command buffer submission.
3043 *
3044 * Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
3045 *
3046 * EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
3047 * and wakes up the FIFO thread.
3048 *
3049 * FIFO thread fetches the command buffer from the queue, processes the commands and writes
3050 * the buffer header back to the guest memory.
3051 *
3052 * If buffers are preempted, then the EMT thread removes all buffers from the context queue.
3053 *
3054 */
3055
3056
3057/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
3058 *
3059 * @param pDevIns The device instance.
3060 * @param GCPhysCB Guest physical address of the command buffer header.
3061 * @param status Command buffer status (SVGA_CB_STATUS_*).
3062 * @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
3063 * errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
3064 * @thread FIFO or EMT.
3065 */
3066static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
3067{
3068 SVGACBHeader hdr;
3069 hdr.status = status;
3070 hdr.errorOffset = errorOffset;
3071 AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
3072 && RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
3073 && RT_OFFSETOF(SVGACBHeader, id) == 8);
3074 size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
3075 ? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
3076 : RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
3077 PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
3078}
3079
3080
3081/** Raise an IRQ.
3082 *
3083 * @param pDevIns The device instance.
3084 * @param pThis The shared VGA/VMSVGA state.
3085 * @param u32IrqStatus SVGA_IRQFLAG_* bits.
3086 * @thread FIFO or EMT.
3087 */
3088static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
3089{
3090 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
3091 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
3092
3093 if (pThis->svga.u32IrqMask & u32IrqStatus)
3094 {
3095 LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
3096 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3097 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3098 }
3099
3100 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3101}
3102
3103
3104/** Allocate a command buffer structure.
3105 *
3106 * @param pCmdBufCtx The command buffer context which must allocate the buffer.
3107 * @return Pointer to the allocated command buffer structure.
3108 */
3109static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
3110{
3111 if (!pCmdBufCtx)
3112 return NULL;
3113
3114 PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
3115 if (pCmdBuf)
3116 {
3117 // RT_ZERO(pCmdBuf->nodeBuffer);
3118 pCmdBuf->pCmdBufCtx = pCmdBufCtx;
3119 // pCmdBuf->GCPhysCB = 0;
3120 // RT_ZERO(pCmdBuf->hdr);
3121 // pCmdBuf->pvCommands = NULL;
3122 }
3123
3124 return pCmdBuf;
3125}
3126
3127
3128/** Free a command buffer structure.
3129 *
3130 * @param pCmdBuf The command buffer pointer.
3131 */
3132static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
3133{
3134 if (pCmdBuf)
3135 RTMemFree(pCmdBuf->pvCommands);
3136 RTMemFree(pCmdBuf);
3137}
3138
3139
3140/** Initialize a command buffer context.
3141 *
3142 * @param pCmdBufCtx The command buffer context.
3143 */
3144static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
3145{
3146 RTListInit(&pCmdBufCtx->listSubmitted);
3147 pCmdBufCtx->cSubmitted = 0;
3148}
3149
3150
3151/** Destroy a command buffer context.
3152 *
3153 * @param pCmdBufCtx The command buffer context pointer.
3154 */
3155static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3156{
3157 if (!pCmdBufCtx)
3158 return;
3159
3160 if (pCmdBufCtx->listSubmitted.pNext)
3161 {
3162 /* If the list has been initialized. */
3163 PVMSVGACMDBUF pIter, pNext;
3164 RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3165 {
3166 RTListNodeRemove(&pIter->nodeBuffer);
3167 --pCmdBufCtx->cSubmitted;
3168 vmsvgaR3CmdBufFree(pIter);
3169 }
3170 }
3171 Assert(pCmdBufCtx->cSubmitted == 0);
3172 pCmdBufCtx->cSubmitted = 0;
3173}
3174
3175
3176/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3177 *
3178 * @param pSvgaR3State VMSVGA R3 state.
3179 * @param pCmd The command data.
3180 * @return SVGACBStatus code.
3181 * @thread EMT
3182 */
3183static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3184{
3185 /* Create or destroy a regular command buffer context. */
3186 if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3187 return SVGA_CB_STATUS_COMMAND_ERROR;
3188 RT_UNTRUSTED_VALIDATED_FENCE();
3189
3190 SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3191
3192 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3193 AssertRC(rc);
3194 if (pCmd->enable)
3195 {
3196 pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3197 if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3198 vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3199 else
3200 CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3201 }
3202 else
3203 {
3204 vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3205 RTMemFree(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3206 pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3207 }
3208 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3209
3210 return CBStatus;
3211}
3212
3213
3214/** Handles SVGA_DC_CMD_PREEMPT command.
3215 *
3216 * @param pDevIns The device instance.
3217 * @param pSvgaR3State VMSVGA R3 state.
3218 * @param pCmd The command data.
3219 * @return SVGACBStatus code.
3220 * @thread EMT
3221 */
3222static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3223{
3224 /* Remove buffers from the processing queue of the specified context. */
3225 if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3226 return SVGA_CB_STATUS_COMMAND_ERROR;
3227 RT_UNTRUSTED_VALIDATED_FENCE();
3228
3229 PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3230 RTLISTANCHOR listPreempted;
3231
3232 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3233 AssertRC(rc);
3234 if (pCmd->ignoreIDZero)
3235 {
3236 RTListInit(&listPreempted);
3237
3238 PVMSVGACMDBUF pIter, pNext;
3239 RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3240 {
3241 if (pIter->hdr.id == 0)
3242 continue;
3243
3244 RTListNodeRemove(&pIter->nodeBuffer);
3245 --pCmdBufCtx->cSubmitted;
3246 RTListAppend(&listPreempted, &pIter->nodeBuffer);
3247 }
3248 }
3249 else
3250 {
3251 RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3252 pCmdBufCtx->cSubmitted = 0;
3253 }
3254 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3255
3256 PVMSVGACMDBUF pIter, pNext;
3257 RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3258 {
3259 RTListNodeRemove(&pIter->nodeBuffer);
3260 vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3261 LogFunc(("Preempted %RX64\n", pIter->GCPhysCB));
3262 vmsvgaR3CmdBufFree(pIter);
3263 }
3264
3265 return SVGA_CB_STATUS_COMPLETED;
3266}
3267
3268
3269/** @def VMSVGA_INC_CMD_SIZE_BREAK
3270 * Increments the size of the command cbCmd by a_cbMore.
3271 * Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3272 * Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3273 */
3274#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3275 if (1) { \
3276 cbCmd += (a_cbMore); \
3277 ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3278 RT_UNTRUSTED_VALIDATED_FENCE(); \
3279 } else do {} while (0)
3280
3281
3282/** Processes Device Context command buffer.
3283 *
3284 * @param pDevIns The device instance.
3285 * @param pSvgaR3State VMSVGA R3 state.
3286 * @param pvCommands Pointer to the command buffer.
3287 * @param cbCommands Size of the command buffer.
3288 * @param poffNextCmd Where to store the offset of the first unprocessed command.
3289 * @return SVGACBStatus code.
3290 * @thread EMT
3291 */
3292static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const *pvCommands, uint32_t cbCommands, uint32_t *poffNextCmd)
3293{
3294 SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3295
3296 uint8_t const *pu8Cmd = (uint8_t *)pvCommands;
3297 uint32_t cbRemain = cbCommands;
3298 while (cbRemain)
3299 {
3300 /* Command identifier is a 32 bit value. */
3301 if (cbRemain < sizeof(uint32_t))
3302 {
3303 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3304 break;
3305 }
3306
3307 /* Fetch the command id. */
3308 uint32_t const cmdId = *(uint32_t *)pu8Cmd;
3309 uint32_t cbCmd = sizeof(uint32_t);
3310 switch (cmdId)
3311 {
3312 case SVGA_DC_CMD_NOP:
3313 {
3314 /* NOP */
3315 break;
3316 }
3317
3318 case SVGA_DC_CMD_START_STOP_CONTEXT:
3319 {
3320 SVGADCCmdStartStop *pCmd = (SVGADCCmdStartStop *)&pu8Cmd[cbCmd];
3321 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3322 CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3323 break;
3324 }
3325
3326 case SVGA_DC_CMD_PREEMPT:
3327 {
3328 SVGADCCmdPreempt *pCmd = (SVGADCCmdPreempt *)&pu8Cmd[cbCmd];
3329 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3330 CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3331 break;
3332 }
3333
3334 default:
3335 {
3336 /* Unsupported command. */
3337 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3338 break;
3339 }
3340 }
3341
3342 if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3343 break;
3344
3345 pu8Cmd += cbCmd;
3346 cbRemain -= cbCmd;
3347 }
3348
3349 Assert(cbRemain <= cbCommands);
3350 *poffNextCmd = cbCommands - cbRemain;
3351 return CBstatus;
3352}
3353
3354
3355/** Submits a device context command buffer for synchronous processing.
3356 *
3357 * @param pDevIns The device instance.
3358 * @param pThisCC The VGA/VMSVGA state for the current context.
3359 * @param ppCmdBuf Pointer to the command buffer pointer.
3360 * The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3361 * @param poffNextCmd Where to store the offset of the first unprocessed command.
3362 * @return SVGACBStatus code.
3363 * @thread EMT
3364 */
3365static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf, uint32_t *poffNextCmd)
3366{
3367 /* Synchronously process the device context commands. */
3368 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3369 return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (*ppCmdBuf)->pvCommands, (*ppCmdBuf)->hdr.length, poffNextCmd);
3370}
3371
3372/** Submits a command buffer for asynchronous processing by the FIFO thread.
3373 *
3374 * @param pDevIns The device instance.
3375 * @param pThis The shared VGA/VMSVGA state.
3376 * @param pThisCC The VGA/VMSVGA state for the current context.
3377 * @param ppCmdBuf Pointer to the command buffer pointer.
3378 * The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3379 * @return SVGACBStatus code.
3380 * @thread EMT
3381 */
3382static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3383{
3384 /* Command buffer submission. */
3385 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3386
3387 SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3388
3389 PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3390 PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3391
3392 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3393 AssertRC(rc);
3394
3395 if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3396 {
3397 RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3398 ++pCmdBufCtx->cSubmitted;
3399 *ppCmdBuf = NULL; /* Consume the buffer. */
3400 ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3401 }
3402 else
3403 CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3404
3405 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3406
3407 /* Inform the FIFO thread. */
3408 if (*ppCmdBuf == NULL)
3409 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3410
3411 return CBstatus;
3412}
3413
3414
3415/** SVGA_REG_COMMAND_LOW write handler.
3416 * Submits a command buffer to the FIFO thread or processes a device context command.
3417 *
3418 * @param pDevIns The device instance.
3419 * @param pThis The shared VGA/VMSVGA state.
3420 * @param pThisCC The VGA/VMSVGA state for the current context.
3421 * @param GCPhysCB Guest physical address of the command buffer header.
3422 * @param CBCtx Context the command buffer is submitted to.
3423 * @thread EMT
3424 */
3425static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3426{
3427 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3428
3429 SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3430 uint32_t offNextCmd = 0;
3431 uint32_t fIRQ = 0;
3432
3433 /* Get the context if the device has the capability. */
3434 PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3435 if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3436 {
3437 if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3438 pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3439 else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3440 pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3441 RT_UNTRUSTED_VALIDATED_FENCE();
3442 }
3443
3444 /* Allocate a new command buffer. */
3445 PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3446 if (RT_LIKELY(pCmdBuf))
3447 {
3448 pCmdBuf->GCPhysCB = GCPhysCB;
3449
3450 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3451 if (RT_SUCCESS(rc))
3452 {
3453 LogFunc(("status %RX32 errorOffset %RX32 id %RX64 flags %RX32 length %RX32 ptr %RX64 offset %RX32 dxContext %RX32 (%RX32 %RX32 %RX32 %RX32 %RX32 %RX32)\n",
3454 pCmdBuf->hdr.status,
3455 pCmdBuf->hdr.errorOffset,
3456 pCmdBuf->hdr.id,
3457 pCmdBuf->hdr.flags,
3458 pCmdBuf->hdr.length,
3459 pCmdBuf->hdr.ptr.pa,
3460 pCmdBuf->hdr.offset,
3461 pCmdBuf->hdr.dxContext,
3462 pCmdBuf->hdr.mustBeZero[0],
3463 pCmdBuf->hdr.mustBeZero[1],
3464 pCmdBuf->hdr.mustBeZero[2],
3465 pCmdBuf->hdr.mustBeZero[3],
3466 pCmdBuf->hdr.mustBeZero[4],
3467 pCmdBuf->hdr.mustBeZero[5]));
3468
3469 /* Verify the command buffer header. */
3470 if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3471 && (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ | SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
3472 && pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3473 {
3474 RT_UNTRUSTED_VALIDATED_FENCE();
3475
3476 /* Read the command buffer content. */
3477 pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3478 if (pCmdBuf->pvCommands)
3479 {
3480 RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3481 rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3482 if (RT_SUCCESS(rc))
3483 {
3484 /* Submit the buffer. Device context buffers will be processed synchronously. */
3485 if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3486 /* This usually processes the CB async and sets pCmbBuf to NULL. */
3487 CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
3488 else
3489 CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3490 }
3491 else
3492 {
3493 ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3494 CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3495 fIRQ = SVGA_IRQFLAG_ERROR | SVGA_IRQFLAG_COMMAND_BUFFER;
3496 }
3497 }
3498 else
3499 {
3500 /* No memory for commands. */
3501 CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3502 }
3503 }
3504 else
3505 {
3506 ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3507 CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3508 fIRQ = SVGA_IRQFLAG_ERROR | SVGA_IRQFLAG_COMMAND_BUFFER;
3509 }
3510 }
3511 else
3512 {
3513 LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3514 ASSERT_GUEST_FAILED();
3515 /* Do not attempt to write the status. */
3516 }
3517
3518 /* Free the buffer if pfnCmdBufSubmit did not consume it. */
3519 vmsvgaR3CmdBufFree(pCmdBuf);
3520 }
3521 else
3522 {
3523 LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3524 AssertFailed();
3525 CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3526 }
3527
3528 if (CBstatus != SVGA_CB_STATUS_NONE)
3529 {
3530 LogFunc(("Write status %#x, offNextCmd %#x, fIRQ %#x\n", CBstatus, offNextCmd, fIRQ));
3531 vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3532 if (fIRQ)
3533 vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3534 }
3535}
3536
3537
3538/** Checks if there are some buffers to be processed.
3539 *
3540 * @param pThisCC The VGA/VMSVGA state for the current context.
3541 * @return true if buffers must be processed.
3542 * @thread FIFO
3543 */
3544static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3545{
3546 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3547 return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3548}
3549
3550
3551/** Processes a command buffer.
3552 *
3553 * @param pDevIns The device instance.
3554 * @param pThis The shared VGA/VMSVGA state.
3555 * @param pThisCC The VGA/VMSVGA state for the current context.
3556 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
3557 * @param pvCommands Pointer to the command buffer.
3558 * @param cbCommands Size of the command buffer.
3559 * @param poffNextCmd Where to store the offset of the first unprocessed command.
3560 * @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3561 * @return SVGACBStatus code.
3562 * @thread FIFO
3563 */
3564static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const *pvCommands, uint32_t cbCommands, uint32_t *poffNextCmd, uint32_t *pu32IrqStatus)
3565{
3566# ifndef VBOX_WITH_VMSVGA3D
3567 RT_NOREF(idDXContext);
3568# endif
3569 SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3570 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3571
3572# ifdef VBOX_WITH_VMSVGA3D
3573# ifdef VMSVGA3D_DX
3574 /* Commands submitted for the SVGA3D_INVALID_ID context do not affect pipeline. So ignore them. */
3575 if (idDXContext != SVGA3D_INVALID_ID)
3576 {
3577 if (pSvgaR3State->idDXContextCurrent != idDXContext)
3578 {
3579 LogFlow(("DXCTX: buffer %d->%d\n", pSvgaR3State->idDXContextCurrent, idDXContext));
3580 vmsvga3dDXSwitchContext(pThisCC, idDXContext);
3581 pSvgaR3State->idDXContextCurrent = idDXContext;
3582 }
3583 }
3584# endif
3585# endif
3586
3587 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3588
3589 uint8_t const *pu8Cmd = (uint8_t *)pvCommands;
3590 uint32_t cbRemain = cbCommands;
3591 while (cbRemain)
3592 {
3593 /* Command identifier is a 32 bit value. */
3594 if (cbRemain < sizeof(uint32_t))
3595 {
3596 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3597 break;
3598 }
3599
3600 /* Fetch the command id.
3601 * 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3602 * warning. Because we support some obsolete and deprecated commands, which are not included in
3603 * the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3604 */
3605 uint32_t const cmdId = *(uint32_t *)pu8Cmd;
3606 uint32_t cbCmd = sizeof(uint32_t);
3607
3608 LogFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
3609# ifdef LOG_ENABLED
3610# ifdef VBOX_WITH_VMSVGA3D
3611 if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
3612 {
3613 SVGA3dCmdHeader const *header = (SVGA3dCmdHeader *)pu8Cmd;
3614 svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
3615 }
3616 else if (cmdId == SVGA_CMD_FENCE)
3617 {
3618 Log7(("\tSVGA_CMD_FENCE\n"));
3619 Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
3620 }
3621# endif
3622# endif
3623
3624 /* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3625 * I.e. pu8Cmd + cbCmd must point to the next command.
3626 * However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3627 * the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3628 */
3629 /** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3630 switch (cmdId)
3631 {
3632 case SVGA_CMD_INVALID_CMD:
3633 {
3634 /* Nothing to do. */
3635 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3636 break;
3637 }
3638
3639 case SVGA_CMD_FENCE:
3640 {
3641 SVGAFifoCmdFence *pCmd = (SVGAFifoCmdFence *)&pu8Cmd[cbCmd];
3642 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3643 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3644 Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3645
3646 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3647 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3648 {
3649 pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3650
3651 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3652 {
3653 Log(("any fence irq\n"));
3654 *pu32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
3655 }
3656 else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3657 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3658 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3659 {
3660 Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3661 *pu32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
3662 }
3663 }
3664 else
3665 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3666 break;
3667 }
3668
3669 case SVGA_CMD_UPDATE:
3670 {
3671 SVGAFifoCmdUpdate *pCmd = (SVGAFifoCmdUpdate *)&pu8Cmd[cbCmd];
3672 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3673 vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3674 break;
3675 }
3676
3677 case SVGA_CMD_UPDATE_VERBOSE:
3678 {
3679 SVGAFifoCmdUpdateVerbose *pCmd = (SVGAFifoCmdUpdateVerbose *)&pu8Cmd[cbCmd];
3680 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3681 vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3682 break;
3683 }
3684
3685 case SVGA_CMD_DEFINE_CURSOR:
3686 {
3687 /* Followed by bitmap data. */
3688 SVGAFifoCmdDefineCursor *pCmd = (SVGAFifoCmdDefineCursor *)&pu8Cmd[cbCmd];
3689 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3690
3691 /* Figure out the size of the bitmap data. */
3692 ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3693 ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3694 ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3695 RT_UNTRUSTED_VALIDATED_FENCE();
3696
3697 uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3698 uint32_t const cbAndMask = cbAndLine * pCmd->height;
3699 uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3700 uint32_t const cbXorMask = cbXorLine * pCmd->height;
3701
3702 VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3703 vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3704 break;
3705 }
3706
3707 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3708 {
3709 /* Followed by bitmap data. */
3710 SVGAFifoCmdDefineAlphaCursor *pCmd = (SVGAFifoCmdDefineAlphaCursor *)&pu8Cmd[cbCmd];
3711 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3712
3713 /* Figure out the size of the bitmap data. */
3714 ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3715
3716 VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3717 vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3718 break;
3719 }
3720
3721 case SVGA_CMD_MOVE_CURSOR:
3722 {
3723 /* Deprecated; there should be no driver which *requires* this command. However, if
3724 * we do ecncounter this command, it might be useful to not get the FIFO completely out of
3725 * alignment.
3726 * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3727 */
3728 SVGAFifoCmdMoveCursor *pCmd = (SVGAFifoCmdMoveCursor *)&pu8Cmd[cbCmd];
3729 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3730 vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3731 break;
3732 }
3733
3734 case SVGA_CMD_DISPLAY_CURSOR:
3735 {
3736 /* Deprecated; there should be no driver which *requires* this command. However, if
3737 * we do ecncounter this command, it might be useful to not get the FIFO completely out of
3738 * alignment.
3739 * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3740 */
3741 SVGAFifoCmdDisplayCursor *pCmd = (SVGAFifoCmdDisplayCursor *)&pu8Cmd[cbCmd];
3742 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3743 vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3744 break;
3745 }
3746
3747 case SVGA_CMD_RECT_FILL:
3748 {
3749 SVGAFifoCmdRectFill *pCmd = (SVGAFifoCmdRectFill *)&pu8Cmd[cbCmd];
3750 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3751 vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3752 break;
3753 }
3754
3755 case SVGA_CMD_RECT_COPY:
3756 {
3757 SVGAFifoCmdRectCopy *pCmd = (SVGAFifoCmdRectCopy *)&pu8Cmd[cbCmd];
3758 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3759 vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3760 break;
3761 }
3762
3763 case SVGA_CMD_RECT_ROP_COPY:
3764 {
3765 SVGAFifoCmdRectRopCopy *pCmd = (SVGAFifoCmdRectRopCopy *)&pu8Cmd[cbCmd];
3766 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3767 vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3768 break;
3769 }
3770
3771 case SVGA_CMD_ESCAPE:
3772 {
3773 /* Followed by 'size' bytes of data. */
3774 SVGAFifoCmdEscape *pCmd = (SVGAFifoCmdEscape *)&pu8Cmd[cbCmd];
3775 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3776
3777 ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3778 RT_UNTRUSTED_VALIDATED_FENCE();
3779
3780 VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3781 vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3782 break;
3783 }
3784# ifdef VBOX_WITH_VMSVGA3D
3785 case SVGA_CMD_DEFINE_GMR2:
3786 {
3787 SVGAFifoCmdDefineGMR2 *pCmd = (SVGAFifoCmdDefineGMR2 *)&pu8Cmd[cbCmd];
3788 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3789 vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3790 break;
3791 }
3792
3793 case SVGA_CMD_REMAP_GMR2:
3794 {
3795 /* Followed by page descriptors or guest ptr. */
3796 SVGAFifoCmdRemapGMR2 *pCmd = (SVGAFifoCmdRemapGMR2 *)&pu8Cmd[cbCmd];
3797 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3798
3799 /* Calculate the size of what comes after next and fetch it. */
3800 uint32_t cbMore = 0;
3801 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3802 cbMore = sizeof(SVGAGuestPtr);
3803 else
3804 {
3805 uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3806 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3807 {
3808 cbMore = cbPageDesc;
3809 pCmd->numPages = 1;
3810 }
3811 else
3812 {
3813 ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3814 cbMore = cbPageDesc * pCmd->numPages;
3815 }
3816 }
3817 VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3818 vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3819# ifdef DEBUG_GMR_ACCESS
3820 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3821# endif
3822 break;
3823 }
3824# endif /* VBOX_WITH_VMSVGA3D */
3825 case SVGA_CMD_DEFINE_SCREEN:
3826 {
3827 /* The size of this command is specified by the guest and depends on capabilities. */
3828 SVGAFifoCmdDefineScreen *pCmd = (SVGAFifoCmdDefineScreen *)&pu8Cmd[cbCmd];
3829 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3830 ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3831 RT_UNTRUSTED_VALIDATED_FENCE();
3832
3833 VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3834 vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3835 break;
3836 }
3837
3838 case SVGA_CMD_DESTROY_SCREEN:
3839 {
3840 SVGAFifoCmdDestroyScreen *pCmd = (SVGAFifoCmdDestroyScreen *)&pu8Cmd[cbCmd];
3841 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3842 vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3843 break;
3844 }
3845
3846 case SVGA_CMD_DEFINE_GMRFB:
3847 {
3848 SVGAFifoCmdDefineGMRFB *pCmd = (SVGAFifoCmdDefineGMRFB *)&pu8Cmd[cbCmd];
3849 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3850 vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3851 break;
3852 }
3853
3854 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3855 {
3856 SVGAFifoCmdBlitGMRFBToScreen *pCmd = (SVGAFifoCmdBlitGMRFBToScreen *)&pu8Cmd[cbCmd];
3857 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3858 vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3859 break;
3860 }
3861
3862 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3863 {
3864 SVGAFifoCmdBlitScreenToGMRFB *pCmd = (SVGAFifoCmdBlitScreenToGMRFB *)&pu8Cmd[cbCmd];
3865 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3866 vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3867 break;
3868 }
3869
3870 case SVGA_CMD_ANNOTATION_FILL:
3871 {
3872 SVGAFifoCmdAnnotationFill *pCmd = (SVGAFifoCmdAnnotationFill *)&pu8Cmd[cbCmd];
3873 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3874 vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3875 break;
3876 }
3877
3878 case SVGA_CMD_ANNOTATION_COPY:
3879 {
3880 SVGAFifoCmdAnnotationCopy *pCmd = (SVGAFifoCmdAnnotationCopy *)&pu8Cmd[cbCmd];
3881 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3882 vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3883 break;
3884 }
3885
3886 default:
3887 {
3888# ifdef VBOX_WITH_VMSVGA3D
3889 if ( cmdId >= SVGA_3D_CMD_BASE
3890 && cmdId < SVGA_3D_CMD_MAX)
3891 {
3892 RT_UNTRUSTED_VALIDATED_FENCE();
3893
3894 /* All 3d commands start with a common header, which defines the identifier and the size
3895 * of the command. The identifier has been already read. Fetch the size.
3896 */
3897 uint32_t const *pcbMore = (uint32_t const *)&pu8Cmd[cbCmd];
3898 VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3899 VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3900 if (RT_LIKELY(pThis->svga.f3DEnabled))
3901 { /* likely */ }
3902 else
3903 {
3904 LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3905 break;
3906 }
3907
3908 /* Command data begins after the 32 bit command length. */
3909 int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3910 if (RT_SUCCESS(rc))
3911 { /* likely */ }
3912 else
3913 {
3914 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3915 break;
3916 }
3917 }
3918 else
3919# endif /* VBOX_WITH_VMSVGA3D */
3920 {
3921 /* Unsupported command. */
3922 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3923 ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3924 LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3925 CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3926 break;
3927 }
3928 }
3929 }
3930
3931 if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3932 break;
3933
3934 pu8Cmd += cbCmd;
3935 cbRemain -= cbCmd;
3936
3937 /* If this is not the last command in the buffer, then generate IRQ, if required.
3938 * This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3939 * in the buffer (usually the case).
3940 */
3941 if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3942 { /* likely */ }
3943 else
3944 {
3945 vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3946 *pu32IrqStatus = 0;
3947 }
3948 }
3949
3950 Assert(cbRemain <= cbCommands);
3951 *poffNextCmd = cbCommands - cbRemain;
3952 return CBstatus;
3953}
3954
3955
3956/** Process command buffers.
3957 *
3958 * @param pDevIns The device instance.
3959 * @param pThis The shared VGA/VMSVGA state.
3960 * @param pThisCC The VGA/VMSVGA state for the current context.
3961 * @param pThread Handle of the FIFO thread.
3962 * @thread FIFO
3963 */
3964static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3965{
3966 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3967
3968 for (;;)
3969 {
3970 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3971 break;
3972
3973 /* See if there is a submitted buffer. */
3974 PVMSVGACMDBUF pCmdBuf = NULL;
3975
3976 int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3977 AssertRC(rc);
3978
3979 /* It seems that a higher queue index has a higher priority.
3980 * See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3981 */
3982 for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3983 {
3984 PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3985 if (pCmdBufCtx)
3986 {
3987 pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3988 if (pCmdBuf)
3989 {
3990 Assert(pCmdBufCtx->cSubmitted > 0);
3991 --pCmdBufCtx->cSubmitted;
3992 break;
3993 }
3994 }
3995 }
3996
3997 if (!pCmdBuf)
3998 {
3999 ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
4000 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4001 break;
4002 }
4003
4004 RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
4005
4006 SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
4007 uint32_t offNextCmd = 0;
4008 uint32_t u32IrqStatus = 0;
4009 uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
4010 ? pCmdBuf->hdr.dxContext
4011 : SVGA3D_INVALID_ID;
4012 /* Process one buffer. */
4013 CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
4014
4015 if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
4016 u32IrqStatus |= SVGA_IRQFLAG_COMMAND_BUFFER;
4017 if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
4018 u32IrqStatus |= SVGA_IRQFLAG_ERROR;
4019
4020 vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
4021 if (u32IrqStatus)
4022 vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
4023
4024 vmsvgaR3CmdBufFree(pCmdBuf);
4025 }
4026}
4027
4028
4029/**
4030 * Worker for vmsvgaR3FifoThread that handles an external command.
4031 *
4032 * @param pDevIns The device instance.
4033 * @param pThis The shared VGA/VMSVGA instance data.
4034 * @param pThisCC The VGA/VMSVGA state for ring-3.
4035 */
4036static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4037{
4038 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
4039 switch (pThis->svga.u8FIFOExtCommand)
4040 {
4041 case VMSVGA_FIFO_EXTCMD_RESET:
4042 Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
4043 Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4044
4045 vmsvgaR3ResetScreens(pThis, pThisCC);
4046# ifdef VBOX_WITH_VMSVGA3D
4047 /* The 3d subsystem must be reset from the fifo thread. */
4048 if (pThis->svga.f3DEnabled)
4049 vmsvga3dReset(pThisCC);
4050# endif
4051 vmsvgaR3ResetSvgaState(pThis, pThisCC);
4052 break;
4053
4054 case VMSVGA_FIFO_EXTCMD_POWEROFF:
4055 Log(("vmsvgaR3FifoLoop: power off.\n"));
4056 Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4057
4058 /* The screens must be reset on the FIFO thread, because they may use 3D resources. */
4059 vmsvgaR3ResetScreens(pThis, pThisCC);
4060 break;
4061
4062 case VMSVGA_FIFO_EXTCMD_TERMINATE:
4063 Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
4064 Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
4065
4066# ifdef VBOX_WITH_VMSVGA3D
4067 /* The 3d subsystem must be shut down from the fifo thread. */
4068 if (pThis->svga.f3DEnabled)
4069 vmsvga3dTerminate(pThisCC);
4070# endif
4071 vmsvgaR3TerminateSvgaState(pThis, pThisCC);
4072 break;
4073
4074 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
4075 {
4076 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
4077 PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
4078 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
4079 vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
4080# ifdef VBOX_WITH_VMSVGA3D
4081 if (pThis->svga.f3DEnabled)
4082 {
4083 if (vmsvga3dIsLegacyBackend(pThisCC))
4084 vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
4085# ifdef VMSVGA3D_DX
4086 else
4087 vmsvga3dDXSaveExec(pDevIns, pThisCC, pSSM);
4088# endif
4089 }
4090# endif
4091 break;
4092 }
4093
4094 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
4095 {
4096 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
4097 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
4098 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
4099 vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4100# ifdef VBOX_WITH_VMSVGA3D
4101 if (pThis->svga.f3DEnabled)
4102 {
4103 /* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
4104# ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
4105 /* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
4106 vmsvgaR3PowerOnDevice(pDevIns, pThis, pThisCC, /*fLoadState=*/ true);
4107# endif
4108
4109 if (vmsvga3dIsLegacyBackend(pThisCC))
4110 vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4111# ifdef VMSVGA3D_DX
4112 else
4113 vmsvga3dDXLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
4114# endif
4115 }
4116# endif
4117 break;
4118 }
4119
4120 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
4121 {
4122# ifdef VBOX_WITH_VMSVGA3D
4123 uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
4124 Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
4125 vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
4126# endif
4127 break;
4128 }
4129
4130
4131 default:
4132 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
4133 break;
4134 }
4135
4136 /*
4137 * Signal the end of the external command.
4138 */
4139 pThisCC->svga.pvFIFOExtCmdParam = NULL;
4140 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
4141 ASMMemoryFence(); /* paranoia^2 */
4142 int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
4143 AssertLogRelRC(rc);
4144}
4145
4146/**
4147 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
4148 * doing a job on the FIFO thread (even when it's officially suspended).
4149 *
4150 * @returns VBox status code (fully asserted).
4151 * @param pDevIns The device instance.
4152 * @param pThis The shared VGA/VMSVGA instance data.
4153 * @param pThisCC The VGA/VMSVGA state for ring-3.
4154 * @param uExtCmd The command to execute on the FIFO thread.
4155 * @param pvParam Pointer to command parameters.
4156 * @param cMsWait The time to wait for the command, given in
4157 * milliseconds.
4158 */
4159static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
4160 uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
4161{
4162 Assert(cMsWait >= RT_MS_1SEC * 5);
4163 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
4164 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
4165
4166 int rc;
4167 PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
4168 PDMTHREADSTATE enmState = pThread->enmState;
4169 if (enmState == PDMTHREADSTATE_SUSPENDED)
4170 {
4171 /*
4172 * The thread is suspended, we have to temporarily wake it up so it can
4173 * perform the task.
4174 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
4175 */
4176 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
4177 /* Post the request. */
4178 pThis->svga.fFifoExtCommandWakeup = true;
4179 pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4180 pThis->svga.u8FIFOExtCommand = uExtCmd;
4181 ASMMemoryFence(); /* paranoia^3 */
4182
4183 /* Resume the thread. */
4184 rc = PDMDevHlpThreadResume(pDevIns, pThread);
4185 AssertLogRelRC(rc);
4186 if (RT_SUCCESS(rc))
4187 {
4188 /* Wait. Take care in case the semaphore was already posted (same as below). */
4189 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4190 if ( rc == VINF_SUCCESS
4191 && pThis->svga.u8FIFOExtCommand == uExtCmd)
4192 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4193 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
4194 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4195
4196 /* suspend the thread */
4197 pThis->svga.fFifoExtCommandWakeup = false;
4198 int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
4199 AssertLogRelRC(rc2);
4200 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
4201 rc = rc2;
4202 }
4203 pThis->svga.fFifoExtCommandWakeup = false;
4204 pThisCC->svga.pvFIFOExtCmdParam = NULL;
4205 }
4206 else if (enmState == PDMTHREADSTATE_RUNNING)
4207 {
4208 /*
4209 * The thread is running, should only happen during reset and vmsvga3dsfc.
4210 * We ASSUME not racing code here, both wrt thread state and ext commands.
4211 */
4212 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
4213 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS || uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
4214
4215 /* Post the request. */
4216 pThisCC->svga.pvFIFOExtCmdParam = pvParam;
4217 pThis->svga.u8FIFOExtCommand = uExtCmd;
4218 ASMMemoryFence(); /* paranoia^2 */
4219 rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4220 AssertLogRelRC(rc);
4221
4222 /* Wait. Take care in case the semaphore was already posted (same as above). */
4223 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4224 if ( rc == VINF_SUCCESS
4225 && pThis->svga.u8FIFOExtCommand == uExtCmd)
4226 rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4227 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
4228 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4229
4230 pThisCC->svga.pvFIFOExtCmdParam = NULL;
4231 }
4232 else
4233 {
4234 /*
4235 * Something is wrong with the thread!
4236 */
4237 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4238 rc = VERR_INVALID_STATE;
4239 }
4240 return rc;
4241}
4242
4243
4244/**
4245 * Marks the FIFO non-busy, notifying any waiting EMTs.
4246 *
4247 * @param pDevIns The device instance.
4248 * @param pThis The shared VGA/VMSVGA instance data.
4249 * @param pThisCC The VGA/VMSVGA state for ring-3.
4250 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
4251 * @param offFifoMin The start byte offset of the command FIFO.
4252 */
4253static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4254{
4255 ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO | VMSVGA_BUSY_F_EMT_FORCE));
4256 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4257 vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4258
4259 /* Wake up any waiting EMTs. */
4260 if (pSVGAState->cBusyDelayedEmts > 0)
4261 {
4262# ifdef VMSVGA_USE_EMT_HALT_CODE
4263 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4264 if (idCpu != NIL_VMCPUID)
4265 {
4266 PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4267 while (idCpu-- > 0)
4268 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4269 PDMDevHlpVMNotifyCpuDeviceReady(pDevIns, idCpu);
4270 }
4271# else
4272 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4273 AssertRC(rc2);
4274# endif
4275 }
4276}
4277
4278/**
4279 * Reads (more) payload into the command buffer.
4280 *
4281 * @returns pbBounceBuf on success
4282 * @retval (void *)1 if the thread was requested to stop.
4283 * @retval NULL on FIFO error.
4284 *
4285 * @param cbPayloadReq The number of bytes of payload requested.
4286 * @param pFIFO The FIFO.
4287 * @param offCurrentCmd The FIFO byte offset of the current command.
4288 * @param offFifoMin The start byte offset of the command FIFO.
4289 * @param offFifoMax The end byte offset of the command FIFO.
4290 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4291 * always sufficient size.
4292 * @param pcbAlreadyRead How much payload we've already read into the bounce
4293 * buffer. (We will NEVER re-read anything.)
4294 * @param pThread The calling PDM thread handle.
4295 * @param pThis The shared VGA/VMSVGA instance data.
4296 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4297 * statistics collection.
4298 * @param pDevIns The device instance.
4299 */
4300static void *vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4301 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4302 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
4303 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4304{
4305 Assert(pbBounceBuf);
4306 Assert(pcbAlreadyRead);
4307 Assert(offFifoMin < offFifoMax);
4308 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4309 Assert(offFifoMax <= pThis->svga.cbFIFO);
4310
4311 /*
4312 * Check if the requested payload size has already been satisfied .
4313 * .
4314 * When called to read more, the caller is responsible for making sure the .
4315 * new command size (cbRequsted) never is smaller than what has already .
4316 * been read.
4317 */
4318 uint32_t cbAlreadyRead = *pcbAlreadyRead;
4319 if (cbPayloadReq <= cbAlreadyRead)
4320 {
4321 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4322 return pbBounceBuf;
4323 }
4324
4325 /*
4326 * Commands bigger than the fifo buffer are invalid.
4327 */
4328 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4329 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4330 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4331 NULL);
4332
4333 /*
4334 * Move offCurrentCmd past the command dword.
4335 */
4336 offCurrentCmd += sizeof(uint32_t);
4337 if (offCurrentCmd >= offFifoMax)
4338 offCurrentCmd = offFifoMin;
4339
4340 /*
4341 * Do we have sufficient payload data available already?
4342 * The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4343 */
4344 uint32_t cbAfter, cbBefore;
4345 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4346 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4347 if (offNextCmd >= offCurrentCmd)
4348 {
4349 if (RT_LIKELY(offNextCmd < offFifoMax))
4350 cbAfter = offNextCmd - offCurrentCmd;
4351 else
4352 {
4353 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4354 LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4355 offNextCmd, offFifoMin, offFifoMax));
4356 cbAfter = offFifoMax - offCurrentCmd;
4357 }
4358 cbBefore = 0;
4359 }
4360 else
4361 {
4362 cbAfter = offFifoMax - offCurrentCmd;
4363 if (offNextCmd >= offFifoMin)
4364 cbBefore = offNextCmd - offFifoMin;
4365 else
4366 {
4367 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4368 LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4369 offNextCmd, offFifoMin, offFifoMax));
4370 cbBefore = 0;
4371 }
4372 }
4373 if (cbAfter + cbBefore < cbPayloadReq)
4374 {
4375 /*
4376 * Insufficient, must wait for it to arrive.
4377 */
4378/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4379 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4380 for (uint32_t i = 0;; i++)
4381 {
4382 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4383 {
4384 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4385 return (void *)(uintptr_t)1;
4386 }
4387 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4388 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4389
4390 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4391
4392 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4393 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4394 if (offNextCmd >= offCurrentCmd)
4395 {
4396 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4397 cbBefore = 0;
4398 }
4399 else
4400 {
4401 cbAfter = offFifoMax - offCurrentCmd;
4402 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4403 }
4404
4405 if (cbAfter + cbBefore >= cbPayloadReq)
4406 break;
4407 }
4408 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4409 }
4410
4411 /*
4412 * Copy out the memory and update what pcbAlreadyRead points to.
4413 */
4414 if (cbAfter >= cbPayloadReq)
4415 memcpy(pbBounceBuf + cbAlreadyRead,
4416 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4417 cbPayloadReq - cbAlreadyRead);
4418 else
4419 {
4420 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4421 if (cbAlreadyRead < cbAfter)
4422 {
4423 memcpy(pbBounceBuf + cbAlreadyRead,
4424 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4425 cbAfter - cbAlreadyRead);
4426 cbAlreadyRead = cbAfter;
4427 }
4428 memcpy(pbBounceBuf + cbAlreadyRead,
4429 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4430 cbPayloadReq - cbAlreadyRead);
4431 }
4432 *pcbAlreadyRead = cbPayloadReq;
4433 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4434 return pbBounceBuf;
4435}
4436
4437
4438/**
4439 * Sends cursor position and visibility information from the FIFO to the front-end.
4440 * @returns SVGA_FIFO_CURSOR_COUNT value used.
4441 */
4442static uint32_t
4443vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4444 uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4445 uint32_t *pxLast, uint32_t *pyLast, uint32_t *pfLastVisible)
4446{
4447 /*
4448 * Check if the cursor update counter has changed and try get a stable
4449 * set of values if it has. This is race-prone, especially consindering
4450 * the screen ID, but little we can do about that.
4451 */
4452 uint32_t x, y, fVisible, idScreen;
4453 for (uint32_t i = 0; ; i++)
4454 {
4455 x = pFIFO[SVGA_FIFO_CURSOR_X];
4456 y = pFIFO[SVGA_FIFO_CURSOR_Y];
4457 fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4458 idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4459 ? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4460 if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4461 || i > 3)
4462 break;
4463 if (i == 0)
4464 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4465 ASMNopPause();
4466 uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4467 }
4468
4469 /*
4470 * Check if anything has changed, as calling into pDrv is not light-weight.
4471 */
4472 if ( *pxLast == x
4473 && *pyLast == y
4474 && (idScreen != SVGA_ID_INVALID || *pfLastVisible == fVisible))
4475 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4476 else
4477 {
4478 /*
4479 * Detected changes.
4480 *
4481 * We handle global, not per-screen visibility information by sending
4482 * pfnVBVAMousePointerShape without shape data.
4483 */
4484 *pxLast = x;
4485 *pyLast = y;
4486 uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4487 if (idScreen != SVGA_ID_INVALID)
4488 fFlags |= VBVA_CURSOR_SCREEN_RELATIVE;
4489 else if (*pfLastVisible != fVisible)
4490 {
4491 LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4492 *pfLastVisible = fVisible;
4493 pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4494 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4495 }
4496 pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4497 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4498 }
4499
4500 /*
4501 * Update done. Signal this to the guest.
4502 */
4503 pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4504
4505 return uCursorUpdateCount;
4506}
4507
4508
4509/**
4510 * Checks if there is work to be done, either cursor updating or FIFO commands.
4511 *
4512 * @returns true if pending work, false if not.
4513 * @param pThisCC The VGA/VMSVGA state for ring-3.
4514 * @param uLastCursorCount The last cursor update counter value.
4515 */
4516DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4517{
4518 /* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4519 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4520 AssertReturn(pFIFO, false);
4521
4522 if (vmsvgaR3CmdBufHasWork(pThisCC))
4523 return true;
4524
4525 if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4526 return true;
4527
4528 if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4529 && VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4530 return true;
4531
4532 return false;
4533}
4534
4535
4536/**
4537 * Called by the VGA refresh timer to wake up the FIFO thread when needed.
4538 *
4539 * @param pDevIns The device instance.
4540 * @param pThis The shared VGA/VMSVGA instance data.
4541 * @param pThisCC The VGA/VMSVGA state for ring-3.
4542 */
4543void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4544{
4545 /* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4546 to recheck it before doing the signalling. */
4547 if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4548 && pThis->svga.fFIFOThreadSleeping
4549 && !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4550 {
4551 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4552 AssertRC(rc);
4553 STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4554 }
4555}
4556
4557
4558/**
4559 * Called by the FIFO thread to process pending actions.
4560 *
4561 * @param pDevIns The device instance.
4562 * @param pThis The shared VGA/VMSVGA instance data.
4563 * @param pThisCC The VGA/VMSVGA state for ring-3.
4564 */
4565static void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4566{
4567 RT_NOREF(pDevIns);
4568
4569 /* Currently just mode changes. */
4570 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4571 {
4572 vmsvgaR3ChangeMode(pThis, pThisCC);
4573# ifdef VBOX_WITH_VMSVGA3D
4574 if (pThisCC->svga.p3dState != NULL)
4575 vmsvga3dChangeMode(pThisCC);
4576# endif
4577 }
4578}
4579
4580
4581/*
4582 * These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4583 * even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4584 */
4585/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4586 * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4587 *
4588 * Will break out of the switch on failure.
4589 * Will restart and quit the loop if the thread was requested to stop.
4590 *
4591 * @param a_PtrVar Request variable pointer.
4592 * @param a_Type Request typedef (not pointer) for casting.
4593 * @param a_cbPayloadReq How much payload to fetch.
4594 * @remarks Accesses a bunch of variables in the current scope!
4595 */
4596# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4597 if (1) { \
4598 (a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4599 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4600 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4601 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4602 } else do {} while (0)
4603/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4604 * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4605 * buffer after figuring out the actual command size.
4606 *
4607 * Will break out of the switch on failure.
4608 *
4609 * @param a_PtrVar Request variable pointer.
4610 * @param a_Type Request typedef (not pointer) for casting.
4611 * @param a_cbPayloadReq How much payload to fetch.
4612 * @remarks Accesses a bunch of variables in the current scope!
4613 */
4614# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4615 if (1) { \
4616 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4617 } else do {} while (0)
4618
4619/**
4620 * @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4621 */
4622static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4623{
4624 PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4625 PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4626 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4627 int rc;
4628
4629 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4630 return VINF_SUCCESS;
4631
4632 /*
4633 * Special mode where we only execute an external command and the go back
4634 * to being suspended. Currently, all ext cmds ends up here, with the reset
4635 * one also being eligble for runtime execution further down as well.
4636 */
4637 if (pThis->svga.fFifoExtCommandWakeup)
4638 {
4639 vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4640 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4641 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4642 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4643 else
4644 vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4645 return VINF_SUCCESS;
4646 }
4647
4648
4649 /*
4650 * Signal the semaphore to make sure we don't wait for 250ms after a
4651 * suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4652 */
4653 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4654
4655 /*
4656 * Allocate a bounce buffer for command we get from the FIFO.
4657 * (All code must return via the end of the function to free this buffer.)
4658 */
4659 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(pThis->svga.cbFIFO);
4660 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4661
4662 /*
4663 * Polling/sleep interval config.
4664 *
4665 * We wait for an a short interval if the guest has recently given us work
4666 * to do, but the interval increases the longer we're kept idle. Once we've
4667 * reached the refresh timer interval, we'll switch to extended waits,
4668 * depending on it or the guest to kick us into action when needed.
4669 *
4670 * Should the refresh time go fishing, we'll just continue increasing the
4671 * sleep length till we reaches the 250 ms max after about 16 seconds.
4672 */
4673 RTMSINTERVAL const cMsMinSleep = 16;
4674 RTMSINTERVAL const cMsIncSleep = 2;
4675 RTMSINTERVAL const cMsMaxSleep = 250;
4676 RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4677 RTMSINTERVAL cMsSleep = cMsMaxSleep;
4678
4679 /*
4680 * Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4681 *
4682 * Initialize with values that will detect an update from the guest.
4683 * Make sure that if the guest never updates the cursor position, then the device does not report it.
4684 * The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4685 * xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4686 */
4687 uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4688 pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4689 uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4690 uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4691 uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4692
4693 /*
4694 * The FIFO loop.
4695 */
4696 LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4697 bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4698 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4699 {
4700# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4701 /*
4702 * Should service the run loop every so often.
4703 */
4704 if (pThis->svga.f3DEnabled)
4705 vmsvga3dCocoaServiceRunLoop();
4706# endif
4707
4708 /* First check any pending actions. */
4709 vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4710
4711 /*
4712 * Unless there's already work pending, go to sleep for a short while.
4713 * (See polling/sleep interval config above.)
4714 */
4715 if ( fBadOrDisabledFifo
4716 || !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4717 {
4718 ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4719 Assert(pThis->cMilliesRefreshInterval > 0);
4720 if (cMsSleep < pThis->cMilliesRefreshInterval)
4721 rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4722 else
4723 {
4724# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4725 int rc2 = PDMDevHlpPGMHandlerPhysicalReset(pDevIns, pThis->svga.GCPhysFIFO);
4726 AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4727# endif
4728 if ( !fBadOrDisabledFifo
4729 && vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4730 rc = VINF_SUCCESS;
4731 else
4732 {
4733 STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4734 rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4735 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4736 }
4737 }
4738 ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4739 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
4740 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4741 {
4742 LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4743 break;
4744 }
4745 }
4746 else
4747 rc = VINF_SUCCESS;
4748 fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4749 if (rc == VERR_TIMEOUT)
4750 {
4751 if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4752 {
4753 cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4754 continue;
4755 }
4756 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4757
4758 Log(("vmsvgaR3FifoLoop: timeout\n"));
4759 }
4760 else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4761 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4762 cMsSleep = cMsMinSleep;
4763
4764 Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4765 Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4766 Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4767
4768 /*
4769 * Handle external commands (currently only reset).
4770 */
4771 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4772 {
4773 vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4774 continue;
4775 }
4776
4777 /*
4778 * If guest misbehaves, then do nothing.
4779 */
4780 if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4781 {
4782 vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4783 cMsSleep = cMsExtendedSleep;
4784 LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4785 continue;
4786 }
4787
4788 /*
4789 * The device must be enabled and configured.
4790 */
4791 if ( !pThis->svga.fEnabled
4792 || !pThis->svga.fConfigured)
4793 {
4794 vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4795 fBadOrDisabledFifo = true;
4796 cMsSleep = cMsMaxSleep; /* cheat */
4797 continue;
4798 }
4799
4800 /*
4801 * Get and check the min/max values. We ASSUME that they will remain
4802 * unchanged while we process requests. A further ASSUMPTION is that
4803 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4804 * we don't read it back while in the loop.
4805 */
4806 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4807 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4808 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4809 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4810 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4811 || offFifoMax <= offFifoMin
4812 || offFifoMax > pThis->svga.cbFIFO
4813 || (offFifoMax & 3) != 0
4814 || (offFifoMin & 3) != 0
4815 || offCurrentCmd < offFifoMin
4816 || offCurrentCmd > offFifoMax))
4817 {
4818 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4819 LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4820 vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4821 fBadOrDisabledFifo = true;
4822 continue;
4823 }
4824 RT_UNTRUSTED_VALIDATED_FENCE();
4825 if (RT_UNLIKELY(offCurrentCmd & 3))
4826 {
4827 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4828 LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4829 offCurrentCmd &= ~UINT32_C(3);
4830 }
4831
4832 /*
4833 * Update the cursor position before we start on the FIFO commands.
4834 */
4835 /** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4836 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4837 {
4838 uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4839 if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4840 { /* halfways likely */ }
4841 else
4842 {
4843 uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4844 &xLastCursor, &yLastCursor, &fLastCursorVisible);
4845 ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4846 }
4847 }
4848
4849 /*
4850 * Mark the FIFO as busy.
4851 */
4852 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4853 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4854 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4855
4856 /*
4857 * Process all submitted command buffers.
4858 */
4859 vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4860
4861 /*
4862 * Execute all queued FIFO commands.
4863 * Quit if pending external command or changes in the thread state.
4864 */
4865 bool fDone = false;
4866 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4867 && pThread->enmState == PDMTHREADSTATE_RUNNING)
4868 {
4869 uint32_t cbPayload = 0;
4870 uint32_t u32IrqStatus = 0;
4871
4872 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4873
4874 /* First check any pending actions. */
4875 vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4876
4877 /* Check for pending external commands (reset). */
4878 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4879 break;
4880
4881 /*
4882 * Process the command.
4883 */
4884 /* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4885 * warning. Because we implement some obsolete and deprecated commands, which are not included in
4886 * the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4887 */
4888 uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4889 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4890 LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4891 offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4892 switch (enmCmdId)
4893 {
4894 case SVGA_CMD_INVALID_CMD:
4895 /* Nothing to do. */
4896 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4897 break;
4898
4899 case SVGA_CMD_FENCE:
4900 {
4901 SVGAFifoCmdFence *pCmdFence;
4902 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4903 STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4904 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4905 {
4906 Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4907 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4908
4909 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4910 {
4911 Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4912 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
4913 }
4914 else
4915 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4916 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4917 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4918 {
4919 Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4920 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
4921 }
4922 }
4923 else
4924 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4925 break;
4926 }
4927
4928 case SVGA_CMD_UPDATE:
4929 {
4930 SVGAFifoCmdUpdate *pCmd;
4931 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4932 vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4933 break;
4934 }
4935
4936 case SVGA_CMD_UPDATE_VERBOSE:
4937 {
4938 SVGAFifoCmdUpdateVerbose *pCmd;
4939 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4940 vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4941 break;
4942 }
4943
4944 case SVGA_CMD_DEFINE_CURSOR:
4945 {
4946 /* Followed by bitmap data. */
4947 SVGAFifoCmdDefineCursor *pCmd;
4948 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4949
4950 /* Figure out the size of the bitmap data. */
4951 ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4952 ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4953 ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4954 RT_UNTRUSTED_VALIDATED_FENCE();
4955
4956 uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4957 uint32_t const cbAndMask = cbAndLine * pCmd->height;
4958 uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->x