VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA-cmd.cpp

Last change on this file was 103469, checked in by vboxsync, 3 months ago

Devices/Graphics: logging
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 311.9 KB
Line 
1/* $Id: DevVGA-SVGA-cmd.cpp 103469 2024-02-20 08:15:41Z vboxsync $ */
2/** @file
3 * VMware SVGA device - implementation of VMSVGA commands.
4 */
5
6/*
7 * Copyright (C) 2013-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef IN_RING3
29# error "DevVGA-SVGA-cmd.cpp is only for ring-3 code"
30#endif
31
32
33#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
34#include <iprt/mem.h>
35#include <VBox/AssertGuest.h>
36#include <VBox/log.h>
37#include <VBox/vmm/pdmdev.h>
38#include <VBoxVideo.h>
39
40/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
41#include "DevVGA.h"
42
43/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
44#ifdef VBOX_WITH_VMSVGA3D
45# include "DevVGA-SVGA3d.h"
46#endif
47#include "DevVGA-SVGA-internal.h"
48
49#include <iprt/formats/bmp.h>
50#include <stdio.h>
51
52#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
53# define SVGA_CASE_ID2STR(idx) case idx: return #idx
54
55static const char *vmsvgaFifo3dCmdToString(SVGAFifo3dCmdId enmCmdId)
56{
57 switch (enmCmdId)
58 {
59 SVGA_CASE_ID2STR(SVGA_3D_CMD_LEGACY_BASE);
60 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE);
61 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DESTROY);
62 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_COPY);
63 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT);
64 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DMA);
65 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DEFINE);
66 SVGA_CASE_ID2STR(SVGA_3D_CMD_CONTEXT_DESTROY);
67 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTRANSFORM);
68 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETZRANGE);
69 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERSTATE);
70 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETRENDERTARGET);
71 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETTEXTURESTATE);
72 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETMATERIAL);
73 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTDATA);
74 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETLIGHTENABLED);
75 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETVIEWPORT);
76 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETCLIPPLANE);
77 SVGA_CASE_ID2STR(SVGA_3D_CMD_CLEAR);
78 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT);
79 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DEFINE);
80 SVGA_CASE_ID2STR(SVGA_3D_CMD_SHADER_DESTROY);
81 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER);
82 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_SHADER_CONST);
83 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_PRIMITIVES);
84 SVGA_CASE_ID2STR(SVGA_3D_CMD_SETSCISSORRECT);
85 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_QUERY);
86 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_QUERY);
87 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_QUERY);
88 SVGA_CASE_ID2STR(SVGA_3D_CMD_PRESENT_READBACK);
89 SVGA_CASE_ID2STR(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
90 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_DEFINE_V2);
91 SVGA_CASE_ID2STR(SVGA_3D_CMD_GENERATE_MIPMAPS);
92 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD4); /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
93 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD5); /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
94 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD6); /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
95 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD7); /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
96 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD8); /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
97 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD9); /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
98 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD10); /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
99 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD11); /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
100 SVGA_CASE_ID2STR(SVGA_3D_CMD_ACTIVATE_SURFACE);
101 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEACTIVATE_SURFACE);
102 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_DMA);
103 SVGA_CASE_ID2STR(SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION); /* SVGA_3D_CMD_DEAD1 */
104 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD2);
105 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD12); /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
106 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD13); /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
107 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD14); /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
108 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD15); /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
109 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD16); /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
110 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD17); /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
111 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE);
112 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_OTABLE);
113 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB);
114 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_MOB);
115 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEAD3);
116 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING);
117 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE);
118 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SURFACE);
119 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE);
120 SVGA_CASE_ID2STR(SVGA_3D_CMD_COND_BIND_GB_SURFACE);
121 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_IMAGE);
122 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SURFACE);
123 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE);
124 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_SURFACE);
125 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE);
126 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_SURFACE);
127 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_CONTEXT);
128 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_CONTEXT);
129 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_CONTEXT);
130 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_CONTEXT);
131 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_CONTEXT);
132 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SHADER);
133 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SHADER);
134 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SHADER);
135 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_OTABLE_BASE64);
136 SVGA_CASE_ID2STR(SVGA_3D_CMD_BEGIN_GB_QUERY);
137 SVGA_CASE_ID2STR(SVGA_3D_CMD_END_GB_QUERY);
138 SVGA_CASE_ID2STR(SVGA_3D_CMD_WAIT_FOR_GB_QUERY);
139 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP);
140 SVGA_CASE_ID2STR(SVGA_3D_CMD_ENABLE_GART);
141 SVGA_CASE_ID2STR(SVGA_3D_CMD_DISABLE_GART);
142 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAP_MOB_INTO_GART);
143 SVGA_CASE_ID2STR(SVGA_3D_CMD_UNMAP_GART_RANGE);
144 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SCREENTARGET);
145 SVGA_CASE_ID2STR(SVGA_3D_CMD_DESTROY_GB_SCREENTARGET);
146 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SCREENTARGET);
147 SVGA_CASE_ID2STR(SVGA_3D_CMD_UPDATE_GB_SCREENTARGET);
148 SVGA_CASE_ID2STR(SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL);
149 SVGA_CASE_ID2STR(SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL);
150 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE);
151 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_SCREEN_DMA);
152 SVGA_CASE_ID2STR(SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH);
153 SVGA_CASE_ID2STR(SVGA_3D_CMD_GB_MOB_FENCE);
154 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V2);
155 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_MOB64);
156 SVGA_CASE_ID2STR(SVGA_3D_CMD_REDEFINE_GB_MOB64);
157 SVGA_CASE_ID2STR(SVGA_3D_CMD_NOP_ERROR);
158 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_STREAMS);
159 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DECLS);
160 SVGA_CASE_ID2STR(SVGA_3D_CMD_SET_VERTEX_DIVISORS);
161 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW);
162 SVGA_CASE_ID2STR(SVGA_3D_CMD_DRAW_INDEXED);
163 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_CONTEXT);
164 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_CONTEXT);
165 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_CONTEXT);
166 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_CONTEXT);
167 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_CONTEXT);
168 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER);
169 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_RESOURCES);
170 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER);
171 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SAMPLERS);
172 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW);
173 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED);
174 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED);
175 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED);
176 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_AUTO);
177 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT);
178 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS);
179 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_INDEX_BUFFER);
180 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_TOPOLOGY);
181 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RENDERTARGETS);
182 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_BLEND_STATE);
183 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE);
184 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE);
185 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_QUERY);
186 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_QUERY);
187 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_QUERY);
188 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_QUERY_OFFSET);
189 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BEGIN_QUERY);
190 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_END_QUERY);
191 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_QUERY);
192 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PREDICATION);
193 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SOTARGETS);
194 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VIEWPORTS);
195 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SCISSORRECTS);
196 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW);
197 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW);
198 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY_REGION);
199 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_COPY);
200 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRESENTBLT);
201 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GENMIPS);
202 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE);
203 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_SUBRESOURCE);
204 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE);
205 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW);
206 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW);
207 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW);
208 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW);
209 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW);
210 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW);
211 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT);
212 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT);
213 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_BLEND_STATE);
214 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_BLEND_STATE);
215 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE);
216 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE);
217 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE);
218 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE);
219 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE);
220 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE);
221 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_SHADER);
222 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_SHADER);
223 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER);
224 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT);
225 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT);
226 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STREAMOUTPUT);
227 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_COTABLE);
228 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_COTABLE);
229 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_COPY);
230 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER);
231 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK);
232 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOVE_QUERY);
233 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_QUERY);
234 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_READBACK_ALL_QUERY);
235 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER);
236 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_MOB_FENCE_64);
237 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_ALL_SHADER);
238 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_HINT);
239 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BUFFER_UPDATE);
240 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET);
241 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET);
242 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET);
243 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET);
244 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET);
245 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET);
246 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER);
247 SVGA_CASE_ID2STR(SVGA_3D_CMD_SCREEN_COPY);
248 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED1);
249 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2);
250 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED3);
251 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED4);
252 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED5);
253 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED6);
254 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED7);
255 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED8);
256 SVGA_CASE_ID2STR(SVGA_3D_CMD_GROW_OTABLE);
257 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_GROW_COTABLE);
258 SVGA_CASE_ID2STR(SVGA_3D_CMD_INTRA_SURFACE_COPY);
259 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V3);
260 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_RESOLVE_COPY);
261 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_RESOLVE_COPY);
262 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT_REGION);
263 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_PRED_CONVERT);
264 SVGA_CASE_ID2STR(SVGA_3D_CMD_WHOLE_SURFACE_COPY);
265 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_UA_VIEW);
266 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DESTROY_UA_VIEW);
267 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT);
268 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT);
269 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT);
270 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_UA_VIEWS);
271 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT);
272 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT);
273 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH);
274 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DISPATCH_INDIRECT);
275 SVGA_CASE_ID2STR(SVGA_3D_CMD_WRITE_ZERO_SURFACE);
276 SVGA_CASE_ID2STR(SVGA_3D_CMD_HINT_ZERO_SURFACE);
277 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER);
278 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT);
279 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_BITBLT);
280 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_TRANSBLT);
281 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_STRETCHBLT);
282 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_COLORFILL);
283 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_ALPHABLEND);
284 SVGA_CASE_ID2STR(SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND);
285 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_1);
286 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_2);
287 SVGA_CASE_ID2STR(SVGA_3D_CMD_DEFINE_GB_SURFACE_V4);
288 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_CS_UA_VIEWS);
289 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_MIN_LOD);
290 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_3);
291 SVGA_CASE_ID2STR(SVGA_3D_CMD_RESERVED2_4);
292 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2);
293 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB);
294 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_SET_SHADER_IFACE);
295 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_STREAMOUTPUT);
296 SVGA_CASE_ID2STR(SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS);
297 SVGA_CASE_ID2STR(SVGA_3D_CMD_DX_BIND_SHADER_IFACE);
298 SVGA_CASE_ID2STR(SVGA_3D_CMD_MAX);
299 SVGA_CASE_ID2STR(SVGA_3D_CMD_FUTURE_MAX);
300
301 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR);
302 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DEFINE_VIDEO_DECODER_OUTPUT_VIEW);
303 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DEFINE_VIDEO_DECODER);
304 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_DECODER_BEGIN_FRAME);
305 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_DECODER_SUBMIT_BUFFERS);
306 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_DECODER_END_FRAME);
307 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR_INPUT_VIEW);
308 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR_OUTPUT_VIEW);
309 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_BLT);
310 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DESTROY_VIDEO_DECODER);
311 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DESTROY_VIDEO_DECODER_OUTPUT_VIEW);
312 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR);
313 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR_INPUT_VIEW);
314 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR_OUTPUT_VIEW);
315 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_TARGET_RECT);
316 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_BACKGROUND_COLOR);
317 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_COLOR_SPACE);
318 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_ALPHA_FILL_MODE);
319 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_CONSTRICTION);
320 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_STEREO_MODE);
321 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_FRAME_FORMAT);
322 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_COLOR_SPACE);
323 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_OUTPUT_RATE);
324 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_SOURCE_RECT);
325 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_DEST_RECT);
326 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_ALPHA);
327 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_PALETTE);
328 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_PIXEL_ASPECT_RATIO);
329 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_LUMA_KEY);
330 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_STEREO_FORMAT);
331 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_AUTO_PROCESSING_MODE);
332 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_FILTER);
333 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_ROTATION);
334 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_GET_VIDEO_CAPABILITY);
335 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_CLEAR_RTV);
336 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_CLEAR_UAV);
337 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_CLEAR_VDOV);
338 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_CLEAR_VPIV);
339 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_DX_CLEAR_VPOV);
340 SVGA_CASE_ID2STR(VBSVGA_3D_CMD_MAX);
341#ifndef DEBUG_sunlover
342 default: break; /* Compiler warning. */
343#endif
344 }
345 return "UNKNOWN_3D";
346}
347
348/**
349 * FIFO command name lookup
350 *
351 * @returns FIFO command string or "UNKNOWN"
352 * @param u32Cmd FIFO command
353 */
354const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
355{
356 switch (u32Cmd)
357 {
358 SVGA_CASE_ID2STR(SVGA_CMD_INVALID_CMD);
359 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE);
360 SVGA_CASE_ID2STR(SVGA_CMD_RECT_FILL);
361 SVGA_CASE_ID2STR(SVGA_CMD_RECT_COPY);
362 SVGA_CASE_ID2STR(SVGA_CMD_RECT_ROP_COPY);
363 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_CURSOR);
364 SVGA_CASE_ID2STR(SVGA_CMD_DISPLAY_CURSOR);
365 SVGA_CASE_ID2STR(SVGA_CMD_MOVE_CURSOR);
366 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_ALPHA_CURSOR);
367 SVGA_CASE_ID2STR(SVGA_CMD_UPDATE_VERBOSE);
368 SVGA_CASE_ID2STR(SVGA_CMD_FRONT_ROP_FILL);
369 SVGA_CASE_ID2STR(SVGA_CMD_FENCE);
370 SVGA_CASE_ID2STR(SVGA_CMD_ESCAPE);
371 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_SCREEN);
372 SVGA_CASE_ID2STR(SVGA_CMD_DESTROY_SCREEN);
373 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMRFB);
374 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_GMRFB_TO_SCREEN);
375 SVGA_CASE_ID2STR(SVGA_CMD_BLIT_SCREEN_TO_GMRFB);
376 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_FILL);
377 SVGA_CASE_ID2STR(SVGA_CMD_ANNOTATION_COPY);
378 SVGA_CASE_ID2STR(SVGA_CMD_DEFINE_GMR2);
379 SVGA_CASE_ID2STR(SVGA_CMD_REMAP_GMR2);
380 SVGA_CASE_ID2STR(SVGA_CMD_DEAD);
381 SVGA_CASE_ID2STR(SVGA_CMD_DEAD_2);
382 SVGA_CASE_ID2STR(SVGA_CMD_NOP);
383 SVGA_CASE_ID2STR(SVGA_CMD_NOP_ERROR);
384 SVGA_CASE_ID2STR(SVGA_CMD_MAX);
385 default:
386 if ( (u32Cmd >= SVGA_3D_CMD_BASE && u32Cmd < SVGA_3D_CMD_MAX)
387 || (u32Cmd >= VBSVGA_3D_CMD_BASE && u32Cmd < VBSVGA_3D_CMD_MAX))
388 return vmsvgaFifo3dCmdToString((SVGAFifo3dCmdId)u32Cmd);
389 }
390 return "UNKNOWN";
391}
392# undef SVGA_CASE_ID2STR
393#endif /* LOG_ENABLED || VBOX_STRICT */
394
395
396/*
397 *
398 * Guest-Backed Objects (GBO).
399 *
400 */
401
402#ifdef VBOX_WITH_VMSVGA3D
403
404static int vmsvgaR3GboCreate(PVMSVGAR3STATE pSvgaR3State, SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, PVMSVGAGBO pGbo)
405{
406 ASSERT_GUEST_RETURN(sizeInBytes <= _128M, VERR_INVALID_PARAMETER); /** @todo Less than SVGA_REG_MOB_MAX_SIZE */
407
408 /*
409 * The 'baseAddress' is a page number and points to the 'root page' of the GBO.
410 * Content of the root page depends on the ptDepth value:
411 * SVGA3D_MOBFMT_PTDEPTH[64]_0 - the only data page;
412 * SVGA3D_MOBFMT_PTDEPTH[64]_1 - array of page numbers for data pages;
413 * SVGA3D_MOBFMT_PTDEPTH[64]_2 - array of page numbers for SVGA3D_MOBFMT_PTDEPTH[64]_1 pages.
414 * The code below extracts the page addresses of the GBO.
415 */
416
417 /* Verify and normalize the ptDepth value. */
418 bool fGCPhys64; /* Whether the page table contains 64 bit page numbers. */
419 if (RT_LIKELY( ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0
420 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1
421 || ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2))
422 fGCPhys64 = true;
423 else if ( ptDepth == SVGA3D_MOBFMT_PTDEPTH_0
424 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_1
425 || ptDepth == SVGA3D_MOBFMT_PTDEPTH_2)
426 {
427 fGCPhys64 = false;
428 /* Shift ptDepth to the SVGA3D_MOBFMT_PTDEPTH64_x range. */
429 ptDepth = (SVGAMobFormat)(ptDepth + SVGA3D_MOBFMT_PTDEPTH64_0 - SVGA3D_MOBFMT_PTDEPTH_0);
430 }
431 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
432 fGCPhys64 = false; /* Does not matter, there is no page table. */
433 else
434 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
435
436 uint32_t const cPPNsPerPage = X86_PAGE_SIZE / (fGCPhys64 ? sizeof(PPN64) : sizeof(PPN));
437
438 pGbo->cbTotal = sizeInBytes;
439 pGbo->cTotalPages = (sizeInBytes + X86_PAGE_SIZE - 1) >> X86_PAGE_SHIFT;
440
441 /* Allocate the maximum amount possible (everything non-continuous) */
442 PVMSVGAGBODESCRIPTOR paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemAlloc(pGbo->cTotalPages * sizeof(VMSVGAGBODESCRIPTOR));
443 AssertReturn(paDescriptors, VERR_NO_MEMORY);
444
445 int rc = VINF_SUCCESS;
446 if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_0)
447 {
448 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages == 1,
449 RTMemFree(paDescriptors),
450 VERR_INVALID_PARAMETER);
451
452 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
453 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
454 paDescriptors[0].GCPhys = GCPhys;
455 paDescriptors[0].cPages = 1;
456 }
457 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_1)
458 {
459 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage,
460 RTMemFree(paDescriptors),
461 VERR_INVALID_PARAMETER);
462
463 /* Read the root page. */
464 uint8_t au8RootPage[X86_PAGE_SIZE];
465 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
466 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPage, sizeof(au8RootPage));
467 if (RT_SUCCESS(rc))
468 {
469 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
470 PPN *paPPN32 = (PPN *)&au8RootPage[0];
471 for (uint32_t iPPN = 0; iPPN < pGbo->cTotalPages; ++iPPN)
472 {
473 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
474 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
475 paDescriptors[iPPN].GCPhys = GCPhys;
476 paDescriptors[iPPN].cPages = 1;
477 }
478 }
479 }
480 else if (ptDepth == SVGA3D_MOBFMT_PTDEPTH64_2)
481 {
482 ASSERT_GUEST_STMT_RETURN(pGbo->cTotalPages <= cPPNsPerPage * cPPNsPerPage,
483 RTMemFree(paDescriptors),
484 VERR_INVALID_PARAMETER);
485
486 /* Read the Level2 root page. */
487 uint8_t au8RootPageLevel2[X86_PAGE_SIZE];
488 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
489 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhys, &au8RootPageLevel2, sizeof(au8RootPageLevel2));
490 if (RT_SUCCESS(rc))
491 {
492 uint32_t cPagesLeft = pGbo->cTotalPages;
493
494 PPN64 *paPPN64Level2 = (PPN64 *)&au8RootPageLevel2[0];
495 PPN *paPPN32Level2 = (PPN *)&au8RootPageLevel2[0];
496
497 uint32_t const cPPNsLevel2 = (pGbo->cTotalPages + cPPNsPerPage - 1) / cPPNsPerPage;
498 for (uint32_t iPPNLevel2 = 0; iPPNLevel2 < cPPNsLevel2; ++iPPNLevel2)
499 {
500 /* Read the Level1 root page. */
501 uint8_t au8RootPage[X86_PAGE_SIZE];
502 RTGCPHYS GCPhysLevel1 = (RTGCPHYS)(fGCPhys64 ? paPPN64Level2[iPPNLevel2] : paPPN32Level2[iPPNLevel2]) << X86_PAGE_SHIFT;
503 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
504 rc = PDMDevHlpPCIPhysRead(pSvgaR3State->pDevIns, GCPhysLevel1, &au8RootPage, sizeof(au8RootPage));
505 if (RT_SUCCESS(rc))
506 {
507 PPN64 *paPPN64 = (PPN64 *)&au8RootPage[0];
508 PPN *paPPN32 = (PPN *)&au8RootPage[0];
509
510 uint32_t const cPPNs = RT_MIN(cPagesLeft, cPPNsPerPage);
511 for (uint32_t iPPN = 0; iPPN < cPPNs; ++iPPN)
512 {
513 GCPhys = (RTGCPHYS)(fGCPhys64 ? paPPN64[iPPN] : paPPN32[iPPN]) << X86_PAGE_SHIFT;
514 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
515 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].GCPhys = GCPhys;
516 paDescriptors[iPPN + iPPNLevel2 * cPPNsPerPage].cPages = 1;
517 }
518 cPagesLeft -= cPPNs;
519 }
520 }
521 }
522 }
523 else if (ptDepth == SVGA3D_MOBFMT_RANGE)
524 {
525 RTGCPHYS GCPhys = (RTGCPHYS)baseAddress << X86_PAGE_SHIFT;
526 GCPhys &= UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
527 paDescriptors[0].GCPhys = GCPhys;
528 paDescriptors[0].cPages = pGbo->cTotalPages;
529 }
530 else
531 {
532 AssertFailed();
533 return VERR_INTERNAL_ERROR; /* ptDepth should be already verified. */
534 }
535
536 /* Compress the descriptors. */
537 if (ptDepth != SVGA3D_MOBFMT_RANGE)
538 {
539 uint32_t iDescriptor = 0;
540 for (uint32_t i = 1; i < pGbo->cTotalPages; ++i)
541 {
542 /* Continuous physical memory? */
543 if (paDescriptors[i].GCPhys == paDescriptors[iDescriptor].GCPhys + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
544 {
545 Assert(paDescriptors[iDescriptor].cPages);
546 paDescriptors[iDescriptor].cPages++;
547 Log5Func(("Page %x GCPhys=%RGp successor\n", i, paDescriptors[i].GCPhys));
548 }
549 else
550 {
551 iDescriptor++;
552 paDescriptors[iDescriptor].GCPhys = paDescriptors[i].GCPhys;
553 paDescriptors[iDescriptor].cPages = 1;
554 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescriptors[iDescriptor].GCPhys));
555 }
556 }
557
558 pGbo->cDescriptors = iDescriptor + 1;
559 Log5Func(("Nr of descriptors %d\n", pGbo->cDescriptors));
560 }
561 else
562 pGbo->cDescriptors = 1;
563
564 if (RT_LIKELY(pGbo->cDescriptors < pGbo->cTotalPages))
565 {
566 pGbo->paDescriptors = (PVMSVGAGBODESCRIPTOR)RTMemRealloc(paDescriptors, pGbo->cDescriptors * sizeof(VMSVGAGBODESCRIPTOR));
567 AssertReturn(pGbo->paDescriptors, VERR_NO_MEMORY);
568 }
569 else
570 pGbo->paDescriptors = paDescriptors;
571
572 pGbo->fGboFlags = 0;
573 pGbo->pvHost = NULL;
574
575 return VINF_SUCCESS;
576}
577
578
579static void vmsvgaR3GboDestroy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
580{
581 RT_NOREF(pSvgaR3State);
582
583 if (RT_LIKELY(VMSVGA_IS_GBO_CREATED(pGbo)))
584 {
585 RTMemFree(pGbo->pvHost);
586 RTMemFree(pGbo->paDescriptors);
587 RT_ZERO(*pGbo);
588 }
589}
590
591/** @todo static void vmsvgaR3GboWriteProtect(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, bool fWriteProtect) */
592
593typedef enum VMSVGAGboTransferDirection
594{
595 VMSVGAGboTransferDirection_Read,
596 VMSVGAGboTransferDirection_Write,
597} VMSVGAGboTransferDirection;
598
599static int vmsvgaR3GboTransfer(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
600 uint32_t off, void *pvData, uint32_t cbData,
601 VMSVGAGboTransferDirection enmDirection)
602{
603 //DEBUG_BREAKPOINT_TEST();
604 int rc = VINF_SUCCESS;
605 uint8_t *pu8CurrentHost = (uint8_t *)pvData;
606
607 /* Find the right descriptor */
608 PCVMSVGAGBODESCRIPTOR const paDescriptors = pGbo->paDescriptors;
609 uint32_t iDescriptor = 0; /* Index in the descriptor array. */
610 uint32_t offDescriptor = 0; /* GMR offset of the current descriptor. */
611 while (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE <= off)
612 {
613 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
614 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
615 ++iDescriptor;
616 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
617 }
618
619 while (cbData)
620 {
621 uint32_t cbToCopy;
622 if (off + cbData <= offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE)
623 cbToCopy = cbData;
624 else
625 {
626 cbToCopy = (offDescriptor + paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE - off);
627 AssertReturn(cbToCopy <= cbData, VERR_INVALID_PARAMETER);
628 }
629
630 RTGCPHYS const GCPhys = paDescriptors[iDescriptor].GCPhys + off - offDescriptor;
631 Log5Func(("%s phys=%RGp\n", (enmDirection == VMSVGAGboTransferDirection_Read) ? "READ" : "WRITE", GCPhys));
632
633 /*
634 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
635 * guest-side VMSVGA driver seems to allocate non-DMA (regular physical) addresses,
636 * see @bugref{9654#c75}.
637 */
638 if (enmDirection == VMSVGAGboTransferDirection_Read)
639 rc = PDMDevHlpPhysRead(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
640 else
641 rc = PDMDevHlpPhysWrite(pSvgaR3State->pDevIns, GCPhys, pu8CurrentHost, cbToCopy);
642 AssertRCBreak(rc);
643
644 cbData -= cbToCopy;
645 off += cbToCopy;
646 pu8CurrentHost += cbToCopy;
647
648 /* Go to the next descriptor if there's anything left. */
649 if (cbData)
650 {
651 offDescriptor += paDescriptors[iDescriptor].cPages * X86_PAGE_SIZE;
652 AssertReturn(offDescriptor < pGbo->cbTotal, VERR_INTERNAL_ERROR);
653 ++iDescriptor;
654 AssertReturn(iDescriptor < pGbo->cDescriptors, VERR_INTERNAL_ERROR);
655 }
656 }
657 return rc;
658}
659
660
661static int vmsvgaR3GboWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
662 uint32_t off, void const *pvData, uint32_t cbData)
663{
664 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
665 off, (void *)pvData, cbData,
666 VMSVGAGboTransferDirection_Write);
667}
668
669
670static int vmsvgaR3GboRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo,
671 uint32_t off, void *pvData, uint32_t cbData)
672{
673 return vmsvgaR3GboTransfer(pSvgaR3State, pGbo,
674 off, pvData, cbData,
675 VMSVGAGboTransferDirection_Read);
676}
677
678
679static int vmsvgaR3GboBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo, uint32_t cbValid)
680{
681 int rc;
682
683 /* Just reread the data if pvHost has been allocated already. */
684 if (!(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED))
685 pGbo->pvHost = RTMemAllocZ(pGbo->cbTotal);
686
687 if (pGbo->pvHost)
688 {
689 cbValid = RT_MIN(cbValid, pGbo->cbTotal);
690 rc = vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, cbValid);
691 }
692 else
693 rc = VERR_NO_MEMORY;
694
695 if (RT_SUCCESS(rc))
696 pGbo->fGboFlags |= VMSVGAGBO_F_HOST_BACKED;
697 else
698 {
699 RTMemFree(pGbo->pvHost);
700 pGbo->pvHost = NULL;
701 }
702 return rc;
703}
704
705
706static void vmsvgaR3GboBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
707{
708 RT_NOREF(pSvgaR3State);
709 AssertReturnVoid(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED);
710 RTMemFree(pGbo->pvHost);
711 pGbo->pvHost = NULL;
712 pGbo->fGboFlags &= ~VMSVGAGBO_F_HOST_BACKED;
713}
714
715
716static int vmsvgaR3GboBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
717{
718 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
719 return vmsvgaR3GboWrite(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
720}
721
722
723static int vmsvgaR3GboBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGbo)
724{
725 AssertReturn(pGbo->fGboFlags & VMSVGAGBO_F_HOST_BACKED, VERR_INVALID_STATE);
726 return vmsvgaR3GboRead(pSvgaR3State, pGbo, 0, pGbo->pvHost, pGbo->cbTotal);
727}
728
729static int vmsvgaR3GboCopy(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboDst, uint32_t offDst,
730 PVMSVGAGBO pGboSrc, uint32_t offSrc, uint32_t cbCopy)
731{
732 uint32_t const cbTmpBuf = GUEST_PAGE_SIZE;
733 void *pvTmpBuf = RTMemTmpAlloc(cbTmpBuf);
734 AssertPtrReturn(pvTmpBuf, VERR_NO_MEMORY);
735
736 int rc = VINF_SUCCESS;
737 while (cbCopy > 0)
738 {
739 uint32_t const cbToCopy = RT_MIN(cbTmpBuf, cbCopy);
740
741 rc = vmsvgaR3GboRead(pSvgaR3State, pGboSrc, offSrc, pvTmpBuf, cbToCopy);
742 AssertRCBreak(rc);
743
744 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboDst, offDst, pvTmpBuf, cbToCopy);
745 AssertRCBreak(rc);
746
747 offSrc += cbToCopy;
748 offDst += cbToCopy;
749 cbCopy -= cbToCopy;
750 }
751
752 RTMemTmpFree(pvTmpBuf);
753 return rc;
754}
755
756
757/*
758 *
759 * Object Tables.
760 *
761 */
762
763static int vmsvgaR3OTableSetOrGrow(PVMSVGAR3STATE pSvgaR3State, SVGAOTableType type, PPN64 baseAddress,
764 uint32_t sizeInBytes, uint32 validSizeInBytes, SVGAMobFormat ptDepth, bool fGrow)
765{
766 ASSERT_GUEST_RETURN(type < RT_ELEMENTS(pSvgaR3State->aGboOTables), VERR_INVALID_PARAMETER);
767 ASSERT_GUEST_RETURN(sizeInBytes >= validSizeInBytes, VERR_INVALID_PARAMETER);
768 RT_UNTRUSTED_VALIDATED_FENCE();
769
770 ASSERT_GUEST_RETURN(pSvgaR3State->aGboOTables[type].cbTotal >= validSizeInBytes, VERR_INVALID_PARAMETER);
771
772 if (sizeInBytes > 0)
773 {
774 /* Create a new guest backed object for the object table. */
775 VMSVGAGBO gbo;
776 int rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, &gbo);
777 AssertRCReturn(rc, rc);
778
779 /* If the guest sets a new OTable (fGrow == false), then it has already copied the valid data to the new GBO. */
780 if (fGrow && validSizeInBytes)
781 {
782 /* Copy data from old gbo to the new one. */
783 rc = vmsvgaR3GboCopy(pSvgaR3State, &gbo, 0, &pSvgaR3State->aGboOTables[type], 0, validSizeInBytes);
784 AssertRCReturnStmt(rc, vmsvgaR3GboDestroy(pSvgaR3State, &gbo), rc);
785 }
786
787 vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[type]);
788 pSvgaR3State->aGboOTables[type] = gbo;
789
790 }
791 else
792 vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[type]);
793
794 return VINF_SUCCESS;
795}
796
797
798static int vmsvgaR3OTableVerifyIndex(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
799 uint32_t idx, uint32_t cbEntry)
800{
801 RT_NOREF(pSvgaR3State);
802
803 /* The table must exist and the index must be within the table. */
804 ASSERT_GUEST_RETURN(VMSVGA_IS_GBO_CREATED(pGboOTable), VERR_INVALID_PARAMETER);
805 ASSERT_GUEST_RETURN(idx < pGboOTable->cbTotal / cbEntry, VERR_INVALID_PARAMETER);
806 RT_UNTRUSTED_VALIDATED_FENCE();
807 return VINF_SUCCESS;
808}
809
810
811static int vmsvgaR3OTableRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
812 uint32_t idx, uint32_t cbEntry,
813 void *pvData, uint32_t cbData)
814{
815 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
816
817 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
818 if (RT_SUCCESS(rc))
819 {
820 uint32_t const off = idx * cbEntry;
821 rc = vmsvgaR3GboRead(pSvgaR3State, pGboOTable, off, pvData, cbData);
822 }
823 return rc;
824}
825
826static int vmsvgaR3OTableWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAGBO pGboOTable,
827 uint32_t idx, uint32_t cbEntry,
828 void const *pvData, uint32_t cbData)
829{
830 AssertReturn(cbData <= cbEntry, VERR_INVALID_PARAMETER);
831
832 int rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, pGboOTable, idx, cbEntry);
833 if (RT_SUCCESS(rc))
834 {
835 uint32_t const off = idx * cbEntry;
836 rc = vmsvgaR3GboWrite(pSvgaR3State, pGboOTable, off, pvData, cbData);
837 }
838 return rc;
839}
840
841
842int vmsvgaR3OTableReadSurface(PVMSVGAR3STATE pSvgaR3State, uint32_t sid, SVGAOTableSurfaceEntry *pEntrySurface)
843{
844 return vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
845 sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, pEntrySurface, sizeof(SVGAOTableSurfaceEntry));
846}
847
848
849/*
850 *
851 * The guest's Memory OBjects (MOB).
852 *
853 */
854
855static int vmsvgaR3MobCreate(PVMSVGAR3STATE pSvgaR3State,
856 SVGAMobFormat ptDepth, PPN64 baseAddress, uint32_t sizeInBytes, SVGAMobId mobid,
857 PVMSVGAMOB pMob)
858{
859 RT_ZERO(*pMob);
860
861 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
862 SVGAOTableMobEntry entry;
863 entry.ptDepth = ptDepth;
864 entry.sizeInBytes = sizeInBytes;
865 entry.base = baseAddress;
866 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
867 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
868 if (RT_SUCCESS(rc))
869 {
870 /* Create the corresponding GBO. */
871 rc = vmsvgaR3GboCreate(pSvgaR3State, ptDepth, baseAddress, sizeInBytes, &pMob->Gbo);
872 if (RT_SUCCESS(rc))
873 {
874 /* If a mob with this id already exists, then delete it. */
875 PVMSVGAMOB pOldMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
876 if (pOldMob)
877 {
878 /* This should not happen. */
879 ASSERT_GUEST_FAILED();
880 RTListNodeRemove(&pOldMob->nodeLRU);
881 vmsvgaR3GboDestroy(pSvgaR3State, &pOldMob->Gbo);
882 RTMemFree(pOldMob);
883 }
884
885 /* Add to the tree of known MOBs and the LRU list. */
886 pMob->Core.Key = mobid;
887 if (RTAvlU32Insert(&pSvgaR3State->MOBTree, &pMob->Core))
888 {
889 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
890 return VINF_SUCCESS;
891 }
892
893 AssertFailedStmt(rc = VERR_INVALID_STATE);
894 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
895 }
896 }
897
898 return rc;
899}
900
901
902static void vmsvgaR3MobFree(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
903{
904 vmsvgaR3GboDestroy(pSvgaR3State, &pMob->Gbo);
905 RTMemFree(pMob);
906}
907
908
909static int vmsvgaR3MobDestroy(PVMSVGAR3STATE pSvgaR3State, SVGAMobId mobid)
910{
911 /* Update the entry in the pSvgaR3State->pGboOTableMob. */
912 SVGAOTableMobEntry entry;
913 RT_ZERO(entry);
914 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
915 mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE, &entry, sizeof(entry));
916
917 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Remove(&pSvgaR3State->MOBTree, mobid);
918 if (pMob)
919 {
920 RTListNodeRemove(&pMob->nodeLRU);
921 vmsvgaR3MobFree(pSvgaR3State, pMob);
922 return VINF_SUCCESS;
923 }
924
925 return VERR_INVALID_PARAMETER;
926}
927
928
929PVMSVGAMOB vmsvgaR3MobGet(PVMSVGAR3STATE pSvgaR3State, SVGAMobId RT_UNTRUSTED_GUEST mobid)
930{
931 if (mobid == SVGA_ID_INVALID)
932 return NULL;
933
934 PVMSVGAMOB pMob = (PVMSVGAMOB)RTAvlU32Get(&pSvgaR3State->MOBTree, mobid);
935 if (pMob)
936 {
937 /* Move to the head of the LRU list. */
938 RTListNodeRemove(&pMob->nodeLRU);
939 RTListPrepend(&pSvgaR3State->MOBLRUList, &pMob->nodeLRU);
940 }
941 else
942 ASSERT_GUEST_FAILED();
943
944 return pMob;
945}
946
947
948int vmsvgaR3MobWrite(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
949 uint32_t off, void const *pvData, uint32_t cbData)
950{
951 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
952}
953
954
955int vmsvgaR3MobRead(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob,
956 uint32_t off, void *pvData, uint32_t cbData)
957{
958 return vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, off, pvData, cbData);
959}
960
961
962/** Create a host ring-3 pointer to the MOB data.
963 * Current approach is to allocate a host memory buffer and copy the guest MOB data if necessary.
964 * @param pSvgaR3State R3 device state.
965 * @param pMob The MOB.
966 * @param cbValid How many bytes of the guest backing memory contain valid data.
967 * @return VBox status.
968 */
969/** @todo uint32_t cbValid -> uint32_t offStart, uint32_t cbData */
970int vmsvgaR3MobBackingStoreCreate(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob, uint32_t cbValid)
971{
972 AssertReturn(pMob, VERR_INVALID_PARAMETER);
973 return vmsvgaR3GboBackingStoreCreate(pSvgaR3State, &pMob->Gbo, cbValid);
974}
975
976
977void vmsvgaR3MobBackingStoreDelete(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
978{
979 if (pMob)
980 vmsvgaR3GboBackingStoreDelete(pSvgaR3State, &pMob->Gbo);
981}
982
983
984int vmsvgaR3MobBackingStoreWriteToGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
985{
986 if (pMob)
987 return vmsvgaR3GboBackingStoreWriteToGuest(pSvgaR3State, &pMob->Gbo);
988 return VERR_INVALID_PARAMETER;
989}
990
991
992int vmsvgaR3MobBackingStoreReadFromGuest(PVMSVGAR3STATE pSvgaR3State, PVMSVGAMOB pMob)
993{
994 if (pMob)
995 return vmsvgaR3GboBackingStoreReadFromGuest(pSvgaR3State, &pMob->Gbo);
996 return VERR_INVALID_PARAMETER;
997}
998
999
1000void *vmsvgaR3MobBackingStorePtr(PVMSVGAMOB pMob, uint32_t off)
1001{
1002 if (pMob && (pMob->Gbo.fGboFlags & VMSVGAGBO_F_HOST_BACKED))
1003 {
1004 if (off <= pMob->Gbo.cbTotal)
1005 return (uint8_t *)pMob->Gbo.pvHost + off;
1006 }
1007 return NULL;
1008}
1009
1010
1011static DECLCALLBACK(int) vmsvgaR3MobFreeCb(PAVLU32NODECORE pNode, void *pvUser)
1012{
1013 PVMSVGAMOB pMob = (PVMSVGAMOB)pNode;
1014 PVMSVGAR3STATE pSvgaR3State = (PVMSVGAR3STATE)pvUser;
1015 vmsvgaR3MobFree(pSvgaR3State, pMob);
1016 return 0;
1017}
1018
1019
1020#endif /* VBOX_WITH_VMSVGA3D */
1021
1022
1023
1024void vmsvgaR3ResetSvgaState(PVGASTATE pThis, PVGASTATECC pThisCC)
1025{
1026#ifdef VBOX_WITH_VMSVGA3D
1027 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1028 RT_NOREF(pThis);
1029
1030 RTAvlU32Destroy(&pSvgaR3State->MOBTree, vmsvgaR3MobFreeCb, pSvgaR3State);
1031 RTListInit(&pSvgaR3State->MOBLRUList);
1032
1033 for (unsigned i = 0; i < RT_ELEMENTS(pSvgaR3State->aGboOTables); ++i)
1034 vmsvgaR3GboDestroy(pSvgaR3State, &pSvgaR3State->aGboOTables[i]);
1035#else
1036 RT_NOREF(pThis, pThisCC);
1037#endif
1038}
1039
1040
1041void vmsvgaR3TerminateSvgaState(PVGASTATE pThis, PVGASTATECC pThisCC)
1042{
1043 vmsvgaR3ResetSvgaState(pThis, pThisCC);
1044}
1045
1046
1047/*
1048 * Screen objects.
1049 */
1050VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
1051{
1052 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1053 if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
1054 && pSVGAState
1055 && pSVGAState->aScreens[idScreen].fDefined)
1056 {
1057 Assert(pSVGAState->aScreens[idScreen].idScreen == idScreen);
1058 return &pSVGAState->aScreens[idScreen];
1059 }
1060 return NULL;
1061}
1062
1063
1064int vmsvgaR3DestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen)
1065{
1066 pScreen->fModified = true;
1067 pScreen->fDefined = false;
1068
1069 /* Notify frontend that the screen is about to be deleted. */
1070 vmsvgaR3ChangeMode(pThis, pThisCC);
1071
1072#ifdef VBOX_WITH_VMSVGA3D
1073 if (RT_LIKELY(pThis->svga.f3DEnabled))
1074 vmsvga3dDestroyScreen(pThisCC, pScreen);
1075#endif
1076
1077 RTMemFree(pScreen->pvScreenBitmap);
1078 pScreen->pvScreenBitmap = NULL;
1079
1080 return VINF_SUCCESS;
1081}
1082
1083
1084void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
1085{
1086 for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
1087 {
1088 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
1089 if (pScreen)
1090 vmsvgaR3DestroyScreen(pThis, pThisCC, pScreen);
1091 }
1092}
1093
1094
1095/**
1096 * Copy a rectangle of pixels within guest VRAM.
1097 */
1098static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1099 uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1100{
1101 if (!width || !height)
1102 return; /* Nothing to do, don't even bother. */
1103
1104 /*
1105 * The guest VRAM (aka GFB) is considered to be a bitmap in the format
1106 * corresponding to the current display mode.
1107 */
1108 uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1109 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1110 uint8_t const *pSrc;
1111 uint8_t *pDst;
1112 unsigned const cbRectWidth = width * cbPixel;
1113 unsigned uMaxOffset;
1114
1115 uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1116 if (uMaxOffset >= cbFrameBuffer)
1117 {
1118 Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1119 return; /* Just don't listen to a bad guest. */
1120 }
1121
1122 pSrc = pDst = pThisCC->pbVRam;
1123 pSrc += srcY * cbScanline + srcX * cbPixel;
1124 pDst += dstY * cbScanline + dstX * cbPixel;
1125
1126 if (srcY >= dstY)
1127 {
1128 /* Source below destination, copy top to bottom. */
1129 for (; height > 0; height--)
1130 {
1131 memmove(pDst, pSrc, cbRectWidth);
1132 pSrc += cbScanline;
1133 pDst += cbScanline;
1134 }
1135 }
1136 else
1137 {
1138 /* Source above destination, copy bottom to top. */
1139 pSrc += cbScanline * (height - 1);
1140 pDst += cbScanline * (height - 1);
1141 for (; height > 0; height--)
1142 {
1143 memmove(pDst, pSrc, cbRectWidth);
1144 pSrc -= cbScanline;
1145 pDst -= cbScanline;
1146 }
1147 }
1148}
1149
1150
1151/**
1152 * Common worker for changing the pointer shape.
1153 *
1154 * @param pThisCC The VGA/VMSVGA state for ring-3.
1155 * @param pSVGAState The VMSVGA ring-3 instance data.
1156 * @param fAlpha Whether there is alpha or not.
1157 * @param xHot Hotspot x coordinate.
1158 * @param yHot Hotspot y coordinate.
1159 * @param cx Width.
1160 * @param cy Height.
1161 * @param pbData Heap copy of the cursor data. Consumed.
1162 * @param cbData The size of the data.
1163 */
1164static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
1165 uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
1166{
1167 LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
1168#ifdef LOG_ENABLED
1169 if (LogIs2Enabled())
1170 {
1171 uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
1172 if (!fAlpha)
1173 {
1174 Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
1175 for (uint32_t y = 0; y < cy; y++)
1176 {
1177 Log2(("%3u:", y));
1178 uint8_t const *pbLine = &pbData[y * cbAndLine];
1179 for (uint32_t x = 0; x < cx; x += 8)
1180 {
1181 uint8_t b = pbLine[x / 8];
1182 char szByte[12];
1183 szByte[0] = b & 0x80 ? '*' : ' '; /* most significant bit first */
1184 szByte[1] = b & 0x40 ? '*' : ' ';
1185 szByte[2] = b & 0x20 ? '*' : ' ';
1186 szByte[3] = b & 0x10 ? '*' : ' ';
1187 szByte[4] = b & 0x08 ? '*' : ' ';
1188 szByte[5] = b & 0x04 ? '*' : ' ';
1189 szByte[6] = b & 0x02 ? '*' : ' ';
1190 szByte[7] = b & 0x01 ? '*' : ' ';
1191 szByte[8] = '\0';
1192 Log2(("%s", szByte));
1193 }
1194 Log2(("\n"));
1195 }
1196 }
1197
1198 Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
1199 uint32_t const *pu32Xor = (uint32_t const *)&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
1200 for (uint32_t y = 0; y < cy; y++)
1201 {
1202 Log2(("%3u:", y));
1203 uint32_t const *pu32Line = &pu32Xor[y * cx];
1204 for (uint32_t x = 0; x < cx; x++)
1205 Log2((" %08x", pu32Line[x]));
1206 Log2(("\n"));
1207 }
1208 }
1209#endif
1210
1211 int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, fAlpha, xHot, yHot, cx, cy, pbData);
1212 AssertRC(rc);
1213
1214 if (pSVGAState->Cursor.fActive)
1215 RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
1216
1217 pSVGAState->Cursor.fActive = true;
1218 pSVGAState->Cursor.xHotspot = xHot;
1219 pSVGAState->Cursor.yHotspot = yHot;
1220 pSVGAState->Cursor.width = cx;
1221 pSVGAState->Cursor.height = cy;
1222 pSVGAState->Cursor.cbData = cbData;
1223 pSVGAState->Cursor.pData = pbData;
1224}
1225
1226
1227#ifdef VBOX_WITH_VMSVGA3D
1228
1229/*
1230 * SVGA_3D_CMD_* handlers.
1231 */
1232
1233
1234/** SVGA_3D_CMD_SURFACE_DEFINE 1040, SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
1235 *
1236 * @param pThisCC The VGA/VMSVGA state for the current context.
1237 * @param pCmd The VMSVGA command.
1238 * @param cMipLevelSizes Number of elements in the paMipLevelSizes array.
1239 * @param paMipLevelSizes Arrays of surface sizes for each face and miplevel.
1240 */
1241static void vmsvga3dCmdDefineSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineSurface_v2 const *pCmd,
1242 uint32_t cMipLevelSizes, SVGA3dSize *paMipLevelSizes)
1243{
1244 ASSERT_GUEST_RETURN_VOID(pCmd->sid < SVGA3D_MAX_SURFACE_IDS);
1245 ASSERT_GUEST_RETURN_VOID(cMipLevelSizes >= 1);
1246 RT_UNTRUSTED_VALIDATED_FENCE();
1247
1248 /* Number of faces (cFaces) is specified as the number of the first non-zero elements in the 'face' array.
1249 * Since only plain surfaces (cFaces == 1) and cubemaps (cFaces == 6) are supported
1250 * (see also SVGA3dCmdDefineSurface definition in svga3d_reg.h), we ignore anything else.
1251 */
1252 uint32_t cRemainingMipLevels = cMipLevelSizes;
1253 uint32_t cFaces = 0;
1254 for (uint32_t i = 0; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1255 {
1256 if (pCmd->face[i].numMipLevels == 0)
1257 break;
1258
1259 /* All SVGA3dSurfaceFace structures must have the same value of numMipLevels field */
1260 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == pCmd->face[0].numMipLevels);
1261
1262 /* numMipLevels value can't be greater than the number of remaining elements in the paMipLevelSizes array. */
1263 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels <= cRemainingMipLevels);
1264 cRemainingMipLevels -= pCmd->face[i].numMipLevels;
1265
1266 ++cFaces;
1267 }
1268 for (uint32_t i = cFaces; i < SVGA3D_MAX_SURFACE_FACES; ++i)
1269 ASSERT_GUEST_RETURN_VOID(pCmd->face[i].numMipLevels == 0);
1270
1271 /* cFaces must be 6 for a cubemap and 1 otherwise. */
1272 ASSERT_GUEST_RETURN_VOID(cFaces == (uint32_t)((pCmd->surfaceFlags & SVGA3D_SURFACE_CUBEMAP) ? 6 : 1));
1273
1274 /* Sum of face[i].numMipLevels must be equal to cMipLevels. */
1275 ASSERT_GUEST_RETURN_VOID(cRemainingMipLevels == 0);
1276 RT_UNTRUSTED_VALIDATED_FENCE();
1277
1278 /* Verify paMipLevelSizes */
1279 uint32_t cWidth = paMipLevelSizes[0].width;
1280 uint32_t cHeight = paMipLevelSizes[0].height;
1281 uint32_t cDepth = paMipLevelSizes[0].depth;
1282 for (uint32_t i = 1; i < pCmd->face[0].numMipLevels; ++i)
1283 {
1284 cWidth >>= 1;
1285 if (cWidth == 0) cWidth = 1;
1286 cHeight >>= 1;
1287 if (cHeight == 0) cHeight = 1;
1288 cDepth >>= 1;
1289 if (cDepth == 0) cDepth = 1;
1290 for (uint32_t iFace = 0; iFace < cFaces; ++iFace)
1291 {
1292 uint32_t const iMipLevelSize = iFace * pCmd->face[0].numMipLevels + i;
1293 ASSERT_GUEST_RETURN_VOID( cWidth == paMipLevelSizes[iMipLevelSize].width
1294 && cHeight == paMipLevelSizes[iMipLevelSize].height
1295 && cDepth == paMipLevelSizes[iMipLevelSize].depth);
1296 }
1297 }
1298 RT_UNTRUSTED_VALIDATED_FENCE();
1299
1300 /* Create the surface. */
1301 SVGA3dMSPattern const multisamplePattern = pCmd->multisampleCount > 1 ? SVGA3D_MS_PATTERN_STANDARD : SVGA3D_MS_PATTERN_NONE;
1302 SVGA3dMSQualityLevel const qualityLevel = pCmd->multisampleCount > 1 ? SVGA3D_MS_QUALITY_FULL : SVGA3D_MS_QUALITY_NONE;
1303 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1304 pCmd->multisampleCount, multisamplePattern, qualityLevel, pCmd->autogenFilter,
1305 pCmd->face[0].numMipLevels, &paMipLevelSizes[0], /* arraySize = */ 0, /* bufferByteStride = */ 0, /* fAllocMipLevels = */ true);
1306}
1307
1308
1309/* SVGA_3D_CMD_SET_OTABLE_BASE 1091 */
1310static void vmsvga3dCmdSetOTableBase(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase const *pCmd)
1311{
1312 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1313 vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
1314 pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /*fGrow*/ false);
1315}
1316
1317
1318/* SVGA_3D_CMD_DEFINE_GB_MOB 1093 */
1319static void vmsvga3dCmdDefineGBMob(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob const *pCmd)
1320{
1321 DEBUG_BREAKPOINT_TEST();
1322 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1323
1324 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1325
1326 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
1327 /* Allocate a structure for the MOB. */
1328 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
1329 AssertPtrReturnVoid(pMob);
1330
1331 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, pMob);
1332 if (RT_SUCCESS(rc))
1333 {
1334 return;
1335 }
1336
1337 AssertFailed();
1338
1339 RTMemFree(pMob);
1340}
1341
1342
1343/* SVGA_3D_CMD_DESTROY_GB_MOB 1094 */
1344static void vmsvga3dCmdDestroyGBMob(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBMob const *pCmd)
1345{
1346 //DEBUG_BREAKPOINT_TEST();
1347 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1348
1349 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
1350
1351 int rc = vmsvgaR3MobDestroy(pSvgaR3State, pCmd->mobid);
1352 if (RT_SUCCESS(rc))
1353 {
1354 return;
1355 }
1356
1357 AssertFailed();
1358}
1359
1360
1361/* SVGA_3D_CMD_DEFINE_GB_SURFACE 1097 */
1362static void vmsvga3dCmdDefineGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface const *pCmd)
1363{
1364 //DEBUG_BREAKPOINT_TEST();
1365 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1366
1367 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1368 SVGAOTableSurfaceEntry entry;
1369 RT_ZERO(entry);
1370 entry.format = pCmd->format;
1371 entry.surface1Flags = pCmd->surfaceFlags;
1372 entry.numMipLevels = pCmd->numMipLevels;
1373 entry.multisampleCount = pCmd->multisampleCount;
1374 entry.autogenFilter = pCmd->autogenFilter;
1375 entry.size = pCmd->size;
1376 entry.mobid = SVGA_ID_INVALID;
1377 // entry.arraySize = 0;
1378 // entry.mobPitch = 0;
1379 // entry.surface2Flags = 0;
1380 // entry.multisamplePattern = 0;
1381 // entry.qualityLevel = 0;
1382 // entry.bufferByteStride = 0;
1383 // entry.minLOD = 0;
1384 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1385 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1386 if (RT_SUCCESS(rc))
1387 {
1388 /* Create the host surface. */
1389 SVGA3dMSPattern const multisamplePattern = pCmd->multisampleCount > 1 ? SVGA3D_MS_PATTERN_STANDARD : SVGA3D_MS_PATTERN_NONE;
1390 SVGA3dMSQualityLevel const qualityLevel = pCmd->multisampleCount > 1 ? SVGA3D_MS_QUALITY_FULL : SVGA3D_MS_QUALITY_NONE;
1391 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
1392 pCmd->multisampleCount, multisamplePattern, qualityLevel, pCmd->autogenFilter,
1393 pCmd->numMipLevels, &pCmd->size, /* arraySize = */ 0, /* bufferByteStride = */ 0, /* fAllocMipLevels = */ false);
1394 }
1395}
1396
1397
1398/* SVGA_3D_CMD_DESTROY_GB_SURFACE 1098 */
1399static void vmsvga3dCmdDestroyGBSurface(PVGASTATECC pThisCC, SVGA3dCmdDestroyGBSurface const *pCmd)
1400{
1401 //DEBUG_BREAKPOINT_TEST();
1402 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1403
1404 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
1405 SVGAOTableSurfaceEntry entry;
1406 RT_ZERO(entry);
1407 entry.mobid = SVGA_ID_INVALID;
1408 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1409 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1410
1411 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
1412}
1413
1414
1415/* SVGA_3D_CMD_BIND_GB_SURFACE 1099 */
1416static void vmsvga3dCmdBindGBSurface(PVGASTATECC pThisCC, SVGA3dCmdBindGBSurface const *pCmd)
1417{
1418 //DEBUG_BREAKPOINT_TEST();
1419 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1420
1421 /* Assign the mobid to the surface. */
1422 int rc = VINF_SUCCESS;
1423 if (pCmd->mobid != SVGA_ID_INVALID)
1424 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
1425 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
1426 if (RT_SUCCESS(rc))
1427 {
1428 SVGAOTableSurfaceEntry entry;
1429 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1430 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1431 if (RT_SUCCESS(rc))
1432 {
1433 entry.mobid = pCmd->mobid;
1434 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1435 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
1436 if (RT_SUCCESS(rc))
1437 {
1438 /* */
1439 }
1440 }
1441 }
1442}
1443
1444
1445typedef union
1446{
1447 float f;
1448 uint32_t u;
1449} Unsigned2Float;
1450
1451float float16ToFloat(uint16_t f16)
1452{
1453 /* Format specs from Wiki: [15] = sign, [14:10] = exponent, [9:0] = fraction */
1454 uint16_t const f = f16 & 0x3FF;
1455 uint16_t const e = (f16 >> 10) & 0x1F;
1456 uint16_t const s = (f16 >> 15) & 0x1;
1457 Unsigned2Float u2f;
1458
1459 if (e == 0)
1460 {
1461 if (f == 0)
1462 {
1463 /* zero, -0 */
1464 u2f.u = (s << 31) | (0 << 23) | 0;
1465 return u2f.f;
1466 }
1467
1468 /* subnormal numbers: (-1)^signbit * 2^-14 * 0.significantbits */
1469 float const k = 1.0f / 16384.0f; /* 2^-14 */
1470 return (s ? -1.0f : 1.0f) * k * (float)f / 1024.0f;
1471 }
1472
1473 if (e == 31)
1474 {
1475 if (f == 0)
1476 {
1477 /* +-infinity */
1478 u2f.u = (s << 31) | (0xFF << 23) | 0;
1479 return u2f.f;
1480 }
1481
1482 /* NaN */
1483 u2f.u = (s << 31) | (0xFF << 23) | 1;
1484 return u2f.f;
1485 }
1486
1487 /* normalized value: (-1)^signbit * 2^(exponent - 15) * 1.significantbits */
1488 /* Build the float, adjusting for exponent bias (float32 bias is 127, float16 is 15)
1489 * and number of bits in the fraction (float32 has 23, float16 has 10). */
1490 u2f.u = (s << 31) | ((e + 127 - 15) << 23) | (f << (23 - 10));
1491 return u2f.f;
1492}
1493
1494
1495static int vmsvga3dBmpWrite(const char *pszFilename, VMSVGA3D_MAPPED_SURFACE const *pMap)
1496{
1497 if ( pMap->cbBlock != 4 && pMap->cbBlock != 2 && pMap->cbBlock != 1
1498 && pMap->format != SVGA3D_R16G16B16A16_FLOAT
1499 && pMap->format != SVGA3D_R32G32B32A32_FLOAT)
1500 return VERR_NOT_SUPPORTED;
1501
1502 int const w = pMap->cbRow / pMap->cbBlock;
1503 int const h = pMap->cRows;
1504
1505 const int cbBitmap = pMap->cbRow * pMap->cRows * 4;
1506
1507 FILE *f = fopen(pszFilename, "wb");
1508 if (!f)
1509 return VERR_FILE_NOT_FOUND;
1510
1511#ifdef RT_OS_WINDOWS
1512 if (pMap->cbBlock == 4)
1513 {
1514 BMPFILEHDR fileHdr;
1515 RT_ZERO(fileHdr);
1516 fileHdr.uType = BMP_HDR_MAGIC;
1517 fileHdr.cbFileSize = sizeof(fileHdr) + sizeof(BITMAPV4HEADER) + cbBitmap;
1518 fileHdr.offBits = sizeof(fileHdr) + sizeof(BITMAPV4HEADER);
1519
1520 BITMAPV4HEADER hdrV4;
1521 RT_ZERO(hdrV4);
1522 hdrV4.bV4Size = sizeof(hdrV4);
1523 hdrV4.bV4Width = w;
1524 hdrV4.bV4Height = -h;
1525 hdrV4.bV4Planes = 1;
1526 hdrV4.bV4BitCount = 32;
1527 hdrV4.bV4V4Compression = BI_BITFIELDS;
1528 hdrV4.bV4SizeImage = cbBitmap;
1529 hdrV4.bV4XPelsPerMeter = 2835;
1530 hdrV4.bV4YPelsPerMeter = 2835;
1531 // hdrV4.bV4ClrUsed = 0;
1532 // hdrV4.bV4ClrImportant = 0;
1533 hdrV4.bV4RedMask = 0x00ff0000;
1534 hdrV4.bV4GreenMask = 0x0000ff00;
1535 hdrV4.bV4BlueMask = 0x000000ff;
1536 hdrV4.bV4AlphaMask = 0xff000000;
1537 hdrV4.bV4CSType = LCS_WINDOWS_COLOR_SPACE;
1538 // hdrV4.bV4Endpoints = {0};
1539 // hdrV4.bV4GammaRed = 0;
1540 // hdrV4.bV4GammaGreen = 0;
1541 // hdrV4.bV4GammaBlue = 0;
1542
1543 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1544 fwrite(&hdrV4, 1, sizeof(hdrV4), f);
1545 }
1546 else
1547#endif
1548 {
1549 BMPFILEHDR fileHdr;
1550 RT_ZERO(fileHdr);
1551 fileHdr.uType = BMP_HDR_MAGIC;
1552 fileHdr.cbFileSize = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR) + cbBitmap;
1553 fileHdr.offBits = sizeof(BMPFILEHDR) + sizeof(BMPWIN3XINFOHDR);
1554
1555 BMPWIN3XINFOHDR coreHdr;
1556 RT_ZERO(coreHdr);
1557 coreHdr.cbSize = sizeof(coreHdr);
1558 coreHdr.uWidth = w;
1559 coreHdr.uHeight = -h;
1560 coreHdr.cPlanes = 1;
1561 coreHdr.cBits = 32;
1562 coreHdr.cbSizeImage = cbBitmap;
1563
1564 fwrite(&fileHdr, 1, sizeof(fileHdr), f);
1565 fwrite(&coreHdr, 1, sizeof(coreHdr), f);
1566 }
1567
1568 if (pMap->format == SVGA3D_R16G16B16A16_FLOAT)
1569 {
1570 const uint8_t *s = (uint8_t *)pMap->pvData;
1571 for (int32_t y = 0; y < h; ++y)
1572 {
1573 for (int32_t x = 0; x < w; ++x)
1574 {
1575 uint16_t const *pu16Pixel = (uint16_t *)(s + x * 8);
1576 uint8_t r = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[0]));
1577 uint8_t g = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[1]));
1578 uint8_t b = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[2]));
1579 uint8_t a = (uint8_t)(255.0 * float16ToFloat(pu16Pixel[3]));
1580 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1581 fwrite(&u32Pixel, 1, 4, f);
1582 }
1583
1584 s += pMap->cbRowPitch;
1585 }
1586 }
1587 else if (pMap->format == SVGA3D_R32G32B32A32_FLOAT)
1588 {
1589 const uint8_t *s = (uint8_t *)pMap->pvData;
1590 for (int32_t y = 0; y < h; ++y)
1591 {
1592 for (int32_t x = 0; x < w; ++x)
1593 {
1594 float const *pPixel = (float *)(s + x * 8);
1595 uint8_t r = (uint8_t)(255.0 * pPixel[0]);
1596 uint8_t g = (uint8_t)(255.0 * pPixel[1]);
1597 uint8_t b = (uint8_t)(255.0 * pPixel[2]);
1598 uint8_t a = (uint8_t)(255.0 * pPixel[3]);
1599 uint32_t u32Pixel = b + (g << 8) + (r << 16) + (a << 24);
1600 fwrite(&u32Pixel, 1, 4, f);
1601 }
1602
1603 s += pMap->cbRowPitch;
1604 }
1605 }
1606 else if (pMap->cbBlock == 4)
1607 {
1608 const uint8_t *s = (uint8_t *)pMap->pvData;
1609 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1610 {
1611 fwrite(s, 1, pMap->cbRow, f);
1612
1613 s += pMap->cbRowPitch;
1614 }
1615 }
1616 else if (pMap->cbBlock == 2)
1617 {
1618 const uint8_t *s = (uint8_t *)pMap->pvData;
1619 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1620 {
1621 for (int32_t x = 0; x < w; ++x)
1622 {
1623 uint16_t const *pPixel = (uint16_t *)(s + x * sizeof(uint16_t));
1624 uint32_t u32Pixel = *pPixel;
1625 fwrite(&u32Pixel, 1, 4, f);
1626 }
1627
1628 s += pMap->cbRowPitch;
1629 }
1630 }
1631 else if (pMap->cbBlock == 1)
1632 {
1633 const uint8_t *s = (uint8_t *)pMap->pvData;
1634 for (uint32_t iRow = 0; iRow < pMap->cRows; ++iRow)
1635 {
1636 for (int32_t x = 0; x < w; ++x)
1637 {
1638 uint32_t u32Pixel = s[x];
1639 fwrite(&u32Pixel, 1, 4, f);
1640 }
1641
1642 s += pMap->cbRowPitch;
1643 }
1644 }
1645
1646 fclose(f);
1647
1648 return VINF_SUCCESS;
1649}
1650
1651
1652void vmsvga3dMapWriteBmpFile(VMSVGA3D_MAPPED_SURFACE const *pMap, char const *pszPrefix)
1653{
1654 static int idxBitmap = 0;
1655 char *pszFilename = RTStrAPrintf2("bmp\\%s%d.bmp", pszPrefix, idxBitmap++);
1656 int rc = vmsvga3dBmpWrite(pszFilename, pMap);
1657 Log(("WriteBmpFile %s format %d %Rrc\n", pszFilename, pMap->format, rc)); RT_NOREF(rc);
1658 RTStrFree(pszFilename);
1659}
1660
1661
1662static int vmsvgaR3TransferSurfaceLevel(PVGASTATECC pThisCC,
1663 PVMSVGAMOB pMob,
1664 SVGA3dSurfaceImageId const *pImage,
1665 SVGA3dBox const *pBox,
1666 SVGA3dTransferType enmTransfer)
1667{
1668 if (vmsvga3dIsMultisampleSurface(pThisCC, pImage->sid))
1669 {
1670 /* Multisample surfaces can't be accessed. Skip. */
1671 return VINF_SUCCESS;
1672 }
1673
1674 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1675
1676 VMSVGA3D_SURFACE_MAP enmMapType;
1677 if (enmTransfer == SVGA3D_WRITE_HOST_VRAM)
1678 enmMapType = pBox
1679 ? VMSVGA3D_SURFACE_MAP_WRITE
1680 : VMSVGA3D_SURFACE_MAP_WRITE_DISCARD;
1681 else if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1682 enmMapType = VMSVGA3D_SURFACE_MAP_READ;
1683 else
1684 AssertFailedReturn(VERR_INVALID_PARAMETER);
1685
1686 VMSVGA3D_MAPPED_SURFACE map;
1687 int rc = vmsvga3dSurfaceMap(pThisCC, pImage, pBox, enmMapType, &map);
1688 if (RT_SUCCESS(rc))
1689 {
1690 /* Copy mapped surface <-> MOB. */
1691 VMSGA3D_BOX_DIMENSIONS dims;
1692 rc = vmsvga3dGetBoxDimensions(pThisCC, pImage, pBox, &dims);
1693 if (RT_SUCCESS(rc))
1694 {
1695 for (uint32_t z = 0; z < map.box.d; ++z)
1696 {
1697 uint8_t *pu8Map = (uint8_t *)map.pvData + z * map.cbDepthPitch;
1698 uint32_t offMob = dims.offSubresource + dims.offBox + z * dims.cbDepthPitch;
1699
1700 for (uint32_t iRow = 0; iRow < map.cRows; ++iRow)
1701 {
1702 if (enmTransfer == SVGA3D_READ_HOST_VRAM)
1703 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1704 else
1705 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, offMob, pu8Map, dims.cbRow);
1706 AssertRCBreak(rc);
1707
1708 pu8Map += map.cbRowPitch;
1709 offMob += dims.cbPitch;
1710 }
1711 }
1712 }
1713
1714 // vmsvga3dMapWriteBmpFile(&map, "Dynamic");
1715
1716 bool const fWritten = (enmTransfer == SVGA3D_WRITE_HOST_VRAM);
1717 vmsvga3dSurfaceUnmap(pThisCC, pImage, &map, fWritten);
1718 }
1719
1720 return rc;
1721}
1722
1723
1724/* SVGA_3D_CMD_UPDATE_GB_IMAGE 1101 */
1725static void vmsvga3dCmdUpdateGBImage(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBImage const *pCmd)
1726{
1727 //DEBUG_BREAKPOINT_TEST();
1728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1729
1730 LogFlowFunc(("sid=%u @%u,%u,%u %ux%ux%u\n",
1731 pCmd->image.sid, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
1732
1733/*
1734 SVGA3dSurfaceFormat format;
1735 SVGA3dSurface1Flags surface1Flags;
1736 uint32 numMipLevels;
1737 uint32 multisampleCount;
1738 SVGA3dTextureFilter autogenFilter;
1739 SVGA3dSize size;
1740 SVGAMobId mobid;
1741 uint32 arraySize;
1742 uint32 mobPitch;
1743 SVGA3dSurface2Flags surface2Flags;
1744 uint8 multisamplePattern;
1745 uint8 qualityLevel;
1746 uint16 bufferByteStride;
1747 float minLOD;
1748*/
1749
1750 /* "update a surface from its backing MOB." */
1751 SVGAOTableSurfaceEntry entrySurface;
1752 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1753 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1754 if (RT_SUCCESS(rc))
1755 {
1756 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1757 if (pMob)
1758 {
1759 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
1760 AssertRC(rc);
1761 }
1762 }
1763}
1764
1765
1766/* SVGA_3D_CMD_UPDATE_GB_SURFACE 1102 */
1767static void vmsvga3dCmdUpdateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBSurface const *pCmd)
1768{
1769 //DEBUG_BREAKPOINT_TEST();
1770 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1771
1772 LogFlowFunc(("sid=%u\n",
1773 pCmd->sid));
1774
1775 /* "update a surface from its backing MOB." */
1776 SVGAOTableSurfaceEntry entrySurface;
1777 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1778 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1779 if (RT_SUCCESS(rc))
1780 {
1781 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1782 if (pMob)
1783 {
1784 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1785 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1786 {
1787 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1788 {
1789 SVGA3dSurfaceImageId image;
1790 image.sid = pCmd->sid;
1791 image.face = iArray;
1792 image.mipmap = iMipmap;
1793
1794 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_WRITE_HOST_VRAM);
1795 AssertRCBreak(rc);
1796 }
1797 }
1798 }
1799 }
1800}
1801
1802
1803/* SVGA_3D_CMD_READBACK_GB_IMAGE 1103 */
1804static void vmsvga3dCmdReadbackGBImage(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBImage const *pCmd)
1805{
1806 //DEBUG_BREAKPOINT_TEST();
1807 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1808
1809 LogFlowFunc(("sid=%u, face=%u, mipmap=%u\n",
1810 pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap));
1811
1812 /* Read a surface to its backing MOB. */
1813 SVGAOTableSurfaceEntry entrySurface;
1814 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1815 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1816 if (RT_SUCCESS(rc))
1817 {
1818 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1819 if (pMob)
1820 {
1821 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &pCmd->image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1822 AssertRC(rc);
1823 }
1824 }
1825}
1826
1827
1828/* SVGA_3D_CMD_READBACK_GB_SURFACE 1104 */
1829static void vmsvga3dCmdReadbackGBSurface(PVGASTATECC pThisCC, SVGA3dCmdReadbackGBSurface const *pCmd)
1830{
1831 //DEBUG_BREAKPOINT_TEST();
1832 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1833
1834 LogFlowFunc(("sid=%u\n",
1835 pCmd->sid));
1836
1837 /* Read a surface to its backing MOB. */
1838 SVGAOTableSurfaceEntry entrySurface;
1839 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1840 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
1841 if (RT_SUCCESS(rc))
1842 {
1843 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
1844 if (pMob)
1845 {
1846 uint32 const arraySize = vmsvga3dGetArrayElements(pThisCC, pCmd->sid);
1847 for (uint32_t iArray = 0; iArray < arraySize; ++iArray)
1848 {
1849 for (uint32_t iMipmap = 0; iMipmap < entrySurface.numMipLevels; ++iMipmap)
1850 {
1851 SVGA3dSurfaceImageId image;
1852 image.sid = pCmd->sid;
1853 image.face = iArray;
1854 image.mipmap = iMipmap;
1855
1856 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
1857 AssertRCBreak(rc);
1858 }
1859 }
1860 }
1861 }
1862}
1863
1864
1865/* SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105 */
1866static void vmsvga3dCmdInvalidateGBImage(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBImage const *pCmd)
1867{
1868 //DEBUG_BREAKPOINT_TEST();
1869 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->image.sid, pCmd->image.face, pCmd->image.mipmap);
1870}
1871
1872
1873/* SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106 */
1874static void vmsvga3dCmdInvalidateGBSurface(PVGASTATECC pThisCC, SVGA3dCmdInvalidateGBSurface const *pCmd)
1875{
1876 //DEBUG_BREAKPOINT_TEST();
1877 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, SVGA_ID_INVALID, SVGA_ID_INVALID);
1878}
1879
1880
1881/* SVGA_3D_CMD_SET_OTABLE_BASE64 1115 */
1882static void vmsvga3dCmdSetOTableBase64(PVGASTATECC pThisCC, SVGA3dCmdSetOTableBase64 const *pCmd)
1883{
1884 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1885 vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
1886 pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /*fGrow*/ false);
1887}
1888
1889
1890/* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124 */
1891static void vmsvga3dCmdDefineGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDefineGBScreenTarget const *pCmd)
1892{
1893 //DEBUG_BREAKPOINT_TEST();
1894 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1895
1896 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1897 ASSERT_GUEST_RETURN_VOID(pCmd->width > 0 && pCmd->width <= pThis->svga.u32MaxWidth); /* SVGA_REG_SCREENTARGET_MAX_WIDTH */
1898 ASSERT_GUEST_RETURN_VOID(pCmd->height > 0 && pCmd->height <= pThis->svga.u32MaxHeight); /* SVGA_REG_SCREENTARGET_MAX_HEIGHT */
1899 RT_UNTRUSTED_VALIDATED_FENCE();
1900
1901 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1902 SVGAOTableScreenTargetEntry entry;
1903 RT_ZERO(entry);
1904 entry.image.sid = SVGA_ID_INVALID;
1905 // entry.image.face = 0;
1906 // entry.image.mipmap = 0;
1907 entry.width = pCmd->width;
1908 entry.height = pCmd->height;
1909 entry.xRoot = pCmd->xRoot;
1910 entry.yRoot = pCmd->yRoot;
1911 entry.flags = pCmd->flags;
1912 entry.dpi = pCmd->dpi;
1913
1914 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1915 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1916 if (RT_SUCCESS(rc))
1917 {
1918 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1919 /** @todo Generic screen object/target interface. */
1920 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1921 Assert(pScreen->idScreen == pCmd->stid);
1922 pScreen->fDefined = true;
1923 pScreen->fModified = true;
1924 pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET
1925 | (RT_BOOL(pCmd->flags & SVGA_STFLAG_PRIMARY) ? SVGA_SCREEN_IS_PRIMARY : 0);
1926
1927 pScreen->xOrigin = pCmd->xRoot;
1928 pScreen->yOrigin = pCmd->yRoot;
1929 pScreen->cWidth = pCmd->width;
1930 pScreen->cHeight = pCmd->height;
1931 pScreen->offVRAM = 0; /* Not applicable for screen targets, they use either a separate memory buffer or a host window. */
1932 pScreen->cbPitch = pCmd->width * 4;
1933 pScreen->cBpp = 32;
1934
1935 if (RT_LIKELY(pThis->svga.f3DEnabled))
1936 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
1937
1938 if (!pScreen->pHwScreen)
1939 {
1940 /* System memory buffer. */
1941 pScreen->pvScreenBitmap = RTMemAllocZ(pScreen->cHeight * pScreen->cbPitch);
1942 }
1943
1944 pThis->svga.fGFBRegisters = false;
1945 vmsvgaR3ChangeMode(pThis, pThisCC);
1946 }
1947}
1948
1949
1950/* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125 */
1951static void vmsvga3dCmdDestroyGBScreenTarget(PVGASTATE pThis, PVGASTATECC pThisCC, SVGA3dCmdDestroyGBScreenTarget const *pCmd)
1952{
1953 //DEBUG_BREAKPOINT_TEST();
1954 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1955
1956 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1957 RT_UNTRUSTED_VALIDATED_FENCE();
1958
1959 /* Update the entry in the pSvgaR3State->pGboOTableScreenTarget. */
1960 SVGAOTableScreenTargetEntry entry;
1961 RT_ZERO(entry);
1962 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1963 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1964 if (RT_SUCCESS(rc))
1965 {
1966 /* Screen objects and screen targets are similar, therefore we will use the same for both. */
1967 /** @todo Generic screen object/target interface. */
1968 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
1969 vmsvgaR3DestroyScreen(pThis, pThisCC, pScreen);
1970 }
1971}
1972
1973
1974/* SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126 */
1975static void vmsvga3dCmdBindGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdBindGBScreenTarget const *pCmd)
1976{
1977 //DEBUG_BREAKPOINT_TEST();
1978 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
1979
1980 /* "Binding a surface to a Screen Target the same as flipping" */
1981
1982 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
1983 ASSERT_GUEST_RETURN_VOID(pCmd->image.face == 0 && pCmd->image.mipmap == 0);
1984 RT_UNTRUSTED_VALIDATED_FENCE();
1985
1986 /* Assign the surface to the screen target. */
1987 int rc = VINF_SUCCESS;
1988 if (pCmd->image.sid != SVGA_ID_INVALID)
1989 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
1990 pCmd->image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE);
1991 if (RT_SUCCESS(rc))
1992 {
1993 SVGAOTableScreenTargetEntry entry;
1994 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
1995 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
1996 if (RT_SUCCESS(rc))
1997 {
1998 entry.image = pCmd->image;
1999 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
2000 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entry, sizeof(entry));
2001 if (RT_SUCCESS(rc))
2002 {
2003 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
2004 rc = pSvgaR3State->pFuncsGBO->pfnScreenTargetBind(pThisCC, pScreen, pCmd->image.sid);
2005 AssertRC(rc);
2006 }
2007 }
2008 }
2009}
2010
2011
2012/* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127 */
2013static void vmsvga3dCmdUpdateGBScreenTarget(PVGASTATECC pThisCC, SVGA3dCmdUpdateGBScreenTarget const *pCmd)
2014{
2015 //DEBUG_BREAKPOINT_TEST();
2016 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2017
2018 /* Update the screen target from its backing surface. */
2019 ASSERT_GUEST_RETURN_VOID(pCmd->stid < RT_ELEMENTS(pSvgaR3State->aScreens));
2020 RT_UNTRUSTED_VALIDATED_FENCE();
2021
2022 /* Get the screen target info. */
2023 SVGAOTableScreenTargetEntry entryScreenTarget;
2024 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SCREENTARGET],
2025 pCmd->stid, SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE, &entryScreenTarget, sizeof(entryScreenTarget));
2026 if (RT_SUCCESS(rc))
2027 {
2028 ASSERT_GUEST_RETURN_VOID(entryScreenTarget.image.face == 0 && entryScreenTarget.image.mipmap == 0);
2029 RT_UNTRUSTED_VALIDATED_FENCE();
2030
2031 if (entryScreenTarget.image.sid != SVGA_ID_INVALID)
2032 {
2033 SVGAOTableSurfaceEntry entrySurface;
2034 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2035 entryScreenTarget.image.sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2036 if (RT_SUCCESS(rc))
2037 {
2038 /* Copy entrySurface.mobid content to the screen target. */
2039 if (entrySurface.mobid != SVGA_ID_INVALID)
2040 {
2041 RT_UNTRUSTED_VALIDATED_FENCE();
2042 SVGA3dRect targetRect = pCmd->rect;
2043
2044 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[pCmd->stid];
2045 if (pScreen->pHwScreen)
2046 {
2047 /* Copy the screen target surface to the backend's screen. */
2048 pSvgaR3State->pFuncsGBO->pfnScreenTargetUpdate(pThisCC, pScreen, &targetRect);
2049 }
2050 else
2051 {
2052 SVGASignedRect r;
2053 r.left = pCmd->rect.x;
2054 r.top = pCmd->rect.y;
2055 r.right = pCmd->rect.x + pCmd->rect.w;
2056 r.bottom = pCmd->rect.y + pCmd->rect.h;
2057 vmsvga3dScreenUpdate(pThisCC, pCmd->stid, r, entryScreenTarget.image, r, 0, NULL);
2058 }
2059 }
2060 }
2061 }
2062 }
2063}
2064
2065
2066/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134 */
2067static void vmsvga3dCmdDefineGBSurface_v2(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v2 const *pCmd)
2068{
2069 //DEBUG_BREAKPOINT_TEST();
2070 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2071
2072 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
2073 SVGAOTableSurfaceEntry entry;
2074 RT_ZERO(entry);
2075 entry.format = pCmd->format;
2076 entry.surface1Flags = pCmd->surfaceFlags;
2077 entry.numMipLevels = pCmd->numMipLevels;
2078 entry.multisampleCount = pCmd->multisampleCount;
2079 entry.autogenFilter = pCmd->autogenFilter;
2080 entry.size = pCmd->size;
2081 entry.mobid = SVGA_ID_INVALID;
2082 entry.arraySize = pCmd->arraySize;
2083 // entry.mobPitch = 0;
2084 // entry.surface2Flags = 0;
2085 // entry.multisamplePattern = 0;
2086 // entry.qualityLevel = 0;
2087 // entry.bufferByteStride = 0;
2088 // entry.minLOD = 0;
2089
2090 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2091 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
2092 if (RT_SUCCESS(rc))
2093 {
2094 /* Create the host surface. */
2095 SVGA3dMSPattern const multisamplePattern = pCmd->multisampleCount > 1 ? SVGA3D_MS_PATTERN_STANDARD : SVGA3D_MS_PATTERN_NONE;
2096 SVGA3dMSQualityLevel const qualityLevel = pCmd->multisampleCount > 1 ? SVGA3D_MS_QUALITY_FULL : SVGA3D_MS_QUALITY_NONE;
2097 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
2098 pCmd->multisampleCount, multisamplePattern, qualityLevel, pCmd->autogenFilter,
2099 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* bufferByteStride = */ 0, /* fAllocMipLevels = */ false);
2100 }
2101}
2102
2103
2104/* SVGA_3D_CMD_DEFINE_GB_MOB64 1135 */
2105static void vmsvga3dCmdDefineGBMob64(PVGASTATECC pThisCC, SVGA3dCmdDefineGBMob64 const *pCmd)
2106{
2107 //DEBUG_BREAKPOINT_TEST();
2108 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2109
2110 ASSERT_GUEST_RETURN_VOID(pCmd->mobid != SVGA_ID_INVALID); /* The guest should not use this id. */
2111
2112 /* Maybe just update the OTable and create Gbo when the MOB is actually accessed? */
2113 /* Allocate a structure for the MOB. */
2114 PVMSVGAMOB pMob = (PVMSVGAMOB)RTMemAllocZ(sizeof(*pMob));
2115 AssertPtrReturnVoid(pMob);
2116
2117 int rc = vmsvgaR3MobCreate(pSvgaR3State, pCmd->ptDepth, pCmd->base, pCmd->sizeInBytes, pCmd->mobid, pMob);
2118 if (RT_SUCCESS(rc))
2119 {
2120 return;
2121 }
2122
2123 RTMemFree(pMob);
2124}
2125
2126
2127/* SVGA_3D_CMD_DX_DEFINE_CONTEXT 1143 */
2128static int vmsvga3dCmdDXDefineContext(PVGASTATECC pThisCC, SVGA3dCmdDXDefineContext const *pCmd, uint32_t cbCmd)
2129{
2130#ifdef VMSVGA3D_DX
2131 //DEBUG_BREAKPOINT_TEST();
2132 RT_NOREF(cbCmd);
2133
2134 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2135
2136 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2137 SVGAOTableDXContextEntry entry;
2138 RT_ZERO(entry);
2139 entry.cid = pCmd->cid;
2140 entry.mobid = SVGA_ID_INVALID;
2141 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2142 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2143 if (RT_SUCCESS(rc))
2144 {
2145 /* Create the host context. */
2146 rc = vmsvga3dDXDefineContext(pThisCC, pCmd->cid);
2147 }
2148
2149 return rc;
2150#else
2151 RT_NOREF(pThisCC, pCmd, cbCmd);
2152 return VERR_NOT_SUPPORTED;
2153#endif
2154}
2155
2156
2157/* SVGA_3D_CMD_DX_DESTROY_CONTEXT 1144 */
2158static int vmsvga3dCmdDXDestroyContext(PVGASTATECC pThisCC, SVGA3dCmdDXDestroyContext const *pCmd, uint32_t cbCmd)
2159{
2160#ifdef VMSVGA3D_DX
2161 //DEBUG_BREAKPOINT_TEST();
2162 RT_NOREF(cbCmd);
2163
2164 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2165
2166 /* Update the entry in the pSvgaR3State->pGboOTable[SVGA_OTABLE_DXCONTEXT]. */
2167 SVGAOTableDXContextEntry entry;
2168 RT_ZERO(entry);
2169 vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2170 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2171
2172 return vmsvga3dDXDestroyContext(pThisCC, pCmd->cid);
2173#else
2174 RT_NOREF(pThisCC, pCmd, cbCmd);
2175 return VERR_NOT_SUPPORTED;
2176#endif
2177}
2178
2179
2180/* SVGA_3D_CMD_DX_BIND_CONTEXT 1145 */
2181static int vmsvga3dCmdDXBindContext(PVGASTATECC pThisCC, SVGA3dCmdDXBindContext const *pCmd, uint32_t cbCmd)
2182{
2183#ifdef VMSVGA3D_DX
2184 //DEBUG_BREAKPOINT_TEST();
2185 RT_NOREF(cbCmd);
2186
2187 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2188
2189 /* Assign a mobid to a cid. */
2190 int rc = VINF_SUCCESS;
2191 if (pCmd->mobid != SVGA_ID_INVALID)
2192 rc = vmsvgaR3OTableVerifyIndex(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_MOB],
2193 pCmd->mobid, SVGA3D_OTABLE_MOB_ENTRY_SIZE);
2194 if (RT_SUCCESS(rc))
2195 {
2196 SVGAOTableDXContextEntry entry;
2197 rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2198 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2199 if (RT_SUCCESS(rc))
2200 {
2201 SVGADXContextMobFormat *pSvgaDXContext = NULL;
2202 if (pCmd->mobid != entry.mobid && entry.mobid != SVGA_ID_INVALID)
2203 {
2204 /* Unbind notification to the DX backend. Copy the context data to the guest backing memory. */
2205 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2206 if (pSvgaDXContext)
2207 {
2208 rc = vmsvga3dDXUnbindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2209 if (RT_SUCCESS(rc))
2210 {
2211 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2212 if (pMob)
2213 {
2214 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2215 }
2216 }
2217
2218 RTMemFree(pSvgaDXContext);
2219 pSvgaDXContext = NULL;
2220 }
2221 }
2222
2223 if (pCmd->mobid != SVGA_ID_INVALID)
2224 {
2225 /* Bind a new context. Copy existing data from the guest backing memory. */
2226 if (pCmd->validContents)
2227 {
2228 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2229 if (pMob)
2230 {
2231 pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2232 if (pSvgaDXContext)
2233 {
2234 rc = vmsvgaR3GboRead(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2235 if (RT_FAILURE(rc))
2236 {
2237 RTMemFree(pSvgaDXContext);
2238 pSvgaDXContext = NULL;
2239 }
2240 }
2241 }
2242 }
2243
2244 rc = vmsvga3dDXBindContext(pThisCC, pCmd->cid, pSvgaDXContext);
2245
2246 RTMemFree(pSvgaDXContext);
2247 }
2248
2249 /* Update the object table. */
2250 entry.mobid = pCmd->mobid;
2251 rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2252 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2253 }
2254 }
2255
2256 return rc;
2257#else
2258 RT_NOREF(pThisCC, pCmd, cbCmd);
2259 return VERR_NOT_SUPPORTED;
2260#endif
2261}
2262
2263
2264/* SVGA_3D_CMD_DX_READBACK_CONTEXT 1146 */
2265static int vmsvga3dCmdDXReadbackContext(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackContext const *pCmd, uint32_t cbCmd)
2266{
2267#ifdef VMSVGA3D_DX
2268 //DEBUG_BREAKPOINT_TEST();
2269 RT_NOREF(cbCmd);
2270
2271 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2272
2273 /* "Request that the device flush the contents back into guest memory." */
2274 SVGAOTableDXContextEntry entry;
2275 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_DXCONTEXT],
2276 pCmd->cid, sizeof(SVGAOTableDXContextEntry), &entry, sizeof(entry));
2277 if (RT_SUCCESS(rc))
2278 {
2279 if (entry.mobid != SVGA_ID_INVALID)
2280 {
2281 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entry.mobid);
2282 if (pMob)
2283 {
2284 /* Get the content. */
2285 SVGADXContextMobFormat *pSvgaDXContext = (SVGADXContextMobFormat *)RTMemAlloc(sizeof(SVGADXContextMobFormat));
2286 if (pSvgaDXContext)
2287 {
2288 rc = vmsvga3dDXReadbackContext(pThisCC, pCmd->cid, pSvgaDXContext);
2289 if (RT_SUCCESS(rc))
2290 rc = vmsvgaR3GboWrite(pSvgaR3State, &pMob->Gbo, 0, pSvgaDXContext, sizeof(SVGADXContextMobFormat));
2291
2292 RTMemFree(pSvgaDXContext);
2293 }
2294 else
2295 rc = VERR_NO_MEMORY;
2296 }
2297 }
2298 }
2299
2300 return rc;
2301#else
2302 RT_NOREF(pThisCC, pCmd, cbCmd);
2303 return VERR_NOT_SUPPORTED;
2304#endif
2305}
2306
2307
2308/* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT 1147 */
2309static int vmsvga3dCmdDXInvalidateContext(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXInvalidateContext const *pCmd, uint32_t cbCmd)
2310{
2311#ifdef VMSVGA3D_DX
2312 DEBUG_BREAKPOINT_TEST();
2313 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2314 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
2315 return vmsvga3dDXInvalidateContext(pThisCC, idDXContext);
2316#else
2317 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2318 return VERR_NOT_SUPPORTED;
2319#endif
2320}
2321
2322
2323/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER 1148 */
2324static int vmsvga3dCmdDXSetSingleConstantBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSingleConstantBuffer const *pCmd, uint32_t cbCmd)
2325{
2326#ifdef VMSVGA3D_DX
2327 //DEBUG_BREAKPOINT_TEST();
2328 RT_NOREF(cbCmd);
2329 return vmsvga3dDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd);
2330#else
2331 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2332 return VERR_NOT_SUPPORTED;
2333#endif
2334}
2335
2336
2337/* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES 1149 */
2338static int vmsvga3dCmdDXSetShaderResources(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderResources const *pCmd, uint32_t cbCmd)
2339{
2340#ifdef VMSVGA3D_DX
2341 //DEBUG_BREAKPOINT_TEST();
2342 SVGA3dShaderResourceViewId const *paShaderResourceViewId = (SVGA3dShaderResourceViewId *)&pCmd[1];
2343 uint32_t const cShaderResourceViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dShaderResourceViewId);
2344 return vmsvga3dDXSetShaderResources(pThisCC, idDXContext, pCmd, cShaderResourceViewId, paShaderResourceViewId);
2345#else
2346 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2347 return VERR_NOT_SUPPORTED;
2348#endif
2349}
2350
2351
2352/* SVGA_3D_CMD_DX_SET_SHADER 1150 */
2353static int vmsvga3dCmdDXSetShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShader const *pCmd, uint32_t cbCmd)
2354{
2355#ifdef VMSVGA3D_DX
2356 //DEBUG_BREAKPOINT_TEST();
2357 RT_NOREF(cbCmd);
2358 return vmsvga3dDXSetShader(pThisCC, idDXContext, pCmd);
2359#else
2360 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2361 return VERR_NOT_SUPPORTED;
2362#endif
2363}
2364
2365
2366/* SVGA_3D_CMD_DX_SET_SAMPLERS 1151 */
2367static int vmsvga3dCmdDXSetSamplers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSamplers const *pCmd, uint32_t cbCmd)
2368{
2369#ifdef VMSVGA3D_DX
2370 //DEBUG_BREAKPOINT_TEST();
2371 SVGA3dSamplerId const *paSamplerId = (SVGA3dSamplerId *)&pCmd[1];
2372 uint32_t const cSamplerId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSamplerId);
2373 return vmsvga3dDXSetSamplers(pThisCC, idDXContext, pCmd, cSamplerId, paSamplerId);
2374#else
2375 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2376 return VERR_NOT_SUPPORTED;
2377#endif
2378}
2379
2380
2381/* SVGA_3D_CMD_DX_DRAW 1152 */
2382static int vmsvga3dCmdDXDraw(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDraw const *pCmd, uint32_t cbCmd)
2383{
2384#ifdef VMSVGA3D_DX
2385 //DEBUG_BREAKPOINT_TEST();
2386 RT_NOREF(cbCmd);
2387 return vmsvga3dDXDraw(pThisCC, idDXContext, pCmd);
2388#else
2389 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2390 return VERR_NOT_SUPPORTED;
2391#endif
2392}
2393
2394
2395/* SVGA_3D_CMD_DX_DRAW_INDEXED 1153 */
2396static int vmsvga3dCmdDXDrawIndexed(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexed const *pCmd, uint32_t cbCmd)
2397{
2398#ifdef VMSVGA3D_DX
2399 //DEBUG_BREAKPOINT_TEST();
2400 RT_NOREF(cbCmd);
2401 return vmsvga3dDXDrawIndexed(pThisCC, idDXContext, pCmd);
2402#else
2403 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2404 return VERR_NOT_SUPPORTED;
2405#endif
2406}
2407
2408
2409/* SVGA_3D_CMD_DX_DRAW_INSTANCED 1154 */
2410static int vmsvga3dCmdDXDrawInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstanced const *pCmd, uint32_t cbCmd)
2411{
2412#ifdef VMSVGA3D_DX
2413 //DEBUG_BREAKPOINT_TEST();
2414 RT_NOREF(cbCmd);
2415 return vmsvga3dDXDrawInstanced(pThisCC, idDXContext, pCmd);
2416#else
2417 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2418 return VERR_NOT_SUPPORTED;
2419#endif
2420}
2421
2422
2423/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED 1155 */
2424static int vmsvga3dCmdDXDrawIndexedInstanced(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstanced const *pCmd, uint32_t cbCmd)
2425{
2426#ifdef VMSVGA3D_DX
2427 //DEBUG_BREAKPOINT_TEST();
2428 RT_NOREF(cbCmd);
2429 return vmsvga3dDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd);
2430#else
2431 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2432 return VERR_NOT_SUPPORTED;
2433#endif
2434}
2435
2436
2437/* SVGA_3D_CMD_DX_DRAW_AUTO 1156 */
2438static int vmsvga3dCmdDXDrawAuto(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawAuto const *pCmd, uint32_t cbCmd)
2439{
2440#ifdef VMSVGA3D_DX
2441 //DEBUG_BREAKPOINT_TEST();
2442 RT_NOREF(pCmd, cbCmd);
2443 return vmsvga3dDXDrawAuto(pThisCC, idDXContext);
2444#else
2445 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2446 return VERR_NOT_SUPPORTED;
2447#endif
2448}
2449
2450
2451/* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT 1157 */
2452static int vmsvga3dCmdDXSetInputLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetInputLayout const *pCmd, uint32_t cbCmd)
2453{
2454#ifdef VMSVGA3D_DX
2455 //DEBUG_BREAKPOINT_TEST();
2456 RT_NOREF(cbCmd);
2457 return vmsvga3dDXSetInputLayout(pThisCC, idDXContext, pCmd->elementLayoutId);
2458#else
2459 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2460 return VERR_NOT_SUPPORTED;
2461#endif
2462}
2463
2464
2465/* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS 1158 */
2466static int vmsvga3dCmdDXSetVertexBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVertexBuffers const *pCmd, uint32_t cbCmd)
2467{
2468#ifdef VMSVGA3D_DX
2469 //DEBUG_BREAKPOINT_TEST();
2470 SVGA3dVertexBuffer const *paVertexBuffer = (SVGA3dVertexBuffer *)&pCmd[1];
2471 uint32_t const cVertexBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dVertexBuffer);
2472 return vmsvga3dDXSetVertexBuffers(pThisCC, idDXContext, pCmd->startBuffer, cVertexBuffer, paVertexBuffer);
2473#else
2474 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2475 return VERR_NOT_SUPPORTED;
2476#endif
2477}
2478
2479
2480/* SVGA_3D_CMD_DX_SET_INDEX_BUFFER 1159 */
2481static int vmsvga3dCmdDXSetIndexBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetIndexBuffer const *pCmd, uint32_t cbCmd)
2482{
2483#ifdef VMSVGA3D_DX
2484 //DEBUG_BREAKPOINT_TEST();
2485 RT_NOREF(cbCmd);
2486 return vmsvga3dDXSetIndexBuffer(pThisCC, idDXContext, pCmd);
2487#else
2488 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2489 return VERR_NOT_SUPPORTED;
2490#endif
2491}
2492
2493
2494/* SVGA_3D_CMD_DX_SET_TOPOLOGY 1160 */
2495static int vmsvga3dCmdDXSetTopology(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetTopology const *pCmd, uint32_t cbCmd)
2496{
2497#ifdef VMSVGA3D_DX
2498 //DEBUG_BREAKPOINT_TEST();
2499 RT_NOREF(cbCmd);
2500 return vmsvga3dDXSetTopology(pThisCC, idDXContext, pCmd->topology);
2501#else
2502 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2503 return VERR_NOT_SUPPORTED;
2504#endif
2505}
2506
2507
2508/* SVGA_3D_CMD_DX_SET_RENDERTARGETS 1161 */
2509static int vmsvga3dCmdDXSetRenderTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRenderTargets const *pCmd, uint32_t cbCmd)
2510{
2511#ifdef VMSVGA3D_DX
2512 //DEBUG_BREAKPOINT_TEST();
2513 SVGA3dRenderTargetViewId const *paRenderTargetViewId = (SVGA3dRenderTargetViewId *)&pCmd[1];
2514 uint32_t const cRenderTargetViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderTargetViewId);
2515 return vmsvga3dDXSetRenderTargets(pThisCC, idDXContext, pCmd->depthStencilViewId, cRenderTargetViewId, paRenderTargetViewId);
2516#else
2517 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2518 return VERR_NOT_SUPPORTED;
2519#endif
2520}
2521
2522
2523/* SVGA_3D_CMD_DX_SET_BLEND_STATE 1162 */
2524static int vmsvga3dCmdDXSetBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetBlendState const *pCmd, uint32_t cbCmd)
2525{
2526#ifdef VMSVGA3D_DX
2527 //DEBUG_BREAKPOINT_TEST();
2528 RT_NOREF(cbCmd);
2529 return vmsvga3dDXSetBlendState(pThisCC, idDXContext, pCmd);
2530#else
2531 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2532 return VERR_NOT_SUPPORTED;
2533#endif
2534}
2535
2536
2537/* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE 1163 */
2538static int vmsvga3dCmdDXSetDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDepthStencilState const *pCmd, uint32_t cbCmd)
2539{
2540#ifdef VMSVGA3D_DX
2541 //DEBUG_BREAKPOINT_TEST();
2542 RT_NOREF(cbCmd);
2543 return vmsvga3dDXSetDepthStencilState(pThisCC, idDXContext, pCmd);
2544#else
2545 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2546 return VERR_NOT_SUPPORTED;
2547#endif
2548}
2549
2550
2551/* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE 1164 */
2552static int vmsvga3dCmdDXSetRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetRasterizerState const *pCmd, uint32_t cbCmd)
2553{
2554#ifdef VMSVGA3D_DX
2555 //DEBUG_BREAKPOINT_TEST();
2556 RT_NOREF(cbCmd);
2557 return vmsvga3dDXSetRasterizerState(pThisCC, idDXContext, pCmd->rasterizerId);
2558#else
2559 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2560 return VERR_NOT_SUPPORTED;
2561#endif
2562}
2563
2564
2565/* SVGA_3D_CMD_DX_DEFINE_QUERY 1165 */
2566static int vmsvga3dCmdDXDefineQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineQuery const *pCmd, uint32_t cbCmd)
2567{
2568#ifdef VMSVGA3D_DX
2569 //DEBUG_BREAKPOINT_TEST();
2570 RT_NOREF(cbCmd);
2571 return vmsvga3dDXDefineQuery(pThisCC, idDXContext, pCmd);
2572#else
2573 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2574 return VERR_NOT_SUPPORTED;
2575#endif
2576}
2577
2578
2579/* SVGA_3D_CMD_DX_DESTROY_QUERY 1166 */
2580static int vmsvga3dCmdDXDestroyQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyQuery const *pCmd, uint32_t cbCmd)
2581{
2582#ifdef VMSVGA3D_DX
2583 //DEBUG_BREAKPOINT_TEST();
2584 RT_NOREF(cbCmd);
2585 return vmsvga3dDXDestroyQuery(pThisCC, idDXContext, pCmd);
2586#else
2587 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2588 return VERR_NOT_SUPPORTED;
2589#endif
2590}
2591
2592
2593/* SVGA_3D_CMD_DX_BIND_QUERY 1167 */
2594static int vmsvga3dCmdDXBindQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindQuery const *pCmd, uint32_t cbCmd)
2595{
2596#ifdef VMSVGA3D_DX
2597 //DEBUG_BREAKPOINT_TEST();
2598 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2599 RT_NOREF(cbCmd);
2600 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
2601 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
2602 return vmsvga3dDXBindQuery(pThisCC, idDXContext, pCmd, pMob);
2603#else
2604 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2605 return VERR_NOT_SUPPORTED;
2606#endif
2607}
2608
2609
2610/* SVGA_3D_CMD_DX_SET_QUERY_OFFSET 1168 */
2611static int vmsvga3dCmdDXSetQueryOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetQueryOffset const *pCmd, uint32_t cbCmd)
2612{
2613#ifdef VMSVGA3D_DX
2614 //DEBUG_BREAKPOINT_TEST();
2615 RT_NOREF(cbCmd);
2616 return vmsvga3dDXSetQueryOffset(pThisCC, idDXContext, pCmd);
2617#else
2618 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2619 return VERR_NOT_SUPPORTED;
2620#endif
2621}
2622
2623
2624/* SVGA_3D_CMD_DX_BEGIN_QUERY 1169 */
2625static int vmsvga3dCmdDXBeginQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBeginQuery const *pCmd, uint32_t cbCmd)
2626{
2627#ifdef VMSVGA3D_DX
2628 //DEBUG_BREAKPOINT_TEST();
2629 RT_NOREF(cbCmd);
2630 return vmsvga3dDXBeginQuery(pThisCC, idDXContext, pCmd);
2631#else
2632 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2633 return VERR_NOT_SUPPORTED;
2634#endif
2635}
2636
2637
2638/* SVGA_3D_CMD_DX_END_QUERY 1170 */
2639static int vmsvga3dCmdDXEndQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXEndQuery const *pCmd, uint32_t cbCmd)
2640{
2641#ifdef VMSVGA3D_DX
2642 //DEBUG_BREAKPOINT_TEST();
2643 RT_NOREF(cbCmd);
2644 return vmsvga3dDXEndQuery(pThisCC, idDXContext, pCmd);
2645#else
2646 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2647 return VERR_NOT_SUPPORTED;
2648#endif
2649}
2650
2651
2652/* SVGA_3D_CMD_DX_READBACK_QUERY 1171 */
2653static int vmsvga3dCmdDXReadbackQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackQuery const *pCmd, uint32_t cbCmd)
2654{
2655#ifdef VMSVGA3D_DX
2656 //DEBUG_BREAKPOINT_TEST();
2657 RT_NOREF(cbCmd);
2658 return vmsvga3dDXReadbackQuery(pThisCC, idDXContext, pCmd);
2659#else
2660 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2661 return VERR_NOT_SUPPORTED;
2662#endif
2663}
2664
2665
2666/* SVGA_3D_CMD_DX_SET_PREDICATION 1172 */
2667static int vmsvga3dCmdDXSetPredication(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPredication const *pCmd, uint32_t cbCmd)
2668{
2669#ifdef VMSVGA3D_DX
2670 //DEBUG_BREAKPOINT_TEST();
2671 RT_NOREF(cbCmd);
2672 return vmsvga3dDXSetPredication(pThisCC, idDXContext, pCmd);
2673#else
2674 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2675 return VERR_NOT_SUPPORTED;
2676#endif
2677}
2678
2679
2680/* SVGA_3D_CMD_DX_SET_SOTARGETS 1173 */
2681static int vmsvga3dCmdDXSetSOTargets(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetSOTargets const *pCmd, uint32_t cbCmd)
2682{
2683#ifdef VMSVGA3D_DX
2684 //DEBUG_BREAKPOINT_TEST();
2685 SVGA3dSoTarget const *paSoTarget = (SVGA3dSoTarget *)&pCmd[1];
2686 uint32_t const cSoTarget = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSoTarget);
2687 return vmsvga3dDXSetSOTargets(pThisCC, idDXContext, cSoTarget, paSoTarget);
2688#else
2689 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2690 return VERR_NOT_SUPPORTED;
2691#endif
2692}
2693
2694
2695/* SVGA_3D_CMD_DX_SET_VIEWPORTS 1174 */
2696static int vmsvga3dCmdDXSetViewports(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetViewports const *pCmd, uint32_t cbCmd)
2697{
2698#ifdef VMSVGA3D_DX
2699 //DEBUG_BREAKPOINT_TEST();
2700 SVGA3dViewport const *paViewport = (SVGA3dViewport *)&pCmd[1];
2701 uint32_t const cViewport = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dViewport);
2702 return vmsvga3dDXSetViewports(pThisCC, idDXContext, cViewport, paViewport);
2703#else
2704 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2705 return VERR_NOT_SUPPORTED;
2706#endif
2707}
2708
2709
2710/* SVGA_3D_CMD_DX_SET_SCISSORRECTS 1175 */
2711static int vmsvga3dCmdDXSetScissorRects(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetScissorRects const *pCmd, uint32_t cbCmd)
2712{
2713#ifdef VMSVGA3D_DX
2714 //DEBUG_BREAKPOINT_TEST();
2715 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
2716 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
2717 return vmsvga3dDXSetScissorRects(pThisCC, idDXContext, cRect, paRect);
2718#else
2719 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2720 return VERR_NOT_SUPPORTED;
2721#endif
2722}
2723
2724
2725/* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW 1176 */
2726static int vmsvga3dCmdDXClearRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearRenderTargetView const *pCmd, uint32_t cbCmd)
2727{
2728#ifdef VMSVGA3D_DX
2729 //DEBUG_BREAKPOINT_TEST();
2730 RT_NOREF(cbCmd);
2731 return vmsvga3dDXClearRenderTargetView(pThisCC, idDXContext, pCmd);
2732#else
2733 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2734 return VERR_NOT_SUPPORTED;
2735#endif
2736}
2737
2738
2739/* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW 1177 */
2740static int vmsvga3dCmdDXClearDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearDepthStencilView const *pCmd, uint32_t cbCmd)
2741{
2742#ifdef VMSVGA3D_DX
2743 //DEBUG_BREAKPOINT_TEST();
2744 RT_NOREF(cbCmd);
2745 return vmsvga3dDXClearDepthStencilView(pThisCC, idDXContext, pCmd);
2746#else
2747 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2748 return VERR_NOT_SUPPORTED;
2749#endif
2750}
2751
2752
2753/* SVGA_3D_CMD_DX_PRED_COPY_REGION 1178 */
2754static int vmsvga3dCmdDXPredCopyRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopyRegion const *pCmd, uint32_t cbCmd)
2755{
2756#ifdef VMSVGA3D_DX
2757 //DEBUG_BREAKPOINT_TEST();
2758 RT_NOREF(cbCmd);
2759 return vmsvga3dDXPredCopyRegion(pThisCC, idDXContext, pCmd);
2760#else
2761 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2762 return VERR_NOT_SUPPORTED;
2763#endif
2764}
2765
2766
2767/* SVGA_3D_CMD_DX_PRED_COPY 1179 */
2768static int vmsvga3dCmdDXPredCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredCopy const *pCmd, uint32_t cbCmd)
2769{
2770#ifdef VMSVGA3D_DX
2771 //DEBUG_BREAKPOINT_TEST();
2772 RT_NOREF(cbCmd);
2773 return vmsvga3dDXPredCopy(pThisCC, idDXContext, pCmd);
2774#else
2775 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2776 return VERR_NOT_SUPPORTED;
2777#endif
2778}
2779
2780
2781/* SVGA_3D_CMD_DX_PRESENTBLT 1180 */
2782static int vmsvga3dCmdDXPresentBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPresentBlt const *pCmd, uint32_t cbCmd)
2783{
2784#ifdef VMSVGA3D_DX
2785 //DEBUG_BREAKPOINT_TEST();
2786 RT_NOREF(cbCmd);
2787 return vmsvga3dDXPresentBlt(pThisCC, idDXContext, pCmd);
2788#else
2789 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2790 return VERR_NOT_SUPPORTED;
2791#endif
2792}
2793
2794
2795/* SVGA_3D_CMD_DX_GENMIPS 1181 */
2796static int vmsvga3dCmdDXGenMips(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXGenMips const *pCmd, uint32_t cbCmd)
2797{
2798#ifdef VMSVGA3D_DX
2799 //DEBUG_BREAKPOINT_TEST();
2800 RT_NOREF(cbCmd);
2801 return vmsvga3dDXGenMips(pThisCC, idDXContext, pCmd);
2802#else
2803 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2804 return VERR_NOT_SUPPORTED;
2805#endif
2806}
2807
2808
2809/* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE 1182 */
2810static int vmsvga3dCmdDXUpdateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXUpdateSubResource const *pCmd, uint32_t cbCmd)
2811{
2812#ifdef VMSVGA3D_DX
2813 //DEBUG_BREAKPOINT_TEST();
2814 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2815 RT_NOREF(cbCmd);
2816
2817 LogFlowFunc(("sid=%u, subResource=%u, box=%d,%d,%d %ux%ux%u\n",
2818 pCmd->sid, pCmd->subResource, pCmd->box.x, pCmd->box.y, pCmd->box.z, pCmd->box.w, pCmd->box.h, pCmd->box.d));
2819
2820 /* "Inform the device that the guest-contents have been updated." */
2821 SVGAOTableSurfaceEntry entrySurface;
2822 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2823 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2824 if (RT_SUCCESS(rc))
2825 {
2826 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2827 if (pMob)
2828 {
2829 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2830 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2831 /* pCmd->box will be verified by the mapping function. */
2832 RT_UNTRUSTED_VALIDATED_FENCE();
2833
2834 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2835 SVGA3dSurfaceImageId image;
2836 image.sid = pCmd->sid;
2837 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2838
2839 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, &pCmd->box, SVGA3D_WRITE_HOST_VRAM);
2840 AssertRC(rc);
2841 }
2842 }
2843
2844 return rc;
2845#else
2846 RT_NOREF(pThisCC, pCmd, cbCmd);
2847 return VERR_NOT_SUPPORTED;
2848#endif
2849}
2850
2851
2852/* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE 1183 */
2853static int vmsvga3dCmdDXReadbackSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXReadbackSubResource const *pCmd, uint32_t cbCmd)
2854{
2855#ifdef VMSVGA3D_DX
2856 //DEBUG_BREAKPOINT_TEST();
2857 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2858 RT_NOREF(cbCmd);
2859
2860 LogFlowFunc(("sid=%u, subResource=%u\n",
2861 pCmd->sid, pCmd->subResource));
2862
2863 /* "Request the device to flush the dirty contents into the guest." */
2864 SVGAOTableSurfaceEntry entrySurface;
2865 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2866 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2867 if (RT_SUCCESS(rc))
2868 {
2869 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, entrySurface.mobid);
2870 if (pMob)
2871 {
2872 uint32 const cSubresource = vmsvga3dGetSubresourceCount(pThisCC, pCmd->sid);
2873 ASSERT_GUEST_RETURN(pCmd->subResource < cSubresource, VERR_INVALID_PARAMETER);
2874 RT_UNTRUSTED_VALIDATED_FENCE();
2875
2876 /** @todo Mapping functions should use subresource index rather than SVGA3dSurfaceImageId? */
2877 SVGA3dSurfaceImageId image;
2878 image.sid = pCmd->sid;
2879 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &image.mipmap, &image.face);
2880
2881 rc = vmsvgaR3TransferSurfaceLevel(pThisCC, pMob, &image, /* all pBox = */ NULL, SVGA3D_READ_HOST_VRAM);
2882 AssertRC(rc);
2883 }
2884 }
2885
2886 return rc;
2887#else
2888 RT_NOREF(pThisCC, pCmd, cbCmd);
2889 return VERR_NOT_SUPPORTED;
2890#endif
2891}
2892
2893
2894/* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE 1184 */
2895static int vmsvga3dCmdDXInvalidateSubResource(PVGASTATECC pThisCC, SVGA3dCmdDXInvalidateSubResource const *pCmd, uint32_t cbCmd)
2896{
2897#ifdef VMSVGA3D_DX
2898 DEBUG_BREAKPOINT_TEST();
2899 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
2900 RT_NOREF(cbCmd);
2901
2902 LogFlowFunc(("sid=%u, subResource=%u\n",
2903 pCmd->sid, pCmd->subResource));
2904
2905 /* "Notify the device that the contents can be lost." */
2906 SVGAOTableSurfaceEntry entrySurface;
2907 int rc = vmsvgaR3OTableRead(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
2908 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entrySurface, sizeof(entrySurface));
2909 if (RT_SUCCESS(rc))
2910 {
2911 uint32_t iFace;
2912 uint32_t iMipmap;
2913 vmsvga3dCalcMipmapAndFace(entrySurface.numMipLevels, pCmd->subResource, &iMipmap, &iFace);
2914 vmsvga3dSurfaceInvalidate(pThisCC, pCmd->sid, iFace, iMipmap);
2915 }
2916
2917 return rc;
2918#else
2919 RT_NOREF(pThisCC, pCmd, cbCmd);
2920 return VERR_NOT_SUPPORTED;
2921#endif
2922}
2923
2924
2925/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW 1185 */
2926static int vmsvga3dCmdDXDefineShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShaderResourceView const *pCmd, uint32_t cbCmd)
2927{
2928#ifdef VMSVGA3D_DX
2929 //DEBUG_BREAKPOINT_TEST();
2930 RT_NOREF(cbCmd);
2931 return vmsvga3dDXDefineShaderResourceView(pThisCC, idDXContext, pCmd);
2932#else
2933 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2934 return VERR_NOT_SUPPORTED;
2935#endif
2936}
2937
2938
2939/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW 1186 */
2940static int vmsvga3dCmdDXDestroyShaderResourceView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShaderResourceView const *pCmd, uint32_t cbCmd)
2941{
2942#ifdef VMSVGA3D_DX
2943 //DEBUG_BREAKPOINT_TEST();
2944 RT_NOREF(cbCmd);
2945 return vmsvga3dDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd);
2946#else
2947 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2948 return VERR_NOT_SUPPORTED;
2949#endif
2950}
2951
2952
2953/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW 1187 */
2954static int vmsvga3dCmdDXDefineRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRenderTargetView const *pCmd, uint32_t cbCmd)
2955{
2956#ifdef VMSVGA3D_DX
2957 //DEBUG_BREAKPOINT_TEST();
2958 RT_NOREF(cbCmd);
2959 return vmsvga3dDXDefineRenderTargetView(pThisCC, idDXContext, pCmd);
2960#else
2961 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2962 return VERR_NOT_SUPPORTED;
2963#endif
2964}
2965
2966
2967/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW 1188 */
2968static int vmsvga3dCmdDXDestroyRenderTargetView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRenderTargetView const *pCmd, uint32_t cbCmd)
2969{
2970#ifdef VMSVGA3D_DX
2971 //DEBUG_BREAKPOINT_TEST();
2972 RT_NOREF(cbCmd);
2973 return vmsvga3dDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd);
2974#else
2975 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2976 return VERR_NOT_SUPPORTED;
2977#endif
2978}
2979
2980
2981/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW 1189 */
2982static int vmsvga3dCmdDXDefineDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView const *pCmd, uint32_t cbCmd)
2983{
2984#ifdef VMSVGA3D_DX
2985 //DEBUG_BREAKPOINT_TEST();
2986 RT_NOREF(cbCmd);
2987 SVGA3dCmdDXDefineDepthStencilView_v2 cmd;
2988 cmd.depthStencilViewId = pCmd->depthStencilViewId;
2989 cmd.sid = pCmd->sid;
2990 cmd.format = pCmd->format;
2991 cmd.resourceDimension = pCmd->resourceDimension;
2992 cmd.mipSlice = pCmd->mipSlice;
2993 cmd.firstArraySlice = pCmd->firstArraySlice;
2994 cmd.arraySize = pCmd->arraySize;
2995 cmd.flags = 0;
2996 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, &cmd);
2997#else
2998 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
2999 return VERR_NOT_SUPPORTED;
3000#endif
3001}
3002
3003
3004/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW 1190 */
3005static int vmsvga3dCmdDXDestroyDepthStencilView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilView const *pCmd, uint32_t cbCmd)
3006{
3007#ifdef VMSVGA3D_DX
3008 //DEBUG_BREAKPOINT_TEST();
3009 RT_NOREF(cbCmd);
3010 return vmsvga3dDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd);
3011#else
3012 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3013 return VERR_NOT_SUPPORTED;
3014#endif
3015}
3016
3017
3018/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT 1191 */
3019static int vmsvga3dCmdDXDefineElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineElementLayout const *pCmd, uint32_t cbCmd)
3020{
3021#ifdef VMSVGA3D_DX
3022 //DEBUG_BREAKPOINT_TEST();
3023 SVGA3dInputElementDesc const *paDesc = (SVGA3dInputElementDesc *)&pCmd[1];
3024 uint32_t const cDesc = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dInputElementDesc);
3025 return vmsvga3dDXDefineElementLayout(pThisCC, idDXContext, pCmd->elementLayoutId, cDesc, paDesc);
3026#else
3027 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3028 return VERR_NOT_SUPPORTED;
3029#endif
3030}
3031
3032
3033/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT 1192 */
3034static int vmsvga3dCmdDXDestroyElementLayout(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyElementLayout const *pCmd, uint32_t cbCmd)
3035{
3036#ifdef VMSVGA3D_DX
3037 //DEBUG_BREAKPOINT_TEST();
3038 RT_NOREF(cbCmd);
3039 return vmsvga3dDXDestroyElementLayout(pThisCC, idDXContext, pCmd);
3040#else
3041 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3042 return VERR_NOT_SUPPORTED;
3043#endif
3044}
3045
3046
3047/* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE 1193 */
3048static int vmsvga3dCmdDXDefineBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineBlendState const *pCmd, uint32_t cbCmd)
3049{
3050#ifdef VMSVGA3D_DX
3051 //DEBUG_BREAKPOINT_TEST();
3052 RT_NOREF(cbCmd);
3053 return vmsvga3dDXDefineBlendState(pThisCC, idDXContext, pCmd);
3054#else
3055 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3056 return VERR_NOT_SUPPORTED;
3057#endif
3058}
3059
3060
3061/* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE 1194 */
3062static int vmsvga3dCmdDXDestroyBlendState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyBlendState const *pCmd, uint32_t cbCmd)
3063{
3064#ifdef VMSVGA3D_DX
3065 //DEBUG_BREAKPOINT_TEST();
3066 RT_NOREF(cbCmd);
3067 return vmsvga3dDXDestroyBlendState(pThisCC, idDXContext, pCmd);
3068#else
3069 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3070 return VERR_NOT_SUPPORTED;
3071#endif
3072}
3073
3074
3075/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE 1195 */
3076static int vmsvga3dCmdDXDefineDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilState const *pCmd, uint32_t cbCmd)
3077{
3078#ifdef VMSVGA3D_DX
3079 //DEBUG_BREAKPOINT_TEST();
3080 RT_NOREF(cbCmd);
3081 return vmsvga3dDXDefineDepthStencilState(pThisCC, idDXContext, pCmd);
3082#else
3083 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3084 return VERR_NOT_SUPPORTED;
3085#endif
3086}
3087
3088
3089/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE 1196 */
3090static int vmsvga3dCmdDXDestroyDepthStencilState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyDepthStencilState const *pCmd, uint32_t cbCmd)
3091{
3092#ifdef VMSVGA3D_DX
3093 //DEBUG_BREAKPOINT_TEST();
3094 RT_NOREF(cbCmd);
3095 return vmsvga3dDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd);
3096#else
3097 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3098 return VERR_NOT_SUPPORTED;
3099#endif
3100}
3101
3102
3103/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE 1197 */
3104static int vmsvga3dCmdDXDefineRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineRasterizerState const *pCmd, uint32_t cbCmd)
3105{
3106#ifdef VMSVGA3D_DX
3107 //DEBUG_BREAKPOINT_TEST();
3108 RT_NOREF(cbCmd);
3109 return vmsvga3dDXDefineRasterizerState(pThisCC, idDXContext, pCmd);
3110#else
3111 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3112 return VERR_NOT_SUPPORTED;
3113#endif
3114}
3115
3116
3117/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE 1198 */
3118static int vmsvga3dCmdDXDestroyRasterizerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyRasterizerState const *pCmd, uint32_t cbCmd)
3119{
3120#ifdef VMSVGA3D_DX
3121 //DEBUG_BREAKPOINT_TEST();
3122 RT_NOREF(cbCmd);
3123 return vmsvga3dDXDestroyRasterizerState(pThisCC, idDXContext, pCmd);
3124#else
3125 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3126 return VERR_NOT_SUPPORTED;
3127#endif
3128}
3129
3130
3131/* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE 1199 */
3132static int vmsvga3dCmdDXDefineSamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineSamplerState const *pCmd, uint32_t cbCmd)
3133{
3134#ifdef VMSVGA3D_DX
3135 //DEBUG_BREAKPOINT_TEST();
3136 RT_NOREF(cbCmd);
3137 return vmsvga3dDXDefineSamplerState(pThisCC, idDXContext, pCmd);
3138#else
3139 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3140 return VERR_NOT_SUPPORTED;
3141#endif
3142}
3143
3144
3145/* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE 1200 */
3146static int vmsvga3dCmdDXDestroySamplerState(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroySamplerState const *pCmd, uint32_t cbCmd)
3147{
3148#ifdef VMSVGA3D_DX
3149 //DEBUG_BREAKPOINT_TEST();
3150 RT_NOREF(cbCmd);
3151 return vmsvga3dDXDestroySamplerState(pThisCC, idDXContext, pCmd);
3152#else
3153 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3154 return VERR_NOT_SUPPORTED;
3155#endif
3156}
3157
3158
3159/* SVGA_3D_CMD_DX_DEFINE_SHADER 1201 */
3160static int vmsvga3dCmdDXDefineShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineShader const *pCmd, uint32_t cbCmd)
3161{
3162#ifdef VMSVGA3D_DX
3163 //DEBUG_BREAKPOINT_TEST();
3164 RT_NOREF(cbCmd);
3165 return vmsvga3dDXDefineShader(pThisCC, idDXContext, pCmd);
3166#else
3167 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3168 return VERR_NOT_SUPPORTED;
3169#endif
3170}
3171
3172
3173/* SVGA_3D_CMD_DX_DESTROY_SHADER 1202 */
3174static int vmsvga3dCmdDXDestroyShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyShader const *pCmd, uint32_t cbCmd)
3175{
3176#ifdef VMSVGA3D_DX
3177 //DEBUG_BREAKPOINT_TEST();
3178 RT_NOREF(cbCmd);
3179 return vmsvga3dDXDestroyShader(pThisCC, idDXContext, pCmd);
3180#else
3181 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3182 return VERR_NOT_SUPPORTED;
3183#endif
3184}
3185
3186
3187/* SVGA_3D_CMD_DX_BIND_SHADER 1203 */
3188static int vmsvga3dCmdDXBindShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShader const *pCmd, uint32_t cbCmd)
3189{
3190#ifdef VMSVGA3D_DX
3191 //DEBUG_BREAKPOINT_TEST();
3192 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3193 RT_NOREF(idDXContext, cbCmd);
3194 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3195 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3196 return vmsvga3dDXBindShader(pThisCC, pCmd, pMob);
3197#else
3198 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3199 return VERR_NOT_SUPPORTED;
3200#endif
3201}
3202
3203
3204/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT 1204 */
3205static int vmsvga3dCmdDXDefineStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutput const *pCmd, uint32_t cbCmd)
3206{
3207#ifdef VMSVGA3D_DX
3208 //DEBUG_BREAKPOINT_TEST();
3209 RT_NOREF(cbCmd);
3210 return vmsvga3dDXDefineStreamOutput(pThisCC, idDXContext, pCmd);
3211#else
3212 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3213 return VERR_NOT_SUPPORTED;
3214#endif
3215}
3216
3217
3218/* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT 1205 */
3219static int vmsvga3dCmdDXDestroyStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyStreamOutput const *pCmd, uint32_t cbCmd)
3220{
3221#ifdef VMSVGA3D_DX
3222 //DEBUG_BREAKPOINT_TEST();
3223 RT_NOREF(cbCmd);
3224 return vmsvga3dDXDestroyStreamOutput(pThisCC, idDXContext, pCmd);
3225#else
3226 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3227 return VERR_NOT_SUPPORTED;
3228#endif
3229}
3230
3231
3232/* SVGA_3D_CMD_DX_SET_STREAMOUTPUT 1206 */
3233static int vmsvga3dCmdDXSetStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStreamOutput const *pCmd, uint32_t cbCmd)
3234{
3235#ifdef VMSVGA3D_DX
3236 //DEBUG_BREAKPOINT_TEST();
3237 RT_NOREF(cbCmd);
3238 return vmsvga3dDXSetStreamOutput(pThisCC, idDXContext, pCmd);
3239#else
3240 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3241 return VERR_NOT_SUPPORTED;
3242#endif
3243}
3244
3245
3246/* SVGA_3D_CMD_DX_SET_COTABLE 1207 */
3247static int vmsvga3dCmdDXSetCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXSetCOTable const *pCmd, uint32_t cbCmd)
3248{
3249#ifdef VMSVGA3D_DX
3250 //DEBUG_BREAKPOINT_TEST();
3251 RT_NOREF(cbCmd);
3252 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3253 /* This returns NULL if mob does not exist. If the guest sends a wrong mob id, the current mob will be unbound. */
3254 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobid);
3255 return vmsvga3dDXSetCOTable(pThisCC, pCmd, pMob);
3256#else
3257 RT_NOREF(pThisCC, pCmd, cbCmd);
3258 return VERR_NOT_SUPPORTED;
3259#endif
3260}
3261
3262
3263/* SVGA_3D_CMD_DX_READBACK_COTABLE 1208 */
3264static int vmsvga3dCmdDXReadbackCOTable(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackCOTable const *pCmd, uint32_t cbCmd)
3265{
3266#ifdef VMSVGA3D_DX
3267 //DEBUG_BREAKPOINT_TEST();
3268 RT_NOREF(idDXContext, cbCmd);
3269 return vmsvga3dDXReadbackCOTable(pThisCC, pCmd);
3270#else
3271 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3272 return VERR_NOT_SUPPORTED;
3273#endif
3274}
3275
3276
3277/* SVGA_3D_CMD_DX_BUFFER_COPY 1209 */
3278static int vmsvga3dCmdDXBufferCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferCopy const *pCmd, uint32_t cbCmd)
3279{
3280#ifdef VMSVGA3D_DX
3281 //DEBUG_BREAKPOINT_TEST();
3282 RT_NOREF(idDXContext, cbCmd);
3283
3284 int rc;
3285
3286 /** @todo Backend should o the copy is both buffers have a hardware resource. */
3287 SVGA3dSurfaceImageId imageBufferSrc;
3288 imageBufferSrc.sid = pCmd->src;
3289 imageBufferSrc.face = 0;
3290 imageBufferSrc.mipmap = 0;
3291
3292 SVGA3dSurfaceImageId imageBufferDest;
3293 imageBufferDest.sid = pCmd->dest;
3294 imageBufferDest.face = 0;
3295 imageBufferDest.mipmap = 0;
3296
3297 /*
3298 * Map the source buffer.
3299 */
3300 VMSVGA3D_MAPPED_SURFACE mapBufferSrc;
3301 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferSrc, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBufferSrc);
3302 if (RT_SUCCESS(rc))
3303 {
3304 /*
3305 * Map the destination buffer.
3306 */
3307 VMSVGA3D_MAPPED_SURFACE mapBufferDest;
3308 rc = vmsvga3dSurfaceMap(pThisCC, &imageBufferDest, NULL, VMSVGA3D_SURFACE_MAP_WRITE, &mapBufferDest);
3309 if (RT_SUCCESS(rc))
3310 {
3311 /*
3312 * Copy the source buffer to the destination.
3313 */
3314 uint8_t const *pu8BufferSrc = (uint8_t *)mapBufferSrc.pvData;
3315 uint32_t const cbBufferSrc = mapBufferSrc.cbRow;
3316
3317 uint8_t *pu8BufferDest = (uint8_t *)mapBufferDest.pvData;
3318 uint32_t const cbBufferDest = mapBufferDest.cbRow;
3319
3320 if ( pCmd->srcX < cbBufferSrc
3321 && pCmd->width <= cbBufferSrc- pCmd->srcX
3322 && pCmd->destX < cbBufferDest
3323 && pCmd->width <= cbBufferDest - pCmd->destX)
3324 {
3325 RT_UNTRUSTED_VALIDATED_FENCE();
3326
3327 memcpy(&pu8BufferDest[pCmd->destX], &pu8BufferSrc[pCmd->srcX], pCmd->width);
3328 }
3329 else
3330 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3331
3332 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferDest, &mapBufferDest, true);
3333 }
3334
3335 vmsvga3dSurfaceUnmap(pThisCC, &imageBufferSrc, &mapBufferSrc, false);
3336 }
3337
3338 return rc;
3339#else
3340 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3341 return VERR_NOT_SUPPORTED;
3342#endif
3343}
3344
3345
3346/* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER 1210 */
3347static int vmsvga3dCmdDXTransferFromBuffer(PVGASTATECC pThisCC, SVGA3dCmdDXTransferFromBuffer const *pCmd, uint32_t cbCmd)
3348{
3349#ifdef VMSVGA3D_DX
3350 //DEBUG_BREAKPOINT_TEST();
3351 RT_NOREF(cbCmd);
3352
3353 /* Plan:
3354 * - map the buffer;
3355 * - map the surface;
3356 * - copy from buffer map to the surface map.
3357 */
3358
3359 int rc;
3360
3361 SVGA3dSurfaceImageId imageBuffer;
3362 imageBuffer.sid = pCmd->srcSid;
3363 imageBuffer.face = 0;
3364 imageBuffer.mipmap = 0;
3365
3366 SVGA3dSurfaceImageId imageSurface;
3367 imageSurface.sid = pCmd->destSid;
3368 rc = vmsvga3dCalcSurfaceMipmapAndFace(pThisCC, pCmd->destSid, pCmd->destSubResource, &imageSurface.mipmap, &imageSurface.face);
3369 AssertRCReturn(rc, rc);
3370
3371 /*
3372 * Map the buffer.
3373 */
3374 VMSVGA3D_MAPPED_SURFACE mapBuffer;
3375 rc = vmsvga3dSurfaceMap(pThisCC, &imageBuffer, NULL, VMSVGA3D_SURFACE_MAP_READ, &mapBuffer);
3376 if (RT_SUCCESS(rc))
3377 {
3378 /*
3379 * Map the surface.
3380 */
3381 VMSVGA3D_MAPPED_SURFACE mapSurface;
3382 rc = vmsvga3dSurfaceMap(pThisCC, &imageSurface, &pCmd->destBox, VMSVGA3D_SURFACE_MAP_WRITE, &mapSurface);
3383 if (RT_SUCCESS(rc))
3384 {
3385 /*
3386 * Copy the mapped buffer to the surface. "Raw byte wise transfer"
3387 */
3388 uint8_t const *pu8Buffer = (uint8_t *)mapBuffer.pvData;
3389 uint32_t const cbBuffer = mapBuffer.cbRow;
3390
3391 if (pCmd->srcOffset <= cbBuffer)
3392 {
3393 RT_UNTRUSTED_VALIDATED_FENCE();
3394 uint8_t const *pu8BufferBegin = pu8Buffer;
3395 uint8_t const *pu8BufferEnd = pu8Buffer + cbBuffer;
3396
3397 pu8Buffer += pCmd->srcOffset;
3398
3399 uint8_t *pu8Surface = (uint8_t *)mapSurface.pvData;
3400
3401 uint32_t const cbRowCopy = RT_MIN(pCmd->srcPitch, mapSurface.cbRow);
3402 for (uint32_t z = 0; z < mapSurface.box.d && RT_SUCCESS(rc); ++z)
3403 {
3404 uint8_t const *pu8BufferRow = pu8Buffer;
3405 uint8_t *pu8SurfaceRow = pu8Surface;
3406 for (uint32_t iRow = 0; iRow < mapSurface.cRows; ++iRow)
3407 {
3408 ASSERT_GUEST_STMT_BREAK( (uintptr_t)pu8BufferRow >= (uintptr_t)pu8BufferBegin
3409 && (uintptr_t)pu8BufferRow < (uintptr_t)pu8BufferEnd
3410 && (uintptr_t)pu8BufferRow < (uintptr_t)(pu8BufferRow + cbRowCopy)
3411 && (uintptr_t)(pu8BufferRow + cbRowCopy) > (uintptr_t)pu8BufferBegin
3412 && (uintptr_t)(pu8BufferRow + cbRowCopy) <= (uintptr_t)pu8BufferEnd,
3413 rc = VERR_INVALID_PARAMETER);
3414
3415 memcpy(pu8SurfaceRow, pu8BufferRow, cbRowCopy);
3416
3417 pu8SurfaceRow += mapSurface.cbRowPitch;
3418 pu8BufferRow += pCmd->srcPitch;
3419 }
3420
3421 pu8Buffer += pCmd->srcSlicePitch;
3422 pu8Surface += mapSurface.cbDepthPitch;
3423 }
3424 }
3425 else
3426 ASSERT_GUEST_FAILED_STMT(rc = VERR_INVALID_PARAMETER);
3427
3428 vmsvga3dSurfaceUnmap(pThisCC, &imageSurface, &mapSurface, true);
3429 }
3430
3431 vmsvga3dSurfaceUnmap(pThisCC, &imageBuffer, &mapBuffer, false);
3432 }
3433
3434 return rc;
3435#else
3436 RT_NOREF(pThisCC, pCmd, cbCmd);
3437 return VERR_NOT_SUPPORTED;
3438#endif
3439}
3440
3441
3442/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK 1211 */
3443static int vmsvga3dCmdDXSurfaceCopyAndReadback(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSurfaceCopyAndReadback const *pCmd, uint32_t cbCmd)
3444{
3445#ifdef VMSVGA3D_DX
3446 DEBUG_BREAKPOINT_TEST();
3447 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3448 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3449 return vmsvga3dDXSurfaceCopyAndReadback(pThisCC, idDXContext);
3450#else
3451 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3452 return VERR_NOT_SUPPORTED;
3453#endif
3454}
3455
3456
3457/* SVGA_3D_CMD_DX_MOVE_QUERY 1212 */
3458static int vmsvga3dCmdDXMoveQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXMoveQuery const *pCmd, uint32_t cbCmd)
3459{
3460#ifdef VMSVGA3D_DX
3461 DEBUG_BREAKPOINT_TEST();
3462 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3463 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3464 return vmsvga3dDXMoveQuery(pThisCC, idDXContext);
3465#else
3466 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3467 return VERR_NOT_SUPPORTED;
3468#endif
3469}
3470
3471
3472/* SVGA_3D_CMD_DX_BIND_ALL_QUERY 1213 */
3473static int vmsvga3dCmdDXBindAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllQuery const *pCmd, uint32_t cbCmd)
3474{
3475#ifdef VMSVGA3D_DX
3476 //DEBUG_BREAKPOINT_TEST();
3477 RT_NOREF(cbCmd);
3478 return vmsvga3dDXBindAllQuery(pThisCC, idDXContext, pCmd);
3479#else
3480 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3481 return VERR_NOT_SUPPORTED;
3482#endif
3483}
3484
3485
3486/* SVGA_3D_CMD_DX_READBACK_ALL_QUERY 1214 */
3487static int vmsvga3dCmdDXReadbackAllQuery(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXReadbackAllQuery const *pCmd, uint32_t cbCmd)
3488{
3489#ifdef VMSVGA3D_DX
3490 //DEBUG_BREAKPOINT_TEST();
3491 RT_NOREF(cbCmd);
3492 return vmsvga3dDXReadbackAllQuery(pThisCC, idDXContext, pCmd);
3493#else
3494 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3495 return VERR_NOT_SUPPORTED;
3496#endif
3497}
3498
3499
3500/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER 1215 */
3501static int vmsvga3dCmdDXPredTransferFromBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredTransferFromBuffer const *pCmd, uint32_t cbCmd)
3502{
3503#ifdef VMSVGA3D_DX
3504 //DEBUG_BREAKPOINT_TEST();
3505 RT_NOREF(idDXContext, cbCmd);
3506
3507 /* This command is executed in a context: "The context is implied from the command buffer header."
3508 * However the device design allows to do the transfer without a context, so re-use context-less command handler.
3509 */
3510 SVGA3dCmdDXTransferFromBuffer cmd;
3511 cmd.srcSid = pCmd->srcSid;
3512 cmd.srcOffset = pCmd->srcOffset;
3513 cmd.srcPitch = pCmd->srcPitch;
3514 cmd.srcSlicePitch = pCmd->srcSlicePitch;
3515 cmd.destSid = pCmd->destSid;
3516 cmd.destSubResource = pCmd->destSubResource;
3517 cmd.destBox = pCmd->destBox;
3518 return vmsvga3dCmdDXTransferFromBuffer(pThisCC, &cmd, sizeof(cmd));
3519#else
3520 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3521 return VERR_NOT_SUPPORTED;
3522#endif
3523}
3524
3525
3526/* SVGA_3D_CMD_DX_MOB_FENCE_64 1216 */
3527static int vmsvga3dCmdDXMobFence64(PVGASTATECC pThisCC, SVGA3dCmdDXMobFence64 const *pCmd, uint32_t cbCmd)
3528{
3529#ifdef VMSVGA3D_DX
3530 //DEBUG_BREAKPOINT_TEST();
3531 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3532 RT_NOREF(cbCmd);
3533
3534 PVMSVGAMOB pMob = vmsvgaR3MobGet(pSvgaR3State, pCmd->mobId);
3535 ASSERT_GUEST_RETURN(pMob, VERR_INVALID_PARAMETER);
3536
3537 int rc = vmsvgaR3MobWrite(pSvgaR3State, pMob, pCmd->mobOffset, &pCmd->value, sizeof(pCmd->value));
3538 ASSERT_GUEST_RETURN(RT_SUCCESS(rc), rc);
3539
3540 return VINF_SUCCESS;
3541#else
3542 RT_NOREF(pThisCC, pCmd, cbCmd);
3543 return VERR_NOT_SUPPORTED;
3544#endif
3545}
3546
3547
3548/* SVGA_3D_CMD_DX_BIND_ALL_SHADER 1217 */
3549static int vmsvga3dCmdDXBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindAllShader const *pCmd, uint32_t cbCmd)
3550{
3551#ifdef VMSVGA3D_DX
3552 DEBUG_BREAKPOINT_TEST();
3553 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3554 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3555 return vmsvga3dDXBindAllShader(pThisCC, idDXContext);
3556#else
3557 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3558 return VERR_NOT_SUPPORTED;
3559#endif
3560}
3561
3562
3563/* SVGA_3D_CMD_DX_HINT 1218 */
3564static int vmsvga3dCmdDXHint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXHint const *pCmd, uint32_t cbCmd)
3565{
3566#ifdef VMSVGA3D_DX
3567 DEBUG_BREAKPOINT_TEST();
3568 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3569 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3570 return vmsvga3dDXHint(pThisCC, idDXContext);
3571#else
3572 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3573 return VERR_NOT_SUPPORTED;
3574#endif
3575}
3576
3577
3578/* SVGA_3D_CMD_DX_BUFFER_UPDATE 1219 */
3579static int vmsvga3dCmdDXBufferUpdate(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBufferUpdate const *pCmd, uint32_t cbCmd)
3580{
3581#ifdef VMSVGA3D_DX
3582 DEBUG_BREAKPOINT_TEST();
3583 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3584 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3585 return vmsvga3dDXBufferUpdate(pThisCC, idDXContext);
3586#else
3587 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3588 return VERR_NOT_SUPPORTED;
3589#endif
3590}
3591
3592
3593/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET 1220 */
3594static int vmsvga3dCmdDXSetVSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetVSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3595{
3596#ifdef VMSVGA3D_DX
3597 //DEBUG_BREAKPOINT_TEST();
3598 RT_NOREF(cbCmd);
3599 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_VS);
3600#else
3601 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3602 return VERR_NOT_SUPPORTED;
3603#endif
3604}
3605
3606
3607/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET 1221 */
3608static int vmsvga3dCmdDXSetPSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetPSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3609{
3610#ifdef VMSVGA3D_DX
3611 //DEBUG_BREAKPOINT_TEST();
3612 RT_NOREF(cbCmd);
3613 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_PS);
3614#else
3615 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3616 return VERR_NOT_SUPPORTED;
3617#endif
3618}
3619
3620
3621/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET 1222 */
3622static int vmsvga3dCmdDXSetGSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetGSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3623{
3624#ifdef VMSVGA3D_DX
3625 //DEBUG_BREAKPOINT_TEST();
3626 RT_NOREF(cbCmd);
3627 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_GS);
3628#else
3629 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3630 return VERR_NOT_SUPPORTED;
3631#endif
3632}
3633
3634
3635/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET 1223 */
3636static int vmsvga3dCmdDXSetHSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetHSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3637{
3638#ifdef VMSVGA3D_DX
3639 //DEBUG_BREAKPOINT_TEST();
3640 RT_NOREF(cbCmd);
3641 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_HS);
3642#else
3643 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3644 return VERR_NOT_SUPPORTED;
3645#endif
3646}
3647
3648
3649/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET 1224 */
3650static int vmsvga3dCmdDXSetDSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetDSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3651{
3652#ifdef VMSVGA3D_DX
3653 //DEBUG_BREAKPOINT_TEST();
3654 RT_NOREF(cbCmd);
3655 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_DS);
3656#else
3657 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3658 return VERR_NOT_SUPPORTED;
3659#endif
3660}
3661
3662
3663/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET 1225 */
3664static int vmsvga3dCmdDXSetCSConstantBufferOffset(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSConstantBufferOffset const *pCmd, uint32_t cbCmd)
3665{
3666#ifdef VMSVGA3D_DX
3667 //DEBUG_BREAKPOINT_TEST();
3668 RT_NOREF(cbCmd);
3669 return vmsvga3dDXSetConstantBufferOffset(pThisCC, idDXContext, pCmd, SVGA3D_SHADERTYPE_CS);
3670#else
3671 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3672 return VERR_NOT_SUPPORTED;
3673#endif
3674}
3675
3676
3677/* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER 1226 */
3678static int vmsvga3dCmdDXCondBindAllShader(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCondBindAllShader const *pCmd, uint32_t cbCmd)
3679{
3680#ifdef VMSVGA3D_DX
3681 DEBUG_BREAKPOINT_TEST();
3682 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3683 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3684 return vmsvga3dDXCondBindAllShader(pThisCC, idDXContext);
3685#else
3686 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3687 return VERR_NOT_SUPPORTED;
3688#endif
3689}
3690
3691
3692/* SVGA_3D_CMD_SCREEN_COPY 1227 */
3693static int vmsvga3dCmdScreenCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdScreenCopy const *pCmd, uint32_t cbCmd)
3694{
3695#ifdef VMSVGA3D_DX
3696 DEBUG_BREAKPOINT_TEST();
3697 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3698 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3699 return vmsvga3dScreenCopy(pThisCC, idDXContext);
3700#else
3701 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3702 return VERR_NOT_SUPPORTED;
3703#endif
3704}
3705
3706
3707/* SVGA_3D_CMD_GROW_OTABLE 1236 */
3708static int vmsvga3dCmdGrowOTable(PVGASTATECC pThisCC, SVGA3dCmdGrowOTable const *pCmd, uint32_t cbCmd)
3709{
3710#ifdef VMSVGA3D_DX
3711 //DEBUG_BREAKPOINT_TEST();
3712 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3713 RT_NOREF(cbCmd);
3714 return vmsvgaR3OTableSetOrGrow(pSvgaR3State, pCmd->type, pCmd->baseAddress,
3715 pCmd->sizeInBytes, pCmd->validSizeInBytes, pCmd->ptDepth, /*fGrow*/ true);
3716#else
3717 RT_NOREF(pThisCC, pCmd, cbCmd);
3718 return VERR_NOT_SUPPORTED;
3719#endif
3720}
3721
3722
3723/* SVGA_3D_CMD_DX_GROW_COTABLE 1237 */
3724static int vmsvga3dCmdDXGrowCOTable(PVGASTATECC pThisCC, SVGA3dCmdDXGrowCOTable const *pCmd, uint32_t cbCmd)
3725{
3726#ifdef VMSVGA3D_DX
3727 //DEBUG_BREAKPOINT_TEST();
3728 RT_NOREF(cbCmd);
3729 return vmsvga3dDXGrowCOTable(pThisCC, pCmd);
3730#else
3731 RT_NOREF(pThisCC, pCmd, cbCmd);
3732 return VERR_NOT_SUPPORTED;
3733#endif
3734}
3735
3736
3737/* SVGA_3D_CMD_INTRA_SURFACE_COPY 1238 */
3738static int vmsvga3dCmdIntraSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdIntraSurfaceCopy const *pCmd, uint32_t cbCmd)
3739{
3740#ifdef VMSVGA3D_DX
3741 //DEBUG_BREAKPOINT_TEST();
3742 RT_NOREF(cbCmd);
3743 return vmsvga3dIntraSurfaceCopy(pThisCC, idDXContext, pCmd);
3744#else
3745 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3746 return VERR_NOT_SUPPORTED;
3747#endif
3748}
3749
3750
3751/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 1239 */
3752static int vmsvga3dCmdDefineGBSurface_v3(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v3 const *pCmd)
3753{
3754#ifdef VMSVGA3D_DX
3755 //DEBUG_BREAKPOINT_TEST();
3756 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3757
3758 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
3759 SVGAOTableSurfaceEntry entry;
3760 RT_ZERO(entry);
3761 entry.format = pCmd->format;
3762 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
3763 entry.numMipLevels = pCmd->numMipLevels;
3764 entry.multisampleCount = pCmd->multisampleCount;
3765 entry.autogenFilter = pCmd->autogenFilter;
3766 entry.size = pCmd->size;
3767 entry.mobid = SVGA_ID_INVALID;
3768 entry.arraySize = pCmd->arraySize;
3769 // entry.mobPitch = 0;
3770 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
3771 entry.multisamplePattern = pCmd->multisamplePattern;
3772 entry.qualityLevel = pCmd->qualityLevel;
3773 // entry.bufferByteStride = 0;
3774 // entry.minLOD = 0;
3775
3776 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
3777 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
3778 if (RT_SUCCESS(rc))
3779 {
3780 /* Create the host surface. */
3781 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
3782 pCmd->multisampleCount, pCmd->multisamplePattern, pCmd->qualityLevel, pCmd->autogenFilter,
3783 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, /* bufferByteStride = */ 0, /* fAllocMipLevels = */ false);
3784 }
3785 return rc;
3786#else
3787 RT_NOREF(pThisCC, pCmd);
3788 return VERR_NOT_SUPPORTED;
3789#endif
3790}
3791
3792
3793/* SVGA_3D_CMD_DX_RESOLVE_COPY 1240 */
3794static int vmsvga3dCmdDXResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXResolveCopy const *pCmd, uint32_t cbCmd)
3795{
3796#ifdef VMSVGA3D_DX
3797 //DEBUG_BREAKPOINT_TEST();
3798 RT_NOREF(cbCmd);
3799 return vmsvga3dDXResolveCopy(pThisCC, idDXContext, pCmd);
3800#else
3801 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3802 return VERR_NOT_SUPPORTED;
3803#endif
3804}
3805
3806
3807/* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY 1241 */
3808static int vmsvga3dCmdDXPredResolveCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredResolveCopy const *pCmd, uint32_t cbCmd)
3809{
3810#ifdef VMSVGA3D_DX
3811 DEBUG_BREAKPOINT_TEST();
3812 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3813 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3814 return vmsvga3dDXPredResolveCopy(pThisCC, idDXContext);
3815#else
3816 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3817 return VERR_NOT_SUPPORTED;
3818#endif
3819}
3820
3821
3822/* SVGA_3D_CMD_DX_PRED_CONVERT_REGION 1242 */
3823static int vmsvga3dCmdDXPredConvertRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvertRegion const *pCmd, uint32_t cbCmd)
3824{
3825#ifdef VMSVGA3D_DX
3826 DEBUG_BREAKPOINT_TEST();
3827 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3828 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3829 return vmsvga3dDXPredConvertRegion(pThisCC, idDXContext);
3830#else
3831 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3832 return VERR_NOT_SUPPORTED;
3833#endif
3834}
3835
3836
3837/* SVGA_3D_CMD_DX_PRED_CONVERT 1243 */
3838static int vmsvga3dCmdDXPredConvert(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXPredConvert const *pCmd, uint32_t cbCmd)
3839{
3840#ifdef VMSVGA3D_DX
3841 DEBUG_BREAKPOINT_TEST();
3842 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3843 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3844 return vmsvga3dDXPredConvert(pThisCC, idDXContext);
3845#else
3846 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3847 return VERR_NOT_SUPPORTED;
3848#endif
3849}
3850
3851
3852/* SVGA_3D_CMD_WHOLE_SURFACE_COPY 1244 */
3853static int vmsvga3dCmdWholeSurfaceCopy(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWholeSurfaceCopy const *pCmd, uint32_t cbCmd)
3854{
3855#ifdef VMSVGA3D_DX
3856 DEBUG_BREAKPOINT_TEST();
3857 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3858 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
3859 return vmsvga3dWholeSurfaceCopy(pThisCC, idDXContext);
3860#else
3861 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3862 return VERR_NOT_SUPPORTED;
3863#endif
3864}
3865
3866
3867/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW 1245 */
3868static int vmsvga3dCmdDXDefineUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineUAView const *pCmd, uint32_t cbCmd)
3869{
3870#ifdef VMSVGA3D_DX
3871 //DEBUG_BREAKPOINT_TEST();
3872 RT_NOREF(cbCmd);
3873 return vmsvga3dDXDefineUAView(pThisCC, idDXContext, pCmd);
3874#else
3875 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3876 return VERR_NOT_SUPPORTED;
3877#endif
3878}
3879
3880
3881/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW 1246 */
3882static int vmsvga3dCmdDXDestroyUAView(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDestroyUAView const *pCmd, uint32_t cbCmd)
3883{
3884#ifdef VMSVGA3D_DX
3885 //DEBUG_BREAKPOINT_TEST();
3886 RT_NOREF(cbCmd);
3887 return vmsvga3dDXDestroyUAView(pThisCC, idDXContext, pCmd);
3888#else
3889 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3890 return VERR_NOT_SUPPORTED;
3891#endif
3892}
3893
3894
3895/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT 1247 */
3896static int vmsvga3dCmdDXClearUAViewUint(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewUint const *pCmd, uint32_t cbCmd)
3897{
3898#ifdef VMSVGA3D_DX
3899 DEBUG_BREAKPOINT_TEST();
3900 RT_NOREF(cbCmd);
3901 return vmsvga3dDXClearUAViewUint(pThisCC, idDXContext, pCmd);
3902#else
3903 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3904 return VERR_NOT_SUPPORTED;
3905#endif
3906}
3907
3908
3909/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT 1248 */
3910static int vmsvga3dCmdDXClearUAViewFloat(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXClearUAViewFloat const *pCmd, uint32_t cbCmd)
3911{
3912#ifdef VMSVGA3D_DX
3913 DEBUG_BREAKPOINT_TEST();
3914 RT_NOREF(cbCmd);
3915 return vmsvga3dDXClearUAViewFloat(pThisCC, idDXContext, pCmd);
3916#else
3917 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3918 return VERR_NOT_SUPPORTED;
3919#endif
3920}
3921
3922
3923/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT 1249 */
3924static int vmsvga3dCmdDXCopyStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXCopyStructureCount const *pCmd, uint32_t cbCmd)
3925{
3926#ifdef VMSVGA3D_DX
3927 //DEBUG_BREAKPOINT_TEST();
3928 RT_NOREF(cbCmd);
3929 return vmsvga3dDXCopyStructureCount(pThisCC, idDXContext, pCmd);
3930#else
3931 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3932 return VERR_NOT_SUPPORTED;
3933#endif
3934}
3935
3936
3937/* SVGA_3D_CMD_DX_SET_UA_VIEWS 1250 */
3938static int vmsvga3dCmdDXSetUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetUAViews const *pCmd, uint32_t cbCmd)
3939{
3940#ifdef VMSVGA3D_DX
3941 //DEBUG_BREAKPOINT_TEST();
3942 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
3943 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
3944 return vmsvga3dDXSetUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
3945#else
3946 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3947 return VERR_NOT_SUPPORTED;
3948#endif
3949}
3950
3951
3952/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT 1251 */
3953static int vmsvga3dCmdDXDrawIndexedInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawIndexedInstancedIndirect const *pCmd, uint32_t cbCmd)
3954{
3955#ifdef VMSVGA3D_DX
3956 //DEBUG_BREAKPOINT_TEST();
3957 RT_NOREF(cbCmd);
3958 return vmsvga3dDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd);
3959#else
3960 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3961 return VERR_NOT_SUPPORTED;
3962#endif
3963}
3964
3965
3966/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT 1252 */
3967static int vmsvga3dCmdDXDrawInstancedIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDrawInstancedIndirect const *pCmd, uint32_t cbCmd)
3968{
3969#ifdef VMSVGA3D_DX
3970 //DEBUG_BREAKPOINT_TEST();
3971 RT_NOREF(cbCmd);
3972 return vmsvga3dDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd);
3973#else
3974 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3975 return VERR_NOT_SUPPORTED;
3976#endif
3977}
3978
3979
3980/* SVGA_3D_CMD_DX_DISPATCH 1253 */
3981static int vmsvga3dCmdDXDispatch(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatch const *pCmd, uint32_t cbCmd)
3982{
3983#ifdef VMSVGA3D_DX
3984 //DEBUG_BREAKPOINT_TEST();
3985 RT_NOREF(cbCmd);
3986 return vmsvga3dDXDispatch(pThisCC, idDXContext, pCmd);
3987#else
3988 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
3989 return VERR_NOT_SUPPORTED;
3990#endif
3991}
3992
3993
3994/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT 1254 */
3995static int vmsvga3dCmdDXDispatchIndirect(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDispatchIndirect const *pCmd, uint32_t cbCmd)
3996{
3997#ifdef VMSVGA3D_DX
3998 DEBUG_BREAKPOINT_TEST();
3999 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4000 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4001 return vmsvga3dDXDispatchIndirect(pThisCC, idDXContext);
4002#else
4003 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4004 return VERR_NOT_SUPPORTED;
4005#endif
4006}
4007
4008
4009/* SVGA_3D_CMD_WRITE_ZERO_SURFACE 1255 */
4010static int vmsvga3dCmdWriteZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdWriteZeroSurface const *pCmd, uint32_t cbCmd)
4011{
4012#ifdef VMSVGA3D_DX
4013 DEBUG_BREAKPOINT_TEST();
4014 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4015 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4016 return vmsvga3dWriteZeroSurface(pThisCC, idDXContext);
4017#else
4018 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4019 return VERR_NOT_SUPPORTED;
4020#endif
4021}
4022
4023
4024/* SVGA_3D_CMD_HINT_ZERO_SURFACE 1256 */
4025static int vmsvga3dCmdHintZeroSurface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdHintZeroSurface const *pCmd, uint32_t cbCmd)
4026{
4027#ifdef VMSVGA3D_DX
4028 DEBUG_BREAKPOINT_TEST();
4029 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4030 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4031 return vmsvga3dHintZeroSurface(pThisCC, idDXContext);
4032#else
4033 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4034 return VERR_NOT_SUPPORTED;
4035#endif
4036}
4037
4038
4039/* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER 1257 */
4040static int vmsvga3dCmdDXTransferToBuffer(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXTransferToBuffer const *pCmd, uint32_t cbCmd)
4041{
4042#ifdef VMSVGA3D_DX
4043 DEBUG_BREAKPOINT_TEST();
4044 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4045 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4046 return vmsvga3dDXTransferToBuffer(pThisCC, idDXContext);
4047#else
4048 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4049 return VERR_NOT_SUPPORTED;
4050#endif
4051}
4052
4053
4054/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT 1258 */
4055static int vmsvga3dCmdDXSetStructureCount(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetStructureCount const *pCmd, uint32_t cbCmd)
4056{
4057#ifdef VMSVGA3D_DX
4058 //DEBUG_BREAKPOINT_TEST();
4059 RT_NOREF(cbCmd);
4060 return vmsvga3dDXSetStructureCount(pThisCC, idDXContext, pCmd);
4061#else
4062 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4063 return VERR_NOT_SUPPORTED;
4064#endif
4065}
4066
4067
4068/* SVGA_3D_CMD_LOGICOPS_BITBLT 1259 */
4069static int vmsvga3dCmdLogicOpsBitBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsBitBlt const *pCmd, uint32_t cbCmd)
4070{
4071#ifdef VMSVGA3D_DX
4072 DEBUG_BREAKPOINT_TEST();
4073 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4074 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4075 return vmsvga3dLogicOpsBitBlt(pThisCC, idDXContext);
4076#else
4077 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4078 return VERR_NOT_SUPPORTED;
4079#endif
4080}
4081
4082
4083/* SVGA_3D_CMD_LOGICOPS_TRANSBLT 1260 */
4084static int vmsvga3dCmdLogicOpsTransBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsTransBlt const *pCmd, uint32_t cbCmd)
4085{
4086#ifdef VMSVGA3D_DX
4087 DEBUG_BREAKPOINT_TEST();
4088 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4089 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4090 return vmsvga3dLogicOpsTransBlt(pThisCC, idDXContext);
4091#else
4092 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4093 return VERR_NOT_SUPPORTED;
4094#endif
4095}
4096
4097
4098/* SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1261 */
4099static int vmsvga3dCmdLogicOpsStretchBlt(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsStretchBlt const *pCmd, uint32_t cbCmd)
4100{
4101#ifdef VMSVGA3D_DX
4102 DEBUG_BREAKPOINT_TEST();
4103 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4104 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4105 return vmsvga3dLogicOpsStretchBlt(pThisCC, idDXContext);
4106#else
4107 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4108 return VERR_NOT_SUPPORTED;
4109#endif
4110}
4111
4112
4113/* SVGA_3D_CMD_LOGICOPS_COLORFILL 1262 */
4114static int vmsvga3dCmdLogicOpsColorFill(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsColorFill const *pCmd, uint32_t cbCmd)
4115{
4116#ifdef VMSVGA3D_DX
4117 DEBUG_BREAKPOINT_TEST();
4118 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4119 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4120 return vmsvga3dLogicOpsColorFill(pThisCC, idDXContext);
4121#else
4122 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4123 return VERR_NOT_SUPPORTED;
4124#endif
4125}
4126
4127
4128/* SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1263 */
4129static int vmsvga3dCmdLogicOpsAlphaBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsAlphaBlend const *pCmd, uint32_t cbCmd)
4130{
4131#ifdef VMSVGA3D_DX
4132 DEBUG_BREAKPOINT_TEST();
4133 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4134 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4135 return vmsvga3dLogicOpsAlphaBlend(pThisCC, idDXContext);
4136#else
4137 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4138 return VERR_NOT_SUPPORTED;
4139#endif
4140}
4141
4142
4143/* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1264 */
4144static int vmsvga3dCmdLogicOpsClearTypeBlend(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdLogicOpsClearTypeBlend const *pCmd, uint32_t cbCmd)
4145{
4146#ifdef VMSVGA3D_DX
4147 DEBUG_BREAKPOINT_TEST();
4148 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4149 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4150 return vmsvga3dLogicOpsClearTypeBlend(pThisCC, idDXContext);
4151#else
4152 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4153 return VERR_NOT_SUPPORTED;
4154#endif
4155}
4156
4157
4158/* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 1267 */
4159static int vmsvga3dCmdDefineGBSurface_v4(PVGASTATECC pThisCC, SVGA3dCmdDefineGBSurface_v4 const *pCmd)
4160{
4161#ifdef VMSVGA3D_DX
4162 //DEBUG_BREAKPOINT_TEST();
4163 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4164
4165 /* Update the entry in the pSvgaR3State->pGboOTableSurface. */
4166 SVGAOTableSurfaceEntry entry;
4167 RT_ZERO(entry);
4168 entry.format = pCmd->format;
4169 entry.surface1Flags = (uint32_t)(pCmd->surfaceFlags);
4170 entry.numMipLevels = pCmd->numMipLevels;
4171 entry.multisampleCount = pCmd->multisampleCount;
4172 entry.autogenFilter = pCmd->autogenFilter;
4173 entry.size = pCmd->size;
4174 entry.mobid = SVGA_ID_INVALID;
4175 entry.arraySize = pCmd->arraySize;
4176 // entry.mobPitch = 0;
4177 entry.surface2Flags = (uint32_t)(pCmd->surfaceFlags >> UINT64_C(32));
4178 entry.multisamplePattern = pCmd->multisamplePattern;
4179 entry.qualityLevel = pCmd->qualityLevel;
4180 entry.bufferByteStride = pCmd->bufferByteStride;
4181 // entry.minLOD = 0;
4182
4183 int rc = vmsvgaR3OTableWrite(pSvgaR3State, &pSvgaR3State->aGboOTables[SVGA_OTABLE_SURFACE],
4184 pCmd->sid, SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, &entry, sizeof(entry));
4185 if (RT_SUCCESS(rc))
4186 {
4187 /* Create the host surface. */
4188 vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format,
4189 pCmd->multisampleCount, pCmd->multisamplePattern, pCmd->qualityLevel, pCmd->autogenFilter,
4190 pCmd->numMipLevels, &pCmd->size, pCmd->arraySize, pCmd->bufferByteStride, /* fAllocMipLevels = */ false);
4191 }
4192 return rc;
4193#else
4194 RT_NOREF(pThisCC, pCmd);
4195 return VERR_NOT_SUPPORTED;
4196#endif
4197}
4198
4199
4200/* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS 1268 */
4201static int vmsvga3dCmdDXSetCSUAViews(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetCSUAViews const *pCmd, uint32_t cbCmd)
4202{
4203#ifdef VMSVGA3D_DX
4204 //DEBUG_BREAKPOINT_TEST();
4205 SVGA3dUAViewId const *paUAViewId = (SVGA3dUAViewId *)&pCmd[1];
4206 uint32_t const cUAViewId = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dUAViewId);
4207 return vmsvga3dDXSetCSUAViews(pThisCC, idDXContext, pCmd, cUAViewId, paUAViewId);
4208#else
4209 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4210 return VERR_NOT_SUPPORTED;
4211#endif
4212}
4213
4214
4215/* SVGA_3D_CMD_DX_SET_MIN_LOD 1269 */
4216static int vmsvga3dCmdDXSetMinLOD(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetMinLOD const *pCmd, uint32_t cbCmd)
4217{
4218#ifdef VMSVGA3D_DX
4219 DEBUG_BREAKPOINT_TEST();
4220 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4221 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4222 return vmsvga3dDXSetMinLOD(pThisCC, idDXContext);
4223#else
4224 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4225 return VERR_NOT_SUPPORTED;
4226#endif
4227}
4228
4229
4230/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 1272 */
4231static int vmsvga3dCmdDXDefineDepthStencilView_v2(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineDepthStencilView_v2 const *pCmd, uint32_t cbCmd)
4232{
4233#ifdef VMSVGA3D_DX
4234 //DEBUG_BREAKPOINT_TEST();
4235 RT_NOREF(cbCmd);
4236 return vmsvga3dDXDefineDepthStencilView(pThisCC, idDXContext, pCmd);
4237#else
4238 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4239 return VERR_NOT_SUPPORTED;
4240#endif
4241}
4242
4243
4244/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB 1273 */
4245static int vmsvga3dCmdDXDefineStreamOutputWithMob(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXDefineStreamOutputWithMob const *pCmd, uint32_t cbCmd)
4246{
4247#ifdef VMSVGA3D_DX
4248 //DEBUG_BREAKPOINT_TEST();
4249 RT_NOREF(cbCmd);
4250 return vmsvga3dDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd);
4251#else
4252 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4253 return VERR_NOT_SUPPORTED;
4254#endif
4255}
4256
4257
4258/* SVGA_3D_CMD_DX_SET_SHADER_IFACE 1274 */
4259static int vmsvga3dCmdDXSetShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXSetShaderIface const *pCmd, uint32_t cbCmd)
4260{
4261#ifdef VMSVGA3D_DX
4262 DEBUG_BREAKPOINT_TEST();
4263 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4264 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4265 return vmsvga3dDXSetShaderIface(pThisCC, idDXContext);
4266#else
4267 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4268 return VERR_NOT_SUPPORTED;
4269#endif
4270}
4271
4272
4273/* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT 1275 */
4274static int vmsvga3dCmdDXBindStreamOutput(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindStreamOutput const *pCmd, uint32_t cbCmd)
4275{
4276#ifdef VMSVGA3D_DX
4277 //DEBUG_BREAKPOINT_TEST();
4278 RT_NOREF(cbCmd);
4279 return vmsvga3dDXBindStreamOutput(pThisCC, idDXContext, pCmd);
4280#else
4281 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4282 return VERR_NOT_SUPPORTED;
4283#endif
4284}
4285
4286
4287/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS 1276 */
4288static int vmsvga3dCmdSurfaceStretchBltNonMSToMS(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdSurfaceStretchBltNonMSToMS const *pCmd, uint32_t cbCmd)
4289{
4290#ifdef VMSVGA3D_DX
4291 DEBUG_BREAKPOINT_TEST();
4292 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4293 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4294 return vmsvga3dSurfaceStretchBltNonMSToMS(pThisCC, idDXContext);
4295#else
4296 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4297 return VERR_NOT_SUPPORTED;
4298#endif
4299}
4300
4301
4302/* SVGA_3D_CMD_DX_BIND_SHADER_IFACE 1277 */
4303static int vmsvga3dCmdDXBindShaderIface(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdDXBindShaderIface const *pCmd, uint32_t cbCmd)
4304{
4305#ifdef VMSVGA3D_DX
4306 DEBUG_BREAKPOINT_TEST();
4307 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
4308 RT_NOREF(pSvgaR3State, pCmd, cbCmd);
4309 return vmsvga3dDXBindShaderIface(pThisCC, idDXContext);
4310#else
4311 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4312 return VERR_NOT_SUPPORTED;
4313#endif
4314}
4315
4316
4317/* SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION 1083 */
4318static int vmsvga3dCmdVBDXClearRenderTargetViewRegion(PVGASTATECC pThisCC, uint32_t idDXContext, SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd, uint32_t cbCmd)
4319{
4320#ifdef VMSVGA3D_DX
4321 //DEBUG_BREAKPOINT_TEST();
4322 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4323 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4324 return vmsvga3dVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cRect, paRect);
4325#else
4326 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4327 return VERR_NOT_SUPPORTED;
4328#endif
4329}
4330
4331
4332/* VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR VBSVGA_3D_CMD_BASE + 0 */
4333static int vmsvga3dVBCmdDXDefineVideoProcessor(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoProcessor *pCmd, uint32_t cbCmd)
4334{
4335#ifdef VMSVGA3D_DX
4336 //DEBUG_BREAKPOINT_TEST();
4337 RT_NOREF(cbCmd);
4338 return vmsvga3dVBDXDefineVideoProcessor(pThisCC, idDXContext, pCmd);
4339#else
4340 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4341 return VERR_NOT_SUPPORTED;
4342#endif
4343}
4344
4345
4346/* VBSVGA_3D_CMD_DX_DEFINE_VIDEO_DECODER_OUTPUT_VIEW VBSVGA_3D_CMD_BASE + 1 */
4347static int vmsvga3dVBCmdDXDefineVideoDecoderOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoDecoderOutputView *pCmd, uint32_t cbCmd)
4348{
4349#ifdef VMSVGA3D_DX
4350 //DEBUG_BREAKPOINT_TEST();
4351 RT_NOREF(cbCmd);
4352 return vmsvga3dVBDXDefineVideoDecoderOutputView(pThisCC, idDXContext, pCmd);
4353#else
4354 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4355 return VERR_NOT_SUPPORTED;
4356#endif
4357}
4358
4359
4360/* VBSVGA_3D_CMD_DX_DEFINE_VIDEO_DECODER VBSVGA_3D_CMD_BASE + 2 */
4361static int vmsvga3dVBCmdDXDefineVideoDecoder(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoDecoder *pCmd, uint32_t cbCmd)
4362{
4363#ifdef VMSVGA3D_DX
4364 //DEBUG_BREAKPOINT_TEST();
4365 RT_NOREF(cbCmd);
4366 return vmsvga3dVBDXDefineVideoDecoder(pThisCC, idDXContext, pCmd);
4367#else
4368 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4369 return VERR_NOT_SUPPORTED;
4370#endif
4371}
4372
4373
4374/* VBSVGA_3D_CMD_DX_VIDEO_DECODER_BEGIN_FRAME VBSVGA_3D_CMD_BASE + 3 */
4375static int vmsvga3dVBCmdDXVideoDecoderBeginFrame(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoDecoderBeginFrame *pCmd, uint32_t cbCmd)
4376{
4377#ifdef VMSVGA3D_DX
4378 //DEBUG_BREAKPOINT_TEST();
4379 RT_NOREF(cbCmd);
4380 return vmsvga3dVBDXVideoDecoderBeginFrame(pThisCC, idDXContext, pCmd);
4381#else
4382 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4383 return VERR_NOT_SUPPORTED;
4384#endif
4385}
4386
4387
4388/* VBSVGA_3D_CMD_DX_VIDEO_DECODER_SUBMIT_BUFFERS VBSVGA_3D_CMD_BASE + 4 */
4389static int vmsvga3dVBCmdDXVideoDecoderSubmitBuffers(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoDecoderSubmitBuffers *pCmd, uint32_t cbCmd)
4390{
4391#ifdef VMSVGA3D_DX
4392 //DEBUG_BREAKPOINT_TEST();
4393 VBSVGA3dVideoDecoderBufferDesc const *paBufferDesc = (VBSVGA3dVideoDecoderBufferDesc *)&pCmd[1];
4394 uint32_t const cBuffer = (cbCmd - sizeof(*pCmd)) / sizeof(VBSVGA3dVideoDecoderBufferDesc);
4395 return vmsvga3dVBDXVideoDecoderSubmitBuffers(pThisCC, idDXContext, pCmd, cBuffer, paBufferDesc);
4396#else
4397 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4398 return VERR_NOT_SUPPORTED;
4399#endif
4400}
4401
4402
4403/* VBSVGA_3D_CMD_DX_VIDEO_DECODER_END_FRAME VBSVGA_3D_CMD_BASE + 5 */
4404static int vmsvga3dVBCmdDXVideoDecoderEndFrame(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoDecoderEndFrame *pCmd, uint32_t cbCmd)
4405{
4406#ifdef VMSVGA3D_DX
4407 //DEBUG_BREAKPOINT_TEST();
4408 RT_NOREF(cbCmd);
4409 return vmsvga3dVBDXVideoDecoderEndFrame(pThisCC, idDXContext, pCmd);
4410#else
4411 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4412 return VERR_NOT_SUPPORTED;
4413#endif
4414}
4415
4416
4417/* VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR_INPUT_VIEW VBSVGA_3D_CMD_BASE + 6 */
4418static int vmsvga3dVBCmdDXDefineVideoProcessorInputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoProcessorInputView *pCmd, uint32_t cbCmd)
4419{
4420#ifdef VMSVGA3D_DX
4421 //DEBUG_BREAKPOINT_TEST();
4422 RT_NOREF(cbCmd);
4423 return vmsvga3dVBDXDefineVideoProcessorInputView(pThisCC, idDXContext, pCmd);
4424#else
4425 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4426 return VERR_NOT_SUPPORTED;
4427#endif
4428}
4429
4430
4431/* VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR_OUTPUT_VIEW VBSVGA_3D_CMD_BASE + 7 */
4432static int vmsvga3dVBCmdDXDefineVideoProcessorOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDefineVideoProcessorOutputView *pCmd, uint32_t cbCmd)
4433{
4434#ifdef VMSVGA3D_DX
4435 //DEBUG_BREAKPOINT_TEST();
4436 RT_NOREF(cbCmd);
4437 return vmsvga3dVBDXDefineVideoProcessorOutputView(pThisCC, idDXContext, pCmd);
4438#else
4439 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4440 return VERR_NOT_SUPPORTED;
4441#endif
4442}
4443
4444
4445/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_BLT VBSVGA_3D_CMD_BASE + 8 */
4446static int vmsvga3dVBCmdDXVideoProcessorBlt(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorBlt *pCmd, uint32_t cbCmd)
4447{
4448#ifdef VMSVGA3D_DX
4449 //DEBUG_BREAKPOINT_TEST();
4450 return vmsvga3dVBDXVideoProcessorBlt(pThisCC, idDXContext, pCmd, cbCmd);
4451#else
4452 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4453 return VERR_NOT_SUPPORTED;
4454#endif
4455}
4456
4457
4458/* VBSVGA_3D_CMD_DX_DESTROY_VIDEO_DECODER VBSVGA_3D_CMD_BASE + 9 */
4459static int vmsvga3dVBCmdDXDestroyVideoDecoder(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoDecoder *pCmd, uint32_t cbCmd)
4460{
4461#ifdef VMSVGA3D_DX
4462 //DEBUG_BREAKPOINT_TEST();
4463 RT_NOREF(cbCmd);
4464 return vmsvga3dVBDXDestroyVideoDecoder(pThisCC, idDXContext, pCmd);
4465#else
4466 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4467 return VERR_NOT_SUPPORTED;
4468#endif
4469}
4470
4471
4472/* VBSVGA_3D_CMD_DX_DESTROY_VIDEO_DECODER_OUTPUT_VIEW VBSVGA_3D_CMD_BASE + 10 */
4473static int vmsvga3dVBCmdDXDestroyVideoDecoderOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoDecoderOutputView *pCmd, uint32_t cbCmd)
4474{
4475#ifdef VMSVGA3D_DX
4476 //DEBUG_BREAKPOINT_TEST();
4477 RT_NOREF(cbCmd);
4478 return vmsvga3dVBDXDestroyVideoDecoderOutputView(pThisCC, idDXContext, pCmd);
4479#else
4480 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4481 return VERR_NOT_SUPPORTED;
4482#endif
4483}
4484
4485
4486/* VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR VBSVGA_3D_CMD_BASE + 11 */
4487static int vmsvga3dVBCmdDXDestroyVideoProcessor(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoProcessor *pCmd, uint32_t cbCmd)
4488{
4489#ifdef VMSVGA3D_DX
4490 //DEBUG_BREAKPOINT_TEST();
4491 RT_NOREF(cbCmd);
4492 return vmsvga3dVBDXDestroyVideoProcessor(pThisCC, idDXContext, pCmd);
4493#else
4494 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4495 return VERR_NOT_SUPPORTED;
4496#endif
4497}
4498
4499
4500/* VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR_INPUT_VIEW VBSVGA_3D_CMD_BASE + 12 */
4501static int vmsvga3dVBCmdDXDestroyVideoProcessorInputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoProcessorInputView *pCmd, uint32_t cbCmd)
4502{
4503#ifdef VMSVGA3D_DX
4504 //DEBUG_BREAKPOINT_TEST();
4505 RT_NOREF(cbCmd);
4506 return vmsvga3dVBDXDestroyVideoProcessorInputView(pThisCC, idDXContext, pCmd);
4507#else
4508 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4509 return VERR_NOT_SUPPORTED;
4510#endif
4511}
4512
4513
4514/* VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR_OUTPUT_VIEW VBSVGA_3D_CMD_BASE + 13 */
4515static int vmsvga3dVBCmdDXDestroyVideoProcessorOutputView(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXDestroyVideoProcessorOutputView *pCmd, uint32_t cbCmd)
4516{
4517#ifdef VMSVGA3D_DX
4518 //DEBUG_BREAKPOINT_TEST();
4519 RT_NOREF(cbCmd);
4520 return vmsvga3dVBDXDestroyVideoProcessorOutputView(pThisCC, idDXContext, pCmd);
4521#else
4522 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4523 return VERR_NOT_SUPPORTED;
4524#endif
4525}
4526
4527
4528/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_TARGET_RECT VBSVGA_3D_CMD_BASE + 14 */
4529static int vmsvga3dVBCmdDXVideoProcessorSetOutputTargetRect(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputTargetRect const *pCmd, uint32_t cbCmd)
4530{
4531#ifdef VMSVGA3D_DX
4532 //DEBUG_BREAKPOINT_TEST();
4533 RT_NOREF(cbCmd);
4534 return vmsvga3dVBDXVideoProcessorSetOutputTargetRect(pThisCC, idDXContext, pCmd);
4535#else
4536 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4537 return VERR_NOT_SUPPORTED;
4538#endif
4539}
4540
4541
4542/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_BACKGROUND_COLOR VBSVGA_3D_CMD_BASE + 15 */
4543static int vmsvga3dVBCmdDXVideoProcessorSetOutputBackgroundColor(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputBackgroundColor const *pCmd, uint32_t cbCmd)
4544{
4545#ifdef VMSVGA3D_DX
4546 //DEBUG_BREAKPOINT_TEST();
4547 RT_NOREF(cbCmd);
4548 return vmsvga3dVBDXVideoProcessorSetOutputBackgroundColor(pThisCC, idDXContext, pCmd);
4549#else
4550 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4551 return VERR_NOT_SUPPORTED;
4552#endif
4553}
4554
4555
4556/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_COLOR_SPACE VBSVGA_3D_CMD_BASE + 16 */
4557static int vmsvga3dVBCmdDXVideoProcessorSetOutputColorSpace(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputColorSpace const *pCmd, uint32_t cbCmd)
4558{
4559#ifdef VMSVGA3D_DX
4560 //DEBUG_BREAKPOINT_TEST();
4561 RT_NOREF(cbCmd);
4562 return vmsvga3dVBDXVideoProcessorSetOutputColorSpace(pThisCC, idDXContext, pCmd);
4563#else
4564 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4565 return VERR_NOT_SUPPORTED;
4566#endif
4567}
4568
4569
4570/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_ALPHA_FILL_MODE VBSVGA_3D_CMD_BASE + 17 */
4571static int vmsvga3dVBCmdDXVideoProcessorSetOutputAlphaFillMode(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputAlphaFillMode const *pCmd, uint32_t cbCmd)
4572{
4573#ifdef VMSVGA3D_DX
4574 //DEBUG_BREAKPOINT_TEST();
4575 RT_NOREF(cbCmd);
4576 return vmsvga3dVBDXVideoProcessorSetOutputAlphaFillMode(pThisCC, idDXContext, pCmd);
4577#else
4578 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4579 return VERR_NOT_SUPPORTED;
4580#endif
4581}
4582
4583
4584/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_CONSTRICTION VBSVGA_3D_CMD_BASE + 18 */
4585static int vmsvga3dVBCmdDXVideoProcessorSetOutputConstriction(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputConstriction const *pCmd, uint32_t cbCmd)
4586{
4587#ifdef VMSVGA3D_DX
4588 //DEBUG_BREAKPOINT_TEST();
4589 RT_NOREF(cbCmd);
4590 return vmsvga3dVBDXVideoProcessorSetOutputConstriction(pThisCC, idDXContext, pCmd);
4591#else
4592 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4593 return VERR_NOT_SUPPORTED;
4594#endif
4595}
4596
4597
4598/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_STEREO_MODE VBSVGA_3D_CMD_BASE + 19 */
4599static int vmsvga3dVBCmdDXVideoProcessorSetOutputStereoMode(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetOutputStereoMode const *pCmd, uint32_t cbCmd)
4600{
4601#ifdef VMSVGA3D_DX
4602 //DEBUG_BREAKPOINT_TEST();
4603 RT_NOREF(cbCmd);
4604 return vmsvga3dVBDXVideoProcessorSetOutputStereoMode(pThisCC, idDXContext, pCmd);
4605#else
4606 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4607 return VERR_NOT_SUPPORTED;
4608#endif
4609}
4610
4611
4612/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_FRAME_FORMAT VBSVGA_3D_CMD_BASE + 20 */
4613static int vmsvga3dVBCmdDXVideoProcessorSetStreamFrameFormat(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamFrameFormat const *pCmd, uint32_t cbCmd)
4614{
4615#ifdef VMSVGA3D_DX
4616 //DEBUG_BREAKPOINT_TEST();
4617 RT_NOREF(cbCmd);
4618 return vmsvga3dVBDXVideoProcessorSetStreamFrameFormat(pThisCC, idDXContext, pCmd);
4619#else
4620 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4621 return VERR_NOT_SUPPORTED;
4622#endif
4623}
4624
4625
4626/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_COLOR_SPACE VBSVGA_3D_CMD_BASE + 21 */
4627static int vmsvga3dVBCmdDXVideoProcessorSetStreamColorSpace(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamColorSpace const *pCmd, uint32_t cbCmd)
4628{
4629#ifdef VMSVGA3D_DX
4630 //DEBUG_BREAKPOINT_TEST();
4631 RT_NOREF(cbCmd);
4632 return vmsvga3dVBDXVideoProcessorSetStreamColorSpace(pThisCC, idDXContext, pCmd);
4633#else
4634 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4635 return VERR_NOT_SUPPORTED;
4636#endif
4637}
4638
4639
4640/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_OUTPUT_RATE VBSVGA_3D_CMD_BASE + 22 */
4641static int vmsvga3dVBCmdDXVideoProcessorSetStreamOutputRate(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamOutputRate const *pCmd, uint32_t cbCmd)
4642{
4643#ifdef VMSVGA3D_DX
4644 //DEBUG_BREAKPOINT_TEST();
4645 RT_NOREF(cbCmd);
4646 return vmsvga3dVBDXVideoProcessorSetStreamOutputRate(pThisCC, idDXContext, pCmd);
4647#else
4648 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4649 return VERR_NOT_SUPPORTED;
4650#endif
4651}
4652
4653
4654/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_SOURCE_RECT VBSVGA_3D_CMD_BASE + 23 */
4655static int vmsvga3dVBCmdDXVideoProcessorSetStreamSourceRect(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamSourceRect const *pCmd, uint32_t cbCmd)
4656{
4657#ifdef VMSVGA3D_DX
4658 //DEBUG_BREAKPOINT_TEST();
4659 RT_NOREF(cbCmd);
4660 return vmsvga3dVBDXVideoProcessorSetStreamSourceRect(pThisCC, idDXContext, pCmd);
4661#else
4662 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4663 return VERR_NOT_SUPPORTED;
4664#endif
4665}
4666
4667
4668/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_DEST_RECT VBSVGA_3D_CMD_BASE + 24 */
4669static int vmsvga3dVBCmdDXVideoProcessorSetStreamDestRect(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamDestRect const *pCmd, uint32_t cbCmd)
4670{
4671#ifdef VMSVGA3D_DX
4672 //DEBUG_BREAKPOINT_TEST();
4673 RT_NOREF(cbCmd);
4674 return vmsvga3dVBDXVideoProcessorSetStreamDestRect(pThisCC, idDXContext, pCmd);
4675#else
4676 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4677 return VERR_NOT_SUPPORTED;
4678#endif
4679}
4680
4681
4682/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_ALPHA VBSVGA_3D_CMD_BASE + 25 */
4683static int vmsvga3dVBCmdDXVideoProcessorSetStreamAlpha(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamAlpha const *pCmd, uint32_t cbCmd)
4684{
4685#ifdef VMSVGA3D_DX
4686 //DEBUG_BREAKPOINT_TEST();
4687 RT_NOREF(cbCmd);
4688 return vmsvga3dVBDXVideoProcessorSetStreamAlpha(pThisCC, idDXContext, pCmd);
4689#else
4690 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4691 return VERR_NOT_SUPPORTED;
4692#endif
4693}
4694
4695
4696/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_PALETTE VBSVGA_3D_CMD_BASE + 26, */
4697static int vmsvga3dVBCmdDXVideoProcessorSetStreamPalette(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamPalette const *pCmd, uint32_t cbCmd)
4698{
4699#ifdef VMSVGA3D_DX
4700 //DEBUG_BREAKPOINT_TEST();
4701 uint32_t const *paEntries = (uint32_t *)&pCmd[1];
4702 uint32_t const cEntries = (cbCmd - sizeof(*pCmd)) / sizeof(uint32_t);
4703 return vmsvga3dVBDXVideoProcessorSetStreamPalette(pThisCC, idDXContext, pCmd, cEntries, paEntries);
4704#else
4705 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4706 return VERR_NOT_SUPPORTED;
4707#endif
4708}
4709
4710
4711/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_PIXEL_ASPECT_RATIO VBSVGA_3D_CMD_BASE + 27 */
4712static int vmsvga3dVBCmdDXVideoProcessorSetStreamPixelAspectRatio(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamPixelAspectRatio const *pCmd, uint32_t cbCmd)
4713{
4714#ifdef VMSVGA3D_DX
4715 //DEBUG_BREAKPOINT_TEST();
4716 RT_NOREF(cbCmd);
4717 return vmsvga3dVBDXVideoProcessorSetStreamPixelAspectRatio(pThisCC, idDXContext, pCmd);
4718#else
4719 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4720 return VERR_NOT_SUPPORTED;
4721#endif
4722}
4723
4724
4725/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_LUMA_KEY VBSVGA_3D_CMD_BASE + 28 */
4726static int vmsvga3dVBCmdDXVideoProcessorSetStreamLumaKey(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamLumaKey const *pCmd, uint32_t cbCmd)
4727{
4728#ifdef VMSVGA3D_DX
4729 //DEBUG_BREAKPOINT_TEST();
4730 RT_NOREF(cbCmd);
4731 return vmsvga3dVBDXVideoProcessorSetStreamLumaKey(pThisCC, idDXContext, pCmd);
4732#else
4733 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4734 return VERR_NOT_SUPPORTED;
4735#endif
4736}
4737
4738
4739/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_STEREO_FORMAT VBSVGA_3D_CMD_BASE + 29 */
4740static int vmsvga3dVBCmdDXVideoProcessorSetStreamStereoFormat(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamStereoFormat const *pCmd, uint32_t cbCmd)
4741{
4742#ifdef VMSVGA3D_DX
4743 //DEBUG_BREAKPOINT_TEST();
4744 RT_NOREF(cbCmd);
4745 return vmsvga3dVBDXVideoProcessorSetStreamStereoFormat(pThisCC, idDXContext, pCmd);
4746#else
4747 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4748 return VERR_NOT_SUPPORTED;
4749#endif
4750}
4751
4752
4753/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_AUTO_PROCESSING_MODE VBSVGA_3D_CMD_BASE + 30 */
4754static int vmsvga3dVBCmdDXVideoProcessorSetStreamAutoProcessingMode(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamAutoProcessingMode const *pCmd, uint32_t cbCmd)
4755{
4756#ifdef VMSVGA3D_DX
4757 //DEBUG_BREAKPOINT_TEST();
4758 RT_NOREF(cbCmd);
4759 return vmsvga3dVBDXVideoProcessorSetStreamAutoProcessingMode(pThisCC, idDXContext, pCmd);
4760#else
4761 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4762 return VERR_NOT_SUPPORTED;
4763#endif
4764}
4765
4766
4767/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_FILTER VBSVGA_3D_CMD_BASE + 31 */
4768static int vmsvga3dVBCmdDXVideoProcessorSetStreamFilter(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamFilter const *pCmd, uint32_t cbCmd)
4769{
4770#ifdef VMSVGA3D_DX
4771 //DEBUG_BREAKPOINT_TEST();
4772 RT_NOREF(cbCmd);
4773 return vmsvga3dVBDXVideoProcessorSetStreamFilter(pThisCC, idDXContext, pCmd);
4774#else
4775 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4776 return VERR_NOT_SUPPORTED;
4777#endif
4778}
4779
4780
4781/* VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_ROTATION VBSVGA_3D_CMD_BASE + 32 */
4782static int vmsvga3dVBCmdDXVideoProcessorSetStreamRotation(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXVideoProcessorSetStreamRotation const *pCmd, uint32_t cbCmd)
4783{
4784#ifdef VMSVGA3D_DX
4785 //DEBUG_BREAKPOINT_TEST();
4786 RT_NOREF(cbCmd);
4787 return vmsvga3dVBDXVideoProcessorSetStreamRotation(pThisCC, idDXContext, pCmd);
4788#else
4789 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4790 return VERR_NOT_SUPPORTED;
4791#endif
4792}
4793
4794
4795/* VBSVGA_3D_CMD_DX_GET_VIDEO_CAPABILITY VBSVGA_3D_CMD_BASE + 33 */
4796static int vmsvga3dVBCmdDXGetVideoCapability(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXGetVideoCapability const *pCmd, uint32_t cbCmd)
4797{
4798#ifdef VMSVGA3D_DX
4799 //DEBUG_BREAKPOINT_TEST();
4800 RT_NOREF(cbCmd);
4801 return vmsvga3dVBDXGetVideoCapability(pThisCC, idDXContext, pCmd);
4802#else
4803 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4804 return VERR_NOT_SUPPORTED;
4805#endif
4806}
4807
4808
4809/* VBSVGA_3D_CMD_DX_CLEAR_RTV VBSVGA_3D_CMD_BASE + 34 */
4810static int vmsvga3dVBCmdDXClearRTV(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXClearView *pCmd, uint32_t cbCmd)
4811{
4812#ifdef VMSVGA3D_DX
4813 //DEBUG_BREAKPOINT_TEST();
4814 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4815 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4816 return vmsvga3dVBDXClearRTV(pThisCC, idDXContext, pCmd, cRect, cRect ? paRect : NULL);
4817#else
4818 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4819 return VERR_NOT_SUPPORTED;
4820#endif
4821}
4822
4823
4824/* VBSVGA_3D_CMD_DX_CLEAR_UAV VBSVGA_3D_CMD_BASE + 35 */
4825static int vmsvga3dVBCmdDXClearUAV(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXClearView *pCmd, uint32_t cbCmd)
4826{
4827#ifdef VMSVGA3D_DX
4828 //DEBUG_BREAKPOINT_TEST();
4829 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4830 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4831 return vmsvga3dVBDXClearUAV(pThisCC, idDXContext, pCmd, cRect, cRect ? paRect : NULL);
4832#else
4833 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4834 return VERR_NOT_SUPPORTED;
4835#endif
4836}
4837
4838
4839/* VBSVGA_3D_CMD_DX_CLEAR_VDOV VBSVGA_3D_CMD_BASE + 36 */
4840static int vmsvga3dVBCmdDXClearVDOV(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXClearView *pCmd, uint32_t cbCmd)
4841{
4842#ifdef VMSVGA3D_DX
4843 //DEBUG_BREAKPOINT_TEST();
4844 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4845 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4846 return vmsvga3dVBDXClearVDOV(pThisCC, idDXContext, pCmd, cRect, cRect ? paRect : NULL);
4847#else
4848 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4849 return VERR_NOT_SUPPORTED;
4850#endif
4851}
4852
4853
4854/* VBSVGA_3D_CMD_DX_CLEAR_VPIV VBSVGA_3D_CMD_BASE + 37 */
4855static int vmsvga3dVBCmdDXClearVPIV(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXClearView *pCmd, uint32_t cbCmd)
4856{
4857#ifdef VMSVGA3D_DX
4858 //DEBUG_BREAKPOINT_TEST();
4859 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4860 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4861 return vmsvga3dVBDXClearVPIV(pThisCC, idDXContext, pCmd, cRect, cRect ? paRect : NULL);
4862#else
4863 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4864 return VERR_NOT_SUPPORTED;
4865#endif
4866}
4867
4868
4869/* VBSVGA_3D_CMD_DX_CLEAR_VPOV VBSVGA_3D_CMD_BASE + 38 */
4870static int vmsvga3dVBCmdDXClearVPOV(PVGASTATECC pThisCC, uint32_t idDXContext, VBSVGA3dCmdDXClearView *pCmd, uint32_t cbCmd)
4871{
4872#ifdef VMSVGA3D_DX
4873 //DEBUG_BREAKPOINT_TEST();
4874 SVGASignedRect const *paRect = (SVGASignedRect *)&pCmd[1];
4875 uint32_t const cRect = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4876 return vmsvga3dVBDXClearVPOV(pThisCC, idDXContext, pCmd, cRect, cRect ? paRect : NULL);
4877#else
4878 RT_NOREF(pThisCC, idDXContext, pCmd, cbCmd);
4879 return VERR_NOT_SUPPORTED;
4880#endif
4881}
4882
4883
4884/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4885 * Check that the 3D command has at least a_cbMin of payload bytes after the
4886 * header. Will break out of the switch if it doesn't.
4887 */
4888# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4889 if (1) { \
4890 AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4891 RT_UNTRUSTED_VALIDATED_FENCE(); \
4892 } else do {} while (0)
4893
4894# define VMSVGA_3D_CMD_NOTIMPL() \
4895 if (1) { \
4896 AssertMsgFailed(("Not implemented %d %s\n", enmCmdId, vmsvgaR3FifoCmdToString(enmCmdId))); \
4897 } else do {} while (0)
4898
4899/** SVGA_3D_CMD_* handler.
4900 * This function parses the command and calls the corresponding command handler.
4901 *
4902 * @param pThis The shared VGA/VMSVGA state.
4903 * @param pThisCC The VGA/VMSVGA state for the current context.
4904 * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
4905 * @param enmCmdId SVGA_3D_CMD_* command identifier.
4906 * @param cbCmd Size of the command in bytes.
4907 * @param pvCmd Pointer to the command.
4908 * @returns VBox status code if an error was detected parsing a command.
4909 */
4910int vmsvgaR3Process3dCmd(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, SVGAFifo3dCmdId enmCmdId, uint32_t cbCmd, void const *pvCmd)
4911{
4912 int rcParse = VINF_SUCCESS;
4913 PVMSVGAR3STATE pSvgaR3State = pThisCC->svga.pSvgaR3State;
4914
4915 switch (enmCmdId)
4916 {
4917 case SVGA_3D_CMD_SURFACE_DEFINE:
4918 {
4919 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)pvCmd;
4920 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4921 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefine);
4922
4923 SVGA3dCmdDefineSurface_v2 cmd;
4924 cmd.sid = pCmd->sid;
4925 cmd.surfaceFlags = pCmd->surfaceFlags;
4926 cmd.format = pCmd->format;
4927 memcpy(cmd.face, pCmd->face, sizeof(cmd.face));
4928 cmd.multisampleCount = 0;
4929 cmd.autogenFilter = SVGA3D_TEX_FILTER_NONE;
4930
4931 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4932 vmsvga3dCmdDefineSurface(pThisCC, &cmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4933# ifdef DEBUG_GMR_ACCESS
4934 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4935# endif
4936 break;
4937 }
4938
4939 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4940 {
4941 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)pvCmd;
4942 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4943 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDefineV2);
4944
4945 uint32_t const cMipLevelSizes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4946 vmsvga3dCmdDefineSurface(pThisCC, pCmd, cMipLevelSizes, (SVGA3dSize *)(pCmd + 1));
4947# ifdef DEBUG_GMR_ACCESS
4948 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4949# endif
4950 break;
4951 }
4952
4953 case SVGA_3D_CMD_SURFACE_DESTROY:
4954 {
4955 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)pvCmd;
4956 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4957 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDestroy);
4958
4959 vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4960 break;
4961 }
4962
4963 case SVGA_3D_CMD_SURFACE_COPY:
4964 {
4965 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)pvCmd;
4966 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4967 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceCopy);
4968
4969 uint32_t const cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4970 vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4971 break;
4972 }
4973
4974 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4975 {
4976 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)pvCmd;
4977 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4978 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceStretchBlt);
4979
4980 vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4981 &pCmd->src, &pCmd->boxSrc, pCmd->mode);
4982 break;
4983 }
4984
4985 case SVGA_3D_CMD_SURFACE_DMA:
4986 {
4987 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)pvCmd;
4988 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4989 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceDma);
4990
4991 uint64_t u64NanoTS = 0;
4992 if (LogRelIs3Enabled())
4993 u64NanoTS = RTTimeNanoTS();
4994 uint32_t const cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4995 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4996 vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4997 cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4998 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dSurfaceDmaProf, a);
4999 if (LogRelIs3Enabled())
5000 {
5001 if (cCopyBoxes)
5002 {
5003 SVGA3dCopyBox *pFirstBox = (SVGA3dCopyBox *)(pCmd + 1);
5004 LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
5005 (RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
5006 pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
5007 pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
5008 }
5009 }
5010 break;
5011 }
5012
5013 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
5014 {
5015 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)pvCmd;
5016 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5017 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSurfaceScreen);
5018
5019 static uint64_t u64FrameStartNanoTS = 0;
5020 static uint64_t u64ElapsedPerSecNano = 0;
5021 static int cFrames = 0;
5022 uint64_t u64NanoTS = 0;
5023 if (LogRelIs3Enabled())
5024 u64NanoTS = RTTimeNanoTS();
5025 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
5026 STAM_REL_PROFILE_START(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
5027 vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
5028 pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
5029 STAM_REL_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dBlitSurfaceToScreenProf, a);
5030 if (LogRelIs3Enabled())
5031 {
5032 uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
5033 u64ElapsedPerSecNano += u64ElapsedNano;
5034
5035 SVGASignedRect *pFirstRect = cRects ? (SVGASignedRect *)(pCmd + 1) : &pCmd->destRect;
5036 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
5037 (u64ElapsedNano) / 1000ULL, cRects,
5038 pFirstRect->left, pFirstRect->top,
5039 pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
5040
5041 ++cFrames;
5042 if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
5043 {
5044 LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
5045 cFrames, u64ElapsedPerSecNano / 1000ULL));
5046 u64FrameStartNanoTS = u64NanoTS;
5047 cFrames = 0;
5048 u64ElapsedPerSecNano = 0;
5049 }
5050 }
5051 break;
5052 }
5053
5054 case SVGA_3D_CMD_CONTEXT_DEFINE:
5055 {
5056 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)pvCmd;
5057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5058 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDefine);
5059
5060 vmsvga3dContextDefine(pThisCC, pCmd->cid);
5061 break;
5062 }
5063
5064 case SVGA_3D_CMD_CONTEXT_DESTROY:
5065 {
5066 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)pvCmd;
5067 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5068 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dContextDestroy);
5069
5070 vmsvga3dContextDestroy(pThisCC, pCmd->cid);
5071 break;
5072 }
5073
5074 case SVGA_3D_CMD_SETTRANSFORM:
5075 {
5076 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)pvCmd;
5077 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5078 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTransform);
5079
5080 vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
5081 break;
5082 }
5083
5084 case SVGA_3D_CMD_SETZRANGE:
5085 {
5086 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)pvCmd;
5087 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5088 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetZRange);
5089
5090 vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
5091 break;
5092 }
5093
5094 case SVGA_3D_CMD_SETRENDERSTATE:
5095 {
5096 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)pvCmd;
5097 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5098 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderState);
5099
5100 uint32_t const cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
5101 vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
5102 break;
5103 }
5104
5105 case SVGA_3D_CMD_SETRENDERTARGET:
5106 {
5107 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)pvCmd;
5108 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5109 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetRenderTarget);
5110
5111 vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
5112 break;
5113 }
5114
5115 case SVGA_3D_CMD_SETTEXTURESTATE:
5116 {
5117 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)pvCmd;
5118 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5119 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetTextureState);
5120
5121 uint32_t const cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
5122 vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
5123 break;
5124 }
5125
5126 case SVGA_3D_CMD_SETMATERIAL:
5127 {
5128 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)pvCmd;
5129 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5130 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetMaterial);
5131
5132 vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
5133 break;
5134 }
5135
5136 case SVGA_3D_CMD_SETLIGHTDATA:
5137 {
5138 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)pvCmd;
5139 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5140 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightData);
5141
5142 vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
5143 break;
5144 }
5145
5146 case SVGA_3D_CMD_SETLIGHTENABLED:
5147 {
5148 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)pvCmd;
5149 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5150 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetLightEnable);
5151
5152 vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
5153 break;
5154 }
5155
5156 case SVGA_3D_CMD_SETVIEWPORT:
5157 {
5158 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)pvCmd;
5159 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5160 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetViewPort);
5161
5162 vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
5163 break;
5164 }
5165
5166 case SVGA_3D_CMD_SETCLIPPLANE:
5167 {
5168 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)pvCmd;
5169 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5170 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetClipPlane);
5171
5172 vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
5173 break;
5174 }
5175
5176 case SVGA_3D_CMD_CLEAR:
5177 {
5178 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)pvCmd;
5179 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5180 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dClear);
5181
5182 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
5183 vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
5184 break;
5185 }
5186
5187 case SVGA_3D_CMD_PRESENT:
5188 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
5189 {
5190 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)pvCmd;
5191 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5192 if (enmCmdId == SVGA_3D_CMD_PRESENT)
5193 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresent);
5194 else
5195 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dPresentReadBack);
5196
5197 uint32_t const cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
5198 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
5199 vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
5200 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dPresentProf, a);
5201 break;
5202 }
5203
5204 case SVGA_3D_CMD_SHADER_DEFINE:
5205 {
5206 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)pvCmd;
5207 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5208 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDefine);
5209
5210 uint32_t const cbData = (cbCmd - sizeof(*pCmd));
5211 vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
5212 break;
5213 }
5214
5215 case SVGA_3D_CMD_SHADER_DESTROY:
5216 {
5217 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)pvCmd;
5218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5219 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dShaderDestroy);
5220
5221 vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
5222 break;
5223 }
5224
5225 case SVGA_3D_CMD_SET_SHADER:
5226 {
5227 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)pvCmd;
5228 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5229 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShader);
5230
5231 vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
5232 break;
5233 }
5234
5235 case SVGA_3D_CMD_SET_SHADER_CONST:
5236 {
5237 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)pvCmd;
5238 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5239 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetShaderConst);
5240
5241 uint32_t const cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
5242 vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
5243 break;
5244 }
5245
5246 case SVGA_3D_CMD_DRAW_PRIMITIVES:
5247 {
5248 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)pvCmd;
5249 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5250 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDrawPrimitives);
5251
5252 ASSERT_GUEST_STMT_BREAK(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES, rcParse = VERR_INVALID_PARAMETER);
5253 ASSERT_GUEST_STMT_BREAK(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS, rcParse = VERR_INVALID_PARAMETER);
5254 uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
5255 + pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
5256 ASSERT_GUEST_STMT_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd), rcParse = VERR_INVALID_PARAMETER);
5257
5258 uint32_t const cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
5259 ASSERT_GUEST_STMT_BREAK(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls, rcParse = VERR_INVALID_PARAMETER);
5260 RT_UNTRUSTED_VALIDATED_FENCE();
5261
5262 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
5263 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *)&pVertexDecl[pCmd->numVertexDecls];
5264 SVGA3dVertexDivisor *pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor *)&pNumRange[pCmd->numRanges] : NULL;
5265
5266 STAM_PROFILE_START(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
5267 vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
5268 pNumRange, cVertexDivisor, pVertexDivisor);
5269 STAM_PROFILE_STOP(&pSvgaR3State->StatR3Cmd3dDrawPrimitivesProf, a);
5270 break;
5271 }
5272
5273 case SVGA_3D_CMD_SETSCISSORRECT:
5274 {
5275 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)pvCmd;
5276 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5277 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dSetScissorRect);
5278
5279 vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
5280 break;
5281 }
5282
5283 case SVGA_3D_CMD_BEGIN_QUERY:
5284 {
5285 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)pvCmd;
5286 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5287 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dBeginQuery);
5288
5289 vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
5290 break;
5291 }
5292
5293 case SVGA_3D_CMD_END_QUERY:
5294 {
5295 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)pvCmd;
5296 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5297 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dEndQuery);
5298
5299 vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type);
5300 break;
5301 }
5302
5303 case SVGA_3D_CMD_WAIT_FOR_QUERY:
5304 {
5305 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)pvCmd;
5306 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5307 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dWaitForQuery);
5308
5309 vmsvga3dQueryWait(pThisCC, pCmd->cid, pCmd->type, pThis, &pCmd->guestResult);
5310 break;
5311 }
5312
5313 case SVGA_3D_CMD_GENERATE_MIPMAPS:
5314 {
5315 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)pvCmd;
5316 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5317 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dGenerateMipmaps);
5318
5319 vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
5320 break;
5321 }
5322
5323 case SVGA_3D_CMD_ACTIVATE_SURFACE:
5324 /* context id + surface id? */
5325 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dActivateSurface);
5326 break;
5327
5328 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
5329 /* context id + surface id? */
5330 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3Cmd3dDeactivateSurface);
5331 break;
5332
5333 /*
5334 *
5335 * VPGU10: SVGA_CAP_GBOBJECTS+ commands.
5336 *
5337 */
5338 case SVGA_3D_CMD_SCREEN_DMA:
5339 {
5340 SVGA3dCmdScreenDMA *pCmd = (SVGA3dCmdScreenDMA *)pvCmd;
5341 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5342 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5343 break;
5344 }
5345
5346 /* case SVGA_3D_CMD_DEAD1: New SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION */
5347 case SVGA_3D_CMD_DEAD2:
5348 case SVGA_3D_CMD_DEAD12: /* Old SVGA_3D_CMD_LOGICOPS_BITBLT */
5349 case SVGA_3D_CMD_DEAD13: /* Old SVGA_3D_CMD_LOGICOPS_TRANSBLT */
5350 case SVGA_3D_CMD_DEAD14: /* Old SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
5351 case SVGA_3D_CMD_DEAD15: /* Old SVGA_3D_CMD_LOGICOPS_COLORFILL */
5352 case SVGA_3D_CMD_DEAD16: /* Old SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
5353 case SVGA_3D_CMD_DEAD17: /* Old SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
5354 {
5355 VMSVGA_3D_CMD_NOTIMPL();
5356 break;
5357 }
5358
5359 case SVGA_3D_CMD_SET_OTABLE_BASE:
5360 {
5361 SVGA3dCmdSetOTableBase *pCmd = (SVGA3dCmdSetOTableBase *)pvCmd;
5362 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5363 vmsvga3dCmdSetOTableBase(pThisCC, pCmd);
5364 break;
5365 }
5366
5367 case SVGA_3D_CMD_READBACK_OTABLE:
5368 {
5369 SVGA3dCmdReadbackOTable *pCmd = (SVGA3dCmdReadbackOTable *)pvCmd;
5370 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5371 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5372 break;
5373 }
5374
5375 case SVGA_3D_CMD_DEFINE_GB_MOB:
5376 {
5377 SVGA3dCmdDefineGBMob *pCmd = (SVGA3dCmdDefineGBMob *)pvCmd;
5378 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5379 vmsvga3dCmdDefineGBMob(pThisCC, pCmd);
5380 break;
5381 }
5382
5383 case SVGA_3D_CMD_DESTROY_GB_MOB:
5384 {
5385 SVGA3dCmdDestroyGBMob *pCmd = (SVGA3dCmdDestroyGBMob *)pvCmd;
5386 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5387 vmsvga3dCmdDestroyGBMob(pThisCC, pCmd);
5388 break;
5389 }
5390
5391 case SVGA_3D_CMD_DEAD3:
5392 {
5393 VMSVGA_3D_CMD_NOTIMPL();
5394 break;
5395 }
5396
5397 case SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING:
5398 {
5399 SVGA3dCmdUpdateGBMobMapping *pCmd = (SVGA3dCmdUpdateGBMobMapping *)pvCmd;
5400 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5401 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5402 break;
5403 }
5404
5405 case SVGA_3D_CMD_DEFINE_GB_SURFACE:
5406 {
5407 SVGA3dCmdDefineGBSurface *pCmd = (SVGA3dCmdDefineGBSurface *)pvCmd;
5408 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5409 vmsvga3dCmdDefineGBSurface(pThisCC, pCmd);
5410 break;
5411 }
5412
5413 case SVGA_3D_CMD_DESTROY_GB_SURFACE:
5414 {
5415 SVGA3dCmdDestroyGBSurface *pCmd = (SVGA3dCmdDestroyGBSurface *)pvCmd;
5416 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5417 vmsvga3dCmdDestroyGBSurface(pThisCC, pCmd);
5418 break;
5419 }
5420
5421 case SVGA_3D_CMD_BIND_GB_SURFACE:
5422 {
5423 SVGA3dCmdBindGBSurface *pCmd = (SVGA3dCmdBindGBSurface *)pvCmd;
5424 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5425 vmsvga3dCmdBindGBSurface(pThisCC, pCmd);
5426 break;
5427 }
5428
5429 case SVGA_3D_CMD_COND_BIND_GB_SURFACE:
5430 {
5431 SVGA3dCmdCondBindGBSurface *pCmd = (SVGA3dCmdCondBindGBSurface *)pvCmd;
5432 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5433 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5434 break;
5435 }
5436
5437 case SVGA_3D_CMD_UPDATE_GB_IMAGE:
5438 {
5439 SVGA3dCmdUpdateGBImage *pCmd = (SVGA3dCmdUpdateGBImage *)pvCmd;
5440 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5441 vmsvga3dCmdUpdateGBImage(pThisCC, pCmd);
5442 break;
5443 }
5444
5445 case SVGA_3D_CMD_UPDATE_GB_SURFACE:
5446 {
5447 SVGA3dCmdUpdateGBSurface *pCmd = (SVGA3dCmdUpdateGBSurface *)pvCmd;
5448 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5449 vmsvga3dCmdUpdateGBSurface(pThisCC, pCmd);
5450 break;
5451 }
5452
5453 case SVGA_3D_CMD_READBACK_GB_IMAGE:
5454 {
5455 SVGA3dCmdReadbackGBImage *pCmd = (SVGA3dCmdReadbackGBImage *)pvCmd;
5456 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5457 vmsvga3dCmdReadbackGBImage(pThisCC, pCmd);
5458 break;
5459 }
5460
5461 case SVGA_3D_CMD_READBACK_GB_SURFACE:
5462 {
5463 SVGA3dCmdReadbackGBSurface *pCmd = (SVGA3dCmdReadbackGBSurface *)pvCmd;
5464 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5465 vmsvga3dCmdReadbackGBSurface(pThisCC, pCmd);
5466 break;
5467 }
5468
5469 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE:
5470 {
5471 SVGA3dCmdInvalidateGBImage *pCmd = (SVGA3dCmdInvalidateGBImage *)pvCmd;
5472 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5473 vmsvga3dCmdInvalidateGBImage(pThisCC, pCmd);
5474 break;
5475 }
5476
5477 case SVGA_3D_CMD_INVALIDATE_GB_SURFACE:
5478 {
5479 SVGA3dCmdInvalidateGBSurface *pCmd = (SVGA3dCmdInvalidateGBSurface *)pvCmd;
5480 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5481 vmsvga3dCmdInvalidateGBSurface(pThisCC, pCmd);
5482 break;
5483 }
5484
5485 case SVGA_3D_CMD_DEFINE_GB_CONTEXT:
5486 {
5487 SVGA3dCmdDefineGBContext *pCmd = (SVGA3dCmdDefineGBContext *)pvCmd;
5488 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5489 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5490 break;
5491 }
5492
5493 case SVGA_3D_CMD_DESTROY_GB_CONTEXT:
5494 {
5495 SVGA3dCmdDestroyGBContext *pCmd = (SVGA3dCmdDestroyGBContext *)pvCmd;
5496 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5497 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5498 break;
5499 }
5500
5501 case SVGA_3D_CMD_BIND_GB_CONTEXT:
5502 {
5503 SVGA3dCmdBindGBContext *pCmd = (SVGA3dCmdBindGBContext *)pvCmd;
5504 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5505 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5506 break;
5507 }
5508
5509 case SVGA_3D_CMD_READBACK_GB_CONTEXT:
5510 {
5511 SVGA3dCmdReadbackGBContext *pCmd = (SVGA3dCmdReadbackGBContext *)pvCmd;
5512 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5513 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5514 break;
5515 }
5516
5517 case SVGA_3D_CMD_INVALIDATE_GB_CONTEXT:
5518 {
5519 SVGA3dCmdInvalidateGBContext *pCmd = (SVGA3dCmdInvalidateGBContext *)pvCmd;
5520 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5521 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5522 break;
5523 }
5524
5525 case SVGA_3D_CMD_DEFINE_GB_SHADER:
5526 {
5527 SVGA3dCmdDefineGBShader *pCmd = (SVGA3dCmdDefineGBShader *)pvCmd;
5528 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5529 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5530 break;
5531 }
5532
5533 case SVGA_3D_CMD_DESTROY_GB_SHADER:
5534 {
5535 SVGA3dCmdDestroyGBShader *pCmd = (SVGA3dCmdDestroyGBShader *)pvCmd;
5536 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5537 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5538 break;
5539 }
5540
5541 case SVGA_3D_CMD_BIND_GB_SHADER:
5542 {
5543 SVGA3dCmdBindGBShader *pCmd = (SVGA3dCmdBindGBShader *)pvCmd;
5544 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5545 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5546 break;
5547 }
5548
5549 case SVGA_3D_CMD_SET_OTABLE_BASE64:
5550 {
5551 SVGA3dCmdSetOTableBase64 *pCmd = (SVGA3dCmdSetOTableBase64 *)pvCmd;
5552 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5553 vmsvga3dCmdSetOTableBase64(pThisCC, pCmd);
5554 break;
5555 }
5556
5557 case SVGA_3D_CMD_BEGIN_GB_QUERY:
5558 {
5559 SVGA3dCmdBeginGBQuery *pCmd = (SVGA3dCmdBeginGBQuery *)pvCmd;
5560 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5561 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5562 break;
5563 }
5564
5565 case SVGA_3D_CMD_END_GB_QUERY:
5566 {
5567 SVGA3dCmdEndGBQuery *pCmd = (SVGA3dCmdEndGBQuery *)pvCmd;
5568 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5569 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5570 break;
5571 }
5572
5573 case SVGA_3D_CMD_WAIT_FOR_GB_QUERY:
5574 {
5575 SVGA3dCmdWaitForGBQuery *pCmd = (SVGA3dCmdWaitForGBQuery *)pvCmd;
5576 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5577 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5578 break;
5579 }
5580
5581 case SVGA_3D_CMD_NOP:
5582 {
5583 /* Apparently there is nothing to do. */
5584 break;
5585 }
5586
5587 case SVGA_3D_CMD_ENABLE_GART:
5588 {
5589 SVGA3dCmdEnableGart *pCmd = (SVGA3dCmdEnableGart *)pvCmd;
5590 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5591 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5592 break;
5593 }
5594
5595 case SVGA_3D_CMD_DISABLE_GART:
5596 {
5597 /* No corresponding SVGA3dCmd structure. */
5598 VMSVGA_3D_CMD_NOTIMPL();
5599 break;
5600 }
5601
5602 case SVGA_3D_CMD_MAP_MOB_INTO_GART:
5603 {
5604 SVGA3dCmdMapMobIntoGart *pCmd = (SVGA3dCmdMapMobIntoGart *)pvCmd;
5605 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5606 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5607 break;
5608 }
5609
5610 case SVGA_3D_CMD_UNMAP_GART_RANGE:
5611 {
5612 SVGA3dCmdUnmapGartRange *pCmd = (SVGA3dCmdUnmapGartRange *)pvCmd;
5613 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5614 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5615 break;
5616 }
5617
5618 case SVGA_3D_CMD_DEFINE_GB_SCREENTARGET:
5619 {
5620 SVGA3dCmdDefineGBScreenTarget *pCmd = (SVGA3dCmdDefineGBScreenTarget *)pvCmd;
5621 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5622 vmsvga3dCmdDefineGBScreenTarget(pThis, pThisCC, pCmd);
5623 break;
5624 }
5625
5626 case SVGA_3D_CMD_DESTROY_GB_SCREENTARGET:
5627 {
5628 SVGA3dCmdDestroyGBScreenTarget *pCmd = (SVGA3dCmdDestroyGBScreenTarget *)pvCmd;
5629 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5630 vmsvga3dCmdDestroyGBScreenTarget(pThis, pThisCC, pCmd);
5631 break;
5632 }
5633
5634 case SVGA_3D_CMD_BIND_GB_SCREENTARGET:
5635 {
5636 SVGA3dCmdBindGBScreenTarget *pCmd = (SVGA3dCmdBindGBScreenTarget *)pvCmd;
5637 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5638 vmsvga3dCmdBindGBScreenTarget(pThisCC, pCmd);
5639 break;
5640 }
5641
5642 case SVGA_3D_CMD_UPDATE_GB_SCREENTARGET:
5643 {
5644 SVGA3dCmdUpdateGBScreenTarget *pCmd = (SVGA3dCmdUpdateGBScreenTarget *)pvCmd;
5645 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5646 vmsvga3dCmdUpdateGBScreenTarget(pThisCC, pCmd);
5647 break;
5648 }
5649
5650 case SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL:
5651 {
5652 SVGA3dCmdReadbackGBImagePartial *pCmd = (SVGA3dCmdReadbackGBImagePartial *)pvCmd;
5653 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5654 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5655 break;
5656 }
5657
5658 case SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL:
5659 {
5660 SVGA3dCmdInvalidateGBImagePartial *pCmd = (SVGA3dCmdInvalidateGBImagePartial *)pvCmd;
5661 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5662 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5663 break;
5664 }
5665
5666 case SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE:
5667 {
5668 SVGA3dCmdSetGBShaderConstInline *pCmd = (SVGA3dCmdSetGBShaderConstInline *)pvCmd;
5669 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5670 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5671 break;
5672 }
5673
5674 case SVGA_3D_CMD_GB_SCREEN_DMA:
5675 {
5676 SVGA3dCmdGBScreenDMA *pCmd = (SVGA3dCmdGBScreenDMA *)pvCmd;
5677 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5678 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5679 break;
5680 }
5681
5682 case SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH:
5683 {
5684 SVGA3dCmdBindGBSurfaceWithPitch *pCmd = (SVGA3dCmdBindGBSurfaceWithPitch *)pvCmd;
5685 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5686 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5687 break;
5688 }
5689
5690 case SVGA_3D_CMD_GB_MOB_FENCE:
5691 {
5692 SVGA3dCmdGBMobFence *pCmd = (SVGA3dCmdGBMobFence *)pvCmd;
5693 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5694 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5695 break;
5696 }
5697
5698 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V2:
5699 {
5700 SVGA3dCmdDefineGBSurface_v2 *pCmd = (SVGA3dCmdDefineGBSurface_v2 *)pvCmd;
5701 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5702 vmsvga3dCmdDefineGBSurface_v2(pThisCC, pCmd);
5703 break;
5704 }
5705
5706 case SVGA_3D_CMD_DEFINE_GB_MOB64:
5707 {
5708 SVGA3dCmdDefineGBMob64 *pCmd = (SVGA3dCmdDefineGBMob64 *)pvCmd;
5709 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5710 vmsvga3dCmdDefineGBMob64(pThisCC, pCmd);
5711 break;
5712 }
5713
5714 case SVGA_3D_CMD_REDEFINE_GB_MOB64:
5715 {
5716 SVGA3dCmdRedefineGBMob64 *pCmd = (SVGA3dCmdRedefineGBMob64 *)pvCmd;
5717 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5718 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5719 break;
5720 }
5721
5722 case SVGA_3D_CMD_NOP_ERROR:
5723 {
5724 /* Apparently there is nothing to do. */
5725 break;
5726 }
5727
5728 case SVGA_3D_CMD_SET_VERTEX_STREAMS:
5729 {
5730 SVGA3dCmdSetVertexStreams *pCmd = (SVGA3dCmdSetVertexStreams *)pvCmd;
5731 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5732 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5733 break;
5734 }
5735
5736 case SVGA_3D_CMD_SET_VERTEX_DECLS:
5737 {
5738 SVGA3dCmdSetVertexDecls *pCmd = (SVGA3dCmdSetVertexDecls *)pvCmd;
5739 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5740 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5741 break;
5742 }
5743
5744 case SVGA_3D_CMD_SET_VERTEX_DIVISORS:
5745 {
5746 SVGA3dCmdSetVertexDivisors *pCmd = (SVGA3dCmdSetVertexDivisors *)pvCmd;
5747 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5748 VMSVGA_3D_CMD_NOTIMPL(); RT_NOREF(pCmd);
5749 break;
5750 }
5751
5752 case SVGA_3D_CMD_DRAW:
5753 {
5754 /* No corresponding SVGA3dCmd structure. */
5755 VMSVGA_3D_CMD_NOTIMPL();
5756 break;
5757 }
5758
5759 case SVGA_3D_CMD_DRAW_INDEXED:
5760 {
5761 /* No corresponding SVGA3dCmd structure. */
5762 VMSVGA_3D_CMD_NOTIMPL();
5763 break;
5764 }
5765
5766 case SVGA_3D_CMD_DX_DEFINE_CONTEXT:
5767 {
5768 SVGA3dCmdDXDefineContext *pCmd = (SVGA3dCmdDXDefineContext *)pvCmd;
5769 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5770 rcParse = vmsvga3dCmdDXDefineContext(pThisCC, pCmd, cbCmd);
5771 break;
5772 }
5773
5774 case SVGA_3D_CMD_DX_DESTROY_CONTEXT:
5775 {
5776 SVGA3dCmdDXDestroyContext *pCmd = (SVGA3dCmdDXDestroyContext *)pvCmd;
5777 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5778 rcParse = vmsvga3dCmdDXDestroyContext(pThisCC, pCmd, cbCmd);
5779 break;
5780 }
5781
5782 case SVGA_3D_CMD_DX_BIND_CONTEXT:
5783 {
5784 SVGA3dCmdDXBindContext *pCmd = (SVGA3dCmdDXBindContext *)pvCmd;
5785 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5786 rcParse = vmsvga3dCmdDXBindContext(pThisCC, pCmd, cbCmd);
5787 break;
5788 }
5789
5790 case SVGA_3D_CMD_DX_READBACK_CONTEXT:
5791 {
5792 SVGA3dCmdDXReadbackContext *pCmd = (SVGA3dCmdDXReadbackContext *)pvCmd;
5793 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5794 rcParse = vmsvga3dCmdDXReadbackContext(pThisCC, pCmd, cbCmd);
5795 break;
5796 }
5797
5798 case SVGA_3D_CMD_DX_INVALIDATE_CONTEXT:
5799 {
5800 SVGA3dCmdDXInvalidateContext *pCmd = (SVGA3dCmdDXInvalidateContext *)pvCmd;
5801 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5802 rcParse = vmsvga3dCmdDXInvalidateContext(pThisCC, idDXContext, pCmd, cbCmd);
5803 break;
5804 }
5805
5806 case SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER:
5807 {
5808 SVGA3dCmdDXSetSingleConstantBuffer *pCmd = (SVGA3dCmdDXSetSingleConstantBuffer *)pvCmd;
5809 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5810 rcParse = vmsvga3dCmdDXSetSingleConstantBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5811 break;
5812 }
5813
5814 case SVGA_3D_CMD_DX_SET_SHADER_RESOURCES:
5815 {
5816 SVGA3dCmdDXSetShaderResources *pCmd = (SVGA3dCmdDXSetShaderResources *)pvCmd;
5817 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5818 rcParse = vmsvga3dCmdDXSetShaderResources(pThisCC, idDXContext, pCmd, cbCmd);
5819 break;
5820 }
5821
5822 case SVGA_3D_CMD_DX_SET_SHADER:
5823 {
5824 SVGA3dCmdDXSetShader *pCmd = (SVGA3dCmdDXSetShader *)pvCmd;
5825 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5826 rcParse = vmsvga3dCmdDXSetShader(pThisCC, idDXContext, pCmd, cbCmd);
5827 break;
5828 }
5829
5830 case SVGA_3D_CMD_DX_SET_SAMPLERS:
5831 {
5832 SVGA3dCmdDXSetSamplers *pCmd = (SVGA3dCmdDXSetSamplers *)pvCmd;
5833 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5834 rcParse = vmsvga3dCmdDXSetSamplers(pThisCC, idDXContext, pCmd, cbCmd);
5835 break;
5836 }
5837
5838 case SVGA_3D_CMD_DX_DRAW:
5839 {
5840 SVGA3dCmdDXDraw *pCmd = (SVGA3dCmdDXDraw *)pvCmd;
5841 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5842 rcParse = vmsvga3dCmdDXDraw(pThisCC, idDXContext, pCmd, cbCmd);
5843 break;
5844 }
5845
5846 case SVGA_3D_CMD_DX_DRAW_INDEXED:
5847 {
5848 SVGA3dCmdDXDrawIndexed *pCmd = (SVGA3dCmdDXDrawIndexed *)pvCmd;
5849 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5850 rcParse = vmsvga3dCmdDXDrawIndexed(pThisCC, idDXContext, pCmd, cbCmd);
5851 break;
5852 }
5853
5854 case SVGA_3D_CMD_DX_DRAW_INSTANCED:
5855 {
5856 SVGA3dCmdDXDrawInstanced *pCmd = (SVGA3dCmdDXDrawInstanced *)pvCmd;
5857 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5858 rcParse = vmsvga3dCmdDXDrawInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5859 break;
5860 }
5861
5862 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED:
5863 {
5864 SVGA3dCmdDXDrawIndexedInstanced *pCmd = (SVGA3dCmdDXDrawIndexedInstanced *)pvCmd;
5865 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5866 rcParse = vmsvga3dCmdDXDrawIndexedInstanced(pThisCC, idDXContext, pCmd, cbCmd);
5867 break;
5868 }
5869
5870 case SVGA_3D_CMD_DX_DRAW_AUTO:
5871 {
5872 SVGA3dCmdDXDrawAuto *pCmd = (SVGA3dCmdDXDrawAuto *)pvCmd;
5873 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5874 rcParse = vmsvga3dCmdDXDrawAuto(pThisCC, idDXContext, pCmd, cbCmd);
5875 break;
5876 }
5877
5878 case SVGA_3D_CMD_DX_SET_INPUT_LAYOUT:
5879 {
5880 SVGA3dCmdDXSetInputLayout *pCmd = (SVGA3dCmdDXSetInputLayout *)pvCmd;
5881 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5882 rcParse = vmsvga3dCmdDXSetInputLayout(pThisCC, idDXContext, pCmd, cbCmd);
5883 break;
5884 }
5885
5886 case SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS:
5887 {
5888 SVGA3dCmdDXSetVertexBuffers *pCmd = (SVGA3dCmdDXSetVertexBuffers *)pvCmd;
5889 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5890 rcParse = vmsvga3dCmdDXSetVertexBuffers(pThisCC, idDXContext, pCmd, cbCmd);
5891 break;
5892 }
5893
5894 case SVGA_3D_CMD_DX_SET_INDEX_BUFFER:
5895 {
5896 SVGA3dCmdDXSetIndexBuffer *pCmd = (SVGA3dCmdDXSetIndexBuffer *)pvCmd;
5897 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5898 rcParse = vmsvga3dCmdDXSetIndexBuffer(pThisCC, idDXContext, pCmd, cbCmd);
5899 break;
5900 }
5901
5902 case SVGA_3D_CMD_DX_SET_TOPOLOGY:
5903 {
5904 SVGA3dCmdDXSetTopology *pCmd = (SVGA3dCmdDXSetTopology *)pvCmd;
5905 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5906 rcParse = vmsvga3dCmdDXSetTopology(pThisCC, idDXContext, pCmd, cbCmd);
5907 break;
5908 }
5909
5910 case SVGA_3D_CMD_DX_SET_RENDERTARGETS:
5911 {
5912 SVGA3dCmdDXSetRenderTargets *pCmd = (SVGA3dCmdDXSetRenderTargets *)pvCmd;
5913 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5914 rcParse = vmsvga3dCmdDXSetRenderTargets(pThisCC, idDXContext, pCmd, cbCmd);
5915 break;
5916 }
5917
5918 case SVGA_3D_CMD_DX_SET_BLEND_STATE:
5919 {
5920 SVGA3dCmdDXSetBlendState *pCmd = (SVGA3dCmdDXSetBlendState *)pvCmd;
5921 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5922 rcParse = vmsvga3dCmdDXSetBlendState(pThisCC, idDXContext, pCmd, cbCmd);
5923 break;
5924 }
5925
5926 case SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE:
5927 {
5928 SVGA3dCmdDXSetDepthStencilState *pCmd = (SVGA3dCmdDXSetDepthStencilState *)pvCmd;
5929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5930 rcParse = vmsvga3dCmdDXSetDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
5931 break;
5932 }
5933
5934 case SVGA_3D_CMD_DX_SET_RASTERIZER_STATE:
5935 {
5936 SVGA3dCmdDXSetRasterizerState *pCmd = (SVGA3dCmdDXSetRasterizerState *)pvCmd;
5937 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5938 rcParse = vmsvga3dCmdDXSetRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
5939 break;
5940 }
5941
5942 case SVGA_3D_CMD_DX_DEFINE_QUERY:
5943 {
5944 SVGA3dCmdDXDefineQuery *pCmd = (SVGA3dCmdDXDefineQuery *)pvCmd;
5945 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5946 rcParse = vmsvga3dCmdDXDefineQuery(pThisCC, idDXContext, pCmd, cbCmd);
5947 break;
5948 }
5949
5950 case SVGA_3D_CMD_DX_DESTROY_QUERY:
5951 {
5952 SVGA3dCmdDXDestroyQuery *pCmd = (SVGA3dCmdDXDestroyQuery *)pvCmd;
5953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5954 rcParse = vmsvga3dCmdDXDestroyQuery(pThisCC, idDXContext, pCmd, cbCmd);
5955 break;
5956 }
5957
5958 case SVGA_3D_CMD_DX_BIND_QUERY:
5959 {
5960 SVGA3dCmdDXBindQuery *pCmd = (SVGA3dCmdDXBindQuery *)pvCmd;
5961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5962 rcParse = vmsvga3dCmdDXBindQuery(pThisCC, idDXContext, pCmd, cbCmd);
5963 break;
5964 }
5965
5966 case SVGA_3D_CMD_DX_SET_QUERY_OFFSET:
5967 {
5968 SVGA3dCmdDXSetQueryOffset *pCmd = (SVGA3dCmdDXSetQueryOffset *)pvCmd;
5969 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5970 rcParse = vmsvga3dCmdDXSetQueryOffset(pThisCC, idDXContext, pCmd, cbCmd);
5971 break;
5972 }
5973
5974 case SVGA_3D_CMD_DX_BEGIN_QUERY:
5975 {
5976 SVGA3dCmdDXBeginQuery *pCmd = (SVGA3dCmdDXBeginQuery *)pvCmd;
5977 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5978 rcParse = vmsvga3dCmdDXBeginQuery(pThisCC, idDXContext, pCmd, cbCmd);
5979 break;
5980 }
5981
5982 case SVGA_3D_CMD_DX_END_QUERY:
5983 {
5984 SVGA3dCmdDXEndQuery *pCmd = (SVGA3dCmdDXEndQuery *)pvCmd;
5985 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5986 rcParse = vmsvga3dCmdDXEndQuery(pThisCC, idDXContext, pCmd, cbCmd);
5987 break;
5988 }
5989
5990 case SVGA_3D_CMD_DX_READBACK_QUERY:
5991 {
5992 SVGA3dCmdDXReadbackQuery *pCmd = (SVGA3dCmdDXReadbackQuery *)pvCmd;
5993 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5994 rcParse = vmsvga3dCmdDXReadbackQuery(pThisCC, idDXContext, pCmd, cbCmd);
5995 break;
5996 }
5997
5998 case SVGA_3D_CMD_DX_SET_PREDICATION:
5999 {
6000 SVGA3dCmdDXSetPredication *pCmd = (SVGA3dCmdDXSetPredication *)pvCmd;
6001 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6002 rcParse = vmsvga3dCmdDXSetPredication(pThisCC, idDXContext, pCmd, cbCmd);
6003 break;
6004 }
6005
6006 case SVGA_3D_CMD_DX_SET_SOTARGETS:
6007 {
6008 SVGA3dCmdDXSetSOTargets *pCmd = (SVGA3dCmdDXSetSOTargets *)pvCmd;
6009 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6010 rcParse = vmsvga3dCmdDXSetSOTargets(pThisCC, idDXContext, pCmd, cbCmd);
6011 break;
6012 }
6013
6014 case SVGA_3D_CMD_DX_SET_VIEWPORTS:
6015 {
6016 SVGA3dCmdDXSetViewports *pCmd = (SVGA3dCmdDXSetViewports *)pvCmd;
6017 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6018 rcParse = vmsvga3dCmdDXSetViewports(pThisCC, idDXContext, pCmd, cbCmd);
6019 break;
6020 }
6021
6022 case SVGA_3D_CMD_DX_SET_SCISSORRECTS:
6023 {
6024 SVGA3dCmdDXSetScissorRects *pCmd = (SVGA3dCmdDXSetScissorRects *)pvCmd;
6025 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6026 rcParse = vmsvga3dCmdDXSetScissorRects(pThisCC, idDXContext, pCmd, cbCmd);
6027 break;
6028 }
6029
6030 case SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW:
6031 {
6032 SVGA3dCmdDXClearRenderTargetView *pCmd = (SVGA3dCmdDXClearRenderTargetView *)pvCmd;
6033 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6034 rcParse = vmsvga3dCmdDXClearRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
6035 break;
6036 }
6037
6038 case SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW:
6039 {
6040 SVGA3dCmdDXClearDepthStencilView *pCmd = (SVGA3dCmdDXClearDepthStencilView *)pvCmd;
6041 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6042 rcParse = vmsvga3dCmdDXClearDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
6043 break;
6044 }
6045
6046 case SVGA_3D_CMD_DX_PRED_COPY_REGION:
6047 {
6048 SVGA3dCmdDXPredCopyRegion *pCmd = (SVGA3dCmdDXPredCopyRegion *)pvCmd;
6049 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6050 rcParse = vmsvga3dCmdDXPredCopyRegion(pThisCC, idDXContext, pCmd, cbCmd);
6051 break;
6052 }
6053
6054 case SVGA_3D_CMD_DX_PRED_COPY:
6055 {
6056 SVGA3dCmdDXPredCopy *pCmd = (SVGA3dCmdDXPredCopy *)pvCmd;
6057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6058 rcParse = vmsvga3dCmdDXPredCopy(pThisCC, idDXContext, pCmd, cbCmd);
6059 break;
6060 }
6061
6062 case SVGA_3D_CMD_DX_PRESENTBLT:
6063 {
6064 SVGA3dCmdDXPresentBlt *pCmd = (SVGA3dCmdDXPresentBlt *)pvCmd;
6065 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6066 rcParse = vmsvga3dCmdDXPresentBlt(pThisCC, idDXContext, pCmd, cbCmd);
6067 break;
6068 }
6069
6070 case SVGA_3D_CMD_DX_GENMIPS:
6071 {
6072 SVGA3dCmdDXGenMips *pCmd = (SVGA3dCmdDXGenMips *)pvCmd;
6073 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6074 rcParse = vmsvga3dCmdDXGenMips(pThisCC, idDXContext, pCmd, cbCmd);
6075 break;
6076 }
6077
6078 case SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE:
6079 {
6080 SVGA3dCmdDXUpdateSubResource *pCmd = (SVGA3dCmdDXUpdateSubResource *)pvCmd;
6081 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6082 rcParse = vmsvga3dCmdDXUpdateSubResource(pThisCC, pCmd, cbCmd);
6083 break;
6084 }
6085
6086 case SVGA_3D_CMD_DX_READBACK_SUBRESOURCE:
6087 {
6088 SVGA3dCmdDXReadbackSubResource *pCmd = (SVGA3dCmdDXReadbackSubResource *)pvCmd;
6089 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6090 rcParse = vmsvga3dCmdDXReadbackSubResource(pThisCC, pCmd, cbCmd);
6091 break;
6092 }
6093
6094 case SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE:
6095 {
6096 SVGA3dCmdDXInvalidateSubResource *pCmd = (SVGA3dCmdDXInvalidateSubResource *)pvCmd;
6097 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6098 rcParse = vmsvga3dCmdDXInvalidateSubResource(pThisCC, pCmd, cbCmd);
6099 break;
6100 }
6101
6102 case SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW:
6103 {
6104 SVGA3dCmdDXDefineShaderResourceView *pCmd = (SVGA3dCmdDXDefineShaderResourceView *)pvCmd;
6105 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6106 rcParse = vmsvga3dCmdDXDefineShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
6107 break;
6108 }
6109
6110 case SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW:
6111 {
6112 SVGA3dCmdDXDestroyShaderResourceView *pCmd = (SVGA3dCmdDXDestroyShaderResourceView *)pvCmd;
6113 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6114 rcParse = vmsvga3dCmdDXDestroyShaderResourceView(pThisCC, idDXContext, pCmd, cbCmd);
6115 break;
6116 }
6117
6118 case SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW:
6119 {
6120 SVGA3dCmdDXDefineRenderTargetView *pCmd = (SVGA3dCmdDXDefineRenderTargetView *)pvCmd;
6121 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6122 rcParse = vmsvga3dCmdDXDefineRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
6123 break;
6124 }
6125
6126 case SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW:
6127 {
6128 SVGA3dCmdDXDestroyRenderTargetView *pCmd = (SVGA3dCmdDXDestroyRenderTargetView *)pvCmd;
6129 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6130 rcParse = vmsvga3dCmdDXDestroyRenderTargetView(pThisCC, idDXContext, pCmd, cbCmd);
6131 break;
6132 }
6133
6134 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW:
6135 {
6136 SVGA3dCmdDXDefineDepthStencilView *pCmd = (SVGA3dCmdDXDefineDepthStencilView *)pvCmd;
6137 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6138 rcParse = vmsvga3dCmdDXDefineDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
6139 break;
6140 }
6141
6142 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW:
6143 {
6144 SVGA3dCmdDXDestroyDepthStencilView *pCmd = (SVGA3dCmdDXDestroyDepthStencilView *)pvCmd;
6145 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6146 rcParse = vmsvga3dCmdDXDestroyDepthStencilView(pThisCC, idDXContext, pCmd, cbCmd);
6147 break;
6148 }
6149
6150 case SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT:
6151 {
6152 SVGA3dCmdDXDefineElementLayout *pCmd = (SVGA3dCmdDXDefineElementLayout *)pvCmd;
6153 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6154 rcParse = vmsvga3dCmdDXDefineElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
6155 break;
6156 }
6157
6158 case SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT:
6159 {
6160 SVGA3dCmdDXDestroyElementLayout *pCmd = (SVGA3dCmdDXDestroyElementLayout *)pvCmd;
6161 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6162 rcParse = vmsvga3dCmdDXDestroyElementLayout(pThisCC, idDXContext, pCmd, cbCmd);
6163 break;
6164 }
6165
6166 case SVGA_3D_CMD_DX_DEFINE_BLEND_STATE:
6167 {
6168 SVGA3dCmdDXDefineBlendState *pCmd = (SVGA3dCmdDXDefineBlendState *)pvCmd;
6169 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6170 rcParse = vmsvga3dCmdDXDefineBlendState(pThisCC, idDXContext, pCmd, cbCmd);
6171 break;
6172 }
6173
6174 case SVGA_3D_CMD_DX_DESTROY_BLEND_STATE:
6175 {
6176 SVGA3dCmdDXDestroyBlendState *pCmd = (SVGA3dCmdDXDestroyBlendState *)pvCmd;
6177 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6178 rcParse = vmsvga3dCmdDXDestroyBlendState(pThisCC, idDXContext, pCmd, cbCmd);
6179 break;
6180 }
6181
6182 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE:
6183 {
6184 SVGA3dCmdDXDefineDepthStencilState *pCmd = (SVGA3dCmdDXDefineDepthStencilState *)pvCmd;
6185 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6186 rcParse = vmsvga3dCmdDXDefineDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
6187 break;
6188 }
6189
6190 case SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE:
6191 {
6192 SVGA3dCmdDXDestroyDepthStencilState *pCmd = (SVGA3dCmdDXDestroyDepthStencilState *)pvCmd;
6193 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6194 rcParse = vmsvga3dCmdDXDestroyDepthStencilState(pThisCC, idDXContext, pCmd, cbCmd);
6195 break;
6196 }
6197
6198 case SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE:
6199 {
6200 SVGA3dCmdDXDefineRasterizerState *pCmd = (SVGA3dCmdDXDefineRasterizerState *)pvCmd;
6201 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6202 rcParse = vmsvga3dCmdDXDefineRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
6203 break;
6204 }
6205
6206 case SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE:
6207 {
6208 SVGA3dCmdDXDestroyRasterizerState *pCmd = (SVGA3dCmdDXDestroyRasterizerState *)pvCmd;
6209 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6210 rcParse = vmsvga3dCmdDXDestroyRasterizerState(pThisCC, idDXContext, pCmd, cbCmd);
6211 break;
6212 }
6213
6214 case SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE:
6215 {
6216 SVGA3dCmdDXDefineSamplerState *pCmd = (SVGA3dCmdDXDefineSamplerState *)pvCmd;
6217 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6218 rcParse = vmsvga3dCmdDXDefineSamplerState(pThisCC, idDXContext, pCmd, cbCmd);
6219 break;
6220 }
6221
6222 case SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE:
6223 {
6224 SVGA3dCmdDXDestroySamplerState *pCmd = (SVGA3dCmdDXDestroySamplerState *)pvCmd;
6225 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6226 rcParse = vmsvga3dCmdDXDestroySamplerState(pThisCC, idDXContext, pCmd, cbCmd);
6227 break;
6228 }
6229
6230 case SVGA_3D_CMD_DX_DEFINE_SHADER:
6231 {
6232 SVGA3dCmdDXDefineShader *pCmd = (SVGA3dCmdDXDefineShader *)pvCmd;
6233 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6234 rcParse = vmsvga3dCmdDXDefineShader(pThisCC, idDXContext, pCmd, cbCmd);
6235 break;
6236 }
6237
6238 case SVGA_3D_CMD_DX_DESTROY_SHADER:
6239 {
6240 SVGA3dCmdDXDestroyShader *pCmd = (SVGA3dCmdDXDestroyShader *)pvCmd;
6241 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6242 rcParse = vmsvga3dCmdDXDestroyShader(pThisCC, idDXContext, pCmd, cbCmd);
6243 break;
6244 }
6245
6246 case SVGA_3D_CMD_DX_BIND_SHADER:
6247 {
6248 SVGA3dCmdDXBindShader *pCmd = (SVGA3dCmdDXBindShader *)pvCmd;
6249 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6250 rcParse = vmsvga3dCmdDXBindShader(pThisCC, idDXContext, pCmd, cbCmd);
6251 break;
6252 }
6253
6254 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT:
6255 {
6256 SVGA3dCmdDXDefineStreamOutput *pCmd = (SVGA3dCmdDXDefineStreamOutput *)pvCmd;
6257 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6258 rcParse = vmsvga3dCmdDXDefineStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6259 break;
6260 }
6261
6262 case SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT:
6263 {
6264 SVGA3dCmdDXDestroyStreamOutput *pCmd = (SVGA3dCmdDXDestroyStreamOutput *)pvCmd;
6265 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6266 rcParse = vmsvga3dCmdDXDestroyStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6267 break;
6268 }
6269
6270 case SVGA_3D_CMD_DX_SET_STREAMOUTPUT:
6271 {
6272 SVGA3dCmdDXSetStreamOutput *pCmd = (SVGA3dCmdDXSetStreamOutput *)pvCmd;
6273 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6274 rcParse = vmsvga3dCmdDXSetStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6275 break;
6276 }
6277
6278 case SVGA_3D_CMD_DX_SET_COTABLE:
6279 {
6280 SVGA3dCmdDXSetCOTable *pCmd = (SVGA3dCmdDXSetCOTable *)pvCmd;
6281 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6282 rcParse = vmsvga3dCmdDXSetCOTable(pThisCC, pCmd, cbCmd);
6283 break;
6284 }
6285
6286 case SVGA_3D_CMD_DX_READBACK_COTABLE:
6287 {
6288 SVGA3dCmdDXReadbackCOTable *pCmd = (SVGA3dCmdDXReadbackCOTable *)pvCmd;
6289 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6290 rcParse = vmsvga3dCmdDXReadbackCOTable(pThisCC, idDXContext, pCmd, cbCmd);
6291 break;
6292 }
6293
6294 case SVGA_3D_CMD_DX_BUFFER_COPY:
6295 {
6296 SVGA3dCmdDXBufferCopy *pCmd = (SVGA3dCmdDXBufferCopy *)pvCmd;
6297 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6298 rcParse = vmsvga3dCmdDXBufferCopy(pThisCC, idDXContext, pCmd, cbCmd);
6299 break;
6300 }
6301
6302 case SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER:
6303 {
6304 SVGA3dCmdDXTransferFromBuffer *pCmd = (SVGA3dCmdDXTransferFromBuffer *)pvCmd;
6305 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6306 rcParse = vmsvga3dCmdDXTransferFromBuffer(pThisCC, pCmd, cbCmd);
6307 break;
6308 }
6309
6310 case SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK:
6311 {
6312 SVGA3dCmdDXSurfaceCopyAndReadback *pCmd = (SVGA3dCmdDXSurfaceCopyAndReadback *)pvCmd;
6313 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6314 rcParse = vmsvga3dCmdDXSurfaceCopyAndReadback(pThisCC, idDXContext, pCmd, cbCmd);
6315 break;
6316 }
6317
6318 case SVGA_3D_CMD_DX_MOVE_QUERY:
6319 {
6320 SVGA3dCmdDXMoveQuery *pCmd = (SVGA3dCmdDXMoveQuery *)pvCmd;
6321 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6322 rcParse = vmsvga3dCmdDXMoveQuery(pThisCC, idDXContext, pCmd, cbCmd);
6323 break;
6324 }
6325
6326 case SVGA_3D_CMD_DX_BIND_ALL_QUERY:
6327 {
6328 SVGA3dCmdDXBindAllQuery *pCmd = (SVGA3dCmdDXBindAllQuery *)pvCmd;
6329 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6330 rcParse = vmsvga3dCmdDXBindAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
6331 break;
6332 }
6333
6334 case SVGA_3D_CMD_DX_READBACK_ALL_QUERY:
6335 {
6336 SVGA3dCmdDXReadbackAllQuery *pCmd = (SVGA3dCmdDXReadbackAllQuery *)pvCmd;
6337 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6338 rcParse = vmsvga3dCmdDXReadbackAllQuery(pThisCC, idDXContext, pCmd, cbCmd);
6339 break;
6340 }
6341
6342 case SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER:
6343 {
6344 SVGA3dCmdDXPredTransferFromBuffer *pCmd = (SVGA3dCmdDXPredTransferFromBuffer *)pvCmd;
6345 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6346 rcParse = vmsvga3dCmdDXPredTransferFromBuffer(pThisCC, idDXContext, pCmd, cbCmd);
6347 break;
6348 }
6349
6350 case SVGA_3D_CMD_DX_MOB_FENCE_64:
6351 {
6352 SVGA3dCmdDXMobFence64 *pCmd = (SVGA3dCmdDXMobFence64 *)pvCmd;
6353 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6354 rcParse = vmsvga3dCmdDXMobFence64(pThisCC, pCmd, cbCmd);
6355 break;
6356 }
6357
6358 case SVGA_3D_CMD_DX_BIND_ALL_SHADER:
6359 {
6360 SVGA3dCmdDXBindAllShader *pCmd = (SVGA3dCmdDXBindAllShader *)pvCmd;
6361 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6362 rcParse = vmsvga3dCmdDXBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
6363 break;
6364 }
6365
6366 case SVGA_3D_CMD_DX_HINT:
6367 {
6368 SVGA3dCmdDXHint *pCmd = (SVGA3dCmdDXHint *)pvCmd;
6369 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6370 rcParse = vmsvga3dCmdDXHint(pThisCC, idDXContext, pCmd, cbCmd);
6371 break;
6372 }
6373
6374 case SVGA_3D_CMD_DX_BUFFER_UPDATE:
6375 {
6376 SVGA3dCmdDXBufferUpdate *pCmd = (SVGA3dCmdDXBufferUpdate *)pvCmd;
6377 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6378 rcParse = vmsvga3dCmdDXBufferUpdate(pThisCC, idDXContext, pCmd, cbCmd);
6379 break;
6380 }
6381
6382 case SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET:
6383 {
6384 SVGA3dCmdDXSetVSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetVSConstantBufferOffset *)pvCmd;
6385 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6386 rcParse = vmsvga3dCmdDXSetVSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
6387 break;
6388 }
6389
6390 case SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET:
6391 {
6392 SVGA3dCmdDXSetPSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetPSConstantBufferOffset *)pvCmd;
6393 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6394 rcParse = vmsvga3dCmdDXSetPSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
6395 break;
6396 }
6397
6398 case SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET:
6399 {
6400 SVGA3dCmdDXSetGSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetGSConstantBufferOffset *)pvCmd;
6401 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6402 rcParse = vmsvga3dCmdDXSetGSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
6403 break;
6404 }
6405
6406 case SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET:
6407 {
6408 SVGA3dCmdDXSetHSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetHSConstantBufferOffset *)pvCmd;
6409 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6410 rcParse = vmsvga3dCmdDXSetHSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
6411 break;
6412 }
6413
6414 case SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET:
6415 {
6416 SVGA3dCmdDXSetDSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetDSConstantBufferOffset *)pvCmd;
6417 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6418 rcParse = vmsvga3dCmdDXSetDSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
6419 break;
6420 }
6421
6422 case SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET:
6423 {
6424 SVGA3dCmdDXSetCSConstantBufferOffset *pCmd = (SVGA3dCmdDXSetCSConstantBufferOffset *)pvCmd;
6425 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6426 rcParse = vmsvga3dCmdDXSetCSConstantBufferOffset(pThisCC, idDXContext, pCmd, cbCmd);
6427 break;
6428 }
6429
6430 case SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER:
6431 {
6432 SVGA3dCmdDXCondBindAllShader *pCmd = (SVGA3dCmdDXCondBindAllShader *)pvCmd;
6433 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6434 rcParse = vmsvga3dCmdDXCondBindAllShader(pThisCC, idDXContext, pCmd, cbCmd);
6435 break;
6436 }
6437
6438 case SVGA_3D_CMD_SCREEN_COPY:
6439 {
6440 SVGA3dCmdScreenCopy *pCmd = (SVGA3dCmdScreenCopy *)pvCmd;
6441 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6442 rcParse = vmsvga3dCmdScreenCopy(pThisCC, idDXContext, pCmd, cbCmd);
6443 break;
6444 }
6445
6446 case SVGA_3D_CMD_RESERVED1:
6447 {
6448 VMSVGA_3D_CMD_NOTIMPL();
6449 break;
6450 }
6451
6452 case SVGA_3D_CMD_RESERVED2:
6453 {
6454 VMSVGA_3D_CMD_NOTIMPL();
6455 break;
6456 }
6457
6458 case SVGA_3D_CMD_RESERVED3:
6459 {
6460 VMSVGA_3D_CMD_NOTIMPL();
6461 break;
6462 }
6463
6464 case SVGA_3D_CMD_RESERVED4:
6465 {
6466 VMSVGA_3D_CMD_NOTIMPL();
6467 break;
6468 }
6469
6470 case SVGA_3D_CMD_RESERVED5:
6471 {
6472 VMSVGA_3D_CMD_NOTIMPL();
6473 break;
6474 }
6475
6476 case SVGA_3D_CMD_RESERVED6:
6477 {
6478 VMSVGA_3D_CMD_NOTIMPL();
6479 break;
6480 }
6481
6482 case SVGA_3D_CMD_RESERVED7:
6483 {
6484 VMSVGA_3D_CMD_NOTIMPL();
6485 break;
6486 }
6487
6488 case SVGA_3D_CMD_RESERVED8:
6489 {
6490 VMSVGA_3D_CMD_NOTIMPL();
6491 break;
6492 }
6493
6494 case SVGA_3D_CMD_GROW_OTABLE:
6495 {
6496 SVGA3dCmdGrowOTable *pCmd = (SVGA3dCmdGrowOTable *)pvCmd;
6497 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6498 rcParse = vmsvga3dCmdGrowOTable(pThisCC, pCmd, cbCmd);
6499 break;
6500 }
6501
6502 case SVGA_3D_CMD_DX_GROW_COTABLE:
6503 {
6504 SVGA3dCmdDXGrowCOTable *pCmd = (SVGA3dCmdDXGrowCOTable *)pvCmd;
6505 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6506 rcParse = vmsvga3dCmdDXGrowCOTable(pThisCC, pCmd, cbCmd);
6507 break;
6508 }
6509
6510 case SVGA_3D_CMD_INTRA_SURFACE_COPY:
6511 {
6512 SVGA3dCmdIntraSurfaceCopy *pCmd = (SVGA3dCmdIntraSurfaceCopy *)pvCmd;
6513 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6514 rcParse = vmsvga3dCmdIntraSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
6515 break;
6516 }
6517
6518 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V3:
6519 {
6520 SVGA3dCmdDefineGBSurface_v3 *pCmd = (SVGA3dCmdDefineGBSurface_v3 *)pvCmd;
6521 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6522 rcParse = vmsvga3dCmdDefineGBSurface_v3(pThisCC, pCmd);
6523 break;
6524 }
6525
6526 case SVGA_3D_CMD_DX_RESOLVE_COPY:
6527 {
6528 SVGA3dCmdDXResolveCopy *pCmd = (SVGA3dCmdDXResolveCopy *)pvCmd;
6529 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6530 rcParse = vmsvga3dCmdDXResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
6531 break;
6532 }
6533
6534 case SVGA_3D_CMD_DX_PRED_RESOLVE_COPY:
6535 {
6536 SVGA3dCmdDXPredResolveCopy *pCmd = (SVGA3dCmdDXPredResolveCopy *)pvCmd;
6537 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6538 rcParse = vmsvga3dCmdDXPredResolveCopy(pThisCC, idDXContext, pCmd, cbCmd);
6539 break;
6540 }
6541
6542 case SVGA_3D_CMD_DX_PRED_CONVERT_REGION:
6543 {
6544 SVGA3dCmdDXPredConvertRegion *pCmd = (SVGA3dCmdDXPredConvertRegion *)pvCmd;
6545 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6546 rcParse = vmsvga3dCmdDXPredConvertRegion(pThisCC, idDXContext, pCmd, cbCmd);
6547 break;
6548 }
6549
6550 case SVGA_3D_CMD_DX_PRED_CONVERT:
6551 {
6552 SVGA3dCmdDXPredConvert *pCmd = (SVGA3dCmdDXPredConvert *)pvCmd;
6553 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6554 rcParse = vmsvga3dCmdDXPredConvert(pThisCC, idDXContext, pCmd, cbCmd);
6555 break;
6556 }
6557
6558 case SVGA_3D_CMD_WHOLE_SURFACE_COPY:
6559 {
6560 SVGA3dCmdWholeSurfaceCopy *pCmd = (SVGA3dCmdWholeSurfaceCopy *)pvCmd;
6561 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6562 rcParse = vmsvga3dCmdWholeSurfaceCopy(pThisCC, idDXContext, pCmd, cbCmd);
6563 break;
6564 }
6565
6566 case SVGA_3D_CMD_DX_DEFINE_UA_VIEW:
6567 {
6568 SVGA3dCmdDXDefineUAView *pCmd = (SVGA3dCmdDXDefineUAView *)pvCmd;
6569 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6570 rcParse = vmsvga3dCmdDXDefineUAView(pThisCC, idDXContext, pCmd, cbCmd);
6571 break;
6572 }
6573
6574 case SVGA_3D_CMD_DX_DESTROY_UA_VIEW:
6575 {
6576 SVGA3dCmdDXDestroyUAView *pCmd = (SVGA3dCmdDXDestroyUAView *)pvCmd;
6577 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6578 rcParse = vmsvga3dCmdDXDestroyUAView(pThisCC, idDXContext, pCmd, cbCmd);
6579 break;
6580 }
6581
6582 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT:
6583 {
6584 SVGA3dCmdDXClearUAViewUint *pCmd = (SVGA3dCmdDXClearUAViewUint *)pvCmd;
6585 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6586 rcParse = vmsvga3dCmdDXClearUAViewUint(pThisCC, idDXContext, pCmd, cbCmd);
6587 break;
6588 }
6589
6590 case SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT:
6591 {
6592 SVGA3dCmdDXClearUAViewFloat *pCmd = (SVGA3dCmdDXClearUAViewFloat *)pvCmd;
6593 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6594 rcParse = vmsvga3dCmdDXClearUAViewFloat(pThisCC, idDXContext, pCmd, cbCmd);
6595 break;
6596 }
6597
6598 case SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT:
6599 {
6600 SVGA3dCmdDXCopyStructureCount *pCmd = (SVGA3dCmdDXCopyStructureCount *)pvCmd;
6601 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6602 rcParse = vmsvga3dCmdDXCopyStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
6603 break;
6604 }
6605
6606 case SVGA_3D_CMD_DX_SET_UA_VIEWS:
6607 {
6608 SVGA3dCmdDXSetUAViews *pCmd = (SVGA3dCmdDXSetUAViews *)pvCmd;
6609 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6610 rcParse = vmsvga3dCmdDXSetUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6611 break;
6612 }
6613
6614 case SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT:
6615 {
6616 SVGA3dCmdDXDrawIndexedInstancedIndirect *pCmd = (SVGA3dCmdDXDrawIndexedInstancedIndirect *)pvCmd;
6617 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6618 rcParse = vmsvga3dCmdDXDrawIndexedInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
6619 break;
6620 }
6621
6622 case SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT:
6623 {
6624 SVGA3dCmdDXDrawInstancedIndirect *pCmd = (SVGA3dCmdDXDrawInstancedIndirect *)pvCmd;
6625 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6626 rcParse = vmsvga3dCmdDXDrawInstancedIndirect(pThisCC, idDXContext, pCmd, cbCmd);
6627 break;
6628 }
6629
6630 case SVGA_3D_CMD_DX_DISPATCH:
6631 {
6632 SVGA3dCmdDXDispatch *pCmd = (SVGA3dCmdDXDispatch *)pvCmd;
6633 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6634 rcParse = vmsvga3dCmdDXDispatch(pThisCC, idDXContext, pCmd, cbCmd);
6635 break;
6636 }
6637
6638 case SVGA_3D_CMD_DX_DISPATCH_INDIRECT:
6639 {
6640 SVGA3dCmdDXDispatchIndirect *pCmd = (SVGA3dCmdDXDispatchIndirect *)pvCmd;
6641 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6642 rcParse = vmsvga3dCmdDXDispatchIndirect(pThisCC, idDXContext, pCmd, cbCmd);
6643 break;
6644 }
6645
6646 case SVGA_3D_CMD_WRITE_ZERO_SURFACE:
6647 {
6648 SVGA3dCmdWriteZeroSurface *pCmd = (SVGA3dCmdWriteZeroSurface *)pvCmd;
6649 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6650 rcParse = vmsvga3dCmdWriteZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
6651 break;
6652 }
6653
6654 case SVGA_3D_CMD_HINT_ZERO_SURFACE:
6655 {
6656 SVGA3dCmdHintZeroSurface *pCmd = (SVGA3dCmdHintZeroSurface *)pvCmd;
6657 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6658 rcParse = vmsvga3dCmdHintZeroSurface(pThisCC, idDXContext, pCmd, cbCmd);
6659 break;
6660 }
6661
6662 case SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER:
6663 {
6664 SVGA3dCmdDXTransferToBuffer *pCmd = (SVGA3dCmdDXTransferToBuffer *)pvCmd;
6665 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6666 rcParse = vmsvga3dCmdDXTransferToBuffer(pThisCC, idDXContext, pCmd, cbCmd);
6667 break;
6668 }
6669
6670 case SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT:
6671 {
6672 SVGA3dCmdDXSetStructureCount *pCmd = (SVGA3dCmdDXSetStructureCount *)pvCmd;
6673 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6674 rcParse = vmsvga3dCmdDXSetStructureCount(pThisCC, idDXContext, pCmd, cbCmd);
6675 break;
6676 }
6677
6678 case SVGA_3D_CMD_LOGICOPS_BITBLT:
6679 {
6680 SVGA3dCmdLogicOpsBitBlt *pCmd = (SVGA3dCmdLogicOpsBitBlt *)pvCmd;
6681 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6682 rcParse = vmsvga3dCmdLogicOpsBitBlt(pThisCC, idDXContext, pCmd, cbCmd);
6683 break;
6684 }
6685
6686 case SVGA_3D_CMD_LOGICOPS_TRANSBLT:
6687 {
6688 SVGA3dCmdLogicOpsTransBlt *pCmd = (SVGA3dCmdLogicOpsTransBlt *)pvCmd;
6689 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6690 rcParse = vmsvga3dCmdLogicOpsTransBlt(pThisCC, idDXContext, pCmd, cbCmd);
6691 break;
6692 }
6693
6694 case SVGA_3D_CMD_LOGICOPS_STRETCHBLT:
6695 {
6696 SVGA3dCmdLogicOpsStretchBlt *pCmd = (SVGA3dCmdLogicOpsStretchBlt *)pvCmd;
6697 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6698 rcParse = vmsvga3dCmdLogicOpsStretchBlt(pThisCC, idDXContext, pCmd, cbCmd);
6699 break;
6700 }
6701
6702 case SVGA_3D_CMD_LOGICOPS_COLORFILL:
6703 {
6704 SVGA3dCmdLogicOpsColorFill *pCmd = (SVGA3dCmdLogicOpsColorFill *)pvCmd;
6705 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6706 rcParse = vmsvga3dCmdLogicOpsColorFill(pThisCC, idDXContext, pCmd, cbCmd);
6707 break;
6708 }
6709
6710 case SVGA_3D_CMD_LOGICOPS_ALPHABLEND:
6711 {
6712 SVGA3dCmdLogicOpsAlphaBlend *pCmd = (SVGA3dCmdLogicOpsAlphaBlend *)pvCmd;
6713 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6714 rcParse = vmsvga3dCmdLogicOpsAlphaBlend(pThisCC, idDXContext, pCmd, cbCmd);
6715 break;
6716 }
6717
6718 case SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND:
6719 {
6720 SVGA3dCmdLogicOpsClearTypeBlend *pCmd = (SVGA3dCmdLogicOpsClearTypeBlend *)pvCmd;
6721 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6722 rcParse = vmsvga3dCmdLogicOpsClearTypeBlend(pThisCC, idDXContext, pCmd, cbCmd);
6723 break;
6724 }
6725
6726 case SVGA_3D_CMD_RESERVED2_1:
6727 {
6728 VMSVGA_3D_CMD_NOTIMPL();
6729 break;
6730 }
6731
6732 case SVGA_3D_CMD_RESERVED2_2:
6733 {
6734 VMSVGA_3D_CMD_NOTIMPL();
6735 break;
6736 }
6737
6738 case SVGA_3D_CMD_DEFINE_GB_SURFACE_V4:
6739 {
6740 SVGA3dCmdDefineGBSurface_v4 *pCmd = (SVGA3dCmdDefineGBSurface_v4 *)pvCmd;
6741 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6742 rcParse = vmsvga3dCmdDefineGBSurface_v4(pThisCC, pCmd);
6743 break;
6744 }
6745
6746 case SVGA_3D_CMD_DX_SET_CS_UA_VIEWS:
6747 {
6748 SVGA3dCmdDXSetCSUAViews *pCmd = (SVGA3dCmdDXSetCSUAViews *)pvCmd;
6749 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6750 rcParse = vmsvga3dCmdDXSetCSUAViews(pThisCC, idDXContext, pCmd, cbCmd);
6751 break;
6752 }
6753
6754 case SVGA_3D_CMD_DX_SET_MIN_LOD:
6755 {
6756 SVGA3dCmdDXSetMinLOD *pCmd = (SVGA3dCmdDXSetMinLOD *)pvCmd;
6757 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6758 rcParse = vmsvga3dCmdDXSetMinLOD(pThisCC, idDXContext, pCmd, cbCmd);
6759 break;
6760 }
6761
6762 case SVGA_3D_CMD_RESERVED2_3:
6763 {
6764 VMSVGA_3D_CMD_NOTIMPL();
6765 break;
6766 }
6767
6768 case SVGA_3D_CMD_RESERVED2_4:
6769 {
6770 VMSVGA_3D_CMD_NOTIMPL();
6771 break;
6772 }
6773
6774 case SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2:
6775 {
6776 SVGA3dCmdDXDefineDepthStencilView_v2 *pCmd = (SVGA3dCmdDXDefineDepthStencilView_v2 *)pvCmd;
6777 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6778 rcParse = vmsvga3dCmdDXDefineDepthStencilView_v2(pThisCC, idDXContext, pCmd, cbCmd);
6779 break;
6780 }
6781
6782 case SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB:
6783 {
6784 SVGA3dCmdDXDefineStreamOutputWithMob *pCmd = (SVGA3dCmdDXDefineStreamOutputWithMob *)pvCmd;
6785 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6786 rcParse = vmsvga3dCmdDXDefineStreamOutputWithMob(pThisCC, idDXContext, pCmd, cbCmd);
6787 break;
6788 }
6789
6790 case SVGA_3D_CMD_DX_SET_SHADER_IFACE:
6791 {
6792 SVGA3dCmdDXSetShaderIface *pCmd = (SVGA3dCmdDXSetShaderIface *)pvCmd;
6793 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6794 rcParse = vmsvga3dCmdDXSetShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6795 break;
6796 }
6797
6798 case SVGA_3D_CMD_DX_BIND_STREAMOUTPUT:
6799 {
6800 SVGA3dCmdDXBindStreamOutput *pCmd = (SVGA3dCmdDXBindStreamOutput *)pvCmd;
6801 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6802 rcParse = vmsvga3dCmdDXBindStreamOutput(pThisCC, idDXContext, pCmd, cbCmd);
6803 break;
6804 }
6805
6806 case SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS:
6807 {
6808 SVGA3dCmdSurfaceStretchBltNonMSToMS *pCmd = (SVGA3dCmdSurfaceStretchBltNonMSToMS *)pvCmd;
6809 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6810 rcParse = vmsvga3dCmdSurfaceStretchBltNonMSToMS(pThisCC, idDXContext, pCmd, cbCmd);
6811 break;
6812 }
6813
6814 case SVGA_3D_CMD_DX_BIND_SHADER_IFACE:
6815 {
6816 SVGA3dCmdDXBindShaderIface *pCmd = (SVGA3dCmdDXBindShaderIface *)pvCmd;
6817 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6818 rcParse = vmsvga3dCmdDXBindShaderIface(pThisCC, idDXContext, pCmd, cbCmd);
6819 break;
6820 }
6821
6822 case SVGA_3D_CMD_VB_DX_CLEAR_RENDERTARGET_VIEW_REGION:
6823 {
6824 SVGA3dCmdVBDXClearRenderTargetViewRegion *pCmd = (SVGA3dCmdVBDXClearRenderTargetViewRegion *)pvCmd;
6825 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6826 rcParse = vmsvga3dCmdVBDXClearRenderTargetViewRegion(pThisCC, idDXContext, pCmd, cbCmd);
6827 break;
6828 }
6829
6830 case VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR:
6831 {
6832 VBSVGA3dCmdDXDefineVideoProcessor *pCmd = (VBSVGA3dCmdDXDefineVideoProcessor *)pvCmd;
6833 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6834 rcParse = vmsvga3dVBCmdDXDefineVideoProcessor(pThisCC, idDXContext, pCmd, cbCmd);
6835 break;
6836 }
6837
6838 case VBSVGA_3D_CMD_DX_DEFINE_VIDEO_DECODER_OUTPUT_VIEW:
6839 {
6840 VBSVGA3dCmdDXDefineVideoDecoderOutputView *pCmd = (VBSVGA3dCmdDXDefineVideoDecoderOutputView *)pvCmd;
6841 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6842 rcParse = vmsvga3dVBCmdDXDefineVideoDecoderOutputView(pThisCC, idDXContext, pCmd, cbCmd);
6843 break;
6844 }
6845
6846 case VBSVGA_3D_CMD_DX_DEFINE_VIDEO_DECODER:
6847 {
6848 VBSVGA3dCmdDXDefineVideoDecoder *pCmd = (VBSVGA3dCmdDXDefineVideoDecoder *)pvCmd;
6849 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6850 rcParse = vmsvga3dVBCmdDXDefineVideoDecoder(pThisCC, idDXContext, pCmd, cbCmd);
6851 break;
6852 }
6853
6854 case VBSVGA_3D_CMD_DX_VIDEO_DECODER_BEGIN_FRAME:
6855 {
6856 VBSVGA3dCmdDXVideoDecoderBeginFrame *pCmd = (VBSVGA3dCmdDXVideoDecoderBeginFrame *)pvCmd;
6857 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6858 rcParse = vmsvga3dVBCmdDXVideoDecoderBeginFrame(pThisCC, idDXContext, pCmd, cbCmd);
6859 break;
6860 }
6861
6862 case VBSVGA_3D_CMD_DX_VIDEO_DECODER_SUBMIT_BUFFERS:
6863 {
6864 VBSVGA3dCmdDXVideoDecoderSubmitBuffers *pCmd = (VBSVGA3dCmdDXVideoDecoderSubmitBuffers *)pvCmd;
6865 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6866 rcParse = vmsvga3dVBCmdDXVideoDecoderSubmitBuffers(pThisCC, idDXContext, pCmd, cbCmd);
6867 break;
6868 }
6869
6870 case VBSVGA_3D_CMD_DX_VIDEO_DECODER_END_FRAME:
6871 {
6872 VBSVGA3dCmdDXVideoDecoderEndFrame *pCmd = (VBSVGA3dCmdDXVideoDecoderEndFrame *)pvCmd;
6873 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6874 rcParse = vmsvga3dVBCmdDXVideoDecoderEndFrame(pThisCC, idDXContext, pCmd, cbCmd);
6875 break;
6876 }
6877
6878 case VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR_INPUT_VIEW:
6879 {
6880 VBSVGA3dCmdDXDefineVideoProcessorInputView *pCmd = (VBSVGA3dCmdDXDefineVideoProcessorInputView *)pvCmd;
6881 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6882 rcParse = vmsvga3dVBCmdDXDefineVideoProcessorInputView(pThisCC, idDXContext, pCmd, cbCmd);
6883 break;
6884 }
6885
6886 case VBSVGA_3D_CMD_DX_DEFINE_VIDEO_PROCESSOR_OUTPUT_VIEW:
6887 {
6888 VBSVGA3dCmdDXDefineVideoProcessorOutputView *pCmd = (VBSVGA3dCmdDXDefineVideoProcessorOutputView *)pvCmd;
6889 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6890 rcParse = vmsvga3dVBCmdDXDefineVideoProcessorOutputView(pThisCC, idDXContext, pCmd, cbCmd);
6891 break;
6892 }
6893
6894 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_BLT:
6895 {
6896 VBSVGA3dCmdDXVideoProcessorBlt *pCmd = (VBSVGA3dCmdDXVideoProcessorBlt *)pvCmd;
6897 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6898 rcParse = vmsvga3dVBCmdDXVideoProcessorBlt(pThisCC, idDXContext, pCmd, cbCmd);
6899 break;
6900 }
6901
6902 case VBSVGA_3D_CMD_DX_DESTROY_VIDEO_DECODER:
6903 {
6904 VBSVGA3dCmdDXDestroyVideoDecoder *pCmd = (VBSVGA3dCmdDXDestroyVideoDecoder *)pvCmd;
6905 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6906 rcParse = vmsvga3dVBCmdDXDestroyVideoDecoder(pThisCC, idDXContext, pCmd, cbCmd);
6907 break;
6908 }
6909
6910 case VBSVGA_3D_CMD_DX_DESTROY_VIDEO_DECODER_OUTPUT_VIEW:
6911 {
6912 VBSVGA3dCmdDXDestroyVideoDecoderOutputView *pCmd = (VBSVGA3dCmdDXDestroyVideoDecoderOutputView *)pvCmd;
6913 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6914 rcParse = vmsvga3dVBCmdDXDestroyVideoDecoderOutputView(pThisCC, idDXContext, pCmd, cbCmd);
6915 break;
6916 }
6917
6918 case VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR:
6919 {
6920 VBSVGA3dCmdDXDestroyVideoProcessor *pCmd = (VBSVGA3dCmdDXDestroyVideoProcessor *)pvCmd;
6921 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6922 rcParse = vmsvga3dVBCmdDXDestroyVideoProcessor(pThisCC, idDXContext, pCmd, cbCmd);
6923 break;
6924 }
6925
6926 case VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR_INPUT_VIEW:
6927 {
6928 VBSVGA3dCmdDXDestroyVideoProcessorInputView *pCmd = (VBSVGA3dCmdDXDestroyVideoProcessorInputView *)pvCmd;
6929 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6930 rcParse = vmsvga3dVBCmdDXDestroyVideoProcessorInputView(pThisCC, idDXContext, pCmd, cbCmd);
6931 break;
6932 }
6933
6934 case VBSVGA_3D_CMD_DX_DESTROY_VIDEO_PROCESSOR_OUTPUT_VIEW:
6935 {
6936 VBSVGA3dCmdDXDestroyVideoProcessorOutputView *pCmd = (VBSVGA3dCmdDXDestroyVideoProcessorOutputView *)pvCmd;
6937 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6938 rcParse = vmsvga3dVBCmdDXDestroyVideoProcessorOutputView(pThisCC, idDXContext, pCmd, cbCmd);
6939 break;
6940 }
6941
6942 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_TARGET_RECT:
6943 {
6944 VBSVGA3dCmdDXVideoProcessorSetOutputTargetRect *pCmd = (VBSVGA3dCmdDXVideoProcessorSetOutputTargetRect *)pvCmd;
6945 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6946 rcParse = vmsvga3dVBCmdDXVideoProcessorSetOutputTargetRect(pThisCC, idDXContext, pCmd, cbCmd);
6947 break;
6948 }
6949
6950 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_BACKGROUND_COLOR:
6951 {
6952 VBSVGA3dCmdDXVideoProcessorSetOutputBackgroundColor *pCmd = (VBSVGA3dCmdDXVideoProcessorSetOutputBackgroundColor *)pvCmd;
6953 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6954 rcParse = vmsvga3dVBCmdDXVideoProcessorSetOutputBackgroundColor(pThisCC, idDXContext, pCmd, cbCmd);
6955 break;
6956 }
6957
6958 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_COLOR_SPACE:
6959 {
6960 VBSVGA3dCmdDXVideoProcessorSetOutputColorSpace *pCmd = (VBSVGA3dCmdDXVideoProcessorSetOutputColorSpace *)pvCmd;
6961 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6962 rcParse = vmsvga3dVBCmdDXVideoProcessorSetOutputColorSpace(pThisCC, idDXContext, pCmd, cbCmd);
6963 break;
6964 }
6965
6966 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_ALPHA_FILL_MODE:
6967 {
6968 VBSVGA3dCmdDXVideoProcessorSetOutputAlphaFillMode *pCmd = (VBSVGA3dCmdDXVideoProcessorSetOutputAlphaFillMode *)pvCmd;
6969 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6970 rcParse = vmsvga3dVBCmdDXVideoProcessorSetOutputAlphaFillMode(pThisCC, idDXContext, pCmd, cbCmd);
6971 break;
6972 }
6973
6974 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_CONSTRICTION:
6975 {
6976 VBSVGA3dCmdDXVideoProcessorSetOutputConstriction *pCmd = (VBSVGA3dCmdDXVideoProcessorSetOutputConstriction *)pvCmd;
6977 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6978 rcParse = vmsvga3dVBCmdDXVideoProcessorSetOutputConstriction(pThisCC, idDXContext, pCmd, cbCmd);
6979 break;
6980 }
6981
6982 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_OUTPUT_STEREO_MODE:
6983 {
6984 VBSVGA3dCmdDXVideoProcessorSetOutputStereoMode *pCmd = (VBSVGA3dCmdDXVideoProcessorSetOutputStereoMode *)pvCmd;
6985 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6986 rcParse = vmsvga3dVBCmdDXVideoProcessorSetOutputStereoMode(pThisCC, idDXContext, pCmd, cbCmd);
6987 break;
6988 }
6989
6990 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_FRAME_FORMAT:
6991 {
6992 VBSVGA3dCmdDXVideoProcessorSetStreamFrameFormat *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamFrameFormat *)pvCmd;
6993 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
6994 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamFrameFormat(pThisCC, idDXContext, pCmd, cbCmd);
6995 break;
6996 }
6997
6998 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_COLOR_SPACE:
6999 {
7000 VBSVGA3dCmdDXVideoProcessorSetStreamColorSpace *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamColorSpace *)pvCmd;
7001 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7002 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamColorSpace(pThisCC, idDXContext, pCmd, cbCmd);
7003 break;
7004 }
7005
7006 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_OUTPUT_RATE:
7007 {
7008 VBSVGA3dCmdDXVideoProcessorSetStreamOutputRate *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamOutputRate *)pvCmd;
7009 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7010 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamOutputRate(pThisCC, idDXContext, pCmd, cbCmd);
7011 break;
7012 }
7013
7014 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_SOURCE_RECT:
7015 {
7016 VBSVGA3dCmdDXVideoProcessorSetStreamSourceRect *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamSourceRect *)pvCmd;
7017 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7018 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamSourceRect(pThisCC, idDXContext, pCmd, cbCmd);
7019 break;
7020 }
7021
7022 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_DEST_RECT:
7023 {
7024 VBSVGA3dCmdDXVideoProcessorSetStreamDestRect *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamDestRect *)pvCmd;
7025 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7026 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamDestRect(pThisCC, idDXContext, pCmd, cbCmd);
7027 break;
7028 }
7029
7030 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_ALPHA:
7031 {
7032 VBSVGA3dCmdDXVideoProcessorSetStreamAlpha *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamAlpha *)pvCmd;
7033 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7034 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamAlpha(pThisCC, idDXContext, pCmd, cbCmd);
7035 break;
7036 }
7037
7038 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_PALETTE:
7039 {
7040 VBSVGA3dCmdDXVideoProcessorSetStreamPalette *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamPalette *)pvCmd;
7041 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7042 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamPalette(pThisCC, idDXContext, pCmd, cbCmd);
7043 break;
7044 }
7045
7046 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_PIXEL_ASPECT_RATIO:
7047 {
7048 VBSVGA3dCmdDXVideoProcessorSetStreamPixelAspectRatio *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamPixelAspectRatio *)pvCmd;
7049 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7050 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamPixelAspectRatio(pThisCC, idDXContext, pCmd, cbCmd);
7051 break;
7052 }
7053
7054 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_LUMA_KEY:
7055 {
7056 VBSVGA3dCmdDXVideoProcessorSetStreamLumaKey *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamLumaKey *)pvCmd;
7057 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7058 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamLumaKey(pThisCC, idDXContext, pCmd, cbCmd);
7059 break;
7060 }
7061
7062 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_STEREO_FORMAT:
7063 {
7064 VBSVGA3dCmdDXVideoProcessorSetStreamStereoFormat *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamStereoFormat *)pvCmd;
7065 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7066 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamStereoFormat(pThisCC, idDXContext, pCmd, cbCmd);
7067 break;
7068 }
7069
7070 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_AUTO_PROCESSING_MODE:
7071 {
7072 VBSVGA3dCmdDXVideoProcessorSetStreamAutoProcessingMode *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamAutoProcessingMode *)pvCmd;
7073 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7074 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamAutoProcessingMode(pThisCC, idDXContext, pCmd, cbCmd);
7075 break;
7076 }
7077
7078 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_FILTER:
7079 {
7080 VBSVGA3dCmdDXVideoProcessorSetStreamFilter *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamFilter *)pvCmd;
7081 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7082 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamFilter(pThisCC, idDXContext, pCmd, cbCmd);
7083 break;
7084 }
7085
7086 case VBSVGA_3D_CMD_DX_VIDEO_PROCESSOR_SET_STREAM_ROTATION:
7087 {
7088 VBSVGA3dCmdDXVideoProcessorSetStreamRotation *pCmd = (VBSVGA3dCmdDXVideoProcessorSetStreamRotation *)pvCmd;
7089 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7090 rcParse = vmsvga3dVBCmdDXVideoProcessorSetStreamRotation(pThisCC, idDXContext, pCmd, cbCmd);
7091 break;
7092 }
7093
7094 case VBSVGA_3D_CMD_DX_GET_VIDEO_CAPABILITY:
7095 {
7096 VBSVGA3dCmdDXGetVideoCapability *pCmd = (VBSVGA3dCmdDXGetVideoCapability *)pvCmd;
7097 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7098 rcParse = vmsvga3dVBCmdDXGetVideoCapability(pThisCC, idDXContext, pCmd, cbCmd);
7099 break;
7100 }
7101
7102 case VBSVGA_3D_CMD_DX_CLEAR_RTV:
7103 {
7104 VBSVGA3dCmdDXClearView *pCmd = (VBSVGA3dCmdDXClearView *)pvCmd;
7105 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7106 rcParse = vmsvga3dVBCmdDXClearRTV(pThisCC, idDXContext, pCmd, cbCmd);
7107 break;
7108 }
7109
7110 case VBSVGA_3D_CMD_DX_CLEAR_UAV:
7111 {
7112 VBSVGA3dCmdDXClearView *pCmd = (VBSVGA3dCmdDXClearView *)pvCmd;
7113 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7114 rcParse = vmsvga3dVBCmdDXClearUAV(pThisCC, idDXContext, pCmd, cbCmd);
7115 break;
7116 }
7117
7118 case VBSVGA_3D_CMD_DX_CLEAR_VDOV:
7119 {
7120 VBSVGA3dCmdDXClearView *pCmd = (VBSVGA3dCmdDXClearView *)pvCmd;
7121 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7122 rcParse = vmsvga3dVBCmdDXClearVDOV(pThisCC, idDXContext, pCmd, cbCmd);
7123 break;
7124 }
7125
7126 case VBSVGA_3D_CMD_DX_CLEAR_VPIV:
7127 {
7128 VBSVGA3dCmdDXClearView *pCmd = (VBSVGA3dCmdDXClearView *)pvCmd;
7129 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7130 rcParse = vmsvga3dVBCmdDXClearVPIV(pThisCC, idDXContext, pCmd, cbCmd);
7131 break;
7132 }
7133
7134 case VBSVGA_3D_CMD_DX_CLEAR_VPOV:
7135 {
7136 VBSVGA3dCmdDXClearView *pCmd = (VBSVGA3dCmdDXClearView *)pvCmd;
7137 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
7138 rcParse = vmsvga3dVBCmdDXClearVPOV(pThisCC, idDXContext, pCmd, cbCmd);
7139 break;
7140 }
7141
7142 /* Unsupported commands. */
7143 case SVGA_3D_CMD_DEAD4: /* SVGA_3D_CMD_VIDEO_CREATE_DECODER */
7144 case SVGA_3D_CMD_DEAD5: /* SVGA_3D_CMD_VIDEO_DESTROY_DECODER */
7145 case SVGA_3D_CMD_DEAD6: /* SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR */
7146 case SVGA_3D_CMD_DEAD7: /* SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR */
7147 case SVGA_3D_CMD_DEAD8: /* SVGA_3D_CMD_VIDEO_DECODE_START_FRAME */
7148 case SVGA_3D_CMD_DEAD9: /* SVGA_3D_CMD_VIDEO_DECODE_RENDER */
7149 case SVGA_3D_CMD_DEAD10: /* SVGA_3D_CMD_VIDEO_DECODE_END_FRAME */
7150 case SVGA_3D_CMD_DEAD11: /* SVGA_3D_CMD_VIDEO_PROCESS_FRAME */
7151 /* Prevent the compiler warning. */
7152 case SVGA_3D_CMD_LEGACY_BASE:
7153 case SVGA_3D_CMD_MAX:
7154 case SVGA_3D_CMD_FUTURE_MAX:
7155 case VBSVGA_3D_CMD_MAX:
7156#ifndef DEBUG_sunlover
7157 default: /* Compiler warning. */
7158#else
7159 /* No 'default' case */
7160#endif
7161 STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
7162 ASSERT_GUEST_MSG_FAILED(("enmCmdId=%d\n", enmCmdId));
7163 LogRelMax(16, ("VMSVGA: unsupported 3D command %d\n", enmCmdId));
7164 rcParse = VERR_NOT_IMPLEMENTED;
7165 break;
7166 }
7167
7168 if (RT_FAILURE(rcParse))
7169 LogRelMax(16, ("VMSVGA: command %d: %Rrc\n", enmCmdId, rcParse));
7170 return VINF_SUCCESS;
7171}
7172# undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
7173#endif /* VBOX_WITH_VMSVGA3D */
7174
7175
7176/*
7177 *
7178 * Handlers for FIFO commands.
7179 *
7180 * Every handler takes the following parameters:
7181 *
7182 * pThis The shared VGA/VMSVGA state.
7183 * pThisCC The VGA/VMSVGA state for ring-3.
7184 * pCmd The command data.
7185 */
7186
7187
7188/* SVGA_CMD_UPDATE */
7189void vmsvgaR3CmdUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdate const *pCmd)
7190{
7191 RT_NOREF(pThis);
7192 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7193
7194 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdate);
7195 Log(("SVGA_CMD_UPDATE %d,%d %dx%d\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height));
7196
7197 /** @todo Multiple screens? */
7198 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
7199 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
7200 return;
7201
7202 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
7203}
7204
7205
7206/* SVGA_CMD_UPDATE_VERBOSE */
7207void vmsvgaR3CmdUpdateVerbose(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdUpdateVerbose const *pCmd)
7208{
7209 RT_NOREF(pThis);
7210 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7211
7212 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdUpdateVerbose);
7213 Log(("SVGA_CMD_UPDATE_VERBOSE %d,%d %dx%d reason %#x\n", pCmd->x, pCmd->y, pCmd->width, pCmd->height, pCmd->reason));
7214
7215 /** @todo Multiple screens? */
7216 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
7217 if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
7218 return;
7219
7220 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->x, pCmd->y, pCmd->width, pCmd->height);
7221}
7222
7223
7224/* SVGA_CMD_RECT_FILL */
7225void vmsvgaR3CmdRectFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectFill const *pCmd)
7226{
7227 RT_NOREF(pThis, pCmd);
7228 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7229
7230 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectFill);
7231 Log(("SVGA_CMD_RECT_FILL %08X @ %d,%d (%dx%d)\n", pCmd->pixel, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
7232 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
7233}
7234
7235
7236/* SVGA_CMD_RECT_COPY */
7237void vmsvgaR3CmdRectCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectCopy const *pCmd)
7238{
7239 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7240
7241 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectCopy);
7242 Log(("SVGA_CMD_RECT_COPY %d,%d -> %d,%d %dx%d\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height));
7243
7244 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
7245 AssertPtrReturnVoid(pScreen);
7246
7247 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
7248 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
7249 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
7250 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
7251 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
7252 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
7253 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
7254
7255 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
7256 pCmd->width, pCmd->height, pThis->vram_size);
7257 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
7258}
7259
7260
7261/* SVGA_CMD_RECT_ROP_COPY */
7262void vmsvgaR3CmdRectRopCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRectRopCopy const *pCmd)
7263{
7264 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7265
7266 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRectRopCopy);
7267 Log(("SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d %dx%d ROP %#X\n", pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
7268
7269 if (pCmd->rop != SVGA_ROP_COPY)
7270 {
7271 /* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
7272 * as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
7273 * respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
7274 * SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
7275 */
7276 LogRelMax(4, ("VMSVGA: SVGA_CMD_RECT_ROP_COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n",
7277 pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height, pCmd->rop));
7278 return;
7279 }
7280
7281 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
7282 AssertPtrReturnVoid(pScreen);
7283
7284 /* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
7285 ASSERT_GUEST_RETURN_VOID(pCmd->srcX < pThis->svga.u32MaxWidth);
7286 ASSERT_GUEST_RETURN_VOID(pCmd->destX < pThis->svga.u32MaxWidth);
7287 ASSERT_GUEST_RETURN_VOID(pCmd->width < pThis->svga.u32MaxWidth);
7288 ASSERT_GUEST_RETURN_VOID(pCmd->srcY < pThis->svga.u32MaxHeight);
7289 ASSERT_GUEST_RETURN_VOID(pCmd->destY < pThis->svga.u32MaxHeight);
7290 ASSERT_GUEST_RETURN_VOID(pCmd->height < pThis->svga.u32MaxHeight);
7291
7292 vmsvgaR3RectCopy(pThisCC, pScreen, pCmd->srcX, pCmd->srcY, pCmd->destX, pCmd->destY,
7293 pCmd->width, pCmd->height, pThis->vram_size);
7294 vmsvgaR3UpdateScreen(pThisCC, pScreen, pCmd->destX, pCmd->destY, pCmd->width, pCmd->height);
7295}
7296
7297
7298/* SVGA_CMD_DISPLAY_CURSOR */
7299void vmsvgaR3CmdDisplayCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDisplayCursor const *pCmd)
7300{
7301 RT_NOREF(pThis, pCmd);
7302 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7303
7304 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDisplayCursor);
7305 Log(("SVGA_CMD_DISPLAY_CURSOR id=%d state=%d\n", pCmd->id, pCmd->state));
7306 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
7307}
7308
7309
7310/* SVGA_CMD_MOVE_CURSOR */
7311void vmsvgaR3CmdMoveCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdMoveCursor const *pCmd)
7312{
7313 RT_NOREF(pThis, pCmd);
7314 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7315
7316 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdMoveCursor);
7317 Log(("SVGA_CMD_MOVE_CURSOR to %d,%d\n", pCmd->pos.x, pCmd->pos.y));
7318 LogRelMax(4, ("VMSVGA: Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
7319}
7320
7321
7322/* SVGA_CMD_DEFINE_CURSOR */
7323void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineCursor const *pCmd)
7324{
7325 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7326
7327 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineCursor);
7328 Log(("SVGA_CMD_DEFINE_CURSOR id=%d size (%dx%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
7329 pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY, pCmd->andMaskDepth, pCmd->xorMaskDepth));
7330
7331 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
7332 ASSERT_GUEST_RETURN_VOID(pCmd->andMaskDepth <= 32);
7333 ASSERT_GUEST_RETURN_VOID(pCmd->xorMaskDepth <= 32);
7334 RT_UNTRUSTED_VALIDATED_FENCE();
7335
7336 uint32_t const cbSrcAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
7337 uint32_t const cbSrcAndMask = cbSrcAndLine * pCmd->height;
7338 uint32_t const cbSrcXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
7339
7340 uint8_t const *pbSrcAndMask = (uint8_t const *)(pCmd + 1);
7341 uint8_t const *pbSrcXorMask = (uint8_t const *)(pCmd + 1) + cbSrcAndMask;
7342
7343 uint32_t const cx = pCmd->width;
7344 uint32_t const cy = pCmd->height;
7345
7346 /*
7347 * Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
7348 * The AND data uses 8-bit aligned scanlines.
7349 * The XOR data must be starting on a 32-bit boundrary.
7350 */
7351 uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
7352 uint32_t cbDstAndMask = cbDstAndLine * cy;
7353 uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
7354 uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
7355
7356 uint8_t *pbCopy = (uint8_t *)RTMemAlloc(cbCopy);
7357 AssertReturnVoid(pbCopy);
7358
7359 /* Convert the AND mask. */
7360 uint8_t *pbDst = pbCopy;
7361 uint8_t const *pbSrc = pbSrcAndMask;
7362 switch (pCmd->andMaskDepth)
7363 {
7364 case 1:
7365 if (cbSrcAndLine == cbDstAndLine)
7366 memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
7367 else
7368 {
7369 Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
7370 for (uint32_t y = 0; y < cy; y++)
7371 {
7372 memcpy(pbDst, pbSrc, cbDstAndLine);
7373 pbDst += cbDstAndLine;
7374 pbSrc += cbSrcAndLine;
7375 }
7376 }
7377 break;
7378 /* Should take the XOR mask into account for the multi-bit AND mask. */
7379 case 8:
7380 for (uint32_t y = 0; y < cy; y++)
7381 {
7382 for (uint32_t x = 0; x < cx; )
7383 {
7384 uint8_t bDst = 0;
7385 uint8_t fBit = 0x80;
7386 do
7387 {
7388 uintptr_t const idxPal = pbSrc[x] * 3;
7389 if ((( pThis->last_palette[idxPal]
7390 | (pThis->last_palette[idxPal] >> 8)
7391 | (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
7392 bDst |= fBit;
7393 fBit >>= 1;
7394 x++;
7395 } while (x < cx && (x & 7));
7396 pbDst[(x - 1) / 8] = bDst;
7397 }
7398 pbDst += cbDstAndLine;
7399 pbSrc += cbSrcAndLine;
7400 }
7401 break;
7402 case 15:
7403 for (uint32_t y = 0; y < cy; y++)
7404 {
7405 for (uint32_t x = 0; x < cx; )
7406 {
7407 uint8_t bDst = 0;
7408 uint8_t fBit = 0x80;
7409 do
7410 {
7411 if ((pbSrc[x * 2] | (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
7412 bDst |= fBit;
7413 fBit >>= 1;
7414 x++;
7415 } while (x < cx && (x & 7));
7416 pbDst[(x - 1) / 8] = bDst;
7417 }
7418 pbDst += cbDstAndLine;
7419 pbSrc += cbSrcAndLine;
7420 }
7421 break;
7422 case 16:
7423 for (uint32_t y = 0; y < cy; y++)
7424 {
7425 for (uint32_t x = 0; x < cx; )
7426 {
7427 uint8_t bDst = 0;
7428 uint8_t fBit = 0x80;
7429 do
7430 {
7431 if ((pbSrc[x * 2] | pbSrc[x * 2 + 1]) >= 0xfc)
7432 bDst |= fBit;
7433 fBit >>= 1;
7434 x++;
7435 } while (x < cx && (x & 7));
7436 pbDst[(x - 1) / 8] = bDst;
7437 }
7438 pbDst += cbDstAndLine;
7439 pbSrc += cbSrcAndLine;
7440 }
7441 break;
7442 case 24:
7443 for (uint32_t y = 0; y < cy; y++)
7444 {
7445 for (uint32_t x = 0; x < cx; )
7446 {
7447 uint8_t bDst = 0;
7448 uint8_t fBit = 0x80;
7449 do
7450 {
7451 if ((pbSrc[x * 3] | pbSrc[x * 3 + 1] | pbSrc[x * 3 + 2]) >= 0xfc)
7452 bDst |= fBit;
7453 fBit >>= 1;
7454 x++;
7455 } while (x < cx && (x & 7));
7456 pbDst[(x - 1) / 8] = bDst;
7457 }
7458 pbDst += cbDstAndLine;
7459 pbSrc += cbSrcAndLine;
7460 }
7461 break;
7462 case 32:
7463 for (uint32_t y = 0; y < cy; y++)
7464 {
7465 for (uint32_t x = 0; x < cx; )
7466 {
7467 uint8_t bDst = 0;
7468 uint8_t fBit = 0x80;
7469 do
7470 {
7471 if ((pbSrc[x * 4] | pbSrc[x * 4 + 1] | pbSrc[x * 4 + 2] | pbSrc[x * 4 + 3]) >= 0xfc)
7472 bDst |= fBit;
7473 fBit >>= 1;
7474 x++;
7475 } while (x < cx && (x & 7));
7476 pbDst[(x - 1) / 8] = bDst;
7477 }
7478 pbDst += cbDstAndLine;
7479 pbSrc += cbSrcAndLine;
7480 }
7481 break;
7482 default:
7483 RTMemFreeZ(pbCopy, cbCopy);
7484 AssertFailedReturnVoid();
7485 }
7486
7487 /* Convert the XOR mask. */
7488 uint32_t *pu32Dst = (uint32_t *)(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
7489 pbSrc = pbSrcXorMask;
7490 switch (pCmd->xorMaskDepth)
7491 {
7492 case 1:
7493 for (uint32_t y = 0; y < cy; y++)
7494 {
7495 for (uint32_t x = 0; x < cx; )
7496 {
7497 /* most significant bit is the left most one. */
7498 uint8_t bSrc = pbSrc[x / 8];
7499 do
7500 {
7501 *pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
7502 bSrc <<= 1;
7503 x++;
7504 } while ((x & 7) && x < cx);
7505 }
7506 pbSrc += cbSrcXorLine;
7507 }
7508 break;
7509 case 8:
7510 for (uint32_t y = 0; y < cy; y++)
7511 {
7512 for (uint32_t x = 0; x < cx; x++)
7513 {
7514 uint32_t u = pThis->last_palette[pbSrc[x]];
7515 *pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
7516 }
7517 pbSrc += cbSrcXorLine;
7518 }
7519 break;
7520 case 15: /* Src: RGB-5-5-5 */
7521 for (uint32_t y = 0; y < cy; y++)
7522 {
7523 for (uint32_t x = 0; x < cx; x++)
7524 {
7525 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
7526 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
7527 ((uValue >> 5) & 0x1f) << 3,
7528 ((uValue >> 10) & 0x1f) << 3, 0);
7529 }
7530 pbSrc += cbSrcXorLine;
7531 }
7532 break;
7533 case 16: /* Src: RGB-5-6-5 */
7534 for (uint32_t y = 0; y < cy; y++)
7535 {
7536 for (uint32_t x = 0; x < cx; x++)
7537 {
7538 uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
7539 *pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
7540 ((uValue >> 5) & 0x3f) << 2,
7541 ((uValue >> 11) & 0x1f) << 3, 0);
7542 }
7543 pbSrc += cbSrcXorLine;
7544 }
7545 break;
7546 case 24:
7547 for (uint32_t y = 0; y < cy; y++)
7548 {
7549 for (uint32_t x = 0; x < cx; x++)
7550 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*3], pbSrc[x*3 + 1], pbSrc[x*3 + 2], 0);
7551 pbSrc += cbSrcXorLine;
7552 }
7553 break;
7554 case 32:
7555 for (uint32_t y = 0; y < cy; y++)
7556 {
7557 for (uint32_t x = 0; x < cx; x++)
7558 *pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x*4], pbSrc[x*4 + 1], pbSrc[x*4 + 2], 0);
7559 pbSrc += cbSrcXorLine;
7560 }
7561 break;
7562 default:
7563 RTMemFreeZ(pbCopy, cbCopy);
7564 AssertFailedReturnVoid();
7565 }
7566
7567 /*
7568 * Pass it to the frontend/whatever.
7569 */
7570 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, false /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
7571 cx, cy, pbCopy, cbCopy);
7572}
7573
7574
7575/* SVGA_CMD_DEFINE_ALPHA_CURSOR */
7576void vmsvgaR3CmdDefineAlphaCursor(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineAlphaCursor const *pCmd)
7577{
7578 RT_NOREF(pThis);
7579 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7580
7581 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineAlphaCursor);
7582 Log(("VMSVGA cmd: SVGA_CMD_DEFINE_ALPHA_CURSOR id=%d size (%dx%d) hotspot (%d,%d)\n", pCmd->id, pCmd->width, pCmd->height, pCmd->hotspotX, pCmd->hotspotY));
7583
7584 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
7585 ASSERT_GUEST_RETURN_VOID(pCmd->height < 2048 && pCmd->width < 2048);
7586 RT_UNTRUSTED_VALIDATED_FENCE();
7587
7588 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
7589 uint32_t cbAndMask = (pCmd->width + 7) / 8 * pCmd->height; /* size of the AND mask */
7590 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
7591 uint32_t cbXorMask = pCmd->width * sizeof(uint32_t) * pCmd->height; /* + size of the XOR mask (32-bit BRGA format) */
7592 uint32_t cbCursorShape = cbAndMask + cbXorMask;
7593
7594 uint8_t *pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
7595 AssertPtrReturnVoid(pCursorCopy);
7596
7597 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
7598 memset(pCursorCopy, 0xff, cbAndMask);
7599 /* Colour data */
7600 memcpy(pCursorCopy + cbAndMask, pCmd + 1, cbXorMask);
7601
7602 vmsvgaR3InstallNewCursor(pThisCC, pSvgaR3State, true /*fAlpha*/, pCmd->hotspotX, pCmd->hotspotY,
7603 pCmd->width, pCmd->height, pCursorCopy, cbCursorShape);
7604}
7605
7606
7607/* SVGA_CMD_ESCAPE */
7608void vmsvgaR3CmdEscape(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdEscape const *pCmd)
7609{
7610 RT_NOREF(pThis);
7611 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7612
7613 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdEscape);
7614
7615 if (pCmd->nsid == SVGA_ESCAPE_NSID_VMWARE)
7616 {
7617 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(uint32_t));
7618 RT_UNTRUSTED_VALIDATED_FENCE();
7619
7620 uint32_t const cmd = *(uint32_t *)(pCmd + 1);
7621 Log(("SVGA_CMD_ESCAPE (%#x %#x) VMWARE cmd=%#x\n", pCmd->nsid, pCmd->size, cmd));
7622
7623 switch (cmd)
7624 {
7625 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
7626 {
7627 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pCmd + 1);
7628 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(pVideoCmd->header));
7629 RT_UNTRUSTED_VALIDATED_FENCE();
7630
7631 uint32_t const cRegs = (pCmd->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
7632
7633 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %#x\n", pVideoCmd->header.streamId));
7634 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
7635 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %#x val %#x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
7636 RT_NOREF_PV(pVideoCmd);
7637 break;
7638 }
7639
7640 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
7641 {
7642 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pCmd + 1);
7643 ASSERT_GUEST_RETURN_VOID(pCmd->size >= sizeof(*pVideoCmd));
7644 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %#x\n", pVideoCmd->streamId));
7645 RT_NOREF_PV(pVideoCmd);
7646 break;
7647 }
7648
7649 default:
7650 Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %#x\n", cmd));
7651 break;
7652 }
7653 }
7654 else
7655 Log(("SVGA_CMD_ESCAPE %#x %#x\n", pCmd->nsid, pCmd->size));
7656}
7657
7658
7659/* SVGA_CMD_DEFINE_SCREEN */
7660void vmsvgaR3CmdDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineScreen const *pCmd)
7661{
7662 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7663
7664 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineScreen);
7665 Log(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
7666 pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
7667 pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
7668
7669 uint32_t const idScreen = pCmd->screen.id;
7670 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
7671
7672 uint32_t const uWidth = pCmd->screen.size.width;
7673 ASSERT_GUEST_RETURN_VOID(uWidth <= pThis->svga.u32MaxWidth);
7674
7675 uint32_t const uHeight = pCmd->screen.size.height;
7676 ASSERT_GUEST_RETURN_VOID(uHeight <= pThis->svga.u32MaxHeight);
7677
7678 uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
7679 uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
7680 ASSERT_GUEST_RETURN_VOID(cbWidth <= cbPitch);
7681
7682 uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
7683 ASSERT_GUEST_RETURN_VOID(uScreenOffset < pThis->vram_size);
7684
7685 uint32_t const cbVram = pThis->vram_size - uScreenOffset;
7686 /* If we have a not zero pitch, then height can't exceed the available VRAM. */
7687 ASSERT_GUEST_RETURN_VOID( (uHeight == 0 && cbPitch == 0)
7688 || (cbPitch > 0 && uHeight <= cbVram / cbPitch));
7689 RT_UNTRUSTED_VALIDATED_FENCE();
7690
7691 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
7692 Assert(pScreen->idScreen == idScreen);
7693 pScreen->fDefined = true;
7694 pScreen->fModified = true;
7695 pScreen->fuScreen = pCmd->screen.flags;
7696 if (!RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE | SVGA_SCREEN_BLANKING)))
7697 {
7698 /* Not blanked. */
7699 ASSERT_GUEST_RETURN_VOID(uWidth > 0 && uHeight > 0);
7700 RT_UNTRUSTED_VALIDATED_FENCE();
7701
7702 pScreen->xOrigin = pCmd->screen.root.x;
7703 pScreen->yOrigin = pCmd->screen.root.y;
7704 pScreen->cWidth = uWidth;
7705 pScreen->cHeight = uHeight;
7706 pScreen->offVRAM = uScreenOffset;
7707 pScreen->cbPitch = cbPitch;
7708 pScreen->cBpp = 32;
7709 }
7710 else
7711 {
7712 /* Screen blanked. Keep old values. */
7713 }
7714
7715 pThis->svga.fGFBRegisters = false;
7716 vmsvgaR3ChangeMode(pThis, pThisCC);
7717
7718#ifdef VBOX_WITH_VMSVGA3D
7719 if (RT_LIKELY(pThis->svga.f3DEnabled))
7720 vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
7721#endif
7722}
7723
7724
7725/* SVGA_CMD_DESTROY_SCREEN */
7726void vmsvgaR3CmdDestroyScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDestroyScreen const *pCmd)
7727{
7728 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7729
7730 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDestroyScreen);
7731 Log(("SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
7732
7733 uint32_t const idScreen = pCmd->screenId;
7734 ASSERT_GUEST_RETURN_VOID(idScreen < RT_ELEMENTS(pSvgaR3State->aScreens));
7735 RT_UNTRUSTED_VALIDATED_FENCE();
7736
7737 VMSVGASCREENOBJECT *pScreen = &pSvgaR3State->aScreens[idScreen];
7738 Assert(pScreen->idScreen == idScreen);
7739 vmsvgaR3DestroyScreen(pThis, pThisCC, pScreen);
7740}
7741
7742
7743/* SVGA_CMD_DEFINE_GMRFB */
7744void vmsvgaR3CmdDefineGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMRFB const *pCmd)
7745{
7746 RT_NOREF(pThis);
7747 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7748
7749 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmrFb);
7750 Log(("SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n",
7751 pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
7752
7753 pSvgaR3State->GMRFB.ptr = pCmd->ptr;
7754 pSvgaR3State->GMRFB.bytesPerLine = pCmd->bytesPerLine;
7755 pSvgaR3State->GMRFB.format = pCmd->format;
7756}
7757
7758
7759/* SVGA_CMD_BLIT_GMRFB_TO_SCREEN */
7760void vmsvgaR3CmdBlitGMRFBToScreen(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitGMRFBToScreen const *pCmd)
7761{
7762 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7763
7764 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitGmrFbToScreen);
7765 Log(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
7766 pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
7767
7768 ASSERT_GUEST_RETURN_VOID(pCmd->destScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
7769 RT_UNTRUSTED_VALIDATED_FENCE();
7770
7771 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
7772 AssertPtrReturnVoid(pScreen);
7773
7774 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp ? */
7775 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
7776
7777 /* Clip destRect to the screen dimensions. */
7778 SVGASignedRect screenRect;
7779 screenRect.left = 0;
7780 screenRect.top = 0;
7781 screenRect.right = pScreen->cWidth;
7782 screenRect.bottom = pScreen->cHeight;
7783 SVGASignedRect clipRect = pCmd->destRect;
7784 vmsvgaR3ClipRect(&screenRect, &clipRect);
7785 RT_UNTRUSTED_VALIDATED_FENCE();
7786
7787 uint32_t const width = clipRect.right - clipRect.left;
7788 uint32_t const height = clipRect.bottom - clipRect.top;
7789
7790 if ( width == 0
7791 || height == 0)
7792 return; /* Nothing to do. */
7793
7794 int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
7795 int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
7796
7797 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
7798 * Prepare parameters for vmsvgaR3GmrTransfer.
7799 */
7800 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
7801
7802 /* Destination: host buffer which describes the screen 0 VRAM.
7803 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
7804 */
7805 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
7806 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
7807 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
7808 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
7809 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
7810 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
7811 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
7812 + cbScanline * clipRect.top;
7813 int32_t const cbHstPitch = cbScanline;
7814
7815 /* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
7816 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
7817 uint32_t const offGst = (srcx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
7818 + pSvgaR3State->GMRFB.bytesPerLine * srcy;
7819 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
7820
7821 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
7822 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7823 gstPtr, offGst, cbGstPitch,
7824 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
7825 AssertRC(rc);
7826 vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
7827}
7828
7829
7830/* SVGA_CMD_BLIT_SCREEN_TO_GMRFB */
7831void vmsvgaR3CmdBlitScreenToGMRFB(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdBlitScreenToGMRFB const *pCmd)
7832{
7833 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7834
7835 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdBlitScreentoGmrFb);
7836 /* Note! This can fetch 3d render results as well!! */
7837 Log(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
7838 pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
7839
7840 ASSERT_GUEST_RETURN_VOID(pCmd->srcScreenId < RT_ELEMENTS(pSvgaR3State->aScreens));
7841 RT_UNTRUSTED_VALIDATED_FENCE();
7842
7843 VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
7844 AssertPtrReturnVoid(pScreen);
7845
7846 /** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp ? */
7847 AssertReturnVoid(pSvgaR3State->GMRFB.format.bitsPerPixel == pScreen->cBpp);
7848
7849 /* Clip destRect to the screen dimensions. */
7850 SVGASignedRect screenRect;
7851 screenRect.left = 0;
7852 screenRect.top = 0;
7853 screenRect.right = pScreen->cWidth;
7854 screenRect.bottom = pScreen->cHeight;
7855 SVGASignedRect clipRect = pCmd->srcRect;
7856 vmsvgaR3ClipRect(&screenRect, &clipRect);
7857 RT_UNTRUSTED_VALIDATED_FENCE();
7858
7859 uint32_t const width = clipRect.right - clipRect.left;
7860 uint32_t const height = clipRect.bottom - clipRect.top;
7861
7862 if ( width == 0
7863 || height == 0)
7864 return; /* Nothing to do. */
7865
7866 int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
7867 int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
7868
7869 /* Copy the defined by GMRFB image to the screen 0 VRAM area.
7870 * Prepare parameters for vmsvgaR3GmrTransfer.
7871 */
7872 AssertReturnVoid(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
7873
7874 /* Source: host buffer which describes the screen 0 VRAM.
7875 * Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
7876 */
7877 uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
7878 uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
7879 width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
7880 uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
7881 if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
7882 cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
7883 uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
7884 + cbScanline * clipRect.top;
7885 int32_t const cbHstPitch = cbScanline;
7886
7887 /* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
7888 SVGAGuestPtr const gstPtr = pSvgaR3State->GMRFB.ptr;
7889 uint32_t const offGst = (dstx * RT_ALIGN(pSvgaR3State->GMRFB.format.bitsPerPixel, 8)) / 8
7890 + pSvgaR3State->GMRFB.bytesPerLine * dsty;
7891 int32_t const cbGstPitch = pSvgaR3State->GMRFB.bytesPerLine;
7892
7893 int rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
7894 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
7895 gstPtr, offGst, cbGstPitch,
7896 (width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
7897 AssertRC(rc);
7898}
7899
7900
7901/* SVGA_CMD_ANNOTATION_FILL */
7902void vmsvgaR3CmdAnnotationFill(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationFill const *pCmd)
7903{
7904 RT_NOREF(pThis);
7905 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7906
7907 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationFill);
7908 Log(("SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
7909
7910 pSvgaR3State->colorAnnotation = pCmd->color;
7911}
7912
7913
7914/* SVGA_CMD_ANNOTATION_COPY */
7915void vmsvgaR3CmdAnnotationCopy(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdAnnotationCopy const *pCmd)
7916{
7917 RT_NOREF(pThis, pCmd);
7918 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7919
7920 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdAnnotationCopy);
7921 Log(("SVGA_CMD_ANNOTATION_COPY srcOrigin %d,%d, srcScreenId %u\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->srcScreenId));
7922
7923 AssertFailed();
7924}
7925
7926
7927#ifdef VBOX_WITH_VMSVGA3D
7928/* SVGA_CMD_DEFINE_GMR2 */
7929void vmsvgaR3CmdDefineGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdDefineGMR2 const *pCmd)
7930{
7931 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7932
7933 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2);
7934 Log(("SVGA_CMD_DEFINE_GMR2 id=%#x %#x pages\n", pCmd->gmrId, pCmd->numPages));
7935
7936 /* Validate current GMR id. */
7937 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
7938 ASSERT_GUEST_RETURN_VOID(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
7939 RT_UNTRUSTED_VALIDATED_FENCE();
7940
7941 if (!pCmd->numPages)
7942 {
7943 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Free);
7944 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
7945 }
7946 else
7947 {
7948 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
7949 if (pGMR->cMaxPages)
7950 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdDefineGmr2Modify);
7951
7952 /* Not sure if we should always free the descriptor, but for simplicity
7953 we do so if the new size is smaller than the current. */
7954 /** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
7955 if (pGMR->cbTotal / X86_PAGE_SIZE > pCmd->numPages)
7956 vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
7957
7958 pGMR->cMaxPages = pCmd->numPages;
7959 /* The rest is done by the REMAP_GMR2 command. */
7960 }
7961}
7962
7963
7964/* SVGA_CMD_REMAP_GMR2 */
7965void vmsvgaR3CmdRemapGMR2(PVGASTATE pThis, PVGASTATECC pThisCC, SVGAFifoCmdRemapGMR2 const *pCmd)
7966{
7967 PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
7968
7969 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2);
7970 Log(("SVGA_CMD_REMAP_GMR2 id=%#x flags=%#x offset=%#x npages=%#x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
7971
7972 /* Validate current GMR id and size. */
7973 ASSERT_GUEST_RETURN_VOID(pCmd->gmrId < pThis->svga.cGMR);
7974 RT_UNTRUSTED_VALIDATED_FENCE();
7975 PGMR pGMR = &pSvgaR3State->paGMR[pCmd->gmrId];
7976 ASSERT_GUEST_RETURN_VOID( (uint64_t)pCmd->offsetPages + pCmd->numPages
7977 <= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
7978 ASSERT_GUEST_RETURN_VOID(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
7979
7980 if (pCmd->numPages == 0)
7981 return;
7982 RT_UNTRUSTED_VALIDATED_FENCE();
7983
7984 /* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
7985 uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
7986
7987 /*
7988 * We flatten the existing descriptors into a page array, overwrite the
7989 * pages specified in this command and then recompress the descriptor.
7990 */
7991 /** @todo Optimize the GMR remap algorithm! */
7992
7993 /* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
7994 uint64_t *paNewPage64 = NULL;
7995 if (pGMR->paDesc)
7996 {
7997 STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdRemapGmr2Modify);
7998
7999 paNewPage64 = (uint64_t *)RTMemAllocZ(cNewTotalPages * sizeof(uint64_t));
8000 AssertPtrReturnVoid(paNewPage64);
8001
8002 uint32_t idxPage = 0;
8003 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
8004 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
8005 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
8006 AssertReturnVoidStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
8007 RT_UNTRUSTED_VALIDATED_FENCE();
8008 }
8009
8010 /* Free the old GMR if present. */
8011 if (pGMR->paDesc)
8012 RTMemFree(pGMR->paDesc);
8013
8014 /* Allocate the maximum amount possible (everything non-continuous) */
8015 PVMSVGAGMRDESCRIPTOR paDescs;
8016 pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
8017 AssertReturnVoidStmt(paDescs, RTMemFree(paNewPage64));
8018
8019 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
8020 {
8021 /** @todo */
8022 AssertFailed();
8023 pGMR->numDescriptors = 0;
8024 }
8025 else
8026 {
8027 uint32_t *paPages32 = (uint32_t *)(pCmd + 1);
8028 uint64_t *paPages64 = (uint64_t *)(pCmd + 1);
8029 bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
8030
8031 uint32_t cPages;
8032 if (paNewPage64)
8033 {
8034 /* Overwrite the old page array with the new page values. */
8035 if (fGCPhys64)
8036 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
8037 paNewPage64[i] = paPages64[i - pCmd->offsetPages];
8038 else
8039 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
8040 paNewPage64[i] = paPages32[i - pCmd->offsetPages];
8041
8042 /* Use the updated page array instead of the command data. */
8043 fGCPhys64 = true;
8044 paPages64 = paNewPage64;
8045 cPages = cNewTotalPages;
8046 }
8047 else
8048 cPages = pCmd->numPages;
8049
8050 /* The first page. */
8051 /** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
8052 * applied to paNewPage64. */
8053 RTGCPHYS GCPhys;
8054 if (fGCPhys64)
8055 GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
8056 else
8057 GCPhys = (RTGCPHYS)paPages32[0] << GUEST_PAGE_SHIFT;
8058 paDescs[0].GCPhys = GCPhys;
8059 paDescs[0].numPages = 1;
8060
8061 /* Subsequent pages. */
8062 uint32_t iDescriptor = 0;
8063 for (uint32_t i = 1; i < cPages; i++)
8064 {
8065 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
8066 GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
8067 else
8068 GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
8069
8070 /* Continuous physical memory? */
8071 if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
8072 {
8073 Assert(paDescs[iDescriptor].numPages);
8074 paDescs[iDescriptor].numPages++;
8075 Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
8076 }
8077 else
8078 {
8079 iDescriptor++;
8080 paDescs[iDescriptor].GCPhys = GCPhys;
8081 paDescs[iDescriptor].numPages = 1;
8082 Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
8083 }
8084 }
8085
8086 pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
8087 Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
8088 pGMR->numDescriptors = iDescriptor + 1;
8089 }
8090
8091 if (paNewPage64)
8092 RTMemFree(paNewPage64);
8093}
8094
8095
8096/**
8097 * Free the specified GMR
8098 *
8099 * @param pThisCC The VGA/VMSVGA state for ring-3.
8100 * @param idGMR GMR id
8101 */
8102void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
8103{
8104 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8105
8106 /* Free the old descriptor if present. */
8107 PGMR pGMR = &pSVGAState->paGMR[idGMR];
8108 if ( pGMR->numDescriptors
8109 || pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
8110 {
8111# ifdef DEBUG_GMR_ACCESS
8112 VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
8113# endif
8114
8115 Assert(pGMR->paDesc);
8116 RTMemFree(pGMR->paDesc);
8117 pGMR->paDesc = NULL;
8118 pGMR->numDescriptors = 0;
8119 pGMR->cbTotal = 0;
8120 pGMR->cMaxPages = 0;
8121 }
8122 Assert(!pGMR->cMaxPages);
8123 Assert(!pGMR->cbTotal);
8124}
8125#endif /* VBOX_WITH_VMSVGA3D */
8126
8127
8128/**
8129 * Copy between a GMR and a host memory buffer.
8130 *
8131 * @returns VBox status code.
8132 * @param pThis The shared VGA/VMSVGA instance data.
8133 * @param pThisCC The VGA/VMSVGA state for ring-3.
8134 * @param enmTransferType Transfer type (read/write)
8135 * @param pbHstBuf Host buffer pointer (valid)
8136 * @param cbHstBuf Size of host buffer (valid)
8137 * @param offHst Host buffer offset of the first scanline
8138 * @param cbHstPitch Destination buffer pitch
8139 * @param gstPtr GMR description
8140 * @param offGst Guest buffer offset of the first scanline
8141 * @param cbGstPitch Guest buffer pitch
8142 * @param cbWidth Width in bytes to copy
8143 * @param cHeight Number of scanllines to copy
8144 */
8145int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
8146 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
8147 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
8148 uint32_t cbWidth, uint32_t cHeight)
8149{
8150 PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
8151 PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
8152 int rc;
8153
8154 LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
8155 enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
8156 pbHstBuf, cbHstBuf, offHst, cbHstPitch,
8157 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
8158 AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
8159
8160 PGMR pGMR;
8161 uint32_t cbGmr; /* The GMR size in bytes. */
8162 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
8163 {
8164 pGMR = NULL;
8165 cbGmr = pThis->vram_size;
8166 }
8167 else
8168 {
8169 AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
8170 RT_UNTRUSTED_VALIDATED_FENCE();
8171 pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
8172 cbGmr = pGMR->cbTotal;
8173 }
8174
8175 /*
8176 * GMR
8177 */
8178 /* Calculate GMR offset of the data to be copied. */
8179 AssertMsgReturn(gstPtr.offset < cbGmr,
8180 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
8181 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
8182 VERR_INVALID_PARAMETER);
8183 RT_UNTRUSTED_VALIDATED_FENCE();
8184 AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
8185 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
8186 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
8187 VERR_INVALID_PARAMETER);
8188 RT_UNTRUSTED_VALIDATED_FENCE();
8189 uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
8190
8191 /* Verify that cbWidth is less than scanline and fits into the GMR. */
8192 uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
8193 AssertMsgReturn(cbGmrScanline != 0,
8194 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
8195 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
8196 VERR_INVALID_PARAMETER);
8197 RT_UNTRUSTED_VALIDATED_FENCE();
8198 AssertMsgReturn(cbWidth <= cbGmrScanline,
8199 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
8200 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
8201 VERR_INVALID_PARAMETER);
8202 AssertMsgReturn(cbWidth <= cbGmr - offGmr,
8203 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
8204 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
8205 VERR_INVALID_PARAMETER);
8206 RT_UNTRUSTED_VALIDATED_FENCE();
8207
8208 /* How many bytes are available for the data in the GMR. */
8209 uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
8210
8211 /* How many scanlines would fit into the available data. */
8212 uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
8213 uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
8214 if (cbWidth <= cbGmrLastScanline)
8215 ++cGmrScanlines;
8216
8217 if (cHeight > cGmrScanlines)
8218 cHeight = cGmrScanlines;
8219
8220 AssertMsgReturn(cHeight > 0,
8221 ("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
8222 gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
8223 VERR_INVALID_PARAMETER);
8224 RT_UNTRUSTED_VALIDATED_FENCE();
8225
8226 /*
8227 * Host buffer.
8228 */
8229 AssertMsgReturn(offHst < cbHstBuf,
8230 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
8231 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
8232 VERR_INVALID_PARAMETER);
8233
8234 /* Verify that cbWidth is less than scanline and fits into the buffer. */
8235 uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
8236 AssertMsgReturn(cbHstScanline != 0,
8237 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
8238 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
8239 VERR_INVALID_PARAMETER);
8240 AssertMsgReturn(cbWidth <= cbHstScanline,
8241 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
8242 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
8243 VERR_INVALID_PARAMETER);
8244 AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
8245 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
8246 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
8247 VERR_INVALID_PARAMETER);
8248
8249 /* How many bytes are available for the data in the buffer. */
8250 uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
8251
8252 /* How many scanlines would fit into the available data. */
8253 uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
8254 uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
8255 if (cbWidth <= cbHstLastScanline)
8256 ++cHstScanlines;
8257
8258 if (cHeight > cHstScanlines)
8259 cHeight = cHstScanlines;
8260
8261 AssertMsgReturn(cHeight > 0,
8262 ("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
8263 pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
8264 VERR_INVALID_PARAMETER);
8265
8266 uint8_t *pbHst = pbHstBuf + offHst;
8267
8268 /* Shortcut for the framebuffer. */
8269 if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
8270 {
8271 uint8_t *pbGst = pThisCC->pbVRam + offGmr;
8272
8273 uint8_t const *pbSrc;
8274 int32_t cbSrcPitch;
8275 uint8_t *pbDst;
8276 int32_t cbDstPitch;
8277
8278 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
8279 {
8280 pbSrc = pbHst;
8281 cbSrcPitch = cbHstPitch;
8282 pbDst = pbGst;
8283 cbDstPitch = cbGstPitch;
8284 }
8285 else
8286 {
8287 pbSrc = pbGst;
8288 cbSrcPitch = cbGstPitch;
8289 pbDst = pbHst;
8290 cbDstPitch = cbHstPitch;
8291 }
8292
8293 if ( cbWidth == (uint32_t)cbGstPitch
8294 && cbGstPitch == cbHstPitch)
8295 {
8296 /* Entire scanlines, positive pitch. */
8297 memcpy(pbDst, pbSrc, cbWidth * cHeight);
8298 }
8299 else
8300 {
8301 for (uint32_t i = 0; i < cHeight; ++i)
8302 {
8303 memcpy(pbDst, pbSrc, cbWidth);
8304
8305 pbDst += cbDstPitch;
8306 pbSrc += cbSrcPitch;
8307 }
8308 }
8309 return VINF_SUCCESS;
8310 }
8311
8312 AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
8313 AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
8314
8315 PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
8316 uint32_t iDesc = 0; /* Index in the descriptor array. */
8317 uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
8318 uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
8319 uint8_t *pbHstScanline = pbHst; /* Host address of the scanline which is being copied. */
8320 for (uint32_t i = 0; i < cHeight; ++i)
8321 {
8322 uint32_t cbCurrentWidth = cbWidth;
8323 uint32_t offGmrCurrent = offGmrScanline;
8324 uint8_t *pbCurrentHost = pbHstScanline;
8325
8326 /* Find the right descriptor */
8327 while (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE <= offGmrCurrent)
8328 {
8329 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
8330 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
8331 ++iDesc;
8332 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
8333 }
8334
8335 while (cbCurrentWidth)
8336 {
8337 uint32_t cbToCopy;
8338
8339 if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE)
8340 cbToCopy = cbCurrentWidth;
8341 else
8342 {
8343 cbToCopy = (offDesc + paDesc[iDesc].numPages * GUEST_PAGE_SIZE - offGmrCurrent);
8344 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
8345 }
8346
8347 RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
8348
8349 Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
8350
8351 /*
8352 * We are deliberately using the non-PCI version of PDMDevHlpPCIPhys[Read|Write] as the
8353 * guest-side VMSVGA driver seems to allocate non-DMA (physical memory) addresses,
8354 * see @bugref{9654#c75}.
8355 */
8356 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
8357 rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
8358 else
8359 rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
8360 AssertRCBreak(rc);
8361
8362 cbCurrentWidth -= cbToCopy;
8363 offGmrCurrent += cbToCopy;
8364 pbCurrentHost += cbToCopy;
8365
8366 /* Go to the next descriptor if there's anything left. */
8367 if (cbCurrentWidth)
8368 {
8369 offDesc += paDesc[iDesc].numPages * GUEST_PAGE_SIZE;
8370 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
8371 ++iDesc;
8372 AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
8373 }
8374 }
8375
8376 offGmrScanline += cbGstPitch;
8377 pbHstScanline += cbHstPitch;
8378 }
8379
8380 return VINF_SUCCESS;
8381}
8382
8383
8384/**
8385 * Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
8386 *
8387 * @param pSizeSrc Source surface dimensions.
8388 * @param pSizeDest Destination surface dimensions.
8389 * @param pBox Coordinates to be clipped.
8390 */
8391void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox)
8392{
8393 /* Src x, w */
8394 if (pBox->srcx > pSizeSrc->width)
8395 pBox->srcx = pSizeSrc->width;
8396 if (pBox->w > pSizeSrc->width - pBox->srcx)
8397 pBox->w = pSizeSrc->width - pBox->srcx;
8398
8399 /* Src y, h */
8400 if (pBox->srcy > pSizeSrc->height)
8401 pBox->srcy = pSizeSrc->height;
8402 if (pBox->h > pSizeSrc->height - pBox->srcy)
8403 pBox->h = pSizeSrc->height - pBox->srcy;
8404
8405 /* Src z, d */
8406 if (pBox->srcz > pSizeSrc->depth)
8407 pBox->srcz = pSizeSrc->depth;
8408 if (pBox->d > pSizeSrc->depth - pBox->srcz)
8409 pBox->d = pSizeSrc->depth - pBox->srcz;
8410
8411 /* Dest x, w */
8412 if (pBox->x > pSizeDest->width)
8413 pBox->x = pSizeDest->width;
8414 if (pBox->w > pSizeDest->width - pBox->x)
8415 pBox->w = pSizeDest->width - pBox->x;
8416
8417 /* Dest y, h */
8418 if (pBox->y > pSizeDest->height)
8419 pBox->y = pSizeDest->height;
8420 if (pBox->h > pSizeDest->height - pBox->y)
8421 pBox->h = pSizeDest->height - pBox->y;
8422
8423 /* Dest z, d */
8424 if (pBox->z > pSizeDest->depth)
8425 pBox->z = pSizeDest->depth;
8426 if (pBox->d > pSizeDest->depth - pBox->z)
8427 pBox->d = pSizeDest->depth - pBox->z;
8428}
8429
8430
8431/**
8432 * Unsigned coordinates in pBox. Clip to [0; pSize).
8433 *
8434 * @param pSize Source surface dimensions.
8435 * @param pBox Coordinates to be clipped.
8436 */
8437void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox)
8438{
8439 /* x, w */
8440 if (pBox->x > pSize->width)
8441 pBox->x = pSize->width;
8442 if (pBox->w > pSize->width - pBox->x)
8443 pBox->w = pSize->width - pBox->x;
8444
8445 /* y, h */
8446 if (pBox->y > pSize->height)
8447 pBox->y = pSize->height;
8448 if (pBox->h > pSize->height - pBox->y)
8449 pBox->h = pSize->height - pBox->y;
8450
8451 /* z, d */
8452 if (pBox->z > pSize->depth)
8453 pBox->z = pSize->depth;
8454 if (pBox->d > pSize->depth - pBox->z)
8455 pBox->d = pSize->depth - pBox->z;
8456}
8457
8458
8459/**
8460 * Clip.
8461 *
8462 * @param pBound Bounding rectangle.
8463 * @param pRect Rectangle to be clipped.
8464 */
8465void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect)
8466{
8467 int32_t left;
8468 int32_t top;
8469 int32_t right;
8470 int32_t bottom;
8471
8472 /* Right order. */
8473 Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
8474 if (pRect->left < pRect->right)
8475 {
8476 left = pRect->left;
8477 right = pRect->right;
8478 }
8479 else
8480 {
8481 left = pRect->right;
8482 right = pRect->left;
8483 }
8484 if (pRect->top < pRect->bottom)
8485 {
8486 top = pRect->top;
8487 bottom = pRect->bottom;
8488 }
8489 else
8490 {
8491 top = pRect->bottom;
8492 bottom = pRect->top;
8493 }
8494
8495 if (left < pBound->left)
8496 left = pBound->left;
8497 if (right < pBound->left)
8498 right = pBound->left;
8499
8500 if (left > pBound->right)
8501 left = pBound->right;
8502 if (right > pBound->right)
8503 right = pBound->right;
8504
8505 if (top < pBound->top)
8506 top = pBound->top;
8507 if (bottom < pBound->top)
8508 bottom = pBound->top;
8509
8510 if (top > pBound->bottom)
8511 top = pBound->bottom;
8512 if (bottom > pBound->bottom)
8513 bottom = pBound->bottom;
8514
8515 pRect->left = left;
8516 pRect->right = right;
8517 pRect->top = top;
8518 pRect->bottom = bottom;
8519}
8520
8521
8522/**
8523 * Clip.
8524 *
8525 * @param pBound Bounding rectangle.
8526 * @param pRect Rectangle to be clipped.
8527 */
8528void vmsvgaR3Clip3dRect(SVGA3dRect const *pBound, SVGA3dRect RT_UNTRUSTED_GUEST *pRect)
8529{
8530 uint32_t const leftBound = pBound->x;
8531 uint32_t const rightBound = pBound->x + pBound->w;
8532 uint32_t const topBound = pBound->y;
8533 uint32_t const bottomBound = pBound->y + pBound->h;
8534
8535 uint32_t x = pRect->x;
8536 uint32_t y = pRect->y;
8537 uint32_t w = pRect->w;
8538 uint32_t h = pRect->h;
8539
8540 /* Make sure that right and bottom coordinates can be safely computed. */
8541 if (x > rightBound)
8542 x = rightBound;
8543 if (w > rightBound - x)
8544 w = rightBound - x;
8545 if (y > bottomBound)
8546 y = bottomBound;
8547 if (h > bottomBound - y)
8548 h = bottomBound - y;
8549
8550 /* Switch from x, y, w, h to left, top, right, bottom. */
8551 uint32_t left = x;
8552 uint32_t right = x + w;
8553 uint32_t top = y;
8554 uint32_t bottom = y + h;
8555
8556 /* A standard left, right, bottom, top clipping. */
8557 if (left < leftBound)
8558 left = leftBound;
8559 if (right < leftBound)
8560 right = leftBound;
8561
8562 if (left > rightBound)
8563 left = rightBound;
8564 if (right > rightBound)
8565 right = rightBound;
8566
8567 if (top < topBound)
8568 top = topBound;
8569 if (bottom < topBound)
8570 bottom = topBound;
8571
8572 if (top > bottomBound)
8573 top = bottomBound;
8574 if (bottom > bottomBound)
8575 bottom = bottomBound;
8576
8577 /* Back to x, y, w, h representation. */
8578 pRect->x = left;
8579 pRect->y = top;
8580 pRect->w = right - left;
8581 pRect->h = bottom - top;
8582}
8583
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use