VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/MsixCommon.cpp

Last change on this file was 106061, checked in by vboxsync, 3 months ago

Copyright year updates by scm.

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1/* $Id: MsixCommon.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * MSI-X support routines
4 */
5
6/*
7 * Copyright (C) 2010-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29#define LOG_GROUP LOG_GROUP_DEV_PCI
30#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
31#include <VBox/pci.h>
32#include <VBox/msi.h>
33#include <VBox/vmm/pdmdev.h>
34#include <VBox/log.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/AssertGuest.h>
37
38#include <iprt/assert.h>
39
40#include "MsiCommon.h"
41#include "DevPciInternal.h"
42#include "PciInline.h"
43
44typedef struct
45{
46 uint32_t u32MsgAddressLo;
47 uint32_t u32MsgAddressHi;
48 uint32_t u32MsgData;
49 uint32_t u32VectorControl;
50} MsixTableRecord;
51AssertCompileSize(MsixTableRecord, VBOX_MSIX_ENTRY_SIZE);
52
53
54/** @todo use accessors so that raw PCI devices work correctly with MSI-X. */
55DECLINLINE(uint16_t) msixGetMessageControl(PPDMPCIDEV pDev)
56{
57 return PCIDevGetWord(pDev, pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL);
58}
59
60DECLINLINE(bool) msixIsEnabled(PPDMPCIDEV pDev)
61{
62 return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_ENABLE) != 0;
63}
64
65DECLINLINE(bool) msixIsMasked(PPDMPCIDEV pDev)
66{
67 return (msixGetMessageControl(pDev) & VBOX_PCI_MSIX_FLAGS_FUNCMASK) != 0;
68}
69
70#ifdef IN_RING3
71DECLINLINE(uint16_t) msixTableSize(PPDMPCIDEV pDev)
72{
73 return (msixGetMessageControl(pDev) & 0x3ff) + 1;
74}
75#endif
76
77DECLINLINE(uint8_t *) msixGetPageOffset(PPDMPCIDEV pDev, uint32_t off)
78{
79 return &pDev->abMsixState[off];
80}
81
82DECLINLINE(MsixTableRecord *) msixGetVectorRecord(PPDMPCIDEV pDev, uint32_t iVector)
83{
84 return (MsixTableRecord *)msixGetPageOffset(pDev, iVector * VBOX_MSIX_ENTRY_SIZE);
85}
86
87DECLINLINE(RTGCPHYS) msixGetMsiAddress(PPDMPCIDEV pDev, uint32_t iVector)
88{
89 MsixTableRecord *pRec = msixGetVectorRecord(pDev, iVector);
90 return RT_MAKE_U64(pRec->u32MsgAddressLo & ~UINT32_C(0x3), pRec->u32MsgAddressHi);
91}
92
93DECLINLINE(uint32_t) msixGetMsiData(PPDMPCIDEV pDev, uint32_t iVector)
94{
95 return msixGetVectorRecord(pDev, iVector)->u32MsgData;
96}
97
98DECLINLINE(uint32_t) msixIsVectorMasked(PPDMPCIDEV pDev, uint32_t iVector)
99{
100 return (msixGetVectorRecord(pDev, iVector)->u32VectorControl & 0x1) != 0;
101}
102
103DECLINLINE(uint8_t *) msixPendingByte(PPDMPCIDEV pDev, uint32_t iVector)
104{
105 return msixGetPageOffset(pDev, pDev->Int.s.offMsixPba + iVector / 8);
106}
107
108DECLINLINE(void) msixSetPending(PPDMPCIDEV pDev, uint32_t iVector)
109{
110 *msixPendingByte(pDev, iVector) |= (1 << (iVector & 0x7));
111}
112
113DECLINLINE(void) msixClearPending(PPDMPCIDEV pDev, uint32_t iVector)
114{
115 *msixPendingByte(pDev, iVector) &= ~(1 << (iVector & 0x7));
116}
117
118#ifdef IN_RING3
119
120DECLINLINE(bool) msixR3IsPending(PPDMPCIDEV pDev, uint32_t iVector)
121{
122 return (*msixPendingByte(pDev, iVector) & (1 << (iVector & 0x7))) != 0;
123}
124
125static void msixR3CheckPendingVector(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t iVector)
126{
127 if (msixR3IsPending(pDev, iVector) && !msixIsVectorMasked(pDev, iVector))
128 MsixNotify(pDevIns, pPciHlp, pDev, iVector, 1 /* iLevel */, 0 /*uTagSrc*/);
129}
130
131/**
132 * @callback_method_impl{FNIOMMMIONEWREAD}
133 */
134static DECLCALLBACK(VBOXSTRICTRC) msixR3MMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
135{
136 PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
137 RT_NOREF(pDevIns);
138
139 /* Validate IOM behaviour. */
140 Assert(cb == 4);
141 Assert((off & 3) == 0);
142
143 /* Do the read if it's within the MSI state. */
144 ASSERT_GUEST_MSG_RETURN(off + cb <= pPciDev->Int.s.cbMsixRegion, ("Out of bounds access for the MSI-X region\n"),
145 VINF_IOM_MMIO_UNUSED_FF);
146 *(uint32_t *)pv = *(uint32_t *)&pPciDev->abMsixState[off];
147
148 LogFlowFunc(("off=%RGp cb=%d -> %#010RX32\n", off, cb, *(uint32_t *)pv));
149 return VINF_SUCCESS;
150}
151
152/**
153 * @callback_method_impl{FNIOMMMIONEWWRITE}
154 */
155static DECLCALLBACK(VBOXSTRICTRC) msixR3MMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
156{
157 PPDMPCIDEV pPciDev = (PPDMPCIDEV)pvUser;
158 LogFlowFunc(("off=%RGp cb=%d %#010RX32\n", off, cb, *(uint32_t *)pv));
159
160 /* Validate IOM behaviour. */
161 Assert(cb == 4);
162 Assert((off & 3) == 0);
163
164 /* Do the write if it's within the MSI state. */
165 ASSERT_GUEST_MSG_RETURN(off + cb <= pPciDev->Int.s.offMsixPba, ("Trying to write to PBA\n"),
166 VINF_SUCCESS);
167 *(uint32_t *)&pPciDev->abMsixState[off] = *(uint32_t *)pv;
168
169 /* (See MsixR3Init the setting up of pvPciBusPtrR3.) */
170 msixR3CheckPendingVector(pDevIns, (PCPDMPCIHLP)pPciDev->Int.s.pvPciBusPtrR3, pPciDev, off / VBOX_MSIX_ENTRY_SIZE);
171 return VINF_SUCCESS;
172}
173
174/**
175 * Initalizes MSI-X support for the given PCI device.
176 */
177int MsixR3Init(PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, PPDMMSIREG pMsiReg)
178{
179 if (pMsiReg->cMsixVectors == 0)
180 return VINF_SUCCESS;
181
182 /* We cannot init MSI-X on raw devices yet. */
183 Assert(!pciDevIsPassthrough(pDev));
184
185 uint16_t cVectors = pMsiReg->cMsixVectors;
186 uint8_t iCapOffset = pMsiReg->iMsixCapOffset;
187 uint8_t iNextOffset = pMsiReg->iMsixNextOffset;
188 uint8_t iBar = pMsiReg->iMsixBar;
189
190 AssertMsgReturn(cVectors <= VBOX_MSIX_MAX_ENTRIES, ("Too many MSI-X vectors: %d\n", cVectors), VERR_TOO_MUCH_DATA);
191 AssertMsgReturn(iBar <= 5, ("Using wrong BAR for MSI-X: %d\n", iBar), VERR_INVALID_PARAMETER);
192 Assert(iCapOffset != 0 && iCapOffset < 0xff && iNextOffset < 0xff);
193
194 uint16_t cbPba = cVectors / 8;
195 if (cVectors % 8)
196 cbPba++;
197 uint16_t cbMsixRegion = RT_ALIGN_T(cVectors * sizeof(MsixTableRecord) + cbPba, _4K, uint16_t);
198 AssertLogRelMsgReturn(cbMsixRegion <= pDev->cbMsixState,
199 ("%#x vs %#x (%s)\n", cbMsixRegion, pDev->cbMsixState, pDev->pszNameR3),
200 VERR_MISMATCH);
201
202 /* If device is passthrough, BAR is registered using common mechanism. */
203 if (!pciDevIsPassthrough(pDev))
204 {
205 /** @todo r=bird: This used to be IOMMMIO_FLAGS_READ_PASSTHRU |
206 * IOMMMIO_FLAGS_WRITE_PASSTHRU with the callbacks asserting and
207 * returning VERR_INTERNAL_ERROR on non-dword reads. That is of
208 * course certifiable insane behaviour. So, instead I've changed it
209 * so the callbacks only see dword reads and writes. I'm not at all
210 * sure about the read-missing behaviour, but it seems like a good
211 * idea for now. */
212 /** @todo r=bird: Shouldn't we at least handle writes in ring-0? */
213 int rc = PDMDevHlpPCIIORegionCreateMmio(pDev->Int.s.CTX_SUFF(pDevIns), iBar, cbMsixRegion, PCI_ADDRESS_SPACE_MEM,
214 msixR3MMIOWrite, msixR3MMIORead, pDev,
215 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_READ_MISSING,
216 "MSI-X tables", &pDev->Int.s.hMmioMsix);
217 AssertRCReturn(rc, rc);
218 }
219
220 uint16_t offTable = 0;
221 uint16_t offPBA = cVectors * sizeof(MsixTableRecord);
222
223 pDev->Int.s.u8MsixCapOffset = iCapOffset;
224 pDev->Int.s.u8MsixCapSize = VBOX_MSIX_CAP_SIZE;
225 pDev->Int.s.cbMsixRegion = cbMsixRegion;
226 pDev->Int.s.offMsixPba = offPBA;
227
228 /* R3 PCI helper */
229 pDev->Int.s.pvPciBusPtrR3 = pPciHlp;
230
231 PCIDevSetByte(pDev, iCapOffset + 0, VBOX_PCI_CAP_ID_MSIX);
232 PCIDevSetByte(pDev, iCapOffset + 1, iNextOffset); /* next */
233 PCIDevSetWord(pDev, iCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL, cVectors - 1);
234
235 PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_TABLE_BIROFFSET, offTable | iBar);
236 PCIDevSetDWord(pDev, iCapOffset + VBOX_MSIX_PBA_BIROFFSET, offPBA | iBar);
237
238 pciDevSetMsixCapable(pDev);
239
240 return VINF_SUCCESS;
241}
242
243#endif /* IN_RING3 */
244
245/**
246 * Checks if MSI-X is enabled for the tiven PCI device.
247 *
248 * (Must use MSIXNotify() for notifications when true.)
249 */
250bool MsixIsEnabled(PPDMPCIDEV pDev)
251{
252 return pciDevIsMsixCapable(pDev) && msixIsEnabled(pDev);
253}
254
255/**
256 * Device notification (aka interrupt).
257 */
258void MsixNotify(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, int iVector, int iLevel, uint32_t uTagSrc)
259{
260 AssertMsg(msixIsEnabled(pDev), ("Must be enabled to use that"));
261
262 Assert(pPciHlp->pfnIoApicSendMsi != NULL);
263
264 /* We only trigger MSI-X on level up */
265 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == 0)
266 {
267 return;
268 }
269
270 // if this vector is somehow disabled
271 if (msixIsMasked(pDev) || msixIsVectorMasked(pDev, iVector))
272 {
273 // mark pending bit
274 msixSetPending(pDev, iVector);
275 return;
276 }
277
278 // clear pending bit
279 msixClearPending(pDev, iVector);
280
281 MSIMSG Msi;
282 Msi.Addr.u64 = msixGetMsiAddress(pDev, iVector);
283 Msi.Data.u32 = msixGetMsiData(pDev, iVector);
284
285 PPDMDEVINS pDevInsBus = pPciHlp->pfnGetBusByNo(pDevIns, pDev->Int.s.idxPdmBus);
286 Assert(pDevInsBus);
287 PDEVPCIBUS pBus = PDMINS_2_DATA(pDevInsBus, PDEVPCIBUS);
288 uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, pDev->uDevFn);
289
290 pPciHlp->pfnIoApicSendMsi(pDevIns, uBusDevFn, &Msi, uTagSrc);
291}
292
293#ifdef IN_RING3
294
295DECLINLINE(bool) msixR3BitJustCleared(uint32_t uOldValue, uint32_t uNewValue, uint32_t uMask)
296{
297 return !!(uOldValue & uMask) && !(uNewValue & uMask);
298}
299
300
301static void msixR3CheckPendingVectors(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev)
302{
303 for (uint32_t i = 0; i < msixTableSize(pDev); i++)
304 msixR3CheckPendingVector(pDevIns, pPciHlp, pDev, i);
305}
306
307/**
308 * PCI config space accessors for MSI-X.
309 */
310void MsixR3PciConfigWrite(PPDMDEVINS pDevIns, PCPDMPCIHLP pPciHlp, PPDMPCIDEV pDev, uint32_t u32Address, uint32_t val, unsigned len)
311{
312 int32_t iOff = u32Address - pDev->Int.s.u8MsixCapOffset;
313 Assert(iOff >= 0 && (pciDevIsMsixCapable(pDev) && iOff < pDev->Int.s.u8MsixCapSize));
314
315 Log2(("MsixR3PciConfigWrite: %d <- %x (%d)\n", iOff, val, len));
316
317 uint32_t uAddr = u32Address;
318 uint8_t u8NewVal;
319 bool fJustEnabled = false;
320
321 for (uint32_t i = 0; i < len; i++)
322 {
323 uint32_t reg = i + iOff;
324 uint8_t u8Val = (uint8_t)val;
325 switch (reg)
326 {
327 case 0: /* Capability ID, ro */
328 case 1: /* Next pointer, ro */
329 break;
330 case VBOX_MSIX_CAP_MESSAGE_CONTROL:
331 /* don't change read-only bits: 0-7 */
332 break;
333 case VBOX_MSIX_CAP_MESSAGE_CONTROL + 1:
334 {
335 /* don't change read-only bits 8-13 */
336 u8NewVal = (u8Val & UINT8_C(~0x3f)) | (pDev->abConfig[uAddr] & UINT8_C(0x3f));
337 /* If just enabled globally - check pending vectors */
338 fJustEnabled |= msixR3BitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_ENABLE >> 8);
339 fJustEnabled |= msixR3BitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_FUNCMASK >> 8);
340 pDev->abConfig[uAddr] = u8NewVal;
341 break;
342 }
343 default:
344 /* other fields read-only too */
345 break;
346 }
347 uAddr++;
348 val >>= 8;
349 }
350
351 if (fJustEnabled)
352 msixR3CheckPendingVectors(pDevIns, pPciHlp, pDev);
353}
354
355#endif /* IN_RING3 */
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