DevPciGenericEcam.cpp@ 101479

Last change on this file since 101479 was 101479, checked in by vboxsync, 19 months ago
Devices/Bus: Add PCI bridge support to the generic PCI ECAM bus (the PCI config space is the same as the ICH9 bridge as of now), bugref:10445 bugref:10528
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1	/* $Id: DevPciGenericEcam.cpp 101479 2023-10-17 14:38:54Z vboxsync $ */
2	/** @file
3	* DevPciGeneric - Generic host to PCIe bridge emulation.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_PCI
33	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
34	#include <VBox/vmm/pdmpcidev.h>
35
36	#include <VBox/AssertGuest.h>
37	#include <VBox/msi.h>
38	#include <VBox/vmm/pdmdev.h>
39	#include <VBox/vmm/mm.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/string.h>
43	#ifdef IN_RING3
44	# include <iprt/mem.h>
45	# include <iprt/uuid.h>
46	#endif
47
48	#include "PciInline.h"
49	#include "VBoxDD.h"
50	#include "MsiCommon.h"
51	#include "DevPciInternal.h"
52
53
54	/*********************************************************************************************************************************
55	* Structures and Typedefs *
56	*********************************************************************************************************************************/
57
58
59	/*********************************************************************************************************************************
60	* Defined Constants And Macros *
61	*********************************************************************************************************************************/
62	/** @todo As this shares a lot of code with the ICH9 PCI device we have to also keep the saved state version in sync. */
63	/** Saved state version of the generic ECAM PCI bus device. */
64	#define VBOX_PCIGENECAM_SAVED_STATE_VERSION VBOX_ICH9PCI_SAVED_STATE_VERSION_4KB_CFG_SPACE
65	/** 4KB config space */
66	#define VBOX_ICH9PCI_SAVED_STATE_VERSION_4KB_CFG_SPACE 4
67
68
69	/*********************************************************************************************************************************
70	* Internal Functions *
71	*********************************************************************************************************************************/
72
73	/**
74	* Returns the interrupt pin for a given device slot on the root port
75	* due to swizzeling.
76	*
77	* @returns Interrupt pin on the root port.
78	* @param uDevFn The device.
79	* @param uPin The interrupt pin on the device.
80	*/
81	DECLINLINE(uint8_t) pciGenEcamGetPirq(uint8_t uDevFn, uint8_t uPin)
82	{
83	uint8_t uSlot = (uDevFn >> 3) - 1;
84	return (uPin + uSlot) & 3;
85	}
86
87
88	/**
89	* Returns whether the interrupt line is asserted on the PCI root for the given pin.
90	*
91	* @returns Flag whther the interrupt line is asserted (true) or not (false).
92	* @param pPciRoot The PCI root bus.
93	* @param u8IrqPin The IRQ pin being checked.
94	*/
95	DECLINLINE(bool) pciGenEcamGetIrqLvl(PDEVPCIROOT pPciRoot, uint8_t u8IrqPin)
96	{
97	return (pPciRoot->u.GenericEcam.auPciIrqLevels[u8IrqPin] != 0);
98	}
99
100
101	static void pciGenEcamSetIrqInternal(PPDMDEVINS pDevIns, PDEVPCIROOT pPciRoot, PDEVPCIBUSCC pBusCC,
102	uint8_t uDevFn, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
103	{
104	PDEVPCIBUS pBus = &pPciRoot->PciBus;
105	uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
106
107	/* If MSI or MSI-X is enabled, PCI INTx# signals are disabled regardless of the PCI command
108	* register interrupt bit state.
109	* PCI 3.0 (section 6.8) forbids MSI and MSI-X to be enabled at the same time and makes
110	* that undefined behavior. We check for MSI first, then MSI-X.
111	*/
112	if (MsiIsEnabled(pPciDev))
113	{
114	Assert(!MsixIsEnabled(pPciDev)); /* Not allowed -- see note above. */
115	LogFlowFunc(("PCI Dev %p : MSI\n", pPciDev));
116	MsiNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
117	return;
118	}
119
120	if (MsixIsEnabled(pPciDev))
121	{
122	LogFlowFunc(("PCI Dev %p : MSI-X\n", pPciDev));
123	MsixNotify(pDevIns, pBusCC->CTX_SUFF(pPciHlp), pPciDev, iIrq, iLevel, uTagSrc);
124	return;
125	}
126
127	LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
128
129	/* Check if the state changed. */
130	if (pPciDev->Int.s.uIrqPinState != iLevel)
131	{
132	pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
133
134	/* Get the pin. */
135	uint8_t uIrqPin = devpciR3GetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
136	uint8_t uIrq = pciGenEcamGetPirq(pPciDev->uDevFn, uIrqPin);
137
138	if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
139	ASMAtomicIncU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
140	else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
141	ASMAtomicDecU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
142
143	bool fIrqLvl = pciGenEcamGetIrqLvl(pPciRoot, uIrq);
144	uint32_t u32IrqNr = pPciRoot->u.GenericEcam.auPciIrqNr[uIrq];
145
146	Log3Func(("%s: uIrqPin=%u uIrqRoot=%u fIrqLvl=%RTbool uIrqNr=%u\n",
147	R3STRING(pPciDev->pszNameR3), uIrqPin, uIrq, fIrqLvl, u32IrqNr));
148	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, u32IrqNr, fIrqLvl, uTagSrc);
149
150	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
151	ASMAtomicDecU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
152	pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
153	fIrqLvl = pciGenEcamGetIrqLvl(pPciRoot, uIrq);
154	Log3Func(("%s: uIrqPin=%u uIrqRoot=%u fIrqLvl=%RTbool uIrqNr=%u\n",
155	R3STRING(pPciDev->pszNameR3), uIrqPin, uIrq, fIrqLvl, u32IrqNr));
156	pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, u32IrqNr, fIrqLvl, uTagSrc);
157	}
158	}
159	}
160
161
162	/**
163	* @interface_method_impl{PDMPCIBUSREGCC,pfnSetIrqR3}
164	*/
165	static DECLCALLBACK(void) pciGenEcamSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
166	{
167	LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
168	pciGenEcamSetIrqInternal(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC),
169	pPciDev->uDevFn, pPciDev, iIrq, iLevel, uTagSrc);
170	}
171
172
173	static DECLCALLBACK(void) pciGenEcamBridgeSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
174	{
175	/*
176	* The PCI-to-PCI bridge specification defines how the interrupt pins
177	* are routed from the secondary to the primary bus (see chapter 9).
178	* iIrq gives the interrupt pin the pci device asserted.
179	* We change iIrq here according to the spec and call the SetIrq function
180	* of our parent passing the device which asserted the interrupt instead of the device of the bridge.
181	*
182	* See ich9pciBiosInitAllDevicesOnBus for corresponding configuration code.
183	*/
184	PDEVPCIBUS pBus;
185	uint8_t uDevFnBridge;
186	int iIrqPinBridge;
187	PPDMDEVINS pDevInsBus = devpcibridgeCommonSetIrqRootWalk(pDevIns, pPciDev, iIrq, &pBus, &uDevFnBridge, &iIrqPinBridge);
188	AssertReturnVoid(pDevInsBus);
189	AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
190	Assert(pDevInsBus->pReg == &g_DevicePciGenericEcam); /* ASSUMPTION: Same style root bus. Need callback interface to mix types. */
191
192	/*
193	* For MSI/MSI-X enabled devices the iIrq doesn't denote the pin but rather a vector which is completely
194	* orthogonal to the pin based approach. The vector is not subject to the pin based routing with PCI bridges.
195	*/
196	int iIrqPinVector = iIrqPinBridge;
197	if ( MsiIsEnabled(pPciDev)
198	\|\| MsixIsEnabled(pPciDev))
199	iIrqPinVector = iIrq;
200	pciGenEcamSetIrqInternal(pDevIns, DEVPCIBUS_2_DEVPCIROOT(pBus), PDMINS_2_DATA_CC(pDevInsBus, PDEVPCIBUSCC),
201	uDevFnBridge, pPciDev, iIrqPinVector, iLevel, uTagSrc);
202	}
203
204
205	/**
206	* @callback_method_impl{FNIOMMMIONEWWRITE,
207	* Emulates writes to PIO space.}
208	*/
209	static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
210	{
211	Log2Func(("%RGp LB %d\n", off, cb));
212	RT_NOREF(pvUser);
213
214	AssertReturn(off < _64K, VERR_INVALID_PARAMETER);
215	AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
216
217	/* Get the value. */
218	uint32_t u32;
219	switch (cb)
220	{
221	case 1:
222	u32 = (uint8_t const )pv;
223	break;
224	case 2:
225	u32 = (uint16_t const )pv;
226	break;
227	case 4:
228	u32 = (uint32_t const )pv;
229	break;
230	default:
231	ASSERT_GUEST_MSG_FAILED(("cb=%u off=%RGp\n", cb, off)); /** @todo how the heck should this work? Split it, right? */
232	u32 = 0;
233	break;
234	}
235
236	return PDMDevHlpIoPortWrite(pDevIns, (RTIOPORT)off, u32, cb);
237	}
238
239
240	/**
241	* @callback_method_impl{FNIOMMMIONEWWRITE,
242	* Emulates reads from PIO space.}
243	*/
244	static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
245	{
246	LogFlowFunc(("%RGp LB %u\n", off, cb));
247	RT_NOREF(pvUser);
248
249	AssertReturn(off < _64K, VERR_INVALID_PARAMETER);
250	AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
251
252	/* Perform PIO space read */
253	uint32_t u32Value = 0;
254	VBOXSTRICTRC rcStrict = PDMDevHlpIoPortRead(pDevIns, (RTIOPORT)off, &u32Value, cb);
255
256	if (RT_SUCCESS(rcStrict))
257	{
258	switch (cb)
259	{
260	case 1:
261	(uint8_t )pv = (uint8_t)u32Value;
262	break;
263	case 2:
264	(uint16_t )pv = (uint16_t)u32Value;
265	break;
266	case 4:
267	(uint32_t )pv = u32Value;
268	break;
269	default:
270	ASSERT_GUEST_MSG_FAILED(("cb=%u off=%RGp\n", cb, off)); /** @todo how the heck should this work? Split it, right? */
271	break;
272	}
273	}
274
275	return rcStrict;
276	}
277
278
279	#ifdef IN_RING3
280
281	/* -=-=-=-=-=- PCI Config Space -=-=-=-=-=- */
282
283
284	/**
285	* @interface_method_impl{PDMDEVREG,pfnConstruct}
286	*/
287	static DECLCALLBACK(int) pciGenEcamR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
288	{
289	RT_NOREF1(iInstance);
290	Assert(iInstance == 0);
291	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
292
293	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
294	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
295	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
296	PDEVPCIBUS pBus = &pPciRoot->PciBus;
297
298	/*
299	* Validate and read configuration.
300	*/
301	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MmioEcamBase"
302	"\|MmioEcamLength"
303	"\|MmioPioBase"
304	"\|MmioPioSize"
305	"\|IntPinA"
306	"\|IntPinB"
307	"\|IntPinC"
308	"\|IntPinD", "");
309
310	int rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamBase", &pPciRoot->u64PciConfigMMioAddress, 0);
311	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\"")));
312
313	rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamLength", &pPciRoot->u64PciConfigMMioLength, 0);
314	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\"")));
315
316	rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioPioBase", &pPciRoot->GCPhysMmioPioEmuBase, 0);
317	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioBase\"")));
318
319	rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioPioSize", &pPciRoot->GCPhysMmioPioEmuSize, 0);
320	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioSize\"")));
321
322	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinA", &pPciRoot->u.GenericEcam.auPciIrqNr[0]);
323	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinA\"")));
324
325	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinB", &pPciRoot->u.GenericEcam.auPciIrqNr[1]);
326	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinB\"")));
327
328	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinC", &pPciRoot->u.GenericEcam.auPciIrqNr[2]);
329	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinC\"")));
330
331	rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinD", &pPciRoot->u.GenericEcam.auPciIrqNr[3]);
332	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinD\"")));
333
334	Log(("PCI: fUseIoApic=%RTbool McfgBase=%#RX64 McfgLength=%#RX64 fR0Enabled=%RTbool fRCEnabled=%RTbool\n", pPciRoot->fUseIoApic,
335	pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
336	Log(("PCI: IntPinA=%u IntPinB=%u IntPinC=%u IntPinD=%u\n", pPciRoot->u.GenericEcam.auPciIrqNr[0],
337	pPciRoot->u.GenericEcam.auPciIrqNr[1], pPciRoot->u.GenericEcam.auPciIrqNr[2], pPciRoot->u.GenericEcam.auPciIrqNr[3]));
338
339	/*
340	* Init data.
341	*/
342	/* And fill values */
343	pBusCC->pDevInsR3 = pDevIns;
344	pPciRoot->hIoPortAddress = NIL_IOMIOPORTHANDLE;
345	pPciRoot->hIoPortData = NIL_IOMIOPORTHANDLE;
346	pPciRoot->hIoPortMagic = NIL_IOMIOPORTHANDLE;
347	pPciRoot->hMmioMcfg = NIL_IOMMMIOHANDLE;
348	pPciRoot->hMmioPioEmu = NIL_IOMMMIOHANDLE;
349	pPciRoot->PciBus.enmType = DEVPCIBUSTYPE_GENERIC_ECAM;
350	pPciRoot->PciBus.fPureBridge = false;
351	pPciRoot->PciBus.papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pPciRoot->PciBus.apDevices));
352	AssertLogRelReturn(pPciRoot->PciBus.papBridgesR3, VERR_NO_MEMORY);
353
354	/*
355	* Disable default device locking.
356	*/
357	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
358	AssertRCReturn(rc, rc);
359
360	/*
361	* Register bus
362	*/
363	PDMPCIBUSREGCC PciBusReg;
364	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
365	PciBusReg.pfnRegisterR3 = devpciR3CommonRegisterDevice;
366	PciBusReg.pfnRegisterMsiR3 = NULL;
367	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
368	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
369	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
370	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
371	PciBusReg.pfnSetIrqR3 = pciGenEcamSetIrq;
372	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
373	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
374	if (RT_FAILURE(rc))
375	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
376	Assert(pBus->iBus == 0);
377	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
378	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
379	N_("PCI helper version mismatch; got %#x expected %#x"),
380	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
381
382	/*
383	* Fill in PCI configs and add them to the bus.
384	*/
385	#if 0
386	/* Host bridge device */
387	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
388	AssertPtr(pPciDev);
389	PDMPciDevSetVendorId( pPciDev, 0x8086); /** @todo Intel */
390	PDMPciDevSetDeviceId( pPciDev, 0x29e0); /** @todo Desktop */
391	PDMPciDevSetRevisionId(pPciDev, 0x01); /* rev. 01 */
392	PDMPciDevSetClassBase( pPciDev, 0x06); /* bridge */
393	PDMPciDevSetClassSub( pPciDev, 0x00); /* Host/PCI bridge */
394	PDMPciDevSetClassProg( pPciDev, 0x00); /* Host/PCI bridge */
395	PDMPciDevSetHeaderType(pPciDev, 0x00); /* bridge */
396	PDMPciDevSetWord(pPciDev, VBOX_PCI_SEC_STATUS, 0x0280); /* secondary status */
397
398	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /fFlags/, 0 /uPciDevNo/, 0 /uPciFunNo/, "Host");
399	AssertLogRelRCReturn(rc, rc);
400	#endif
401
402	/*
403	* MMIO handlers.
404	*/
405	if (pPciRoot->u64PciConfigMMioAddress != 0)
406	{
407	rc = PDMDevHlpMmioCreateAndMap(pDevIns, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength,
408	devpciCommonMcfgMmioWrite, devpciCommonMcfgMmioRead,
409	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
410	"ECAM window", &pPciRoot->hMmioMcfg);
411	AssertMsgRCReturn(rc, ("rc=%Rrc %#RX64/%#RX64\n", rc, pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength), rc);
412	}
413
414	if (pPciRoot->GCPhysMmioPioEmuBase != 0)
415	{
416	rc = PDMDevHlpMmioCreateAndMap(pDevIns, pPciRoot->GCPhysMmioPioEmuBase, pPciRoot->GCPhysMmioPioEmuSize,
417	pciHostR3MmioPioWrite, pciHostR3MmioPioRead,
418	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
419	"PIO range", &pPciRoot->hMmioPioEmu);
420	AssertMsgRCReturn(rc, ("rc=%Rrc %#RGp/%#RGp\n", rc, pPciRoot->GCPhysMmioPioEmuBase, pPciRoot->GCPhysMmioPioEmuSize), rc);
421	}
422
423	/*
424	* Saved state and info handlers.
425	*/
426	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCIGENECAM_SAVED_STATE_VERSION,
427	sizeof(pBus) + 16128, "pgm",
428	NULL, NULL, NULL,
429	NULL, devpciR3CommonSaveExec, NULL,
430	NULL, devpciR3CommonLoadExec, NULL);
431	AssertRCReturn(rc, rc);
432
433	PDMDevHlpDBGFInfoRegister(pDevIns, "pci",
434	"Display PCI bus status. Recognizes 'basic' or 'verbose' as arguments, defaults to 'basic'.",
435	devpciR3InfoPci);
436	PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ state. (no arguments)", devpciR3InfoPciIrq);
437
438	return VINF_SUCCESS;
439	}
440
441
442	/**
443	* @interface_method_impl{PDMDEVREG,pfnDestruct}
444	*/
445	static DECLCALLBACK(int) pciGenEcamR3Destruct(PPDMDEVINS pDevIns)
446	{
447	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
448	if (pPciRoot->PciBus.papBridgesR3)
449	{
450	PDMDevHlpMMHeapFree(pDevIns, pPciRoot->PciBus.papBridgesR3);
451	pPciRoot->PciBus.papBridgesR3 = NULL;
452	}
453	return VINF_SUCCESS;
454	}
455
456
457	/**
458	* @interface_method_impl{PDMDEVREG,pfnReset}
459	*/
460	static DECLCALLBACK(void) pciGenEcamR3Reset(PPDMDEVINS pDevIns)
461	{
462	/* Reset everything under the root bridge. */
463	devpciR3CommonResetBridge(pDevIns);
464	}
465
466
467	/**
468	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
469	*/
470	static DECLCALLBACK(void ) pciGenEcamBridgeQueryInterface(PPDMIBASE pInterface, const char pszIID)
471	{
472	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
473	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
474
475	/* HACK ALERT! Special access to the PDMPCIDEV structure of an ich9pcibridge
476	instance (see PDMIICH9BRIDGEPDMPCIDEV_IID for details). */
477	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIICH9BRIDGEPDMPCIDEV, pDevIns->apPciDevs[0]);
478	return NULL;
479	}
480
481
482	/**
483	* @interface_method_impl{PDMDEVREG,pfnDestruct}
484	*/
485	static DECLCALLBACK(int) pciGenEcamBridgeR3Destruct(PPDMDEVINS pDevIns)
486	{
487	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
488	if (pBus->papBridgesR3)
489	{
490	PDMDevHlpMMHeapFree(pDevIns, pBus->papBridgesR3);
491	pBus->papBridgesR3 = NULL;
492	}
493	return VINF_SUCCESS;
494	}
495
496
497	/**
498	* @interface_method_impl{PDMDEVREG,pfnConstruct}
499	*/
500	static DECLCALLBACK(int) pciGenEcamBridgeR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
501	{
502	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
503	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
504
505	/*
506	* Validate and read configuration.
507	*/
508	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "ExpressEnabled\|ExpressPortType", "");
509
510	/* check if we're supposed to implement a PCIe bridge. */
511	bool fExpress;
512	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExpressEnabled", &fExpress, false);
513	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ExpressEnabled\"")));
514
515	char szExpressPortType[80];
516	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ExpressPortType", szExpressPortType, sizeof(szExpressPortType), "RootCmplxIntEp");
517	AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read \"ExpressPortType\" as string")));
518
519	uint8_t const uExpressPortType = devpciR3BridgeCommonGetExpressPortTypeFromString(szExpressPortType);
520	Log(("PCI/bridge#%u: fR0Enabled=%RTbool fRCEnabled=%RTbool fExpress=%RTbool uExpressPortType=%u (%s)\n",
521	iInstance, pDevIns->fR0Enabled, pDevIns->fRCEnabled, fExpress, uExpressPortType, szExpressPortType));
522
523	/*
524	* Init data and register the PCI bus.
525	*/
526	pDevIns->IBase.pfnQueryInterface = pciGenEcamBridgeQueryInterface;
527
528	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
529	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
530
531	pBus->enmType = DEVPCIBUSTYPE_ICH9;
532	pBus->fPureBridge = true;
533	pBusCC->pDevInsR3 = pDevIns;
534	pBus->papBridgesR3 = (PPDMPCIDEV )PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPDMPCIDEV) RT_ELEMENTS(pBus->apDevices));
535	AssertLogRelReturn(pBus->papBridgesR3, VERR_NO_MEMORY);
536
537	PDMPCIBUSREGCC PciBusReg;
538	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
539	PciBusReg.pfnRegisterR3 = devpcibridgeR3CommonRegisterDevice;
540	PciBusReg.pfnRegisterMsiR3 = NULL;
541	PciBusReg.pfnIORegionRegisterR3 = devpciR3CommonIORegionRegister;
542	PciBusReg.pfnInterceptConfigAccesses = devpciR3CommonInterceptConfigAccesses;
543	PciBusReg.pfnConfigWrite = devpciR3CommonConfigWrite;
544	PciBusReg.pfnConfigRead = devpciR3CommonConfigRead;
545	PciBusReg.pfnSetIrqR3 = pciGenEcamBridgeSetIrq;
546	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
547	rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBusCC->pPciHlpR3, &pBus->iBus);
548	if (RT_FAILURE(rc))
549	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as a PCI Bus"));
550	Assert(pBus->iBus == (uint32_t)iInstance + 1); /* Can be removed when adding support for multiple bridge implementations. */
551	if (pBusCC->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
552	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
553	N_("PCI helper version mismatch; got %#x expected %#x"),
554	pBusCC->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
555
556	LogRel(("PCI: Registered bridge instance #%u as PDM bus no %u.\n", iInstance, pBus->iBus));
557
558
559	/* Disable default device locking. */
560	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
561	AssertRCReturn(rc, rc);
562
563	/** @todo r=aeichner This is the same as the ICH9 bridge. */
564	/*
565	* Fill in PCI configs and add them to the bus.
566	*/
567	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
568	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
569
570	PDMPciDevSetVendorId( pPciDev, 0x8086); /* Intel */
571	if (fExpress)
572	{
573	PDMPciDevSetDeviceId(pPciDev, 0x29e1); /* 82X38/X48 Express Host-Primary PCI Express Bridge. */
574	PDMPciDevSetRevisionId(pPciDev, 0x01);
575	}
576	else
577	{
578	PDMPciDevSetDeviceId(pPciDev, 0x2448); /* 82801 Mobile PCI bridge. */
579	PDMPciDevSetRevisionId(pPciDev, 0xf2);
580	}
581	PDMPciDevSetClassSub( pPciDev, 0x04); /* pci2pci */
582	PDMPciDevSetClassBase( pPciDev, 0x06); /* PCI_bridge */
583	if (fExpress)
584	PDMPciDevSetClassProg(pPciDev, 0x00); /* Normal decoding. */
585	else
586	PDMPciDevSetClassProg(pPciDev, 0x01); /* Supports subtractive decoding. */
587	PDMPciDevSetHeaderType(pPciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
588	if (fExpress)
589	{
590	PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_SERR);
591	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Has capabilities. */
592	PDMPciDevSetByte(pPciDev, VBOX_PCI_CACHE_LINE_SIZE, 8); /* 32 bytes */
593	/* PCI Express */
594	PDMPciDevSetByte(pPciDev, 0xa0 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
595	PDMPciDevSetByte(pPciDev, 0xa0 + 1, 0); /* next */
596	PDMPciDevSetWord(pPciDev, 0xa0 + 2,
597	/* version */ 0x2
598	\| (uExpressPortType << 4));
599	PDMPciDevSetDWord(pPciDev, 0xa0 + 4, VBOX_PCI_EXP_DEVCAP_RBE); /* Device capabilities. */
600	PDMPciDevSetWord(pPciDev, 0xa0 + 8, 0x0000); /* Device control. */
601	PDMPciDevSetWord(pPciDev, 0xa0 + 10, 0x0000); /* Device status. */
602	PDMPciDevSetDWord(pPciDev, 0xa0 + 12,
603	/* Max Link Speed */ 2
604	\| /* Maximum Link Width */ (16 << 4)
605	\| /* Active State Power Management (ASPM) Sopport */ (0 << 10)
606	\| VBOX_PCI_EXP_LNKCAP_LBNC
607	\| /* Port Number / ((2 + iInstance) << 24)); / Link capabilities. */
608	PDMPciDevSetWord(pPciDev, 0xa0 + 16, VBOX_PCI_EXP_LNKCTL_CLOCK); /* Link control. */
609	PDMPciDevSetWord(pPciDev, 0xa0 + 18,
610	/* Current Link Speed */ 2
611	\| /* Negotiated Link Width */ (16 << 4)
612	\| VBOX_PCI_EXP_LNKSTA_SL_CLK); /* Link status. */
613	PDMPciDevSetDWord(pPciDev, 0xa0 + 20,
614	/* Slot Power Limit Value */ (75 << 7)
615	\| /* Physical Slot Number / (0 << 19)); / Slot capabilities. */
616	PDMPciDevSetWord(pPciDev, 0xa0 + 24, 0x0000); /* Slot control. */
617	PDMPciDevSetWord(pPciDev, 0xa0 + 26, 0x0000); /* Slot status. */
618	PDMPciDevSetWord(pPciDev, 0xa0 + 28, 0x0000); /* Root control. */
619	PDMPciDevSetWord(pPciDev, 0xa0 + 30, 0x0000); /* Root capabilities. */
620	PDMPciDevSetDWord(pPciDev, 0xa0 + 32, 0x00000000); /* Root status. */
621	PDMPciDevSetDWord(pPciDev, 0xa0 + 36, 0x00000000); /* Device capabilities 2. */
622	PDMPciDevSetWord(pPciDev, 0xa0 + 40, 0x0000); /* Device control 2. */
623	PDMPciDevSetWord(pPciDev, 0xa0 + 42, 0x0000); /* Device status 2. */
624	PDMPciDevSetDWord(pPciDev, 0xa0 + 44,
625	/* Supported Link Speeds Vector / (2 << 1)); / Link capabilities 2. */
626	PDMPciDevSetWord(pPciDev, 0xa0 + 48,
627	/* Target Link Speed / 2); / Link control 2. */
628	PDMPciDevSetWord(pPciDev, 0xa0 + 50, 0x0000); /* Link status 2. */
629	PDMPciDevSetDWord(pPciDev, 0xa0 + 52, 0x00000000); /* Slot capabilities 2. */
630	PDMPciDevSetWord(pPciDev, 0xa0 + 56, 0x0000); /* Slot control 2. */
631	PDMPciDevSetWord(pPciDev, 0xa0 + 58, 0x0000); /* Slot status 2. */
632	PDMPciDevSetCapabilityList(pPciDev, 0xa0);
633	}
634	else
635	{
636	PDMPciDevSetCommand(pPciDev, 0x00);
637	PDMPciDevSetStatus(pPciDev, 0x20); /* 66MHz Capable. */
638	}
639	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* This device does not assert interrupts. */
640
641	/*
642	* This device does not generate interrupts. Interrupt delivery from
643	* devices attached to the bus is unaffected.
644	*/
645	PDMPciDevSetInterruptPin (pPciDev, 0x00);
646
647	if (fExpress)
648	{
649	/** @todo r=klaus set up the PCIe config space beyond the old 256 byte
650	* limit, containing additional capability descriptors. */
651	}
652
653	/*
654	* Register this PCI bridge. The called function will take care on which bus we will get registered.
655	*/
656	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_PCI_BRIDGE, PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
657	PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, "pci-generic-ecam-bridge");
658	AssertLogRelRCReturn(rc, rc);
659
660	pPciDev->Int.s.pfnBridgeConfigRead = devpciR3BridgeCommonConfigRead;
661	pPciDev->Int.s.pfnBridgeConfigWrite = devpciR3BridgeCommonConfigWrite;
662
663	/*
664	* Register SSM handlers. We use the same saved state version as for the host bridge
665	* to make changes easier.
666	*/
667	rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCIGENECAM_SAVED_STATE_VERSION,
668	sizeof(pBus) + 16128,
669	"pgm" /* before */,
670	NULL, NULL, NULL,
671	NULL, devpciR3BridgeCommonSaveExec, NULL,
672	NULL, devpciR3BridgeCommonLoadExec, NULL);
673	AssertLogRelRCReturn(rc, rc);
674
675	return VINF_SUCCESS;
676	}
677
678	#else /* !IN_RING3 */
679
680	/**
681	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
682	*/
683	DECLCALLBACK(int) pciGenEcamRZConstruct(PPDMDEVINS pDevIns)
684	{
685	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
686	PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
687	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
688
689	/* Mirror the ring-3 device lock disabling: */
690	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
691	AssertRCReturn(rc, rc);
692
693	/* Set up the RZ PCI bus callbacks: */
694	PDMPCIBUSREGCC PciBusReg;
695	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
696	PciBusReg.iBus = pPciRoot->PciBus.iBus;
697	PciBusReg.pfnSetIrq = pciGenEcamSetIrq;
698	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
699	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
700	AssertRCReturn(rc, rc);
701
702	/* Set up MMIO callbacks: */
703	if (pPciRoot->hMmioMcfg != NIL_IOMMMIOHANDLE)
704	{
705	rc = PDMDevHlpMmioSetUpContext(pDevIns, pPciRoot->hMmioMcfg, devpciCommonMcfgMmioWrite, devpciCommonMcfgMmioRead, NULL /pvUser/);
706	AssertLogRelRCReturn(rc, rc);
707	}
708
709	return rc;
710	}
711
712
713	/**
714	* @interface_method_impl{PDMDEVREGR0,pfnConstruct}
715	*/
716	static DECLCALLBACK(int) pciGenEcamBridgeRZConstruct(PPDMDEVINS pDevIns)
717	{
718	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
719	PDEVPCIBUS pBus = PDMINS_2_DATA(pDevIns, PDEVPCIBUS);
720	PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
721
722	/* Mirror the ring-3 device lock disabling: */
723	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
724	AssertRCReturn(rc, rc);
725
726	/* Set up the RZ PCI bus callbacks: */
727	PDMPCIBUSREGCC PciBusReg;
728	PciBusReg.u32Version = PDM_PCIBUSREGCC_VERSION;
729	PciBusReg.iBus = pBus->iBus;
730	PciBusReg.pfnSetIrq = pciGenEcamBridgeSetIrq;
731	PciBusReg.u32EndVersion = PDM_PCIBUSREGCC_VERSION;
732	rc = PDMDevHlpPCIBusSetUpContext(pDevIns, &PciBusReg, &pBusCC->CTX_SUFF(pPciHlp));
733	AssertRCReturn(rc, rc);
734
735	return rc;
736	}
737
738	#endif /* !IN_RING3 */
739
740	/**
741	* The PCI bus device registration structure.
742	*/
743	const PDMDEVREG g_DevicePciGenericEcam =
744	{
745	/* .u32Version = */ PDM_DEVREG_VERSION,
746	/* .uReserved0 = */ 0,
747	/* .szName = */ "pci-generic-ecam",
748	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
749	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
750	/* .cMaxInstances = */ 1,
751	/* .uSharedVersion = */ 42,
752	/* .cbInstanceShared = */ sizeof(DEVPCIROOT),
753	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
754	/* .cbInstanceRC = */ sizeof(DEVPCIBUSRC),
755	/* .cMaxPciDevices = */ 1,
756	/* .cMaxMsixVectors = */ 0,
757	/* .pszDescription = */ "Generic PCI host bridge (working with pci-host-ecam-generic driver)",
758	#if defined(IN_RING3)
759	/* .pszRCMod = */ "VBoxDDRC.rc",
760	/* .pszR0Mod = */ "VBoxDDR0.r0",
761	/* .pfnConstruct = */ pciGenEcamR3Construct,
762	/* .pfnDestruct = */ pciGenEcamR3Destruct,
763	/* .pfnRelocate = */ NULL,
764	/* .pfnMemSetup = */ NULL,
765	/* .pfnPowerOn = */ NULL,
766	/* .pfnReset = */ pciGenEcamR3Reset,
767	/* .pfnSuspend = */ NULL,
768	/* .pfnResume = */ NULL,
769	/* .pfnAttach = */ NULL,
770	/* .pfnDetach = */ NULL,
771	/* .pfnQueryInterface = */ NULL,
772	/* .pfnInitComplete = */ NULL,
773	/* .pfnPowerOff = */ NULL,
774	/* .pfnSoftReset = */ NULL,
775	/* .pfnReserved0 = */ NULL,
776	/* .pfnReserved1 = */ NULL,
777	/* .pfnReserved2 = */ NULL,
778	/* .pfnReserved3 = */ NULL,
779	/* .pfnReserved4 = */ NULL,
780	/* .pfnReserved5 = */ NULL,
781	/* .pfnReserved6 = */ NULL,
782	/* .pfnReserved7 = */ NULL,
783	#elif defined(IN_RING0)
784	/* .pfnEarlyConstruct = */ NULL,
785	/* .pfnConstruct = */ pciGenEcamRZConstruct,
786	/* .pfnDestruct = */ NULL,
787	/* .pfnFinalDestruct = */ NULL,
788	/* .pfnRequest = */ NULL,
789	/* .pfnReserved0 = */ NULL,
790	/* .pfnReserved1 = */ NULL,
791	/* .pfnReserved2 = */ NULL,
792	/* .pfnReserved3 = */ NULL,
793	/* .pfnReserved4 = */ NULL,
794	/* .pfnReserved5 = */ NULL,
795	/* .pfnReserved6 = */ NULL,
796	/* .pfnReserved7 = */ NULL,
797	#elif defined(IN_RC)
798	/* .pfnConstruct = */ pciGenEcamRZConstruct,
799	/* .pfnReserved0 = */ NULL,
800	/* .pfnReserved1 = */ NULL,
801	/* .pfnReserved2 = */ NULL,
802	/* .pfnReserved3 = */ NULL,
803	/* .pfnReserved4 = */ NULL,
804	/* .pfnReserved5 = */ NULL,
805	/* .pfnReserved6 = */ NULL,
806	/* .pfnReserved7 = */ NULL,
807	#else
808	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
809	#endif
810	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
811	};
812
813	/**
814	* The device registration structure
815	* for the PCI-to-PCI bridge.
816	*/
817	const PDMDEVREG g_DevicePciGenericEcamBridge =
818	{
819	/* .u32Version = */ PDM_DEVREG_VERSION,
820	/* .uReserved0 = */ 0,
821	/* .szName = */ "pci-generic-ecam-bridge",
822	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
823	/* .fClass = */ PDM_DEVREG_CLASS_BUS_PCI,
824	/* .cMaxInstances = */ ~0U,
825	/* .uSharedVersion = */ 42,
826	/* .cbInstanceShared = */ sizeof(DEVPCIBUS),
827	/* .cbInstanceCC = */ sizeof(CTX_SUFF(DEVPCIBUS)),
828	/* .cbInstanceRC = */ 0,
829	/* .cMaxPciDevices = */ 1,
830	/* .cMaxMsixVectors = */ 0,
831	/* .pszDescription = */ "Generic ECAM PCI to PCI bridge",
832	#if defined(IN_RING3)
833	/* .pszRCMod = */ "VBoxDDRC.rc",
834	/* .pszR0Mod = */ "VBoxDDR0.r0",
835	/* .pfnConstruct = */ pciGenEcamBridgeR3Construct,
836	/* .pfnDestruct = */ pciGenEcamBridgeR3Destruct,
837	/* .pfnRelocate = */ NULL,
838	/* .pfnMemSetup = */ NULL,
839	/* .pfnPowerOn = */ NULL,
840	/* .pfnReset = / NULL, / Must be NULL, to make sure only bus driver handles reset */
841	/* .pfnSuspend = */ NULL,
842	/* .pfnResume = */ NULL,
843	/* .pfnAttach = */ NULL,
844	/* .pfnDetach = */ NULL,
845	/* .pfnQueryInterface = */ NULL,
846	/* .pfnInitComplete = */ NULL,
847	/* .pfnPowerOff = */ NULL,
848	/* .pfnSoftReset = */ NULL,
849	/* .pfnReserved0 = */ NULL,
850	/* .pfnReserved1 = */ NULL,
851	/* .pfnReserved2 = */ NULL,
852	/* .pfnReserved3 = */ NULL,
853	/* .pfnReserved4 = */ NULL,
854	/* .pfnReserved5 = */ NULL,
855	/* .pfnReserved6 = */ NULL,
856	/* .pfnReserved7 = */ NULL,
857	#elif defined(IN_RING0)
858	/* .pfnEarlyConstruct = */ NULL,
859	/* .pfnConstruct = */ pciGenEcamBridgeRZConstruct,
860	/* .pfnDestruct = */ NULL,
861	/* .pfnFinalDestruct = */ NULL,
862	/* .pfnRequest = */ NULL,
863	/* .pfnReserved0 = */ NULL,
864	/* .pfnReserved1 = */ NULL,
865	/* .pfnReserved2 = */ NULL,
866	/* .pfnReserved3 = */ NULL,
867	/* .pfnReserved4 = */ NULL,
868	/* .pfnReserved5 = */ NULL,
869	/* .pfnReserved6 = */ NULL,
870	/* .pfnReserved7 = */ NULL,
871	#elif defined(IN_RC)
872	/* .pfnConstruct = */ pciGenEcamBridgeRZConstruct,
873	/* .pfnReserved0 = */ NULL,
874	/* .pfnReserved1 = */ NULL,
875	/* .pfnReserved2 = */ NULL,
876	/* .pfnReserved3 = */ NULL,
877	/* .pfnReserved4 = */ NULL,
878	/* .pfnReserved5 = */ NULL,
879	/* .pfnReserved6 = */ NULL,
880	/* .pfnReserved7 = */ NULL,
881	#else
882	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
883	#endif
884	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
885	};

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source: vbox/trunk/src/VBox/Devices/Bus/DevPciGenericEcam.cpp@ 101479

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