VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 103914

Last change on this file since 103914 was 99280, checked in by vboxsync, 18 months ago

Devices/Bus/DevIommuIntel: Memory cleanup on the semevent wait failure case.

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1/* $Id: DevIommuIntel.cpp 99280 2023-04-04 13:05:53Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - Intel implementation.
4 */
5
6/*
7 * Copyright (C) 2021-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_IOMMU
33#include "VBoxDD.h"
34#include "DevIommuIntel.h"
35
36#include <VBox/iommu-intel.h>
37#include <iprt/mem.h>
38#include <iprt/string.h>
39
40
41/*********************************************************************************************************************************
42* Defined Constants And Macros *
43*********************************************************************************************************************************/
44/** Gets the low uint32_t of a uint64_t or something equivalent.
45 *
46 * This is suitable for casting constants outside code (since RT_LO_U32 can't be
47 * used as it asserts for correctness when compiling on certain compilers). */
48#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
49
50/** Gets the high uint32_t of a uint64_t or something equivalent.
51 *
52 * This is suitable for casting constants outside code (since RT_HI_U32 can't be
53 * used as it asserts for correctness when compiling on certain compilers). */
54#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
55
56/** Asserts MMIO access' offset and size are valid or returns appropriate error
57 * code suitable for returning from MMIO access handlers. */
58#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
59 do { \
60 AssertReturn((a_cb) == 4 || (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
61 AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
62 } while (0)
63
64/** Checks if the MMIO offset is valid. */
65#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
66 || (a_off) - (uint16_t)DMAR_MMIO_GROUP_1_OFF_FIRST < (uint16_t)DMAR_MMIO_GROUP_1_SIZE)
67
68/** Acquires the DMAR lock but returns with the given busy error code on failure. */
69#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
70 do { \
71 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
72 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
73 { /* likely */ } \
74 else \
75 return rcLock; \
76 } while (0)
77
78/** Acquires the DMAR lock (can fail under extraordinary circumstance in ring-0). */
79#define DMAR_LOCK(a_pDevIns, a_pThisCC) \
80 do { \
81 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
82 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), NULL, rcLock); \
83 } while (0)
84
85/** Release the DMAR lock. */
86#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
87
88/** Asserts that the calling thread owns the DMAR lock. */
89#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
90 do { \
91 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
92 RT_NOREF1(a_pThisCC); \
93 } while (0)
94
95/** Asserts that the calling thread does not own the DMAR lock. */
96#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
97 do { \
98 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
99 RT_NOREF1(a_pThisCC); \
100 } while (0)
101
102/** The number of fault recording registers our implementation supports.
103 * Normal guest operation shouldn't trigger faults anyway, so we only support the
104 * minimum number of registers (which is 1).
105 *
106 * See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
107#define DMAR_FRCD_REG_COUNT UINT32_C(1)
108
109/** Number of register groups (used in saved states). */
110#define DMAR_MMIO_GROUP_COUNT 2
111/** Offset of first register in group 0. */
112#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
113/** Offset of last register in group 0 (inclusive). */
114#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
115/** Last valid offset in group 0 (exclusive). */
116#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
117/** Size of the group 0 (in bytes). */
118#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
119/** Number of implementation-defined MMIO register offsets - IVA_REG and
120 * FRCD_LO_REG (used in saved state). IOTLB_REG and FRCD_HI_REG are derived from
121 * IVA_REG and FRCD_LO_REG respectively */
122#define DMAR_MMIO_OFF_IMPL_COUNT 2
123/** Implementation-specific MMIO offset of IVA_REG (used in saved state). */
124#define DMAR_MMIO_OFF_IVA_REG 0xe50
125/** Implementation-specific MMIO offset of IOTLB_REG. */
126#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
127/** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */
128#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
129/** Implementation-specific MMIO offset of FRCD_HI_REG. */
130#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
131AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
132AssertCompile(DMAR_MMIO_OFF_IOTLB_REG == DMAR_MMIO_OFF_IVA_REG + 8);
133AssertCompile(DMAR_MMIO_OFF_FRCD_HI_REG == DMAR_MMIO_OFF_FRCD_LO_REG + 8);
134
135/** Offset of first register in group 1. */
136#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
137/** Offset of last register in group 1 (inclusive). */
138#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
139/** Last valid offset in group 1 (exclusive). */
140#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
141/** Size of the group 1 (in bytes). */
142#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
143
144/** DMAR implementation's major version number (exposed to software).
145 * We report 6 as the major version since we support queued-invalidations as
146 * software may make assumptions based on that.
147 *
148 * See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
149#define DMAR_VER_MAJOR 6
150/** DMAR implementation's minor version number (exposed to software). */
151#define DMAR_VER_MINOR 0
152
153/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
154 * 7=Reserved). */
155#define DMAR_ND 6
156
157/** @name DMAR_PERM_XXX: DMA request permissions.
158 * The order of R, W, X bits is important as it corresponds to those bits in
159 * page-table entries.
160 *
161 * @{ */
162/** DMA request permission: Read. */
163#define DMAR_PERM_READ RT_BIT(0)
164/** DMA request permission: Write. */
165#define DMAR_PERM_WRITE RT_BIT(1)
166/** DMA request permission: Execute (ER). */
167#define DMAR_PERM_EXE RT_BIT(2)
168/** DMA request permission: Supervisor privilege (PR). */
169#define DMAR_PERM_PRIV RT_BIT(3)
170/** DMA request permissions: All. */
171#define DMAR_PERM_ALL (DMAR_PERM_READ | DMAR_PERM_WRITE | DMAR_PERM_EXE | DMAR_PERM_PRIV)
172/** @} */
173
174/** Release log prefix string. */
175#define DMAR_LOG_PFX "Intel-IOMMU"
176/** The current saved state version. */
177#define DMAR_SAVED_STATE_VERSION 1
178
179
180/*********************************************************************************************************************************
181* Structures and Typedefs *
182*********************************************************************************************************************************/
183/**
184 * DMAR error diagnostics.
185 * Sorted alphabetically so it's easier to add and locate items, no other reason.
186 *
187 * @note Members of this enum are used as array indices, so no gaps in enum
188 * values are not allowed. Update g_apszDmarDiagDesc when you modify
189 * fields in this enum.
190 */
191typedef enum
192{
193 /* No error, this must be zero! */
194 kDmarDiag_None = 0,
195
196 /* Address Translation Faults. */
197 kDmarDiag_At_Lm_CtxEntry_Not_Present,
198 kDmarDiag_At_Lm_CtxEntry_Read_Failed,
199 kDmarDiag_At_Lm_CtxEntry_Rsvd,
200 kDmarDiag_At_Lm_Pt_At_Block,
201 kDmarDiag_At_Lm_Pt_Aw_Invalid,
202 kDmarDiag_At_Lm_RootEntry_Not_Present,
203 kDmarDiag_At_Lm_RootEntry_Read_Failed,
204 kDmarDiag_At_Lm_RootEntry_Rsvd,
205 kDmarDiag_At_Lm_Tt_Invalid,
206 kDmarDiag_At_Lm_Ut_At_Block,
207 kDmarDiag_At_Lm_Ut_Aw_Invalid,
208 kDmarDiag_At_Rta_Adms_Not_Supported,
209 kDmarDiag_At_Rta_Rsvd,
210 kDmarDiag_At_Rta_Smts_Not_Supported,
211 kDmarDiag_At_Xm_AddrIn_Invalid,
212 kDmarDiag_At_Xm_AddrOut_Invalid,
213 kDmarDiag_At_Xm_Perm_Read_Denied,
214 kDmarDiag_At_Xm_Perm_Write_Denied,
215 kDmarDiag_At_Xm_Pte_Not_Present,
216 kDmarDiag_At_Xm_Pte_Rsvd,
217 kDmarDiag_At_Xm_Pte_Sllps_Invalid,
218 kDmarDiag_At_Xm_Read_Pte_Failed,
219 kDmarDiag_At_Xm_Slpptr_Read_Failed,
220
221 /* CCMD_REG faults. */
222 kDmarDiag_CcmdReg_Not_Supported,
223 kDmarDiag_CcmdReg_Qi_Enabled,
224 kDmarDiag_CcmdReg_Ttm_Invalid,
225
226 /* IQA_REG faults. */
227 kDmarDiag_IqaReg_Dsc_Fetch_Error,
228 kDmarDiag_IqaReg_Dw_128_Invalid,
229 kDmarDiag_IqaReg_Dw_256_Invalid,
230
231 /* Invalidation Queue Error Info. */
232 kDmarDiag_Iqei_Dsc_Type_Invalid,
233 kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
234 kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
235 kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
236 kDmarDiag_Iqei_Ttm_Rsvd,
237
238 /* IQT_REG faults. */
239 kDmarDiag_IqtReg_Qt_Invalid,
240 kDmarDiag_IqtReg_Qt_Not_Aligned,
241
242 /* Interrupt Remapping Faults. */
243 kDmarDiag_Ir_Cfi_Blocked,
244 kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
245 kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
246 kDmarDiag_Ir_Rfi_Irte_Not_Present,
247 kDmarDiag_Ir_Rfi_Irte_Read_Failed,
248 kDmarDiag_Ir_Rfi_Irte_Rsvd,
249 kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
250 kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
251 kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
252 kDmarDiag_Ir_Rfi_Rsvd,
253
254 /* Member for determining array index limit. */
255 kDmarDiag_End,
256
257 /* Usual 32-bit type size hack. */
258 kDmarDiag_32Bit_Hack = 0x7fffffff
259} DMARDIAG;
260AssertCompileSize(DMARDIAG, 4);
261
262#ifdef IN_RING3
263/** DMAR diagnostic enum description expansion.
264 * The below construct ensures typos in the input to this macro are caught
265 * during compile time. */
266# define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
267
268/** DMAR diagnostics description for members in DMARDIAG. */
269static const char *const g_apszDmarDiagDesc[] =
270{
271 DMARDIAG_DESC(None ),
272
273 /* Address Translation Faults. */
274 DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
275 DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
276 DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
277 DMARDIAG_DESC(At_Lm_Pt_At_Block ),
278 DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
279 DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
280 DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
281 DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
282 DMARDIAG_DESC(At_Lm_Tt_Invalid ),
283 DMARDIAG_DESC(At_Lm_Ut_At_Block ),
284 DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
285 DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
286 DMARDIAG_DESC(At_Rta_Rsvd ),
287 DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
288 DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
289 DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
290 DMARDIAG_DESC(At_Xm_Perm_Read_Denied ),
291 DMARDIAG_DESC(At_Xm_Perm_Write_Denied ),
292 DMARDIAG_DESC(At_Xm_Pte_Not_Present ),
293 DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
294 DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
295 DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
296 DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
297
298 /* CCMD_REG faults. */
299 DMARDIAG_DESC(CcmdReg_Not_Supported ),
300 DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
301 DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
302
303 /* IQA_REG faults. */
304 DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
305 DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
306 DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
307
308 /* Invalidation Queue Error Info. */
309 DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
310 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
311 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
312 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
313 DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
314
315 /* IQT_REG faults. */
316 DMARDIAG_DESC(IqtReg_Qt_Invalid ),
317 DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
318
319 /* Interrupt remapping faults. */
320 DMARDIAG_DESC(Ir_Cfi_Blocked ),
321 DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
322 DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
323 DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
324 DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
325 DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
326 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
327 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
328 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
329 DMARDIAG_DESC(Ir_Rfi_Rsvd ),
330 /* kDmarDiag_End */
331};
332AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
333# undef DMARDIAG_DESC
334#endif /* IN_RING3 */
335
336/**
337 * The shared DMAR device state.
338 */
339typedef struct DMAR
340{
341 /** IOMMU device index. */
342 uint32_t idxIommu;
343 /** Padding. */
344 uint32_t u32Padding0;
345
346 /** Registers (group 0). */
347 uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
348 /** Registers (group 1). */
349 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
350
351 /** @name Lazily activated registers.
352 * These are the active values for lazily activated registers. Software is free to
353 * modify the actual register values while remapping/translation is enabled but they
354 * take effect only when explicitly signaled by software, hence we need to hold the
355 * active values separately.
356 * @{ */
357 /** Currently active IRTA_REG. */
358 uint64_t uIrtaReg;
359 /** Currently active RTADDR_REG. */
360 uint64_t uRtaddrReg;
361 /** @} */
362
363 /** @name Register copies for a tiny bit faster and more convenient access.
364 * @{ */
365 /** Copy of VER_REG. */
366 uint8_t uVerReg;
367 /** Alignment. */
368 uint8_t abPadding0[7];
369 /** Copy of CAP_REG. */
370 uint64_t fCapReg;
371 /** Copy of ECAP_REG. */
372 uint64_t fExtCapReg;
373 /** @} */
374
375 /** Host-address width (HAW) base address mask. */
376 uint64_t fHawBaseMask;
377 /** Maximum guest-address width (MGAW) invalid address mask. */
378 uint64_t fMgawInvMask;
379 /** Context-entry qword-1 valid mask. */
380 uint64_t fCtxEntryQw1ValidMask;
381 /** Maximum supported paging level (3, 4 or 5). */
382 uint8_t cMaxPagingLevel;
383 /** DMA request valid permissions mask. */
384 uint8_t fPermValidMask;
385 /** Alignment. */
386 uint8_t abPadding1[6];
387
388 /** The event semaphore the invalidation-queue thread waits on. */
389 SUPSEMEVENT hEvtInvQueue;
390 /** Error diagnostic. */
391 DMARDIAG enmDiag;
392 /** Padding. */
393 uint32_t uPadding0;
394 /** The MMIO handle. */
395 IOMMMIOHANDLE hMmio;
396
397#ifdef VBOX_WITH_STATISTICS
398 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
399 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
400 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
401 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
402
403 STAMCOUNTER StatMsiRemapCfiR3; /**< Number of compatibility-format interrupts remap requests in R3. */
404 STAMCOUNTER StatMsiRemapCfiRZ; /**< Number of compatibility-format interrupts remap requests in RZ. */
405 STAMCOUNTER StatMsiRemapRfiR3; /**< Number of remappable-format interrupts remap requests in R3. */
406 STAMCOUNTER StatMsiRemapRfiRZ; /**< Number of remappable-format interrupts remap requests in RZ. */
407
408 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
409 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
410 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
411 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
412
413 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
414 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
415 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
416 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
417
418 STAMCOUNTER StatCcInvDsc; /**< Number of Context-cache descriptors processed. */
419 STAMCOUNTER StatIotlbInvDsc; /**< Number of IOTLB descriptors processed. */
420 STAMCOUNTER StatDevtlbInvDsc; /**< Number of Device-TLB descriptors processed. */
421 STAMCOUNTER StatIecInvDsc; /**< Number of Interrupt-Entry cache descriptors processed. */
422 STAMCOUNTER StatInvWaitDsc; /**< Number of Invalidation wait descriptors processed. */
423 STAMCOUNTER StatPasidIotlbInvDsc; /**< Number of PASID-based IOTLB descriptors processed. */
424 STAMCOUNTER StatPasidCacheInvDsc; /**< Number of PASID-cache descriptors processed. */
425 STAMCOUNTER StatPasidDevtlbInvDsc; /**< Number of PASID-based device-TLB descriptors processed. */
426#endif
427} DMAR;
428/** Pointer to the DMAR device state. */
429typedef DMAR *PDMAR;
430/** Pointer to the const DMAR device state. */
431typedef DMAR const *PCDMAR;
432AssertCompileMemberAlignment(DMAR, abRegs0, 8);
433AssertCompileMemberAlignment(DMAR, abRegs1, 8);
434
435/**
436 * The ring-3 DMAR device state.
437 */
438typedef struct DMARR3
439{
440 /** Device instance. */
441 PPDMDEVINSR3 pDevInsR3;
442 /** The IOMMU helper. */
443 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
444 /** The invalidation-queue thread. */
445 R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
446} DMARR3;
447/** Pointer to the ring-3 DMAR device state. */
448typedef DMARR3 *PDMARR3;
449/** Pointer to the const ring-3 DMAR device state. */
450typedef DMARR3 const *PCDMARR3;
451
452/**
453 * The ring-0 DMAR device state.
454 */
455typedef struct DMARR0
456{
457 /** Device instance. */
458 PPDMDEVINSR0 pDevInsR0;
459 /** The IOMMU helper. */
460 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
461} DMARR0;
462/** Pointer to the ring-0 IOMMU device state. */
463typedef DMARR0 *PDMARR0;
464/** Pointer to the const ring-0 IOMMU device state. */
465typedef DMARR0 const *PCDMARR0;
466
467/**
468 * The raw-mode DMAR device state.
469 */
470typedef struct DMARRC
471{
472 /** Device instance. */
473 PPDMDEVINSRC pDevInsRC;
474 /** The IOMMU helper. */
475 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
476} DMARRC;
477/** Pointer to the raw-mode DMAR device state. */
478typedef DMARRC *PDMARRC;
479/** Pointer to the const raw-mode DMAR device state. */
480typedef DMARRC const *PCIDMARRC;
481
482/** The DMAR device state for the current context. */
483typedef CTX_SUFF(DMAR) DMARCC;
484/** Pointer to the DMAR device state for the current context. */
485typedef CTX_SUFF(PDMAR) PDMARCC;
486/** Pointer to the const DMAR device state for the current context. */
487typedef CTX_SUFF(PDMAR) const PCDMARCC;
488
489/**
490 * DMAR originated events that generate interrupts.
491 */
492typedef enum DMAREVENTTYPE
493{
494 /** Invalidation completion event. */
495 DMAREVENTTYPE_INV_COMPLETE = 0,
496 /** Fault event. */
497 DMAREVENTTYPE_FAULT
498} DMAREVENTTYPE;
499
500/**
501 * I/O Page.
502 */
503typedef struct DMARIOPAGE
504{
505 /** The base DMA address of a page. */
506 RTGCPHYS GCPhysBase;
507 /** The page shift. */
508 uint8_t cShift;
509 /** The permissions of this page (DMAR_PERM_XXX). */
510 uint8_t fPerm;
511} DMARIOPAGE;
512/** Pointer to an I/O page. */
513typedef DMARIOPAGE *PDMARIOPAGE;
514/** Pointer to a const I/O address range. */
515typedef DMARIOPAGE const *PCDMARIOPAGE;
516
517/**
518 * I/O Address Range.
519 */
520typedef struct DMARIOADDRRANGE
521{
522 /** The starting DMA address of this range. */
523 uint64_t uAddr;
524 /** The size of the range (in bytes). */
525 size_t cb;
526 /** The permissions of this range (DMAR_PERM_XXX). */
527 uint8_t fPerm;
528} DMARIOADDRRANGE;
529/** Pointer to an I/O address range. */
530typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
531/** Pointer to a const I/O address range. */
532typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
533
534/**
535 * DMA Memory Request (Input).
536 */
537typedef struct DMARMEMREQIN
538{
539 /** The address range being accessed. */
540 DMARIOADDRRANGE AddrRange;
541 /** The source device ID (bus, device, function). */
542 uint16_t idDevice;
543 /** The PASID if present (can be NIL_PCIPASID). */
544 PCIPASID Pasid;
545 /* The address translation type. */
546 PCIADDRTYPE enmAddrType;
547 /** The request type. */
548 VTDREQTYPE enmReqType;
549} DMARMEMREQIN;
550/** Pointer to a DMA memory request input. */
551typedef DMARMEMREQIN *PDMARMEMREQIN;
552/** Pointer to a const DMA memory input. */
553typedef DMARMEMREQIN const *PCDMARMEMREQIN;
554
555/**
556 * DMA Memory Request (Output).
557 */
558typedef struct DMARMEMREQOUT
559{
560 /** The address range of the translated region. */
561 DMARIOADDRRANGE AddrRange;
562 /** The domain ID of the translated region. */
563 uint16_t idDomain;
564} DMARMEMREQOUT;
565/** Pointer to a DMA memory request output. */
566typedef DMARMEMREQOUT *PDMARMEMREQOUT;
567/** Pointer to a const DMA memory request output. */
568typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
569
570/**
571 * DMA Memory Request (Auxiliary Info).
572 * These get updated and used as part of the translation process.
573 */
574typedef struct DMARMEMREQAUX
575{
576 /** The table translation mode (VTD_TTM_XXX). */
577 uint8_t fTtm;
578 /** The fault processing disabled (FPD) bit. */
579 uint8_t fFpd;
580 /** The paging level of the translation. */
581 uint8_t cPagingLevel;
582 uint8_t abPadding[5];
583 /** The address of the first-level page-table. */
584 uint64_t GCPhysFlPt;
585 /** The address of second-level page-table. */
586 uint64_t GCPhysSlPt;
587} DMARMEMREQAUX;
588/** Pointer to a DMA memory request output. */
589typedef DMARMEMREQAUX *PDMARMEMREQAUX;
590/** Pointer to a const DMA memory request output. */
591typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
592
593/**
594 * DMA Memory Request Remapping Information.
595 */
596typedef struct DMARMEMREQREMAP
597{
598 /** The DMA memory request input. */
599 DMARMEMREQIN In;
600 /** DMA memory request auxiliary information. */
601 DMARMEMREQAUX Aux;
602 /** The DMA memory request output. */
603 DMARMEMREQOUT Out;
604} DMARMEMREQREMAP;
605/** Pointer to a DMA remap info. */
606typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
607/** Pointer to a const DMA remap info. */
608typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
609
610/**
611 * Callback function to lookup a DMA address.
612 *
613 * @returns VBox status code.
614 * @param pDevIns The IOMMU device instance.
615 * @param pMemReqIn The DMA memory request input.
616 * @param pMemReqAux The DMA memory request auxiliary info.
617 * @param pIoPageOut Where to store the output of the lookup.
618 */
619typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
620 PDMARIOPAGE pIoPageOut));
621/** Pointer to a DMA address-lookup function. */
622typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
623
624
625/*********************************************************************************************************************************
626* Global Variables *
627*********************************************************************************************************************************/
628/**
629 * Read-write masks for DMAR registers (group 0).
630 */
631static uint32_t const g_au32RwMasks0[] =
632{
633 /* Offset Register Low High */
634 /* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
635 /* 0x004 Reserved */ 0,
636 /* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
637 /* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
638 /* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
639 /* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
640 /* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
641 /* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
642 /* 0x030 Reserved */ 0,
643 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
644 /* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
645 /* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
646 /* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
647 /* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
648 /* 0x048 Reserved */ 0, 0,
649 /* 0x050 Reserved */ 0, 0,
650 /* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
651 /* 0x060 Reserved */ 0,
652 /* 0x064 PMEN_REG */ 0, /* RO as we don't support PLMR and PHMR. */
653 /* 0x068 PLMBASE_REG */ 0, /* RO as we don't support PLMR. */
654 /* 0x06c PLMLIMIT_REG */ 0, /* RO as we don't support PLMR. */
655 /* 0x070 PHMBASE_REG */ 0, 0, /* RO as we don't support PHMR. */
656 /* 0x078 PHMLIMIT_REG */ 0, 0, /* RO as we don't support PHMR. */
657 /* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
658 /* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
659 /* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
660 /* 0x098 Reserved */ 0,
661 /* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
662 /* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
663 /* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
664 /* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
665 /* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
666 /* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
667 /* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
668 /* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
669 /* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
670 /* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
671 /* 0x0d8 Reserved */ 0,
672 /* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
673 /* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
674 /* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
675 /* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
676 /* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
677 /* 0x0f0 Reserved */ 0, 0,
678 /* 0x0f8 Reserved */ 0, 0,
679 /* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
680 /* 0x108 MTRRDEF_REG */ 0, 0, /* RO as we don't support MTS. */
681 /* 0x110 Reserved */ 0, 0,
682 /* 0x118 Reserved */ 0, 0,
683 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0, /* RO as we don't support MTS. */
684 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
685 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
686 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
687 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
688 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
689 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
690 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
691 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
692 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
693 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
694 /* 0x178 Reserved */ 0, 0,
695 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0, /* RO as we don't support MTS. */
696 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
697 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
698 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
699 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
700 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
701 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
702 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
703 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
704 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
705 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
706 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
707 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
708 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
709 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
710 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
711 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
712 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
713 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
714 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
715};
716AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
717
718/**
719 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
720 */
721static uint32_t const g_au32Rw1cMasks0[] =
722{
723 /* Offset Register Low High */
724 /* 0x000 VER_REG */ 0,
725 /* 0x004 Reserved */ 0,
726 /* 0x008 CAP_REG */ 0, 0,
727 /* 0x010 ECAP_REG */ 0, 0,
728 /* 0x018 GCMD_REG */ 0,
729 /* 0x01c GSTS_REG */ 0,
730 /* 0x020 RTADDR_REG */ 0, 0,
731 /* 0x028 CCMD_REG */ 0, 0,
732 /* 0x030 Reserved */ 0,
733 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
734 /* 0x038 FECTL_REG */ 0,
735 /* 0x03c FEDATA_REG */ 0,
736 /* 0x040 FEADDR_REG */ 0,
737 /* 0x044 FEUADDR_REG */ 0,
738 /* 0x048 Reserved */ 0, 0,
739 /* 0x050 Reserved */ 0, 0,
740 /* 0x058 AFLOG_REG */ 0, 0,
741 /* 0x060 Reserved */ 0,
742 /* 0x064 PMEN_REG */ 0,
743 /* 0x068 PLMBASE_REG */ 0,
744 /* 0x06c PLMLIMIT_REG */ 0,
745 /* 0x070 PHMBASE_REG */ 0, 0,
746 /* 0x078 PHMLIMIT_REG */ 0, 0,
747 /* 0x080 IQH_REG */ 0, 0,
748 /* 0x088 IQT_REG */ 0, 0,
749 /* 0x090 IQA_REG */ 0, 0,
750 /* 0x098 Reserved */ 0,
751 /* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
752 /* 0x0a0 IECTL_REG */ 0,
753 /* 0x0a4 IEDATA_REG */ 0,
754 /* 0x0a8 IEADDR_REG */ 0,
755 /* 0x0ac IEUADDR_REG */ 0,
756 /* 0x0b0 IQERCD_REG */ 0, 0,
757 /* 0x0b8 IRTA_REG */ 0, 0,
758 /* 0x0c0 PQH_REG */ 0, 0,
759 /* 0x0c8 PQT_REG */ 0, 0,
760 /* 0x0d0 PQA_REG */ 0, 0,
761 /* 0x0d8 Reserved */ 0,
762 /* 0x0dc PRS_REG */ 0,
763 /* 0x0e0 PECTL_REG */ 0,
764 /* 0x0e4 PEDATA_REG */ 0,
765 /* 0x0e8 PEADDR_REG */ 0,
766 /* 0x0ec PEUADDR_REG */ 0,
767 /* 0x0f0 Reserved */ 0, 0,
768 /* 0x0f8 Reserved */ 0, 0,
769 /* 0x100 MTRRCAP_REG */ 0, 0,
770 /* 0x108 MTRRDEF_REG */ 0, 0,
771 /* 0x110 Reserved */ 0, 0,
772 /* 0x118 Reserved */ 0, 0,
773 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
774 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
775 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
776 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
777 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
778 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
779 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
780 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
781 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
782 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
783 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
784 /* 0x178 Reserved */ 0, 0,
785 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
786 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
787 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
788 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
789 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
790 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
791 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
792 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
793 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
794 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
795 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
796 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
797 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
798 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
799 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
800 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
801 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
802 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
803 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
804 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
805};
806AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
807
808/**
809 * Read-write masks for DMAR registers (group 1).
810 */
811static uint32_t const g_au32RwMasks1[] =
812{
813 /* Offset Register Low High */
814 /* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
815 /* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
816 /* 0xe10 VCMD_REG */ 0, 0, /* RO: VCS not supported. */
817 /* 0xe18 VCMDRSVD_REG */ 0, 0,
818 /* 0xe20 VCRSP_REG */ 0, 0, /* RO: VCS not supported. */
819 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
820 /* 0xe30 Reserved */ 0, 0,
821 /* 0xe38 Reserved */ 0, 0,
822 /* 0xe40 Reserved */ 0, 0,
823 /* 0xe48 Reserved */ 0, 0,
824 /* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
825 /* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
826 /* 0xe60 Reserved */ 0, 0,
827 /* 0xe68 Reserved */ 0, 0,
828 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
829 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
830};
831AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
832AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
833
834/**
835 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
836 */
837static uint32_t const g_au32Rw1cMasks1[] =
838{
839 /* Offset Register Low High */
840 /* 0xe00 VCCAP_REG */ 0, 0,
841 /* 0xe08 VCMD_EO_REG */ 0, 0,
842 /* 0xe10 VCMD_REG */ 0, 0,
843 /* 0xe18 VCMDRSVD_REG */ 0, 0,
844 /* 0xe20 VCRSP_REG */ 0, 0,
845 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
846 /* 0xe30 Reserved */ 0, 0,
847 /* 0xe38 Reserved */ 0, 0,
848 /* 0xe40 Reserved */ 0, 0,
849 /* 0xe48 Reserved */ 0, 0,
850 /* 0xe50 IVA_REG */ 0, 0,
851 /* 0xe58 IOTLB_REG */ 0, 0,
852 /* 0xe60 Reserved */ 0, 0,
853 /* 0xe68 Reserved */ 0, 0,
854 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
855 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
856};
857AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
858
859/** Array of RW masks for each register group. */
860static uint8_t const *g_apbRwMasks[] = { (uint8_t *)&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
861
862/** Array of RW1C masks for each register group. */
863static uint8_t const *g_apbRw1cMasks[] = { (uint8_t *)&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
864
865/* Masks arrays must be identical in size (even bounds checking code assumes this). */
866AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
867
868#ifdef IN_RING3
869/** Array of valid domain-ID bits. */
870static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
871AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
872#endif
873
874
875#ifndef VBOX_DEVICE_STRUCT_TESTCASE
876#ifdef IN_RING3
877/**
878 * Returns the supported adjusted guest-address width (SAGAW) given the maximum
879 * guest address width (MGAW).
880 *
881 * @returns The CAP_REG.SAGAW value.
882 * @param uMgaw The CAP_REG.MGAW value.
883 */
884static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
885{
886 /*
887 * It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
888 * 5-level paging but not 4 or 3-level paging. So smaller page-table levels
889 * are always OR'ed in below.
890 *
891 * The bit values below (57, 48, 39 bits) represents the levels of page-table walks
892 * for 4KB base page size (5-level, 4-level and 3-level paging respectively).
893 *
894 * See Intel VT-d spec. 10.4.2 "Capability Register".
895 */
896 ++uMgaw;
897 uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) | RT_BIT(2) | RT_BIT(1)
898 : uMgaw >= 48 ? RT_BIT(2) | RT_BIT(1)
899 : uMgaw >= 39 ? RT_BIT(1)
900 : 0;
901 return fSagaw;
902}
903
904
905/**
906 * Returns the maximum supported paging level given the supported adjusted
907 * guest-address width (SAGAW) field.
908 *
909 * @returns The highest paging level supported, 0 if invalid.
910 * @param fSagaw The CAP_REG.SAGAW value.
911 */
912static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
913{
914 uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
915 : fSagaw & RT_BIT(2) ? 4
916 : fSagaw & RT_BIT(1) ? 3
917 : 0;
918 return cMaxPagingLevel;
919}
920
921
922/**
923 * Returns table translation mode's descriptive name.
924 *
925 * @returns The descriptive name.
926 * @param uTtm The RTADDR_REG.TTM value.
927 */
928static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
929{
930 Assert(!(uTtm & 3));
931 static const char* s_apszTtmNames[] =
932 {
933 "Legacy Mode",
934 "Scalable Mode",
935 "Reserved",
936 "Abort-DMA Mode"
937 };
938 return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
939}
940#endif /* IN_RING3 */
941
942
943/**
944 * Returns whether the interrupt remapping (IR) fault is qualified or not.
945 *
946 * @returns @c true if qualified, @c false otherwise.
947 * @param enmIrFault The interrupt remapping fault condition.
948 */
949static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
950{
951 switch (enmIrFault)
952 {
953 case VTDIRFAULT_IRTE_NOT_PRESENT:
954 case VTDIRFAULT_IRTE_PRESENT_RSVD:
955 case VTDIRFAULT_IRTE_PRESENT_INVALID:
956 case VTDIRFAULT_PID_READ_FAILED:
957 case VTDIRFAULT_PID_RSVD:
958 return true;
959 default:
960 return false;
961 }
962}
963
964
965/**
966 * Gets the index of the group the register belongs to given its MMIO offset.
967 *
968 * @returns The group index.
969 * @param offReg The MMIO offset of the register.
970 * @param cbReg The size of the access being made (for bounds checking on
971 * debug builds).
972 */
973DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
974{
975 uint16_t const offLast = offReg + cbReg - 1;
976 AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
977 AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
978 return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
979}
980
981
982/**
983 * Gets the group the register belongs to given its MMIO offset.
984 *
985 * @returns Pointer to the first element of the register group.
986 * @param pThis The shared DMAR device state.
987 * @param offReg The MMIO offset of the register.
988 * @param cbReg The size of the access being made (for bounds checking on
989 * debug builds).
990 * @param pIdxGroup Where to store the index of the register group the register
991 * belongs to.
992 */
993DECLINLINE(uint8_t *) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
994{
995 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
996 uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
997 return apbRegs[*pIdxGroup];
998}
999
1000
1001/**
1002 * Const/read-only version of dmarRegGetGroup.
1003 *
1004 * @copydoc dmarRegGetGroup
1005 */
1006DECLINLINE(uint8_t const*) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
1007{
1008 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
1009 uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
1010 return apbRegs[*pIdxGroup];
1011}
1012
1013
1014/**
1015 * Writes a 32-bit register with the exactly the supplied value.
1016 *
1017 * @param pThis The shared DMAR device state.
1018 * @param offReg The MMIO offset of the register.
1019 * @param uReg The 32-bit value to write.
1020 */
1021static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
1022{
1023 uint8_t idxGroup;
1024 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1025 NOREF(idxGroup);
1026 *(uint32_t *)(pabRegs + offReg) = uReg;
1027}
1028
1029
1030/**
1031 * Writes a 64-bit register with the exactly the supplied value.
1032 *
1033 * @param pThis The shared DMAR device state.
1034 * @param offReg The MMIO offset of the register.
1035 * @param uReg The 64-bit value to write.
1036 */
1037static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1038{
1039 uint8_t idxGroup;
1040 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1041 NOREF(idxGroup);
1042 *(uint64_t *)(pabRegs + offReg) = uReg;
1043}
1044
1045
1046/**
1047 * Reads a 32-bit register with exactly the value it contains.
1048 *
1049 * @returns The raw register value.
1050 * @param pThis The shared DMAR device state.
1051 * @param offReg The MMIO offset of the register.
1052 */
1053static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1054{
1055 uint8_t idxGroup;
1056 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1057 NOREF(idxGroup);
1058 return *(uint32_t *)(pabRegs + offReg);
1059}
1060
1061
1062/**
1063 * Reads a 64-bit register with exactly the value it contains.
1064 *
1065 * @returns The raw register value.
1066 * @param pThis The shared DMAR device state.
1067 * @param offReg The MMIO offset of the register.
1068 */
1069static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1070{
1071 uint8_t idxGroup;
1072 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1073 NOREF(idxGroup);
1074 return *(uint64_t *)(pabRegs + offReg);
1075}
1076
1077
1078/**
1079 * Reads a 32-bit register with exactly the value it contains along with their
1080 * corresponding masks
1081 *
1082 * @param pThis The shared DMAR device state.
1083 * @param offReg The MMIO offset of the register.
1084 * @param puReg Where to store the raw 32-bit register value.
1085 * @param pfRwMask Where to store the RW mask corresponding to this register.
1086 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1087 */
1088static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
1089{
1090 uint8_t idxGroup;
1091 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1092 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1093 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1094 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1095 *puReg = *(uint32_t *)(pabRegs + offReg);
1096 *pfRwMask = *(uint32_t *)(pabRwMasks + offReg);
1097 *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
1098}
1099
1100
1101/**
1102 * Reads a 64-bit register with exactly the value it contains along with their
1103 * corresponding masks.
1104 *
1105 * @param pThis The shared DMAR device state.
1106 * @param offReg The MMIO offset of the register.
1107 * @param puReg Where to store the raw 64-bit register value.
1108 * @param pfRwMask Where to store the RW mask corresponding to this register.
1109 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1110 */
1111static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
1112{
1113 uint8_t idxGroup;
1114 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1115 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1116 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1117 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1118 *puReg = *(uint64_t *)(pabRegs + offReg);
1119 *pfRwMask = *(uint64_t *)(pabRwMasks + offReg);
1120 *pfRw1cMask = *(uint64_t *)(pabRw1cMasks + offReg);
1121}
1122
1123
1124/**
1125 * Writes a 32-bit register as it would be when written by software.
1126 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1127 *
1128 * @returns The value that's actually written to the register.
1129 * @param pThis The shared DMAR device state.
1130 * @param offReg The MMIO offset of the register.
1131 * @param uReg The 32-bit value to write.
1132 * @param puPrev Where to store the register value prior to writing.
1133 */
1134static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1135{
1136 /* Read current value from the 32-bit register. */
1137 uint32_t uCurReg;
1138 uint32_t fRwMask;
1139 uint32_t fRw1cMask;
1140 dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1141 *puPrev = uCurReg;
1142
1143 uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1144 uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1145 uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1146 uint32_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
1147
1148 /* Write new value to the 32-bit register. */
1149 dmarRegWriteRaw32(pThis, offReg, uNewReg);
1150 return uNewReg;
1151}
1152
1153
1154/**
1155 * Writes a 64-bit register as it would be when written by software.
1156 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1157 *
1158 * @returns The value that's actually written to the register.
1159 * @param pThis The shared DMAR device state.
1160 * @param offReg The MMIO offset of the register.
1161 * @param uReg The 64-bit value to write.
1162 * @param puPrev Where to store the register value prior to writing.
1163 */
1164static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1165{
1166 /* Read current value from the 64-bit register. */
1167 uint64_t uCurReg;
1168 uint64_t fRwMask;
1169 uint64_t fRw1cMask;
1170 dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1171 *puPrev = uCurReg;
1172
1173 uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1174 uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1175 uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1176 uint64_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
1177
1178 /* Write new value to the 64-bit register. */
1179 dmarRegWriteRaw64(pThis, offReg, uNewReg);
1180 return uNewReg;
1181}
1182
1183
1184/**
1185 * Reads a 32-bit register as it would be when read by software.
1186 *
1187 * @returns The register value.
1188 * @param pThis The shared DMAR device state.
1189 * @param offReg The MMIO offset of the register.
1190 */
1191static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1192{
1193 return dmarRegReadRaw32(pThis, offReg);
1194}
1195
1196
1197/**
1198 * Reads a 64-bit register as it would be when read by software.
1199 *
1200 * @returns The register value.
1201 * @param pThis The shared DMAR device state.
1202 * @param offReg The MMIO offset of the register.
1203 */
1204static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1205{
1206 return dmarRegReadRaw64(pThis, offReg);
1207}
1208
1209
1210/**
1211 * Modifies a 32-bit register.
1212 *
1213 * @param pThis The shared DMAR device state.
1214 * @param offReg The MMIO offset of the register.
1215 * @param fAndMask The AND mask (applied first).
1216 * @param fOrMask The OR mask.
1217 * @remarks This does NOT apply RO or RW1C masks while modifying the
1218 * register.
1219 */
1220static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1221{
1222 uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1223 uReg = (uReg & fAndMask) | fOrMask;
1224 dmarRegWriteRaw32(pThis, offReg, uReg);
1225}
1226
1227
1228/**
1229 * Modifies a 64-bit register.
1230 *
1231 * @param pThis The shared DMAR device state.
1232 * @param offReg The MMIO offset of the register.
1233 * @param fAndMask The AND mask (applied first).
1234 * @param fOrMask The OR mask.
1235 * @remarks This does NOT apply RO or RW1C masks while modifying the
1236 * register.
1237 */
1238static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1239{
1240 uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1241 uReg = (uReg & fAndMask) | fOrMask;
1242 dmarRegWriteRaw64(pThis, offReg, uReg);
1243}
1244
1245
1246/**
1247 * Checks if the invalidation-queue is empty.
1248 *
1249 * Extended version which optionally returns the current queue head and tail
1250 * offsets.
1251 *
1252 * @returns @c true if empty, @c false otherwise.
1253 * @param pThis The shared DMAR device state.
1254 * @param poffQh Where to store the queue head offset. Optional, can be NULL.
1255 * @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1256 */
1257static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t *poffQh, uint32_t *poffQt)
1258{
1259 /* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1260 uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1261 uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1262
1263 /* Don't bother masking QT, QH since other bits are RsvdZ. */
1264 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1265 Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1266 if (poffQh)
1267 *poffQh = uIqhReg;
1268 if (poffQt)
1269 *poffQt = uIqtReg;
1270 return uIqtReg == uIqhReg;
1271}
1272
1273
1274/**
1275 * Checks if the invalidation-queue is empty.
1276 *
1277 * @returns @c true if empty, @c false otherwise.
1278 * @param pThis The shared DMAR device state.
1279 */
1280static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1281{
1282 return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh */, NULL /* poffQt */);
1283}
1284
1285
1286/**
1287 * Checks if the invalidation-queue is capable of processing requests.
1288 *
1289 * @returns @c true if the invalidation-queue can process requests, @c false
1290 * otherwise.
1291 * @param pThis The shared DMAR device state.
1292 */
1293static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1294{
1295 /* Check if queued-invalidation is enabled. */
1296 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1297 if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1298 {
1299 /* Check if there are no invalidation-queue or timeout errors. */
1300 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1301 if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_ITE_MASK)))
1302 return true;
1303 }
1304 return false;
1305}
1306
1307
1308/**
1309 * Wakes up the invalidation-queue thread if there are requests to be processed.
1310 *
1311 * @param pDevIns The IOMMU device instance.
1312 */
1313static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1314{
1315 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1316 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1317 LogFlowFunc(("\n"));
1318
1319 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1320
1321 if ( dmarInvQueueCanProcessRequests(pThis)
1322 && !dmarInvQueueIsEmpty(pThis))
1323 {
1324 Log4Func(("Signaling the invalidation-queue thread\n"));
1325 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1326 }
1327}
1328
1329
1330/**
1331 * Raises an event on behalf of the DMAR.
1332 *
1333 * These are events that are generated by the DMAR itself (like faults and
1334 * invalidation completion notifications).
1335 *
1336 * @param pDevIns The IOMMU device instance.
1337 * @param enmEventType The DMAR event type.
1338 *
1339 * @remarks The DMAR lock must be held while calling this function.
1340 */
1341static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1342{
1343 uint16_t offCtlReg;
1344 uint32_t fIntrMaskedMask;
1345 uint32_t fIntrPendingMask;
1346 uint16_t offMsiAddrLoReg;
1347 uint16_t offMsiAddrHiReg;
1348 uint16_t offMsiDataReg;
1349 switch (enmEventType)
1350 {
1351 case DMAREVENTTYPE_INV_COMPLETE:
1352 {
1353 offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1354 fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1355 fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1356 offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1357 offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1358 offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1359 break;
1360 }
1361
1362 case DMAREVENTTYPE_FAULT:
1363 {
1364 offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1365 fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1366 fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1367 offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1368 offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1369 offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1370 break;
1371 }
1372
1373 default:
1374 {
1375 /* Shouldn't ever happen. */
1376 AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1377 }
1378 }
1379
1380 /* Check if software has masked the interrupt. */
1381 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1382 uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1383 if (!(uCtlReg & fIntrMaskedMask))
1384 {
1385 /*
1386 * Interrupt is unmasked, raise it.
1387 * Interrupts generated by the DMAR have trigger mode and level as 0.
1388 * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1389 */
1390 MSIMSG Msi;
1391 Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1392 Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1393 Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1394 Assert(Msi.Data.n.u1Level == 0);
1395 Assert(Msi.Data.n.u1TriggerMode == 0);
1396
1397 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1398 pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1399
1400 /* Clear interrupt pending bit. */
1401 uCtlReg &= ~fIntrPendingMask;
1402 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1403 }
1404 else
1405 {
1406 /* Interrupt is masked, set the interrupt pending bit. */
1407 uCtlReg |= fIntrPendingMask;
1408 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1409 }
1410}
1411
1412
1413/**
1414 * Raises an interrupt in response to a fault event.
1415 *
1416 * @param pDevIns The IOMMU device instance.
1417 *
1418 * @remarks This assumes the caller has already set the required status bits in the
1419 * FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1420 */
1421static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1422{
1423 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1424 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1425
1426#ifdef VBOX_STRICT
1427 {
1428 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
1429 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1430 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK
1431 /* | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_AFO_MASK */ /* AFL not supported */
1432 /* | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK */ /* Device-TLBs not supported */
1433 | VTD_BF_FSTS_REG_IQE_MASK;
1434 Assert(uFstsReg & fFaultMask);
1435 }
1436#endif
1437 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1438}
1439
1440
1441#ifdef IN_RING3
1442/**
1443 * Raises an interrupt in response to an invalidation (complete) event.
1444 *
1445 * @param pDevIns The IOMMU device instance.
1446 */
1447static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1448{
1449 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1450 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1451 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1452
1453 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1454 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1455 {
1456 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1457 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1458 }
1459}
1460#endif /* IN_RING3 */
1461
1462
1463/**
1464 * Checks if a primary fault can be recorded.
1465 *
1466 * @returns @c true if the fault can be recorded, @c false otherwise.
1467 * @param pDevIns The IOMMU device instance.
1468 * @param pThis The shared DMAR device state.
1469 *
1470 * @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1471 * NOT call it unless there is a fault condition!
1472 */
1473static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1474{
1475 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1476 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1477
1478 uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1479 if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1480 return false;
1481
1482 /*
1483 * If we add more FRCD registers, we'll have to loop through them here.
1484 * Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1485 * nor do we need to increment FRI.
1486 *
1487 * See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1488 */
1489 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1490 uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1491 if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1492 {
1493 uFstsReg |= VTD_BF_FSTS_REG_PFO_MASK;
1494 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1495 return false;
1496 }
1497
1498 return true;
1499}
1500
1501
1502/**
1503 * Records a primary fault.
1504 *
1505 * @param pDevIns The IOMMU device instance.
1506 * @param uFrcdHi The FRCD_HI_REG value for this fault.
1507 * @param uFrcdLo The FRCD_LO_REG value for this fault.
1508 */
1509static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1510{
1511 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1512 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1513
1514 DMAR_LOCK(pDevIns, pThisCC);
1515
1516 /* We don't support advance fault logging. */
1517 Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1518
1519 if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1520 {
1521 /* Update the fault recording registers with the fault information. */
1522 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1523 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1524
1525 /* Set the Pending Primary Fault (PPF) field in the status register. */
1526 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1527
1528 /* Raise interrupt if necessary. */
1529 dmarFaultEventRaiseInterrupt(pDevIns);
1530 }
1531
1532 DMAR_UNLOCK(pDevIns, pThisCC);
1533}
1534
1535
1536/**
1537 * Records an interrupt request fault.
1538 *
1539 * @param pDevIns The IOMMU device instance.
1540 * @param enmDiag The diagnostic reason.
1541 * @param idDevice The device ID (bus, device, function).
1542 * @param idxIntr The interrupt index.
1543 * @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1544 * not qualified.
1545 */
1546static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1547{
1548 /*
1549 * Update the diagnostic reason (even if software wants to supress faults).
1550 */
1551 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1552 pThis->enmDiag = enmDiag;
1553
1554 /*
1555 * Figure out the fault reason to report to software from our diagnostic code.
1556 * The case labels below are sorted alphabetically for convenience.
1557 */
1558 VTDIRFAULT enmIrFault;
1559 switch (enmDiag)
1560 {
1561 case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1562 case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1563 case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1564 case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1565 case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1566 case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1567 case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1568 case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1569 case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1570 case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1571
1572 /* Shouldn't ever happen. */
1573 default:
1574 {
1575 AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1576 enmDiag));
1577 }
1578 }
1579
1580 /*
1581 * Qualified faults are those that can be suppressed by software using the FPD bit
1582 * in the interrupt-remapping table entry.
1583 */
1584 bool fFpd;
1585 bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1586 if (fQualifiedFault)
1587 {
1588 AssertReturnVoid(pIrte);
1589 fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1590 }
1591 else
1592 fFpd = false;
1593
1594 if (!fFpd)
1595 {
1596 /* Construct and record the error. */
1597 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1598 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1599 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1600 uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1601 dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1602 }
1603}
1604
1605
1606/**
1607 * Records an address translation fault.
1608 *
1609 * @param pDevIns The IOMMU device instance.
1610 * @param enmDiag The diagnostic reason.
1611 * @param pMemReqIn The DMA memory request input.
1612 * @param pMemReqAux The DMA memory request auxiliary info.
1613 */
1614static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1615{
1616 /*
1617 * Update the diagnostic reason (even if software wants to supress faults).
1618 */
1619 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1620 pThis->enmDiag = enmDiag;
1621
1622 /*
1623 * Qualified faults are those that can be suppressed by software using the FPD bit
1624 * in the context entry, scalable-mode context entry etc.
1625 */
1626 if (!pMemReqAux->fFpd)
1627 {
1628 /*
1629 * Figure out the fault reason to report to software from our diagnostic code.
1630 * The case labels below are sorted alphabetically for convenience.
1631 */
1632 VTDATFAULT enmAtFault;
1633 bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1634 switch (enmDiag)
1635 {
1636 /* LM (Legacy Mode) faults. */
1637 case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1638 case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1639 case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1640 case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1641 case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1642 case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1643 case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1644 case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1645 case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1646 case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1647 case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1648
1649 /* RTA (Root Table Address) faults. */
1650 case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1651 case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1652 case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1653
1654 /* XM (Legacy mode or Scalable Mode) faults. */
1655 case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1656 case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1657 case kDmarDiag_At_Xm_Perm_Read_Denied: enmAtFault = fLm ? VTDATFAULT_LGN_3 : VTDATFAULT_SGN_7; break;
1658 case kDmarDiag_At_Xm_Perm_Write_Denied: enmAtFault = fLm ? VTDATFAULT_LGN_2 : VTDATFAULT_SGN_6; break;
1659 case kDmarDiag_At_Xm_Pte_Not_Present:
1660 case kDmarDiag_At_Xm_Pte_Rsvd: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1661 case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1662 case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1663 case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1664
1665 /* Shouldn't ever happen. */
1666 default:
1667 {
1668 AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1669 DMAR_LOG_PFX, enmDiag));
1670 }
1671 }
1672
1673 /* Construct and record the error. */
1674 uint16_t const idDevice = pMemReqIn->idDevice;
1675 uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1676 uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1677 uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1678 uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1679 bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1680 uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1681 PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1682
1683 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1684 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1685 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1686 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1687 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1688 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1689 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1690 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1691 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1692 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1693 uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1694 dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1695 }
1696}
1697
1698
1699/**
1700 * Records an IQE fault.
1701 *
1702 * @param pDevIns The IOMMU device instance.
1703 * @param enmIqei The IQE information.
1704 * @param enmDiag The diagnostic reason.
1705 */
1706static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1707{
1708 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1709 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1710
1711 DMAR_LOCK(pDevIns, pThisCC);
1712
1713 /* Update the diagnostic reason. */
1714 pThis->enmDiag = enmDiag;
1715
1716 /* Set the error bit. */
1717 uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1718 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1719
1720 /* Set the error information. */
1721 uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1722 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1723
1724 dmarFaultEventRaiseInterrupt(pDevIns);
1725
1726 DMAR_UNLOCK(pDevIns, pThisCC);
1727}
1728
1729
1730/**
1731 * Handles writes to GCMD_REG.
1732 *
1733 * @returns Strict VBox status code.
1734 * @param pDevIns The IOMMU device instance.
1735 * @param uGcmdReg The value written to GCMD_REG.
1736 */
1737static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1738{
1739 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1740 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1741 uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1742 uint64_t const fExtCapReg = pThis->fExtCapReg;
1743
1744 /* Queued-invalidation. */
1745 if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1746 && (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1747 {
1748 if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1749 {
1750 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1751 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1752 }
1753 else
1754 {
1755 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1756 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1757 }
1758 }
1759
1760 if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1761 {
1762 /* Set Interrupt Remapping Table Pointer (SIRTP). */
1763 if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1764 {
1765 /** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1766 * supported. */
1767 pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1768 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1769 }
1770
1771 /* Interrupt remapping. */
1772 if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1773 {
1774 if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1775 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1776 else
1777 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1778 }
1779
1780 /* Compatibility format interrupts. */
1781 if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1782 {
1783 if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1784 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1785 else
1786 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1787 }
1788 }
1789
1790 /* Set Root Table Pointer (SRTP). */
1791 if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1792 {
1793 /** @todo Perform global invalidation of all remapping translation caches when
1794 * ESRTPS is supported. */
1795 pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1796 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1797 }
1798
1799 /* Translation (DMA remapping). */
1800 if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1801 {
1802 if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1803 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1804 else
1805 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1806 }
1807
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/**
1813 * Handles writes to CCMD_REG.
1814 *
1815 * @returns Strict VBox status code.
1816 * @param pDevIns The IOMMU device instance.
1817 * @param offReg The MMIO register offset.
1818 * @param cbReg The size of the MMIO access (in bytes).
1819 * @param uCcmdReg The value written to CCMD_REG.
1820 */
1821static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1822{
1823 /* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1824 if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1825 {
1826 /* Check if we need to invalidate the context-context. */
1827 bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1828 if (fIcc)
1829 {
1830 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1831 uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1832 if (uMajorVersion < 6)
1833 {
1834 /* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1835 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1836 if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1837 {
1838 /* Verify table translation mode is legacy. */
1839 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1840 if (fTtm == VTD_TTM_LEGACY_MODE)
1841 {
1842 /** @todo Invalidate. */
1843 return VINF_SUCCESS;
1844 }
1845 pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1846 }
1847 else
1848 pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1849 }
1850 else
1851 pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1852 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1853 }
1854 }
1855 return VINF_SUCCESS;
1856}
1857
1858
1859/**
1860 * Handles writes to FECTL_REG.
1861 *
1862 * @returns Strict VBox status code.
1863 * @param pDevIns The IOMMU device instance.
1864 * @param uFectlReg The value written to FECTL_REG.
1865 */
1866static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1867{
1868 /*
1869 * If software unmasks the interrupt when the interrupt is pending, we must raise
1870 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1871 */
1872 if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1873 && ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1874 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1875 return VINF_SUCCESS;
1876}
1877
1878
1879/**
1880 * Handles writes to FSTS_REG.
1881 *
1882 * @returns Strict VBox status code.
1883 * @param pDevIns The IOMMU device instance.
1884 * @param uFstsReg The value written to FSTS_REG.
1885 * @param uPrev The value in FSTS_REG prior to writing it.
1886 */
1887static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1888{
1889 /*
1890 * If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1891 * the interrupt pending (IP) bit must be cleared.
1892 *
1893 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1894 */
1895 uint32_t const fChanged = uPrev ^ uFstsReg;
1896 if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK
1897 | VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_PFO_MASK))
1898 {
1899 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1900 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1901 }
1902 return VINF_SUCCESS;
1903}
1904
1905
1906/**
1907 * Handles writes to IQT_REG.
1908 *
1909 * @returns Strict VBox status code.
1910 * @param pDevIns The IOMMU device instance.
1911 * @param offReg The MMIO register offset.
1912 * @param uIqtReg The value written to IQT_REG.
1913 */
1914static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1915{
1916 /* We only care about the low 32-bits, high 32-bits are reserved. */
1917 Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1918 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1919
1920 /* Paranoia. */
1921 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1922
1923 uint32_t const offQt = uIqtReg;
1924 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1925 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1926
1927 /* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1928 if ( fDw != VTD_IQA_REG_DW_256_BIT
1929 || !(offQt & RT_BIT(4)))
1930 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1931 else
1932 {
1933 /* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1934 dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1935 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1936 }
1937 return VINF_SUCCESS;
1938}
1939
1940
1941/**
1942 * Handles writes to IQA_REG.
1943 *
1944 * @returns Strict VBox status code.
1945 * @param pDevIns The IOMMU device instance.
1946 * @param offReg The MMIO register offset.
1947 * @param uIqaReg The value written to IQA_REG.
1948 */
1949static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1950{
1951 /* At present, we only care about the low 32-bits, high 32-bits are data. */
1952 Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1953
1954 /** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1955 * returns true? The Intel VT-d spec. doesn't state anywhere that it
1956 * cannot happen or that it's ignored when it does happen. */
1957
1958 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1959 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1960 if (fDw == VTD_IQA_REG_DW_256_BIT)
1961 {
1962 bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK | VTD_BF_ECAP_REG_ADMS_MASK));
1963 if (fSupports256BitDw)
1964 { /* likely */ }
1965 else
1966 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1967 }
1968 /* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1969
1970 return VINF_SUCCESS;
1971}
1972
1973
1974/**
1975 * Handles writes to ICS_REG.
1976 *
1977 * @returns Strict VBox status code.
1978 * @param pDevIns The IOMMU device instance.
1979 * @param uIcsReg The value written to ICS_REG.
1980 */
1981static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1982{
1983 /*
1984 * If the IP field is set when software services the interrupt condition,
1985 * (by clearing the IWC field), the IP field must be cleared.
1986 */
1987 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1988 {
1989 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1990 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1991 }
1992 return VINF_SUCCESS;
1993}
1994
1995
1996/**
1997 * Handles writes to IECTL_REG.
1998 *
1999 * @returns Strict VBox status code.
2000 * @param pDevIns The IOMMU device instance.
2001 * @param uIectlReg The value written to IECTL_REG.
2002 */
2003static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
2004{
2005 /*
2006 * If software unmasks the interrupt when the interrupt is pending, we must raise
2007 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
2008 */
2009 if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
2010 && ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
2011 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
2012 return VINF_SUCCESS;
2013}
2014
2015
2016/**
2017 * Handles writes to FRCD_REG (High 64-bits).
2018 *
2019 * @returns Strict VBox status code.
2020 * @param pDevIns The IOMMU device instance.
2021 * @param offReg The MMIO register offset.
2022 * @param cbReg The size of the MMIO access (in bytes).
2023 * @param uFrcdHiReg The value written to FRCD_REG.
2024 * @param uPrev The value in FRCD_REG prior to writing it.
2025 */
2026static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2027{
2028 /* We only care about responding to high 32-bits, low 32-bits are read-only. */
2029 if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2030 {
2031 /*
2032 * If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2033 * Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2034 * has only 1 FRCD register.
2035 *
2036 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2037 */
2038 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2039 uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2040 if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2041 {
2042 Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2043 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2044 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2045 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2046 }
2047 }
2048 return VINF_SUCCESS;
2049}
2050
2051
2052/**
2053 * Performs a PCI target abort for a DMA remapping (DR) operation.
2054 *
2055 * @param pDevIns The IOMMU device instance.
2056 */
2057static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2058{
2059 /** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2060 * as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2061 * who knows. */
2062 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2063 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2064 PDMPciDevSetStatus(pPciDev, u16Status);
2065}
2066
2067
2068/**
2069 * Checks whether the address width (AW) is supported by our hardware
2070 * implementation for legacy mode address translation.
2071 *
2072 * @returns @c true if it's supported, @c false otherwise.
2073 * @param pThis The shared DMAR device state.
2074 * @param pCtxEntry The context entry.
2075 * @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2076 */
2077static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2078{
2079 uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2080 uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2081 uint8_t const fAwMask = RT_BIT(fAw);
2082 uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2083 Assert(!(fSagaw & ~(RT_BIT(1) | RT_BIT(2) | RT_BIT(3))));
2084
2085 uint8_t const cPagingLevel = fAw + 2;
2086 if (pcPagingLevel)
2087 *pcPagingLevel = cPagingLevel;
2088
2089 /* With pass-through, the address width must be the largest AGAW supported by hardware. */
2090 if (fTt == VTD_TT_UNTRANSLATED_PT)
2091 {
2092 Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2093 return cPagingLevel == pThis->cMaxPagingLevel;
2094 }
2095
2096 /* The address width must be any of the ones supported by hardware. */
2097 if (fAw < 4)
2098 return (fSagaw & fAwMask) != 0;
2099
2100 return false;
2101}
2102
2103
2104/**
2105 * Reads a root entry from guest memory.
2106 *
2107 * @returns VBox status code.
2108 * @param pDevIns The IOMMU device instance.
2109 * @param uRtaddrReg The current RTADDR_REG value.
2110 * @param idxRootEntry The index of the root entry to read.
2111 * @param pRootEntry Where to store the read root entry.
2112 */
2113static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2114{
2115 size_t const cbRootEntry = sizeof(*pRootEntry);
2116 RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2117 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2118}
2119
2120
2121/**
2122 * Reads a context entry from guest memory.
2123 *
2124 * @returns VBox status code.
2125 * @param pDevIns The IOMMU device instance.
2126 * @param GCPhysCtxTable The physical address of the context table.
2127 * @param idxCtxEntry The index of the context entry to read.
2128 * @param pCtxEntry Where to store the read context entry.
2129 */
2130static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2131{
2132 /* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2133 size_t const cbCtxEntry = sizeof(*pCtxEntry);
2134 RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2135 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2136}
2137
2138
2139/**
2140 * Validates and updates the output I/O page of a translation.
2141 *
2142 * @returns VBox status code.
2143 * @param pDevIns The IOMMU device instance.
2144 * @param GCPhysBase The output address of the translation.
2145 * @param cShift The page shift of the translated address.
2146 * @param fPerm The permissions granted for the translated region.
2147 * @param pMemReqIn The DMA memory request input.
2148 * @param pMemReqAux The DMA memory request auxiliary info.
2149 * @param pIoPageOut Where to store the output of the translation.
2150 */
2151static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2152 PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2153{
2154 Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2155
2156 /* Ensure the output address is not in the interrupt address range. */
2157 if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2158 {
2159 pIoPageOut->GCPhysBase = GCPhysBase;
2160 pIoPageOut->cShift = cShift;
2161 pIoPageOut->fPerm = fPerm;
2162 return VINF_SUCCESS;
2163 }
2164
2165 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2166 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2167}
2168
2169
2170/**
2171 * Performs second level translation by walking the I/O page tables.
2172 *
2173 * This is a DMA address-lookup callback function which performs the translation
2174 * (and access control) as part of the lookup.
2175 *
2176 * @returns VBox status code.
2177 * @param pDevIns The IOMMU device instance.
2178 * @param pMemReqIn The DMA memory request input.
2179 * @param pMemReqAux The DMA memory request auxiliary info.
2180 * @param pIoPageOut Where to store the output of the translation.
2181 */
2182static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2183 PDMARIOPAGE pIoPageOut)
2184{
2185 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2186
2187 /* Sanity. */
2188 Assert(pIoPageOut);
2189 Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ | DMAR_PERM_WRITE));
2190 Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2191 || pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2192 Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2193
2194 /* Mask of reserved paging entry bits. */
2195 static uint64_t const s_auPtEntityInvMasks[] =
2196 {
2197 ~VTD_SL_PTE_VALID_MASK,
2198 ~VTD_SL_PDE_VALID_MASK,
2199 ~VTD_SL_PDPE_VALID_MASK,
2200 ~VTD_SL_PML4E_VALID_MASK,
2201 ~VTD_SL_PML5E_VALID_MASK
2202 };
2203
2204 /* Paranoia. */
2205 Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2206 AssertCompile(RT_ELEMENTS(s_auPtEntityInvMasks) == 5);
2207
2208 /* Second-level translations restricts input address to an implementation-specific MGAW. */
2209 uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2210 if (!(uAddrIn & pThis->fMgawInvMask))
2211 { /* likely */ }
2212 else
2213 {
2214 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2215 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2216 }
2217
2218 /*
2219 * Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2220 * Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2221 */
2222 if (pMemReqAux->cPagingLevel > 0)
2223 {
2224 uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2225 for (uint8_t idxLevel = pMemReqAux->cPagingLevel - 1; /* not needed: idxLevel >= 0 */; idxLevel--)
2226 {
2227 /*
2228 * Read the paging entry for the current level.
2229 */
2230 uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2231 {
2232 uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2233 uint16_t const offPte = idxPte << 3;
2234 RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) | offPte;
2235 int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2236 if (RT_SUCCESS(rc))
2237 { /* likely */ }
2238 else
2239 {
2240 if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2241 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2242 else
2243 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2244 break;
2245 }
2246 }
2247
2248 /*
2249 * Check I/O permissions.
2250 * This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2251 * See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2252 */
2253 uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2254 uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2255 Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2256 Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2257 if ((fPtPerm & fReqPerm) == fReqPerm)
2258 { /* likely */ }
2259 else
2260 {
2261 if ((fPtPerm & (VTD_BF_SL_PTE_R_MASK | VTD_BF_SL_PTE_W_MASK)) == 0)
2262 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Not_Present, pMemReqIn, pMemReqAux);
2263 else if ((pMemReqIn->AddrRange.fPerm & DMAR_PERM_READ) != (fPtPerm & VTD_BF_SL_PTE_R_MASK))
2264 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Read_Denied, pMemReqIn, pMemReqAux);
2265 else
2266 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Write_Denied, pMemReqIn, pMemReqAux);
2267 break;
2268 }
2269
2270 /*
2271 * Validate reserved bits of the current paging entry.
2272 */
2273 if (!(uPtEntity & s_auPtEntityInvMasks[(uintptr_t)idxLevel]))
2274 { /* likely */ }
2275 else
2276 {
2277 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2278 break;
2279 }
2280
2281 /*
2282 * Check if this is a 1GB page or a 2MB page.
2283 */
2284 AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2285 uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2286 if (fLargePage && idxLevel > 0)
2287 {
2288 Assert(idxLevel == 1 || idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2289 uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2290 if (fSllpsMask & RT_BIT(idxLevel - 1))
2291 {
2292 /*
2293 * We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2294 * All other reserved bits are identical to the regular page-size paging entity which we've already
2295 * checked above.
2296 */
2297 Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2298
2299 RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2300 return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2301 }
2302
2303 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2304 break;
2305 }
2306
2307 /*
2308 * If this is the final PTE, compute the translation address and we're done.
2309 */
2310 if (idxLevel == 0)
2311 {
2312 RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2313 return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2314 }
2315 }
2316 }
2317
2318 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2319}
2320
2321
2322/**
2323 * Looks up the range of addresses for a DMA memory request remapping.
2324 *
2325 * @returns VBox status code.
2326 * @param pDevIns The IOMMU device instance.
2327 * @param pfnLookup The DMA address lookup function.
2328 * @param pMemReqRemap The DMA memory request remapping info.
2329 */
2330static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2331{
2332 AssertPtr(pfnLookup);
2333
2334 RTGCPHYS GCPhysAddrOut = NIL_RTGCPHYS;
2335 DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2336 uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2337 size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2338 uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2339 uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2340 size_t cbRemaining = cbAddrIn;
2341 size_t const cbPage = X86_PAGE_4K_SIZE;
2342
2343 int rc;
2344 DMARIOPAGE IoPagePrev;
2345 RT_ZERO(IoPagePrev);
2346 for (;;)
2347 {
2348 /* Update the input memory request with the next address in our range that needs translation. */
2349 MemReqIn.AddrRange.uAddr = uAddrInBase;
2350 MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2351
2352 /* Lookup the physical page corresponding to the DMA virtual address. */
2353 DMARIOPAGE IoPage;
2354 rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2355 if (RT_SUCCESS(rc))
2356 {
2357 /* Validate results of the translation. */
2358 Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2359 Assert(!(IoPage.GCPhysBase & X86_GET_PAGE_OFFSET_MASK(IoPage.cShift)));
2360 Assert((IoPage.fPerm & MemReqIn.AddrRange.fPerm) == MemReqIn.AddrRange.fPerm);
2361
2362 /* Store the translated address and permissions before continuing to access more pages. */
2363 if (cbRemaining == cbAddrIn)
2364 {
2365 uint64_t const offAddrOut = uAddrIn & X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2366 GCPhysAddrOut = IoPage.GCPhysBase | offAddrOut;
2367 }
2368 /* Check if addresses translated so far result in a physically contiguous region. */
2369 /** @todo Ensure permissions are identical as well if we implementing IOTLB caching
2370 * that relies on it being so. */
2371 else if (IoPagePrev.GCPhysBase + cbPage == IoPage.GCPhysBase)
2372 { /* likely */ }
2373 else
2374 {
2375 rc = VERR_OUT_OF_RANGE;
2376 break;
2377 }
2378
2379 /* Store the I/O page lookup from the first/previous access. */
2380 IoPagePrev = IoPage;
2381
2382 /* Check if we need to access more pages. */
2383 if (cbRemaining > cbPage - offAddrIn)
2384 {
2385 cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2386 uAddrInBase += cbPage; /* Update address of the next access. */
2387 offAddrIn = 0; /* After the first page, remaining pages are accessed from offset 0. */
2388 }
2389 else
2390 {
2391 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
2392 cbRemaining = 0;
2393 break;
2394 }
2395 }
2396 else
2397 break;
2398 }
2399
2400 pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddrOut;
2401 pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2402 pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2403 return rc;
2404}
2405
2406
2407/**
2408 * Handles legacy mode DMA address remapping.
2409 *
2410 * @returns VBox status code.
2411 * @param pDevIns The IOMMU device instance.
2412 * @param uRtaddrReg The current RTADDR_REG value.
2413 * @param pMemReqRemap The DMA memory request remapping info.
2414 */
2415static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2416{
2417 PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2418 PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2419 PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2420 Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2421
2422 /* Read the root-entry from guest memory. */
2423 uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2424 VTD_ROOT_ENTRY_T RootEntry;
2425 int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2426 if (RT_SUCCESS(rc))
2427 {
2428 /* Check if the root entry is present (must be done before validating reserved bits). */
2429 uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2430 uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2431 bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2432 if (fRootEntryPresent)
2433 {
2434 /* Validate reserved bits in the root entry. */
2435 if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2436 && !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2437 {
2438 /* Read the context-entry from guest memory. */
2439 RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2440 uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2441 VTD_CONTEXT_ENTRY_T CtxEntry;
2442 rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2443 if (RT_SUCCESS(rc))
2444 {
2445 uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2446 uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2447
2448 /* Note the FPD bit which software can use to supress translation faults from here on in. */
2449 pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2450
2451 /* Check if the context-entry is present (must be done before validating reserved bits). */
2452 bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2453 if (fCtxEntryPresent)
2454 {
2455 /* Validate reserved bits in the context-entry. */
2456 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2457 if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2458 && !(uCtxEntryQword1 & ~pThis->fCtxEntryQw1ValidMask))
2459 {
2460 /* Get the domain ID for this mapping. */
2461 pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2462
2463 /* Validate the translation type (TT). */
2464 uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2465 switch (fTt)
2466 {
2467 case VTD_TT_UNTRANSLATED_SLP:
2468 {
2469 /*
2470 * Untranslated requests are translated using second-level paging structures referenced
2471 * through SLPTPTR. Translated requests and Translation Requests are blocked.
2472 */
2473 if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2474 {
2475 /* Validate the address width and get the paging level. */
2476 uint8_t cPagingLevel;
2477 if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2478 {
2479 /*
2480 * The second-level page table is located at the physical address specified
2481 * in the context entry with which we can finally perform second-level translation.
2482 */
2483 pMemReqAux->cPagingLevel = cPagingLevel;
2484 pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2485 rc = dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2486 if (rc == VERR_OUT_OF_RANGE)
2487 rc = VINF_SUCCESS;
2488 return rc;
2489 }
2490 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2491 }
2492 else
2493 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2494 break;
2495 }
2496
2497 case VTD_TT_UNTRANSLATED_PT:
2498 {
2499 /*
2500 * Untranslated requests are processed as pass-through (PT) if PT is supported.
2501 * Translated and translation requests are blocked. If PT isn't supported this TT value
2502 * is reserved which I assume raises a fault (hence fallthru below).
2503 */
2504 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2505 {
2506 if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2507 {
2508 if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2509 {
2510 PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2511 PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2512 pOut->AddrRange.uAddr = pIn->AddrRange.uAddr;
2513 pOut->AddrRange.cb = pIn->AddrRange.cb;
2514 pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2515 return VINF_SUCCESS;
2516 }
2517 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2518 }
2519 else
2520 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2521 break;
2522 }
2523 RT_FALL_THRU();
2524 }
2525
2526 case VTD_TT_UNTRANSLATED_DEV_TLB:
2527 {
2528 /*
2529 * Untranslated, translated and translation requests are supported but requires
2530 * device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2531 */
2532 Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2533 RT_FALL_THRU();
2534 }
2535
2536 default:
2537 {
2538 /* Any other TT value is reserved. */
2539 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2540 break;
2541 }
2542 }
2543 }
2544 else
2545 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2546 }
2547 else
2548 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2549 }
2550 else
2551 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2552 }
2553 else
2554 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2555 }
2556 else
2557 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2558 }
2559 else
2560 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2561 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2562}
2563
2564
2565/**
2566 * Handles remapping of DMA address requests in scalable mode.
2567 *
2568 * @returns VBox status code.
2569 * @param pDevIns The IOMMU device instance.
2570 * @param uRtaddrReg The current RTADDR_REG value.
2571 * @param pMemReqRemap The DMA memory request remapping info.
2572 */
2573static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2574{
2575 RT_NOREF3(pDevIns, uRtaddrReg, pMemReqRemap);
2576 return VERR_NOT_IMPLEMENTED;
2577}
2578
2579
2580/**
2581 * Gets the DMA access permissions and the address-translation request
2582 * type given the PDM IOMMU memory access flags.
2583 *
2584 * @param pDevIns The IOMMU device instance.
2585 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2586 * @param fBulk Whether this is a bulk memory access (used for
2587 * statistics).
2588 * @param penmReqType Where to store the address-translation request type.
2589 * @param pfReqPerm Where to store the DMA access permissions.
2590 */
2591static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2592{
2593 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2594 if (fFlags & PDMIOMMU_MEM_F_READ)
2595 {
2596 *penmReqType = VTDREQTYPE_READ;
2597 *pfReqPerm = DMAR_PERM_READ;
2598#ifdef VBOX_WITH_STATISTICS
2599 if (!fBulk)
2600 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2601 else
2602 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2603#else
2604 RT_NOREF2(pThis, fBulk);
2605#endif
2606 }
2607 else
2608 {
2609 *penmReqType = VTDREQTYPE_WRITE;
2610 *pfReqPerm = DMAR_PERM_WRITE;
2611#ifdef VBOX_WITH_STATISTICS
2612 if (!fBulk)
2613 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2614 else
2615 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2616#else
2617 RT_NOREF2(pThis, fBulk);
2618#endif
2619 }
2620}
2621
2622
2623/**
2624 * Handles DMA remapping based on the table translation mode (TTM).
2625 *
2626 * @returns VBox status code.
2627 * @param pDevIns The IOMMU device instance.
2628 * @param uRtaddrReg The current RTADDR_REG value.
2629 * @param pMemReqRemap The DMA memory request remapping info.
2630 */
2631static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2632{
2633 int rc;
2634 switch (pMemReqRemap->Aux.fTtm)
2635 {
2636 case VTD_TTM_LEGACY_MODE:
2637 {
2638 rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2639 break;
2640 }
2641
2642 case VTD_TTM_SCALABLE_MODE:
2643 {
2644 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2645 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2646 rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2647 else
2648 {
2649 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2650 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2651 }
2652 break;
2653 }
2654
2655 case VTD_TTM_ABORT_DMA_MODE:
2656 {
2657 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2658 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2659 dmarDrTargetAbort(pDevIns);
2660 else
2661 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2662 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2663 break;
2664 }
2665
2666 default:
2667 {
2668 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2669 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2670 break;
2671 }
2672 }
2673 return rc;
2674}
2675
2676
2677/**
2678 * Memory access bulk (one or more 4K pages) request from a device.
2679 *
2680 * @returns VBox status code.
2681 * @param pDevIns The IOMMU device instance.
2682 * @param idDevice The device ID (bus, device, function).
2683 * @param cIovas The number of addresses being accessed.
2684 * @param pauIovas The I/O virtual addresses for each page being accessed.
2685 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2686 * @param paGCPhysSpa Where to store the translated physical addresses.
2687 *
2688 * @thread Any.
2689 */
2690static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2691 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2692{
2693 /* Validate. */
2694 AssertPtr(pDevIns);
2695 Assert(cIovas > 0);
2696 AssertPtr(pauIovas);
2697 AssertPtr(paGCPhysSpa);
2698 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2699
2700 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2701 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2702
2703 DMAR_LOCK(pDevIns, pThisCC);
2704 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2705 uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2706 DMAR_UNLOCK(pDevIns, pThisCC);
2707
2708 if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2709 {
2710 VTDREQTYPE enmReqType;
2711 uint8_t fReqPerm;
2712 dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2713
2714 DMARMEMREQREMAP MemReqRemap;
2715 RT_ZERO(MemReqRemap);
2716 MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2717 MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2718 MemReqRemap.In.idDevice = idDevice;
2719 MemReqRemap.In.Pasid = NIL_PCIPASID;
2720 MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2721 MemReqRemap.In.enmReqType = enmReqType;
2722 MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2723 MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2724
2725 for (size_t i = 0; i < cIovas; i++)
2726 {
2727 MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2728 int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2729 if (RT_SUCCESS(rc))
2730 {
2731 paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr | (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2732 Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2733 }
2734 else
2735 {
2736 LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2737 return rc;
2738 }
2739 }
2740 }
2741 else
2742 {
2743 /* Addresses are forwarded without translation when the translation is disabled. */
2744 for (size_t i = 0; i < cIovas; i++)
2745 paGCPhysSpa[i] = pauIovas[i];
2746 }
2747
2748 return VINF_SUCCESS;
2749}
2750
2751
2752/**
2753 * Memory access transaction from a device.
2754 *
2755 * @returns VBox status code.
2756 * @param pDevIns The IOMMU device instance.
2757 * @param idDevice The device ID (bus, device, function).
2758 * @param uIova The I/O virtual address being accessed.
2759 * @param cbIova The size of the access.
2760 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2761 * @param pGCPhysSpa Where to store the translated system physical address.
2762 * @param pcbContiguous Where to store the number of contiguous bytes translated
2763 * and permission-checked.
2764 *
2765 * @thread Any.
2766 */
2767static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2768 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2769{
2770 /* Validate. */
2771 AssertPtr(pDevIns);
2772 AssertPtr(pGCPhysSpa);
2773 AssertPtr(pcbContiguous);
2774 Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2775 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2776
2777 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2778 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2779
2780 DMAR_LOCK(pDevIns, pThisCC);
2781 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2782 uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2783 DMAR_UNLOCK(pDevIns, pThisCC);
2784
2785 if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2786 {
2787 VTDREQTYPE enmReqType;
2788 uint8_t fReqPerm;
2789 dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2790
2791 DMARMEMREQREMAP MemReqRemap;
2792 RT_ZERO(MemReqRemap);
2793 MemReqRemap.In.AddrRange.uAddr = uIova;
2794 MemReqRemap.In.AddrRange.cb = cbIova;
2795 MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2796 MemReqRemap.In.idDevice = idDevice;
2797 MemReqRemap.In.Pasid = NIL_PCIPASID;
2798 MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2799 MemReqRemap.In.enmReqType = enmReqType;
2800 MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2801 MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2802
2803 int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2804 *pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2805 *pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2806 return rc;
2807 }
2808
2809 *pGCPhysSpa = uIova;
2810 *pcbContiguous = cbIova;
2811 return VINF_SUCCESS;
2812}
2813
2814
2815/**
2816 * Reads an IRTE from guest memory.
2817 *
2818 * @returns VBox status code.
2819 * @param pDevIns The IOMMU device instance.
2820 * @param uIrtaReg The IRTA_REG.
2821 * @param idxIntr The interrupt index.
2822 * @param pIrte Where to store the read IRTE.
2823 */
2824static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2825{
2826 Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2827
2828 size_t const cbIrte = sizeof(*pIrte);
2829 RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2830 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2831}
2832
2833
2834/**
2835 * Remaps the source MSI to the destination MSI given the IRTE.
2836 *
2837 * @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2838 * IRTA_REG.EIME).
2839 * @param pIrte The IRTE used for the remapping.
2840 * @param pMsiIn The source MSI (currently unused).
2841 * @param pMsiOut Where to store the remapped MSI.
2842 */
2843static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2844{
2845 NOREF(pMsiIn);
2846 uint64_t const uIrteQword0 = pIrte->au64[0];
2847
2848 /*
2849 * Let's start with a clean slate and preserve unspecified bits if the need arises.
2850 * For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2851 * but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2852 * it copies it from the source MSI.
2853 */
2854 RT_ZERO(*pMsiOut);
2855 pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2856 pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2857 pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2858 if (fExtIntrMode)
2859 {
2860 /*
2861 * Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2862 * high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2863 */
2864 uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2865 pMsiOut->Addr.n.u8DestId = idDest;
2866 pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2867 }
2868 else
2869 pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2870
2871 pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2872 pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2873 pMsiOut->Data.n.u1Level = 1;
2874 pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2875}
2876
2877
2878/**
2879 * Handles remapping of interrupts in remappable interrupt format.
2880 *
2881 * @returns VBox status code.
2882 * @param pDevIns The IOMMU device instance.
2883 * @param uIrtaReg The IRTA_REG.
2884 * @param idDevice The device ID (bus, device, function).
2885 * @param pMsiIn The source MSI.
2886 * @param pMsiOut Where to store the remapped MSI.
2887 */
2888static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2889{
2890 Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2891
2892 /* Validate reserved bits in the interrupt request. */
2893 AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2894 if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2895 {
2896 /* Compute the index into the interrupt remap table. */
2897 uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2898 uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2899 uint16_t const uHandle = uHandleLo | (uHandleHi << 15);
2900 bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2901 uint16_t const idxIntr = fSubHandleValid
2902 ? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2903 : uHandle;
2904
2905 /* Validate the index. */
2906 uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2907 if (idxIntr < cEntries)
2908 {
2909 /** @todo Implement and read IRTE from interrupt-entry cache here. */
2910
2911 /* Read the interrupt remap table entry (IRTE) at the index. */
2912 VTD_IRTE_T Irte;
2913 int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2914 if (RT_SUCCESS(rc))
2915 {
2916 /* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2917 uint64_t const uIrteQword0 = Irte.au64[0];
2918 uint64_t const uIrteQword1 = Irte.au64[1];
2919 bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2920 if (fPresent)
2921 {
2922 /* Validate reserved bits in the IRTE. */
2923 bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2924 uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2925 if ( !(uIrteQword0 & ~fQw0ValidMask)
2926 && !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2927 {
2928 /* Validate requester id (the device ID) as configured in the IRTE. */
2929 bool fSrcValid;
2930 DMARDIAG enmIrDiag;
2931 uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2932 switch (fSvt)
2933 {
2934 case VTD_IRTE_SVT_NONE:
2935 {
2936 fSrcValid = true;
2937 enmIrDiag = kDmarDiag_None;
2938 break;
2939 }
2940
2941 case VTD_IRTE_SVT_VALIDATE_MASK:
2942 {
2943 static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2944 uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2945 uint16_t const fValidMask = s_afValidMasks[idxMask];
2946 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2947 fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2948 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2949 break;
2950 }
2951
2952 case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2953 {
2954 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2955 uint8_t const uBusFirst = RT_HI_U8(idSource);
2956 uint8_t const uBusLast = RT_LO_U8(idSource);
2957 uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2958 fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2959 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2960 break;
2961 }
2962
2963 default:
2964 {
2965 fSrcValid = false;
2966 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2967 break;
2968 }
2969 }
2970
2971 if (fSrcValid)
2972 {
2973 uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2974 if (!fPostedMode)
2975 {
2976 dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2977 return VINF_SUCCESS;
2978 }
2979 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2980 }
2981 else
2982 dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2983 }
2984 else
2985 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2986 }
2987 else
2988 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2989 }
2990 else
2991 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2992 }
2993 else
2994 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2995 }
2996 else
2997 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr */, NULL /* pIrte */);
2998 return VERR_IOMMU_INTR_REMAP_DENIED;
2999}
3000
3001
3002/**
3003 * Interrupt remap request from a device.
3004 *
3005 * @returns VBox status code.
3006 * @param pDevIns The IOMMU device instance.
3007 * @param idDevice The device ID (bus, device, function).
3008 * @param pMsiIn The source MSI.
3009 * @param pMsiOut Where to store the remapped MSI.
3010 */
3011static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3012{
3013 /* Validate. */
3014 Assert(pDevIns);
3015 Assert(pMsiIn);
3016 Assert(pMsiOut);
3017 RT_NOREF1(idDevice);
3018
3019 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3020 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3021
3022 /* Lock and read all registers required for interrupt remapping up-front. */
3023 DMAR_LOCK(pDevIns, pThisCC);
3024 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3025 uint64_t const uIrtaReg = pThis->uIrtaReg;
3026 DMAR_UNLOCK(pDevIns, pThisCC);
3027
3028 /* Check if interrupt remapping is enabled. */
3029 if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3030 {
3031 bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3032 if (!fIsRemappable)
3033 {
3034 /* Handle compatibility format interrupts. */
3035 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3036
3037 /* If EIME is enabled or CFIs are disabled, block the interrupt. */
3038 if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3039 || !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3040 {
3041 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3042 return VERR_IOMMU_INTR_REMAP_DENIED;
3043 }
3044
3045 /* Interrupt isn't subject to remapping, pass-through the interrupt. */
3046 *pMsiOut = *pMsiIn;
3047 return VINF_SUCCESS;
3048 }
3049
3050 /* Handle remappable format interrupts. */
3051 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3052 return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3053 }
3054
3055 /* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3056 *pMsiOut = *pMsiIn;
3057 return VINF_SUCCESS;
3058}
3059
3060
3061/**
3062 * @callback_method_impl{FNIOMMMIONEWWRITE}
3063 */
3064static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3065{
3066 RT_NOREF1(pvUser);
3067 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3068
3069 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3070 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3071
3072 uint16_t const offReg = off;
3073 uint16_t const offLast = offReg + cb - 1;
3074 if (DMAR_IS_MMIO_OFF_VALID(offLast))
3075 {
3076 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3077 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3078
3079 uint64_t uPrev = 0;
3080 uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv, &uPrev)
3081 : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv, (uint32_t *)&uPrev);
3082 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3083 switch (off)
3084 {
3085 case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3086 {
3087 rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3088 break;
3089 }
3090
3091 case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3092 case VTD_MMIO_OFF_CCMD_REG + 4:
3093 {
3094 rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3095 break;
3096 }
3097
3098 case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3099 {
3100 rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3101 break;
3102 }
3103
3104 case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3105 {
3106 rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3107 break;
3108 }
3109
3110 case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3111 /* VTD_MMIO_OFF_IQT_REG + 4: */ /* High 32-bits reserved. */
3112 {
3113 rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3114 break;
3115 }
3116
3117 case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3118 /* VTD_MMIO_OFF_IQA_REG + 4: */ /* High 32-bits data. */
3119 {
3120 rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3121 break;
3122 }
3123
3124 case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3125 {
3126 rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3127 break;
3128 }
3129
3130 case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3131 {
3132 rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3133 break;
3134 }
3135
3136 case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3137 case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3138 {
3139 rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3140 break;
3141 }
3142 }
3143
3144 DMAR_UNLOCK(pDevIns, pThisCC);
3145 LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3146 return rcStrict;
3147 }
3148
3149 return VINF_IOM_MMIO_UNUSED_FF;
3150}
3151
3152
3153/**
3154 * @callback_method_impl{FNIOMMMIONEWREAD}
3155 */
3156static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3157{
3158 RT_NOREF1(pvUser);
3159 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3160
3161 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3162 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3163
3164 uint16_t const offReg = off;
3165 uint16_t const offLast = offReg + cb - 1;
3166 if (DMAR_IS_MMIO_OFF_VALID(offLast))
3167 {
3168 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3169 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3170
3171 if (cb == 8)
3172 {
3173 *(uint64_t *)pv = dmarRegRead64(pThis, offReg);
3174 LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, *(uint64_t *)pv));
3175 }
3176 else
3177 {
3178 *(uint32_t *)pv = dmarRegRead32(pThis, offReg);
3179 LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, *(uint32_t *)pv));
3180 }
3181
3182 DMAR_UNLOCK(pDevIns, pThisCC);
3183 return VINF_SUCCESS;
3184 }
3185
3186 return VINF_IOM_MMIO_UNUSED_FF;
3187}
3188
3189
3190#ifdef IN_RING3
3191/**
3192 * Process requests in the invalidation queue.
3193 *
3194 * @param pDevIns The IOMMU device instance.
3195 * @param pvRequests The requests to process.
3196 * @param cbRequests The size of all requests (in bytes).
3197 * @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3198 * VTD_IQA_REG_DW_256_BIT).
3199 * @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3200 */
3201static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3202 uint8_t fTtm)
3203{
3204#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3205 do \
3206 { \
3207 dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3208 return; \
3209 } while (0)
3210
3211 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3212 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3213
3214 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3215 Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3216
3217 /*
3218 * The below check is redundant since we check both TTM and DW for each
3219 * descriptor type we process. However, the order of errors reported by hardware
3220 * may differ hence this is kept commented out but not removed if we need to
3221 * change this in the future.
3222 *
3223 * In our implementation, we would report the descriptor type as invalid,
3224 * while on real hardware it may report descriptor width as invalid.
3225 * The Intel VT-d spec. is not clear which error takes preceedence.
3226 */
3227#if 0
3228 /*
3229 * Verify that 128-bit descriptors are not used when operating in scalable mode.
3230 * We don't check this while software writes IQA_REG but defer it until now because
3231 * RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3232 * -IS- performed when software writes IQA_REG since it only requires checking against
3233 * immutable hardware features.
3234 */
3235 if ( fTtm != VTD_TTM_SCALABLE_MODE
3236 || fDw != VTD_IQA_REG_DW_128_BIT)
3237 { /* likely */ }
3238 else
3239 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3240#endif
3241
3242 /*
3243 * Process requests in FIFO order.
3244 */
3245 uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3246 for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3247 {
3248 uint64_t const *puDscQwords = (uint64_t const *)((uintptr_t)pvRequests + offDsc);
3249 uint64_t const uQword0 = puDscQwords[0];
3250 uint64_t const uQword1 = puDscQwords[1];
3251 uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3252 switch (fDscType)
3253 {
3254 case VTD_INV_WAIT_DSC_TYPE:
3255 {
3256 /* Validate descriptor type. */
3257 if ( fTtm == VTD_TTM_LEGACY_MODE
3258 || fDw == VTD_IQA_REG_DW_256_BIT)
3259 { /* likely */ }
3260 else
3261 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3262
3263 /* Validate reserved bits. */
3264 uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3265 ? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3266 : VTD_INV_WAIT_DSC_0_VALID_MASK;
3267 if ( !(uQword0 & ~fValidMask0)
3268 && !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3269 { /* likely */ }
3270 else
3271 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3272
3273 if (fDw == VTD_IQA_REG_DW_256_BIT)
3274 {
3275 if ( !puDscQwords[2]
3276 && !puDscQwords[3])
3277 { /* likely */ }
3278 else
3279 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3280 }
3281
3282 /* Perform status write (this must be done prior to generating the completion interrupt). */
3283 bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3284 if (fSw)
3285 {
3286 uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3287 RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3288 int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3289 AssertRC(rc);
3290 }
3291
3292 /* Generate invalidation event interrupt. */
3293 bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3294 if (fIf)
3295 {
3296 DMAR_LOCK(pDevIns, pThisR3);
3297 dmarR3InvEventRaiseInterrupt(pDevIns);
3298 DMAR_UNLOCK(pDevIns, pThisR3);
3299 }
3300
3301 STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3302 break;
3303 }
3304
3305 case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3306 case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3307 case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3308 case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3309 case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3310 case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3311 case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3312 default:
3313 {
3314 /* Stop processing further requests. */
3315 LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3316 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3317 }
3318 }
3319 }
3320#undef DMAR_IQE_FAULT_RECORD_RET
3321}
3322
3323
3324/**
3325 * The invalidation-queue thread.
3326 *
3327 * @returns VBox status code.
3328 * @param pDevIns The IOMMU device instance.
3329 * @param pThread The command thread.
3330 */
3331static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3332{
3333 NOREF(pThread);
3334 LogFlowFunc(("\n"));
3335
3336 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3337 return VINF_SUCCESS;
3338
3339 /*
3340 * Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3341 * This prevents trashing the heap as well as deal with out-of-memory situations
3342 * up-front while starting the VM. It also simplifies the code from having to
3343 * dynamically grow/shrink the allocation based on how software sizes the queue.
3344 * Guests normally don't alter the queue size all the time, but that's not an
3345 * assumption we can make.
3346 */
3347 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3348 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3349 void *pvRequests = RTMemAllocZ(cbMaxQs);
3350 AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3351
3352 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3353 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3354
3355 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3356 {
3357 /*
3358 * Sleep until we are woken up.
3359 */
3360 {
3361 int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3362 AssertLogRelMsgReturnStmt(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), RTMemFree(pvRequests), rc);
3363 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3364 break;
3365 }
3366
3367 DMAR_LOCK(pDevIns, pThisR3);
3368 if (dmarInvQueueCanProcessRequests(pThis))
3369 {
3370 uint32_t offQueueHead;
3371 uint32_t offQueueTail;
3372 bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3373 if (!fIsEmpty)
3374 {
3375 /*
3376 * Get the current queue size, descriptor width, queue base address and the
3377 * table translation mode while the lock is still held.
3378 */
3379 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3380 uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3381 uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3382 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3383 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3384 RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3385
3386 /* Paranoia. */
3387 Assert(cbQueue <= cbMaxQs);
3388 Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3389 Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3390 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4)));
3391 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4)));
3392 Assert(offQueueHead < cbQueue);
3393
3394 /*
3395 * A table translation mode of "reserved" isn't valid for any descriptor type.
3396 * However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3397 * but if ESRTPS is support, we will perform a global invalidation when software
3398 * changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3399 * So caching TTM while reading all descriptors should not be a problem.
3400 *
3401 * Also, validate the queue tail offset as it's mutable by software.
3402 */
3403 if ( fTtm != VTD_TTM_RSVD
3404 && offQueueTail < cbQueue)
3405 {
3406 /* Don't hold the lock while reading (a potentially large amount of) requests */
3407 DMAR_UNLOCK(pDevIns, pThisR3);
3408
3409 int rc;
3410 uint32_t cbRequests;
3411 if (offQueueTail > offQueueHead)
3412 {
3413 /* The requests have not wrapped around, read them in one go. */
3414 cbRequests = offQueueTail - offQueueHead;
3415 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3416 }
3417 else
3418 {
3419 /* The requests have wrapped around, read forward and wrapped-around. */
3420 uint32_t const cbForward = cbQueue - offQueueHead;
3421 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3422
3423 uint32_t const cbWrapped = offQueueTail;
3424 if ( RT_SUCCESS(rc)
3425 && cbWrapped > 0)
3426 {
3427 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3428 (void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3429 }
3430 cbRequests = cbForward + cbWrapped;
3431 }
3432
3433 /* Re-acquire the lock since we need to update device state. */
3434 DMAR_LOCK(pDevIns, pThisR3);
3435
3436 if (RT_SUCCESS(rc))
3437 {
3438 /* Indicate to software we've fetched all requests. */
3439 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3440
3441 /* Don't hold the lock while processing requests. */
3442 DMAR_UNLOCK(pDevIns, pThisR3);
3443
3444 /* Process all requests. */
3445 Assert(cbRequests <= cbQueue);
3446 dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3447
3448 /*
3449 * We've processed all requests and the lock shouldn't be held at this point.
3450 * Using 'continue' here allows us to skip re-acquiring the lock just to release
3451 * it again before going back to the thread loop. It's a bit ugly but it certainly
3452 * helps with performance.
3453 */
3454 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3455 continue;
3456 }
3457 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3458 }
3459 else
3460 {
3461 if (fTtm == VTD_TTM_RSVD)
3462 dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3463 else
3464 {
3465 Assert(offQueueTail >= cbQueue);
3466 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3467 }
3468 }
3469 }
3470 }
3471 DMAR_UNLOCK(pDevIns, pThisR3);
3472 }
3473
3474 RTMemFree(pvRequests);
3475 pvRequests = NULL;
3476
3477 LogFlowFunc(("Invalidation-queue thread terminating\n"));
3478 return VINF_SUCCESS;
3479}
3480
3481
3482/**
3483 * Wakes up the invalidation-queue thread so it can respond to a state
3484 * change.
3485 *
3486 * @returns VBox status code.
3487 * @param pDevIns The IOMMU device instance.
3488 * @param pThread The invalidation-queue thread.
3489 *
3490 * @thread EMT.
3491 */
3492static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3493{
3494 RT_NOREF(pThread);
3495 LogFlowFunc(("\n"));
3496 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3497 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3498}
3499
3500
3501/**
3502 * @callback_method_impl{FNDBGFHANDLERDEV}
3503 */
3504static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3505{
3506 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3507 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3508 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3509
3510 /*
3511 * We lock the device to get a consistent register state as it is
3512 * ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3513 * ones we care about here) into temporaries and release the lock ASAP.
3514 *
3515 * Order of register being read and outputted is in accordance with the
3516 * spec. for no particular reason.
3517 * See Intel VT-d spec. 10.4 "Register Descriptions".
3518 */
3519 DMAR_LOCK(pDevIns, pThisR3);
3520
3521 DMARDIAG const enmDiag = pThis->enmDiag;
3522 uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3523 uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3524 uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3525 uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3526 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3527 uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3528 uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3529 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3530 uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3531 uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3532 uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3533 uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3534 uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3535 uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3536 uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3537 uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3538 uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3539 uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3540 uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3541 uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3542 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3543 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3544 uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3545 uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3546 uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3547 uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3548 uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3549 uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3550 uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3551 uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3552 uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3553 uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3554 uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3555 uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3556 uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3557 uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3558 uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3559 uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3560
3561 DMAR_UNLOCK(pDevIns, pThisR3);
3562
3563 const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3564 pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3565 pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3566
3567 /*
3568 * Non-verbose output.
3569 */
3570 if (!fVerbose)
3571 {
3572 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3573 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3574 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3575 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3576 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3577 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3578 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3579 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3580 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3581 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3582 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3583 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3584 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3585 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3586 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3587 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3588 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3589 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3590 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3591 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3592 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3593 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3594 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3595 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3596 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3597 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3598 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3599 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3600 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3601 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3602 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3603 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3604 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3605 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3606 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3607 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3608 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3609 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3610 pHlp->pfnPrintf(pHlp, "\n");
3611 return;
3612 }
3613
3614 /*
3615 * Verbose output.
3616 */
3617 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3618 {
3619 pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3620 pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3621 }
3622 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3623 {
3624 uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3625 uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3626 pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3627 pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3628 pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3629 pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3630 pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3631 pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3632 pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3633 pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3634 pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3635 pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3636 pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3637 pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3638 pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3639 pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3640 pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3641 pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3642 pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3643 pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3644 pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3645 pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3646 pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3647 }
3648 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3649 {
3650 uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3651 pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3652 pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3653 pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3654 pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3655 pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3656 pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3657 pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3658 pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3659 pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3660 pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3661 pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3662 pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3663 pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3664 pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3665 pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3666 pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3667 pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3668 pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3669 pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3670 pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3671 pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3672 pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3673 pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3674 pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3675 pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3676 pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3677 pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3678 pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3679 pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3680 }
3681 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3682 {
3683 uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3684 pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3685 pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3686 pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3687 pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3688 pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3689 pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3690 pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3691 pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3692 pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3693 }
3694 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3695 {
3696 uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3697 pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3698 pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3699 pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3700 pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3701 pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3702 pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3703 pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3704 pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3705 pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3706 }
3707 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3708 {
3709 uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3710 pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3711 pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3712 }
3713 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3714 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3715 {
3716 pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3717 pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3718 pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3719 pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3720 pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3721 pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3722 pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3723 pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3724 }
3725 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3726 {
3727 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3728 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3729 }
3730 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3731 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3732 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3733 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3734 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3735 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3736 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3737 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3738 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3739 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3740 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3741 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3742 {
3743 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3744 uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3745 uint8_t const cQueuePages = 1 << fQs;
3746 pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3747 pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3748 }
3749 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3750 {
3751 pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3752 }
3753 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3754 {
3755 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3756 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3757 }
3758 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3759 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3760 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3761 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3762 {
3763 pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3764 pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3765 pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3766 }
3767 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3768 {
3769 uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3770 uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3771 pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3772 pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3773 pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3774 }
3775 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3776 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3777 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3778 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3779 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3780 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3781 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3782 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3783 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3784 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3785 pHlp->pfnPrintf(pHlp, "\n");
3786}
3787
3788
3789/**
3790 * Initializes all registers in the DMAR unit.
3791 *
3792 * @param pDevIns The IOMMU device instance.
3793 */
3794static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3795{
3796 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3797 LogFlowFunc(("\n"));
3798
3799 /*
3800 * Wipe all registers (required on reset).
3801 */
3802 RT_ZERO(pThis->abRegs0);
3803 RT_ZERO(pThis->abRegs1);
3804
3805 /*
3806 * Initialize registers not mutable by software prior to initializing other registers.
3807 */
3808 /* VER_REG */
3809 {
3810 pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3811 | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3812 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3813 }
3814
3815 uint8_t const fFlts = 0; /* First-level translation support. */
3816 uint8_t const fSlts = 1; /* Second-level translation support. */
3817 uint8_t const fPt = 1; /* Pass-Through support. */
3818 uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3819 uint8_t const fNest = 0; /* Nested translation support. */
3820
3821 /* CAP_REG */
3822 {
3823 uint8_t cGstPhysAddrBits;
3824 uint8_t cGstLinearAddrBits;
3825 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3826
3827 uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3828 uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3829 uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3830 uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3831 uint8_t const fSllps = fSl2mp | (fSl2gp << 1); /* Second-level large page support. */
3832 uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3833 : X86_PAGE_2M_SHIFT)
3834 - X86_PAGE_4K_SHIFT;
3835 uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3836 uint8_t const fPsi = 1; /* Page selective invalidation. */
3837 uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3838 uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3839 uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3840 uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3841 uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3842
3843 pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3844 | RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3845 | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3846 | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3847 | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3848 | RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3849 | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3850 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3851 | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3852 | RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3853 | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3854 | RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3855 | RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3856 | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3857 | RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3858 | RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3859 | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3860 | RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3861 | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3862 | RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3863 | RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3864 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3865
3866 AssertCompile(fNd <= RT_ELEMENTS(g_auNdMask));
3867 pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3868 pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3869 pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3870 pThis->fCtxEntryQw1ValidMask = VTD_BF_1_CONTEXT_ENTRY_AW_MASK
3871 | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK
3872 | RT_BF_MAKE(VTD_BF_1_CONTEXT_ENTRY_DID, g_auNdMask[fNd]);
3873 }
3874
3875 /* ECAP_REG */
3876 {
3877 uint8_t const fQi = 1; /* Queued-invalidations. */
3878 uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3879 uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3880 uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3881 uint8_t const fEim = 1; /* Extended interrupt mode.*/
3882 uint8_t const fAdms = 1; /* Abort DMA mode support. */
3883 uint8_t const fErs = 0; /* Execute Request (not supported). */
3884
3885 pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3886 | RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3887 | RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3888 | RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3889 | RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3890 | RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3891 | RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3892 | RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3893 | RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3894 | RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3895 | RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3896 | RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3897 | RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3898 | RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3899 | RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3900 | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3901 | RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3902 | RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3903 | RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3904 | RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3905 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3906 | RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3907 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3908 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3909 | RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3910 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3911 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3912 | RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3913 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3914 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3915
3916 pThis->fPermValidMask = DMAR_PERM_READ | DMAR_PERM_WRITE;
3917 if (fErs)
3918 pThis->fPermValidMask = DMAR_PERM_EXE;
3919 }
3920
3921 /*
3922 * Initialize registers mutable by software.
3923 */
3924 /* FECTL_REG */
3925 {
3926 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3927 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3928 }
3929
3930 /* ICETL_REG */
3931 {
3932 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3933 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3934 }
3935
3936#ifdef VBOX_STRICT
3937 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3938 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3939#endif
3940}
3941
3942
3943/**
3944 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3945 */
3946static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3947{
3948 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3949 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3950 LogFlowFunc(("\n"));
3951
3952 /* First, save software-immutable registers that we validate on state load. */
3953 pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3954 pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3955 pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3956
3957 /* Save MMIO registers. */
3958 pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3959 pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3960 pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3961 pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3962 pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3963
3964 /*
3965 * Save our implemention-defined MMIO registers offsets.
3966 * The register themselves are currently all part of group 1 (saved above).
3967 * We save these to ensure they're located where the code expects them while loading state.
3968 */
3969 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT);
3970 AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 2);
3971 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG);
3972 pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG);
3973
3974 /* Save lazily activated registers. */
3975 pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3976 pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3977
3978 /* Save terminator marker and return status. */
3979 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3980}
3981
3982
3983/**
3984 * @callback_method_impl{FNSSMDEVLOADEXEC}
3985 */
3986static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3987{
3988 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3989 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3990 int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3991 int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3992 LogFlowFunc(("\n"));
3993
3994 /*
3995 * Validate saved-state version.
3996 */
3997 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3998 if (uVersion != DMAR_SAVED_STATE_VERSION)
3999 {
4000 LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
4001 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4002 }
4003
4004 /*
4005 * Load and validate software-immutable registers.
4006 * The features we had exposed to the guest (in the saved state) must be identical
4007 * to what is currently emulated.
4008 */
4009 {
4010 /* VER_REG */
4011 uint32_t uVerReg = 0;
4012 int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
4013 AssertRCReturn(rc, rc);
4014 AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
4015 ("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
4016 rcDataErr);
4017 /* CAP_REG */
4018 uint64_t fCapReg = 0;
4019 pHlp->pfnSSMGetU64(pSSM, &fCapReg);
4020 AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
4021 ("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
4022 rcDataErr);
4023 /* ECAP_REG */
4024 uint64_t fExtCapReg = 0;
4025 pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
4026 AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4027 ("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4028 fExtCapReg), rcDataErr);
4029 }
4030
4031 /*
4032 * Load MMIO registers.
4033 */
4034 {
4035 /* Group count. */
4036 uint32_t cRegGroups = 0;
4037 pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4038 AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4039 ("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4040 cRegGroups), rcFmtErr);
4041 /* Group 0. */
4042 uint32_t cbRegs0 = 0;
4043 pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4044 AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4045 ("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4046 cbRegs0), rcFmtErr);
4047 pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4048 /* Group 1. */
4049 uint32_t cbRegs1 = 0;
4050 pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4051 AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4052 ("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4053 cbRegs1), rcFmtErr);
4054 pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4055 }
4056
4057 /*
4058 * Validate implementation-defined MMIO register offsets.
4059 */
4060 {
4061 /* Offset count. */
4062 uint16_t cOffsets = 0;
4063 pHlp->pfnSSMGetU16(pSSM, &cOffsets);
4064 AssertLogRelMsgReturn(cOffsets == DMAR_MMIO_OFF_IMPL_COUNT,
4065 ("%s: MMIO offset count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IMPL_COUNT,
4066 cOffsets), rcFmtErr);
4067 /* IVA_REG. */
4068 uint16_t offReg = 0;
4069 pHlp->pfnSSMGetU16(pSSM, &offReg);
4070 AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IVA_REG,
4071 ("%s: IVA_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IVA_REG,
4072 offReg), rcFmtErr);
4073 /* IOTLB_REG. */
4074 AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_IOTLB_REG,
4075 ("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG,
4076 offReg), rcFmtErr);
4077 /* FRCD_LO_REG. */
4078 pHlp->pfnSSMGetU16(pSSM, &offReg);
4079 AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_LO_REG,
4080 ("%s: FRCD_LO_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_LO_REG,
4081 offReg), rcFmtErr);
4082 /* FRCD_HI_REG. */
4083 AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_FRCD_HI_REG,
4084 ("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG,
4085 offReg), rcFmtErr);
4086 }
4087
4088 /*
4089 * Load lazily activated registers.
4090 */
4091 {
4092 /* Active IRTA_REG. */
4093 pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4094 AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4095 ("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4096 /* Active RTADDR_REG. */
4097 pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4098 AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4099 ("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4100 }
4101
4102 /*
4103 * Verify terminator marker.
4104 */
4105 {
4106 uint32_t uEndMarker = 0;
4107 int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4108 AssertRCReturn(rc, rc);
4109 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4110 ("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4111 rcFmtErr);
4112 }
4113 return VINF_SUCCESS;
4114}
4115
4116
4117/**
4118 * @callback_method_impl{FNSSMDEVLOADDONE}
4119 */
4120static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4121{
4122 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4123 LogFlowFunc(("\n"));
4124 RT_NOREF(pSSM);
4125 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4126
4127 DMAR_LOCK(pDevIns, pThisR3);
4128 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4129 DMAR_UNLOCK(pDevIns, pThisR3);
4130 return VINF_SUCCESS;
4131}
4132
4133
4134/**
4135 * @interface_method_impl{PDMDEVREG,pfnReset}
4136 */
4137static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4138{
4139 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4140 LogFlowFunc(("\n"));
4141
4142 DMAR_LOCK(pDevIns, pThisR3);
4143 dmarR3RegsInit(pDevIns);
4144 DMAR_UNLOCK(pDevIns, pThisR3);
4145}
4146
4147
4148/**
4149 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4150 */
4151static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4152{
4153 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4154 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4155 LogFlowFunc(("\n"));
4156
4157 DMAR_LOCK(pDevIns, pThisR3);
4158
4159 if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4160 {
4161 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4162 pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4163 }
4164
4165 DMAR_UNLOCK(pDevIns, pThisR3);
4166 return VINF_SUCCESS;
4167}
4168
4169
4170/**
4171 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4172 */
4173static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4174{
4175 RT_NOREF(pCfg);
4176
4177 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4178 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4179 pThisR3->pDevInsR3 = pDevIns;
4180
4181 LogFlowFunc(("iInstance=%d\n", iInstance));
4182 NOREF(iInstance);
4183
4184 /*
4185 * Register the IOMMU with PDM.
4186 */
4187 PDMIOMMUREGR3 IommuReg;
4188 RT_ZERO(IommuReg);
4189 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4190 IommuReg.pfnMemAccess = iommuIntelMemAccess;
4191 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4192 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4193 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4194 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4195 if (RT_FAILURE(rc))
4196 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4197 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4198 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4199 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4200 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4201 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4202 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4203 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4204 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4205 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4206 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4207 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4208 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4209
4210 /*
4211 * Use PDM's critical section (via helpers) for the IOMMU device.
4212 */
4213 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4214 AssertRCReturn(rc, rc);
4215
4216 /*
4217 * Initialize PCI configuration registers.
4218 */
4219 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4220 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4221
4222 /* Header. */
4223 PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4224 PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4225 PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4226 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4227 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4228 PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4229 PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4230 PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4231
4232 /** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4233 PDMPciDevSetStatus(pPciDev, 0);
4234 PDMPciDevSetCapabilityList(pPciDev, 0);
4235 /** @todo VTBAR at 0x180? */
4236
4237 /*
4238 * Register the PCI function with PDM.
4239 */
4240 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4241 AssertLogRelRCReturn(rc, rc);
4242
4243 /*
4244 * Register MMIO region.
4245 */
4246 AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4247 rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4248 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4249 &pThis->hMmio);
4250 AssertLogRelRCReturn(rc, rc);
4251
4252 /*
4253 * Register saved state handlers.
4254 */
4255 rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4256 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
4257 NULL /* pfnSavePrep */, dmarR3SaveExec, NULL /* pfnSaveDone */,
4258 NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4259 AssertLogRelRCReturn(rc, rc);
4260
4261 /*
4262 * Register debugger info items.
4263 */
4264 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4265 AssertLogRelRCReturn(rc, rc);
4266
4267#ifdef VBOX_WITH_STATISTICS
4268 /*
4269 * Statistics.
4270 */
4271 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4272 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4273
4274 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4275 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4276
4277 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4278 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4279 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4280 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4281
4282 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4283 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4284
4285 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4286 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4287
4288 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4289 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4290
4291 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4292 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4293
4294 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4295 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4296 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4297 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4298 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4299 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4300 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4301 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4302#endif
4303
4304 /*
4305 * Initialize registers.
4306 */
4307 dmarR3RegsInit(pDevIns);
4308
4309 /*
4310 * Create invalidation-queue thread and semaphore.
4311 */
4312 char szInvQueueThread[32];
4313 RT_ZERO(szInvQueueThread);
4314 RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4315 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4316 0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4317 AssertLogRelRCReturn(rc, rc);
4318
4319 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4320 AssertLogRelRCReturn(rc, rc);
4321
4322 /*
4323 * Log some of the features exposed to software.
4324 */
4325 uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4326 uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4327 uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4328 uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4329 uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4330 uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4331 LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4332 DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4333 LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4334 DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4335 pThis->fMgawInvMask, offFrcd, offIva));
4336 return VINF_SUCCESS;
4337}
4338
4339#else
4340
4341/**
4342 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4343 */
4344static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4345{
4346 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4347 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4348 PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4349 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4350
4351 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
4352 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4353 AssertRCReturn(rc, rc);
4354
4355 /* Set up the MMIO RZ handlers. */
4356 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4357 AssertRCReturn(rc, rc);
4358
4359 /* Set up the IOMMU RZ callbacks. */
4360 PDMIOMMUREGCC IommuReg;
4361 RT_ZERO(IommuReg);
4362 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4363 IommuReg.idxIommu = pThis->idxIommu;
4364 IommuReg.pfnMemAccess = iommuIntelMemAccess;
4365 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4366 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4367 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4368
4369 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4370 AssertRCReturn(rc, rc);
4371 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4372 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4373 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4374 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4375 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4376 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4377 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4378
4379 return VINF_SUCCESS;
4380}
4381
4382#endif
4383
4384
4385/**
4386 * The device registration structure.
4387 */
4388PDMDEVREG const g_DeviceIommuIntel =
4389{
4390 /* .u32Version = */ PDM_DEVREG_VERSION,
4391 /* .uReserved0 = */ 0,
4392 /* .szName = */ "iommu-intel",
4393 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4394 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4395 /* .cMaxInstances = */ 1,
4396 /* .uSharedVersion = */ 42,
4397 /* .cbInstanceShared = */ sizeof(DMAR),
4398 /* .cbInstanceCC = */ sizeof(DMARCC),
4399 /* .cbInstanceRC = */ sizeof(DMARRC),
4400 /* .cMaxPciDevices = */ 1,
4401 /* .cMaxMsixVectors = */ 0,
4402 /* .pszDescription = */ "IOMMU (Intel)",
4403#if defined(IN_RING3)
4404 /* .pszRCMod = */ "VBoxDDRC.rc",
4405 /* .pszR0Mod = */ "VBoxDDR0.r0",
4406 /* .pfnConstruct = */ iommuIntelR3Construct,
4407 /* .pfnDestruct = */ iommuIntelR3Destruct,
4408 /* .pfnRelocate = */ NULL,
4409 /* .pfnMemSetup = */ NULL,
4410 /* .pfnPowerOn = */ NULL,
4411 /* .pfnReset = */ iommuIntelR3Reset,
4412 /* .pfnSuspend = */ NULL,
4413 /* .pfnResume = */ NULL,
4414 /* .pfnAttach = */ NULL,
4415 /* .pfnDetach = */ NULL,
4416 /* .pfnQueryInterface = */ NULL,
4417 /* .pfnInitComplete = */ NULL,
4418 /* .pfnPowerOff = */ NULL,
4419 /* .pfnSoftReset = */ NULL,
4420 /* .pfnReserved0 = */ NULL,
4421 /* .pfnReserved1 = */ NULL,
4422 /* .pfnReserved2 = */ NULL,
4423 /* .pfnReserved3 = */ NULL,
4424 /* .pfnReserved4 = */ NULL,
4425 /* .pfnReserved5 = */ NULL,
4426 /* .pfnReserved6 = */ NULL,
4427 /* .pfnReserved7 = */ NULL,
4428#elif defined(IN_RING0)
4429 /* .pfnEarlyConstruct = */ NULL,
4430 /* .pfnConstruct = */ iommuIntelRZConstruct,
4431 /* .pfnDestruct = */ NULL,
4432 /* .pfnFinalDestruct = */ NULL,
4433 /* .pfnRequest = */ NULL,
4434 /* .pfnReserved0 = */ NULL,
4435 /* .pfnReserved1 = */ NULL,
4436 /* .pfnReserved2 = */ NULL,
4437 /* .pfnReserved3 = */ NULL,
4438 /* .pfnReserved4 = */ NULL,
4439 /* .pfnReserved5 = */ NULL,
4440 /* .pfnReserved6 = */ NULL,
4441 /* .pfnReserved7 = */ NULL,
4442#elif defined(IN_RC)
4443 /* .pfnConstruct = */ iommuIntelRZConstruct,
4444 /* .pfnReserved0 = */ NULL,
4445 /* .pfnReserved1 = */ NULL,
4446 /* .pfnReserved2 = */ NULL,
4447 /* .pfnReserved3 = */ NULL,
4448 /* .pfnReserved4 = */ NULL,
4449 /* .pfnReserved5 = */ NULL,
4450 /* .pfnReserved6 = */ NULL,
4451 /* .pfnReserved7 = */ NULL,
4452#else
4453# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4454#endif
4455 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4456};
4457
4458#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4459
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