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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.h@ 103914

Last change on this file since 103914 was 98103, checked in by vboxsync, 21 months ago

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1/* $Id: DevHdaStream.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
29#define VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
35# error "Only include DevHda.h!"
36#endif
37
38
39/**
40 * Structure containing HDA stream debug stuff, configurable at runtime.
41 */
42typedef struct HDASTREAMDEBUGRT
43{
44 /** Whether debugging is enabled or not. */
45 bool fEnabled;
46 uint8_t Padding[7];
47 /** File for dumping stream reads / writes.
48 * For input streams, this dumps data being written to the device FIFO,
49 * whereas for output streams this dumps data being read from the device FIFO. */
50 R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
51 /** File for dumping raw DMA reads / writes.
52 * For input streams, this dumps data being written to the device DMA,
53 * whereas for output streams this dumps data being read from the device DMA. */
54 R3PTRTYPE(PAUDIOHLPFILE) pFileDMARaw;
55 /** File for dumping mapped (that is, extracted) DMA reads / writes. */
56 R3PTRTYPE(PAUDIOHLPFILE) pFileDMAMapped;
57} HDASTREAMDEBUGRT;
58
59/**
60 * Structure containing HDA stream debug information.
61 */
62typedef struct HDASTREAMDEBUG
63{
64 /** Runtime debug info. */
65 HDASTREAMDEBUGRT Runtime;
66 uint64_t au64Alignment[2];
67} HDASTREAMDEBUG;
68
69/**
70 * Internal state of a HDA stream.
71 */
72typedef struct HDASTREAMSTATE
73{
74 /** Flag indicating whether this stream currently is
75 * in reset mode and therefore not acccessible by the guest. */
76 volatile bool fInReset;
77 /** Flag indicating if the stream is in running state or not. */
78 volatile bool fRunning;
79 /** How many interrupts are pending due to
80 * BDLE interrupt-on-completion (IOC) bits set. */
81 uint8_t cTransferPendingInterrupts;
82 /** Input streams only: Set when we switch from feeding the guest silence and
83 * commits to proving actual audio input bytes. */
84 bool fInputPreBuffered;
85 /** Input streams only: The number of bytes we need to prebuffer. */
86 uint32_t cbInputPreBuffer;
87 /** Timestamp (absolute, in timer ticks) of the last DMA data transfer.
88 * @note This is used for wall clock (WALCLK) calculations. */
89 uint64_t volatile tsTransferLast;
90 /** The stream's current configuration (matches SDnFMT). */
91 PDMAUDIOSTREAMCFG Cfg;
92 /** Timestamp (real time, in ns) of last DMA transfer. */
93 uint64_t tsLastTransferNs;
94 /** Timestamp (real time, in ns) of last stream read (to backends).
95 * When running in async I/O mode, this differs from \a tsLastTransferNs,
96 * because reading / processing will be done in a separate stream. */
97 uint64_t tsLastReadNs;
98
99 /** The start time for the playback (on the timer clock). */
100 uint64_t tsStart;
101
102 /** @name DMA engine
103 * @{ */
104 /** Timestamp (absolute, in timer ticks) of the next DMA data transfer.
105 * Next for determining the next scheduling window.
106 * Can be 0 if no next transfer is scheduled. */
107 uint64_t tsTransferNext;
108 /** The size of the current DMA transfer period. */
109 uint32_t cbCurDmaPeriod;
110 /** The size of an average transfer. */
111 uint32_t cbAvgTransfer;
112
113 /** Current circular buffer read offset (for tracing & logging). */
114 uint64_t offRead;
115 /** Current circular buffer write offset (for tracing & logging). */
116 uint64_t offWrite;
117
118 /** The offset into the current BDLE. */
119 uint32_t offCurBdle;
120 /** LVI + 1 */
121 uint16_t cBdles;
122 /** The index of the current BDLE.
123 * This is the entry which period is currently "running" on the DMA timer. */
124 uint8_t idxCurBdle;
125 /** The number of prologue scheduling steps.
126 * This is used when the tail BDLEs doesn't have IOC set. */
127 uint8_t cSchedulePrologue;
128 /** Number of scheduling steps. */
129 uint16_t cSchedule;
130 /** Current scheduling step. */
131 uint16_t idxSchedule;
132 /** Current loop number within the current scheduling step. */
133 uint32_t idxScheduleLoop;
134
135 /** Buffer descriptors and additional timer scheduling state.
136 * (Same as HDABDLEDESC, with more sensible naming.) */
137 struct
138 {
139 /** The buffer address. */
140 uint64_t GCPhys;
141 /** The buffer size (guest bytes). */
142 uint32_t cb;
143 /** The flags (only bit 0 is defined). */
144 uint32_t fFlags;
145 } aBdl[256];
146 /** Scheduling steps. */
147 struct
148 {
149 /** Number of timer ticks per period.
150 * ASSUMES that we don't need a full second and that the timer resolution
151 * isn't much higher than nanoseconds. */
152 uint32_t cPeriodTicks;
153 /** The period length in host bytes. */
154 uint32_t cbPeriod;
155 /** Number of times to repeat the period. */
156 uint32_t cLoops;
157 /** The BDL index of the first entry. */
158 uint8_t idxFirst;
159 /** The number of BDL entries. */
160 uint8_t cEntries;
161 uint8_t abPadding[2];
162 } aSchedule[512+8];
163
164#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
165 /** Number of valid bytes in abDma.
166 * @note Volatile to prevent the compiler from re-reading it after we've
167 * validated the value in ring-0. */
168 uint32_t volatile cbDma;
169 /** Total number of bytes going via abDma this timer period. */
170 uint32_t cbDmaTotal;
171 /** DMA bounce buffer for ring-0 register reads (LPIB). */
172 uint8_t abDma[2048 - 8];
173#endif
174 /** @} */
175} HDASTREAMSTATE;
176AssertCompileSizeAlignment(HDASTREAMSTATE, 16);
177AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 8);
178AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 16);
179AssertCompileMemberAlignment(HDASTREAMSTATE, aSchedule, 16);
180
181/**
182 * An HDA stream (SDI / SDO) - shared.
183 *
184 * @note This HDA stream has nothing to do with a regular audio stream handled
185 * by the audio connector or the audio mixer. This HDA stream is a serial
186 * data in/out stream (SDI/SDO) defined in hardware and can contain
187 * multiple audio streams in one single SDI/SDO (interleaving streams).
188 *
189 * Contains only register values which do *not* change until a stream reset
190 * occurs.
191 */
192typedef struct HDASTREAM
193{
194 /** Internal state of this stream. */
195 HDASTREAMSTATE State;
196
197 /** Stream descriptor number (SDn). */
198 uint8_t u8SD;
199 /** Current channel index.
200 * For a stereo stream, this is u8Channel + 1. */
201 uint8_t u8Channel;
202 /** FIFO Watermark (checked + translated in bytes, FIFOW).
203 * This will be update from hdaRegWriteSDFIFOW() and also copied
204 * hdaR3StreamInit() for some reason. */
205 uint8_t u8FIFOW;
206
207 /** @name Register values at stream setup.
208 * These will all be copied in hdaR3StreamInit().
209 * @{ */
210 /** FIFO Size (checked + translated in bytes, FIFOS).
211 * This is supposedly the max number of bytes we'll be DMA'ing in one chunk
212 * and correspondingly the LPIB & wall clock update jumps. However, we're
213 * not at all being honest with the guest about this. */
214 uint8_t u8FIFOS;
215 /** Cyclic Buffer Length (SDnCBL) - Represents the size of the ring buffer. */
216 uint32_t u32CBL;
217 /** Last Valid Index (SDnLVI). */
218 uint16_t u16LVI;
219 /** Format (SDnFMT). */
220 uint16_t u16FMT;
221 uint8_t abPadding[4];
222 /** DMA base address (SDnBDPU - SDnBDPL). */
223 uint64_t u64BDLBase;
224 /** @} */
225
226 /** The timer for pumping data thru the attached LUN drivers. */
227 TMTIMERHANDLE hTimer;
228
229 /** Pad the structure size to a 64 byte alignment. */
230 uint64_t au64Padding1[2];
231} HDASTREAM;
232AssertCompileMemberAlignment(HDASTREAM, State.aBdl, 16);
233AssertCompileMemberAlignment(HDASTREAM, State.aSchedule, 16);
234AssertCompileSizeAlignment(HDASTREAM, 64);
235/** Pointer to an HDA stream (SDI / SDO). */
236typedef HDASTREAM *PHDASTREAM;
237
238
239/**
240 * An HDA stream (SDI / SDO) - ring-3 bits.
241 */
242typedef struct HDASTREAMR3
243{
244 /** Stream descriptor number (SDn). */
245 uint8_t u8SD;
246 uint8_t abPadding[7];
247 /** The shared state for the parent HDA device. */
248 R3PTRTYPE(PHDASTATE) pHDAStateShared;
249 /** The ring-3 state for the parent HDA device. */
250 R3PTRTYPE(PHDASTATER3) pHDAStateR3;
251 /** Pointer to HDA sink this stream is attached to. */
252 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
253 /** Internal state of this stream. */
254 struct
255 {
256 /** Circular buffer (FIFO) for holding DMA'ed data. */
257 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
258 /** The mixer sink this stream has registered AIO update callback with.
259 * This is NULL till we register it, typically in hdaR3StreamEnable.
260 * (The problem with following the pMixSink assignment is that hdaR3StreamReset
261 * sets it without updating the HDA sink structure, so things get out of
262 * wack in hdaR3MixerControl later in the initial device reset.) */
263 PAUDMIXSINK pAioRegSink;
264
265 /** Size of the DMA buffer (pCircBuf) in bytes. */
266 uint32_t StatDmaBufSize;
267 /** Number of used bytes in the DMA buffer (pCircBuf). */
268 uint32_t StatDmaBufUsed;
269 /** Counter for all under/overflows problems. */
270 STAMCOUNTER StatDmaFlowProblems;
271 /** Counter for unresovled under/overflows problems. */
272 STAMCOUNTER StatDmaFlowErrors;
273 /** Number of bytes involved in unresolved flow errors. */
274 STAMCOUNTER StatDmaFlowErrorBytes;
275 /** DMA skipped because buffer interrupt pending. */
276 STAMCOUNTER StatDmaSkippedPendingBcis;
277
278 STAMPROFILE StatStart;
279 STAMPROFILE StatReset;
280 STAMPROFILE StatStop;
281 } State;
282 /** Debug bits. */
283 HDASTREAMDEBUG Dbg;
284 uint64_t au64Alignment[3];
285} HDASTREAMR3;
286AssertCompileSizeAlignment(HDASTREAMR3, 64);
287/** Pointer to an HDA stream (SDI / SDO). */
288typedef HDASTREAMR3 *PHDASTREAMR3;
289
290/** @name Stream functions (all contexts).
291 * @{
292 */
293VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
294 uint64_t tsNow, uint32_t cbToTransfer);
295VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis,
296 PHDASTREAM pStreamShared, uint64_t tsNow);
297/** @} */
298
299#ifdef IN_RING3
300
301/** @name Stream functions (ring-3).
302 * @{
303 */
304int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis,
305 PHDASTATER3 pThisCC, uint8_t uSD);
306void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3);
307int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
308 PHDASTREAMR3 pStreamR3, uint8_t uSD);
309void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC,
310 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD);
311int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable);
312void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow);
313void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared);
314
315uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
316 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
317DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser);
318/** @} */
319
320/** @name Helper functions associated with the stream code.
321 * @{ */
322int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
323# ifdef LOG_ENABLED
324void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
325# endif
326/** @} */
327
328#endif /* IN_RING3 */
329#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaStream_h */
330
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