VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp

Last change on this file was 103134, checked in by vboxsync, 3 months ago

Audio: More locking needed to avoid debug assertions when draining a stream on stream disable. This debug assertion will happen because EMT and the mixer's async I/O thread work on the same circular buffer. There can be situations, if no locking is being used, that the async I/O thread just has consumed the remaining data just a tad before EMT looks for remaining data within the same buffer when disabling the stream. Also, don't immediately (hard) reset the circular buffer when a stream gets disabled, as this will wipe the already announced amount of remaining data when draining a stream. bugref:10354
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 104.4 KB
Line 
1/* $Id: DevHdaStream.cpp 103134 2024-01-31 09:21:06Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_HDA
33#include <VBox/log.h>
34
35#include <iprt/mem.h>
36#include <iprt/semaphore.h>
37#include <iprt/zero.h>
38
39#include <VBox/AssertGuest.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmaudioifs.h>
42#include <VBox/vmm/pdmaudioinline.h>
43
44#include "AudioHlp.h"
45
46#include "DevHda.h"
47
48#ifdef VBOX_WITH_DTRACE
49# include "dtrace/VBoxDD.h"
50#endif
51
52
53/*********************************************************************************************************************************
54* Internal Functions *
55*********************************************************************************************************************************/
56#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
57static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
58#endif
59#ifdef IN_RING3
60# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
61static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
62# endif
63static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
64 uint32_t cbNeeded, uint64_t nsNow,
65 const char *pszCaller, uint32_t const cbStreamFree);
66static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
67 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
68#endif
69
70
71#ifdef IN_RING3
72
73/**
74 * Creates an HDA stream.
75 *
76 * @returns VBox status code.
77 * @param pStreamShared The HDA stream to construct - shared bits.
78 * @param pStreamR3 The HDA stream to construct - ring-3 bits.
79 * @param pThis The shared HDA device instance.
80 * @param pThisCC The ring-3 HDA device instance.
81 * @param uSD Stream descriptor number to assign.
82 */
83int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
84{
85 pStreamR3->u8SD = uSD;
86 pStreamShared->u8SD = uSD;
87 pStreamR3->pMixSink = NULL;
88 pStreamR3->pHDAStateShared = pThis;
89 pStreamR3->pHDAStateR3 = pThisCC;
90 Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
91
92 pStreamShared->State.fInReset = false;
93 pStreamShared->State.fRunning = false;
94
95 AssertPtr(pStreamR3->pHDAStateR3);
96 AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
97
98 const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
99
100 if (fIsInput)
101 {
102 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
103 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
104 }
105 else
106 {
107 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
108 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
109 }
110
111 pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
112
113 if (pStreamR3->Dbg.Runtime.fEnabled)
114 {
115 int rc2 = AudioHlpFileCreateF(&pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
116 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
117 fIsInput ? "hdaStreamWriteSD%RU8" : "hdaStreamReadSD%RU8", uSD);
118 AssertRC(rc2);
119
120 /* pFileDMARaw */
121 rc2 = AudioHlpFileCreateF(&pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
122 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
123 fIsInput ? "hdaDMARawWriteSD%RU8" : "hdaDMARawReadSD%RU8", uSD);
124 AssertRC(rc2);
125
126 /* pFileDMAMapped */
127 rc2 = AudioHlpFileCreateF(&pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_FLAGS_NONE, AUDIOHLPFILETYPE_WAV,
128 pThisCC->Dbg.pszOutPath, AUDIOHLPFILENAME_FLAGS_NONE, 0 /*uInstance*/,
129 fIsInput ? "hdaDMAWriteMappedSD%RU8" : "hdaDMAReadMappedSD%RU8", uSD);
130 AssertRC(rc2);
131
132 /* Delete stale debugging files from a former run. */
133 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
134 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
135 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
136 }
137
138 return VINF_SUCCESS;
139}
140
141/**
142 * Destroys an HDA stream.
143 *
144 * @param pStreamR3 The HDA stream to destroy - ring-3 bits.
145 */
146void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
147{
148 LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
149 int rc2;
150
151 if (pStreamR3->State.pAioRegSink)
152 {
153 rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
154 AssertRC(rc2);
155 pStreamR3->State.pAioRegSink = NULL;
156 }
157
158 if (pStreamR3->State.pCircBuf)
159 {
160 RTCircBufDestroy(pStreamR3->State.pCircBuf);
161 pStreamR3->State.pCircBuf = NULL;
162 pStreamR3->State.StatDmaBufSize = 0;
163 pStreamR3->State.StatDmaBufUsed = 0;
164 }
165
166 if (pStreamR3->Dbg.Runtime.fEnabled)
167 {
168 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
169 pStreamR3->Dbg.Runtime.pFileStream = NULL;
170
171 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
172 pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
173
174 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
175 pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
176 }
177
178 LogFlowFuncLeave();
179}
180
181
182/**
183 * Converts an HDA stream's SDFMT register into a given PCM properties structure.
184 *
185 * @returns VBox status code.
186 * @param u16SDFMT The HDA stream's SDFMT value to convert.
187 * @param pProps PCM properties structure to hold converted result on success.
188 */
189int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps)
190{
191 AssertPtrReturn(pProps, VERR_INVALID_POINTER);
192
193# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
194
195 int rc = VINF_SUCCESS;
196
197 uint32_t u32Hz = EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
198 ? 44100 : 48000;
199 uint32_t u32HzMult = 1;
200 uint32_t u32HzDiv = 1;
201
202 switch (EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
203 {
204 case 0: u32HzMult = 1; break;
205 case 1: u32HzMult = 2; break;
206 case 2: u32HzMult = 3; break;
207 case 3: u32HzMult = 4; break;
208 default:
209 LogFunc(("Unsupported multiplier %x\n",
210 EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
211 rc = VERR_NOT_SUPPORTED;
212 break;
213 }
214 switch (EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
215 {
216 case 0: u32HzDiv = 1; break;
217 case 1: u32HzDiv = 2; break;
218 case 2: u32HzDiv = 3; break;
219 case 3: u32HzDiv = 4; break;
220 case 4: u32HzDiv = 5; break;
221 case 5: u32HzDiv = 6; break;
222 case 6: u32HzDiv = 7; break;
223 case 7: u32HzDiv = 8; break;
224 default:
225 LogFunc(("Unsupported divisor %x\n",
226 EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
227 rc = VERR_NOT_SUPPORTED;
228 break;
229 }
230
231 uint8_t cbSample = 0;
232 switch (EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
233 {
234 case 0:
235 cbSample = 1;
236 break;
237 case 1:
238 cbSample = 2;
239 break;
240 case 4:
241 cbSample = 4;
242 break;
243 default:
244 AssertMsgFailed(("Unsupported bits per sample %x\n",
245 EXTRACT_VALUE(u16SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
246 rc = VERR_NOT_SUPPORTED;
247 break;
248 }
249
250 if (RT_SUCCESS(rc))
251 {
252 PDMAudioPropsInit(pProps, cbSample, true /*fSigned*/, (u16SDFMT & 0xf) + 1 /*cChannels*/, u32Hz * u32HzMult / u32HzDiv);
253 /** @todo is there anything we need to / can do about channel assignments? */
254 }
255
256# undef EXTRACT_VALUE
257 return rc;
258}
259
260# ifdef LOG_ENABLED
261void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
262{
263 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
264 if (!u64BDLBase)
265 return;
266
267 uint32_t cbBDLE = 0;
268 for (uint16_t i = 0; i < cBDLE; i++)
269 {
270 HDABDLEDESC bd;
271 PDMDevHlpPhysRead(pDevIns, u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
272
273 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
274 i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_F_IOC));
275
276 cbBDLE += bd.u32BufSize;
277 }
278
279 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
280
281 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
282 return;
283
284 LogFlowFunc(("DMA counters:\n"));
285
286 for (int i = 0; i < cBDLE; i++)
287 {
288 uint32_t uDMACnt;
289 PDMDevHlpPhysRead(pDevIns, (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
290 &uDMACnt, sizeof(uDMACnt));
291
292 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
293 }
294}
295# endif /* LOG_ENABLED */
296
297
298/**
299 * Appends a item to the scheduler.
300 *
301 * @returns VBox status code.
302 * @param pStreamShared The stream which scheduler should be modified.
303 * @param cbCur The period length in guest bytes.
304 * @param cbMaxPeriod The max period in guest bytes.
305 * @param idxLastBdle The last BDLE in the period.
306 * @param pProps The PCM properties.
307 * @param pcbBorrow Where to account for bytes borrowed across buffers
308 * to align scheduling items on frame boundraries.
309 */
310static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod,
311 uint32_t idxLastBdle, PCPDMAUDIOPCMPROPS pProps, uint32_t *pcbBorrow)
312{
313 /* Check that we've got room (shouldn't ever be a problem). */
314 size_t idx = pStreamShared->State.cSchedule;
315 AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
316
317 /* Figure out the BDLE range for this period. */
318 uint32_t const idxFirstBdle = idx == 0 ? 0
319 : RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
320 + pStreamShared->State.aSchedule[idx - 1].cEntries),
321 idxLastBdle);
322
323 pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
324 pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
325 ? idxLastBdle - idxFirstBdle + 1
326 : pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
327
328 /* Deal with borrowing due to unaligned IOC buffers. */
329 uint32_t const cbBorrowed = *pcbBorrow;
330 if (cbBorrowed < cbCur)
331 cbCur -= cbBorrowed;
332 else
333 {
334 /* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
335 ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
336 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
337 LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
338 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
339 return VERR_OUT_OF_RANGE;
340 }
341
342 uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pProps, cbCur);
343 *pcbBorrow = cbCurAligned - cbCur;
344
345 /* Do we need to split up the period? */
346 if (cbCurAligned <= cbMaxPeriod)
347 {
348 pStreamShared->State.aSchedule[idx].cbPeriod = cbCurAligned;
349 pStreamShared->State.aSchedule[idx].cLoops = 1;
350 }
351 else
352 {
353 /* Reduce till we've below the threshold. */
354 uint32_t cbLoop = cbCurAligned;
355 do
356 cbLoop = cbLoop / 2;
357 while (cbLoop > cbMaxPeriod);
358 cbLoop = PDMAudioPropsRoundUpBytesToFrame(pProps, cbLoop);
359
360 /* Complete the scheduling item. */
361 pStreamShared->State.aSchedule[idx].cbPeriod = cbLoop;
362 pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
363
364 /* If there is a remainder, add it as a separate entry (this is
365 why the schedule must be more than twice the size of the BDL).*/
366 cbCurAligned %= cbLoop;
367 if (cbCurAligned)
368 {
369 pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
370 idx++;
371 pStreamShared->State.aSchedule[idx].cbPeriod = cbCurAligned;
372 pStreamShared->State.aSchedule[idx].cLoops = 1;
373 }
374 }
375
376 /* Done. */
377 pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
378
379 return VINF_SUCCESS;
380}
381
382/**
383 * Creates the DMA timer schedule for the stream
384 *
385 * This is called from the stream setup code.
386 *
387 * @returns VBox status code.
388 * @param pStreamShared The stream to create a schedule for. The BDL
389 * must be loaded.
390 * @param cSegments Number of BDL segments.
391 * @param cBufferIrqs Number of the BDLEs with IOC=1.
392 * @param cbTotal The total BDL length in guest bytes.
393 * @param cbMaxPeriod Max period in guest bytes. This is in case the
394 * guest want to play the whole "Der Ring des
395 * Nibelungen" cycle in one go.
396 * @param cTimerTicksPerSec The DMA timer frequency.
397 * @param pProps The PCM properties.
398 */
399static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
400 uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec, PCPDMAUDIOPCMPROPS pProps)
401{
402 int rc;
403
404 /*
405 * Reset scheduling state.
406 */
407 RT_ZERO(pStreamShared->State.aSchedule);
408 pStreamShared->State.cSchedule = 0;
409 pStreamShared->State.cSchedulePrologue = 0;
410 pStreamShared->State.idxSchedule = 0;
411 pStreamShared->State.idxScheduleLoop = 0;
412
413 /*
414 * Do the basic schedule compilation.
415 */
416 uint32_t cPotentialPrologue = 0;
417 uint32_t cbBorrow = 0;
418 uint32_t cbCur = 0;
419 uint32_t cbMin = UINT32_MAX;
420 pStreamShared->State.aSchedule[0].idxFirst = 0;
421 for (uint32_t i = 0; i < cSegments; i++)
422 {
423 cbCur += pStreamShared->State.aBdl[i].cb;
424 if (pStreamShared->State.aBdl[i].cb < cbMin)
425 cbMin = pStreamShared->State.aBdl[i].cb;
426 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
427 {
428 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pProps, &cbBorrow);
429 ASSERT_GUEST_RC_RETURN(rc, rc);
430
431 if (cPotentialPrologue == 0)
432 cPotentialPrologue = pStreamShared->State.cSchedule;
433 cbCur = 0;
434 }
435 }
436
437 /*
438 * Deal with any loose ends.
439 */
440 if (cbCur && cBufferIrqs == 0)
441 {
442 /*
443 * No IOC. Vista ends up here, typically with three buffers configured.
444 *
445 * The perferred option here is to aim at processing one average BDLE with
446 * each DMA timer period, since that best matches how we update LPIB at
447 * present.
448 *
449 * The second alternative is to divide the whole span up into 3-4 periods
450 * to try increase our chances of keeping ahead of the guest. We may need
451 * to pick this if there are too few buffer descriptor or they are too small.
452 *
453 * However, what we probably should be doing is to do real DMA work whenever
454 * the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
455 * timer periods, however we'll be postponing the DMA timer every time we
456 * return to ring-3 and signal the AIO, so in the end we'd probably not use
457 * the timer callback at all. (This is assuming a small shared per-stream
458 * buffer for keeping the DMA data in and that it's size will force a return
459 * to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
460 */
461 Assert(cbCur == cbTotal);
462
463 /* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
464 is at least 5ms big. */
465 if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pProps, cbMin) >= 5 /*ms*/)
466 {
467 for (uint32_t i = 0; i < cSegments; i++)
468 {
469 rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod, i, pProps, &cbBorrow);
470 ASSERT_GUEST_RC_RETURN(rc, rc);
471 }
472 }
473 /* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
474 It seems, though, that this only really work for windows vista if we avoid
475 working accross buffer lines. */
476 /** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
477 * is read, assuming ofc that LPIB is read before each buffer update. */
478 else
479 {
480 uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pProps, cbCur) >= 4 * 5 /*ms*/
481 ? 4 : cSegments != 2 ? 3 : 2;
482 uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pProps, cbCur / cPeriods);
483 uint32_t iBdle = 0;
484 uint32_t offBdle = 0;
485 for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
486 {
487 if (iPeriod + 1 < cPeriods)
488 {
489 offBdle += cbPeriod;
490 while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
491 offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
492 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
493 pProps, &cbBorrow);
494 }
495 else
496 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
497 pProps, &cbBorrow);
498 ASSERT_GUEST_RC_RETURN(rc, rc);
499 }
500
501 }
502 }
503 else if (cbCur)
504 {
505 /* The last BDLE didn't have IOC set, so we must continue processing
506 from the start till we hit one that has. */
507 uint32_t i;
508 for (i = 0; i < cSegments; i++)
509 {
510 cbCur += pStreamShared->State.aBdl[i].cb;
511 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
512 break;
513 }
514 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pProps, &cbBorrow);
515 ASSERT_GUEST_RC_RETURN(rc, rc);
516
517 /* The initial scheduling items covering the wrap around area are
518 considered a prologue and must not repeated later. */
519 Assert(cPotentialPrologue);
520 pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
521 }
522
523 AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
524 pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
525 VERR_INTERNAL_ERROR_3);
526
527 /*
528 * If there is just one BDLE with IOC set, we have to make sure
529 * we've got at least two periods scheduled, otherwise there is
530 * a very good chance the guest will overwrite the start of the
531 * buffer before we ever get around to reading it.
532 */
533 if (cBufferIrqs == 1)
534 {
535 uint32_t i = pStreamShared->State.cSchedulePrologue;
536 Assert(i < pStreamShared->State.cSchedule);
537 if ( i + 1 == pStreamShared->State.cSchedule
538 && pStreamShared->State.aSchedule[i].cLoops == 1)
539 {
540 uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
541 uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
542 pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
543 if (cbFirstHalf == cbOtherHalf)
544 pStreamShared->State.aSchedule[i].cLoops = 2;
545 else
546 {
547 pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
548 pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
549 pStreamShared->State.cSchedule++;
550 }
551 }
552 }
553
554 /*
555 * Go over the schduling entries and calculate the timer ticks for each period.
556 */
557 LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
558 pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
559 uint64_t const cbPerSec = PDMAudioPropsFramesToBytes(pProps, pProps->uHz);
560 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
561 {
562 uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod, cbPerSec);
563 AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
564 pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
565 LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
566 pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
567 pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
568 }
569
570 return VINF_SUCCESS;
571}
572
573
574/**
575 * Sets up ((re-)iniitalizes) an HDA stream.
576 *
577 * @returns VBox status code. VINF_NO_CHANGE if the stream does not need
578 * be set-up again because the stream's (hardware) parameters did
579 * not change.
580 * @param pDevIns The device instance.
581 * @param pThis The shared HDA device state (for HW register
582 * parameters).
583 * @param pStreamShared HDA stream to set up, shared portion.
584 * @param pStreamR3 HDA stream to set up, ring-3 portion.
585 * @param uSD Stream descriptor number to assign it.
586 */
587int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
588{
589 /* This must be valid all times. */
590 AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
591
592 /* These member can only change on data corruption, despite what the code does further down (bird). */
593 AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
594 AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
595
596 const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
597 HDA_STREAM_REG(pThis, BDPU, uSD));
598 const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
599 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
600 const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
601 uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
602 const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
603
604 /* Is the bare minimum set of registers configured for the stream?
605 * If not, bail out early, as there's nothing to do here for us (yet). */
606 if ( !u64BDLBase
607 || !u16LVI
608 || !u32CBL
609 || !u8FIFOS
610 || !u8FIFOW
611 || !u16FMT)
612 {
613 LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
614 return VINF_SUCCESS;
615 }
616
617 /*
618 * Convert the config to PDM PCM properties and configure the stream.
619 */
620 PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
621 int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
622 if (RT_SUCCESS(rc))
623 pCfg->enmDir = hdaGetDirFromSD(uSD);
624 else
625 {
626 LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
627 return rc;
628 }
629
630 ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
631 && u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
632 ("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
633 uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
634 VERR_INVALID_PARAMETER);
635
636 /* Make sure the guest behaves regarding the stream's FIFO. */
637 ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
638 ("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
639 u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
640
641 pStreamShared->u8SD = uSD;
642
643 /* Update all register copies so that we later know that something has changed. */
644 pStreamShared->u64BDLBase = u64BDLBase;
645 pStreamShared->u16LVI = u16LVI;
646 pStreamShared->u32CBL = u32CBL;
647 pStreamShared->u8FIFOS = u8FIFOS;
648 pStreamShared->u8FIFOW = u8FIFOW;
649 pStreamShared->u16FMT = u16FMT;
650
651 /* The the stream's name, based on the direction. */
652 switch (pCfg->enmDir)
653 {
654 case PDMAUDIODIR_IN:
655# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
656# error "Implement me!"
657# else
658 pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
659 RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
660# endif
661 break;
662
663 case PDMAUDIODIR_OUT:
664 /* Destination(s) will be set in hdaR3AddStreamOut(),
665 * based on the channels / stream layout. */
666 break;
667
668 default:
669 AssertFailedReturn(VERR_NOT_SUPPORTED);
670 break;
671 }
672
673 LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
674 pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
675
676 /*
677 * Load the buffer descriptor list.
678 *
679 * Section 3.6.2 states that "the BDL should not be modified unless the RUN
680 * bit is 0", so it should be within the specs to read it once here and not
681 * re-read any BDLEs later.
682 */
683 /* Reset BDL state. */
684 RT_ZERO(pStreamShared->State.aBdl);
685 pStreamShared->State.offCurBdle = 0;
686 pStreamShared->State.idxCurBdle = 0;
687
688 uint32_t /*const*/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
689 if (cTransferFragments <= 1)
690 LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
691 AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
692 pStreamShared->State.cBdles = cTransferFragments;
693
694 /* Load them. */
695 rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
696 sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
697 AssertRC(rc);
698
699 /* Check what we just loaded. Refuse overly large buffer lists. */
700 uint64_t cbTotal = 0;
701 uint32_t cBufferIrqs = 0;
702 for (uint32_t i = 0; i < cTransferFragments; i++)
703 {
704 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
705 cBufferIrqs++;
706 cbTotal += pStreamShared->State.aBdl[i].cb;
707 }
708 ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
709 LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
710 uSD, cbTotal, cbTotal)),
711 VERR_NOT_SUPPORTED);
712 ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
713 LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
714 uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
715 VERR_NOT_SUPPORTED);
716
717 /*
718 * Create a DMA timer schedule.
719 */
720 rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
721 PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
722 PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer), &pCfg->Props);
723 if (RT_FAILURE(rc))
724 return rc;
725
726 pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[0].cbPeriod;
727
728 /*
729 * Calculate the transfer Hz for use in the circular buffer calculation
730 * and the average period for the scheduling hint.
731 */
732 uint32_t cbMaxPeriod = 0;
733 uint32_t cbMinPeriod = UINT32_MAX;
734 uint64_t cTicks = 0;
735 uint32_t cPeriods = 0;
736 for (uint32_t i = pStreamShared->State.cSchedulePrologue; i < pStreamShared->State.cSchedule; i++)
737 {
738 uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
739 cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
740 cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
741 cPeriods += pStreamShared->State.aSchedule[i].cLoops;
742 cTicks += pStreamShared->State.aSchedule[i].cPeriodTicks * pStreamShared->State.aSchedule[i].cLoops;
743 }
744 /* Only consider the prologue in relation to the max period. */
745 for (uint32_t i = 0; i < pStreamShared->State.cSchedulePrologue; i++)
746 cbMaxPeriod = RT_MAX(cbMaxPeriod, pStreamShared->State.aSchedule[i].cbPeriod);
747
748 AssertLogRelReturn(cPeriods > 0, VERR_INTERNAL_ERROR_3);
749 uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
750 4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
751 unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
752 LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
753 uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
754 uTransferHz /= 1000;
755
756 if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
757 LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
758 uSD, uTransferHz));
759
760 pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
761
762 /* Calculate the average scheduling period length in nanoseconds. */
763 uint64_t const cTimerResolution = PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer);
764 Assert(cTimerResolution <= UINT32_MAX);
765 uint64_t const cNsPerPeriod = ASMMultU64ByU32DivByU32(cTicks / cPeriods, RT_NS_1SEC, cTimerResolution);
766 AssertLogRelReturn(cNsPerPeriod > 0, VERR_INTERNAL_ERROR_3);
767
768 /* For input streams we must determin a pre-buffering requirement.
769 We use the initial delay as a basis here, though we must have at
770 least two max periods worth of data queued up due to the way we
771 work the AIO thread. */
772 pStreamShared->State.fInputPreBuffered = false;
773 pStreamShared->State.cbInputPreBuffer = cbMaxPeriod * 2;
774
775 /*
776 * Set up data transfer stuff.
777 */
778 /* Set I/O scheduling hint for the backends. */
779 pCfg->Device.cMsSchedulingHint = cNsPerPeriod > RT_NS_1MS ? (cNsPerPeriod + RT_NS_1MS / 2) / RT_NS_1MS : 1;
780 LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
781
782 /* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
783 /** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
784 * locate the right place in the schedule and whatnot...
785 *
786 * This is a similar scenario as when loading state saved, btw.
787 */
788 if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
789 LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
790 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
791
792# ifdef LOG_ENABLED
793 hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
794# endif
795
796 /*
797 * Set up internal ring buffer.
798 */
799
800 /*
801 * The default internal ring buffer size must be:
802 *
803 * - Large enough for at least three periodic DMA transfers.
804 *
805 * It is critically important that we don't experience underruns
806 * in the DMA OUT code, because it will cause the buffer processing
807 * to get skewed and possibly overlap with what the guest is updating.
808 * At the time of writing (2021-03-05) there is no code for getting
809 * back into sync there.
810 *
811 * - Large enough for at least three I/O scheduling hints.
812 *
813 * We want to lag behind a DMA period or two, but there must be
814 * sufficent space for the AIO thread to get schedule and shuffle
815 * data thru the mixer and onto the host audio hardware.
816 *
817 * - Both above with plenty to spare.
818 *
819 * So, just take the longest of the two periods and multipling it by 6.
820 * We aren't not talking about very large base buffers heres, so size isn't
821 * an issue.
822 *
823 * Note: Use pCfg->Props as PCM properties here, as we only want to store the
824 * samples we actually need, in other words, skipping the interleaved
825 * channels we don't support / need to save space.
826 */
827 uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, RT_MS_1SEC * 6 / uTransferHz);
828 LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
829 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
830
831 uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
832 if (msCircBufCfg) /* Anything set via CFGM? */
833 {
834 cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
835 LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
836 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
837 }
838
839 /* Serious paranoia: */
840 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
841 ("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
842 cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
843 rc = VERR_INVALID_PARAMETER);
844 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
845 rc = VERR_INVALID_PARAMETER);
846 if (RT_SUCCESS(rc))
847 {
848 /**
849 * Note: Only re-create the DMA buffer if the size actually has changed.
850 *
851 * Otherwise do *not* reset the stream's circular buffer here, as the audio mixer still relies on
852 * previously announced DMA data (via AudioMixerSinkDrainAndStop()) and processes it asynchronously.
853 * Resetting the buffer here will cause a race condition. See @bugref{10354}. */
854 if (pStreamR3->State.StatDmaBufSize != cbCircBuf)
855 {
856 /* (Re-)Allocate the stream's internal DMA buffer,
857 * based on the timing *and* PCM properties we just got above. */
858 if (pStreamR3->State.pCircBuf)
859 {
860 RTCircBufDestroy(pStreamR3->State.pCircBuf);
861 pStreamR3->State.pCircBuf = NULL;
862 pStreamR3->State.StatDmaBufSize = 0;
863 pStreamR3->State.StatDmaBufUsed = 0;
864 }
865 pStreamShared->State.offWrite = 0;
866 pStreamShared->State.offRead = 0;
867
868 rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
869 if (RT_SUCCESS(rc))
870 {
871 pStreamR3->State.StatDmaBufSize = cbCircBuf;
872
873 /*
874 * Forward the timer frequency hint to TM as well for better accuracy on
875 * systems w/o preemption timers (also good for 'info timers').
876 */
877 PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
878 }
879 }
880 }
881
882 if (RT_FAILURE(rc))
883 LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
884
885# ifdef VBOX_WITH_DTRACE
886 VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
887 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
888 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
889# endif
890 return rc;
891}
892
893
894/**
895 * Worker for hdaR3StreamReset().
896 *
897 * @returns The default mixer sink, NULL if none found.
898 * @param pThisCC The ring-3 HDA device state.
899 * @param uSD SD# to return mixer sink for.
900 * NULL if not found / handled.
901 */
902static PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATER3 pThisCC, uint8_t uSD)
903{
904 if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN)
905 {
906 const uint8_t uFirstSDI = 0;
907
908 if (uSD == uFirstSDI) /* First SDI. */
909 return &pThisCC->SinkLineIn;
910# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
911 if (uSD == uFirstSDI + 1)
912 return &pThisCC->SinkMicIn;
913# else
914 /* If we don't have a dedicated Mic-In sink, use the always present Line-In sink. */
915 return &pThisCC->SinkLineIn;
916# endif
917 }
918 else
919 {
920 const uint8_t uFirstSDO = HDA_MAX_SDI;
921
922 if (uSD == uFirstSDO)
923 return &pThisCC->SinkFront;
924# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
925 if (uSD == uFirstSDO + 1)
926 return &pThisCC->SinkCenterLFE;
927 if (uSD == uFirstSDO + 2)
928 return &pThisCC->SinkRear;
929# endif
930 }
931
932 return NULL;
933}
934
935
936/**
937 * Resets an HDA stream.
938 *
939 * @param pThis The shared HDA device state.
940 * @param pThisCC The ring-3 HDA device state.
941 * @param pStreamShared HDA stream to reset (shared).
942 * @param pStreamR3 HDA stream to reset (ring-3).
943 * @param uSD Stream descriptor (SD) number to use for this stream.
944 */
945void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
946{
947 LogFunc(("[SD%RU8] Reset\n", uSD));
948
949 /*
950 * Assert some sanity.
951 */
952 AssertPtr(pThis);
953 AssertPtr(pStreamShared);
954 AssertPtr(pStreamR3);
955 Assert(uSD < HDA_MAX_STREAMS);
956 Assert(pStreamShared->u8SD == uSD);
957 Assert(pStreamR3->u8SD == uSD);
958 AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
959
960 /*
961 * Set reset state.
962 */
963 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
964 ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
965
966 /*
967 * Second, initialize the registers.
968 */
969 /* See 6.2.33: Clear on reset. */
970 HDA_STREAM_REG(pThis, STS, uSD) = 0;
971 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
972 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
973 HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
974 /* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
975 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
976 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
977 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
978 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
979 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
980 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
981 HDA_STREAM_REG(pThis, FMT, uSD) = 0;
982 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
983 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
984
985 /* Assign the default mixer sink to the stream. */
986 pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
987 if (pStreamR3->State.pAioRegSink)
988 {
989 int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
990 AssertRC(rc2);
991 pStreamR3->State.pAioRegSink = NULL;
992 }
993
994 /* Reset transfer stuff. */
995 pStreamShared->State.cTransferPendingInterrupts = 0;
996 pStreamShared->State.tsTransferLast = 0;
997 pStreamShared->State.tsTransferNext = 0;
998
999 /* Initialize timestamps. */
1000 pStreamShared->State.tsLastTransferNs = 0;
1001 pStreamShared->State.tsLastReadNs = 0;
1002 pStreamShared->State.tsStart = 0;
1003
1004 RT_ZERO(pStreamShared->State.aBdl);
1005 RT_ZERO(pStreamShared->State.aSchedule);
1006 pStreamShared->State.offCurBdle = 0;
1007 pStreamShared->State.cBdles = 0;
1008 pStreamShared->State.idxCurBdle = 0;
1009 pStreamShared->State.cSchedulePrologue = 0;
1010 pStreamShared->State.cSchedule = 0;
1011 pStreamShared->State.idxSchedule = 0;
1012 pStreamShared->State.idxScheduleLoop = 0;
1013 pStreamShared->State.fInputPreBuffered = false;
1014
1015 /* Note: Do *not* reset the stream's circular buffer here, as the audio mixer still relies on
1016 * previously announced DMA data (via AudioMixerSinkDrainAndStop()) and processes it asynchronously.
1017 * Resetting the buffer here will cause a race condition. See @bugref{10354}. */
1018
1019 /* Report that we're done resetting this stream. */
1020 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
1021
1022# ifdef VBOX_WITH_DTRACE
1023 VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
1024# endif
1025 LogFunc(("[SD%RU8] Reset\n", uSD));
1026
1027 /* Exit reset mode. */
1028 ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
1029}
1030
1031/**
1032 * Enables or disables an HDA audio stream.
1033 *
1034 * @returns VBox status code.
1035 * @param pThis The shared HDA device state.
1036 * @param pStreamShared HDA stream to enable or disable - shared bits.
1037 * @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
1038 * @param fEnable Whether to enable or disble the stream.
1039 */
1040int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
1041{
1042 AssertPtr(pStreamR3);
1043 AssertPtr(pStreamShared);
1044
1045 LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
1046
1047 /* First, enable or disable the stream and the stream's sink, if any. */
1048 int rc = VINF_SUCCESS;
1049 PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1050 if (pSink)
1051 {
1052 AudioMixerSinkLock(pSink);
1053
1054 if (fEnable)
1055 {
1056 if (pStreamR3->State.pAioRegSink != pSink)
1057 {
1058 if (pStreamR3->State.pAioRegSink)
1059 {
1060 rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
1061 AssertRC(rc);
1062 }
1063 rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
1064 pStreamShared->State.Cfg.Device.cMsSchedulingHint);
1065 AssertLogRelRC(rc);
1066 pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
1067 }
1068 rc = AudioMixerSinkStart(pSink);
1069 }
1070 else
1071 rc = AudioMixerSinkDrainAndStop(pSink,
1072 pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
1073
1074 AudioMixerSinkUnlock(pSink);
1075 }
1076 if ( RT_SUCCESS(rc)
1077 && fEnable
1078 && pStreamR3->Dbg.Runtime.fEnabled)
1079 {
1080 Assert(AudioHlpPcmPropsAreValidAndSupported(&pStreamShared->State.Cfg.Props));
1081
1082 if (fEnable)
1083 {
1084 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
1085 {
1086 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1087 &pStreamShared->State.Cfg.Props);
1088 AssertRC(rc2);
1089 }
1090
1091 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
1092 {
1093 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1094 &pStreamShared->State.Cfg.Props);
1095 AssertRC(rc2);
1096 }
1097
1098 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
1099 {
1100 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
1101 &pStreamShared->State.Cfg.Props);
1102 AssertRC(rc2);
1103 }
1104 }
1105 }
1106
1107 if (RT_SUCCESS(rc))
1108 {
1109 if (fEnable)
1110 pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
1111 pStreamShared->State.fRunning = fEnable;
1112
1113 /*
1114 * Set the FIFORDY bit when we start running and clear it when stopping.
1115 *
1116 * This prevents Linux from timing out in snd_hdac_stream_sync when starting
1117 * a stream. Technically, Linux also uses the SSYNC feature there, but we
1118 * can get away with just setting the FIFORDY bit for now.
1119 */
1120 if (fEnable)
1121 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_FIFORDY;
1122 else
1123 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1124 }
1125
1126 LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1127 return rc;
1128}
1129
1130/**
1131 * Marks the stream as started.
1132 *
1133 * Used after the stream has been enabled and the DMA timer has been armed.
1134 */
1135void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1136{
1137 pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1138 pStreamShared->State.tsStart = tsNow;
1139 Log3Func(("#%u: tsStart=%RU64 tsLastReadNs=%RU64\n",
1140 pStreamShared->u8SD, pStreamShared->State.tsStart, pStreamShared->State.tsLastReadNs));
1141 RT_NOREF(pDevIns, pThis);
1142}
1143
1144/**
1145 * Marks the stream as stopped.
1146 */
1147void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1148{
1149 Log3Func(("#%u\n", pStreamShared->u8SD));
1150 RT_NOREF(pStreamShared);
1151}
1152
1153#endif /* IN_RING3 */
1154#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1155
1156/**
1157 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1158 * setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1159 *
1160 * @param pStreamShared HDA stream to update read / write position for (shared).
1161 * @param pDevIns The device instance.
1162 * @param pThis The shared HDA device state.
1163 * @param uLPIB Absolute position (in bytes) to set current read / write position to.
1164 */
1165static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1166{
1167 AssertPtrReturnVoid(pStreamShared);
1168 AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1169
1170 Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1171
1172 /* Update LPIB in any case. */
1173 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1174
1175 /* Do we need to tell the current DMA position? */
1176 if (pThis->fDMAPosition)
1177 {
1178 /*
1179 * Linux switched to using the position buffers some time during 2.6.x.
1180 * 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1181 * the two version things were being changing quite a bit.
1182 *
1183 * Since 2.6.17, they will treat a zero DMA position value during the first
1184 * period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1185 * 2.6.27+, and azx_pcm_pointer before that). They later also added
1186 * UINT32_MAX to the values causing same.
1187 *
1188 * Since 2.6.35 azx_position_ok will read the wall clock register before
1189 * determining the position.
1190 */
1191 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1192 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1193 (void *)&uLPIB, sizeof(uint32_t));
1194 AssertRC(rc2);
1195 }
1196}
1197
1198
1199/**
1200 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1201 * adding a value to its associated LPIB register and DMA position buffer (if enabled).
1202 *
1203 * @note Handles automatic CBL wrap-around.
1204 *
1205 * @param pStreamShared HDA stream to update read / write position for (shared).
1206 * @param pDevIns The device instance.
1207 * @param pThis The shared HDA device state.
1208 * @param cbToAdd Position (in bytes) to add to the current read / write position.
1209 */
1210static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1211{
1212 if (cbToAdd) /* No need to update anything if 0. */
1213 {
1214 uint32_t const uCBL = pStreamShared->u32CBL;
1215 if (uCBL) /* paranoia */
1216 {
1217 uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1218# if 1 /** @todo r=bird: this is wrong according to the spec */
1219 uNewLpid %= uCBL;
1220# else
1221 /* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1222 if (uNewLpid > uCBL)
1223 uNewLpid %= uCBL;
1224# endif
1225 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1226 }
1227 }
1228}
1229
1230#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1231#ifdef IN_RING3
1232
1233/**
1234 * Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1235 *
1236 * @returns Available data (in bytes).
1237 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1238 */
1239static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1240{
1241 AssertPtrReturn(pStreamR3, 0);
1242
1243 if (pStreamR3->State.pCircBuf)
1244 return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1245 return 0;
1246}
1247
1248/**
1249 * Retrieves the free size of audio data (in bytes) of a given HDA stream.
1250 *
1251 * @returns Free data (in bytes).
1252 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1253 */
1254static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1255{
1256 AssertPtrReturn(pStreamR3, 0);
1257
1258 if (pStreamR3->State.pCircBuf)
1259 return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1260 return 0;
1261}
1262
1263#endif /* IN_RING3 */
1264#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1265
1266/**
1267 * Get the current address and number of bytes left in the current BDLE.
1268 *
1269 * @returns The current physical address.
1270 * @param pStreamShared The stream to check.
1271 * @param pcbLeft The number of bytes left at the returned address.
1272 */
1273DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1274{
1275 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1276 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1277
1278 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1279 uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1280 AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1281
1282 *pcbLeft = cbCurBdl - offCurBdle;
1283 return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1284}
1285
1286/**
1287 * Checks if the current BDLE is completed.
1288 *
1289 * @retval true if complete
1290 * @retval false if not.
1291 * @param pStreamShared The stream to check.
1292 */
1293DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1294{
1295 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1296 AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1297
1298 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1299 uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1300 Assert(offCurBdle <= cbCurBdl);
1301 return offCurBdle >= cbCurBdl;
1302}
1303
1304/**
1305 * Checks if the current BDLE needs a completion IRQ.
1306 *
1307 * @retval true if IRQ is needed.
1308 * @retval false if not.
1309 * @param pStreamShared The stream to check.
1310 */
1311DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1312{
1313 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1314 AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1315 return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1316}
1317
1318/**
1319 * Advances the DMA engine to the next BDLE.
1320 *
1321 * @param pStreamShared The stream which DMA engine is to be updated.
1322 */
1323DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1324{
1325 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1326 Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1327
1328 if (idxBdle < pStreamShared->State.cBdles - 1)
1329 idxBdle++;
1330 else
1331 idxBdle = 0;
1332 pStreamShared->State.idxCurBdle = idxBdle;
1333 pStreamShared->State.offCurBdle = 0;
1334}
1335
1336#endif /* defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA) */
1337#ifdef IN_RING3
1338
1339/**
1340 * Common do-DMA prologue code.
1341 *
1342 * @retval true if DMA processing can take place
1343 * @retval false if caller should return immediately.
1344 * @param pThis The shared HDA device state.
1345 * @param pStreamShared HDA stream to update (shared).
1346 * @param pStreamR3 HDA stream to update (ring-3).
1347 * @param uSD The stream ID (for asserting).
1348 * @param tsNowNs The current RTTimeNano() value.
1349 * @param pszFunction The function name (for logging).
1350 */
1351DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1352 uint64_t tsNowNs, const char *pszFunction)
1353{
1354 RT_NOREF(uSD, pszFunction);
1355
1356 /*
1357 * Check if we should skip town...
1358 */
1359 /* Stream not running (anymore)? */
1360 if (pStreamShared->State.fRunning)
1361 { /* likely */ }
1362 else
1363 {
1364 Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1365 return false;
1366 }
1367
1368 if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1369 { /* likely */ }
1370 else
1371 {
1372 /** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1373 * the transfer immediately after the guest clears the interrupt.
1374 * The same fishy code is present in AC'97 with just a little
1375 * explanation as here, see @bugref{9890#c95}.
1376 *
1377 * The reasoning is probably that the developer noticed some windows
1378 * versions don't like having their BCIS interrupts bundled. There were
1379 * comments to that effect elsewhere, probably as a result of a fixed
1380 * uTimerHz approach to DMA scheduling. However, pausing DMA for a
1381 * period isn't going to help us with the host backends, as they don't
1382 * pause and will want samples ASAP. So, we should at least unpause
1383 * DMA as quickly as we possible when BCIS is cleared. We might even
1384 * not skip it iff the DMA work here doesn't involve raising any IOC,
1385 * which is possible although unlikely. */
1386 Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1387 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1388 Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1389# ifdef HDA_STRICT
1390 /* Timing emulation bug or guest is misbehaving -- let me know. */
1391 AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1392# endif
1393 return false;
1394 }
1395
1396 /*
1397 * Stream sanity checks.
1398 */
1399 /* Register sanity checks. */
1400 Assert(uSD < HDA_MAX_STREAMS);
1401 Assert(pStreamShared->u64BDLBase);
1402 Assert(pStreamShared->u32CBL);
1403 Assert(pStreamShared->u8FIFOS);
1404
1405 /* State sanity checks. */
1406 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1407 Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1408
1409 /*
1410 * Some timestamp stuff for logging/debugging.
1411 */
1412 /*const uint64_t tsNowNs = RTTimeNanoTS();*/
1413 Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1414 pStreamShared->State.tsLastTransferNs = tsNowNs;
1415
1416 return true;
1417}
1418
1419/**
1420 * Common do-DMA epilogue.
1421 *
1422 * @param pDevIns The device instance.
1423 * @param pStreamShared The HDA stream (shared).
1424 * @param pStreamR3 The HDA stream (ring-3).
1425 */
1426DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1427{
1428 /*
1429 * We must update this in the epilogue rather than in the prologue
1430 * as it is used for WALCLK calculation and we must make sure the
1431 * guest doesn't think we've processed the current period till we
1432 * actually have.
1433 */
1434 pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1435
1436 /*
1437 * Update the buffer statistics.
1438 */
1439 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1440}
1441
1442#endif /* IN_RING3 */
1443
1444#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1445/**
1446 * Completes a BDLE at the end of a DMA loop iteration, if possible.
1447 *
1448 * @retval true if buffer completed and new loaded.
1449 * @retval false if buffer not completed.
1450 * @param pDevIns The device instance.
1451 * @param pThis The shared HDA device state.
1452 * @param pStreamShared HDA stream to update (shared).
1453 * @param pszFunction The function name (for logging).
1454 */
1455DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1456 PHDASTREAM pStreamShared, const char *pszFunction)
1457{
1458 RT_NOREF(pszFunction);
1459
1460 /*
1461 * Is the buffer descriptor complete.
1462 */
1463 if (hdaStreamDmaBufIsComplete(pStreamShared))
1464 {
1465 Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1466 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1467 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1468 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1469
1470 /* Does the current BDLE require an interrupt to be sent? */
1471 if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1472 {
1473 /* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1474 register is set we need to generate an interrupt. */
1475 if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1476 {
1477 /* Assert the interrupt before actually fetching the next BDLE below. */
1478 pStreamShared->State.cTransferPendingInterrupts = 1;
1479 Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1480
1481 /* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1482 * ending / beginning of a period. */
1483 /** @todo r=bird: What does the above comment mean? */
1484 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_BCIS;
1485 HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1486 }
1487 }
1488
1489 /*
1490 * Advance to the next BDLE.
1491 */
1492 hdaStreamDmaBufAdvanceToNext(pStreamShared);
1493 return true;
1494 }
1495
1496 Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1497 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1498 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1499 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1500 return false;
1501}
1502#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1503
1504#ifdef IN_RING3
1505
1506/**
1507 * Does DMA transfer for an HDA input stream.
1508 *
1509 * Reads audio data from the HDA stream's internal DMA buffer and writing to
1510 * guest memory.
1511 *
1512 * @param pDevIns The device instance.
1513 * @param pThis The shared HDA device state.
1514 * @param pStreamShared HDA stream to update (shared).
1515 * @param pStreamR3 HDA stream to update (ring-3).
1516 * @param cbToConsume The max amount of data to consume from the
1517 * internal DMA buffer. The caller will make sure
1518 * this is always the transfer size fo the current
1519 * period (unless something is seriously wrong).
1520 * @param fWriteSilence Whether to feed the guest silence rather than
1521 * fetching bytes from the internal DMA buffer.
1522 * This is set initially while we pre-buffer a
1523 * little bit of input, so we can better handle
1524 * time catch-ups and other schduling fun.
1525 * @param tsNowNs The current RTTimeNano() value.
1526 *
1527 * @remarks Caller owns the stream lock.
1528 */
1529static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1530 PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1531{
1532 uint8_t const uSD = pStreamShared->u8SD;
1533 LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1534
1535 /*
1536 * Common prologue.
1537 */
1538 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1539 { /* likely */ }
1540 else
1541 return;
1542
1543 /*
1544 *
1545 * The DMA copy loop.
1546 *
1547 * Note! Unaligned BDLEs shouldn't be a problem since the circular buffer
1548 * doesn't care about alignment. Only, we have to read the rest
1549 * of the incomplete frame from it ASAP.
1550 */
1551 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1552 uint32_t cbLeft = cbToConsume;
1553 Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1554 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1555
1556 while (cbLeft > 0)
1557 {
1558 STAM_PROFILE_START(&pThis->StatIn, a);
1559
1560 /*
1561 * Figure out how much we can read & write in this iteration.
1562 */
1563 uint32_t cbChunk = 0;
1564 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1565
1566 if (cbChunk <= cbLeft)
1567 { /* very likely */ }
1568 else
1569 cbChunk = cbLeft;
1570
1571 uint32_t cbWritten = 0;
1572 if (!fWriteSilence)
1573 {
1574 /*
1575 * Write the host data directly into the guest buffers.
1576 */
1577 while (cbChunk > 0)
1578 {
1579 /* Grab internal DMA buffer space and read into it. */
1580 void /*const*/ *pvBufSrc;
1581 size_t cbBufSrc;
1582 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1583 AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1584
1585 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1586 AssertRC(rc2);
1587
1588# ifdef HDA_DEBUG_SILENCE
1589 fix me if relevant;
1590# endif
1591 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.pFileDMARaw))
1592 { /* likely */ }
1593 else
1594 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc);
1595
1596# ifdef VBOX_WITH_DTRACE
1597 VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1598# endif
1599 pStreamShared->State.offRead += cbBufSrc;
1600 RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1601 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1602
1603 /* advance */
1604 cbChunk -= (uint32_t)cbBufSrc;
1605 cbWritten += (uint32_t)cbBufSrc;
1606 GCPhys += cbBufSrc;
1607 pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1608 }
1609 }
1610 /*
1611 * Write silence. Since we only do signed formats, we can use the zero
1612 * buffers from IPRT as source here.
1613 */
1614 else
1615 {
1616 Assert(PDMAudioPropsIsSigned(&pStreamShared->State.Cfg.Props));
1617 while (cbChunk > 0)
1618 {
1619 /* Write it to the guest buffer. */
1620 uint32_t cbToWrite = RT_MIN(sizeof(g_abRTZero64K), cbChunk);
1621 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, g_abRTZero64K, cbToWrite);
1622 AssertRC(rc2);
1623 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbToWrite);
1624
1625 /* advance */
1626 cbWritten += cbToWrite;
1627 cbChunk -= cbToWrite;
1628 GCPhys += cbToWrite;
1629 pStreamShared->State.offCurBdle += cbToWrite;
1630 }
1631 }
1632
1633 cbLeft -= cbWritten;
1634 STAM_PROFILE_STOP(&pThis->StatIn, a);
1635
1636 /*
1637 * Complete the buffer if necessary (common with the output DMA code).
1638 *
1639 * Must update the DMA position before we do this as the buffer IRQ may
1640 * fire on another vCPU and run in parallel to us, although it is very
1641 * unlikely it can make much progress as long as we're sitting on the
1642 * lock, it could still read the DMA position (Linux won't, as it reads
1643 * WALCLK and possibly SDnSTS before the DMA position).
1644 */
1645 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1646 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1647 }
1648
1649 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1650
1651 /*
1652 * Common epilogue.
1653 */
1654 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1655
1656 /*
1657 * Log and leave.
1658 */
1659 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1660 uSD, cbToConsume, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offRead - cbToConsume,
1661 pStreamShared->State.cTransferPendingInterrupts));
1662}
1663
1664
1665/**
1666 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1667 * buffer.
1668 *
1669 * @param pStreamShared HDA stream to update (shared).
1670 * @param pStreamR3 HDA stream to update (ring-3 bits).
1671 * @param pSink The mixer sink to pull from.
1672 */
1673static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1674{
1675# ifdef LOG_ENABLED
1676 uint64_t const offWriteOld = pStreamShared->State.offWrite;
1677# endif
1678 pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1679 pStreamR3->State.pCircBuf,
1680 pStreamShared->State.offWrite,
1681 pStreamR3->u8SD,
1682 pStreamR3->Dbg.Runtime.fEnabled
1683 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1684
1685 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1686 pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1687
1688 /* Update buffer stats. */
1689 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1690}
1691
1692
1693/**
1694 * Does DMA transfer for an HDA output stream.
1695 *
1696 * This transfers one DMA timer period worth of data from the guest and into the
1697 * internal DMA buffer.
1698 *
1699 * @param pDevIns The device instance.
1700 * @param pThis The shared HDA device state.
1701 * @param pStreamShared HDA stream to update (shared).
1702 * @param pStreamR3 HDA stream to update (ring-3).
1703 * @param cbToProduce The max amount of data to produce (i.e. put into
1704 * the circular buffer). Unless something is going
1705 * seriously wrong, this will always be transfer
1706 * size for the current period.
1707 * @param tsNowNs The current RTTimeNano() value.
1708 *
1709 * @remarks Caller owns the stream lock.
1710 */
1711static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1712 PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1713{
1714 uint8_t const uSD = pStreamShared->u8SD;
1715 LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1716
1717 /*
1718 * Common prologue.
1719 */
1720 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1721 { /* likely */ }
1722 else
1723 return;
1724
1725 /*
1726 *
1727 * The DMA copy loop.
1728 *
1729 * Note! Unaligned BDLEs shouldn't be a problem since the circular buffer
1730 * doesn't care about alignment. Only, we have to write the rest
1731 * of the incomplete frame to it ASAP.
1732 */
1733 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1734 uint32_t cbLeft = cbToProduce;
1735# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1736 Assert(cbLeft <= pStreamShared->State.cbCurDmaPeriod); /* a little pointless with the DMA'ing on LPIB read. */
1737# else
1738 Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1739# endif
1740 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1741
1742 while (cbLeft > 0)
1743 {
1744 STAM_PROFILE_START(&pThis->StatOut, a);
1745
1746 /*
1747 * Figure out how much we can read & write in this iteration.
1748 */
1749 uint32_t cbChunk = 0;
1750 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1751
1752 if (cbChunk <= cbLeft)
1753 { /* very likely */ }
1754 else
1755 cbChunk = cbLeft;
1756
1757 /*
1758 * Read the guest data directly into the internal DMA buffer.
1759 */
1760 uint32_t cbRead = 0;
1761 while (cbChunk > 0)
1762 {
1763 /* Grab internal DMA buffer space and read into it. */
1764 void *pvBufDst;
1765 size_t cbBufDst;
1766 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1767 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1768
1769 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1770 AssertRC(rc2);
1771
1772# ifdef HDA_DEBUG_SILENCE
1773 fix me if relevant;
1774# endif
1775 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.pFileDMARaw))
1776 { /* likely */ }
1777 else
1778 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst);
1779
1780# ifdef VBOX_WITH_DTRACE
1781 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1782# endif
1783 pStreamShared->State.offWrite += cbBufDst;
1784 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1785 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1786
1787 /* advance */
1788 cbChunk -= (uint32_t)cbBufDst;
1789 cbRead += (uint32_t)cbBufDst;
1790 GCPhys += cbBufDst;
1791 pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1792 }
1793
1794 cbLeft -= cbRead;
1795 STAM_PROFILE_STOP(&pThis->StatOut, a);
1796
1797 /*
1798 * Complete the buffer if necessary (common with the input DMA code).
1799 *
1800 * Must update the DMA position before we do this as the buffer IRQ may
1801 * fire on another vCPU and run in parallel to us, although it is very
1802 * unlikely it can make much progress as long as we're sitting on the
1803 * lock, it could still read the DMA position (Linux won't, as it reads
1804 * WALCLK and possibly SDnSTS before the DMA position).
1805 */
1806 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1807 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1808 }
1809
1810 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1811
1812 /*
1813 * Common epilogue.
1814 */
1815 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1816
1817 /*
1818 * Log and leave.
1819 */
1820 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1821 uSD, cbToProduce, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offWrite - cbToProduce,
1822 pStreamShared->State.cTransferPendingInterrupts));
1823}
1824
1825#endif /* IN_RING3 */
1826#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1827
1828/**
1829 * Do DMA output transfer on LPIB/WALCLK register access.
1830 *
1831 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1832 * @param pDevIns The device instance.
1833 * @param pThis The shared instance data.
1834 * @param pStreamShared The shared stream data.
1835 * @param tsNow The current time on the timer clock.
1836 * @param cbToTransfer How much to transfer.
1837 */
1838VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1839 uint64_t tsNow, uint32_t cbToTransfer)
1840{
1841 AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1842 int rc = VINF_SUCCESS;
1843
1844 /*
1845 * Check if we're exceeding the available buffer, go to ring-3 to
1846 * handle that (we would perhaps always take this path when in ring-3).
1847 */
1848 uint32_t cbDma = pStreamShared->State.cbDma;
1849 ASMCompilerBarrier();
1850 if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1851 || cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1852 || cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1853 {
1854# ifndef IN_RING3
1855 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1856 LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1857 pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1858 return VINF_IOM_R3_MMIO_READ;
1859# else /* IN_RING3 */
1860 /*
1861 * Flush the bounce buffer, then do direct transfers to the
1862 * internal DMA buffer (updates LPIB).
1863 */
1864 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1865 uintptr_t const idxStream = pStreamShared->u8SD;
1866 AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1867 PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1868
1869 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1870
1871 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1872 if (cbStreamFree >= cbToTransfer)
1873 { /* likely */ }
1874 else
1875 {
1876 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1877 if (pSink)
1878 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1879 "hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1880 else
1881 {
1882 LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1883 pStreamShared->u8SD, cbStreamFree));
1884 return VINF_SUCCESS;
1885 }
1886 cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1887 if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1888 {
1889 LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1890 return VINF_SUCCESS;
1891 }
1892 }
1893 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1894 pStreamShared->State.cbDmaTotal += cbToTransfer;
1895# endif /* IN_RING3 */
1896 }
1897 else
1898 {
1899 /*
1900 * Transfer into the DMA bounce buffer.
1901 */
1902 LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1903 pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1904 uint32_t cbLeft = cbToTransfer;
1905 do
1906 {
1907 uint32_t cbChunk = 0;
1908 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1909
1910 bool fMustAdvanceBuffer;
1911 if (cbLeft < cbChunk)
1912 {
1913 fMustAdvanceBuffer = false;
1914 cbChunk = cbLeft;
1915 }
1916 else
1917 fMustAdvanceBuffer = true;
1918
1919 /* Read the guest data directly into the DMA bounce buffer. */
1920 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1921 AssertRC(rc2);
1922
1923 /* We update offWrite and StatBytesRead here even if we haven't moved the data
1924 to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1925# ifdef VBOX_WITH_DTRACE
1926 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1927# endif
1928 pStreamShared->State.offWrite += cbChunk;
1929 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1930
1931 /* advance */
1932 pStreamShared->State.offCurBdle += cbChunk;
1933 pStreamShared->State.cbDmaTotal += cbChunk;
1934 cbDma += cbChunk;
1935 pStreamShared->State.cbDma = cbDma;
1936 cbLeft -= cbChunk;
1937 Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1938 cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1939 pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1940
1941 /* Next buffer. */
1942 bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1943 AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1944 } while (cbLeft > 0);
1945
1946 /*
1947 * Advance LPIB and update the last transfer time (for WALCLK).
1948 */
1949 pStreamShared->State.tsTransferLast = tsNow;
1950 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
1951 }
1952
1953# ifdef VBOX_STRICT
1954 uint32_t idxSched = pStreamShared->State.idxSchedule;
1955 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
1956 uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1957 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1958# endif
1959
1960 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
1961 return rc;
1962}
1963
1964
1965/**
1966 * Consider doing DMA output transfer on LPIB/WALCLK register access.
1967 *
1968 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1969 * @param pDevIns The device instance.
1970 * @param pThis The shared instance data.
1971 * @param pStreamShared The shared stream data.
1972 * @param tsNow The current time on the timer clock. Used to do the
1973 * calculation.
1974 */
1975VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1976{
1977 Assert(pStreamShared->State.fRunning); /* caller should check this */
1978
1979 /*
1980 * Calculate where the DMA engine should be according to the clock, if we can.
1981 */
1982 uint32_t const cbFrame = PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props);
1983 uint32_t const cbPeriod = pStreamShared->State.cbCurDmaPeriod;
1984 if (cbPeriod > cbFrame)
1985 {
1986 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1987 uint64_t const tsTransferNext = pStreamShared->State.tsTransferNext;
1988 uint32_t cbFuture;
1989 if (tsNow < tsTransferNext)
1990 {
1991 /** @todo ASSUMES nanosecond clock ticks, need to make this
1992 * resolution independent. */
1993 cbFuture = PDMAudioPropsNanoToBytes(&pStreamShared->State.Cfg.Props, tsTransferNext - tsNow);
1994 cbFuture = RT_MIN(cbFuture, cbPeriod - cbFrame);
1995 }
1996 else
1997 {
1998 /* We've hit/overshot the timer deadline. Return to ring-3 if we're
1999 not already there to increase the chance that we'll help expidite
2000 the timer. If we're already in ring-3, do all but the last frame. */
2001# ifndef IN_RING3
2002 LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> VINF_IOM_R3_MMIO_READ\n",
2003 tsNow, tsTransferNext));
2004 return VINF_IOM_R3_MMIO_READ;
2005# else
2006 cbFuture = cbPeriod - cbFrame;
2007 LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> cbFuture=%#x (cbPeriod=%#x - cbFrame=%#x)\n",
2008 tsNow, tsTransferNext, cbFuture, cbPeriod, cbFrame));
2009# endif
2010 }
2011 uint32_t const offNow = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbPeriod - cbFuture);
2012
2013 /*
2014 * Should we transfer a little? Minimum is 64 bytes (semi-random,
2015 * suspect real hardware might be doing some cache aligned stuff,
2016 * which might soon get complicated if you take unaligned buffers
2017 * into consideration and which cache line size (128 bytes is just
2018 * as likely as 64 or 32 bytes)).
2019 */
2020 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2021 if (cbDmaTotal + 64 <= offNow)
2022 {
2023# ifdef LOG_ENABLED
2024 uint32_t const uOldLpib = HDA_STREAM_REG(pThis, CBL, pStreamShared->u8SD);
2025# endif
2026 VBOXSTRICTRC rcStrict = hdaStreamDoOnAccessDmaOutput(pDevIns, pThis, pStreamShared, tsNow, offNow - cbDmaTotal);
2027 LogFlowFunc(("[SD%RU8] LPIB=%#RX32 -> LPIB=%#RX32 offNow=%#x rcStrict=%Rrc\n", pStreamShared->u8SD,
2028 uOldLpib, HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD), offNow, VBOXSTRICTRC_VAL(rcStrict) ));
2029 return rcStrict;
2030 }
2031
2032 /*
2033 * Do nothing.
2034 */
2035 LogFlowFunc(("[SD%RU8] Skipping DMA transfer: cbDmaTotal=%#x offNow=%#x\n", pStreamShared->u8SD, cbDmaTotal, offNow));
2036 }
2037 else
2038 LogFunc(("[SD%RU8] cbPeriod=%#x <= cbFrame=%#x\n", pStreamShared->u8SD, cbPeriod, cbFrame));
2039 return VINF_SUCCESS;
2040}
2041
2042#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2043#ifdef IN_RING3
2044
2045/**
2046 * Output streams: Pushes data to the mixer.
2047 *
2048 * @param pStreamShared HDA stream to update (shared bits).
2049 * @param pStreamR3 HDA stream to update (ring-3 bits).
2050 * @param pSink The mixer sink to push to.
2051 * @param nsNow The current RTTimeNanoTS() value.
2052 */
2053static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
2054{
2055# ifdef LOG_ENABLED
2056 uint64_t const offReadOld = pStreamShared->State.offRead;
2057# endif
2058 pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
2059 pStreamR3->State.pCircBuf,
2060 pStreamShared->State.offRead,
2061 pStreamR3->u8SD,
2062 pStreamR3->Dbg.Runtime.fEnabled
2063 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
2064
2065 Assert(nsNow >= pStreamShared->State.tsLastReadNs);
2066 Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
2067 nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
2068 RT_NOREF(pStreamShared, nsNow);
2069
2070 /* Update buffer stats. */
2071 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
2072}
2073
2074
2075/**
2076 * Deals with a DMA buffer overrun.
2077 *
2078 * Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
2079 *
2080 * @returns Number of bytes free in the internal DMA buffer.
2081 * @param pStreamShared The shared data for the HDA stream.
2082 * @param pStreamR3 The ring-3 data for the HDA stream.
2083 * @param pSink The mixer sink (valid).
2084 * @param cbNeeded How much space we need (in bytes).
2085 * @param nsNow Current RTNanoTimeTS() timestamp.
2086 * @param cbStreamFree The current amount of free buffer space.
2087 * @param pszCaller The caller (for logging).
2088 */
2089static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
2090 uint32_t cbNeeded, uint64_t nsNow,
2091 const char *pszCaller, uint32_t const cbStreamFree)
2092{
2093 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2094 Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
2095 pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
2096 RT_NOREF(pszCaller, cbStreamFree);
2097
2098 int rc = AudioMixerSinkTryLock(pSink);
2099 if (RT_SUCCESS(rc))
2100 {
2101 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
2102 AudioMixerSinkUpdate(pSink, 0, 0);
2103 AudioMixerSinkUnlock(pSink);
2104 }
2105 else
2106 RTThreadYield();
2107
2108 uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
2109 Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
2110 if (cbRet >= cbNeeded)
2111 return cbRet;
2112
2113 /*
2114 * Unable to make sufficient space. Drop the whole buffer content.
2115 *
2116 * This is needed in order to keep the device emulation running at a
2117 * constant rate, at the cost of losing valid (but too much) data.
2118 */
2119 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2120 LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
2121 pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
2122# ifdef HDA_STRICT
2123 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2124# endif
2125/**
2126 *
2127 * @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2128 * owning the AIO lock. See the note in the documentation about it not being
2129 * multi-threading aware (safe). Wish I'd verified this code much earlier.
2130 * Sigh^3!
2131 *
2132 */
2133 RTCircBufReset(pStreamR3->State.pCircBuf);
2134 pStreamShared->State.offWrite = 0;
2135 pStreamShared->State.offRead = 0;
2136 return hdaR3StreamGetFree(pStreamR3);
2137}
2138
2139
2140# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2141/**
2142 * Flushes the DMA bounce buffer content to the internal DMA buffer.
2143 *
2144 * @param pStreamShared The shared data of the stream to have its DMA bounce
2145 * buffer flushed.
2146 * @param pStreamR3 The ring-3 stream data for same.
2147 */
2148static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2149{
2150 uint32_t cbDma = pStreamShared->State.cbDma;
2151 LogFlowFunc(("cbDma=%#x\n", cbDma));
2152 if (cbDma)
2153 {
2154 AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2155 PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2156 if (pCircBuf)
2157 {
2158 uint32_t offDma = 0;
2159 while (offDma < cbDma)
2160 {
2161 uint32_t const cbSrcLeft = cbDma - offDma;
2162
2163 /*
2164 * Grab a chunk of the internal DMA buffer.
2165 */
2166 void *pvBufDst = NULL;
2167 size_t cbBufDst = 0;
2168 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2169 if (cbBufDst > 0)
2170 { /* likely */ }
2171 else
2172 {
2173 /* We've got buffering trouble. */
2174 RTCircBufReleaseWriteBlock(pCircBuf, 0);
2175
2176 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2177 if (pSink)
2178 hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2179 "hdaR3StreamFlushDmaBounceBufferOutput", 0 /*cbStreamFree*/);
2180 else
2181 {
2182 LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2183 break;
2184 }
2185
2186 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2187 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2188 }
2189
2190 /*
2191 * Copy the samples into it and write it to the debug file if open.
2192 *
2193 * We do not fire the dtrace probe here nor update offRead as that was
2194 * done already (not sure that was a good idea?).
2195 */
2196 memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2197
2198 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.pFileDMARaw))
2199 { /* likely */ }
2200 else
2201 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst);
2202
2203 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2204
2205 offDma += (uint32_t)cbBufDst;
2206 }
2207 }
2208
2209 /*
2210 * Mark the buffer empty.
2211 */
2212 pStreamShared->State.cbDma = 0;
2213 }
2214}
2215# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2216
2217
2218/**
2219 * The stream's main function when called by the timer.
2220 *
2221 * @note This function also will be called without timer invocation when
2222 * starting (enabling) the stream to minimize startup latency.
2223 *
2224 * @returns Current timer time if the timer is enabled, otherwise zero.
2225 * @param pDevIns The device instance.
2226 * @param pThis The shared HDA device state.
2227 * @param pThisCC The ring-3 HDA device state.
2228 * @param pStreamShared HDA stream to update (shared bits).
2229 * @param pStreamR3 HDA stream to update (ring-3 bits).
2230 */
2231uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2232 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2233{
2234 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2235 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2236
2237 /* Do the work: */
2238 hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2239
2240 /* Re-arm the timer if the sink is still active: */
2241 if ( pStreamShared->State.fRunning
2242 && pStreamR3->pMixSink
2243 && AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2244 {
2245 /* Advance the schduling: */
2246 uint32_t idxSched = pStreamShared->State.idxSchedule;
2247 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2248 uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2249 if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2250 {
2251 idxSched += 1;
2252 if ( idxSched >= pStreamShared->State.cSchedule
2253 || idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /*paranoia^2*/)
2254 {
2255 idxSched = pStreamShared->State.cSchedulePrologue;
2256 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2257 }
2258 pStreamShared->State.idxSchedule = idxSched;
2259 idxLoop = 0;
2260 }
2261 pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2262
2263 /* Do the actual timer re-arming. */
2264 uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2265 uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2266 Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2267 pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2268 int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2269 AssertRC(rc);
2270
2271 /* Some legacy stuff: */
2272 pStreamShared->State.tsTransferNext = tsTransferNext;
2273 pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2274
2275 return tsNow;
2276 }
2277
2278 Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2279 return 0;
2280}
2281
2282
2283/**
2284 * Updates a HDA stream by doing DMA transfers.
2285 *
2286 * Will do mixer transfers too to try fix an overrun/underrun situation.
2287 *
2288 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2289 * does - we just hope like heck it matches the speed at which the *backend*
2290 * host audio driver processes samples).
2291 *
2292 * @param pDevIns The device instance.
2293 * @param pThis The shared HDA device state.
2294 * @param pThisCC The ring-3 HDA device state.
2295 * @param pStreamShared HDA stream to update (shared bits).
2296 * @param pStreamR3 HDA stream to update (ring-3 bits).
2297 */
2298static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2299 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2300{
2301 RT_NOREF(pThisCC);
2302 int rc2;
2303
2304 /*
2305 * Make sure we're running and got an active mixer sink.
2306 */
2307 if (RT_LIKELY(pStreamShared->State.fRunning))
2308 { /* likely */ }
2309 else
2310 return;
2311
2312 PAUDMIXSINK pSink = NULL;
2313 if (pStreamR3->pMixSink)
2314 pSink = pStreamR3->pMixSink->pMixSink;
2315 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2316 { /* likely */ }
2317 else
2318 return;
2319
2320 /*
2321 * Get scheduling info common to both input and output streams.
2322 */
2323 const uint64_t tsNowNs = RTTimeNanoTS();
2324 uint32_t idxSched = pStreamShared->State.idxSchedule;
2325 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2326 uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2327
2328 /*
2329 * Output streams (SDO).
2330 */
2331 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2332 {
2333# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2334 /* Subtract already transferred bytes and flush the DMA bounce buffer. */
2335 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2336 if (cbDmaTotal > 0)
2337 {
2338 AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2339 cbPeriod -= cbDmaTotal;
2340 pStreamShared->State.cbDmaTotal = 0;
2341 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2342 }
2343 else
2344 Assert(pStreamShared->State.cbDma == 0);
2345# endif
2346
2347 /*
2348 * Check how much room we have in our DMA buffer. There should be at
2349 * least one period worth of space there or we're in an overflow situation.
2350 */
2351 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2352 if (cbStreamFree >= cbPeriod)
2353 { /* likely */ }
2354 else
2355 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2356 "hdaR3StreamUpdateDma", cbStreamFree);
2357
2358 /*
2359 * Do the DMA transfer.
2360 */
2361 uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2362 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2363
2364 /*
2365 * Should we push data to down thru the mixer to and to the host drivers?
2366 */
2367 bool fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2368 || hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2369
2370 Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2371 (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2372 pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2373 pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2374
2375 if (fKickAioThread)
2376 {
2377 /* Notify the async I/O worker thread that there's work to do. */
2378 Log5Func(("Notifying AIO thread\n"));
2379 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2380 AssertRC(rc2);
2381 /* Update last read timestamp for logging/debugging. */
2382 pStreamShared->State.tsLastReadNs = tsNowNs;
2383 }
2384 }
2385 /*
2386 * Input stream (SDI).
2387 */
2388 else
2389 {
2390 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2391
2392 /*
2393 * See how much data we've got buffered...
2394 */
2395 bool fWriteSilence = false;
2396 uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2397 if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2398 { /*likely*/ }
2399 /*
2400 * Because it may take a while for the input stream to get going (at
2401 * least with pulseaudio), we feed the guest silence till we've
2402 * pre-buffer a reasonable amount of audio.
2403 */
2404 else if (!pStreamShared->State.fInputPreBuffered)
2405 {
2406 if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2407 {
2408 Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2409 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2410 fWriteSilence = true;
2411 }
2412 else
2413 {
2414 Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2415 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2416 pStreamShared->State.fInputPreBuffered = true;
2417 fWriteSilence = true; /* For now, just do the most conservative thing. */
2418 }
2419 cbStreamUsed = cbPeriod;
2420 }
2421 /*
2422 * When we're low on data, we must really try fetch some ourselves
2423 * as buffer underruns must not happen.
2424 */
2425 else
2426 {
2427 /** @todo We're ending up here to frequently with pulse audio at least (just
2428 * watch the stream stats in the statistcs viewer, and way to often we
2429 * have to inject silence bytes. I suspect part of the problem is
2430 * that the HDA device require a much better latency than what the
2431 * pulse audio is configured for by default (10 ms vs 150ms). */
2432 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2433 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2434 pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2435 int rc = AudioMixerSinkTryLock(pSink);
2436 if (RT_SUCCESS(rc))
2437 {
2438 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2439 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2440 AudioMixerSinkUnlock(pSink);
2441 }
2442 else
2443 RTThreadYield();
2444 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2445 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2446 if (cbStreamUsed < cbPeriod)
2447 {
2448 /* Unable to find sufficient input data by simple prodding.
2449 In order to keep a constant byte stream following thru the DMA
2450 engine into the guest, we will try again and then fall back on
2451 filling the gap with silence. */
2452 uint32_t cbSilence = 0;
2453 do
2454 {
2455 AudioMixerSinkLock(pSink);
2456
2457 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2458 if (cbStreamUsed < cbPeriod)
2459 {
2460 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2461 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2462 while (cbStreamUsed < cbPeriod)
2463 {
2464 void *pvDstBuf;
2465 size_t cbDstBuf;
2466 RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2467 &pvDstBuf, &cbDstBuf);
2468 RT_BZERO(pvDstBuf, cbDstBuf);
2469 RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2470 cbSilence += (uint32_t)cbDstBuf;
2471 cbStreamUsed += (uint32_t)cbDstBuf;
2472 }
2473 }
2474
2475 AudioMixerSinkUnlock(pSink);
2476 } while (cbStreamUsed < cbPeriod);
2477 if (cbSilence > 0)
2478 {
2479 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2480 STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2481 LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2482 cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2483 }
2484 }
2485 }
2486
2487 /*
2488 * Do the DMA'ing.
2489 */
2490 if (cbStreamUsed)
2491 hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2492 RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2493
2494 /*
2495 * We should always kick the AIO thread.
2496 */
2497 /** @todo This isn't entirely ideal. If we get into an underrun situation,
2498 * we ideally want the AIO thread to run right before the DMA timer
2499 * rather than right after it ran. */
2500 Log5Func(("Notifying AIO thread\n"));
2501 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2502 AssertRC(rc2);
2503 pStreamShared->State.tsLastReadNs = tsNowNs;
2504 }
2505}
2506
2507
2508/**
2509 * @callback_method_impl{FNAUDMIXSINKUPDATE}
2510 *
2511 * For output streams this moves data from the internal DMA buffer (in which
2512 * hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2513 * devices.
2514 *
2515 * For input streams this pulls data from the backend audio device(s), thru the
2516 * mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2517 * to pump into guest memory.
2518 */
2519DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2520{
2521 PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2522 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2523 PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2524 PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2525 Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2526 Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2527 RT_NOREF(pSink);
2528
2529 /*
2530 * Make sure we haven't change sink and that it's still active (it
2531 * should be or we wouldn't have been called).
2532 */
2533 AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2534 AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2535
2536 /*
2537 * Output streams (SDO).
2538 */
2539 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2540 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2541 /*
2542 * Input stream (SDI).
2543 */
2544 else
2545 {
2546 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2547 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2548 }
2549}
2550
2551#endif /* IN_RING3 */
2552
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use