VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaCommon.h@ 89765

Last change on this file since 89765 was 88235, checked in by vboxsync, 3 years ago

Audio: File header adjustments. bugref:9890
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 25.7 KB
Line 
1/* $Id: DevHdaCommon.h 88235 2021-03-22 10:44:43Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Common stuff.
4 *
5 * @todo r=bird: Wtf is this? Do we have some other HDA implementations
6 * that I'm not aware of that shares this code?
7 */
8
9/*
10 * Copyright (C) 2016-2020 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaCommon_h
22#define VBOX_INCLUDED_SRC_Audio_DevHdaCommon_h
23#ifndef RT_WITHOUT_PRAGMA_ONCE
24# pragma once
25#endif
26
27#include "AudioMixer.h"
28#include <VBox/log.h> /* LOG_ENABLED */
29
30/** Pointer to an HDA stream (SDI / SDO). */
31typedef struct HDASTREAMR3 *PHDASTREAMR3;
32
33
34
35/** Read callback. */
36typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
37/** Write callback. */
38typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
39
40/**
41 * HDA register descriptor.
42 *
43 * See 302349 p 6.2.
44 */
45typedef struct HDAREGDESC
46{
47 /** Register offset in the register space. */
48 uint32_t offset;
49 /** Size in bytes. Registers of size > 4 are in fact tables. */
50 uint32_t size;
51 /** Readable bits. */
52 uint32_t readable;
53 /** Writable bits. */
54 uint32_t writable;
55 /** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
56 * specify the handling (read/write) policy of the register. */
57 uint32_t fFlags;
58 /** Read callback. */
59 FNHDAREGREAD *pfnRead;
60 /** Write callback. */
61 FNHDAREGWRITE *pfnWrite;
62 /** Index into the register storage array. */
63 uint32_t mem_idx;
64 /** Abbreviated name. */
65 const char *abbrev;
66 /** Descripton. */
67 const char *desc;
68} HDAREGDESC;
69/** Pointer to a a const HDA register descriptor. */
70typedef HDAREGDESC const *PCHDAREGDESC;
71
72/**
73 * HDA register aliases (HDA spec 3.3.45).
74 * @remarks Sorted by offReg.
75 */
76typedef struct HDAREGALIAS
77{
78 /** The alias register offset. */
79 uint32_t offReg;
80 /** The register index. */
81 int idxAlias;
82} HDAREGALIAS;
83
84/**
85 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
86 * Bidirectional streams are currently *not* supported.
87 *
88 * Note: When changing any of those values, be prepared for some saved state
89 * fixups / trouble!
90 */
91#define HDA_MAX_SDI 4
92#define HDA_MAX_SDO 4
93#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
94AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
95
96/** Number of general registers. */
97#define HDA_NUM_GENERAL_REGS 34
98/** Number of total registers in the HDA's register map. */
99#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
100/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
101#define HDA_MAX_TAGS 16
102
103/**
104 * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
105 * Formula: size - 1
106 * Other values not listed are not supported.
107 */
108
109/** Default timer frequency (in Hz).
110 *
111 * 20 Hz now seems enough for most setups, even with load on the guest.
112 * Raising the rate will produce more I/O load on the guest and therefore
113 * also will affect the performance.
114 */
115#define HDA_TIMER_HZ_DEFAULT 100
116
117/** Default position adjustment (in audio samples).
118 *
119 * For snd_hda_intel (Linux guests), the first BDL entry always is being used as
120 * so-called BDL adjustment, which can vary, and is being used for chipsets which
121 * misbehave and/or are incorrectly implemented.
122 *
123 * The BDL adjustment entry *always* has the IOC (Interrupt on Completion) bit set.
124 *
125 * For Intel Baytrail / Braswell implementations the BDL default adjustment is 32 frames, whereas
126 * for ICH / PCH it's only one (1) frame.
127 *
128 * See default_bdl_pos_adj() and snd_hdac_stream_setup_periods() for more information.
129 *
130 * By default we apply some simple heuristics in hdaStreamInit().
131 */
132#define HDA_POS_ADJUST_DEFAULT 0
133
134/** HDA's (fixed) audio frame size in bytes.
135 * We only support 16-bit stereo frames at the moment. */
136#define HDA_FRAME_SIZE_DEFAULT 4
137
138/** Offset of the SD0 register map. */
139#define HDA_REG_DESC_SD0_BASE 0x80
140
141/** Turn a short global register name into an memory index and a stringized name. */
142#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
143
144/** Turns a short stream register name into an memory index and a stringized name. */
145#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
146
147/** Same as above for a register *not* stored in memory. */
148#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
149
150extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
151
152/**
153 * NB: Register values stored in memory (au32Regs[]) are indexed through
154 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
155 * register descriptors in g_aHdaRegMap[] are indexed through the
156 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
157 *
158 * The au32Regs[] layout is kept unchanged for saved state
159 * compatibility.
160 */
161
162/* Registers */
163#define HDA_REG_IND_NAME(x) HDA_REG_##x
164#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
165#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
166#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
167
168
169#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
170#define HDA_RMX_GCAP 0
171/**
172 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
173 *
174 * oss (15:12) - Number of output streams supported.
175 * iss (11:8) - Number of input streams supported.
176 * bss (7:3) - Number of bidirectional streams supported.
177 * bds (2:1) - Number of serial data out (SDO) signals supported.
178 * b64sup (0) - 64 bit addressing supported.
179 */
180#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
181 ( (((oss) & 0xF) << 12) \
182 | (((iss) & 0xF) << 8) \
183 | (((bss) & 0x1F) << 3) \
184 | (((bds) & 0x3) << 2) \
185 | ((b64sup) & 1))
186
187#define HDA_REG_VMIN 1 /* 0x02 */
188#define HDA_RMX_VMIN 1
189
190#define HDA_REG_VMAJ 2 /* 0x03 */
191#define HDA_RMX_VMAJ 2
192
193#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
194#define HDA_RMX_OUTPAY 3
195
196#define HDA_REG_INPAY 4 /* 0x06-0x07 */
197#define HDA_RMX_INPAY 4
198
199#define HDA_REG_GCTL 5 /* 0x08-0x0B */
200#define HDA_RMX_GCTL 5
201#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
202#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
203#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
204
205#define HDA_REG_WAKEEN 6 /* 0x0C */
206#define HDA_RMX_WAKEEN 6
207
208#define HDA_REG_STATESTS 7 /* 0x0E */
209#define HDA_RMX_STATESTS 7
210#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
211
212#define HDA_REG_GSTS 8 /* 0x10-0x11*/
213#define HDA_RMX_GSTS 8
214#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
215
216#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
217#define HDA_RMX_OUTSTRMPAY 112
218
219#define HDA_REG_INSTRMPAY 10 /* 0x1a */
220#define HDA_RMX_INSTRMPAY 113
221
222#define HDA_REG_INTCTL 11 /* 0x20 */
223#define HDA_RMX_INTCTL 9
224#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
225#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
226/** Bits 0-29 correspond to streams 0-29. */
227#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
228
229#define HDA_REG_INTSTS 12 /* 0x24 */
230#define HDA_RMX_INTSTS 10
231#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
232#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
233
234#define HDA_REG_WALCLK 13 /* 0x30 */
235/**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
236
237/**
238 * Note: The HDA specification defines a SSYNC register at offset 0x38. The
239 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
240 * the datasheet.
241 */
242#define HDA_REG_SSYNC 14 /* 0x34 */
243#define HDA_RMX_SSYNC 12
244
245#define HDA_REG_CORBLBASE 15 /* 0x40 */
246#define HDA_RMX_CORBLBASE 13
247
248#define HDA_REG_CORBUBASE 16 /* 0x44 */
249#define HDA_RMX_CORBUBASE 14
250
251#define HDA_REG_CORBWP 17 /* 0x48 */
252#define HDA_RMX_CORBWP 15
253
254#define HDA_REG_CORBRP 18 /* 0x4A */
255#define HDA_RMX_CORBRP 16
256#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
257
258#define HDA_REG_CORBCTL 19 /* 0x4C */
259#define HDA_RMX_CORBCTL 17
260#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
261#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
262
263#define HDA_REG_CORBSTS 20 /* 0x4D */
264#define HDA_RMX_CORBSTS 18
265
266#define HDA_REG_CORBSIZE 21 /* 0x4E */
267#define HDA_RMX_CORBSIZE 19
268#define HDA_CORBSIZE_SZ_CAP 0xF0
269#define HDA_CORBSIZE_SZ 0x3
270
271/** Number of CORB buffer entries. */
272#define HDA_CORB_SIZE 256
273/** CORB element size (in bytes). */
274#define HDA_CORB_ELEMENT_SIZE 4
275/** Number of RIRB buffer entries. */
276#define HDA_RIRB_SIZE 256
277/** RIRB element size (in bytes). */
278#define HDA_RIRB_ELEMENT_SIZE 8
279
280#define HDA_REG_RIRBLBASE 22 /* 0x50 */
281#define HDA_RMX_RIRBLBASE 20
282
283#define HDA_REG_RIRBUBASE 23 /* 0x54 */
284#define HDA_RMX_RIRBUBASE 21
285
286#define HDA_REG_RIRBWP 24 /* 0x58 */
287#define HDA_RMX_RIRBWP 22
288#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
289
290#define HDA_REG_RINTCNT 25 /* 0x5A */
291#define HDA_RMX_RINTCNT 23
292
293/** Maximum number of Response Interrupts. */
294#define HDA_MAX_RINTCNT 256
295
296#define HDA_REG_RIRBCTL 26 /* 0x5C */
297#define HDA_RMX_RIRBCTL 24
298#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
299#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
300#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
301
302#define HDA_REG_RIRBSTS 27 /* 0x5D */
303#define HDA_RMX_RIRBSTS 25
304#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
305#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
306
307#define HDA_REG_RIRBSIZE 28 /* 0x5E */
308#define HDA_RMX_RIRBSIZE 26
309
310#define HDA_REG_IC 29 /* 0x60 */
311#define HDA_RMX_IC 27
312
313#define HDA_REG_IR 30 /* 0x64 */
314#define HDA_RMX_IR 28
315
316#define HDA_REG_IRS 31 /* 0x68 */
317#define HDA_RMX_IRS 29
318#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
319#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
320
321#define HDA_REG_DPLBASE 32 /* 0x70 */
322#define HDA_RMX_DPLBASE 30
323
324#define HDA_REG_DPUBASE 33 /* 0x74 */
325#define HDA_RMX_DPUBASE 31
326
327#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
328
329#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
330#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
331/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
332#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
333
334#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
335
336/** @todo Condense marcos! */
337
338#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
339#define HDA_RMX_SD0CTL 32
340#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
341#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
342#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
343#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
344#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
345#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
346#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
347
348#define HDA_SDCTL_NUM_MASK 0xF
349#define HDA_SDCTL_NUM_SHIFT 20
350#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
351#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
352#define HDA_SDCTL_STRIPE_MASK 0x3
353#define HDA_SDCTL_STRIPE_SHIFT 16
354#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
355#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
356#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
357#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
358#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
359
360#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
361#define HDA_RMX_SD0STS 33
362#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
363#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
364#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
365#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
366#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
367#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
368#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
369
370#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
371#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
372#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
373#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
374
375#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
376#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
377#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
378#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
379#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
380#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
381#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
382#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
383#define HDA_RMX_SD0LPIB 34
384#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
385#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
386#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
387#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
388#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
389#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
390#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
391
392#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
393#define HDA_RMX_SD0CBL 35
394#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
395#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
396#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
397#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
398#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
399#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
400#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
401
402#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
403#define HDA_RMX_SD0LVI 36
404#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
405#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
406#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
407#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
408#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
409#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
410#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
411
412#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
413#define HDA_RMX_SD0FIFOW 37
414#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
415#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
416#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
417#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
418#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
419#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
420#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
421
422/*
423 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
424 */
425#define HDA_SDFIFOW_8B 0x2
426#define HDA_SDFIFOW_16B 0x3
427#define HDA_SDFIFOW_32B 0x4
428
429#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
430#define HDA_RMX_SD0FIFOS 38
431#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
432#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
433#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
434#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
435#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
436#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
437#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
438
439#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
440#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
441
442#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
443#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
444#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
445#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
446#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
448
449#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
450#define HDA_RMX_SD0FMT 39
451#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
452#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
453#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
454#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
455#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
456#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
457#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
458
459#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
460#define HDA_RMX_SD0BDPL 40
461#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
462#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
463#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
464#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
465#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
466#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
467#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
468
469#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
470#define HDA_RMX_SD0BDPU 41
471#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
472#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
473#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
474#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
475#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
476#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
477#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
478
479#define HDA_CODEC_CAD_SHIFT 28
480/** Encodes the (required) LUN into a codec command. */
481#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
482
483#define HDA_SDFMT_NON_PCM_SHIFT 15
484#define HDA_SDFMT_NON_PCM_MASK 0x1
485#define HDA_SDFMT_BASE_RATE_SHIFT 14
486#define HDA_SDFMT_BASE_RATE_MASK 0x1
487#define HDA_SDFMT_MULT_SHIFT 11
488#define HDA_SDFMT_MULT_MASK 0x7
489#define HDA_SDFMT_DIV_SHIFT 8
490#define HDA_SDFMT_DIV_MASK 0x7
491#define HDA_SDFMT_BITS_SHIFT 4
492#define HDA_SDFMT_BITS_MASK 0x7
493#define HDA_SDFMT_CHANNELS_MASK 0xF
494
495#define HDA_SDFMT_TYPE RT_BIT(15)
496#define HDA_SDFMT_TYPE_PCM (0)
497#define HDA_SDFMT_TYPE_NON_PCM (1)
498
499#define HDA_SDFMT_BASE RT_BIT(14)
500#define HDA_SDFMT_BASE_48KHZ (0)
501#define HDA_SDFMT_BASE_44KHZ (1)
502
503#define HDA_SDFMT_MULT_1X (0)
504#define HDA_SDFMT_MULT_2X (1)
505#define HDA_SDFMT_MULT_3X (2)
506#define HDA_SDFMT_MULT_4X (3)
507
508#define HDA_SDFMT_DIV_1X (0)
509#define HDA_SDFMT_DIV_2X (1)
510#define HDA_SDFMT_DIV_3X (2)
511#define HDA_SDFMT_DIV_4X (3)
512#define HDA_SDFMT_DIV_5X (4)
513#define HDA_SDFMT_DIV_6X (5)
514#define HDA_SDFMT_DIV_7X (6)
515#define HDA_SDFMT_DIV_8X (7)
516
517#define HDA_SDFMT_8_BIT (0)
518#define HDA_SDFMT_16_BIT (1)
519#define HDA_SDFMT_20_BIT (2)
520#define HDA_SDFMT_24_BIT (3)
521#define HDA_SDFMT_32_BIT (4)
522
523#define HDA_SDFMT_CHAN_MONO (0)
524#define HDA_SDFMT_CHAN_STEREO (1)
525
526/** Emits a SDnFMT register format.
527 * Also being used in the codec's converter format. */
528#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
529 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
530 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
531 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
532 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
533 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
534 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
535
536/** Interrupt on completion (IOC) flag. */
537#define HDA_BDLE_F_IOC RT_BIT(0)
538
539
540
541/** Pointer to a shared HDA state. */
542typedef struct HDASTATE *PHDASTATE;
543/** Pointer to a HDA stream state. */
544typedef struct HDASTREAM *PHDASTREAM;
545/** Pointer to a mixer sink. */
546typedef struct HDAMIXERSINK *PHDAMIXERSINK;
547
548
549/**
550 * BDL description structure.
551 * Do not touch this, as this must match to the HDA specs.
552 */
553typedef struct HDABDLEDESC
554{
555 /** Starting address of the actual buffer. Must be 128-bit aligned. */
556 uint64_t u64BufAddr;
557 /** Size of the actual buffer (in bytes). */
558 uint32_t u32BufSize;
559 /** Bit 0: Interrupt on completion; the controller will generate
560 * an interrupt when the last byte of the buffer has been
561 * fetched by the DMA engine.
562 *
563 * Rest is reserved for further use and must be 0. */
564 uint32_t fFlags;
565} HDABDLEDESC, *PHDABDLEDESC;
566AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
567
568
569/** @name Object lookup functions.
570 * @{
571 */
572#ifdef IN_RING3
573PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATER3 pThisCC, uint8_t uSD);
574#endif
575PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
576//PHDASTREAM hdaGetStreamFromSD(PHDASTATER3 pThisCC, uint8_t uSD);
577#ifdef IN_RING3
578PHDASTREAMR3 hdaR3GetR3StreamFromSink(PHDAMIXERSINK pSink);
579PHDASTREAM hdaR3GetSharedStreamFromSink(PHDAMIXERSINK pSink);
580#endif
581/** @} */
582
583/** @name Interrupt functions.
584 * @{
585 */
586#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
587void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
588# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
589#else
590void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
591# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
592#endif
593/** @} */
594
595/** @name Register utility functions.
596 * @{ */
597uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
598/** @} */
599
600/** @name Register functions.
601 * @{
602 */
603uint32_t hdaGetINTSTS(PHDASTATE pThis);
604#ifdef IN_RING3
605int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
606#endif /* IN_RING3 */
607/** @} */
608
609/** @name BDLE (Buffer Descriptor List Entry) functions.
610 * @{
611 */
612#ifdef IN_RING3
613# ifdef LOG_ENABLED
614void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
615# endif
616#endif /* IN_RING3 */
617/** @} */
618
619#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaCommon_h */
620
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use