VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHda.h

Last change on this file was 98103, checked in by vboxsync, 16 months ago

Copyright year updates by scm.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 38.1 KB
Line 
1/* $Id: DevHda.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Structures.
4 */
5
6/*
7 * Copyright (C) 2016-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
29#define VBOX_INCLUDED_SRC_Audio_DevHda_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <iprt/path.h>
35#include <VBox/vmm/pdmdev.h>
36#include "AudioMixer.h"
37
38/*
39 * Compile time feature configuration.
40 */
41
42/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
43 * Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
44 * addition to the DMA timer. All but the last frame can be done during
45 * register accesses (as we don't wish to leave the DMA timer w/o work to
46 * do in case that upsets it). */
47#if defined(DOXYGEN_RUNNING) || 0
48# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
49#endif
50
51#ifdef DEBUG_andy
52/** Enables strict mode, which checks for stuff which isn't supposed to happen.
53 * Be prepared for assertions coming in! */
54//# define HDA_STRICT
55#endif
56
57/** @def HDA_AS_PCI_EXPRESS
58 * Enables PCI express hardware. */
59#if defined(DOXYGEN_RUNNING) || 0
60# define HDA_AS_PCI_EXPRESS
61#endif
62
63/** @def HDA_DEBUG_SILENCE
64 * To debug silence coming from the guest in form of audio gaps.
65 * Very crude implementation for now.
66 * @todo probably borked atm */
67#if defined(DOXYGEN_RUNNING) || 0
68# define HDA_DEBUG_SILENCE
69#endif
70
71
72/*
73 * Common pointer types.
74 */
75/** Pointer to an HDA stream (SDI / SDO). */
76typedef struct HDASTREAMR3 *PHDASTREAMR3;
77/** Pointer to a shared HDA device state. */
78typedef struct HDASTATE *PHDASTATE;
79/** Pointer to a ring-3 HDA device state. */
80typedef struct HDASTATER3 *PHDASTATER3;
81/** Pointer to an HDA mixer sink definition (ring-3). */
82typedef struct HDAMIXERSINK *PHDAMIXERSINK;
83
84
85/*
86 * The rest of the headers.
87 */
88#include "DevHdaStream.h"
89#include "DevHdaCodec.h"
90
91
92
93/** @name Stream counts.
94 *
95 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
96 * Bidirectional streams are currently *not* supported.
97 *
98 * @note When changing any of those values, be prepared for some saved state
99 * fixups / trouble!
100 * @{
101 */
102#define HDA_MAX_SDI 4
103#define HDA_MAX_SDO 4
104#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
105/** @} */
106AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
107
108
109/** @defgroup grp_hda_regs HDA Register Definitions
110 *
111 * There are two variants for most register defines:
112 * - HDA_REG_XXX: Index into g_aHdaRegMap
113 * - HDA_RMX_XXX: Index into HDASTATE::au32Regs
114 *
115 * Use the HDA_REG and HDA_STREAM_REG macros to access registers where possible.
116 *
117 * @note The au32Regs[] layout is kept unchanged for saved state compatibility,
118 * thus the HDA_RMX_XXX assignments are for all purposes set in stone.
119 *
120 * @{ */
121
122/** Number of general registers. */
123#define HDA_NUM_GENERAL_REGS 36
124/** Number of stream registers (10 registers per stream). */
125#define HDA_NUM_STREAM_REGS (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */)
126/** Number of register after the stream registers. */
127#define HDA_NUM_POST_STREAM_REGS (2 + HDA_MAX_STREAMS * 2)
128/** Number of total registers in the HDA's register map. */
129#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + HDA_NUM_STREAM_REGS + HDA_NUM_POST_STREAM_REGS)
130/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
131#define HDA_MAX_TAGS 16
132
133
134/** Offset of the SD0 register map. */
135#define HDA_REG_DESC_SD0_BASE 0x80
136
137/* Registers */
138#define HDA_REG_IND_NAME(x) HDA_REG_##x
139#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
140
141/** Direct register access by HDASTATE::au32Reg index. */
142#define HDA_REG_BY_IDX(a_pThis, a_idxReg) ((a_pThis)->au32Regs[(a_idxReg)])
143
144/** Accesses register @a ShortRegNm. */
145#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
146# define HDA_REG(a_pThis, a_ShortRegNm) (*hdaStrictRegAccessor(a_pThis, HDA_REG_IND_NAME(a_ShortRegNm), HDA_MEM_IND_NAME(a_ShortRegNm)))
147#else
148# define HDA_REG(a_pThis, a_ShortRegNm) HDA_REG_BY_IDX(a_pThis, HDA_MEM_IND_NAME(a_ShortRegNm))
149#endif
150
151/** Indirect register access via g_aHdaRegMap[].idxReg. */
152#define HDA_REG_IND(a_pThis, a_idxMap) HDA_REG_BY_IDX(a_pThis, g_aHdaRegMap[(a_idxMap)].idxReg)
153
154
155#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
156#define HDA_RMX_GCAP 0
157/**
158 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
159 *
160 * oss (15:12) - Number of output streams supported.
161 * iss (11:8) - Number of input streams supported.
162 * bss (7:3) - Number of bidirectional streams supported.
163 * bds (2:1) - Number of serial data out (SDO) signals supported.
164 * b64sup (0) - 64 bit addressing supported.
165 */
166#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
167 ( (((oss) & 0xF) << 12) \
168 | (((iss) & 0xF) << 8) \
169 | (((bss) & 0x1F) << 3) \
170 | (((bds) & 0x3) << 2) \
171 | ((b64sup) & 1))
172
173#define HDA_REG_VMIN 1 /* 0x02 */
174#define HDA_RMX_VMIN 1
175
176#define HDA_REG_VMAJ 2 /* 0x03 */
177#define HDA_RMX_VMAJ 2
178
179#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
180#define HDA_RMX_OUTPAY 3
181
182#define HDA_REG_INPAY 4 /* 0x06-0x07 */
183#define HDA_RMX_INPAY 4
184
185#define HDA_REG_GCTL 5 /* 0x08-0x0B */
186#define HDA_RMX_GCTL 5
187#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
188#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
189#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
190
191#define HDA_REG_WAKEEN 6 /* 0x0C */
192#define HDA_RMX_WAKEEN 6
193
194#define HDA_REG_STATESTS 7 /* 0x0E */
195#define HDA_RMX_STATESTS 7
196#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
197
198#define HDA_REG_GSTS 8 /* 0x10-0x11*/
199#define HDA_RMX_GSTS 8
200#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
201
202#define HDA_REG_LLCH 9 /* 0x14 */
203#define HDA_RMX_LLCH 114
204
205#define HDA_REG_OUTSTRMPAY 10 /* 0x18 */
206#define HDA_RMX_OUTSTRMPAY 112
207
208#define HDA_REG_INSTRMPAY 11 /* 0x1a */
209#define HDA_RMX_INSTRMPAY 113
210
211#define HDA_REG_INTCTL 12 /* 0x20 */
212#define HDA_RMX_INTCTL 9
213#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
214#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
215/** Bits 0-29 correspond to streams 0-29. */
216#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
217
218#define HDA_REG_INTSTS 13 /* 0x24 */
219#define HDA_RMX_INTSTS 10
220#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
221#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
222
223#define HDA_REG_WALCLK 14 /* 0x30 */
224/* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
225
226/**
227 * @note The HDA specification defines a SSYNC register at offset 0x38. The ICH6/ICH9
228 * datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches the datasheet.
229 * See also https://mailman.alsa-project.org/pipermail/alsa-devel/2011-March/037819.html
230 */
231#define HDA_REG_SSYNC 15 /* 0x34 */
232#define HDA_RMX_SSYNC 12
233
234#define HDA_REG_NEW_SSYNC 16 /* 0x38 */
235#define HDA_RMX_NEW_SSYNC HDA_RMX_SSYNC
236
237#define HDA_REG_CORBLBASE 17 /* 0x40 */
238#define HDA_RMX_CORBLBASE 13
239
240#define HDA_REG_CORBUBASE 18 /* 0x44 */
241#define HDA_RMX_CORBUBASE 14
242
243#define HDA_REG_CORBWP 19 /* 0x48 */
244#define HDA_RMX_CORBWP 15
245
246#define HDA_REG_CORBRP 20 /* 0x4A */
247#define HDA_RMX_CORBRP 16
248#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
249
250#define HDA_REG_CORBCTL 21 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
253#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
254
255#define HDA_REG_CORBSTS 22 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257
258#define HDA_REG_CORBSIZE 23 /* 0x4E */
259#define HDA_RMX_CORBSIZE 19
260#define HDA_CORBSIZE_SZ_CAP 0xF0
261#define HDA_CORBSIZE_SZ 0x3
262
263/** Number of CORB buffer entries. */
264#define HDA_CORB_SIZE 256
265/** CORB element size (in bytes). */
266#define HDA_CORB_ELEMENT_SIZE 4
267/** Number of RIRB buffer entries. */
268#define HDA_RIRB_SIZE 256
269/** RIRB element size (in bytes). */
270#define HDA_RIRB_ELEMENT_SIZE 8
271
272#define HDA_REG_RIRBLBASE 24 /* 0x50 */
273#define HDA_RMX_RIRBLBASE 20
274
275#define HDA_REG_RIRBUBASE 25 /* 0x54 */
276#define HDA_RMX_RIRBUBASE 21
277
278#define HDA_REG_RIRBWP 26 /* 0x58 */
279#define HDA_RMX_RIRBWP 22
280#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
281
282#define HDA_REG_RINTCNT 27 /* 0x5A */
283#define HDA_RMX_RINTCNT 23
284
285/** Maximum number of Response Interrupts. */
286#define HDA_MAX_RINTCNT 256
287
288#define HDA_REG_RIRBCTL 28 /* 0x5C */
289#define HDA_RMX_RIRBCTL 24
290#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
291#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
292#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
293
294#define HDA_REG_RIRBSTS 29 /* 0x5D */
295#define HDA_RMX_RIRBSTS 25
296#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
297#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
298
299#define HDA_REG_RIRBSIZE 30 /* 0x5E */
300#define HDA_RMX_RIRBSIZE 26
301
302#define HDA_REG_IC 31 /* 0x60 */
303#define HDA_RMX_IC 27
304
305#define HDA_REG_IR 32 /* 0x64 */
306#define HDA_RMX_IR 28
307
308#define HDA_REG_IRS 33 /* 0x68 */
309#define HDA_RMX_IRS 29
310#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
311#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
312
313#define HDA_REG_DPLBASE 34 /* 0x70 */
314#define HDA_RMX_DPLBASE 30
315
316#define HDA_REG_DPUBASE 35 /* 0x74 */
317#define HDA_RMX_DPUBASE 31
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/** @note sdnum here _MUST_ be stream reg number [0,7]. */
324#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
325# define HDA_STREAM_REG(pThis, name, sdnum) (*hdaStrictStreamRegAccessor((pThis), HDA_REG_SD0##name, HDA_RMX_SD0##name, (sdnum)))
326#else
327# define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_BY_IDX((pThis), HDA_RMX_SD0##name + (sdnum) * 10))
328#endif
329
330#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
331#define HDA_SD_TO_REG(a_Name, uSD) (HDA_STREAM_REG_DEF(a_Name, 0) + (uSD) * 10)
332
333/** @todo Condense marcos! */
334
335#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
336#define HDA_RMX_SD0CTL 32
337#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
338#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
339#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
340#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
341#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
342#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
343#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
344
345#define HDA_SDCTL_NUM_MASK 0xF
346#define HDA_SDCTL_NUM_SHIFT 20
347#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
348#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
349#define HDA_SDCTL_STRIPE_MASK 0x3
350#define HDA_SDCTL_STRIPE_SHIFT 16
351#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
352#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
353#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
354#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
355#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
356
357#define HDA_REG_SD0STS (HDA_NUM_GENERAL_REGS + 1) /* 0x83; other streams offset by 0x20 */
358#define HDA_RMX_SD0STS 33
359#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
360#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
361#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
362#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
363#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
364#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
365#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
366
367#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
368#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
369#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
370#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
371
372#define HDA_REG_SD0LPIB (HDA_NUM_GENERAL_REGS + 2) /* 0x84; other streams offset by 0x20 */
373#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
374#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
375#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
376#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
377#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
378#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
379#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
380#define HDA_RMX_SD0LPIB 34
381#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
382#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
383#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
384#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
385#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
386#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
387#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
388
389#define HDA_REG_SD0CBL (HDA_NUM_GENERAL_REGS + 3) /* 0x88; other streams offset by 0x20 */
390#define HDA_RMX_SD0CBL 35
391#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
392#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
393#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
394#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
395#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
396#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
397#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
398
399#define HDA_REG_SD0LVI (HDA_NUM_GENERAL_REGS + 4) /* 0x8C; other streams offset by 0x20 */
400#define HDA_RMX_SD0LVI 36
401#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
402#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
403#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
404#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
405#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
406#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
407#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
408
409#define HDA_REG_SD0FIFOW (HDA_NUM_GENERAL_REGS + 5) /* 0x8E; other streams offset by 0x20 */
410#define HDA_RMX_SD0FIFOW 37
411#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
412#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
413#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
414#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
415#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
416#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
417#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
418
419/*
420 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
421 */
422#define HDA_SDFIFOW_8B 0x2
423#define HDA_SDFIFOW_16B 0x3
424#define HDA_SDFIFOW_32B 0x4
425
426#define HDA_REG_SD0FIFOS (HDA_NUM_GENERAL_REGS + 6) /* 0x90; other streams offset by 0x20 */
427#define HDA_RMX_SD0FIFOS 38
428#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
429#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
430#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
431#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
432#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
433#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
434#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
435
436/* The ICH6 datasheet defines limits for FIFOS registers (18.2.39).
437 Formula: size - 1
438 Other values not listed are not supported. */
439
440#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
441#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
442
443#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
444#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
445#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
446#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
448#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
449
450#define HDA_REG_SD0FMT (HDA_NUM_GENERAL_REGS + 7) /* 0x92; other streams offset by 0x20 */
451#define HDA_RMX_SD0FMT 39
452#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
453#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
454#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
455#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
456#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
457#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
458#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
459
460#define HDA_REG_SD0BDPL (HDA_NUM_GENERAL_REGS + 8) /* 0x98; other streams offset by 0x20 */
461#define HDA_RMX_SD0BDPL 40
462#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
463#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
464#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
465#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
466#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
467#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
468#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
469
470#define HDA_REG_SD0BDPU (HDA_NUM_GENERAL_REGS + 9) /* 0x9C; other streams offset by 0x20 */
471#define HDA_RMX_SD0BDPU 41
472#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
473#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
474#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
475#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
476#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
477#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
478#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
479
480#define HDA_CODEC_CAD_SHIFT 28
481/** Encodes the (required) LUN into a codec command. */
482#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
483
484#define HDA_SDFMT_NON_PCM_SHIFT 15
485#define HDA_SDFMT_NON_PCM_MASK 0x1
486#define HDA_SDFMT_BASE_RATE_SHIFT 14
487#define HDA_SDFMT_BASE_RATE_MASK 0x1
488#define HDA_SDFMT_MULT_SHIFT 11
489#define HDA_SDFMT_MULT_MASK 0x7
490#define HDA_SDFMT_DIV_SHIFT 8
491#define HDA_SDFMT_DIV_MASK 0x7
492#define HDA_SDFMT_BITS_SHIFT 4
493#define HDA_SDFMT_BITS_MASK 0x7
494#define HDA_SDFMT_CHANNELS_MASK 0xF
495
496#define HDA_SDFMT_TYPE RT_BIT(15)
497#define HDA_SDFMT_TYPE_PCM (0)
498#define HDA_SDFMT_TYPE_NON_PCM (1)
499
500#define HDA_SDFMT_BASE RT_BIT(14)
501#define HDA_SDFMT_BASE_48KHZ (0)
502#define HDA_SDFMT_BASE_44KHZ (1)
503
504#define HDA_SDFMT_MULT_1X (0)
505#define HDA_SDFMT_MULT_2X (1)
506#define HDA_SDFMT_MULT_3X (2)
507#define HDA_SDFMT_MULT_4X (3)
508
509#define HDA_SDFMT_DIV_1X (0)
510#define HDA_SDFMT_DIV_2X (1)
511#define HDA_SDFMT_DIV_3X (2)
512#define HDA_SDFMT_DIV_4X (3)
513#define HDA_SDFMT_DIV_5X (4)
514#define HDA_SDFMT_DIV_6X (5)
515#define HDA_SDFMT_DIV_7X (6)
516#define HDA_SDFMT_DIV_8X (7)
517
518#define HDA_SDFMT_8_BIT (0)
519#define HDA_SDFMT_16_BIT (1)
520#define HDA_SDFMT_20_BIT (2)
521#define HDA_SDFMT_24_BIT (3)
522#define HDA_SDFMT_32_BIT (4)
523
524#define HDA_SDFMT_CHAN_MONO (0)
525#define HDA_SDFMT_CHAN_STEREO (1)
526
527/** Emits a SDnFMT register format.
528 * Also being used in the codec's converter format. */
529#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
530 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
531 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
532 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
533 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
534 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
535 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
536
537
538/* Post stream registers: */
539#define HDA_REG_MLCH (HDA_NUM_GENERAL_REGS + HDA_NUM_STREAM_REGS) /* 0xc00 */
540#define HDA_RMX_MLCH 115
541#define HDA_REG_MLCD (HDA_REG_MLCH + 1) /* 0xc04 */
542#define HDA_RMX_MLCD 116
543
544/* Registers added/specific-to skylake/broxton: */
545#define HDA_SD_NUM_FROM_SKYLAKE_REG(a_Name, a_iMap) (((a_iMap) - HDA_STREAM_REG_DEF(a_Name, 0)) / 2)
546
547#define HDA_REG_SD0DPIB (HDA_REG_MLCD + 1) /* 0x1084 */
548#define HDA_REG_SD1DPIB (HDA_REG_SD0DPIB + 1*2)
549#define HDA_REG_SD2DPIB (HDA_REG_SD0DPIB + 2*2)
550#define HDA_REG_SD3DPIB (HDA_REG_SD0DPIB + 3*2)
551#define HDA_REG_SD4DPIB (HDA_REG_SD0DPIB + 4*2)
552#define HDA_REG_SD5DPIB (HDA_REG_SD0DPIB + 5*2)
553#define HDA_REG_SD6DPIB (HDA_REG_SD0DPIB + 6*2)
554#define HDA_REG_SD7DPIB (HDA_REG_SD0DPIB + 7*2)
555
556#define HDA_RMX_SD0DPIB HDA_RMX_SD0LPIB
557#define HDA_RMX_SD1DPIB HDA_RMX_SD1LPIB
558#define HDA_RMX_SD2DPIB HDA_RMX_SD2LPIB
559#define HDA_RMX_SD3DPIB HDA_RMX_SD3LPIB
560#define HDA_RMX_SD4DPIB HDA_RMX_SD4LPIB
561#define HDA_RMX_SD5DPIB HDA_RMX_SD5LPIB
562#define HDA_RMX_SD6DPIB HDA_RMX_SD6LPIB
563#define HDA_RMX_SD7DPIB HDA_RMX_SD7LPIB
564
565#define HDA_REG_SD0EFIFOS (HDA_REG_SD0DPIB + 1) /* 0x1094 */
566#define HDA_REG_SD1EFIFOS (HDA_REG_SD0EFIFOS + 1*2)
567#define HDA_REG_SD2EFIFOS (HDA_REG_SD0EFIFOS + 2*2)
568#define HDA_REG_SD3EFIFOS (HDA_REG_SD0EFIFOS + 3*2)
569#define HDA_REG_SD4EFIFOS (HDA_REG_SD0EFIFOS + 4*2)
570#define HDA_REG_SD5EFIFOS (HDA_REG_SD0EFIFOS + 5*2)
571#define HDA_REG_SD6EFIFOS (HDA_REG_SD0EFIFOS + 6*2)
572#define HDA_REG_SD7EFIFOS (HDA_REG_SD0EFIFOS + 7*2)
573
574#define HDA_RMX_SD0EFIFOS 117
575#define HDA_RMX_SD1EFIFOS (HDA_RMX_SD0EFIFOS + 1)
576#define HDA_RMX_SD2EFIFOS (HDA_RMX_SD0EFIFOS + 2)
577#define HDA_RMX_SD3EFIFOS (HDA_RMX_SD0EFIFOS + 3)
578#define HDA_RMX_SD4EFIFOS (HDA_RMX_SD0EFIFOS + 4)
579#define HDA_RMX_SD5EFIFOS (HDA_RMX_SD0EFIFOS + 5)
580#define HDA_RMX_SD6EFIFOS (HDA_RMX_SD0EFIFOS + 6)
581#define HDA_RMX_SD7EFIFOS (HDA_RMX_SD0EFIFOS + 7)
582
583/** @} */ /* grp_hda_regs */
584
585
586/**
587 * Buffer descriptor list entry (BDLE).
588 *
589 * See 3.6.3 in HDA specs rev 1.0a (2010-06-17).
590 */
591typedef struct HDABDLEDESC
592{
593 /** Starting address of the actual buffer. Must be 128-bit aligned. */
594 uint64_t u64BufAddr;
595 /** Size of the actual buffer (in bytes). */
596 uint32_t u32BufSize;
597 /** HDA_BDLE_F_XXX.
598 *
599 * Bit 0: IOC - Interrupt on completion / HDA_BDLE_F_IOC.
600 * The controller will generate an interrupt when the last byte of the buffer
601 * has been fetched by the DMA engine.
602 *
603 * Bits 31:1 are reserved for further use and must be 0. */
604 uint32_t fFlags;
605} HDABDLEDESC, *PHDABDLEDESC;
606AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
607
608/** Interrupt on completion (IOC) flag. */
609#define HDA_BDLE_F_IOC RT_BIT(0)
610
611
612/**
613 * HDA mixer sink definition (ring-3).
614 *
615 * Its purpose is to know which audio mixer sink is bound to which SDn
616 * (SDI/SDO) device stream.
617 *
618 * This is needed in order to handle interleaved streams (that is, multiple
619 * channels in one stream) or non-interleaved streams (each channel has a
620 * dedicated stream).
621 *
622 * This is only known to the actual device emulation level.
623 */
624typedef struct HDAMIXERSINK
625{
626 R3PTRTYPE(PHDASTREAM) pStreamShared;
627 R3PTRTYPE(PHDASTREAMR3) pStreamR3;
628 /** Pointer to the actual audio mixer sink. */
629 R3PTRTYPE(PAUDMIXSINK) pMixSink;
630} HDAMIXERSINK;
631
632/**
633 * Mapping a stream tag to an HDA stream (ring-3).
634 */
635typedef struct HDATAG
636{
637 /** Own stream tag. */
638 uint8_t uTag;
639 uint8_t Padding[7];
640 /** Pointer to associated stream. */
641 R3PTRTYPE(PHDASTREAMR3) pStreamR3;
642} HDATAG;
643/** Pointer to a HDA stream tag mapping. */
644typedef HDATAG *PHDATAG;
645
646/**
647 * Shared ICH Intel HD audio controller state.
648 */
649typedef struct HDASTATE
650{
651 /** Critical section protecting the HDA state. */
652 PDMCRITSECT CritSect;
653 /** Internal stream states (aligned on 64 byte boundrary). */
654 HDASTREAM aStreams[HDA_MAX_STREAMS];
655 /** The HDA's register set. */
656 uint32_t au32Regs[HDA_NUM_REGS];
657 /** CORB buffer base address. */
658 uint64_t u64CORBBase;
659 /** RIRB buffer base address. */
660 uint64_t u64RIRBBase;
661 /** DMA base address.
662 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
663 uint64_t u64DPBase;
664 /** Size in bytes of CORB buffer (#au32CorbBuf). */
665 uint32_t cbCorbBuf;
666 /** Size in bytes of RIRB buffer (#au64RirbBuf). */
667 uint32_t cbRirbBuf;
668 /** Response Interrupt Count (RINTCNT). */
669 uint16_t u16RespIntCnt;
670 /** DMA position buffer enable bit. */
671 bool fDMAPosition;
672 /** Current IRQ level. */
673 uint8_t u8IRQL;
674 /** Config: Internal input DMA buffer size override, specified in milliseconds.
675 * Zero means default size according to buffer and stream config.
676 * @sa BufSizeInMs config value. */
677 uint16_t cMsCircBufIn;
678 /** Config: Internal output DMA buffer size override, specified in milliseconds.
679 * Zero means default size according to buffer and stream config.
680 * @sa BufSizeOutMs config value. */
681 uint16_t cMsCircBufOut;
682 /** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
683 uint64_t tsWalClkStart;
684 /** CORB DMA task handle.
685 * We use this when there is stuff we cannot handle in ring-0. */
686 PDMTASKHANDLE hCorbDmaTask;
687 /** The CORB buffer. */
688 uint32_t au32CorbBuf[HDA_CORB_SIZE];
689 /** Pointer to RIRB buffer. */
690 uint64_t au64RirbBuf[HDA_RIRB_SIZE];
691
692 /** PCI Region \#0: 16KB of MMIO stuff. */
693 IOMMMIOHANDLE hMmio;
694
695#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
696 STAMCOUNTER StatAccessDmaOutput;
697 STAMCOUNTER StatAccessDmaOutputToR3;
698#endif
699#ifdef VBOX_WITH_STATISTICS
700 STAMPROFILE StatIn;
701 STAMPROFILE StatOut;
702 STAMCOUNTER StatBytesRead;
703 STAMCOUNTER StatBytesWritten;
704
705 /** @name Register statistics.
706 * The array members run parallel to g_aHdaRegMap.
707 * @{ */
708 STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
709 STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
710 STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
711 STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
712 STAMCOUNTER StatRegMultiReadsRZ;
713 STAMCOUNTER StatRegMultiReadsR3;
714 STAMCOUNTER StatRegMultiWritesRZ;
715 STAMCOUNTER StatRegMultiWritesR3;
716 STAMCOUNTER StatRegSubWriteRZ;
717 STAMCOUNTER StatRegSubWriteR3;
718 STAMCOUNTER StatRegUnknownReads;
719 STAMCOUNTER StatRegUnknownWrites;
720 STAMCOUNTER StatRegWritesBlockedByReset;
721 STAMCOUNTER StatRegWritesBlockedByRun;
722 /** @} */
723#endif
724
725#ifdef DEBUG
726 /** Debug stuff.
727 * @todo Make STAM values out some of this? */
728 struct
729 {
730# if 0 /* unused */
731 /** Timestamp (in ns) of the last timer callback (hdaTimer).
732 * Used to calculate the time actually elapsed between two timer callbacks. */
733 uint64_t tsTimerLastCalledNs;
734# endif
735 /** IRQ debugging information. */
736 struct
737 {
738 /** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
739 uint64_t tsProcessedLastNs;
740 /** Timestamp (in ns) of last asserted IRQ. */
741 uint64_t tsAssertedNs;
742# if 0 /* unused */
743 /** How many IRQs have been asserted already. */
744 uint64_t cAsserted;
745 /** Accumulated elapsed time (in ns) of all IRQ being asserted. */
746 uint64_t tsAssertedTotalNs;
747 /** Timestamp (in ns) of last deasserted IRQ. */
748 uint64_t tsDeassertedNs;
749 /** How many IRQs have been deasserted already. */
750 uint64_t cDeasserted;
751 /** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
752 uint64_t tsDeassertedTotalNs;
753# endif
754 } IRQ;
755 } Dbg;
756#endif
757 /** This is for checking that the build was correctly configured in all contexts.
758 * This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
759 uint64_t uAlignmentCheckMagic;
760} HDASTATE;
761AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
762/** Pointer to a shared HDA device state. */
763typedef HDASTATE *PHDASTATE;
764
765/** Value for HDASTATE:uAlignmentCheckMagic. */
766#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
767
768/**
769 * Ring-0 ICH Intel HD audio controller state.
770 */
771typedef struct HDASTATER0
772{
773# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
774 /** Pointer to HDA codec to use. */
775 HDACODECR0 Codec;
776# else
777 uint32_t u32Dummy;
778# endif
779} HDASTATER0;
780/** Pointer to a ring-0 HDA device state. */
781typedef HDASTATER0 *PHDASTATER0;
782
783/**
784 * Ring-3 ICH Intel HD audio controller state.
785 */
786typedef struct HDASTATER3
787{
788 /** Internal stream states. */
789 HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
790 /** Mapping table between stream tags and stream states. */
791 HDATAG aTags[HDA_MAX_TAGS];
792 /** R3 Pointer to the device instance. */
793 PPDMDEVINSR3 pDevIns;
794 /** The base interface for LUN\#0. */
795 PDMIBASE IBase;
796 /** List of associated LUN drivers (HDADRIVER). */
797 RTLISTANCHORR3 lstDrv;
798 /** The device' software mixer. */
799 R3PTRTYPE(PAUDIOMIXER) pMixer;
800 /** HDA sink for (front) output. */
801 HDAMIXERSINK SinkFront;
802#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
803 /** HDA sink for center / LFE output. */
804 HDAMIXERSINK SinkCenterLFE;
805 /** HDA sink for rear output. */
806 HDAMIXERSINK SinkRear;
807#endif
808 /** HDA mixer sink for line input. */
809 HDAMIXERSINK SinkLineIn;
810#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
811 /** Audio mixer sink for microphone input. */
812 HDAMIXERSINK SinkMicIn;
813#endif
814 /** Debug stuff. */
815 struct
816 {
817 /** Whether debugging is enabled or not. */
818 bool fEnabled;
819 /** Path where to dump the debug output to.
820 * Can be NULL, in which the system's temporary directory will be used then. */
821 R3PTRTYPE(char *) pszOutPath;
822 } Dbg;
823 /** Align the codec state on a cache line. */
824 uint64_t au64Padding[3];
825 /** The HDA codec state. */
826 HDACODECR3 Codec;
827} HDASTATER3;
828AssertCompileMemberAlignment(HDASTATER3, Codec, 64);
829
830
831/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
832typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
833
834
835/** @def HDA_PROCESS_INTERRUPT
836 * Wrapper around hdaProcessInterrupt that supplies the source function name
837 * string in logging builds. */
838#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
839void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
840# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
841#else
842void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
843# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
844#endif
845
846/**
847 * Returns the audio direction of a specified stream descriptor.
848 *
849 * The register layout specifies that input streams (SDI) come first,
850 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
851 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
852 *
853 * @note SDnFMT register does not provide that information, so we have to judge
854 * for ourselves.
855 *
856 * @return Audio direction.
857 * @param uSD The stream number.
858 */
859DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
860{
861 if (uSD < HDA_MAX_SDI)
862 return PDMAUDIODIR_IN;
863 AssertReturn(uSD < HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
864 return PDMAUDIODIR_OUT;
865}
866
867/* Used by hdaR3StreamSetUp: */
868uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
869
870#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
871/* Only in DevHda.cpp: */
872DECLINLINE(uint32_t *) hdaStrictRegAccessor(PHDASTATE pThis, uint32_t idxMap, uint32_t idxReg);
873DECLINLINE(uint32_t *) hdaStrictStreamRegAccessor(PHDASTATE pThis, uint32_t idxMap0, uint32_t idxReg0, size_t idxStream);
874#endif /* VBOX_STRICT && VBOX_HDA_CAN_ACCESS_REG_MAP */
875
876
877/** @name HDA device functions used by the codec.
878 * @{ */
879DECLHIDDEN(int) hdaR3MixerAddStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PCPDMAUDIOSTREAMCFG pCfg);
880DECLHIDDEN(int) hdaR3MixerRemoveStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, bool fImmediate);
881DECLHIDDEN(int) hdaR3MixerControl(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel);
882DECLHIDDEN(int) hdaR3MixerSetVolume(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol);
883/** @} */
884
885
886/** @name Saved state versions for the HDA device
887 * @{ */
888/** The current staved state version.
889 * @note Only for the registration call. Never used for tests. */
890#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
891
892/** Removed period and redefined wall clock. */
893#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
894/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
895 * Added (Controller): Current IRQ level.
896 * Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
897 * Added (Per stream): Struct g_aSSMStreamStateFields7.
898 * Added (Per stream): Struct g_aSSMStreamPeriodFields7.
899 * Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
900 * Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
901#define HDA_SAVED_STATE_VERSION_7 7
902/** Saves the current BDLE state.
903 * @since 5.0.14 (r104839) */
904#define HDA_SAVED_STATE_VERSION_6 6
905/** Introduced dynamic number of streams + stream identifiers for serialization.
906 * Bug: Did not save the BDLE states correctly.
907 * Those will be skipped on load then.
908 * @since 5.0.12 (r104520) */
909#define HDA_SAVED_STATE_VERSION_5 5
910/** Since this version the number of MMIO registers can be flexible. */
911#define HDA_SAVED_STATE_VERSION_4 4
912#define HDA_SAVED_STATE_VERSION_3 3
913#define HDA_SAVED_STATE_VERSION_2 2
914#define HDA_SAVED_STATE_VERSION_1 1
915/** @} */
916
917#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
918
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use