[69202] | 1 | ;; @file
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| 2 | ; IPRT - X86 and AMD64 Structures and Definitions.
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| 3 | ;
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| 4 | ; Automatically generated by various.sed. DO NOT EDIT!
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| 5 | ;
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| 6 |
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| 7 | ;
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[98103] | 8 | ; Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[69202] | 9 | ;
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[96407] | 10 | ; This file is part of VirtualBox base platform packages, as
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| 11 | ; available from https://www.virtualbox.org.
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[69202] | 12 | ;
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[96407] | 13 | ; This program is free software; you can redistribute it and/or
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| 14 | ; modify it under the terms of the GNU General Public License
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| 15 | ; as published by the Free Software Foundation, in version 3 of the
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| 16 | ; License.
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| 17 | ;
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| 18 | ; This program is distributed in the hope that it will be useful, but
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| 19 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 20 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 21 | ; General Public License for more details.
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| 22 | ;
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| 23 | ; You should have received a copy of the GNU General Public License
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| 24 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 25 | ;
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[69202] | 26 | ; The contents of this file may alternatively be used under the terms
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| 27 | ; of the Common Development and Distribution License Version 1.0
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[96407] | 28 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 29 | ; in the VirtualBox distribution, in which case the provisions of the
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[69202] | 30 | ; CDDL are applicable instead of those of the GPL.
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| 31 | ;
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| 32 | ; You may elect to license modified versions of this file under the
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| 33 | ; terms and conditions of either the GPL or the CDDL or both.
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| 34 | ;
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[96407] | 35 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 36 | ;
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[69202] | 37 |
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[76557] | 38 | %ifndef IPRT_INCLUDED_x86_h
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| 39 | %define IPRT_INCLUDED_x86_h
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[76886] | 40 | %ifndef RT_WITHOUT_PRAGMA_ONCE
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| 41 | %endif
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[41300] | 42 | %ifndef VBOX_FOR_DTRACE_LIB
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[103930] | 43 | %ifndef __ASSEMBLER__
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| 44 | %else
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| 45 | %endif
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[41300] | 46 | %else
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| 47 | %endif
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[20742] | 48 | %ifdef RT_OS_SOLARIS
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| 49 | %endif
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[103930] | 50 | %ifndef __ASSEMBLER__
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| 51 | %ifndef VBOX_FOR_DTRACE_LIB
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| 52 | %endif
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| 53 | %ifndef VBOX_FOR_DTRACE_LIB
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| 54 | %endif
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| 55 | %ifndef VBOX_FOR_DTRACE_LIB
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| 56 | %endif
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[41300] | 57 | %endif
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[59965] | 58 | %define X86_EFL_CF RT_BIT_32(0)
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[48909] | 59 | %define X86_EFL_CF_BIT 0
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[59965] | 60 | %define X86_EFL_1 RT_BIT_32(1)
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| 61 | %define X86_EFL_PF RT_BIT_32(2)
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[96200] | 62 | %define X86_EFL_PF_BIT 2
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[59965] | 63 | %define X86_EFL_AF RT_BIT_32(4)
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[48909] | 64 | %define X86_EFL_AF_BIT 4
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[59965] | 65 | %define X86_EFL_ZF RT_BIT_32(6)
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[48909] | 66 | %define X86_EFL_ZF_BIT 6
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[59965] | 67 | %define X86_EFL_SF RT_BIT_32(7)
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[48909] | 68 | %define X86_EFL_SF_BIT 7
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[59965] | 69 | %define X86_EFL_TF RT_BIT_32(8)
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[96200] | 70 | %define X86_EFL_TF_BIT 8
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[59965] | 71 | %define X86_EFL_IF RT_BIT_32(9)
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[96200] | 72 | %define X86_EFL_IF_BIT 9
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[59965] | 73 | %define X86_EFL_DF RT_BIT_32(10)
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[96200] | 74 | %define X86_EFL_DF_BIT 10
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[59965] | 75 | %define X86_EFL_OF RT_BIT_32(11)
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[48909] | 76 | %define X86_EFL_OF_BIT 11
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[59965] | 77 | %define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
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| 78 | %define X86_EFL_NT RT_BIT_32(14)
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[96200] | 79 | %define X86_EFL_NT_BIT 14
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[59965] | 80 | %define X86_EFL_RF RT_BIT_32(16)
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[96200] | 81 | %define X86_EFL_RF_BIT 16
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[59965] | 82 | %define X86_EFL_VM RT_BIT_32(17)
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[96200] | 83 | %define X86_EFL_VM_BIT 17
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[59965] | 84 | %define X86_EFL_AC RT_BIT_32(18)
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[96200] | 85 | %define X86_EFL_AC_BIT 18
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[59965] | 86 | %define X86_EFL_VIF RT_BIT_32(19)
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[96200] | 87 | %define X86_EFL_VIF_BIT 19
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[59965] | 88 | %define X86_EFL_VIP RT_BIT_32(20)
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[96200] | 89 | %define X86_EFL_VIP_BIT 20
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[59965] | 90 | %define X86_EFL_ID RT_BIT_32(21)
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[96200] | 91 | %define X86_EFL_ID_BIT 21
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[47876] | 92 | %define X86_EFL_LIVE_MASK 0x003f7fd5
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| 93 | %define X86_EFL_RA1_MASK RT_BIT_32(1)
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[102126] | 94 | %define X86_EFL_RAZ_MASK 0xffc08028
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| 95 | %define X86_EFL_RAZ_LO_MASK 0x00008028
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[1] | 96 | %define X86_EFL_IOPL_SHIFT 12
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| 97 | %define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
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[47442] | 98 | %define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
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| 99 | | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
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[61316] | 100 | %define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
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| 101 | | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
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[48909] | 102 | %define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
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[103930] | 103 | %ifndef __ASSEMBLER__
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| 104 | %ifndef VBOX_FOR_DTRACE_LIB
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| 105 | %else
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| 106 | %endif
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| 107 | %ifndef VBOX_FOR_DTRACE_LIB
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| 108 | %else
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| 109 | %endif
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[41300] | 110 | %endif
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[20742] | 111 | %define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
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| 112 | %define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
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| 113 | %define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
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| 114 | %define X86_CPUID_VENDOR_AMD_EBX 0x68747541
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| 115 | %define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
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| 116 | %define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
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[42396] | 117 | %define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
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| 118 | %define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
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| 119 | %define X86_CPUID_VENDOR_VIA_EDX 0x48727561
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[76886] | 120 | %define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020
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| 121 | %define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961
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| 122 | %define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61
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[81605] | 123 | %define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948
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| 124 | %define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975
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| 125 | %define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e
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[59965] | 126 | %define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
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| 127 | %define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
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| 128 | %define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
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| 129 | %define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
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| 130 | %define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
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| 131 | %define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
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| 132 | %define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
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| 133 | %define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
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| 134 | %define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
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| 135 | %define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
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| 136 | %define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
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| 137 | %define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
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| 138 | %define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
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| 139 | %define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
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| 140 | %define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
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| 141 | %define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
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| 142 | %define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
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| 143 | %define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
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| 144 | %define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
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| 145 | %define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
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| 146 | %define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
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| 147 | %define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
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| 148 | %define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
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| 149 | %define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
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| 150 | %define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
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| 151 | %define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
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| 152 | %define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
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| 153 | %define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
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| 154 | %define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
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| 155 | %define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
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| 156 | %define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
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| 157 | %define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
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| 158 | %define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
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| 159 | %define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
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| 160 | %define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
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[60313] | 161 | %define X86_CPUID_FEATURE_EDX_PSE_BIT 3
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[59965] | 162 | %define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
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| 163 | %define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
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| 164 | %define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
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[60313] | 165 | %define X86_CPUID_FEATURE_EDX_PAE_BIT 6
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[59965] | 166 | %define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
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| 167 | %define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
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| 168 | %define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
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| 169 | %define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
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| 170 | %define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
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| 171 | %define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
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| 172 | %define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
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| 173 | %define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
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| 174 | %define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
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| 175 | %define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
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| 176 | %define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
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| 177 | %define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
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| 178 | %define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
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| 179 | %define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
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| 180 | %define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
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| 181 | %define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
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| 182 | %define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
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| 183 | %define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
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| 184 | %define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
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| 185 | %define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
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| 186 | %define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
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| 187 | %define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
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| 188 | %define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
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| 189 | %define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
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[103930] | 190 | %define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
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| 191 | %define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
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| 192 | %define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
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| 193 | %define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
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| 194 | %define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
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| 195 | %define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
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| 196 | %define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
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| 197 | %define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
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| 198 | %define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
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| 199 | %define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
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| 200 | %define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
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| 201 | %define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
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| 202 | %define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
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| 203 | %define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
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| 204 | %define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
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| 205 | %define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
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| 206 | %define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
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[59965] | 207 | %define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
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| 208 | %define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
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[61316] | 209 | %define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
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[59965] | 210 | %define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
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| 211 | %define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
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| 212 | %define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
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[61316] | 213 | %define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
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[59965] | 214 | %define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
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| 215 | %define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
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| 216 | %define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
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| 217 | %define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
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| 218 | %define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
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| 219 | %define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
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| 220 | %define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
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| 221 | %define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
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| 222 | %define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
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| 223 | %define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
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| 224 | %define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
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| 225 | %define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
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| 226 | %define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
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| 227 | %define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
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| 228 | %define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
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| 229 | %define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
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| 230 | %define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
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| 231 | %define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
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| 232 | %define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
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| 233 | %define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
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[75994] | 234 | %define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
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| 235 | %define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
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| 236 | %define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
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[102126] | 237 | %define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
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[75994] | 238 | %define X86_CPUID_STEXT_FEATURE_ECX_MAWAU 0x003e0000
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| 239 | %define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
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| 240 | %define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
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[87358] | 241 | %define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
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[102126] | 242 | %define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
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[70606] | 243 | %define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
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| 244 | %define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
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[76678] | 245 | %define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
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[70606] | 246 | %define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
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[103930] | 247 | %define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
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[87358] | 248 | %define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
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[59965] | 249 | %define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
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| 250 | %define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
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| 251 | %define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
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| 252 | %define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
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| 253 | %define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
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| 254 | %define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
|
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| 255 | %define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
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| 256 | %define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
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| 257 | %define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
|
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| 258 | %define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
|
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| 259 | %define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
|
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| 260 | %define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
|
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| 261 | %define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
|
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| 262 | %define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
|
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| 263 | %define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
|
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| 264 | %define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
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| 265 | %define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
|
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| 266 | %define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
|
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| 267 | %define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
|
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| 268 | %define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
|
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| 269 | %define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
|
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| 270 | %define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
|
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| 271 | %define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
|
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| 272 | %define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
|
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| 273 | %define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
|
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| 274 | %define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
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| 275 | %define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
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| 276 | %define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
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| 277 | %define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
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| 278 | %define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
|
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| 279 | %define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
|
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| 280 | %define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
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| 281 | %define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
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| 282 | %define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
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| 283 | %define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
|
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| 284 | %define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
|
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| 285 | %define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
|
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| 286 | %define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
|
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| 287 | %define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
|
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| 288 | %define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
|
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| 289 | %define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
|
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| 290 | %define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
|
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| 291 | %define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
|
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| 292 | %define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
|
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| 293 | %define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
|
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| 294 | %define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
|
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| 295 | %define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
|
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| 296 | %define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
|
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| 297 | %define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
|
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| 298 | %define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
|
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| 299 | %define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
|
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| 300 | %define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
|
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| 301 | %define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
|
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| 302 | %define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
|
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| 303 | %define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
|
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| 304 | %define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
|
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| 305 | %define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
|
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| 306 | %define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
|
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| 307 | %define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
|
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[87358] | 308 | %define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
|
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| 309 | %define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
|
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| 310 | %define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
|
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| 311 | %define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
|
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| 312 | %define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
|
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| 313 | %define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
|
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| 314 | %define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
|
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| 315 | %define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
|
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| 316 | %define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
|
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| 317 | %define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
|
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| 318 | %define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
|
---|
| 319 | %define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
|
---|
| 320 | %define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
|
---|
| 321 | %define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
|
---|
[66604] | 322 | %define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
|
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| 323 | %define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
|
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| 324 | %define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
|
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| 325 | %define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
|
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| 326 | %define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
|
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| 327 | %define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
|
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| 328 | %define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
|
---|
[70254] | 329 | %define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
|
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[66604] | 330 | %define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
|
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| 331 | %define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
|
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| 332 | %define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
|
---|
[69202] | 333 | %define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
|
---|
| 334 | %define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
|
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[87358] | 335 | %define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
|
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[102126] | 336 | %define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
|
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[96200] | 337 | %define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
|
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| 338 | %define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
|
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[102126] | 339 | %define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
|
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[96200] | 340 | %define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
|
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| 341 | %define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
|
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[102126] | 342 | %define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
|
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| 343 | %define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
|
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| 344 | %define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
|
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| 345 | %define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
|
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| 346 | %define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
|
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[59965] | 347 | %define X86_CR0_PE RT_BIT_32(0)
|
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| 348 | %define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
|
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[103930] | 349 | %define X86_CR0_PE_BIT 0
|
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[59965] | 350 | %define X86_CR0_MP RT_BIT_32(1)
|
---|
| 351 | %define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
|
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[103930] | 352 | %define X86_CR0_MP_BIT 1
|
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[59965] | 353 | %define X86_CR0_EM RT_BIT_32(2)
|
---|
| 354 | %define X86_CR0_EMULATE_FPU RT_BIT_32(2)
|
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[103930] | 355 | %define X86_CR0_EM_BIT 2
|
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[59965] | 356 | %define X86_CR0_TS RT_BIT_32(3)
|
---|
| 357 | %define X86_CR0_TASK_SWITCH RT_BIT_32(3)
|
---|
[103930] | 358 | %define X86_CR0_TS_BIT 3
|
---|
[59965] | 359 | %define X86_CR0_ET RT_BIT_32(4)
|
---|
| 360 | %define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
|
---|
[103930] | 361 | %define X86_CR0_ET_BIT 4
|
---|
[59965] | 362 | %define X86_CR0_NE RT_BIT_32(5)
|
---|
| 363 | %define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
|
---|
[103930] | 364 | %define X86_CR0_NE_BIT 5
|
---|
[59965] | 365 | %define X86_CR0_WP RT_BIT_32(16)
|
---|
| 366 | %define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
|
---|
[103930] | 367 | %define X86_CR0_WP_BIT 16
|
---|
[59965] | 368 | %define X86_CR0_AM RT_BIT_32(18)
|
---|
| 369 | %define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
|
---|
[103930] | 370 | %define X86_CR0_AM_BIT 18
|
---|
[59965] | 371 | %define X86_CR0_NW RT_BIT_32(29)
|
---|
| 372 | %define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
|
---|
[103930] | 373 | %define X86_CR0_NW_BIT 29
|
---|
[59965] | 374 | %define X86_CR0_CD RT_BIT_32(30)
|
---|
| 375 | %define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
|
---|
[103930] | 376 | %define X86_CR0_CD_BIT 30
|
---|
[59965] | 377 | %define X86_CR0_PG RT_BIT_32(31)
|
---|
| 378 | %define X86_CR0_PAGING RT_BIT_32(31)
|
---|
[75994] | 379 | %define X86_CR0_BIT_PG 31
|
---|
[59965] | 380 | %define X86_CR3_PWT RT_BIT_32(3)
|
---|
[103930] | 381 | %define X86_CR3_PWT_BIT 3
|
---|
[59965] | 382 | %define X86_CR3_PCD RT_BIT_32(4)
|
---|
[103930] | 383 | %define X86_CR3_PCD_BIT 4
|
---|
[1] | 384 | %define X86_CR3_PAGE_MASK (0xfffff000)
|
---|
| 385 | %define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
|
---|
[30969] | 386 | %define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
|
---|
[102126] | 387 | %define X86_CR3_EPT_PAGE_MASK 0x000ffffffffff000
|
---|
[59965] | 388 | %define X86_CR4_VME RT_BIT_32(0)
|
---|
[103930] | 389 | %define X86_CR4_VME_BIT 0
|
---|
[59965] | 390 | %define X86_CR4_PVI RT_BIT_32(1)
|
---|
[103930] | 391 | %define X86_CR4_PVI_BIT 1
|
---|
[59965] | 392 | %define X86_CR4_TSD RT_BIT_32(2)
|
---|
[103930] | 393 | %define X86_CR4_TSD_BIT 2
|
---|
[59965] | 394 | %define X86_CR4_DE RT_BIT_32(3)
|
---|
[103930] | 395 | %define X86_CR4_DE_BIT 3
|
---|
[59965] | 396 | %define X86_CR4_PSE RT_BIT_32(4)
|
---|
[103930] | 397 | %define X86_CR4_PSE_BIT 4
|
---|
[59965] | 398 | %define X86_CR4_PAE RT_BIT_32(5)
|
---|
[103930] | 399 | %define X86_CR4_PAE_BIT 5
|
---|
[59965] | 400 | %define X86_CR4_MCE RT_BIT_32(6)
|
---|
[103930] | 401 | %define X86_CR4_MCE_BIT 6
|
---|
[59965] | 402 | %define X86_CR4_PGE RT_BIT_32(7)
|
---|
[103930] | 403 | %define X86_CR4_PGE_BIT 7
|
---|
[59965] | 404 | %define X86_CR4_PCE RT_BIT_32(8)
|
---|
[103930] | 405 | %define X86_CR4_PCE_BIT 8
|
---|
[59965] | 406 | %define X86_CR4_OSFXSR RT_BIT_32(9)
|
---|
[103930] | 407 | %define X86_CR4_OSFXSR_BIT 9
|
---|
[59965] | 408 | %define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
|
---|
[103930] | 409 | %define X86_CR4_OSXMMEEXCPT_BIT 10
|
---|
[87358] | 410 | %define X86_CR4_UMIP RT_BIT_32(11)
|
---|
[103930] | 411 | %define X86_CR4_UMIP_BIT 11
|
---|
[59965] | 412 | %define X86_CR4_VMXE RT_BIT_32(13)
|
---|
[103930] | 413 | %define X86_CR4_VMXE_BIT 13
|
---|
[59965] | 414 | %define X86_CR4_SMXE RT_BIT_32(14)
|
---|
[103930] | 415 | %define X86_CR4_SMXE_BIT 14
|
---|
[75994] | 416 | %define X86_CR4_FSGSBASE RT_BIT_32(16)
|
---|
[103930] | 417 | %define X86_CR4_FSGSBASE_BIT 16
|
---|
[59965] | 418 | %define X86_CR4_PCIDE RT_BIT_32(17)
|
---|
[103930] | 419 | %define X86_CR4_PCIDE_BIT 17
|
---|
[59965] | 420 | %define X86_CR4_OSXSAVE RT_BIT_32(18)
|
---|
[103930] | 421 | %define X86_CR4_OSXSAVE_BIT 18
|
---|
[59965] | 422 | %define X86_CR4_SMEP RT_BIT_32(20)
|
---|
[103930] | 423 | %define X86_CR4_SMEP_BIt 20
|
---|
[59965] | 424 | %define X86_CR4_SMAP RT_BIT_32(21)
|
---|
[103930] | 425 | %define X86_CR4_SMAP_BIT 21
|
---|
[59965] | 426 | %define X86_CR4_PKE RT_BIT_32(22)
|
---|
[103930] | 427 | %define X86_CR4_PKE_BIT 22
|
---|
[87358] | 428 | %define X86_CR4_CET RT_BIT_32(23)
|
---|
[103930] | 429 | %define X86_CR4_CET_BIT 23
|
---|
[59965] | 430 | %define X86_DR6_B0 RT_BIT_32(0)
|
---|
| 431 | %define X86_DR6_B1 RT_BIT_32(1)
|
---|
| 432 | %define X86_DR6_B2 RT_BIT_32(2)
|
---|
| 433 | %define X86_DR6_B3 RT_BIT_32(3)
|
---|
[47442] | 434 | %define X86_DR6_B_MASK 0x0000000f
|
---|
[59965] | 435 | %define X86_DR6_BD RT_BIT_32(13)
|
---|
| 436 | %define X86_DR6_BS RT_BIT_32(14)
|
---|
| 437 | %define X86_DR6_BT RT_BIT_32(15)
|
---|
[75994] | 438 | %define X86_DR6_RTM RT_BIT_32(16)
|
---|
| 439 | %define X86_DR6_INIT_VAL 0xffff0ff0
|
---|
[47442] | 440 | %define X86_DR6_RA1_MASK 0xffff0ff0
|
---|
[75994] | 441 | %define X86_DR6_RA1_MASK_RTM 0xfffe0ff0
|
---|
[47442] | 442 | %define X86_DR6_RAZ_MASK RT_BIT_64(12)
|
---|
| 443 | %define X86_DR6_MBZ_MASK 0xffffffff00000000
|
---|
| 444 | %define X86_DR6_B(iBp) RT_BIT_64(iBp)
|
---|
[59965] | 445 | %define X86_DR7_L0 RT_BIT_32(0)
|
---|
| 446 | %define X86_DR7_G0 RT_BIT_32(1)
|
---|
| 447 | %define X86_DR7_L1 RT_BIT_32(2)
|
---|
| 448 | %define X86_DR7_G1 RT_BIT_32(3)
|
---|
| 449 | %define X86_DR7_L2 RT_BIT_32(4)
|
---|
| 450 | %define X86_DR7_G2 RT_BIT_32(5)
|
---|
| 451 | %define X86_DR7_L3 RT_BIT_32(6)
|
---|
| 452 | %define X86_DR7_G3 RT_BIT_32(7)
|
---|
| 453 | %define X86_DR7_LE RT_BIT_32(8)
|
---|
| 454 | %define X86_DR7_GE RT_BIT_32(9)
|
---|
[47876] | 455 | %define X86_DR7_LE_ALL 0x0000000000000055
|
---|
| 456 | %define X86_DR7_GE_ALL 0x00000000000000aa
|
---|
[75994] | 457 | %define X86_DR7_RTM RT_BIT_32(11)
|
---|
[59965] | 458 | %define X86_DR7_ICE_IR RT_BIT_32(12)
|
---|
| 459 | %define X86_DR7_GD RT_BIT_32(13)
|
---|
| 460 | %define X86_DR7_ICE_TR1 RT_BIT_32(14)
|
---|
| 461 | %define X86_DR7_ICE_TR2 RT_BIT_32(15)
|
---|
[1] | 462 | %define X86_DR7_RW0_MASK (3 << 16)
|
---|
| 463 | %define X86_DR7_LEN0_MASK (3 << 18)
|
---|
| 464 | %define X86_DR7_RW1_MASK (3 << 20)
|
---|
| 465 | %define X86_DR7_LEN1_MASK (3 << 22)
|
---|
| 466 | %define X86_DR7_RW2_MASK (3 << 24)
|
---|
| 467 | %define X86_DR7_LEN2_MASK (3 << 26)
|
---|
| 468 | %define X86_DR7_RW3_MASK (3 << 28)
|
---|
| 469 | %define X86_DR7_LEN3_MASK (3 << 30)
|
---|
[59965] | 470 | %define X86_DR7_RA1_MASK RT_BIT_32(10)
|
---|
[47442] | 471 | %define X86_DR7_RAZ_MASK 0x0000d800
|
---|
| 472 | %define X86_DR7_MBZ_MASK 0xffffffff00000000
|
---|
[30736] | 473 | %define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
|
---|
| 474 | %define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
|
---|
[47442] | 475 | %define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
|
---|
[1] | 476 | %define X86_DR7_RW_EO 0
|
---|
| 477 | %define X86_DR7_RW_WO 1
|
---|
| 478 | %define X86_DR7_RW_IO 2
|
---|
| 479 | %define X86_DR7_RW_RW 3
|
---|
| 480 | %define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
|
---|
[47442] | 481 | %define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
|
---|
| 482 | %define X86_DR7_RW_ALL_MASKS 0x33330000
|
---|
[55254] | 483 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
[102126] | 484 | %define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (0x000f0000 << ((a_iBp) * 4))) == 0 )
|
---|
| 485 | %define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
|
---|
| 486 | ( ((a_uDR7) & (0x03 << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
|
---|
| 487 | %define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
|
---|
| 488 | ( (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
|
---|
| 489 | || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
|
---|
| 490 | || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
|
---|
| 491 | || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
|
---|
[55254] | 492 | %define X86_DR7_ANY_RW_IO(uDR7) \
|
---|
[47442] | 493 | ( ( 0x22220000 & (uDR7) )
|
---|
[55254] | 494 | %endif
|
---|
[1] | 495 | %define X86_DR7_LEN_BYTE 0
|
---|
| 496 | %define X86_DR7_LEN_WORD 1
|
---|
[13702] | 497 | %define X86_DR7_LEN_QWORD 2
|
---|
[1] | 498 | %define X86_DR7_LEN_DWORD 3
|
---|
| 499 | %define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
|
---|
[47442] | 500 | %define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
|
---|
| 501 | %define X86_DR7_ENABLED_MASK 0x000000ff
|
---|
[47876] | 502 | %define X86_DR7_LEN_ALL_MASKS 0xcccc0000
|
---|
| 503 | %define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
|
---|
[13702] | 504 | %define X86_DR7_INIT_VAL 0x400
|
---|
[48909] | 505 | %define MSR_P5_MC_ADDR 0x00000000
|
---|
| 506 | %define MSR_P5_MC_TYPE 0x00000001
|
---|
[10375] | 507 | %define MSR_IA32_TSC 0x10
|
---|
[48909] | 508 | %define MSR_IA32_CESR 0x00000011
|
---|
| 509 | %define MSR_IA32_CTR0 0x00000012
|
---|
| 510 | %define MSR_IA32_CTR1 0x00000013
|
---|
[13702] | 511 | %define MSR_IA32_PLATFORM_ID 0x17
|
---|
[20742] | 512 | %ifndef MSR_IA32_APICBASE
|
---|
[47876] | 513 | %define MSR_IA32_APICBASE 0x1b
|
---|
| 514 | %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
|
---|
| 515 | %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
|
---|
| 516 | %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
|
---|
| 517 | %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
|
---|
[61316] | 518 | %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
|
---|
| 519 | %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
|
---|
[20742] | 520 | %endif
|
---|
[103930] | 521 | %define MSR_MEMORY_CTRL 0x33
|
---|
| 522 | %define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
|
---|
| 523 | %define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
|
---|
| 524 | %define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
|
---|
[48909] | 525 | %define MSR_CORE_THREAD_COUNT 0x35
|
---|
[75994] | 526 | %define MSR_IA32_FEATURE_CONTROL 0x3A
|
---|
| 527 | %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
|
---|
| 528 | %define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
|
---|
| 529 | %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
|
---|
| 530 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
|
---|
| 531 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
|
---|
| 532 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
|
---|
| 533 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
|
---|
| 534 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
|
---|
| 535 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
|
---|
| 536 | %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
|
---|
| 537 | %define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
|
---|
| 538 | %define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
|
---|
| 539 | %define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
|
---|
| 540 | %define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
|
---|
[53626] | 541 | %define MSR_IA32_TSC_ADJUST 0x3B
|
---|
[70606] | 542 | %define MSR_IA32_SPEC_CTRL 0x48
|
---|
| 543 | %define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
|
---|
| 544 | %define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
|
---|
[87358] | 545 | %define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
|
---|
[70606] | 546 | %define MSR_IA32_PRED_CMD 0x49
|
---|
| 547 | %define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
|
---|
[13702] | 548 | %define MSR_IA32_BIOS_UPDT_TRIG 0x79
|
---|
| 549 | %define MSR_IA32_BIOS_SIGN_ID 0x8B
|
---|
[59388] | 550 | %define MSR_IA32_SMM_MONITOR_CTL 0x9B
|
---|
[75994] | 551 | %define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
|
---|
| 552 | %define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
|
---|
| 553 | %define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & 0xfffff)
|
---|
| 554 | %define MSR_IA32_SMBASE 0x9E
|
---|
[28828] | 555 | %define MSR_IA32_PMC0 0xC1
|
---|
| 556 | %define MSR_IA32_PMC1 0xC2
|
---|
| 557 | %define MSR_IA32_PMC2 0xC3
|
---|
| 558 | %define MSR_IA32_PMC3 0xC4
|
---|
[87358] | 559 | %define MSR_IA32_PMC4 0xC5
|
---|
| 560 | %define MSR_IA32_PMC5 0xC6
|
---|
| 561 | %define MSR_IA32_PMC6 0xC7
|
---|
| 562 | %define MSR_IA32_PMC7 0xC8
|
---|
[28828] | 563 | %define MSR_IA32_PLATFORM_INFO 0xCE
|
---|
[103930] | 564 | %define MSR_IA32_CORE_CAPABILITIES 0xCF
|
---|
| 565 | %define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
|
---|
| 566 | %define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
|
---|
| 567 | %define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
|
---|
| 568 | %define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
|
---|
| 569 | %define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
|
---|
| 570 | %define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
|
---|
| 571 | %define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
|
---|
[28828] | 572 | %define MSR_IA32_FSB_CLOCK_STS 0xCD
|
---|
[48909] | 573 | %define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
|
---|
| 574 | %define MSR_IA32_MPERF 0xE7
|
---|
| 575 | %define MSR_IA32_APERF 0xE8
|
---|
[10375] | 576 | %define MSR_IA32_MTRR_CAP 0xFE
|
---|
[102126] | 577 | %define MSR_IA32_MTRR_CAP_VCNT_MASK 0x00000000000000ff
|
---|
| 578 | %define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
|
---|
| 579 | %define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
|
---|
| 580 | %define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
|
---|
| 581 | %define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
|
---|
[103930] | 582 | %ifndef __ASSEMBLER__
|
---|
| 583 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 584 | %endif
|
---|
[102126] | 585 | %endif
|
---|
| 586 | %define X86_MTRR_MT_UC 0
|
---|
| 587 | %define X86_MTRR_MT_WC 1
|
---|
| 588 | %define X86_MTRR_MT_WT 4
|
---|
| 589 | %define X86_MTRR_MT_WP 5
|
---|
| 590 | %define X86_MTRR_MT_WB 6
|
---|
[75994] | 591 | %define MSR_IA32_ARCH_CAPABILITIES 0x10a
|
---|
[76678] | 592 | %define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
|
---|
| 593 | %define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
|
---|
| 594 | %define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
|
---|
| 595 | %define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
|
---|
[87358] | 596 | %define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
|
---|
[76678] | 597 | %define MSR_IA32_FLUSH_CMD 0x10b
|
---|
| 598 | %define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
|
---|
[48909] | 599 | %define MSR_BBL_CR_CTL3 0x11e
|
---|
[20742] | 600 | %ifndef MSR_IA32_SYSENTER_CS
|
---|
[1] | 601 | %define MSR_IA32_SYSENTER_CS 0x174
|
---|
| 602 | %define MSR_IA32_SYSENTER_ESP 0x175
|
---|
| 603 | %define MSR_IA32_SYSENTER_EIP 0x176
|
---|
[20742] | 604 | %endif
|
---|
[48909] | 605 | %define MSR_IA32_MCG_CAP 0x179
|
---|
| 606 | %define MSR_IA32_MCG_STATUS 0x17A
|
---|
| 607 | %define MSR_IA32_MCG_CTRL 0x17B
|
---|
[9768] | 608 | %define MSR_IA32_CR_PAT 0x277
|
---|
[75994] | 609 | %define MSR_IA32_CR_PAT_INIT_VAL 0x0007040600070406
|
---|
[102126] | 610 | %define MSR_IA32_PAT_MT_UC 0
|
---|
| 611 | %define MSR_IA32_PAT_MT_WC 1
|
---|
| 612 | %define MSR_IA32_PAT_MT_RSVD_2 2
|
---|
| 613 | %define MSR_IA32_PAT_MT_RSVD_3 3
|
---|
| 614 | %define MSR_IA32_PAT_MT_WT 4
|
---|
| 615 | %define MSR_IA32_PAT_MT_WP 5
|
---|
| 616 | %define MSR_IA32_PAT_MT_WB 6
|
---|
| 617 | %define MSR_IA32_PAT_MT_UCD 7
|
---|
[18842] | 618 | %define MSR_IA32_PERFEVTSEL0 0x186
|
---|
| 619 | %define MSR_IA32_PERFEVTSEL1 0x187
|
---|
[87358] | 620 | %define MSR_IA32_PERFEVTSEL2 0x188
|
---|
| 621 | %define MSR_IA32_PERFEVTSEL3 0x189
|
---|
[48909] | 622 | %define MSR_FLEX_RATIO 0x194
|
---|
[18842] | 623 | %define MSR_IA32_PERF_STATUS 0x198
|
---|
| 624 | %define MSR_IA32_PERF_CTL 0x199
|
---|
[28828] | 625 | %define MSR_IA32_THERM_STATUS 0x19c
|
---|
[87358] | 626 | %define MSR_OFFCORE_RSP_0 0x1a6
|
---|
| 627 | %define MSR_OFFCORE_RSP_1 0x1a7
|
---|
[37968] | 628 | %define MSR_IA32_MISC_ENABLE 0x1A0
|
---|
[50255] | 629 | %define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
|
---|
| 630 | %define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
|
---|
| 631 | %define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
|
---|
| 632 | %define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
|
---|
| 633 | %define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
|
---|
| 634 | %define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
|
---|
| 635 | %define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
|
---|
| 636 | %define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
|
---|
| 637 | %define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
|
---|
| 638 | %define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
|
---|
[48909] | 639 | %define MSR_IA32_DEBUGCTL 0x000001d9
|
---|
[70459] | 640 | %define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
|
---|
| 641 | %define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
|
---|
| 642 | %define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
|
---|
| 643 | %define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
|
---|
| 644 | %define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
|
---|
| 645 | %define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
|
---|
| 646 | %define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
|
---|
| 647 | %define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
|
---|
| 648 | %define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
|
---|
| 649 | %define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
|
---|
| 650 | %define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
|
---|
| 651 | %define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
|
---|
| 652 | %define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
|
---|
| 653 | %define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
|
---|
| 654 | %define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
|
---|
[75994] | 655 | %define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
|
---|
| 656 | | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
|
---|
| 657 | | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
|
---|
| 658 | | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
|
---|
| 659 | | MSR_IA32_DEBUGCTL_RTM)
|
---|
[87358] | 660 | %define MSR_P4_LASTBRANCH_0 0x1db
|
---|
| 661 | %define MSR_P4_LASTBRANCH_1 0x1dc
|
---|
| 662 | %define MSR_P4_LASTBRANCH_2 0x1dd
|
---|
| 663 | %define MSR_P4_LASTBRANCH_3 0x1de
|
---|
| 664 | %define MSR_P4_LASTBRANCH_TOS 0x1da
|
---|
| 665 | %define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
|
---|
| 666 | %define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
|
---|
| 667 | %define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
|
---|
| 668 | %define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
|
---|
| 669 | %define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
|
---|
| 670 | %define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
|
---|
| 671 | %define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
|
---|
| 672 | %define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
|
---|
| 673 | %define MSR_CORE2_LASTBRANCH_TOS 0x1c9
|
---|
| 674 | %define MSR_LASTBRANCH_0_FROM_IP 0x680
|
---|
| 675 | %define MSR_LASTBRANCH_1_FROM_IP 0x681
|
---|
| 676 | %define MSR_LASTBRANCH_2_FROM_IP 0x682
|
---|
| 677 | %define MSR_LASTBRANCH_3_FROM_IP 0x683
|
---|
| 678 | %define MSR_LASTBRANCH_4_FROM_IP 0x684
|
---|
| 679 | %define MSR_LASTBRANCH_5_FROM_IP 0x685
|
---|
| 680 | %define MSR_LASTBRANCH_6_FROM_IP 0x686
|
---|
| 681 | %define MSR_LASTBRANCH_7_FROM_IP 0x687
|
---|
| 682 | %define MSR_LASTBRANCH_8_FROM_IP 0x688
|
---|
| 683 | %define MSR_LASTBRANCH_9_FROM_IP 0x689
|
---|
| 684 | %define MSR_LASTBRANCH_10_FROM_IP 0x68a
|
---|
| 685 | %define MSR_LASTBRANCH_11_FROM_IP 0x68b
|
---|
| 686 | %define MSR_LASTBRANCH_12_FROM_IP 0x68c
|
---|
| 687 | %define MSR_LASTBRANCH_13_FROM_IP 0x68d
|
---|
| 688 | %define MSR_LASTBRANCH_14_FROM_IP 0x68e
|
---|
| 689 | %define MSR_LASTBRANCH_15_FROM_IP 0x68f
|
---|
| 690 | %define MSR_LASTBRANCH_16_FROM_IP 0x690
|
---|
| 691 | %define MSR_LASTBRANCH_17_FROM_IP 0x691
|
---|
| 692 | %define MSR_LASTBRANCH_18_FROM_IP 0x692
|
---|
| 693 | %define MSR_LASTBRANCH_19_FROM_IP 0x693
|
---|
| 694 | %define MSR_LASTBRANCH_20_FROM_IP 0x694
|
---|
| 695 | %define MSR_LASTBRANCH_21_FROM_IP 0x695
|
---|
| 696 | %define MSR_LASTBRANCH_22_FROM_IP 0x696
|
---|
| 697 | %define MSR_LASTBRANCH_23_FROM_IP 0x697
|
---|
| 698 | %define MSR_LASTBRANCH_24_FROM_IP 0x698
|
---|
| 699 | %define MSR_LASTBRANCH_25_FROM_IP 0x699
|
---|
| 700 | %define MSR_LASTBRANCH_26_FROM_IP 0x69a
|
---|
| 701 | %define MSR_LASTBRANCH_27_FROM_IP 0x69b
|
---|
| 702 | %define MSR_LASTBRANCH_28_FROM_IP 0x69c
|
---|
| 703 | %define MSR_LASTBRANCH_29_FROM_IP 0x69d
|
---|
| 704 | %define MSR_LASTBRANCH_30_FROM_IP 0x69e
|
---|
| 705 | %define MSR_LASTBRANCH_31_FROM_IP 0x69f
|
---|
| 706 | %define MSR_LASTBRANCH_0_TO_IP 0x6c0
|
---|
| 707 | %define MSR_LASTBRANCH_1_TO_IP 0x6c1
|
---|
| 708 | %define MSR_LASTBRANCH_2_TO_IP 0x6c2
|
---|
| 709 | %define MSR_LASTBRANCH_3_TO_IP 0x6c3
|
---|
| 710 | %define MSR_LASTBRANCH_4_TO_IP 0x6c4
|
---|
| 711 | %define MSR_LASTBRANCH_5_TO_IP 0x6c5
|
---|
| 712 | %define MSR_LASTBRANCH_6_TO_IP 0x6c6
|
---|
| 713 | %define MSR_LASTBRANCH_7_TO_IP 0x6c7
|
---|
| 714 | %define MSR_LASTBRANCH_8_TO_IP 0x6c8
|
---|
| 715 | %define MSR_LASTBRANCH_9_TO_IP 0x6c9
|
---|
| 716 | %define MSR_LASTBRANCH_10_TO_IP 0x6ca
|
---|
| 717 | %define MSR_LASTBRANCH_11_TO_IP 0x6cb
|
---|
| 718 | %define MSR_LASTBRANCH_12_TO_IP 0x6cc
|
---|
| 719 | %define MSR_LASTBRANCH_13_TO_IP 0x6cd
|
---|
| 720 | %define MSR_LASTBRANCH_14_TO_IP 0x6ce
|
---|
| 721 | %define MSR_LASTBRANCH_15_TO_IP 0x6cf
|
---|
| 722 | %define MSR_LASTBRANCH_16_TO_IP 0x6d0
|
---|
| 723 | %define MSR_LASTBRANCH_17_TO_IP 0x6d1
|
---|
| 724 | %define MSR_LASTBRANCH_18_TO_IP 0x6d2
|
---|
| 725 | %define MSR_LASTBRANCH_19_TO_IP 0x6d3
|
---|
| 726 | %define MSR_LASTBRANCH_20_TO_IP 0x6d4
|
---|
| 727 | %define MSR_LASTBRANCH_21_TO_IP 0x6d5
|
---|
| 728 | %define MSR_LASTBRANCH_22_TO_IP 0x6d6
|
---|
| 729 | %define MSR_LASTBRANCH_23_TO_IP 0x6d7
|
---|
| 730 | %define MSR_LASTBRANCH_24_TO_IP 0x6d8
|
---|
| 731 | %define MSR_LASTBRANCH_25_TO_IP 0x6d9
|
---|
| 732 | %define MSR_LASTBRANCH_26_TO_IP 0x6da
|
---|
| 733 | %define MSR_LASTBRANCH_27_TO_IP 0x6db
|
---|
| 734 | %define MSR_LASTBRANCH_28_TO_IP 0x6dc
|
---|
| 735 | %define MSR_LASTBRANCH_29_TO_IP 0x6dd
|
---|
| 736 | %define MSR_LASTBRANCH_30_TO_IP 0x6de
|
---|
| 737 | %define MSR_LASTBRANCH_31_TO_IP 0x6df
|
---|
[96200] | 738 | %define MSR_LASTBRANCH_0_INFO 0xdc0
|
---|
| 739 | %define MSR_LASTBRANCH_1_INFO 0xdc1
|
---|
| 740 | %define MSR_LASTBRANCH_2_INFO 0xdc2
|
---|
| 741 | %define MSR_LASTBRANCH_3_INFO 0xdc3
|
---|
| 742 | %define MSR_LASTBRANCH_4_INFO 0xdc4
|
---|
| 743 | %define MSR_LASTBRANCH_5_INFO 0xdc5
|
---|
| 744 | %define MSR_LASTBRANCH_6_INFO 0xdc6
|
---|
| 745 | %define MSR_LASTBRANCH_7_INFO 0xdc7
|
---|
| 746 | %define MSR_LASTBRANCH_8_INFO 0xdc8
|
---|
| 747 | %define MSR_LASTBRANCH_9_INFO 0xdc9
|
---|
| 748 | %define MSR_LASTBRANCH_10_INFO 0xdca
|
---|
| 749 | %define MSR_LASTBRANCH_11_INFO 0xdcb
|
---|
| 750 | %define MSR_LASTBRANCH_12_INFO 0xdcc
|
---|
| 751 | %define MSR_LASTBRANCH_13_INFO 0xdcd
|
---|
| 752 | %define MSR_LASTBRANCH_14_INFO 0xdce
|
---|
| 753 | %define MSR_LASTBRANCH_15_INFO 0xdcf
|
---|
| 754 | %define MSR_LASTBRANCH_16_INFO 0xdd0
|
---|
| 755 | %define MSR_LASTBRANCH_17_INFO 0xdd1
|
---|
| 756 | %define MSR_LASTBRANCH_18_INFO 0xdd2
|
---|
| 757 | %define MSR_LASTBRANCH_19_INFO 0xdd3
|
---|
| 758 | %define MSR_LASTBRANCH_20_INFO 0xdd4
|
---|
| 759 | %define MSR_LASTBRANCH_21_INFO 0xdd5
|
---|
| 760 | %define MSR_LASTBRANCH_22_INFO 0xdd6
|
---|
| 761 | %define MSR_LASTBRANCH_23_INFO 0xdd7
|
---|
| 762 | %define MSR_LASTBRANCH_24_INFO 0xdd8
|
---|
| 763 | %define MSR_LASTBRANCH_25_INFO 0xdd9
|
---|
| 764 | %define MSR_LASTBRANCH_26_INFO 0xdda
|
---|
| 765 | %define MSR_LASTBRANCH_27_INFO 0xddb
|
---|
| 766 | %define MSR_LASTBRANCH_28_INFO 0xddc
|
---|
| 767 | %define MSR_LASTBRANCH_29_INFO 0xddd
|
---|
| 768 | %define MSR_LASTBRANCH_30_INFO 0xdde
|
---|
| 769 | %define MSR_LASTBRANCH_31_INFO 0xddf
|
---|
| 770 | %define MSR_LASTBRANCH_SELECT 0x1c8
|
---|
[87358] | 771 | %define MSR_LASTBRANCH_TOS 0x1c9
|
---|
[96200] | 772 | %define MSR_LER_FROM_IP 0x1dd
|
---|
| 773 | %define MSR_LER_TO_IP 0x1de
|
---|
[87358] | 774 | %define MSR_IA32_TSX_CTRL 0x122
|
---|
| 775 | %define MSR_IA32_MTRR_PHYSBASE0 0x200
|
---|
| 776 | %define MSR_IA32_MTRR_PHYSMASK0 0x201
|
---|
| 777 | %define MSR_IA32_MTRR_PHYSBASE1 0x202
|
---|
| 778 | %define MSR_IA32_MTRR_PHYSMASK1 0x203
|
---|
| 779 | %define MSR_IA32_MTRR_PHYSBASE2 0x204
|
---|
| 780 | %define MSR_IA32_MTRR_PHYSMASK2 0x205
|
---|
| 781 | %define MSR_IA32_MTRR_PHYSBASE3 0x206
|
---|
| 782 | %define MSR_IA32_MTRR_PHYSMASK3 0x207
|
---|
| 783 | %define MSR_IA32_MTRR_PHYSBASE4 0x208
|
---|
| 784 | %define MSR_IA32_MTRR_PHYSMASK4 0x209
|
---|
| 785 | %define MSR_IA32_MTRR_PHYSBASE5 0x20a
|
---|
| 786 | %define MSR_IA32_MTRR_PHYSMASK5 0x20b
|
---|
| 787 | %define MSR_IA32_MTRR_PHYSBASE6 0x20c
|
---|
| 788 | %define MSR_IA32_MTRR_PHYSMASK6 0x20d
|
---|
| 789 | %define MSR_IA32_MTRR_PHYSBASE7 0x20e
|
---|
| 790 | %define MSR_IA32_MTRR_PHYSMASK7 0x20f
|
---|
| 791 | %define MSR_IA32_MTRR_PHYSBASE8 0x210
|
---|
| 792 | %define MSR_IA32_MTRR_PHYSMASK8 0x211
|
---|
| 793 | %define MSR_IA32_MTRR_PHYSBASE9 0x212
|
---|
| 794 | %define MSR_IA32_MTRR_PHYSMASK9 0x213
|
---|
| 795 | %define MSR_IA32_MTRR_FIX64K_00000 0x250
|
---|
| 796 | %define MSR_IA32_MTRR_FIX16K_80000 0x258
|
---|
| 797 | %define MSR_IA32_MTRR_FIX16K_A0000 0x259
|
---|
| 798 | %define MSR_IA32_MTRR_FIX4K_C0000 0x268
|
---|
| 799 | %define MSR_IA32_MTRR_FIX4K_C8000 0x269
|
---|
| 800 | %define MSR_IA32_MTRR_FIX4K_D0000 0x26a
|
---|
| 801 | %define MSR_IA32_MTRR_FIX4K_D8000 0x26b
|
---|
| 802 | %define MSR_IA32_MTRR_FIX4K_E0000 0x26c
|
---|
| 803 | %define MSR_IA32_MTRR_FIX4K_E8000 0x26d
|
---|
| 804 | %define MSR_IA32_MTRR_FIX4K_F0000 0x26e
|
---|
| 805 | %define MSR_IA32_MTRR_FIX4K_F8000 0x26f
|
---|
[10375] | 806 | %define MSR_IA32_MTRR_DEF_TYPE 0x2FF
|
---|
[102126] | 807 | %define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
|
---|
| 808 | %define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
|
---|
| 809 | %define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
|
---|
| 810 | %define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
|
---|
| 811 | | MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
|
---|
| 812 | | MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
|
---|
| 813 | %define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
|
---|
[103930] | 814 | %define MSR_IA32_MTRR_PHYSBASE_MT_MASK 0xff
|
---|
[61316] | 815 | %define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
|
---|
| 816 | %define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
|
---|
| 817 | %define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
|
---|
| 818 | %define MSR_IA32_PEBS_ENABLE 0x3F1
|
---|
[13702] | 819 | %define MSR_IA32_MC0_CTL 0x400
|
---|
| 820 | %define MSR_IA32_MC0_STATUS 0x401
|
---|
[75994] | 821 | %define MSR_IA32_VMX_BASIC 0x480
|
---|
[1] | 822 | %define MSR_IA32_VMX_PINBASED_CTLS 0x481
|
---|
| 823 | %define MSR_IA32_VMX_PROCBASED_CTLS 0x482
|
---|
| 824 | %define MSR_IA32_VMX_EXIT_CTLS 0x483
|
---|
| 825 | %define MSR_IA32_VMX_ENTRY_CTLS 0x484
|
---|
| 826 | %define MSR_IA32_VMX_MISC 0x485
|
---|
| 827 | %define MSR_IA32_VMX_CR0_FIXED0 0x486
|
---|
| 828 | %define MSR_IA32_VMX_CR0_FIXED1 0x487
|
---|
| 829 | %define MSR_IA32_VMX_CR4_FIXED0 0x488
|
---|
| 830 | %define MSR_IA32_VMX_CR4_FIXED1 0x489
|
---|
| 831 | %define MSR_IA32_VMX_VMCS_ENUM 0x48A
|
---|
[13702] | 832 | %define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
|
---|
[45701] | 833 | %define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
|
---|
[66148] | 834 | %define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
|
---|
| 835 | %define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
|
---|
| 836 | %define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
|
---|
| 837 | %define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
|
---|
[75994] | 838 | %define MSR_IA32_VMX_VMFUNC 0x491
|
---|
[96200] | 839 | %define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
|
---|
[102126] | 840 | %define MSR_IA32_VMX_EXIT_CTLS2 0x493
|
---|
[75994] | 841 | %define MSR_IA32_RTIT_CTL 0x570
|
---|
[25559] | 842 | %define MSR_IA32_DS_AREA 0x600
|
---|
[48909] | 843 | %define MSR_RAPL_POWER_UNIT 0x606
|
---|
[87358] | 844 | %define MSR_PKGC3_IRTL 0x60a
|
---|
| 845 | %define MSR_PKGC_IRTL1 0x60b
|
---|
| 846 | %define MSR_PKGC_IRTL2 0x60c
|
---|
| 847 | %define MSR_PKG_C2_RESIDENCY 0x60d
|
---|
| 848 | %define MSR_PKG_POWER_LIMIT 0x610
|
---|
| 849 | %define MSR_PKG_ENERGY_STATUS 0x611
|
---|
| 850 | %define MSR_PKG_PERF_STATUS 0x613
|
---|
| 851 | %define MSR_PKG_POWER_INFO 0x614
|
---|
| 852 | %define MSR_DRAM_POWER_LIMIT 0x618
|
---|
| 853 | %define MSR_DRAM_ENERGY_STATUS 0x619
|
---|
| 854 | %define MSR_DRAM_PERF_STATUS 0x61b
|
---|
| 855 | %define MSR_DRAM_POWER_INFO 0x61c
|
---|
| 856 | %define MSR_PKG_C10_RESIDENCY 0x632
|
---|
| 857 | %define MSR_PP0_ENERGY_STATUS 0x639
|
---|
| 858 | %define MSR_PP1_ENERGY_STATUS 0x641
|
---|
| 859 | %define MSR_TURBO_ACTIVATION_RATIO 0x64c
|
---|
| 860 | %define MSR_CORE_PERF_LIMIT_REASONS 0x64f
|
---|
[102126] | 861 | %define MSR_IA32_U_CET 0x6a0
|
---|
| 862 | %define MSR_IA32_S_CET 0x6a2
|
---|
| 863 | %define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
|
---|
| 864 | %define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
|
---|
| 865 | %define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
|
---|
| 866 | %define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
|
---|
| 867 | %define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
|
---|
| 868 | %define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
|
---|
| 869 | %define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
|
---|
| 870 | %define MSR_IA32_CET_TRACKER RT_BIT_64(11)
|
---|
| 871 | %define MSR_IA32_CET_EB_LEG_BITMAP_BASE 0xfffffffffffff000
|
---|
[43974] | 872 | %define MSR_IA32_X2APIC_START 0x800
|
---|
[59965] | 873 | %define MSR_IA32_X2APIC_ID 0x802
|
---|
| 874 | %define MSR_IA32_X2APIC_VERSION 0x803
|
---|
[43974] | 875 | %define MSR_IA32_X2APIC_TPR 0x808
|
---|
[59965] | 876 | %define MSR_IA32_X2APIC_PPR 0x80A
|
---|
| 877 | %define MSR_IA32_X2APIC_EOI 0x80B
|
---|
| 878 | %define MSR_IA32_X2APIC_LDR 0x80D
|
---|
| 879 | %define MSR_IA32_X2APIC_SVR 0x80F
|
---|
| 880 | %define MSR_IA32_X2APIC_ISR0 0x810
|
---|
| 881 | %define MSR_IA32_X2APIC_ISR1 0x811
|
---|
| 882 | %define MSR_IA32_X2APIC_ISR2 0x812
|
---|
| 883 | %define MSR_IA32_X2APIC_ISR3 0x813
|
---|
| 884 | %define MSR_IA32_X2APIC_ISR4 0x814
|
---|
| 885 | %define MSR_IA32_X2APIC_ISR5 0x815
|
---|
| 886 | %define MSR_IA32_X2APIC_ISR6 0x816
|
---|
| 887 | %define MSR_IA32_X2APIC_ISR7 0x817
|
---|
| 888 | %define MSR_IA32_X2APIC_TMR0 0x818
|
---|
| 889 | %define MSR_IA32_X2APIC_TMR1 0x819
|
---|
| 890 | %define MSR_IA32_X2APIC_TMR2 0x81A
|
---|
| 891 | %define MSR_IA32_X2APIC_TMR3 0x81B
|
---|
| 892 | %define MSR_IA32_X2APIC_TMR4 0x81C
|
---|
| 893 | %define MSR_IA32_X2APIC_TMR5 0x81D
|
---|
| 894 | %define MSR_IA32_X2APIC_TMR6 0x81E
|
---|
| 895 | %define MSR_IA32_X2APIC_TMR7 0x81F
|
---|
| 896 | %define MSR_IA32_X2APIC_IRR0 0x820
|
---|
| 897 | %define MSR_IA32_X2APIC_IRR1 0x821
|
---|
| 898 | %define MSR_IA32_X2APIC_IRR2 0x822
|
---|
| 899 | %define MSR_IA32_X2APIC_IRR3 0x823
|
---|
| 900 | %define MSR_IA32_X2APIC_IRR4 0x824
|
---|
| 901 | %define MSR_IA32_X2APIC_IRR5 0x825
|
---|
| 902 | %define MSR_IA32_X2APIC_IRR6 0x826
|
---|
| 903 | %define MSR_IA32_X2APIC_IRR7 0x827
|
---|
| 904 | %define MSR_IA32_X2APIC_ESR 0x828
|
---|
| 905 | %define MSR_IA32_X2APIC_LVT_CMCI 0x82F
|
---|
| 906 | %define MSR_IA32_X2APIC_ICR 0x830
|
---|
| 907 | %define MSR_IA32_X2APIC_LVT_TIMER 0x832
|
---|
| 908 | %define MSR_IA32_X2APIC_LVT_THERMAL 0x833
|
---|
| 909 | %define MSR_IA32_X2APIC_LVT_PERF 0x834
|
---|
| 910 | %define MSR_IA32_X2APIC_LVT_LINT0 0x835
|
---|
| 911 | %define MSR_IA32_X2APIC_LVT_LINT1 0x836
|
---|
| 912 | %define MSR_IA32_X2APIC_LVT_ERROR 0x837
|
---|
| 913 | %define MSR_IA32_X2APIC_TIMER_ICR 0x838
|
---|
| 914 | %define MSR_IA32_X2APIC_TIMER_CCR 0x839
|
---|
[60087] | 915 | %define MSR_IA32_X2APIC_TIMER_DCR 0x83E
|
---|
[59965] | 916 | %define MSR_IA32_X2APIC_SELF_IPI 0x83F
|
---|
[87358] | 917 | %define MSR_IA32_X2APIC_END 0x8FF
|
---|
[60087] | 918 | %define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
|
---|
| 919 | %define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
|
---|
[1] | 920 | %define MSR_K6_EFER 0xc0000080
|
---|
[59965] | 921 | %define MSR_K6_EFER_SCE RT_BIT_32(0)
|
---|
| 922 | %define MSR_K6_EFER_LME RT_BIT_32(8)
|
---|
[75994] | 923 | %define MSR_K6_EFER_BIT_LME 8
|
---|
[59965] | 924 | %define MSR_K6_EFER_LMA RT_BIT_32(10)
|
---|
[75994] | 925 | %define MSR_K6_EFER_BIT_LMA 10
|
---|
[59965] | 926 | %define MSR_K6_EFER_NXE RT_BIT_32(11)
|
---|
[66148] | 927 | %define MSR_K6_EFER_BIT_NXE 11
|
---|
[59965] | 928 | %define MSR_K6_EFER_SVME RT_BIT_32(12)
|
---|
| 929 | %define MSR_K6_EFER_LMSLE RT_BIT_32(13)
|
---|
| 930 | %define MSR_K6_EFER_FFXSR RT_BIT_32(14)
|
---|
| 931 | %define MSR_K6_EFER_TCE RT_BIT_32(15)
|
---|
[87358] | 932 | %define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
|
---|
[1] | 933 | %define MSR_K6_STAR 0xc0000081
|
---|
| 934 | %define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
|
---|
| 935 | %define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
|
---|
| 936 | %define MSR_K6_STAR_SEL_MASK 0xffff
|
---|
| 937 | %define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
|
---|
| 938 | %define MSR_K6_WHCR 0xc0000082
|
---|
| 939 | %define MSR_K6_UWCCR 0xc0000085
|
---|
| 940 | %define MSR_K6_PSOR 0xc0000087
|
---|
| 941 | %define MSR_K6_PFIR 0xc0000088
|
---|
| 942 | %define MSR_K7_EVNTSEL0 0xc0010000
|
---|
| 943 | %define MSR_K7_EVNTSEL1 0xc0010001
|
---|
| 944 | %define MSR_K7_EVNTSEL2 0xc0010002
|
---|
| 945 | %define MSR_K7_EVNTSEL3 0xc0010003
|
---|
| 946 | %define MSR_K7_PERFCTR0 0xc0010004
|
---|
| 947 | %define MSR_K7_PERFCTR1 0xc0010005
|
---|
| 948 | %define MSR_K7_PERFCTR2 0xc0010006
|
---|
| 949 | %define MSR_K7_PERFCTR3 0xc0010007
|
---|
| 950 | %define MSR_K8_LSTAR 0xc0000082
|
---|
| 951 | %define MSR_K8_CSTAR 0xc0000083
|
---|
| 952 | %define MSR_K8_SF_MASK 0xc0000084
|
---|
| 953 | %define MSR_K8_FS_BASE 0xc0000100
|
---|
| 954 | %define MSR_K8_GS_BASE 0xc0000101
|
---|
| 955 | %define MSR_K8_KERNEL_GS_BASE 0xc0000102
|
---|
| 956 | %define MSR_K8_TSC_AUX 0xc0000103
|
---|
| 957 | %define MSR_K8_SYSCFG 0xc0010010
|
---|
| 958 | %define MSR_K8_HWCR 0xc0010015
|
---|
| 959 | %define MSR_K8_IORRBASE0 0xc0010016
|
---|
| 960 | %define MSR_K8_IORRMASK0 0xc0010017
|
---|
| 961 | %define MSR_K8_IORRBASE1 0xc0010018
|
---|
| 962 | %define MSR_K8_IORRMASK1 0xc0010019
|
---|
| 963 | %define MSR_K8_TOP_MEM1 0xc001001a
|
---|
| 964 | %define MSR_K8_TOP_MEM2 0xc001001d
|
---|
[87358] | 965 | %define MSR_K7_SMBASE 0xc0010111
|
---|
| 966 | %define MSR_K7_SMM_ADDR 0xc0010112
|
---|
| 967 | %define MSR_K7_SMM_MASK 0xc0010113
|
---|
[48909] | 968 | %define MSR_K8_NB_CFG 0xc001001f
|
---|
| 969 | %define MSR_K8_INT_PENDING 0xc0010055
|
---|
[1] | 970 | %define MSR_K8_VM_CR 0xc0010114
|
---|
[66148] | 971 | %define MSR_K8_VM_CR_DPD RT_BIT_32(0)
|
---|
| 972 | %define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
|
---|
| 973 | %define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
|
---|
| 974 | %define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
|
---|
[59965] | 975 | %define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
|
---|
[1] | 976 | %define MSR_K8_IGNNE 0xc0010115
|
---|
| 977 | %define MSR_K8_SMM_CTL 0xc0010116
|
---|
| 978 | %define MSR_K8_VM_HSAVE_PA 0xc0010117
|
---|
[87358] | 979 | %define MSR_AMD_VIRT_SPEC_CTL 0xc001011f
|
---|
| 980 | %define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
|
---|
[103930] | 981 | %ifndef __ASSEMBLER__
|
---|
| 982 | %endif
|
---|
[1] | 983 | %define X86_PG_ENTRIES 1024
|
---|
[103930] | 984 | %ifndef __ASSEMBLER__
|
---|
| 985 | %endif
|
---|
[1] | 986 | %define X86_PG_PAE_ENTRIES 512
|
---|
[7706] | 987 | %define X86_PG_PAE_PDPE_ENTRIES 4
|
---|
| 988 | %define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
|
---|
| 989 | %define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
|
---|
[61316] | 990 | %define X86_PAGE_SIZE X86_PAGE_4K_SIZE
|
---|
| 991 | %define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
|
---|
| 992 | %define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
|
---|
| 993 | %define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
|
---|
| 994 | %define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
|
---|
[1] | 995 | %define X86_PAGE_4K_SIZE _4K
|
---|
| 996 | %define X86_PAGE_4K_SHIFT 12
|
---|
| 997 | %define X86_PAGE_4K_OFFSET_MASK 0xfff
|
---|
[20742] | 998 | %define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
|
---|
[13702] | 999 | %define X86_PAGE_4K_BASE_MASK_32 0xfffff000
|
---|
[1] | 1000 | %define X86_PAGE_2M_SIZE _2M
|
---|
| 1001 | %define X86_PAGE_2M_SHIFT 21
|
---|
| 1002 | %define X86_PAGE_2M_OFFSET_MASK 0x001fffff
|
---|
[20742] | 1003 | %define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
|
---|
[13702] | 1004 | %define X86_PAGE_2M_BASE_MASK_32 0xffe00000
|
---|
[1] | 1005 | %define X86_PAGE_4M_SIZE _4M
|
---|
| 1006 | %define X86_PAGE_4M_SHIFT 22
|
---|
| 1007 | %define X86_PAGE_4M_OFFSET_MASK 0x003fffff
|
---|
[20742] | 1008 | %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
|
---|
[13702] | 1009 | %define X86_PAGE_4M_BASE_MASK_32 0xffc00000
|
---|
[75994] | 1010 | %define X86_PAGE_1G_SIZE _1G
|
---|
| 1011 | %define X86_PAGE_1G_SHIFT 30
|
---|
| 1012 | %define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
|
---|
| 1013 | %define X86_PAGE_1G_BASE_MASK 0xffffffffc0000000
|
---|
[50255] | 1014 | %define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
|
---|
[96200] | 1015 | %define X86_GET_PAGE_BASE_MASK(a_cShift) (0xffffffffffffffff << (a_cShift))
|
---|
| 1016 | %define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
|
---|
[18842] | 1017 | %define X86_PTE_BIT_P 0
|
---|
| 1018 | %define X86_PTE_BIT_RW 1
|
---|
| 1019 | %define X86_PTE_BIT_US 2
|
---|
| 1020 | %define X86_PTE_BIT_PWT 3
|
---|
| 1021 | %define X86_PTE_BIT_PCD 4
|
---|
| 1022 | %define X86_PTE_BIT_A 5
|
---|
| 1023 | %define X86_PTE_BIT_D 6
|
---|
| 1024 | %define X86_PTE_BIT_PAT 7
|
---|
| 1025 | %define X86_PTE_BIT_G 8
|
---|
[66148] | 1026 | %define X86_PTE_PAE_BIT_NX 63
|
---|
[59965] | 1027 | %define X86_PTE_P RT_BIT_32(0)
|
---|
| 1028 | %define X86_PTE_RW RT_BIT_32(1)
|
---|
| 1029 | %define X86_PTE_US RT_BIT_32(2)
|
---|
| 1030 | %define X86_PTE_PWT RT_BIT_32(3)
|
---|
| 1031 | %define X86_PTE_PCD RT_BIT_32(4)
|
---|
| 1032 | %define X86_PTE_A RT_BIT_32(5)
|
---|
| 1033 | %define X86_PTE_D RT_BIT_32(6)
|
---|
| 1034 | %define X86_PTE_PAT RT_BIT_32(7)
|
---|
| 1035 | %define X86_PTE_G RT_BIT_32(8)
|
---|
| 1036 | %define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 1037 | %define X86_PTE_PG_MASK ( 0xfffff000 )
|
---|
[33933] | 1038 | %define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
|
---|
[5605] | 1039 | %define X86_PTE_PAE_NX RT_BIT_64(63)
|
---|
[30969] | 1040 | %define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
|
---|
| 1041 | %define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
|
---|
| 1042 | %define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
|
---|
| 1043 | %define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
|
---|
[103930] | 1044 | %ifndef __ASSEMBLER__
|
---|
| 1045 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1046 | %endif
|
---|
| 1047 | %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
|
---|
| 1048 | %endif
|
---|
| 1049 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1050 | %endif
|
---|
| 1051 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1052 | %endif
|
---|
| 1053 | %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
|
---|
| 1054 | %endif
|
---|
| 1055 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1056 | %endif
|
---|
| 1057 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1058 | %endif
|
---|
[59388] | 1059 | %endif
|
---|
[1] | 1060 | %define X86_PT_SHIFT 12
|
---|
| 1061 | %define X86_PT_MASK 0x3ff
|
---|
[103930] | 1062 | %ifndef __ASSEMBLER__
|
---|
| 1063 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1064 | %endif
|
---|
[59388] | 1065 | %endif
|
---|
[1] | 1066 | %define X86_PT_PAE_SHIFT 12
|
---|
| 1067 | %define X86_PT_PAE_MASK 0x1ff
|
---|
[59965] | 1068 | %define X86_PDE_P RT_BIT_32(0)
|
---|
| 1069 | %define X86_PDE_RW RT_BIT_32(1)
|
---|
| 1070 | %define X86_PDE_US RT_BIT_32(2)
|
---|
| 1071 | %define X86_PDE_PWT RT_BIT_32(3)
|
---|
| 1072 | %define X86_PDE_PCD RT_BIT_32(4)
|
---|
| 1073 | %define X86_PDE_A RT_BIT_32(5)
|
---|
| 1074 | %define X86_PDE_PS RT_BIT_32(7)
|
---|
| 1075 | %define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[1] | 1076 | %define X86_PDE_PG_MASK ( 0xfffff000 )
|
---|
[33933] | 1077 | %define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
|
---|
[5605] | 1078 | %define X86_PDE_PAE_NX RT_BIT_64(63)
|
---|
[30969] | 1079 | %define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
|
---|
| 1080 | %define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
|
---|
| 1081 | %define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
|
---|
| 1082 | %define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
|
---|
[103930] | 1083 | %ifndef __ASSEMBLER__
|
---|
| 1084 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1085 | %endif
|
---|
| 1086 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1087 | %endif
|
---|
[59388] | 1088 | %endif
|
---|
[59965] | 1089 | %define X86_PDE4M_P RT_BIT_32(0)
|
---|
| 1090 | %define X86_PDE4M_RW RT_BIT_32(1)
|
---|
| 1091 | %define X86_PDE4M_US RT_BIT_32(2)
|
---|
| 1092 | %define X86_PDE4M_PWT RT_BIT_32(3)
|
---|
| 1093 | %define X86_PDE4M_PCD RT_BIT_32(4)
|
---|
| 1094 | %define X86_PDE4M_A RT_BIT_32(5)
|
---|
| 1095 | %define X86_PDE4M_D RT_BIT_32(6)
|
---|
| 1096 | %define X86_PDE4M_PS RT_BIT_32(7)
|
---|
| 1097 | %define X86_PDE4M_G RT_BIT_32(8)
|
---|
| 1098 | %define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
| 1099 | %define X86_PDE4M_PAT RT_BIT_32(12)
|
---|
[1] | 1100 | %define X86_PDE4M_PAT_SHIFT (12 - 7)
|
---|
| 1101 | %define X86_PDE4M_PG_MASK ( 0xffc00000 )
|
---|
| 1102 | %define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
|
---|
| 1103 | %define X86_PDE4M_PG_HIGH_SHIFT 19
|
---|
[30969] | 1104 | %define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
|
---|
| 1105 | %define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
|
---|
| 1106 | %define X86_PDE2M_PAE_NX RT_BIT_64(63)
|
---|
| 1107 | %define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
|
---|
| 1108 | %define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
|
---|
| 1109 | %define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
|
---|
| 1110 | %define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
|
---|
[103930] | 1111 | %ifndef __ASSEMBLER__
|
---|
| 1112 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1113 | %endif
|
---|
| 1114 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1115 | %endif
|
---|
[59388] | 1116 | %endif
|
---|
[103930] | 1117 | %ifndef __ASSEMBLER__
|
---|
| 1118 | %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
|
---|
| 1119 | %endif
|
---|
| 1120 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1121 | %endif
|
---|
| 1122 | %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
|
---|
| 1123 | %endif
|
---|
| 1124 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1125 | %endif
|
---|
| 1126 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1127 | %endif
|
---|
[59388] | 1128 | %endif
|
---|
[1] | 1129 | %define X86_PD_SHIFT 22
|
---|
| 1130 | %define X86_PD_MASK 0x3ff
|
---|
[103930] | 1131 | %ifndef __ASSEMBLER__
|
---|
| 1132 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1133 | %endif
|
---|
[59388] | 1134 | %endif
|
---|
[1] | 1135 | %define X86_PD_PAE_SHIFT 21
|
---|
| 1136 | %define X86_PD_PAE_MASK 0x1ff
|
---|
[59965] | 1137 | %define X86_PDPE_P RT_BIT_32(0)
|
---|
| 1138 | %define X86_PDPE_RW RT_BIT_32(1)
|
---|
| 1139 | %define X86_PDPE_US RT_BIT_32(2)
|
---|
| 1140 | %define X86_PDPE_PWT RT_BIT_32(3)
|
---|
| 1141 | %define X86_PDPE_PCD RT_BIT_32(4)
|
---|
| 1142 | %define X86_PDPE_A RT_BIT_32(5)
|
---|
| 1143 | %define X86_PDPE_LM_PS RT_BIT_32(7)
|
---|
| 1144 | %define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[30969] | 1145 | %define X86_PDPE_PG_MASK 0x000ffffffffff000
|
---|
[96200] | 1146 | %define X86_PDPE1G_PG_MASK 0x000fffffc0000000
|
---|
[30969] | 1147 | %define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
|
---|
| 1148 | %define X86_PDPE_LM_NX RT_BIT_64(63)
|
---|
| 1149 | %define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
|
---|
| 1150 | %define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
|
---|
| 1151 | %define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
|
---|
| 1152 | %define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
|
---|
[103930] | 1153 | %ifndef __ASSEMBLER__
|
---|
| 1154 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1155 | %endif
|
---|
| 1156 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1157 | %endif
|
---|
| 1158 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1159 | %endif
|
---|
| 1160 | %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
|
---|
| 1161 | %endif
|
---|
| 1162 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1163 | %endif
|
---|
| 1164 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1165 | %endif
|
---|
[59388] | 1166 | %endif
|
---|
[9768] | 1167 | %define X86_PDPT_SHIFT 30
|
---|
| 1168 | %define X86_PDPT_MASK_PAE 0x3
|
---|
| 1169 | %define X86_PDPT_MASK_AMD64 0x1ff
|
---|
[59965] | 1170 | %define X86_PML4E_P RT_BIT_32(0)
|
---|
| 1171 | %define X86_PML4E_RW RT_BIT_32(1)
|
---|
| 1172 | %define X86_PML4E_US RT_BIT_32(2)
|
---|
| 1173 | %define X86_PML4E_PWT RT_BIT_32(3)
|
---|
| 1174 | %define X86_PML4E_PCD RT_BIT_32(4)
|
---|
| 1175 | %define X86_PML4E_A RT_BIT_32(5)
|
---|
| 1176 | %define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
[33933] | 1177 | %define X86_PML4E_PG_MASK 0x000ffffffffff000
|
---|
[30969] | 1178 | %define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
|
---|
| 1179 | %define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
|
---|
[5605] | 1180 | %define X86_PML4E_NX RT_BIT_64(63)
|
---|
[103930] | 1181 | %ifndef __ASSEMBLER__
|
---|
| 1182 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1183 | %endif
|
---|
| 1184 | %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
|
---|
| 1185 | %endif
|
---|
| 1186 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1187 | %endif
|
---|
| 1188 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1189 | %endif
|
---|
[59388] | 1190 | %endif
|
---|
[1] | 1191 | %define X86_PML4_SHIFT 39
|
---|
| 1192 | %define X86_PML4_MASK 0x1ff
|
---|
[75994] | 1193 | %define X86_INVPCID_TYPE_INDV_ADDR 0
|
---|
| 1194 | %define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
|
---|
| 1195 | %define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
|
---|
| 1196 | %define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
|
---|
| 1197 | %define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
|
---|
[96200] | 1198 | %define X86_FPU_INT64_INDEFINITE INT64_MIN
|
---|
| 1199 | %define X86_FPU_INT32_INDEFINITE INT32_MIN
|
---|
| 1200 | %define X86_FPU_INT16_INDEFINITE INT16_MIN
|
---|
[103930] | 1201 | %ifndef __ASSEMBLER__
|
---|
| 1202 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1203 | %endif
|
---|
| 1204 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1205 | %endif
|
---|
| 1206 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1207 | %endif
|
---|
| 1208 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1209 | %endif
|
---|
| 1210 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1211 | %endif
|
---|
| 1212 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1213 | %endif
|
---|
| 1214 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1215 | %endif
|
---|
| 1216 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1217 | %endif
|
---|
[55254] | 1218 | %endif
|
---|
[53626] | 1219 | %define X86_OFF_FXSTATE_RSVD 0x1d0
|
---|
| 1220 | %define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
|
---|
[55254] | 1221 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1222 | %endif
|
---|
[59965] | 1223 | %define X86_FSW_IE RT_BIT_32(0)
|
---|
[96211] | 1224 | %define X86_FSW_IE_BIT 0
|
---|
[59965] | 1225 | %define X86_FSW_DE RT_BIT_32(1)
|
---|
[96211] | 1226 | %define X86_FSW_DE_BIT 1
|
---|
[59965] | 1227 | %define X86_FSW_ZE RT_BIT_32(2)
|
---|
[96211] | 1228 | %define X86_FSW_ZE_BIT 2
|
---|
[59965] | 1229 | %define X86_FSW_OE RT_BIT_32(3)
|
---|
[96211] | 1230 | %define X86_FSW_OE_BIT 3
|
---|
[59965] | 1231 | %define X86_FSW_UE RT_BIT_32(4)
|
---|
[96211] | 1232 | %define X86_FSW_UE_BIT 4
|
---|
[59965] | 1233 | %define X86_FSW_PE RT_BIT_32(5)
|
---|
[96211] | 1234 | %define X86_FSW_PE_BIT 5
|
---|
[59965] | 1235 | %define X86_FSW_SF RT_BIT_32(6)
|
---|
[96211] | 1236 | %define X86_FSW_SF_BIT 6
|
---|
[59965] | 1237 | %define X86_FSW_ES RT_BIT_32(7)
|
---|
[96211] | 1238 | %define X86_FSW_ES_BIT 7
|
---|
[40161] | 1239 | %define X86_FSW_XCPT_MASK 0x007f
|
---|
| 1240 | %define X86_FSW_XCPT_ES_MASK 0x00ff
|
---|
[96200] | 1241 | %define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
|
---|
| 1242 | %define X86_FSW_C0_BIT 8
|
---|
| 1243 | %define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
|
---|
| 1244 | %define X86_FSW_C1_BIT 9
|
---|
| 1245 | %define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
|
---|
| 1246 | %define X86_FSW_C2_BIT 10
|
---|
[37968] | 1247 | %define X86_FSW_TOP_MASK 0x3800
|
---|
| 1248 | %define X86_FSW_TOP_SHIFT 11
|
---|
| 1249 | %define X86_FSW_TOP_SMASK 0x0007
|
---|
| 1250 | %define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
|
---|
[96200] | 1251 | %define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
|
---|
| 1252 | %define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
|
---|
| 1253 | %define X86_FSW_C3_BIT 14
|
---|
[40161] | 1254 | %define X86_FSW_C_MASK 0x4700
|
---|
[59965] | 1255 | %define X86_FSW_B RT_BIT_32(15)
|
---|
[96200] | 1256 | %define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
|
---|
| 1257 | ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
|
---|
| 1258 | | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
|
---|
| 1259 | | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
|
---|
| 1260 | %define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
|
---|
| 1261 | ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
|
---|
| 1262 | | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
|
---|
| 1263 | | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
|
---|
[59965] | 1264 | %define X86_FCW_IM RT_BIT_32(0)
|
---|
[96200] | 1265 | %define X86_FCW_IM_BIT 0
|
---|
[59965] | 1266 | %define X86_FCW_DM RT_BIT_32(1)
|
---|
[96200] | 1267 | %define X86_FCW_DM_BIT 1
|
---|
[59965] | 1268 | %define X86_FCW_ZM RT_BIT_32(2)
|
---|
[96200] | 1269 | %define X86_FCW_ZM_BIT 2
|
---|
[59965] | 1270 | %define X86_FCW_OM RT_BIT_32(3)
|
---|
[96200] | 1271 | %define X86_FCW_OM_BIT 3
|
---|
[59965] | 1272 | %define X86_FCW_UM RT_BIT_32(4)
|
---|
[96200] | 1273 | %define X86_FCW_UM_BIT 4
|
---|
[59965] | 1274 | %define X86_FCW_PM RT_BIT_32(5)
|
---|
[96200] | 1275 | %define X86_FCW_PM_BIT 5
|
---|
[40076] | 1276 | %define X86_FCW_MASK_ALL 0x007f
|
---|
[96200] | 1277 | %define X86_FCW_XCPT_MASK 0x003f
|
---|
[40069] | 1278 | %define X86_FCW_PC_MASK 0x0300
|
---|
[96200] | 1279 | %define X86_FCW_PC_SHIFT 8
|
---|
[40069] | 1280 | %define X86_FCW_PC_24 0x0000
|
---|
| 1281 | %define X86_FCW_PC_RSVD 0x0100
|
---|
| 1282 | %define X86_FCW_PC_53 0x0200
|
---|
| 1283 | %define X86_FCW_PC_64 0x0300
|
---|
| 1284 | %define X86_FCW_RC_MASK 0x0c00
|
---|
[96200] | 1285 | %define X86_FCW_RC_SHIFT 10
|
---|
[40069] | 1286 | %define X86_FCW_RC_NEAREST 0x0000
|
---|
| 1287 | %define X86_FCW_RC_DOWN 0x0400
|
---|
| 1288 | %define X86_FCW_RC_UP 0x0800
|
---|
| 1289 | %define X86_FCW_RC_ZERO 0x0c00
|
---|
[96200] | 1290 | %define X86_FCW_IC_MASK 0x1000
|
---|
| 1291 | %define X86_FCW_IC_AFFINE 0x1000
|
---|
| 1292 | %define X86_FCW_IC_PROJECTIVE 0x0000
|
---|
[41300] | 1293 | %define X86_FCW_ZERO_MASK 0xf080
|
---|
[69202] | 1294 | %define X86_MXCSR_IE RT_BIT_32(0)
|
---|
| 1295 | %define X86_MXCSR_DE RT_BIT_32(1)
|
---|
| 1296 | %define X86_MXCSR_ZE RT_BIT_32(2)
|
---|
| 1297 | %define X86_MXCSR_OE RT_BIT_32(3)
|
---|
| 1298 | %define X86_MXCSR_UE RT_BIT_32(4)
|
---|
| 1299 | %define X86_MXCSR_PE RT_BIT_32(5)
|
---|
[96204] | 1300 | %define X86_MXCSR_XCPT_FLAGS 0x003f
|
---|
[69202] | 1301 | %define X86_MXCSR_DAZ RT_BIT_32(6)
|
---|
| 1302 | %define X86_MXCSR_IM RT_BIT_32(7)
|
---|
| 1303 | %define X86_MXCSR_DM RT_BIT_32(8)
|
---|
| 1304 | %define X86_MXCSR_ZM RT_BIT_32(9)
|
---|
| 1305 | %define X86_MXCSR_OM RT_BIT_32(10)
|
---|
| 1306 | %define X86_MXCSR_UM RT_BIT_32(11)
|
---|
| 1307 | %define X86_MXCSR_PM RT_BIT_32(12)
|
---|
[96204] | 1308 | %define X86_MXCSR_XCPT_MASK 0x1f80
|
---|
| 1309 | %define X86_MXCSR_XCPT_MASK_SHIFT 7
|
---|
[69202] | 1310 | %define X86_MXCSR_RC_MASK 0x6000
|
---|
[96200] | 1311 | %define X86_MXCSR_RC_SHIFT 13
|
---|
[69202] | 1312 | %define X86_MXCSR_RC_NEAREST 0x0000
|
---|
| 1313 | %define X86_MXCSR_RC_DOWN 0x2000
|
---|
| 1314 | %define X86_MXCSR_RC_UP 0x4000
|
---|
| 1315 | %define X86_MXCSR_RC_ZERO 0x6000
|
---|
| 1316 | %define X86_MXCSR_FZ RT_BIT_32(15)
|
---|
| 1317 | %define X86_MXCSR_MM RT_BIT_32(17)
|
---|
[96818] | 1318 | %define X86_MXCSR_ZERO_MASK 0xfffd0000
|
---|
[103930] | 1319 | %ifndef __ASSEMBLER__
|
---|
| 1320 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1321 | %endif
|
---|
| 1322 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1323 | %endif
|
---|
| 1324 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1325 | %endif
|
---|
| 1326 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1327 | %endif
|
---|
| 1328 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1329 | %endif
|
---|
| 1330 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1331 | %endif
|
---|
| 1332 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1333 | %endif
|
---|
| 1334 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1335 | %endif
|
---|
| 1336 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1337 | %endif
|
---|
[41300] | 1338 | %endif
|
---|
[56637] | 1339 | %define XSAVE_C_X87_BIT 0
|
---|
| 1340 | %define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
|
---|
| 1341 | %define XSAVE_C_SSE_BIT 1
|
---|
| 1342 | %define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
|
---|
| 1343 | %define XSAVE_C_YMM_BIT 2
|
---|
| 1344 | %define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
|
---|
| 1345 | %define XSAVE_C_BNDREGS_BIT 3
|
---|
| 1346 | %define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
|
---|
| 1347 | %define XSAVE_C_BNDCSR_BIT 4
|
---|
| 1348 | %define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
|
---|
| 1349 | %define XSAVE_C_OPMASK_BIT 5
|
---|
| 1350 | %define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
|
---|
| 1351 | %define XSAVE_C_ZMM_HI256_BIT 6
|
---|
| 1352 | %define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
|
---|
| 1353 | %define XSAVE_C_ZMM_16HI_BIT 7
|
---|
| 1354 | %define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
|
---|
| 1355 | %define XSAVE_C_PKRU_BIT 9
|
---|
| 1356 | %define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
|
---|
| 1357 | %define XSAVE_C_LWP_BIT 62
|
---|
| 1358 | %define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
|
---|
[69202] | 1359 | %define XSAVE_C_X_BIT 63
|
---|
| 1360 | %define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
|
---|
[103930] | 1361 | %ifndef __ASSEMBLER__
|
---|
| 1362 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1363 | %endif
|
---|
[55254] | 1364 | %endif
|
---|
[47267] | 1365 | %define X86DESCATTR_TYPE 0x0000000f
|
---|
| 1366 | %define X86DESCATTR_DT 0x00000010
|
---|
| 1367 | %define X86DESCATTR_DPL 0x00000060
|
---|
| 1368 | %define X86DESCATTR_DPL_SHIFT 5
|
---|
[47876] | 1369 | %define X86DESCATTR_P 0x00000080
|
---|
[47267] | 1370 | %define X86DESCATTR_LIMIT_HIGH 0x00000f00
|
---|
| 1371 | %define X86DESCATTR_AVL 0x00001000
|
---|
| 1372 | %define X86DESCATTR_L 0x00002000
|
---|
| 1373 | %define X86DESCATTR_D 0x00004000
|
---|
| 1374 | %define X86DESCATTR_G 0x00008000
|
---|
| 1375 | %define X86DESCATTR_UNUSABLE 0x00010000
|
---|
[103930] | 1376 | %ifndef __ASSEMBLER__
|
---|
| 1377 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1378 | %endif
|
---|
[41300] | 1379 | %endif
|
---|
| 1380 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
[103930] | 1381 | %ifndef __ASSEMBLER__
|
---|
| 1382 | %endif
|
---|
| 1383 | %define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
|
---|
| 1384 | %define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
|
---|
| 1385 | %define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
|
---|
| 1386 | %define X86DESCGENERIC_BIT_OFF_TYPE (40)
|
---|
| 1387 | %define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
|
---|
| 1388 | %define X86DESCGENERIC_BIT_OFF_DPL (45)
|
---|
| 1389 | %define X86DESCGENERIC_BIT_OFF_PRESENT (47)
|
---|
| 1390 | %define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
|
---|
| 1391 | %define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
|
---|
| 1392 | %define X86DESCGENERIC_BIT_OFF_LONG (53)
|
---|
| 1393 | %define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
|
---|
| 1394 | %define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
|
---|
| 1395 | %define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
|
---|
| 1396 | %define X86LAR_F_TYPE 0x0f00
|
---|
| 1397 | %define X86LAR_F_DT 0x1000
|
---|
| 1398 | %define X86LAR_F_DPL 0x6000
|
---|
| 1399 | %define X86LAR_F_DPL_SHIFT 13
|
---|
| 1400 | %define X86LAR_F_P 0x8000
|
---|
| 1401 | %define X86LAR_F_AVL 0x00100000
|
---|
| 1402 | %define X86LAR_F_L 0x00200000
|
---|
| 1403 | %define X86LAR_F_D 0x00400000
|
---|
| 1404 | %define X86LAR_F_G 0x00800000
|
---|
| 1405 | %ifndef __ASSEMBLER__
|
---|
| 1406 | %endif
|
---|
[41300] | 1407 | %endif
|
---|
[103930] | 1408 | %ifndef __ASSEMBLER__
|
---|
| 1409 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1410 | %endif
|
---|
| 1411 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1412 | %endif
|
---|
[41300] | 1413 | %endif
|
---|
[103930] | 1414 | %ifndef __ASSEMBLER__
|
---|
| 1415 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1416 | %endif
|
---|
| 1417 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1418 | %endif
|
---|
| 1419 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1420 | %endif
|
---|
[20742] | 1421 | %if HC_ARCH_BITS == 64
|
---|
| 1422 | %else
|
---|
| 1423 | %endif
|
---|
[22429] | 1424 | %if HC_ARCH_BITS == 64
|
---|
| 1425 | %else
|
---|
| 1426 | %endif
|
---|
| 1427 | %if HC_ARCH_BITS == 64
|
---|
| 1428 | %else
|
---|
| 1429 | %endif
|
---|
[103930] | 1430 | %endif
|
---|
[1] | 1431 | %define X86_SEL_TYPE_CODE 8
|
---|
[59965] | 1432 | %define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
|
---|
[1] | 1433 | %define X86_SEL_TYPE_ACCESSED 1
|
---|
| 1434 | %define X86_SEL_TYPE_DOWN 4
|
---|
| 1435 | %define X86_SEL_TYPE_CONF 4
|
---|
| 1436 | %define X86_SEL_TYPE_WRITE 2
|
---|
| 1437 | %define X86_SEL_TYPE_READ 2
|
---|
[42588] | 1438 | %define X86_SEL_TYPE_READ_BIT 1
|
---|
[1] | 1439 | %define X86_SEL_TYPE_RO 0
|
---|
| 1440 | %define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
|
---|
| 1441 | %define X86_SEL_TYPE_RW 2
|
---|
| 1442 | %define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
|
---|
| 1443 | %define X86_SEL_TYPE_RO_DOWN 4
|
---|
| 1444 | %define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
|
---|
| 1445 | %define X86_SEL_TYPE_RW_DOWN 6
|
---|
| 1446 | %define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
|
---|
| 1447 | %define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
|
---|
| 1448 | %define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 1449 | %define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
|
---|
| 1450 | %define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 1451 | %define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
|
---|
| 1452 | %define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
| 1453 | %define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
|
---|
| 1454 | %define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
|
---|
[37968] | 1455 | %define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
|
---|
[4720] | 1456 | %define X86_SEL_TYPE_SYS_UNDEFINED 0
|
---|
| 1457 | %define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
|
---|
| 1458 | %define X86_SEL_TYPE_SYS_LDT 2
|
---|
| 1459 | %define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
|
---|
| 1460 | %define X86_SEL_TYPE_SYS_286_CALL_GATE 4
|
---|
| 1461 | %define X86_SEL_TYPE_SYS_TASK_GATE 5
|
---|
| 1462 | %define X86_SEL_TYPE_SYS_286_INT_GATE 6
|
---|
| 1463 | %define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
|
---|
| 1464 | %define X86_SEL_TYPE_SYS_UNDEFINED2 8
|
---|
| 1465 | %define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
|
---|
| 1466 | %define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
|
---|
| 1467 | %define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
|
---|
| 1468 | %define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
|
---|
| 1469 | %define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
|
---|
| 1470 | %define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
|
---|
| 1471 | %define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
|
---|
| 1472 | %define AMD64_SEL_TYPE_SYS_LDT 2
|
---|
| 1473 | %define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
|
---|
| 1474 | %define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
|
---|
| 1475 | %define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
|
---|
| 1476 | %define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
|
---|
| 1477 | %define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
|
---|
[59965] | 1478 | %define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
|
---|
| 1479 | %define X86_DESC_S RT_BIT_32(12)
|
---|
| 1480 | %define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
|
---|
| 1481 | %define X86_DESC_P RT_BIT_32(15)
|
---|
| 1482 | %define X86_DESC_AVL RT_BIT_32(20)
|
---|
| 1483 | %define X86_DESC_DB RT_BIT_32(22)
|
---|
| 1484 | %define X86_DESC_G RT_BIT_32(23)
|
---|
[53626] | 1485 | %define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
|
---|
| 1486 | %define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
|
---|
[103930] | 1487 | %ifndef __ASSEMBLER__
|
---|
| 1488 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1489 | %endif
|
---|
| 1490 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1491 | %endif
|
---|
| 1492 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1493 | %endif
|
---|
[41300] | 1494 | %endif
|
---|
[42585] | 1495 | %define X86_SEL_SHIFT 3
|
---|
| 1496 | %define X86_SEL_MASK 0xfff8
|
---|
| 1497 | %define X86_SEL_MASK_OFF_RPL 0xfffc
|
---|
| 1498 | %define X86_SEL_LDT 0x0004
|
---|
| 1499 | %define X86_SEL_RPL 0x0003
|
---|
| 1500 | %define X86_SEL_RPL_LDT 0x0007
|
---|
[103930] | 1501 | %ifndef __ASSEMBLER__
|
---|
| 1502 | %endif
|
---|
[66599] | 1503 | %define X86_XCPT_LAST 0x1f
|
---|
[1] | 1504 | %define X86_TRAP_ERR_EXTERNAL 1
|
---|
| 1505 | %define X86_TRAP_ERR_IDT 2
|
---|
| 1506 | %define X86_TRAP_ERR_TI 4
|
---|
| 1507 | %define X86_TRAP_ERR_SEL_MASK 0xfff8
|
---|
| 1508 | %define X86_TRAP_ERR_SEL_SHIFT 3
|
---|
[59965] | 1509 | %define X86_TRAP_PF_P RT_BIT_32(0)
|
---|
| 1510 | %define X86_TRAP_PF_RW RT_BIT_32(1)
|
---|
| 1511 | %define X86_TRAP_PF_US RT_BIT_32(2)
|
---|
| 1512 | %define X86_TRAP_PF_RSVD RT_BIT_32(3)
|
---|
| 1513 | %define X86_TRAP_PF_ID RT_BIT_32(4)
|
---|
| 1514 | %define X86_TRAP_PF_PK RT_BIT_32(5)
|
---|
[103930] | 1515 | %ifndef __ASSEMBLER__
|
---|
| 1516 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1517 | %else
|
---|
| 1518 | %endif
|
---|
| 1519 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
| 1520 | %else
|
---|
| 1521 | %endif
|
---|
[41300] | 1522 | %endif
|
---|
[37968] | 1523 | %define X86_MODRM_RM_MASK 0x07
|
---|
| 1524 | %define X86_MODRM_REG_MASK 0x38
|
---|
| 1525 | %define X86_MODRM_REG_SMASK 0x07
|
---|
| 1526 | %define X86_MODRM_REG_SHIFT 3
|
---|
| 1527 | %define X86_MODRM_MOD_MASK 0xc0
|
---|
| 1528 | %define X86_MODRM_MOD_SMASK 0x03
|
---|
| 1529 | %define X86_MODRM_MOD_SHIFT 6
|
---|
[102126] | 1530 | %define X86_MOD_MEM0 0
|
---|
| 1531 | %define X86_MOD_MEM1 1
|
---|
| 1532 | %define X86_MOD_MEM4 2
|
---|
| 1533 | %define X86_MOD_REG 3
|
---|
[41300] | 1534 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
[66148] | 1535 | %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
|
---|
[41300] | 1536 | %endif
|
---|
[37968] | 1537 | %define X86_SIB_BASE_MASK 0x07
|
---|
| 1538 | %define X86_SIB_INDEX_MASK 0x38
|
---|
| 1539 | %define X86_SIB_INDEX_SMASK 0x07
|
---|
| 1540 | %define X86_SIB_INDEX_SHIFT 3
|
---|
| 1541 | %define X86_SIB_SCALE_MASK 0xc0
|
---|
| 1542 | %define X86_SIB_SCALE_SMASK 0x03
|
---|
| 1543 | %define X86_SIB_SCALE_SHIFT 6
|
---|
[41300] | 1544 | %ifndef VBOX_FOR_DTRACE_LIB
|
---|
[102126] | 1545 | %define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
|
---|
| 1546 | (((a_Scale) << X86_SIB_SCALE_SHIFT) | ((a_IndexReg) << X86_SIB_INDEX_SHIFT) | (a_BaseReg))
|
---|
[41300] | 1547 | %endif
|
---|
[37968] | 1548 | %define X86_GREG_xAX 0
|
---|
| 1549 | %define X86_GREG_xCX 1
|
---|
| 1550 | %define X86_GREG_xDX 2
|
---|
| 1551 | %define X86_GREG_xBX 3
|
---|
| 1552 | %define X86_GREG_xSP 4
|
---|
| 1553 | %define X86_GREG_xBP 5
|
---|
| 1554 | %define X86_GREG_xSI 6
|
---|
| 1555 | %define X86_GREG_xDI 7
|
---|
| 1556 | %define X86_GREG_x8 8
|
---|
| 1557 | %define X86_GREG_x9 9
|
---|
| 1558 | %define X86_GREG_x10 10
|
---|
| 1559 | %define X86_GREG_x11 11
|
---|
| 1560 | %define X86_GREG_x12 12
|
---|
| 1561 | %define X86_GREG_x13 13
|
---|
| 1562 | %define X86_GREG_x14 14
|
---|
| 1563 | %define X86_GREG_x15 15
|
---|
[87358] | 1564 | %define X86_GREG_COUNT 16
|
---|
[37968] | 1565 | %define X86_SREG_ES 0
|
---|
| 1566 | %define X86_SREG_CS 1
|
---|
| 1567 | %define X86_SREG_SS 2
|
---|
| 1568 | %define X86_SREG_DS 3
|
---|
| 1569 | %define X86_SREG_FS 4
|
---|
| 1570 | %define X86_SREG_GS 5
|
---|
[42396] | 1571 | %define X86_SREG_COUNT 6
|
---|
[47305] | 1572 | %define X86_OP_PRF_CS 0x2e
|
---|
| 1573 | %define X86_OP_PRF_SS 0x36
|
---|
| 1574 | %define X86_OP_PRF_DS 0x3e
|
---|
| 1575 | %define X86_OP_PRF_ES 0x26
|
---|
| 1576 | %define X86_OP_PRF_FS 0x64
|
---|
| 1577 | %define X86_OP_PRF_GS 0x65
|
---|
| 1578 | %define X86_OP_PRF_SIZE_OP 0x66
|
---|
| 1579 | %define X86_OP_PRF_SIZE_ADDR 0x67
|
---|
| 1580 | %define X86_OP_PRF_LOCK 0xf0
|
---|
[66148] | 1581 | %define X86_OP_PRF_REPZ 0xf3
|
---|
[65776] | 1582 | %define X86_OP_PRF_REPNZ 0xf2
|
---|
[102126] | 1583 | %define X86_OP_REX 0x40
|
---|
[47305] | 1584 | %define X86_OP_REX_B 0x41
|
---|
| 1585 | %define X86_OP_REX_X 0x42
|
---|
| 1586 | %define X86_OP_REX_R 0x44
|
---|
| 1587 | %define X86_OP_REX_W 0x48
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[103930] | 1588 | %define X86_OP_VEX3 0xc4
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| 1589 | %define X86_OP_VEX2 0xc5
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| 1590 | %define X86_OP_VEX2_BYTE1_P_MASK 0x3
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| 1591 | %define X86_OP_VEX2_BYTE1_P_NO_PRF 0
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| 1592 | %define X86_OP_VEX2_BYTE1_P_066H 1
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| 1593 | %define X86_OP_VEX2_BYTE1_P_0F3H 2
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| 1594 | %define X86_OP_VEX2_BYTE1_P_0F2H 3
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| 1595 | %define X86_OP_VEX2_BYTE1_L RT_BIT(2)
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| 1596 | %define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
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| 1597 | %define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
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| 1598 | %define X86_OP_VEX2_BYTE1_VVVV_NONE 15
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| 1599 | %define X86_OP_VEX2_BYTE1_R RT_BIT(7)
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| 1600 | %define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
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| 1601 | ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
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| 1602 | | (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
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| 1603 | | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
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| 1604 | | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
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| 1605 | %define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
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| 1606 | ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
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| 1607 | | (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
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| 1608 | | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
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| 1609 | | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
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| 1610 | %define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
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| 1611 | %define X86_OP_VEX3_BYTE1_B RT_BIT(5)
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| 1612 | %define X86_OP_VEX3_BYTE1_X RT_BIT(6)
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| 1613 | %define X86_OP_VEX3_BYTE1_R RT_BIT(7)
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| 1614 | %define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
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| 1615 | ( (uint8_t)(a_idxMap) \
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| 1616 | | ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
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| 1617 | | ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
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| 1618 | | ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
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| 1619 | %define X86_OP_VEX3_BYTE2_P_MASK 0x3
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| 1620 | %define X86_OP_VEX3_BYTE2_P_NO_PRF 0
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| 1621 | %define X86_OP_VEX3_BYTE2_P_066H 1
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| 1622 | %define X86_OP_VEX3_BYTE2_P_0F3H 2
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| 1623 | %define X86_OP_VEX3_BYTE2_P_0F2H 3
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| 1624 | %define X86_OP_VEX3_BYTE2_L RT_BIT(2)
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| 1625 | %define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
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| 1626 | %define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
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| 1627 | %define X86_OP_VEX3_BYTE2_VVVV_NONE 15
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| 1628 | %define X86_OP_VEX3_BYTE2_W RT_BIT(7)
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| 1629 | %define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
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| 1630 | ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
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| 1631 | | ((~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
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| 1632 | | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
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| 1633 | | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
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| 1634 | %define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
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| 1635 | ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
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| 1636 | | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
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| 1637 | | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
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| 1638 | | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
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[20742] | 1639 | %endif
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[40138] | 1640 | %include "iprt/x86extra.mac"
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