x86.h@ 107729

Last change on this file since 107729 was 107729, checked in by vboxsync, 4 months ago
VMM/CPUM: Explode more MSR_IA32_ARCH_CAPABILITIES bits into the CPUMFEATURES. VBP-947
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 207.7 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	#define X86_EFL_1_BIT 1
193	/** Bit 2 - PF - Parity flag - Status flag. */
194	#define X86_EFL_PF RT_BIT_32(2)
195	#define X86_EFL_PF_BIT 2
196	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
197	#define X86_EFL_AF RT_BIT_32(4)
198	#define X86_EFL_AF_BIT 4
199	/** Bit 6 - ZF - Zero flag - Status flag. */
200	#define X86_EFL_ZF RT_BIT_32(6)
201	#define X86_EFL_ZF_BIT 6
202	/** Bit 7 - SF - Signed flag - Status flag. */
203	#define X86_EFL_SF RT_BIT_32(7)
204	#define X86_EFL_SF_BIT 7
205	/** Bit 8 - TF - Trap flag - System flag. */
206	#define X86_EFL_TF RT_BIT_32(8)
207	#define X86_EFL_TF_BIT 8
208	/** Bit 9 - IF - Interrupt flag - System flag. */
209	#define X86_EFL_IF RT_BIT_32(9)
210	#define X86_EFL_IF_BIT 9
211	/** Bit 10 - DF - Direction flag - Control flag. */
212	#define X86_EFL_DF RT_BIT_32(10)
213	#define X86_EFL_DF_BIT 10
214	/** Bit 11 - OF - Overflow flag - Status flag. */
215	#define X86_EFL_OF RT_BIT_32(11)
216	#define X86_EFL_OF_BIT 11
217	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
218	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
219	/** Bit 14 - NT - Nested task flag - System flag. */
220	#define X86_EFL_NT RT_BIT_32(14)
221	#define X86_EFL_NT_BIT 14
222	/** Bit 16 - RF - Resume flag - System flag. */
223	#define X86_EFL_RF RT_BIT_32(16)
224	#define X86_EFL_RF_BIT 16
225	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
226	#define X86_EFL_VM RT_BIT_32(17)
227	#define X86_EFL_VM_BIT 17
228	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
229	#define X86_EFL_AC RT_BIT_32(18)
230	#define X86_EFL_AC_BIT 18
231	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
232	#define X86_EFL_VIF RT_BIT_32(19)
233	#define X86_EFL_VIF_BIT 19
234	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
235	#define X86_EFL_VIP RT_BIT_32(20)
236	#define X86_EFL_VIP_BIT 20
237	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
238	#define X86_EFL_ID RT_BIT_32(21)
239	#define X86_EFL_ID_BIT 21
240	/** All live bits. */
241	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
242	/** Read as 1 bits. */
243	#define X86_EFL_RA1_MASK RT_BIT_32(1)
244	/** Read as 0 bits, excluding bits 31:22.
245	* Bits 3, 5, 15, and 22 thru 31. */
246	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
247	/** Read as 0 bits, excluding bits 31:22.
248	* Bits 3, 5 and 15. */
249	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
250	/** IOPL shift. */
251	#define X86_EFL_IOPL_SHIFT 12
252	/** The IOPL level from the flags. */
253	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
254	/** Bits restored by popf */
255	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
256	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
257	/** Bits restored by popf */
258	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
259	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
260	/** The status bits commonly updated by arithmetic instructions. */
261	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
262	/** @} */
263
264
265	#ifndef __ASSEMBLER__
266
267	/** CPUID Feature information - ECX.
268	* CPUID query with EAX=1.
269	*/
270	# ifndef VBOX_FOR_DTRACE_LIB
271	typedef struct X86CPUIDFEATECX
272	{
273	/** Bit 0 - SSE3 - Supports SSE3 or not. */
274	unsigned u1SSE3 : 1;
275	/** Bit 1 - PCLMULQDQ. */
276	unsigned u1PCLMULQDQ : 1;
277	/** Bit 2 - DS Area 64-bit layout. */
278	unsigned u1DTE64 : 1;
279	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
280	unsigned u1Monitor : 1;
281	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
282	unsigned u1CPLDS : 1;
283	/** Bit 5 - VMX - Virtual Machine Technology. */
284	unsigned u1VMX : 1;
285	/** Bit 6 - SMX: Safer Mode Extensions. */
286	unsigned u1SMX : 1;
287	/** Bit 7 - EST - Enh. SpeedStep Tech. */
288	unsigned u1EST : 1;
289	/** Bit 8 - TM2 - Terminal Monitor 2. */
290	unsigned u1TM2 : 1;
291	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
292	unsigned u1SSSE3 : 1;
293	/** Bit 10 - CNTX-ID - L1 Context ID. */
294	unsigned u1CNTXID : 1;
295	/** Bit 11 - Reserved. */
296	unsigned u1Reserved1 : 1;
297	/** Bit 12 - FMA. */
298	unsigned u1FMA : 1;
299	/** Bit 13 - CX16 - CMPXCHG16B. */
300	unsigned u1CX16 : 1;
301	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
302	unsigned u1TPRUpdate : 1;
303	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
304	unsigned u1PDCM : 1;
305	/** Bit 16 - Reserved. */
306	unsigned u1Reserved2 : 1;
307	/** Bit 17 - PCID - Process-context identifiers. */
308	unsigned u1PCID : 1;
309	/** Bit 18 - Direct Cache Access. */
310	unsigned u1DCA : 1;
311	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
312	unsigned u1SSE4_1 : 1;
313	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
314	unsigned u1SSE4_2 : 1;
315	/** Bit 21 - x2APIC. */
316	unsigned u1x2APIC : 1;
317	/** Bit 22 - MOVBE - Supports MOVBE. */
318	unsigned u1MOVBE : 1;
319	/** Bit 23 - POPCNT - Supports POPCNT. */
320	unsigned u1POPCNT : 1;
321	/** Bit 24 - TSC-Deadline. */
322	unsigned u1TSCDEADLINE : 1;
323	/** Bit 25 - AES. */
324	unsigned u1AES : 1;
325	/** Bit 26 - XSAVE - Supports XSAVE. */
326	unsigned u1XSAVE : 1;
327	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
328	unsigned u1OSXSAVE : 1;
329	/** Bit 28 - AVX - Supports AVX instruction extensions. */
330	unsigned u1AVX : 1;
331	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
332	unsigned u1F16C : 1;
333	/** Bit 30 - RDRAND - Supports RDRAND. */
334	unsigned u1RDRAND : 1;
335	/** Bit 31 - Hypervisor present (we're a guest). */
336	unsigned u1HVP : 1;
337	} X86CPUIDFEATECX;
338	# else /* VBOX_FOR_DTRACE_LIB */
339	typedef uint32_t X86CPUIDFEATECX;
340	# endif /* VBOX_FOR_DTRACE_LIB */
341	/** Pointer to CPUID Feature Information - ECX. */
342	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
343	/** Pointer to const CPUID Feature Information - ECX. */
344	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
345
346
347	/** CPUID Feature Information - EDX.
348	* CPUID query with EAX=1.
349	*/
350	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
351	typedef struct X86CPUIDFEATEDX
352	{
353	/** Bit 0 - FPU - x87 FPU on Chip. */
354	unsigned u1FPU : 1;
355	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
356	unsigned u1VME : 1;
357	/** Bit 2 - DE - Debugging extensions. */
358	unsigned u1DE : 1;
359	/** Bit 3 - PSE - Page Size Extension. */
360	unsigned u1PSE : 1;
361	/** Bit 4 - TSC - Time Stamp Counter. */
362	unsigned u1TSC : 1;
363	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
364	unsigned u1MSR : 1;
365	/** Bit 6 - PAE - Physical Address Extension. */
366	unsigned u1PAE : 1;
367	/** Bit 7 - MCE - Machine Check Exception. */
368	unsigned u1MCE : 1;
369	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
370	unsigned u1CX8 : 1;
371	/** Bit 9 - APIC - APIC On-Chip. */
372	unsigned u1APIC : 1;
373	/** Bit 10 - Reserved. */
374	unsigned u1Reserved1 : 1;
375	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
376	unsigned u1SEP : 1;
377	/** Bit 12 - MTRR - Memory Type Range Registers. */
378	unsigned u1MTRR : 1;
379	/** Bit 13 - PGE - PTE Global Bit. */
380	unsigned u1PGE : 1;
381	/** Bit 14 - MCA - Machine Check Architecture. */
382	unsigned u1MCA : 1;
383	/** Bit 15 - CMOV - Conditional Move Instructions. */
384	unsigned u1CMOV : 1;
385	/** Bit 16 - PAT - Page Attribute Table. */
386	unsigned u1PAT : 1;
387	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
388	unsigned u1PSE36 : 1;
389	/** Bit 18 - PSN - Processor Serial Number. */
390	unsigned u1PSN : 1;
391	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
392	unsigned u1CLFSH : 1;
393	/** Bit 20 - Reserved. */
394	unsigned u1Reserved2 : 1;
395	/** Bit 21 - DS - Debug Store. */
396	unsigned u1DS : 1;
397	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
398	unsigned u1ACPI : 1;
399	/** Bit 23 - MMX - Intel MMX 'Technology'. */
400	unsigned u1MMX : 1;
401	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
402	unsigned u1FXSR : 1;
403	/** Bit 25 - SSE - SSE Support. */
404	unsigned u1SSE : 1;
405	/** Bit 26 - SSE2 - SSE2 Support. */
406	unsigned u1SSE2 : 1;
407	/** Bit 27 - SS - Self Snoop. */
408	unsigned u1SS : 1;
409	/** Bit 28 - HTT - Hyper-Threading Technology. */
410	unsigned u1HTT : 1;
411	/** Bit 29 - TM - Thermal Monitor. */
412	unsigned u1TM : 1;
413	/** Bit 30 - Reserved - . */
414	unsigned u1Reserved3 : 1;
415	/** Bit 31 - PBE - Pending Break Enabled. */
416	unsigned u1PBE : 1;
417	} X86CPUIDFEATEDX;
418	# else /* VBOX_FOR_DTRACE_LIB */
419	typedef uint32_t X86CPUIDFEATEDX;
420	# endif /* VBOX_FOR_DTRACE_LIB */
421	/** Pointer to CPUID Feature Information - EDX. */
422	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
423	/** Pointer to const CPUID Feature Information - EDX. */
424	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
425
426	#endif /* !__ASSEMBLER__ */
427
428
429	/** @name CPUID Vendor information.
430	* CPUID query with EAX=0.
431	* @{
432	*/
433	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
434	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
435	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
436
437	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
438	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
439	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
440
441	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
442	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
443	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
444
445	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
446	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
447	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
448
449	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
450	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
451	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
452	/** @} */
453
454
455	/** @name CPUID Feature information.
456	* CPUID query with EAX=1.
457	* @{
458	*/
459	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
460	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
461	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
462	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
463	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
464	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
465	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
466	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
467	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
468	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
469	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
470	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
471	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
472	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
473	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
474	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
475	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
476	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
477	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
478	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
479	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
480	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
481	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
482	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
483	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
484	/** ECX Bit 12 - FMA. */
485	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
486	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
487	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
488	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
489	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
490	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
491	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
492	/** ECX Bit 17 - PCID - Process-context identifiers. */
493	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
494	/** ECX Bit 18 - DCA - Direct Cache Access. */
495	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
496	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
497	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
498	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
499	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
500	/** ECX Bit 21 - x2APIC support. */
501	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
502	/** ECX Bit 22 - MOVBE instruction. */
503	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
504	/** ECX Bit 23 - POPCNT instruction. */
505	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
506	/** ECX Bir 24 - TSC-Deadline. */
507	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
508	/** ECX Bit 25 - AES instructions. */
509	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
510	/** ECX Bit 26 - XSAVE instruction. */
511	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
512	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
513	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
514	/** ECX Bit 28 - AVX. */
515	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
516	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
517	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
518	/** ECX Bit 30 - RDRAND instruction. */
519	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
520	/** ECX Bit 31 - Hypervisor Present (software only). */
521	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
522
523
524	/** Bit 0 - FPU - x87 FPU on Chip. */
525	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
526	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
527	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
528	/** Bit 2 - DE - Debugging extensions. */
529	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
530	/** Bit 3 - PSE - Page Size Extension. */
531	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
532	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
533	/** Bit 4 - TSC - Time Stamp Counter. */
534	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
535	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
536	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
537	/** Bit 6 - PAE - Physical Address Extension. */
538	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
539	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
540	/** Bit 7 - MCE - Machine Check Exception. */
541	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
542	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
543	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
544	/** Bit 9 - APIC - APIC On-Chip. */
545	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
546	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
547	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
548	/** Bit 12 - MTRR - Memory Type Range Registers. */
549	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
550	/** Bit 13 - PGE - PTE Global Bit. */
551	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
552	/** Bit 14 - MCA - Machine Check Architecture. */
553	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
554	/** Bit 15 - CMOV - Conditional Move Instructions. */
555	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
556	/** Bit 16 - PAT - Page Attribute Table. */
557	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
558	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
559	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
560	/** Bit 18 - PSN - Processor Serial Number. */
561	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
562	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
563	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
564	/** Bit 21 - DS - Debug Store. */
565	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
566	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
567	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
568	/** Bit 23 - MMX - Intel MMX Technology. */
569	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
570	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
571	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
572	/** Bit 25 - SSE - SSE Support. */
573	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
574	/** Bit 26 - SSE2 - SSE2 Support. */
575	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
576	/** Bit 27 - SS - Self Snoop. */
577	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
578	/** Bit 28 - HTT - Hyper-Threading Technology. */
579	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
580	/** Bit 29 - TM - Therm. Monitor. */
581	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
582	/** Bit 31 - PBE - Pending Break Enabled. */
583	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
584	/** @} */
585
586	/** @name CPUID mwait/monitor information.
587	* CPUID query with EAX=5.
588	* @{
589	*/
590	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
591	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
592	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
593	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
594	/** @} */
595
596
597	/** @name CPUID Thermal and Power Management information.
598	* Generally Intel only unless noted otherwise.
599	* CPUID query with EAX=5. @{
600	*/
601	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
602	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
603	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
604	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
605	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
606	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
607	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
608	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
609	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
610	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
611	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
612	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
613	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
614	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
615	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
616	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
617	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
618	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
619	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
620	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
621	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
622	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
623	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
624	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
625	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
626	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
627	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
628	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
629	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
630	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
631	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
632	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
633
634	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
635	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
636	/** @} */
637
638
639	/** @name CPUID Structured Extended Feature information.
640	* CPUID query with EAX=7.
641	* @{
642	*/
643	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
644	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
645	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
646	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
647	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
648	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
649	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
650	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
651	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
652	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
653	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
654	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
655	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
656	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
657	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
658	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
659	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
660	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
661	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
662	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
663	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
664	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
665	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
666	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
667	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
668	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
669	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
670	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
671	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
672	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
673	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
674	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
675	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
676	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
677	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
678	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
679	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
680	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
681	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
682	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
683	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
684	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
685	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
686	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
687	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
688	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
689	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
690	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
691	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
692	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
693	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
694	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
695
696	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
697	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
698	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
699	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
700	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
701	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
702	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
703	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
704	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
705	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
706	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
707	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
708	/** ECX Bit 22 - RDPID - Support pread process ID. */
709	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
710	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
711	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
712
713	/** EDX bit 9 - SRBDS_CTRL - (Special Register Buffer Data Sample Control)
714	* Supports IA32_MCU_OPT_CTRL and IA32_MCU_OPT_CTRL.RNGDS_MITG_DIS. */
715	#define X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL RT_BIT_32(9)
716	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
717	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
718	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
719	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
720	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
721	* IBPB command in IA32_PRED_CMD. */
722	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
723	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
724	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
725	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
726	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
727	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
728	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
729	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
730	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
731	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
732	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
733
734	/** @} */
735
736
737	/** @name CPUID Extended Feature information.
738	* CPUID query with EAX=0x80000001.
739	* @{
740	*/
741	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
742	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
743
744	/** EDX Bit 11 - SYSCALL/SYSRET. */
745	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
746	/** EDX Bit 20 - No-Execute/Execute-Disable. */
747	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
748	/** EDX Bit 26 - 1 GB large page. */
749	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
750	/** EDX Bit 27 - RDTSCP. */
751	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
752	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
753	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
754	/** @}*/
755
756	/** @name CPUID AMD Feature information.
757	* CPUID query with EAX=0x80000001.
758	* @{
759	*/
760	/** Bit 0 - FPU - x87 FPU on Chip. */
761	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
762	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
763	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
764	/** Bit 2 - DE - Debugging extensions. */
765	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
766	/** Bit 3 - PSE - Page Size Extension. */
767	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
768	/** Bit 4 - TSC - Time Stamp Counter. */
769	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
770	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
771	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
772	/** Bit 6 - PAE - Physical Address Extension. */
773	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
774	/** Bit 7 - MCE - Machine Check Exception. */
775	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
776	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
777	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
778	/** Bit 9 - APIC - APIC On-Chip. */
779	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
780	/** Bit 12 - MTRR - Memory Type Range Registers. */
781	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
782	/** Bit 13 - PGE - PTE Global Bit. */
783	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
784	/** Bit 14 - MCA - Machine Check Architecture. */
785	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
786	/** Bit 15 - CMOV - Conditional Move Instructions. */
787	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
788	/** Bit 16 - PAT - Page Attribute Table. */
789	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
790	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
791	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
792	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
793	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
794	/** Bit 23 - MMX - Intel MMX Technology. */
795	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
796	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
797	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
798	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
799	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
800	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
801	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
802	/** Bit 31 - 3DNOW - AMD 3DNow. */
803	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
804
805	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
806	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
807	/** Bit 2 - SVM - AMD VM extensions. */
808	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
809	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
810	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
811	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
812	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
813	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
814	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
815	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
816	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
817	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
818	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
819	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
820	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
821	/** Bit 9 - OSVW - AMD OS visible workaround. */
822	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
823	/** Bit 10 - IBS - Instruct based sampling. */
824	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
825	/** Bit 11 - XOP - Extended operation support (see APM6). */
826	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
827	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
828	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
829	/** Bit 13 - WDT - AMD Watchdog timer support. */
830	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
831	/** Bit 15 - LWP - Lightweight profiling support. */
832	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
833	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
834	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
835	/** Bit 19 - NodeId - Indicates support for
836	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
837	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
838	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
839	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
840	/** Bit 22 - TopologyExtensions - . */
841	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
842	/** @} */
843
844
845	/** @name CPUID AMD Feature information.
846	* CPUID query with EAX=0x80000007.
847	* @{
848	*/
849	/** Bit 0 - TS - Temperature Sensor. */
850	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
851	/** Bit 1 - FID - Frequency ID Control. */
852	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
853	/** Bit 2 - VID - Voltage ID Control. */
854	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
855	/** Bit 3 - TTP - THERMTRIP. */
856	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
857	/** Bit 4 - TM - Hardware Thermal Control. */
858	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
859	/** Bit 5 - STC - Software Thermal Control. */
860	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
861	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
862	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
863	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
864	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
865	/** Bit 8 - TSCINVAR - TSC Invariant. */
866	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
867	/** Bit 9 - CPB - TSC Invariant. */
868	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
869	/** Bit 10 - EffFreqRO - MPERF/APERF. */
870	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
871	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
872	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
873	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
874	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
875	/** @} */
876
877
878	/** @name CPUID AMD extended feature extensions ID (EBX).
879	* CPUID query with EAX=0x80000008.
880	* @{
881	*/
882	/** Bit 0 - CLZERO - Clear zero instruction. */
883	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
884	/** Bit 1 - IRPerf - Instructions retired count support. */
885	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
886	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
887	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
888	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
889	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
890	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
891	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
892	/* AMD pipeline length: 9 feature bits ;-) */
893	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
894	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
895	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
896	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
897	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
898	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
899	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
900	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
901	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
902	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
903	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
904	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
905	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
906	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
907	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
908	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
909	/** Bit 26 - Speculative Store Bypass Disable not required. */
910	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
911	/** @} */
912
913
914	/** @name CPUID AMD SVM Feature information.
915	* CPUID query with EAX=0x8000000a.
916	* @{
917	*/
918	/** Bit 0 - NP - Nested Paging supported. */
919	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
920	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
921	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
922	/** Bit 2 - SVML - SVM locking bit supported. */
923	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
924	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
925	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
926	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
927	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
928	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
929	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
930	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
931	* VMCB.TLB_Control is supported. */
932	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
933	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
934	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
935	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
936	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
937	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
938	* intercept filter cycle count threshold. */
939	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
940	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
941	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
942	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
943	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
944	/** Bit 16 - VGIF - Supports virtualized GIF. */
945	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
946	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
947	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
948	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
949	* mode. */
950	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
951	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
952	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
953	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
954	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
955	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
956	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
957	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
958	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
959	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
960	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
961	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
962	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
963	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
964	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
965	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
966	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
967	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
968	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
969	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
970	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
971
972	/** @} */
973
974
975	/** @name CR0
976	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
977	* reserved flags.
978	* @{ */
979	/** Bit 0 - PE - Protection Enabled */
980	#define X86_CR0_PE RT_BIT_32(0)
981	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
982	#define X86_CR0_PE_BIT 0
983	/** Bit 1 - MP - Monitor Coprocessor */
984	#define X86_CR0_MP RT_BIT_32(1)
985	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
986	#define X86_CR0_MP_BIT 1
987	/** Bit 2 - EM - Emulation. */
988	#define X86_CR0_EM RT_BIT_32(2)
989	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
990	#define X86_CR0_EM_BIT 2
991	/** Bit 3 - TS - Task Switch. */
992	#define X86_CR0_TS RT_BIT_32(3)
993	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
994	#define X86_CR0_TS_BIT 3
995	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
996	#define X86_CR0_ET RT_BIT_32(4)
997	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
998	#define X86_CR0_ET_BIT 4
999	/** Bit 5 - NE - Numeric error (486+). */
1000	#define X86_CR0_NE RT_BIT_32(5)
1001	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
1002	#define X86_CR0_NE_BIT 5
1003	/** Bit 16 - WP - Write Protect (486+). */
1004	#define X86_CR0_WP RT_BIT_32(16)
1005	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1006	#define X86_CR0_WP_BIT 16
1007	/** Bit 18 - AM - Alignment Mask (486+). */
1008	#define X86_CR0_AM RT_BIT_32(18)
1009	#define X86_CR0_ALIGNMENT_MASK RT_BIT_32(18)
1010	#define X86_CR0_AM_BIT 18
1011	/** Bit 29 - NW - Not Write-though (486+). */
1012	#define X86_CR0_NW RT_BIT_32(29)
1013	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1014	#define X86_CR0_NW_BIT 29
1015	/** Bit 30 - WP - Cache Disable (486+). */
1016	#define X86_CR0_CD RT_BIT_32(30)
1017	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1018	#define X86_CR0_CD_BIT 30
1019	/** Bit 31 - PG - Paging. */
1020	#define X86_CR0_PG RT_BIT_32(31)
1021	#define X86_CR0_PAGING RT_BIT_32(31)
1022	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1023	/** @} */
1024
1025
1026	/** @name CR3
1027	* @{ */
1028	/** Bit 3 - PWT - Page-level Writes Transparent. */
1029	#define X86_CR3_PWT RT_BIT_32(3)
1030	#define X86_CR3_PWT_BIT 3
1031	/** Bit 4 - PCD - Page-level Cache Disable. */
1032	#define X86_CR3_PCD RT_BIT_32(4)
1033	#define X86_CR3_PCD_BIT 4
1034	/** Bits 12-31 - - Page directory page number. */
1035	#define X86_CR3_PAGE_MASK (0xfffff000)
1036	/** Bits 5-31 - - PAE Page directory page number. */
1037	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1038	/** Bits 12-51 - - AMD64 PML4 page number.
1039	* @note This is a maxed out mask, the actual acceptable CR3 value can
1040	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1041	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1042	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1043	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1044	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1045	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1046	/** @} */
1047
1048
1049	/** @name CR4
1050	* @{ */
1051	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1052	#define X86_CR4_VME RT_BIT_32(0)
1053	#define X86_CR4_VME_BIT 0
1054	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1055	#define X86_CR4_PVI RT_BIT_32(1)
1056	#define X86_CR4_PVI_BIT 1
1057	/** Bit 2 - TSD - Time Stamp Disable. */
1058	#define X86_CR4_TSD RT_BIT_32(2)
1059	#define X86_CR4_TSD_BIT 2
1060	/** Bit 3 - DE - Debugging Extensions. */
1061	#define X86_CR4_DE RT_BIT_32(3)
1062	#define X86_CR4_DE_BIT 3
1063	/** Bit 4 - PSE - Page Size Extension. */
1064	#define X86_CR4_PSE RT_BIT_32(4)
1065	#define X86_CR4_PSE_BIT 4
1066	/** Bit 5 - PAE - Physical Address Extension. */
1067	#define X86_CR4_PAE RT_BIT_32(5)
1068	#define X86_CR4_PAE_BIT 5
1069	/** Bit 6 - MCE - Machine-Check Enable. */
1070	#define X86_CR4_MCE RT_BIT_32(6)
1071	#define X86_CR4_MCE_BIT 6
1072	/** Bit 7 - PGE - Page Global Enable. */
1073	#define X86_CR4_PGE RT_BIT_32(7)
1074	#define X86_CR4_PGE_BIT 7
1075	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1076	#define X86_CR4_PCE RT_BIT_32(8)
1077	#define X86_CR4_PCE_BIT 8
1078	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1079	#define X86_CR4_OSFXSR RT_BIT_32(9)
1080	#define X86_CR4_OSFXSR_BIT 9
1081	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1082	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1083	#define X86_CR4_OSXMMEEXCPT_BIT 10
1084	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1085	#define X86_CR4_UMIP RT_BIT_32(11)
1086	#define X86_CR4_UMIP_BIT 11
1087	/** Bit 13 - VMXE - VMX mode is enabled. */
1088	#define X86_CR4_VMXE RT_BIT_32(13)
1089	#define X86_CR4_VMXE_BIT 13
1090	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1091	#define X86_CR4_SMXE RT_BIT_32(14)
1092	#define X86_CR4_SMXE_BIT 14
1093	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1094	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1095	#define X86_CR4_FSGSBASE_BIT 16
1096	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1097	#define X86_CR4_PCIDE RT_BIT_32(17)
1098	#define X86_CR4_PCIDE_BIT 17
1099	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1100	* extended states. */
1101	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1102	#define X86_CR4_OSXSAVE_BIT 18
1103	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1104	#define X86_CR4_SMEP RT_BIT_32(20)
1105	#define X86_CR4_SMEP_BIt 20
1106	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1107	#define X86_CR4_SMAP RT_BIT_32(21)
1108	#define X86_CR4_SMAP_BIT 21
1109	/** Bit 22 - PKE - Protection Key Enable. */
1110	#define X86_CR4_PKE RT_BIT_32(22)
1111	#define X86_CR4_PKE_BIT 22
1112	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1113	#define X86_CR4_CET RT_BIT_32(23)
1114	#define X86_CR4_CET_BIT 23
1115	/** @} */
1116
1117
1118	/** @name DR6
1119	* @{ */
1120	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1121	#define X86_DR6_B0 RT_BIT_32(0)
1122	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1123	#define X86_DR6_B1 RT_BIT_32(1)
1124	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1125	#define X86_DR6_B2 RT_BIT_32(2)
1126	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1127	#define X86_DR6_B3 RT_BIT_32(3)
1128	/** Mask of all the Bx bits. */
1129	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1130	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1131	#define X86_DR6_BD RT_BIT_32(13)
1132	/** Bit 14 - BS - Single step */
1133	#define X86_DR6_BS RT_BIT_32(14)
1134	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1135	#define X86_DR6_BT RT_BIT_32(15)
1136	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1137	#define X86_DR6_RTM RT_BIT_32(16)
1138	/** Value of DR6 after powerup/reset. */
1139	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1140	/** Bits which must be 1s in DR6. */
1141	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1142	/** Bits which must be 1s in DR6, when RTM is supported. */
1143	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1144	/** Bits which must be 0s in DR6. */
1145	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1146	/** Bits which must be 0s on writes to DR6. */
1147	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1148	/** @} */
1149
1150	/** Get the DR6.Bx bit for a the given breakpoint. */
1151	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1152
1153
1154	/** @name DR7
1155	* @{ */
1156	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1157	#define X86_DR7_L0 RT_BIT_32(0)
1158	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1159	#define X86_DR7_G0 RT_BIT_32(1)
1160	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1161	#define X86_DR7_L1 RT_BIT_32(2)
1162	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1163	#define X86_DR7_G1 RT_BIT_32(3)
1164	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1165	#define X86_DR7_L2 RT_BIT_32(4)
1166	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1167	#define X86_DR7_G2 RT_BIT_32(5)
1168	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1169	#define X86_DR7_L3 RT_BIT_32(6)
1170	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1171	#define X86_DR7_G3 RT_BIT_32(7)
1172	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1173	#define X86_DR7_LE RT_BIT_32(8)
1174	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1175	#define X86_DR7_GE RT_BIT_32(9)
1176
1177	/** L0, L1, L2, and L3. */
1178	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1179	/** L0, L1, L2, and L3. */
1180	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1181
1182	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1183	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1184	#define X86_DR7_RTM RT_BIT_32(11)
1185	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1186	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1187	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1188	* instruction is executed.
1189	* @see http://www.rcollins.org/secrets/DR7.html */
1190	#define X86_DR7_ICE_IR RT_BIT_32(12)
1191	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1192	* any DR register is accessed. */
1193	#define X86_DR7_GD RT_BIT_32(13)
1194	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1195	* Pentium. */
1196	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1197	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1198	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1199	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1200	#define X86_DR7_RW0_MASK (3 << 16)
1201	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1202	#define X86_DR7_LEN0_MASK (3 << 18)
1203	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1204	#define X86_DR7_RW1_MASK (3 << 20)
1205	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1206	#define X86_DR7_LEN1_MASK (3 << 22)
1207	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1208	#define X86_DR7_RW2_MASK (3 << 24)
1209	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1210	#define X86_DR7_LEN2_MASK (3 << 26)
1211	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1212	#define X86_DR7_RW3_MASK (3 << 28)
1213	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1214	#define X86_DR7_LEN3_MASK (3 << 30)
1215
1216	/** Bits which reads as 1s. */
1217	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1218	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1219	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1220	/** Bits which must be 0s when writing to DR7. */
1221	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1222
1223	/** Calcs the L bit of Nth breakpoint.
1224	* @param iBp The breakpoint number [0..3].
1225	*/
1226	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1227
1228	/** Calcs the G bit of Nth breakpoint.
1229	* @param iBp The breakpoint number [0..3].
1230	*/
1231	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1232
1233	/** Calcs the L and G bits of Nth breakpoint.
1234	* @param iBp The breakpoint number [0..3].
1235	*/
1236	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1237
1238	/** @name Read/Write values.
1239	* @{ */
1240	/** Break on instruction fetch only. */
1241	#define X86_DR7_RW_EO UINT32_C(0)
1242	/** Break on write only. */
1243	#define X86_DR7_RW_WO UINT32_C(1)
1244	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1245	#define X86_DR7_RW_IO UINT32_C(2)
1246	/** Break on read or write (but not instruction fetches). */
1247	#define X86_DR7_RW_RW UINT32_C(3)
1248	/** @} */
1249
1250	/** Shifts a X86_DR7_RW_* value to its right place.
1251	* @param iBp The breakpoint number [0..3].
1252	* @param fRw One of the X86_DR7_RW_* value.
1253	*/
1254	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1255
1256	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1257	* one of the X86_DR7_RW_XXX constants).
1258	*
1259	* @returns X86_DR7_RW_XXX
1260	* @param uDR7 DR7 value
1261	* @param iBp The breakpoint number [0..3].
1262	*/
1263	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1264
1265	/** R/W0, R/W1, R/W2, and R/W3. */
1266	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1267
1268	#ifndef VBOX_FOR_DTRACE_LIB
1269	/** Checks if the RW and LEN fields are set up for an instruction breakpoint.
1270	* @note This does not check if it's enabled. */
1271	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1272	/** Checks if an instruction breakpoint is enabled and configured correctly.
1273	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1274	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1275	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1276	/** Checks if there are any instruction fetch breakpoint types configured in
1277	* the RW and LEN registers and enabled in the Lx/Gx bits.
1278	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1279	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1280	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1281	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1282	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1283	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1284
1285	/** Checks if the RW field is set up for a read-write data breakpoint.
1286	* @note This does not check if it's enabled. */
1287	# define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (UINT32_C(0x00030000) << ((a_iBp) * 4))) == 0)
1288
1289	/** Checks if there are any read-write data breakpoint types configured in the
1290	* RW registers and enabled in the Lx/Gx bits.
1291	*
1292	* @note We don't consider the LEN registers here, even if qword isn't
1293	* techincally valid for older processors - see
1294	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1295	*/
1296	# define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
1297	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
1298	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
1299	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
1300	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
1301
1302	/** Checks if the RW field is set up for a write-only or read-write data
1303	* breakpoint.
1304	* @note This does not check if it's enabled. */
1305	# define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x00010000) << ((a_iBp) * 4))) != 0)
1306
1307	/** Checks if there are any read-write or write-only data breakpoint types
1308	* configured in the the RW registers and enabled in the Lx/Gx bits.
1309	*
1310	* @note We don't consider the LEN registers here, even if qword isn't
1311	* techincally valid for older processors - see
1312	* @sdmv3{082,645,18.2.4,Debug Control Register (DR7)} for details.
1313	*/
1314	# define X86_DR7_ANY_W_ENABLED(a_uDR7) \
1315	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
1316	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
1317	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
1318	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
1319
1320	/** Checks if there are any I/O breakpoint types configured in the RW
1321	* registers. Does NOT check if these are enabled, sorry. */
1322	# define X86_DR7_ANY_RW_IO(uDR7) \
1323	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1324	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1325	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1326	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1327	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1328	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1329	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1330	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1331	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1332	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1333	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1334
1335	#endif /* !VBOX_FOR_DTRACE_LIB */
1336
1337	/** @name Length values.
1338	* @{ */
1339	#define X86_DR7_LEN_BYTE UINT32_C(0)
1340	#define X86_DR7_LEN_WORD UINT32_C(1)
1341	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1342	#define X86_DR7_LEN_DWORD UINT32_C(3)
1343	/** @} */
1344
1345	/** Shifts a X86_DR7_LEN_* value to its right place.
1346	* @param iBp The breakpoint number [0..3].
1347	* @param cb One of the X86_DR7_LEN_* values.
1348	*/
1349	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1350
1351	/** Fetch the breakpoint length bits from the DR7 value.
1352	* @param uDR7 DR7 value
1353	* @param iBp The breakpoint number [0..3].
1354	*/
1355	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1356
1357	/** Mask used to check if any breakpoints are enabled. */
1358	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1359
1360	/** LEN0, LEN1, LEN2, and LEN3. */
1361	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1362	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1363	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1364
1365	/** Value of DR7 after powerup/reset. */
1366	#define X86_DR7_INIT_VAL 0x400
1367	/** @} */
1368
1369
1370	/** @name Machine Specific Registers
1371	* @{
1372	*/
1373	/** Machine check address register (P5). */
1374	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1375	/** Machine check type register (P5). */
1376	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1377	/** Time Stamp Counter. */
1378	#define MSR_IA32_TSC 0x10
1379	#define MSR_IA32_CESR UINT32_C(0x00000011)
1380	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1381	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1382
1383	#define MSR_IA32_PLATFORM_ID 0x17
1384
1385	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1386	# define MSR_IA32_APICBASE 0x1b
1387	/** Local APIC enabled. */
1388	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1389	/** X2APIC enabled (requires the EN bit to be set). */
1390	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1391	/** The processor is the boot strap processor (BSP). */
1392	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1393	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1394	* width. */
1395	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1396	/** The default physical base address of the APIC. */
1397	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1398	/** Gets the physical base address from the MSR. */
1399	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1400	#endif
1401
1402	/** Memory Control (Intel-specific). */
1403	#define MSR_MEMORY_CTRL 0x33
1404	/** Memory Control - UC-store throttle. */
1405	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1406	/** Memory Control - UC-lock disable. */
1407	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1408	/** Memory Control - Split-lock disable. */
1409	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1410
1411	/** Undocumented intel MSR for reporting thread and core counts.
1412	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1413	* first 16 bits is the thread count. The next 16 bits the core count, except
1414	* on Westmere where it seems it's only the next 4 bits for some reason. */
1415	#define MSR_CORE_THREAD_COUNT 0x35
1416
1417	/** CPU Feature control. */
1418	#define MSR_IA32_FEATURE_CONTROL 0x3A
1419	/** Feature control - Lock MSR from writes (R/W0). */
1420	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1421	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1422	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1423	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1424	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1425	/** Feature control - SENTER local functions enable (R/WL). */
1426	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1427	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1428	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1429	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1430	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1431	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1432	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1433	/** Feature control - SENTER global enable (R/WL). */
1434	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1435	/** Feature control - SGX launch control enable (R/WL). */
1436	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1437	/** Feature control - SGX global enable (R/WL). */
1438	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1439	/** Feature control - LMCE on (R/WL). */
1440	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1441
1442	/** Per-processor TSC adjust MSR. */
1443	#define MSR_IA32_TSC_ADJUST 0x3B
1444
1445	/** Spectre control register.
1446	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1447	#define MSR_IA32_SPEC_CTRL 0x48
1448	/** @name MSR_IA32_SPEC_CTRL bits
1449	* @{ */
1450	/** IBRS - Indirect branch restricted speculation. */
1451	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_64(0)
1452	/** STIBP - Single thread indirect branch predictors. */
1453	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_64(1)
1454	/** SSBD - Speculative Store Bypass Disable. */
1455	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_64(2)
1456	#define MSR_IA32_SPEC_CTRL_F_IPRED_DIS_U RT_BIT_64(3)
1457	#define MSR_IA32_SPEC_CTRL_F_IPRED_DIS_S RT_BIT_64(4)
1458	#define MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_U RT_BIT_64(5)
1459	#define MSR_IA32_SPEC_CTRL_F_RRSBA_DIS_S RT_BIT_64(6)
1460	#define MSR_IA32_SPEC_CTRL_F_PSFD RT_BIT_64(7)
1461	#define MSR_IA32_SPEC_CTRL_F_DDPD_U RT_BIT_64(8)
1462	/* 9 is reserved (for DDPD_S?) */
1463	#define MSR_IA32_SPEC_CTRL_F_BHI_DIS_S RT_BIT_64(9)
1464	/** @} */
1465
1466	/** Prediction command register.
1467	* Write only, logical processor scope, no state since write only. */
1468	#define MSR_IA32_PRED_CMD 0x49
1469	/** IBPB - Indirect branch prediction barrie when written as 1. */
1470	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_64(0)
1471
1472	/** BIOS update trigger (microcode update). */
1473	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1474
1475	/** BIOS update signature (microcode). */
1476	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1477
1478	/** SMM monitor control. */
1479	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1480	/** SMM control - Valid. */
1481	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1482	/** SMM control - VMXOFF unblocks SMI. */
1483	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1484	/** SMM control - MSEG base physical address. */
1485	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1486
1487	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1488	#define MSR_IA32_SMBASE 0x9E
1489
1490	/** General performance counter no. 0. */
1491	#define MSR_IA32_PMC0 0xC1
1492	/** General performance counter no. 1. */
1493	#define MSR_IA32_PMC1 0xC2
1494	/** General performance counter no. 2. */
1495	#define MSR_IA32_PMC2 0xC3
1496	/** General performance counter no. 3. */
1497	#define MSR_IA32_PMC3 0xC4
1498	/** General performance counter no. 4. */
1499	#define MSR_IA32_PMC4 0xC5
1500	/** General performance counter no. 5. */
1501	#define MSR_IA32_PMC5 0xC6
1502	/** General performance counter no. 6. */
1503	#define MSR_IA32_PMC6 0xC7
1504	/** General performance counter no. 7. */
1505	#define MSR_IA32_PMC7 0xC8
1506
1507	/** Nehalem power control. */
1508	#define MSR_IA32_PLATFORM_INFO 0xCE
1509
1510	/** Core Capabilities (Intel-specific). */
1511	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1512	/** STLB QoS feature supported. */
1513	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1514	/** FUSA feature supported. */
1515	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1516	/** RSM instruction only allowed in CPL 0. */
1517	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1518	/** UC lock disable supported. */
1519	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1520	/** Split-lock disable supported. */
1521	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1522	/** Snoop filter QoS Mask MSRs supported. */
1523	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1524	/** UC store throttling supported. */
1525	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1526
1527	/** Get FSB clock status (Intel-specific). */
1528	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1529
1530	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1531	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1532
1533	/** C0 Maximum Frequency Clock Count */
1534	#define MSR_IA32_MPERF 0xE7
1535	/** C0 Actual Frequency Clock Count */
1536	#define MSR_IA32_APERF 0xE8
1537
1538	/** MTRR Capabilities. */
1539	#define MSR_IA32_MTRR_CAP 0xFE
1540	/** Bits 0-7 - VCNT - Variable range registers count. */
1541	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1542	/** Bit 8 - FIX - Fixed range registers supported. */
1543	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1544	/** Bit 10 - WC - Write-Combining memory type supported. */
1545	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1546	/** Bit 11 - SMRR - System Management Range Register supported. */
1547	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1548	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1549	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1550
1551
1552	#ifndef __ASSEMBLER__
1553	/**
1554	* Variable-range MTRR MSR pair.
1555	*/
1556	typedef struct X86MTRRVAR
1557	{
1558	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1559	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1560	} X86MTRRVAR;
1561	# ifndef VBOX_FOR_DTRACE_LIB
1562	AssertCompileSize(X86MTRRVAR, 16);
1563	# endif
1564	/** Pointer to a variable-range MTRR MSR pair. */
1565	typedef X86MTRRVAR *PX86MTRRVAR;
1566	/** Pointer to a const variable-range MTRR MSR pair. */
1567	typedef const X86MTRRVAR *PCX86MTRRVAR;
1568	#endif /* __ASSEMBLER__ */
1569
1570
1571	/** Memory types that can be encoded in MTRRs.
1572	* @{ */
1573	/** Uncacheable. */
1574	#define X86_MTRR_MT_UC 0
1575	/** Write Combining. */
1576	#define X86_MTRR_MT_WC 1
1577	/** Write-through. */
1578	#define X86_MTRR_MT_WT 4
1579	/** Write-protected. */
1580	#define X86_MTRR_MT_WP 5
1581	/** Writeback. */
1582	#define X86_MTRR_MT_WB 6
1583	/** @}*/
1584
1585	/** Architecture capabilities (bugfixes). */
1586	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1587	/** @name MSR_IA32_ARCH_CAPABILITIES bits
1588	* @{ */
1589	/** CPU is no subject to meltdown problems. */
1590	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_64(0)
1591	/** CPU has better IBRS and you can leave it on all the time. */
1592	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_64(1)
1593	/** CPU has return stack buffer (RSB) override. */
1594	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_64(2)
1595	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1596	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1597	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_64(3)
1598	/** CPU does not suffer from speculative store bypass (SSB) issues. */
1599	#define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_64(4)
1600	/** CPU does not suffer from microarchitectural data sampling (MDS) issues. */
1601	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_64(5)
1602	/** CPU does not suffer MCE after change code page size w/o invlpg issues. */
1603	#define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_64(6)
1604	/** CPU has RTM_DISABLE and TXS_CPUID_CLEAR support. */
1605	#define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_64(7)
1606	/** CPU does not suffer from transaction synchronization extensions (TSX)
1607	* asyncrhonous abort (TAA) issues. */
1608	#define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_64(8)
1609	/* 9 is 'reserved' */
1610	#define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_64(10)
1611	#define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_64(11)
1612	#define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_64(12)
1613	#define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_64(13)
1614	#define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_64(14)
1615	#define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_64(15)
1616	/* 16 is 'reserved' */
1617	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_64(17)
1618	#define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_64(18)
1619	#define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_64(19)
1620	#define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_64(20)
1621	#define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_64(21)
1622	/* 22 is 'reserved' */
1623	#define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_64(23)
1624	#define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_64(24)
1625	#define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_64(25)
1626	#define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_64(26)
1627	#define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_64(27)
1628	#define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_64(28)
1629	#define MSR_IA32_ARCH_CAP_F_IGN_UMONITOR_SUPPORT RT_BIT_64(29)
1630	#define MSR_IA32_ARCH_CAP_F_MON_UMON_MITIG_SUPPORT RT_BIT_64(30)
1631	/** @} */
1632
1633	/** Flush command register. */
1634	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1635	/** Flush the level 1 data cache when this bit is written. */
1636	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_64(0)
1637
1638	/** Cache control/info. */
1639	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1640
1641	/** Microcode Update Option Control (R/W). */
1642	#define MSR_IA32_MCU_OPT_CTRL 0x123
1643	/** MSR_IA32_MCU_OPT_CTRL[0]: RNGDS_MITG_DIS - disable SRBDS mitigations
1644	* for RDRAND & RDSEED when set. */
1645	#define MSR_IA32_MCU_OPT_CTRL_RNGDS_MITG_DIS RT_BIT_64(0)
1646	/** MSR_IA32_MCU_OPT_CTRL[1]: RTM_ALLOW - Allow TXS according to IA32_TSX_CTRL. */
1647	#define MSR_IA32_MCU_OPT_CTRL_RTM_ALLOW RT_BIT_64(1)
1648	/** MSR_IA32_MCU_OPT_CTRL[2]: RTM_LOCKED - Lock RTM_ALLOW at zero. */
1649	#define MSR_IA32_MCU_OPT_CTRL_RTM_LOCKED RT_BIT_64(2)
1650	/** MSR_IA32_MCU_OPT_CTRL[3]: FB_CLEAR_DIS - Disables FB_CLEAR part of VERW. */
1651	#define MSR_IA32_MCU_OPT_CTRL_FB_CLEAR_DIS RT_BIT_64(3)
1652	/** MSR_IA32_MCU_OPT_CTRL[4]: GDS_MITG_DIS - Disables GDS mitigation on core. */
1653	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_DIS RT_BIT_64(4)
1654	/** MSR_IA32_MCU_OPT_CTRL[5]: GDS_MITG_DIS - Disables GDS mitigation on core. */
1655	#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_LOCK RT_BIT_64(5)
1656	/** MSR_IA32_MCU_OPT_CTRL[6]: IGN_UMONITOR - Ignore UMONITOR & fail UMWAIT. */
1657	#define MSR_IA32_MCU_OPT_CTRL_IGN_UMONITOR RT_BIT_64(6)
1658	/** MSR_IA32_MCU_OPT_CTRL[7]: MON_UMON_MITG - UMONITOR/MONITOR mitigation
1659	* (may affect sibling hyperthreads). */
1660	#define MSR_IA32_MCU_OPT_CTRL_MON_UMON_MITG RT_BIT_64(7)
1661	/* Bits 63:7 reserved. */
1662	#define MSR_IA32_MCU_OPT_CTRL_RSVD_MASK UINT64_C(0xffffffffffffff80)
1663
1664	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1665	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1666	* R0 SS == CS + 8
1667	* R3 CS == CS + 16
1668	* R3 SS == CS + 24
1669	*/
1670	#define MSR_IA32_SYSENTER_CS 0x174
1671	/** SYSENTER_ESP - the R0 ESP. */
1672	#define MSR_IA32_SYSENTER_ESP 0x175
1673	/** SYSENTER_EIP - the R0 EIP. */
1674	#define MSR_IA32_SYSENTER_EIP 0x176
1675	#endif
1676
1677	/** Machine Check Global Capabilities Register. */
1678	#define MSR_IA32_MCG_CAP 0x179
1679	/** Machine Check Global Status Register. */
1680	#define MSR_IA32_MCG_STATUS 0x17A
1681	/** Machine Check Global Control Register. */
1682	#define MSR_IA32_MCG_CTRL 0x17B
1683
1684	/** Page Attribute Table. */
1685	#define MSR_IA32_CR_PAT 0x277
1686	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1687	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1688	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1689
1690	/** Memory types that can be encoded in the IA32_PAT MSR.
1691	* @{ */
1692	/** Uncacheable. */
1693	#define MSR_IA32_PAT_MT_UC 0
1694	/** Write Combining. */
1695	#define MSR_IA32_PAT_MT_WC 1
1696	/** Reserved value 2. */
1697	#define MSR_IA32_PAT_MT_RSVD_2 2
1698	/** Reserved value 3. */
1699	#define MSR_IA32_PAT_MT_RSVD_3 3
1700	/** Write-through. */
1701	#define MSR_IA32_PAT_MT_WT 4
1702	/** Write-protected. */
1703	#define MSR_IA32_PAT_MT_WP 5
1704	/** Writeback. */
1705	#define MSR_IA32_PAT_MT_WB 6
1706	/** Uncached (UC-). */
1707	#define MSR_IA32_PAT_MT_UCD 7
1708	/** @}*/
1709
1710
1711	/** Performance event select MSRs. (Intel only) */
1712	#define MSR_IA32_PERFEVTSEL0 0x186
1713	#define MSR_IA32_PERFEVTSEL1 0x187
1714	#define MSR_IA32_PERFEVTSEL2 0x188
1715	#define MSR_IA32_PERFEVTSEL3 0x189
1716
1717	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1718	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1719	* holds a ratio that Apple takes for TSC granularity.
1720	*
1721	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1722	#define MSR_FLEX_RATIO 0x194
1723	/** Performance state value and starting with Intel core more.
1724	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1725	#define MSR_IA32_PERF_STATUS 0x198
1726	#define MSR_IA32_PERF_CTL 0x199
1727	#define MSR_IA32_THERM_STATUS 0x19c
1728
1729	/** Offcore response event select registers. */
1730	#define MSR_OFFCORE_RSP_0 0x1a6
1731	#define MSR_OFFCORE_RSP_1 0x1a7
1732
1733	/** Enable misc. processor features (R/W). */
1734	#define MSR_IA32_MISC_ENABLE 0x1A0
1735	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1736	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1737	/** Automatic Thermal Control Circuit Enable (R/W). */
1738	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1739	/** Performance Monitoring Available (R). */
1740	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1741	/** Branch Trace Storage Unavailable (R/O). */
1742	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1743	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1744	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1745	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1746	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1747	/** If MONITOR/MWAIT is supported (R/W). */
1748	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1749	/** Limit CPUID Maxval to 3 leafs (R/W). */
1750	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1751	/** When set to 1, xTPR messages are disabled (R/W). */
1752	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1753	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1754	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1755
1756	/** Trace/Profile Resource Control (R/W) */
1757	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1758	/** Last branch record. */
1759	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1760	/** Branch trace flag (single step on branches). */
1761	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1762	/** Performance monitoring pin control (AMD only). */
1763	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1764	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1765	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1766	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1767	/** Trace message enable (Intel only). */
1768	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1769	/** Branch trace store (Intel only). */
1770	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1771	/** Branch trace interrupt (Intel only). */
1772	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1773	/** Branch trace off in privileged code (Intel only). */
1774	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1775	/** Branch trace off in user code (Intel only). */
1776	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1777	/** Freeze LBR on PMI flag (Intel only). */
1778	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1779	/** Freeze PERFMON on PMI flag (Intel only). */
1780	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1781	/** Freeze while SMM enabled (Intel only). */
1782	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1783	/** Advanced debugging of RTM regions (Intel only). */
1784	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1785	/** Debug control MSR valid bits (Intel only). */
1786	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1787	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1788	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1789	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1790	\| MSR_IA32_DEBUGCTL_RTM)
1791
1792	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1793	* @{ */
1794	#define MSR_P4_LASTBRANCH_0 0x1db
1795	#define MSR_P4_LASTBRANCH_1 0x1dc
1796	#define MSR_P4_LASTBRANCH_2 0x1dd
1797	#define MSR_P4_LASTBRANCH_3 0x1de
1798
1799	/** LBR Top-of-stack MSR (index to most recent record). */
1800	#define MSR_P4_LASTBRANCH_TOS 0x1da
1801	/** @} */
1802
1803	/** @name Last branch registers for Core 2 and related Xeons.
1804	* @{ */
1805	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1806	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1807	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1808	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1809
1810	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1811	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1812	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1813	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1814
1815	/** LBR Top-of-stack MSR (index to most recent record). */
1816	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1817	/** @} */
1818
1819	/** @name Last branch registers.
1820	* @{ */
1821	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1822	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1823	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1824	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1825	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1826	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1827	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1828	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1829	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1830	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1831	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1832	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1833	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1834	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1835	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1836	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1837	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1838	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1839	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1840	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1841	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1842	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1843	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1844	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1845	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1846	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1847	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1848	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1849	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1850	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1851	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1852	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1853
1854	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1855	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1856	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1857	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1858	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1859	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1860	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1861	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1862	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1863	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1864	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1865	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1866	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1867	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1868	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1869	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1870	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1871	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1872	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1873	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1874	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1875	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1876	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1877	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1878	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1879	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1880	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1881	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1882	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1883	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1884	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1885	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1886
1887	#define MSR_LASTBRANCH_0_INFO 0xdc0
1888	#define MSR_LASTBRANCH_1_INFO 0xdc1
1889	#define MSR_LASTBRANCH_2_INFO 0xdc2
1890	#define MSR_LASTBRANCH_3_INFO 0xdc3
1891	#define MSR_LASTBRANCH_4_INFO 0xdc4
1892	#define MSR_LASTBRANCH_5_INFO 0xdc5
1893	#define MSR_LASTBRANCH_6_INFO 0xdc6
1894	#define MSR_LASTBRANCH_7_INFO 0xdc7
1895	#define MSR_LASTBRANCH_8_INFO 0xdc8
1896	#define MSR_LASTBRANCH_9_INFO 0xdc9
1897	#define MSR_LASTBRANCH_10_INFO 0xdca
1898	#define MSR_LASTBRANCH_11_INFO 0xdcb
1899	#define MSR_LASTBRANCH_12_INFO 0xdcc
1900	#define MSR_LASTBRANCH_13_INFO 0xdcd
1901	#define MSR_LASTBRANCH_14_INFO 0xdce
1902	#define MSR_LASTBRANCH_15_INFO 0xdcf
1903	#define MSR_LASTBRANCH_16_INFO 0xdd0
1904	#define MSR_LASTBRANCH_17_INFO 0xdd1
1905	#define MSR_LASTBRANCH_18_INFO 0xdd2
1906	#define MSR_LASTBRANCH_19_INFO 0xdd3
1907	#define MSR_LASTBRANCH_20_INFO 0xdd4
1908	#define MSR_LASTBRANCH_21_INFO 0xdd5
1909	#define MSR_LASTBRANCH_22_INFO 0xdd6
1910	#define MSR_LASTBRANCH_23_INFO 0xdd7
1911	#define MSR_LASTBRANCH_24_INFO 0xdd8
1912	#define MSR_LASTBRANCH_25_INFO 0xdd9
1913	#define MSR_LASTBRANCH_26_INFO 0xdda
1914	#define MSR_LASTBRANCH_27_INFO 0xddb
1915	#define MSR_LASTBRANCH_28_INFO 0xddc
1916	#define MSR_LASTBRANCH_29_INFO 0xddd
1917	#define MSR_LASTBRANCH_30_INFO 0xdde
1918	#define MSR_LASTBRANCH_31_INFO 0xddf
1919
1920	/** LBR branch tracking selection MSR. */
1921	#define MSR_LASTBRANCH_SELECT 0x1c8
1922	/** LBR Top-of-stack MSR (index to most recent record). */
1923	#define MSR_LASTBRANCH_TOS 0x1c9
1924	/** @} */
1925
1926	/** @name Last event record registers.
1927	* @{ */
1928	/** Last event record source IP register. */
1929	#define MSR_LER_FROM_IP 0x1dd
1930	/** Last event record destination IP register. */
1931	#define MSR_LER_TO_IP 0x1de
1932	/** @} */
1933
1934	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1935	#define MSR_IA32_TSX_CTRL 0x122
1936
1937	/** Variable range MTRRs.
1938	* @{ */
1939	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1940	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1941	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1942	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1943	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1944	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1945	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1946	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1947	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1948	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1949	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1950	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1951	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1952	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1953	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1954	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1955	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1956	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1957	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1958	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1959	/** @} */
1960
1961	/** Fixed range MTRRs.
1962	* @{ */
1963	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1964	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1965	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1966	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1967	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1968	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1969	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1970	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1971	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1972	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1973	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1974	/** @} */
1975
1976	/** MTRR Default Type.
1977	* @{ */
1978	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1979	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1980	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1981	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1982	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1983	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1984	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1985	/** @} */
1986
1987	/** Variable-range MTRR physical mask valid. */
1988	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1989
1990	/** Variable-range MTRR memory type mask. */
1991	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1992
1993	/** Global performance counter control facilities (Intel only). */
1994	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1995	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1996	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1997
1998	/** Precise Event Based sampling (Intel only). */
1999	#define MSR_IA32_PEBS_ENABLE 0x3F1
2000
2001	#define MSR_IA32_MC0_CTL 0x400
2002	#define MSR_IA32_MC0_STATUS 0x401
2003
2004	/** Basic VMX information. */
2005	#define MSR_IA32_VMX_BASIC 0x480
2006	/** Allowed settings for pin-based VM execution controls. */
2007	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
2008	/** Allowed settings for proc-based VM execution controls. */
2009	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
2010	/** Allowed settings for the VM-exit controls. */
2011	#define MSR_IA32_VMX_EXIT_CTLS 0x483
2012	/** Allowed settings for the VM-entry controls. */
2013	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
2014	/** Misc VMX info. */
2015	#define MSR_IA32_VMX_MISC 0x485
2016	/** Fixed cleared bits in CR0. */
2017	#define MSR_IA32_VMX_CR0_FIXED0 0x486
2018	/** Fixed set bits in CR0. */
2019	#define MSR_IA32_VMX_CR0_FIXED1 0x487
2020	/** Fixed cleared bits in CR4. */
2021	#define MSR_IA32_VMX_CR4_FIXED0 0x488
2022	/** Fixed set bits in CR4. */
2023	#define MSR_IA32_VMX_CR4_FIXED1 0x489
2024	/** Information for enumerating fields in the VMCS. */
2025	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
2026	/** Allowed settings for secondary processor-based VM-execution controls. */
2027	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
2028	/** EPT capabilities. */
2029	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
2030	/** Allowed settings of all pin-based VM execution controls. */
2031	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
2032	/** Allowed settings of all proc-based VM execution controls. */
2033	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
2034	/** Allowed settings of all VMX exit controls. */
2035	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
2036	/** Allowed settings of all VMX entry controls. */
2037	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
2038	/** Allowed settings for the VM-function controls. */
2039	#define MSR_IA32_VMX_VMFUNC 0x491
2040	/** Tertiary processor-based VM execution controls. */
2041	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
2042	/** Secondary VM-exit controls. */
2043	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
2044
2045	/** Intel PT - Enable and control for trace packet generation. */
2046	#define MSR_IA32_RTIT_CTL 0x570
2047
2048	/** DS Save Area (R/W). */
2049	#define MSR_IA32_DS_AREA 0x600
2050	/** Running Average Power Limit (RAPL) power units. */
2051	#define MSR_RAPL_POWER_UNIT 0x606
2052	/** Package C3 Interrupt Response Limit. */
2053	#define MSR_PKGC3_IRTL 0x60a
2054	/** Package C6/C7S Interrupt Response Limit 1. */
2055	#define MSR_PKGC_IRTL1 0x60b
2056	/** Package C6/C7S Interrupt Response Limit 2. */
2057	#define MSR_PKGC_IRTL2 0x60c
2058	/** Package C2 Residency Counter. */
2059	#define MSR_PKG_C2_RESIDENCY 0x60d
2060	/** PKG RAPL Power Limit Control. */
2061	#define MSR_PKG_POWER_LIMIT 0x610
2062	/** PKG Energy Status. */
2063	#define MSR_PKG_ENERGY_STATUS 0x611
2064	/** PKG Perf Status. */
2065	#define MSR_PKG_PERF_STATUS 0x613
2066	/** PKG RAPL Parameters. */
2067	#define MSR_PKG_POWER_INFO 0x614
2068	/** DRAM RAPL Power Limit Control. */
2069	#define MSR_DRAM_POWER_LIMIT 0x618
2070	/** DRAM Energy Status. */
2071	#define MSR_DRAM_ENERGY_STATUS 0x619
2072	/** DRAM Performance Throttling Status. */
2073	#define MSR_DRAM_PERF_STATUS 0x61b
2074	/** DRAM RAPL Parameters. */
2075	#define MSR_DRAM_POWER_INFO 0x61c
2076	/** Package C10 Residency Counter. */
2077	#define MSR_PKG_C10_RESIDENCY 0x632
2078	/** PP0 Energy Status. */
2079	#define MSR_PP0_ENERGY_STATUS 0x639
2080	/** PP1 Energy Status. */
2081	#define MSR_PP1_ENERGY_STATUS 0x641
2082	/** Turbo Activation Ratio. */
2083	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
2084	/** Core Performance Limit Reasons. */
2085	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
2086
2087	/** Userspace Control flow Enforcement Technology setting. */
2088	#define MSR_IA32_U_CET 0x6a0
2089	/** Supervisor space Control flow Enforcement Technology setting. */
2090	#define MSR_IA32_S_CET 0x6a2
2091	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
2092	* @{ */
2093	/** Enables the Shadow stack. */
2094	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
2095	/** Enables WRSS{D,Q}W instructions. */
2096	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
2097	/** Enables indirect branch tracking. */
2098	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
2099	/** Enable legacy compatibility treatment for indirect branch tracking. */
2100	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
2101	/** Enables the use of no-track prefix for indirect branch tracking. */
2102	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
2103	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
2104	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
2105	/** Suppresses indirect branch tracking. */
2106	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2107	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2108	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2109	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2110	* on a ENDBRANCH instruction. */
2111	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2112	/** @} */
2113
2114	/** X2APIC MSR range start. */
2115	#define MSR_IA32_X2APIC_START 0x800
2116	/** X2APIC MSR - APIC ID Register. */
2117	#define MSR_IA32_X2APIC_ID 0x802
2118	/** X2APIC MSR - APIC Version Register. */
2119	#define MSR_IA32_X2APIC_VERSION 0x803
2120	/** X2APIC MSR - Task Priority Register. */
2121	#define MSR_IA32_X2APIC_TPR 0x808
2122	/** X2APIC MSR - Processor Priority register. */
2123	#define MSR_IA32_X2APIC_PPR 0x80A
2124	/** X2APIC MSR - End Of Interrupt register. */
2125	#define MSR_IA32_X2APIC_EOI 0x80B
2126	/** X2APIC MSR - Logical Destination Register. */
2127	#define MSR_IA32_X2APIC_LDR 0x80D
2128	/** X2APIC MSR - Spurious Interrupt Vector Register. */
2129	#define MSR_IA32_X2APIC_SVR 0x80F
2130	/** X2APIC MSR - In-service Register (bits 31:0). */
2131	#define MSR_IA32_X2APIC_ISR0 0x810
2132	/** X2APIC MSR - In-service Register (bits 63:32). */
2133	#define MSR_IA32_X2APIC_ISR1 0x811
2134	/** X2APIC MSR - In-service Register (bits 95:64). */
2135	#define MSR_IA32_X2APIC_ISR2 0x812
2136	/** X2APIC MSR - In-service Register (bits 127:96). */
2137	#define MSR_IA32_X2APIC_ISR3 0x813
2138	/** X2APIC MSR - In-service Register (bits 159:128). */
2139	#define MSR_IA32_X2APIC_ISR4 0x814
2140	/** X2APIC MSR - In-service Register (bits 191:160). */
2141	#define MSR_IA32_X2APIC_ISR5 0x815
2142	/** X2APIC MSR - In-service Register (bits 223:192). */
2143	#define MSR_IA32_X2APIC_ISR6 0x816
2144	/** X2APIC MSR - In-service Register (bits 255:224). */
2145	#define MSR_IA32_X2APIC_ISR7 0x817
2146	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2147	#define MSR_IA32_X2APIC_TMR0 0x818
2148	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2149	#define MSR_IA32_X2APIC_TMR1 0x819
2150	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2151	#define MSR_IA32_X2APIC_TMR2 0x81A
2152	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2153	#define MSR_IA32_X2APIC_TMR3 0x81B
2154	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2155	#define MSR_IA32_X2APIC_TMR4 0x81C
2156	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2157	#define MSR_IA32_X2APIC_TMR5 0x81D
2158	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2159	#define MSR_IA32_X2APIC_TMR6 0x81E
2160	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2161	#define MSR_IA32_X2APIC_TMR7 0x81F
2162	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2163	#define MSR_IA32_X2APIC_IRR0 0x820
2164	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2165	#define MSR_IA32_X2APIC_IRR1 0x821
2166	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2167	#define MSR_IA32_X2APIC_IRR2 0x822
2168	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2169	#define MSR_IA32_X2APIC_IRR3 0x823
2170	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2171	#define MSR_IA32_X2APIC_IRR4 0x824
2172	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2173	#define MSR_IA32_X2APIC_IRR5 0x825
2174	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2175	#define MSR_IA32_X2APIC_IRR6 0x826
2176	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2177	#define MSR_IA32_X2APIC_IRR7 0x827
2178	/** X2APIC MSR - Error Status Register. */
2179	#define MSR_IA32_X2APIC_ESR 0x828
2180	/** X2APIC MSR - LVT CMCI Register. */
2181	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2182	/** X2APIC MSR - Interrupt Command Register. */
2183	#define MSR_IA32_X2APIC_ICR 0x830
2184	/** X2APIC MSR - LVT Timer Register. */
2185	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2186	/** X2APIC MSR - LVT Thermal Sensor Register. */
2187	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2188	/** X2APIC MSR - LVT Performance Counter Register. */
2189	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2190	/** X2APIC MSR - LVT LINT0 Register. */
2191	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2192	/** X2APIC MSR - LVT LINT1 Register. */
2193	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2194	/** X2APIC MSR - LVT Error Register . */
2195	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2196	/** X2APIC MSR - Timer Initial Count Register. */
2197	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2198	/** X2APIC MSR - Timer Current Count Register. */
2199	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2200	/** X2APIC MSR - Timer Divide Configuration Register. */
2201	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2202	/** X2APIC MSR - Self IPI. */
2203	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2204	/** X2APIC MSR range end. */
2205	#define MSR_IA32_X2APIC_END 0x8FF
2206	/** X2APIC MSR - LVT start range. */
2207	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2208	/** X2APIC MSR - LVT end range (inclusive). */
2209	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2210
2211	/** K6 EFER - Extended Feature Enable Register. */
2212	#define MSR_K6_EFER UINT32_C(0xc0000080)
2213	/** @todo document EFER */
2214	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2215	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2216	/** Bit 8 - LME - Long mode enabled. (R/W) */
2217	#define MSR_K6_EFER_LME RT_BIT_32(8)
2218	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2219	/** Bit 10 - LMA - Long mode active. (R) */
2220	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2221	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2222	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2223	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2224	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2225	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2226	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2227	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2228	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2229	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2230	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2231	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2232	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2233	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2234	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2235
2236	/** K6 STAR - SYSCALL/RET targets. */
2237	#define MSR_K6_STAR UINT32_C(0xc0000081)
2238	/** Shift value for getting the SYSRET CS and SS value. */
2239	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2240	/** Shift value for getting the SYSCALL CS and SS value. */
2241	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2242	/** Selector mask for use after shifting. */
2243	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2244	/** The mask which give the SYSCALL EIP. */
2245	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2246	/** K6 WHCR - Write Handling Control Register. */
2247	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2248	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2249	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2250	/** K6 PSOR - Processor State Observability Register. */
2251	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2252	/** K6 PFIR - Page Flush/Invalidate Register. */
2253	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2254
2255	/** Performance counter MSRs. (AMD only) */
2256	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2257	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2258	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2259	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2260	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2261	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2262	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2263	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2264
2265	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2266	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2267	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2268	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2269	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2270	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2271	/** K8 FS.base - The 64-bit base FS register. */
2272	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2273	/** K8 GS.base - The 64-bit base GS register. */
2274	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2275	/** K8 KernelGSbase - Used with SWAPGS. */
2276	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2277	/** K8 TSC_AUX - Used with RDTSCP. */
2278	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2279	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2280	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2281	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2282	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2283	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2284	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2285	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2286	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2287
2288	/** SMM MSRs. */
2289	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2290	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2291	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2292
2293	/** North bridge config? See BIOS & Kernel dev guides for
2294	* details. */
2295	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2296
2297	/** Hypertransport interrupt pending register.
2298	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2299	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2300
2301	/** SVM Control. */
2302	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2303	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2304	* features. */
2305	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2306	/** If set, non-intercepted INIT signals are converted to \#SX
2307	* exceptions. */
2308	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2309	/** Disables A20 masking. */
2310	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2311	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2312	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2313	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2314	* clear, EFER.SVME can be written normally. */
2315	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2316
2317	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2318	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2319	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2320	* host state during world switch. */
2321	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2322
2323	/** Virtualized speculation control for AMD processors.
2324	*
2325	* Unified interface among different CPU generations.
2326	* The VMM will set any architectural MSRs based on the CPU.
2327	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2328	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2329	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2330	/** Speculative Store Bypass Disable. */
2331	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2332
2333	/** @} */
2334
2335
2336	/** @name Page Table / Directory / Directory Pointers / L4.
2337	* @{
2338	*/
2339
2340	#ifndef __ASSEMBLER__
2341	/** Page table/directory entry as an unsigned integer. */
2342	typedef uint32_t X86PGUINT;
2343	/** Pointer to a page table/directory table entry as an unsigned integer. */
2344	typedef X86PGUINT *PX86PGUINT;
2345	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2346	typedef X86PGUINT const *PCX86PGUINT;
2347	#endif
2348
2349	/** Number of entries in a 32-bit PT/PD. */
2350	#define X86_PG_ENTRIES 1024
2351
2352
2353	#ifndef __ASSEMBLER__
2354	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2355	typedef uint64_t X86PGPAEUINT;
2356	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2357	typedef X86PGPAEUINT *PX86PGPAEUINT;
2358	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2359	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2360	#endif
2361
2362	/** Number of entries in a PAE PT/PD. */
2363	#define X86_PG_PAE_ENTRIES 512
2364	/** Number of entries in a PAE PDPT. */
2365	#define X86_PG_PAE_PDPE_ENTRIES 4
2366
2367	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2368	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2369	/** Number of entries in an AMD64 PDPT.
2370	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2371	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2372
2373	/** The size of a default page. */
2374	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2375	/** The page shift of a default page. */
2376	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2377	/** The default page offset mask. */
2378	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2379	/** The default page base mask for virtual addresses. */
2380	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2381	/** The default page base mask for virtual addresses - 32bit version. */
2382	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2383
2384	/** The size of a 4KB page. */
2385	#define X86_PAGE_4K_SIZE _4K
2386	/** The page shift of a 4KB page. */
2387	#define X86_PAGE_4K_SHIFT 12
2388	/** The 4KB page offset mask. */
2389	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2390	/** The 4KB page base mask for virtual addresses. */
2391	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2392	/** The 4KB page base mask for virtual addresses - 32bit version. */
2393	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2394
2395	/** The size of a 2MB page. */
2396	#define X86_PAGE_2M_SIZE _2M
2397	/** The page shift of a 2MB page. */
2398	#define X86_PAGE_2M_SHIFT 21
2399	/** The 2MB page offset mask. */
2400	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2401	/** The 2MB page base mask for virtual addresses. */
2402	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2403	/** The 2MB page base mask for virtual addresses - 32bit version. */
2404	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2405
2406	/** The size of a 4MB page. */
2407	#define X86_PAGE_4M_SIZE _4M
2408	/** The page shift of a 4MB page. */
2409	#define X86_PAGE_4M_SHIFT 22
2410	/** The 4MB page offset mask. */
2411	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2412	/** The 4MB page base mask for virtual addresses. */
2413	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2414	/** The 4MB page base mask for virtual addresses - 32bit version. */
2415	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2416
2417	/** The size of a 1GB page. */
2418	#define X86_PAGE_1G_SIZE _1G
2419	/** The page shift of a 1GB page. */
2420	#define X86_PAGE_1G_SHIFT 30
2421	/** The 1GB page offset mask. */
2422	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2423	/** The 1GB page base mask for virtual addresses. */
2424	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2425
2426	/**
2427	* Check if the given address is canonical.
2428	*/
2429	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2430
2431	/**
2432	* Gets the page base mask given the page shift.
2433	*/
2434	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2435
2436	/**
2437	* Gets the page offset mask given the page shift.
2438	*/
2439	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2440
2441
2442	/** @name Page Table Entry
2443	* @{
2444	*/
2445	/** Bit 0 - P - Present bit. */
2446	#define X86_PTE_BIT_P 0
2447	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2448	#define X86_PTE_BIT_RW 1
2449	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2450	#define X86_PTE_BIT_US 2
2451	/** Bit 3 - PWT - Page level write thru bit. */
2452	#define X86_PTE_BIT_PWT 3
2453	/** Bit 4 - PCD - Page level cache disable bit. */
2454	#define X86_PTE_BIT_PCD 4
2455	/** Bit 5 - A - Access bit. */
2456	#define X86_PTE_BIT_A 5
2457	/** Bit 6 - D - Dirty bit. */
2458	#define X86_PTE_BIT_D 6
2459	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2460	#define X86_PTE_BIT_PAT 7
2461	/** Bit 8 - G - Global flag. */
2462	#define X86_PTE_BIT_G 8
2463	/** Bits 63 - NX - PAE/LM - No execution flag. */
2464	#define X86_PTE_PAE_BIT_NX 63
2465
2466	/** Bit 0 - P - Present bit mask. */
2467	#define X86_PTE_P RT_BIT_32(0)
2468	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2469	#define X86_PTE_RW RT_BIT_32(1)
2470	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2471	#define X86_PTE_US RT_BIT_32(2)
2472	/** Bit 3 - PWT - Page level write thru bit mask. */
2473	#define X86_PTE_PWT RT_BIT_32(3)
2474	/** Bit 4 - PCD - Page level cache disable bit mask. */
2475	#define X86_PTE_PCD RT_BIT_32(4)
2476	/** Bit 5 - A - Access bit mask. */
2477	#define X86_PTE_A RT_BIT_32(5)
2478	/** Bit 6 - D - Dirty bit mask. */
2479	#define X86_PTE_D RT_BIT_32(6)
2480	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2481	#define X86_PTE_PAT RT_BIT_32(7)
2482	/** Bit 8 - G - Global bit mask. */
2483	#define X86_PTE_G RT_BIT_32(8)
2484
2485	/** Bits 9-11 - - Available for use to system software. */
2486	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2487	/** Bits 12-31 - - Physical Page number of the next level. */
2488	#define X86_PTE_PG_MASK ( 0xfffff000 )
2489
2490	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2491	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2492	/** Bits 63 - NX - PAE/LM - No execution flag. */
2493	#define X86_PTE_PAE_NX RT_BIT_64(63)
2494	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2495	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2496	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2497	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2498	/** No bits - - LM - MBZ bits when NX is active. */
2499	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2500	/** Bits 63 - - LM - MBZ bits when no NX. */
2501	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2502
2503	#ifndef __ASSEMBLER__
2504
2505	/**
2506	* Page table entry.
2507	*/
2508	typedef struct X86PTEBITS
2509	{
2510	/** Flags whether(=1) or not the page is present. */
2511	uint32_t u1Present : 1;
2512	/** Read(=0) / Write(=1) flag. */
2513	uint32_t u1Write : 1;
2514	/** User(=1) / Supervisor (=0) flag. */
2515	uint32_t u1User : 1;
2516	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2517	uint32_t u1WriteThru : 1;
2518	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2519	uint32_t u1CacheDisable : 1;
2520	/** Accessed flag.
2521	* Indicates that the page have been read or written to. */
2522	uint32_t u1Accessed : 1;
2523	/** Dirty flag.
2524	* Indicates that the page has been written to. */
2525	uint32_t u1Dirty : 1;
2526	/** Reserved / If PAT enabled, bit 2 of the index. */
2527	uint32_t u1PAT : 1;
2528	/** Global flag. (Ignored in all but final level.) */
2529	uint32_t u1Global : 1;
2530	/** Available for use to system software. */
2531	uint32_t u3Available : 3;
2532	/** Physical Page number of the next level. */
2533	uint32_t u20PageNo : 20;
2534	} X86PTEBITS;
2535	# ifndef VBOX_FOR_DTRACE_LIB
2536	AssertCompileSize(X86PTEBITS, 4);
2537	# endif
2538	/** Pointer to a page table entry. */
2539	typedef X86PTEBITS *PX86PTEBITS;
2540	/** Pointer to a const page table entry. */
2541	typedef const X86PTEBITS *PCX86PTEBITS;
2542
2543	/**
2544	* Page table entry.
2545	*/
2546	typedef union X86PTE
2547	{
2548	/** Unsigned integer view */
2549	X86PGUINT u;
2550	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2551	/** Bit field view. */
2552	X86PTEBITS n;
2553	# endif
2554	/** 32-bit view. */
2555	uint32_t au32[1];
2556	/** 16-bit view. */
2557	uint16_t au16[2];
2558	/** 8-bit view. */
2559	uint8_t au8[4];
2560	} X86PTE;
2561	# ifndef VBOX_FOR_DTRACE_LIB
2562	AssertCompileSize(X86PTE, 4);
2563	# endif
2564	/** Pointer to a page table entry. */
2565	typedef X86PTE *PX86PTE;
2566	/** Pointer to a const page table entry. */
2567	typedef const X86PTE *PCX86PTE;
2568
2569
2570	/**
2571	* PAE page table entry.
2572	*/
2573	typedef struct X86PTEPAEBITS
2574	{
2575	/** Flags whether(=1) or not the page is present. */
2576	uint32_t u1Present : 1;
2577	/** Read(=0) / Write(=1) flag. */
2578	uint32_t u1Write : 1;
2579	/** User(=1) / Supervisor(=0) flag. */
2580	uint32_t u1User : 1;
2581	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2582	uint32_t u1WriteThru : 1;
2583	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2584	uint32_t u1CacheDisable : 1;
2585	/** Accessed flag.
2586	* Indicates that the page have been read or written to. */
2587	uint32_t u1Accessed : 1;
2588	/** Dirty flag.
2589	* Indicates that the page has been written to. */
2590	uint32_t u1Dirty : 1;
2591	/** Reserved / If PAT enabled, bit 2 of the index. */
2592	uint32_t u1PAT : 1;
2593	/** Global flag. (Ignored in all but final level.) */
2594	uint32_t u1Global : 1;
2595	/** Available for use to system software. */
2596	uint32_t u3Available : 3;
2597	/** Physical Page number of the next level - Low Part. Don't use this. */
2598	uint32_t u20PageNoLow : 20;
2599	/** Physical Page number of the next level - High Part. Don't use this. */
2600	uint32_t u20PageNoHigh : 20;
2601	/** MBZ bits */
2602	uint32_t u11Reserved : 11;
2603	/** No Execute flag. */
2604	uint32_t u1NoExecute : 1;
2605	} X86PTEPAEBITS;
2606	# ifndef VBOX_FOR_DTRACE_LIB
2607	AssertCompileSize(X86PTEPAEBITS, 8);
2608	# endif
2609	/** Pointer to a page table entry. */
2610	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2611	/** Pointer to a page table entry. */
2612	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2613
2614	/**
2615	* PAE Page table entry.
2616	*/
2617	typedef union X86PTEPAE
2618	{
2619	/** Unsigned integer view */
2620	X86PGPAEUINT u;
2621	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2622	/** Bit field view. */
2623	X86PTEPAEBITS n;
2624	# endif
2625	/** 32-bit view. */
2626	uint32_t au32[2];
2627	/** 16-bit view. */
2628	uint16_t au16[4];
2629	/** 8-bit view. */
2630	uint8_t au8[8];
2631	} X86PTEPAE;
2632	# ifndef VBOX_FOR_DTRACE_LIB
2633	AssertCompileSize(X86PTEPAE, 8);
2634	# endif
2635	/** Pointer to a PAE page table entry. */
2636	typedef X86PTEPAE *PX86PTEPAE;
2637	/** Pointer to a const PAE page table entry. */
2638	typedef const X86PTEPAE *PCX86PTEPAE;
2639	/** @} */
2640
2641	/**
2642	* Page table.
2643	*/
2644	typedef struct X86PT
2645	{
2646	/** PTE Array. */
2647	X86PTE a[X86_PG_ENTRIES];
2648	} X86PT;
2649	# ifndef VBOX_FOR_DTRACE_LIB
2650	AssertCompileSize(X86PT, 4096);
2651	# endif
2652	/** Pointer to a page table. */
2653	typedef X86PT *PX86PT;
2654	/** Pointer to a const page table. */
2655	typedef const X86PT *PCX86PT;
2656
2657	#endif /* !__ASSEMBLER__ */
2658
2659	/** The page shift to get the PT index. */
2660	#define X86_PT_SHIFT 12
2661	/** The PT index mask (apply to a shifted page address). */
2662	#define X86_PT_MASK 0x3ff
2663
2664
2665	#ifndef __ASSEMBLER__
2666	/**
2667	* Page directory.
2668	*/
2669	typedef struct X86PTPAE
2670	{
2671	/** PTE Array. */
2672	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2673	} X86PTPAE;
2674	# ifndef VBOX_FOR_DTRACE_LIB
2675	AssertCompileSize(X86PTPAE, 4096);
2676	# endif
2677	/** Pointer to a page table. */
2678	typedef X86PTPAE *PX86PTPAE;
2679	/** Pointer to a const page table. */
2680	typedef const X86PTPAE *PCX86PTPAE;
2681	#endif /* !__ASSEMBLER__ */
2682
2683	/** The page shift to get the PA PTE index. */
2684	#define X86_PT_PAE_SHIFT 12
2685	/** The PAE PT index mask (apply to a shifted page address). */
2686	#define X86_PT_PAE_MASK 0x1ff
2687
2688
2689	/** @name 4KB Page Directory Entry
2690	* @{
2691	*/
2692	/** Bit 0 - P - Present bit. */
2693	#define X86_PDE_P RT_BIT_32(0)
2694	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2695	#define X86_PDE_RW RT_BIT_32(1)
2696	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2697	#define X86_PDE_US RT_BIT_32(2)
2698	/** Bit 3 - PWT - Page level write thru bit. */
2699	#define X86_PDE_PWT RT_BIT_32(3)
2700	/** Bit 4 - PCD - Page level cache disable bit. */
2701	#define X86_PDE_PCD RT_BIT_32(4)
2702	/** Bit 5 - A - Access bit. */
2703	#define X86_PDE_A RT_BIT_32(5)
2704	/** Bit 7 - PS - Page size attribute.
2705	* Clear mean 4KB pages, set means large pages (2/4MB). */
2706	#define X86_PDE_PS RT_BIT_32(7)
2707	/** Bits 9-11 - - Available for use to system software. */
2708	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2709	/** Bits 12-31 - - Physical Page number of the next level. */
2710	#define X86_PDE_PG_MASK ( 0xfffff000 )
2711
2712	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2713	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2714	/** Bits 63 - NX - PAE/LM - No execution flag. */
2715	#define X86_PDE_PAE_NX RT_BIT_64(63)
2716	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2717	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2718	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2719	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2720	/** Bit 7 - - LM - MBZ bits when NX is active. */
2721	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2722	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2723	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2724
2725	#ifndef __ASSEMBLER__
2726
2727	/**
2728	* Page directory entry.
2729	*/
2730	typedef struct X86PDEBITS
2731	{
2732	/** Flags whether(=1) or not the page is present. */
2733	uint32_t u1Present : 1;
2734	/** Read(=0) / Write(=1) flag. */
2735	uint32_t u1Write : 1;
2736	/** User(=1) / Supervisor (=0) flag. */
2737	uint32_t u1User : 1;
2738	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2739	uint32_t u1WriteThru : 1;
2740	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2741	uint32_t u1CacheDisable : 1;
2742	/** Accessed flag.
2743	* Indicates that the page has been read or written to. */
2744	uint32_t u1Accessed : 1;
2745	/** Reserved / Ignored (dirty bit). */
2746	uint32_t u1Reserved0 : 1;
2747	/** Size bit if PSE is enabled - in any event it's 0. */
2748	uint32_t u1Size : 1;
2749	/** Reserved / Ignored (global bit). */
2750	uint32_t u1Reserved1 : 1;
2751	/** Available for use to system software. */
2752	uint32_t u3Available : 3;
2753	/** Physical Page number of the next level. */
2754	uint32_t u20PageNo : 20;
2755	} X86PDEBITS;
2756	# ifndef VBOX_FOR_DTRACE_LIB
2757	AssertCompileSize(X86PDEBITS, 4);
2758	# endif
2759	/** Pointer to a page directory entry. */
2760	typedef X86PDEBITS *PX86PDEBITS;
2761	/** Pointer to a const page directory entry. */
2762	typedef const X86PDEBITS *PCX86PDEBITS;
2763
2764
2765	/**
2766	* PAE page directory entry.
2767	*/
2768	typedef struct X86PDEPAEBITS
2769	{
2770	/** Flags whether(=1) or not the page is present. */
2771	uint32_t u1Present : 1;
2772	/** Read(=0) / Write(=1) flag. */
2773	uint32_t u1Write : 1;
2774	/** User(=1) / Supervisor (=0) flag. */
2775	uint32_t u1User : 1;
2776	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2777	uint32_t u1WriteThru : 1;
2778	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2779	uint32_t u1CacheDisable : 1;
2780	/** Accessed flag.
2781	* Indicates that the page has been read or written to. */
2782	uint32_t u1Accessed : 1;
2783	/** Reserved / Ignored (dirty bit). */
2784	uint32_t u1Reserved0 : 1;
2785	/** Size bit if PSE is enabled - in any event it's 0. */
2786	uint32_t u1Size : 1;
2787	/** Reserved / Ignored (global bit). / */
2788	uint32_t u1Reserved1 : 1;
2789	/** Available for use to system software. */
2790	uint32_t u3Available : 3;
2791	/** Physical Page number of the next level - Low Part. Don't use! */
2792	uint32_t u20PageNoLow : 20;
2793	/** Physical Page number of the next level - High Part. Don't use! */
2794	uint32_t u20PageNoHigh : 20;
2795	/** MBZ bits */
2796	uint32_t u11Reserved : 11;
2797	/** No Execute flag. */
2798	uint32_t u1NoExecute : 1;
2799	} X86PDEPAEBITS;
2800	# ifndef VBOX_FOR_DTRACE_LIB
2801	AssertCompileSize(X86PDEPAEBITS, 8);
2802	# endif
2803	/** Pointer to a page directory entry. */
2804	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2805	/** Pointer to a const page directory entry. */
2806	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2807
2808	#endif /* !__ASSEMBLER__ */
2809
2810	/** @} */
2811
2812
2813	/** @name 2/4MB Page Directory Entry
2814	* @{
2815	*/
2816	/** Bit 0 - P - Present bit. */
2817	#define X86_PDE4M_P RT_BIT_32(0)
2818	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2819	#define X86_PDE4M_RW RT_BIT_32(1)
2820	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2821	#define X86_PDE4M_US RT_BIT_32(2)
2822	/** Bit 3 - PWT - Page level write thru bit. */
2823	#define X86_PDE4M_PWT RT_BIT_32(3)
2824	/** Bit 4 - PCD - Page level cache disable bit. */
2825	#define X86_PDE4M_PCD RT_BIT_32(4)
2826	/** Bit 5 - A - Access bit. */
2827	#define X86_PDE4M_A RT_BIT_32(5)
2828	/** Bit 6 - D - Dirty bit. */
2829	#define X86_PDE4M_D RT_BIT_32(6)
2830	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2831	#define X86_PDE4M_PS RT_BIT_32(7)
2832	/** Bit 8 - G - Global flag. */
2833	#define X86_PDE4M_G RT_BIT_32(8)
2834	/** Bits 9-11 - AVL - Available for use to system software. */
2835	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2836	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2837	#define X86_PDE4M_PAT RT_BIT_32(12)
2838	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2839	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2840	/** Bits 22-31 - - Physical Page number. */
2841	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2842	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2843	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2844	/** The number of bits to the high part of the page number. */
2845	#define X86_PDE4M_PG_HIGH_SHIFT 19
2846	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2847	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2848
2849	/** Bits 21-51 - - PAE/LM - Physical Page number.
2850	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2851	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2852	/** Bits 63 - NX - PAE/LM - No execution flag. */
2853	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2854	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2855	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2856	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2857	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2858	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2859	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2860	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2861	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2862
2863	#ifndef __ASSEMBLER__
2864
2865	/**
2866	* 4MB page directory entry.
2867	*/
2868	typedef struct X86PDE4MBITS
2869	{
2870	/** Flags whether(=1) or not the page is present. */
2871	uint32_t u1Present : 1;
2872	/** Read(=0) / Write(=1) flag. */
2873	uint32_t u1Write : 1;
2874	/** User(=1) / Supervisor (=0) flag. */
2875	uint32_t u1User : 1;
2876	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2877	uint32_t u1WriteThru : 1;
2878	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2879	uint32_t u1CacheDisable : 1;
2880	/** Accessed flag.
2881	* Indicates that the page have been read or written to. */
2882	uint32_t u1Accessed : 1;
2883	/** Dirty flag.
2884	* Indicates that the page has been written to. */
2885	uint32_t u1Dirty : 1;
2886	/** Page size flag - always 1 for 4MB entries. */
2887	uint32_t u1Size : 1;
2888	/** Global flag. */
2889	uint32_t u1Global : 1;
2890	/** Available for use to system software. */
2891	uint32_t u3Available : 3;
2892	/** Reserved / If PAT enabled, bit 2 of the index. */
2893	uint32_t u1PAT : 1;
2894	/** Bits 32-39 of the page number on AMD64.
2895	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2896	uint32_t u8PageNoHigh : 8;
2897	/** Reserved. */
2898	uint32_t u1Reserved : 1;
2899	/** Physical Page number of the page. */
2900	uint32_t u10PageNo : 10;
2901	} X86PDE4MBITS;
2902	# ifndef VBOX_FOR_DTRACE_LIB
2903	AssertCompileSize(X86PDE4MBITS, 4);
2904	# endif
2905	/** Pointer to a page table entry. */
2906	typedef X86PDE4MBITS *PX86PDE4MBITS;
2907	/** Pointer to a const page table entry. */
2908	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2909
2910
2911	/**
2912	* 2MB PAE page directory entry.
2913	*/
2914	typedef struct X86PDE2MPAEBITS
2915	{
2916	/** Flags whether(=1) or not the page is present. */
2917	uint32_t u1Present : 1;
2918	/** Read(=0) / Write(=1) flag. */
2919	uint32_t u1Write : 1;
2920	/** User(=1) / Supervisor(=0) flag. */
2921	uint32_t u1User : 1;
2922	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2923	uint32_t u1WriteThru : 1;
2924	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2925	uint32_t u1CacheDisable : 1;
2926	/** Accessed flag.
2927	* Indicates that the page have been read or written to. */
2928	uint32_t u1Accessed : 1;
2929	/** Dirty flag.
2930	* Indicates that the page has been written to. */
2931	uint32_t u1Dirty : 1;
2932	/** Page size flag - always 1 for 2MB entries. */
2933	uint32_t u1Size : 1;
2934	/** Global flag. */
2935	uint32_t u1Global : 1;
2936	/** Available for use to system software. */
2937	uint32_t u3Available : 3;
2938	/** Reserved / If PAT enabled, bit 2 of the index. */
2939	uint32_t u1PAT : 1;
2940	/** Reserved. */
2941	uint32_t u9Reserved : 9;
2942	/** Physical Page number of the next level - Low part. Don't use! */
2943	uint32_t u10PageNoLow : 10;
2944	/** Physical Page number of the next level - High part. Don't use! */
2945	uint32_t u20PageNoHigh : 20;
2946	/** MBZ bits */
2947	uint32_t u11Reserved : 11;
2948	/** No Execute flag. */
2949	uint32_t u1NoExecute : 1;
2950	} X86PDE2MPAEBITS;
2951	# ifndef VBOX_FOR_DTRACE_LIB
2952	AssertCompileSize(X86PDE2MPAEBITS, 8);
2953	# endif
2954	/** Pointer to a 2MB PAE page table entry. */
2955	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2956	/** Pointer to a 2MB PAE page table entry. */
2957	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2958
2959	#endif /* !__ASSEMBLER__ */
2960
2961	/** @} */
2962
2963	#ifndef __ASSEMBLER__
2964
2965	/**
2966	* Page directory entry.
2967	*/
2968	typedef union X86PDE
2969	{
2970	/** Unsigned integer view. */
2971	X86PGUINT u;
2972	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2973	/** Normal view. */
2974	X86PDEBITS n;
2975	/** 4MB view (big). */
2976	X86PDE4MBITS b;
2977	# endif
2978	/** 8 bit unsigned integer view. */
2979	uint8_t au8[4];
2980	/** 16 bit unsigned integer view. */
2981	uint16_t au16[2];
2982	/** 32 bit unsigned integer view. */
2983	uint32_t au32[1];
2984	} X86PDE;
2985	# ifndef VBOX_FOR_DTRACE_LIB
2986	AssertCompileSize(X86PDE, 4);
2987	# endif
2988	/** Pointer to a page directory entry. */
2989	typedef X86PDE *PX86PDE;
2990	/** Pointer to a const page directory entry. */
2991	typedef const X86PDE *PCX86PDE;
2992
2993	/**
2994	* PAE page directory entry.
2995	*/
2996	typedef union X86PDEPAE
2997	{
2998	/** Unsigned integer view. */
2999	X86PGPAEUINT u;
3000	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3001	/** Normal view. */
3002	X86PDEPAEBITS n;
3003	/** 2MB page view (big). */
3004	X86PDE2MPAEBITS b;
3005	# endif
3006	/** 8 bit unsigned integer view. */
3007	uint8_t au8[8];
3008	/** 16 bit unsigned integer view. */
3009	uint16_t au16[4];
3010	/** 32 bit unsigned integer view. */
3011	uint32_t au32[2];
3012	} X86PDEPAE;
3013	# ifndef VBOX_FOR_DTRACE_LIB
3014	AssertCompileSize(X86PDEPAE, 8);
3015	# endif
3016	/** Pointer to a page directory entry. */
3017	typedef X86PDEPAE *PX86PDEPAE;
3018	/** Pointer to a const page directory entry. */
3019	typedef const X86PDEPAE *PCX86PDEPAE;
3020
3021	/**
3022	* Page directory.
3023	*/
3024	typedef struct X86PD
3025	{
3026	/** PDE Array. */
3027	X86PDE a[X86_PG_ENTRIES];
3028	} X86PD;
3029	# ifndef VBOX_FOR_DTRACE_LIB
3030	AssertCompileSize(X86PD, 4096);
3031	# endif
3032	/** Pointer to a page directory. */
3033	typedef X86PD *PX86PD;
3034	/** Pointer to a const page directory. */
3035	typedef const X86PD *PCX86PD;
3036
3037	#endif /* !__ASSEMBLER__ */
3038
3039	/** The page shift to get the PD index. */
3040	#define X86_PD_SHIFT 22
3041	/** The PD index mask (apply to a shifted page address). */
3042	#define X86_PD_MASK 0x3ff
3043
3044
3045	#ifndef __ASSEMBLER__
3046	/**
3047	* PAE page directory.
3048	*/
3049	typedef struct X86PDPAE
3050	{
3051	/** PDE Array. */
3052	X86PDEPAE a[X86_PG_PAE_ENTRIES];
3053	} X86PDPAE;
3054	# ifndef VBOX_FOR_DTRACE_LIB
3055	AssertCompileSize(X86PDPAE, 4096);
3056	# endif
3057	/** Pointer to a PAE page directory. */
3058	typedef X86PDPAE *PX86PDPAE;
3059	/** Pointer to a const PAE page directory. */
3060	typedef const X86PDPAE *PCX86PDPAE;
3061	#endif /* !__ASSEMBLER__ */
3062
3063	/** The page shift to get the PAE PD index. */
3064	#define X86_PD_PAE_SHIFT 21
3065	/** The PAE PD index mask (apply to a shifted page address). */
3066	#define X86_PD_PAE_MASK 0x1ff
3067
3068
3069	/** @name Page Directory Pointer Table Entry (PAE)
3070	* @{
3071	*/
3072	/** Bit 0 - P - Present bit. */
3073	#define X86_PDPE_P RT_BIT_32(0)
3074	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
3075	#define X86_PDPE_RW RT_BIT_32(1)
3076	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
3077	#define X86_PDPE_US RT_BIT_32(2)
3078	/** Bit 3 - PWT - Page level write thru bit. */
3079	#define X86_PDPE_PWT RT_BIT_32(3)
3080	/** Bit 4 - PCD - Page level cache disable bit. */
3081	#define X86_PDPE_PCD RT_BIT_32(4)
3082	/** Bit 5 - A - Access bit. Long Mode only. */
3083	#define X86_PDPE_A RT_BIT_32(5)
3084	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
3085	#define X86_PDPE_LM_PS RT_BIT_32(7)
3086	/** Bits 9-11 - - Available for use to system software. */
3087	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3088	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3089	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
3090	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
3091	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
3092	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
3093	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
3094	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
3095	#define X86_PDPE_LM_NX RT_BIT_64(63)
3096	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
3097	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
3098	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
3099	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
3100	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
3101	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
3102	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
3103	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
3104
3105	#ifndef __ASSEMBLER__
3106
3107	/**
3108	* Page directory pointer table entry.
3109	*/
3110	typedef struct X86PDPEBITS
3111	{
3112	/** Flags whether(=1) or not the page is present. */
3113	uint32_t u1Present : 1;
3114	/** Chunk of reserved bits. */
3115	uint32_t u2Reserved : 2;
3116	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3117	uint32_t u1WriteThru : 1;
3118	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3119	uint32_t u1CacheDisable : 1;
3120	/** Chunk of reserved bits. */
3121	uint32_t u4Reserved : 4;
3122	/** Available for use to system software. */
3123	uint32_t u3Available : 3;
3124	/** Physical Page number of the next level - Low Part. Don't use! */
3125	uint32_t u20PageNoLow : 20;
3126	/** Physical Page number of the next level - High Part. Don't use! */
3127	uint32_t u20PageNoHigh : 20;
3128	/** MBZ bits */
3129	uint32_t u12Reserved : 12;
3130	} X86PDPEBITS;
3131	# ifndef VBOX_FOR_DTRACE_LIB
3132	AssertCompileSize(X86PDPEBITS, 8);
3133	# endif
3134	/** Pointer to a page directory pointer table entry. */
3135	typedef X86PDPEBITS *PX86PTPEBITS;
3136	/** Pointer to a const page directory pointer table entry. */
3137	typedef const X86PDPEBITS *PCX86PTPEBITS;
3138
3139	/**
3140	* Page directory pointer table entry. AMD64 version
3141	*/
3142	typedef struct X86PDPEAMD64BITS
3143	{
3144	/** Flags whether(=1) or not the page is present. */
3145	uint32_t u1Present : 1;
3146	/** Read(=0) / Write(=1) flag. */
3147	uint32_t u1Write : 1;
3148	/** User(=1) / Supervisor (=0) flag. */
3149	uint32_t u1User : 1;
3150	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3151	uint32_t u1WriteThru : 1;
3152	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3153	uint32_t u1CacheDisable : 1;
3154	/** Accessed flag.
3155	* Indicates that the page have been read or written to. */
3156	uint32_t u1Accessed : 1;
3157	/** Chunk of reserved bits. */
3158	uint32_t u3Reserved : 3;
3159	/** Available for use to system software. */
3160	uint32_t u3Available : 3;
3161	/** Physical Page number of the next level - Low Part. Don't use! */
3162	uint32_t u20PageNoLow : 20;
3163	/** Physical Page number of the next level - High Part. Don't use! */
3164	uint32_t u20PageNoHigh : 20;
3165	/** MBZ bits */
3166	uint32_t u11Reserved : 11;
3167	/** No Execute flag. */
3168	uint32_t u1NoExecute : 1;
3169	} X86PDPEAMD64BITS;
3170	# ifndef VBOX_FOR_DTRACE_LIB
3171	AssertCompileSize(X86PDPEAMD64BITS, 8);
3172	# endif
3173	/** Pointer to a page directory pointer table entry. */
3174	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3175	/** Pointer to a const page directory pointer table entry. */
3176	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3177
3178	/**
3179	* Page directory pointer table entry for 1GB page. (AMD64 only)
3180	*/
3181	typedef struct X86PDPE1GB
3182	{
3183	/** 0: Flags whether(=1) or not the page is present. */
3184	uint32_t u1Present : 1;
3185	/** 1: Read(=0) / Write(=1) flag. */
3186	uint32_t u1Write : 1;
3187	/** 2: User(=1) / Supervisor (=0) flag. */
3188	uint32_t u1User : 1;
3189	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3190	uint32_t u1WriteThru : 1;
3191	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3192	uint32_t u1CacheDisable : 1;
3193	/** 5: Accessed flag.
3194	* Indicates that the page have been read or written to. */
3195	uint32_t u1Accessed : 1;
3196	/** 6: Dirty flag for 1GB pages. */
3197	uint32_t u1Dirty : 1;
3198	/** 7: Indicates 1GB page if set. */
3199	uint32_t u1Size : 1;
3200	/** 8: Global 1GB page. */
3201	uint32_t u1Global: 1;
3202	/** 9-11: Available for use to system software. */
3203	uint32_t u3Available : 3;
3204	/** 12: PAT bit for 1GB page. */
3205	uint32_t u1PAT : 1;
3206	/** 13-29: MBZ bits. */
3207	uint32_t u17Reserved : 17;
3208	/** 30-31: Physical page number - Low Part. Don't use! */
3209	uint32_t u2PageNoLow : 2;
3210	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3211	uint32_t u20PageNoHigh : 20;
3212	/** 52-62: MBZ bits */
3213	uint32_t u11Reserved : 11;
3214	/** 63: No Execute flag. */
3215	uint32_t u1NoExecute : 1;
3216	} X86PDPE1GB;
3217	# ifndef VBOX_FOR_DTRACE_LIB
3218	AssertCompileSize(X86PDPE1GB, 8);
3219	# endif
3220	/** Pointer to a page directory pointer table entry for a 1GB page. */
3221	typedef X86PDPE1GB *PX86PDPE1GB;
3222	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3223	typedef const X86PDPE1GB *PCX86PDPE1GB;
3224
3225	/**
3226	* Page directory pointer table entry.
3227	*/
3228	typedef union X86PDPE
3229	{
3230	/** Unsigned integer view. */
3231	X86PGPAEUINT u;
3232	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3233	/** Normal view. */
3234	X86PDPEBITS n;
3235	/** AMD64 view. */
3236	X86PDPEAMD64BITS lm;
3237	/** AMD64 big view. */
3238	X86PDPE1GB b;
3239	# endif
3240	/** 8 bit unsigned integer view. */
3241	uint8_t au8[8];
3242	/** 16 bit unsigned integer view. */
3243	uint16_t au16[4];
3244	/** 32 bit unsigned integer view. */
3245	uint32_t au32[2];
3246	} X86PDPE;
3247	# ifndef VBOX_FOR_DTRACE_LIB
3248	AssertCompileSize(X86PDPE, 8);
3249	# endif
3250	/** Pointer to a page directory pointer table entry. */
3251	typedef X86PDPE *PX86PDPE;
3252	/** Pointer to a const page directory pointer table entry. */
3253	typedef const X86PDPE *PCX86PDPE;
3254
3255
3256	/**
3257	* Page directory pointer table.
3258	*/
3259	typedef struct X86PDPT
3260	{
3261	/** PDE Array. */
3262	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3263	} X86PDPT;
3264	# ifndef VBOX_FOR_DTRACE_LIB
3265	AssertCompileSize(X86PDPT, 4096);
3266	# endif
3267	/** Pointer to a page directory pointer table. */
3268	typedef X86PDPT *PX86PDPT;
3269	/** Pointer to a const page directory pointer table. */
3270	typedef const X86PDPT *PCX86PDPT;
3271
3272	#endif /* !__ASSEMBLER__ */
3273
3274	/** The page shift to get the PDPT index. */
3275	#define X86_PDPT_SHIFT 30
3276	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3277	#define X86_PDPT_MASK_PAE 0x3
3278	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3279	#define X86_PDPT_MASK_AMD64 0x1ff
3280
3281	/** @} */
3282
3283
3284	/** @name Page Map Level-4 Entry (Long Mode PAE)
3285	* @{
3286	*/
3287	/** Bit 0 - P - Present bit. */
3288	#define X86_PML4E_P RT_BIT_32(0)
3289	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3290	#define X86_PML4E_RW RT_BIT_32(1)
3291	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3292	#define X86_PML4E_US RT_BIT_32(2)
3293	/** Bit 3 - PWT - Page level write thru bit. */
3294	#define X86_PML4E_PWT RT_BIT_32(3)
3295	/** Bit 4 - PCD - Page level cache disable bit. */
3296	#define X86_PML4E_PCD RT_BIT_32(4)
3297	/** Bit 5 - A - Access bit. */
3298	#define X86_PML4E_A RT_BIT_32(5)
3299	/** Bits 9-11 - - Available for use to system software. */
3300	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3301	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3302	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3303	/** Bits 8, 7 - - MBZ bits when NX is active. */
3304	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3305	/** Bits 63, 7 - - MBZ bits when no NX. */
3306	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3307	/** Bits 63 - NX - PAE - No execution flag. */
3308	#define X86_PML4E_NX RT_BIT_64(63)
3309
3310	#ifndef __ASSEMBLER__
3311
3312	/**
3313	* Page Map Level-4 Entry
3314	*/
3315	typedef struct X86PML4EBITS
3316	{
3317	/** Flags whether(=1) or not the page is present. */
3318	uint32_t u1Present : 1;
3319	/** Read(=0) / Write(=1) flag. */
3320	uint32_t u1Write : 1;
3321	/** User(=1) / Supervisor (=0) flag. */
3322	uint32_t u1User : 1;
3323	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3324	uint32_t u1WriteThru : 1;
3325	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3326	uint32_t u1CacheDisable : 1;
3327	/** Accessed flag.
3328	* Indicates that the page have been read or written to. */
3329	uint32_t u1Accessed : 1;
3330	/** Chunk of reserved bits. */
3331	uint32_t u3Reserved : 3;
3332	/** Available for use to system software. */
3333	uint32_t u3Available : 3;
3334	/** Physical Page number of the next level - Low Part. Don't use! */
3335	uint32_t u20PageNoLow : 20;
3336	/** Physical Page number of the next level - High Part. Don't use! */
3337	uint32_t u20PageNoHigh : 20;
3338	/** MBZ bits */
3339	uint32_t u11Reserved : 11;
3340	/** No Execute flag. */
3341	uint32_t u1NoExecute : 1;
3342	} X86PML4EBITS;
3343	# ifndef VBOX_FOR_DTRACE_LIB
3344	AssertCompileSize(X86PML4EBITS, 8);
3345	# endif
3346	/** Pointer to a page map level-4 entry. */
3347	typedef X86PML4EBITS *PX86PML4EBITS;
3348	/** Pointer to a const page map level-4 entry. */
3349	typedef const X86PML4EBITS *PCX86PML4EBITS;
3350
3351	/**
3352	* Page Map Level-4 Entry.
3353	*/
3354	typedef union X86PML4E
3355	{
3356	/** Unsigned integer view. */
3357	X86PGPAEUINT u;
3358	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3359	/** Normal view. */
3360	X86PML4EBITS n;
3361	# endif
3362	/** 8 bit unsigned integer view. */
3363	uint8_t au8[8];
3364	/** 16 bit unsigned integer view. */
3365	uint16_t au16[4];
3366	/** 32 bit unsigned integer view. */
3367	uint32_t au32[2];
3368	} X86PML4E;
3369	# ifndef VBOX_FOR_DTRACE_LIB
3370	AssertCompileSize(X86PML4E, 8);
3371	# endif
3372	/** Pointer to a page map level-4 entry. */
3373	typedef X86PML4E *PX86PML4E;
3374	/** Pointer to a const page map level-4 entry. */
3375	typedef const X86PML4E *PCX86PML4E;
3376
3377
3378	/**
3379	* Page Map Level-4.
3380	*/
3381	typedef struct X86PML4
3382	{
3383	/** PDE Array. */
3384	X86PML4E a[X86_PG_PAE_ENTRIES];
3385	} X86PML4;
3386	# ifndef VBOX_FOR_DTRACE_LIB
3387	AssertCompileSize(X86PML4, 4096);
3388	# endif
3389	/** Pointer to a page map level-4. */
3390	typedef X86PML4 *PX86PML4;
3391	/** Pointer to a const page map level-4. */
3392	typedef const X86PML4 *PCX86PML4;
3393
3394	#endif /* !__ASSEMBLER__ */
3395
3396	/** The page shift to get the PML4 index. */
3397	#define X86_PML4_SHIFT 39
3398	/** The PML4 index mask (apply to a shifted page address). */
3399	#define X86_PML4_MASK 0x1ff
3400
3401	/** @} */
3402
3403	/** @} */
3404
3405	/**
3406	* Intel PCID invalidation types.
3407	*/
3408	/** Individual address invalidation. */
3409	#define X86_INVPCID_TYPE_INDV_ADDR 0
3410	/** Single-context invalidation. */
3411	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3412	/** All-context including globals invalidation. */
3413	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3414	/** All-context excluding globals invalidation. */
3415	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3416	/** The maximum valid invalidation type value. */
3417	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3418
3419
3420	/** @name Special FPU integer values.
3421	* @{ */
3422	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3423	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3424	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3425	/** @} */
3426
3427	#ifndef __ASSEMBLER__
3428
3429	/**
3430	* 32-bit protected mode FSTENV image.
3431	*/
3432	typedef struct X86FSTENV32P
3433	{
3434	uint16_t FCW; /*< 0x00 /
3435	uint16_t padding1; /*< 0x02 /
3436	uint16_t FSW; /*< 0x04 /
3437	uint16_t padding2; /*< 0x06 /
3438	uint16_t FTW; /*< 0x08 /
3439	uint16_t padding3; /*< 0x0a /
3440	uint32_t FPUIP; /*< 0x0c /
3441	uint16_t FPUCS; /*< 0x10 /
3442	uint16_t FOP; /*< 0x12 /
3443	uint32_t FPUDP; /*< 0x14 /
3444	uint16_t FPUDS; /*< 0x18 /
3445	uint16_t padding4; /*< 0x1a /
3446	} X86FSTENV32P;
3447	# ifndef VBOX_FOR_DTRACE_LIB
3448	AssertCompileSize(X86FSTENV32P, 0x1c);
3449	# endif
3450	/** Pointer to a 32-bit protected mode FSTENV image. */
3451	typedef X86FSTENV32P *PX86FSTENV32P;
3452	/** Pointer to a const 32-bit protected mode FSTENV image. */
3453	typedef X86FSTENV32P const *PCX86FSTENV32P;
3454
3455
3456	/**
3457	* 80-bit MMX/FPU register type.
3458	*/
3459	typedef struct X86FPUMMX
3460	{
3461	uint8_t reg[10];
3462	} X86FPUMMX;
3463	# ifndef VBOX_FOR_DTRACE_LIB
3464	AssertCompileSize(X86FPUMMX, 10);
3465	# endif
3466	/** Pointer to a 80-bit MMX/FPU register type. */
3467	typedef X86FPUMMX *PX86FPUMMX;
3468	/** Pointer to a const 80-bit MMX/FPU register type. */
3469	typedef const X86FPUMMX *PCX86FPUMMX;
3470
3471	/** FPU (x87) register. */
3472	typedef union X86FPUREG
3473	{
3474	/** MMX view. */
3475	uint64_t mmx;
3476	/** FPU view - todo. */
3477	X86FPUMMX fpu;
3478	/** Extended precision floating point view. */
3479	RTFLOAT80U r80;
3480	/** Extended precision floating point view v2 */
3481	RTFLOAT80U2 r80Ex;
3482	/** 8-bit view. */
3483	uint8_t au8[16];
3484	/** 16-bit view. */
3485	uint16_t au16[8];
3486	/** 32-bit view. */
3487	uint32_t au32[4];
3488	/** 64-bit view. */
3489	uint64_t au64[2];
3490	/** 128-bit view. (yeah, very helpful) */
3491	uint128_t au128[1];
3492	} X86FPUREG;
3493	# ifndef VBOX_FOR_DTRACE_LIB
3494	AssertCompileSize(X86FPUREG, 16);
3495	# endif
3496	/** Pointer to a FPU register. */
3497	typedef X86FPUREG *PX86FPUREG;
3498	/** Pointer to a const FPU register. */
3499	typedef X86FPUREG const *PCX86FPUREG;
3500
3501	/** FPU (x87) register - v2 with correct size. */
3502	# pragma pack(1)
3503	typedef union X86FPUREG2
3504	{
3505	/** MMX view. */
3506	uint64_t mmx;
3507	/** FPU view - todo. */
3508	X86FPUMMX fpu;
3509	/** Extended precision floating point view. */
3510	RTFLOAT80U r80;
3511	/** 8-bit view. */
3512	uint8_t au8[10];
3513	/** 16-bit view. */
3514	uint16_t au16[5];
3515	/** 32-bit view. */
3516	uint32_t au32[2];
3517	/** 64-bit view. */
3518	uint64_t au64[1];
3519	} X86FPUREG2;
3520	# pragma pack()
3521	# ifndef VBOX_FOR_DTRACE_LIB
3522	AssertCompileSize(X86FPUREG2, 10);
3523	# endif
3524	/** Pointer to a FPU register - v2. */
3525	typedef X86FPUREG2 *PX86FPUREG2;
3526	/** Pointer to a const FPU register - v2. */
3527	typedef X86FPUREG2 const *PCX86FPUREG2;
3528
3529	/**
3530	* XMM register union.
3531	*/
3532	typedef union X86XMMREG
3533	{
3534	/** XMM Register view. */
3535	uint128_t xmm;
3536	/** 8-bit view. */
3537	uint8_t au8[16];
3538	/** 16-bit view. */
3539	uint16_t au16[8];
3540	/** 32-bit view. */
3541	uint32_t au32[4];
3542	/** 64-bit view. */
3543	uint64_t au64[2];
3544	/** Signed 8-bit view. */
3545	int8_t ai8[16];
3546	/** Signed 16-bit view. */
3547	int16_t ai16[8];
3548	/** Signed 32-bit view. */
3549	int32_t ai32[4];
3550	/** Signed 64-bit view. */
3551	int64_t ai64[2];
3552	/** 128-bit view. (yeah, very helpful) */
3553	uint128_t au128[1];
3554	/** Single precision floating point view. */
3555	RTFLOAT32U ar32[4];
3556	/** Double precision floating point view. */
3557	RTFLOAT64U ar64[2];
3558	# ifndef VBOX_FOR_DTRACE_LIB
3559	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3560	RTUINT128U uXmm;
3561	# endif
3562	} X86XMMREG;
3563	# ifndef VBOX_FOR_DTRACE_LIB
3564	AssertCompileSize(X86XMMREG, 16);
3565	# endif
3566	/** Pointer to an XMM register state. */
3567	typedef X86XMMREG *PX86XMMREG;
3568	/** Pointer to a const XMM register state. */
3569	typedef X86XMMREG const *PCX86XMMREG;
3570
3571	/**
3572	* YMM register union.
3573	*/
3574	typedef union X86YMMREG
3575	{
3576	/** YMM register view. */
3577	RTUINT256U ymm;
3578	/** 8-bit view. */
3579	uint8_t au8[32];
3580	/** 16-bit view. */
3581	uint16_t au16[16];
3582	/** 32-bit view. */
3583	uint32_t au32[8];
3584	/** 64-bit view. */
3585	uint64_t au64[4];
3586	/** Signed 8-bit view. */
3587	int8_t ai8[32];
3588	/** Signed 16-bit view. */
3589	int16_t ai16[16];
3590	/** Signed 32-bit view. */
3591	int32_t ai32[8];
3592	/** Signed 64-bit view. */
3593	int64_t ai64[4];
3594	/** 128-bit view. (yeah, very helpful) */
3595	uint128_t au128[2];
3596	/** Single precision floating point view. */
3597	RTFLOAT32U ar32[8];
3598	/** Double precision floating point view. */
3599	RTFLOAT64U ar64[4];
3600	/** XMM sub register view. */
3601	X86XMMREG aXmm[2];
3602	} X86YMMREG;
3603	# ifndef VBOX_FOR_DTRACE_LIB
3604	AssertCompileSize(X86YMMREG, 32);
3605	# endif
3606	/** Pointer to an YMM register state. */
3607	typedef X86YMMREG *PX86YMMREG;
3608	/** Pointer to a const YMM register state. */
3609	typedef X86YMMREG const *PCX86YMMREG;
3610
3611	/**
3612	* ZMM register union.
3613	*/
3614	typedef union X86ZMMREG
3615	{
3616	/** 8-bit view. */
3617	uint8_t au8[64];
3618	/** 16-bit view. */
3619	uint16_t au16[32];
3620	/** 32-bit view. */
3621	uint32_t au32[16];
3622	/** 64-bit view. */
3623	uint64_t au64[8];
3624	/** Signed 8-bit view. */
3625	int8_t ai8[64];
3626	/** Signed 16-bit view. */
3627	int16_t ai16[32];
3628	/** Signed 32-bit view. */
3629	int32_t ai32[16];
3630	/** Signed 64-bit view. */
3631	int64_t ai64[8];
3632	/** 128-bit view. (yeah, very helpful) */
3633	uint128_t au128[4];
3634	/** Single precision floating point view. */
3635	RTFLOAT32U ar32[16];
3636	/** Double precision floating point view. */
3637	RTFLOAT64U ar64[8];
3638	/** XMM sub register view. */
3639	X86XMMREG aXmm[4];
3640	/** YMM sub register view. */
3641	X86YMMREG aYmm[2];
3642	} X86ZMMREG;
3643	# ifndef VBOX_FOR_DTRACE_LIB
3644	AssertCompileSize(X86ZMMREG, 64);
3645	# endif
3646	/** Pointer to an ZMM register state. */
3647	typedef X86ZMMREG *PX86ZMMREG;
3648	/** Pointer to a const ZMM register state. */
3649	typedef X86ZMMREG const *PCX86ZMMREG;
3650
3651
3652	/**
3653	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3654	*/
3655	# pragma pack(1)
3656	typedef struct X86FPUSTATE
3657	{
3658	/** 0x00 - Control word. */
3659	uint16_t FCW;
3660	/** 0x02 - Alignment word */
3661	uint16_t Dummy1;
3662	/** 0x04 - Status word. */
3663	uint16_t FSW;
3664	/** 0x06 - Alignment word */
3665	uint16_t Dummy2;
3666	/** 0x08 - Tag word */
3667	uint16_t FTW;
3668	/** 0x0a - Alignment word */
3669	uint16_t Dummy3;
3670
3671	/** 0x0c - Instruction pointer. */
3672	uint32_t FPUIP;
3673	/** 0x10 - Code selector. */
3674	uint16_t CS;
3675	/** 0x12 - Opcode. */
3676	uint16_t FOP;
3677	/** 0x14 - Data pointer. */
3678	uint32_t FPUOO;
3679	/** 0x18 - FOS. */
3680	uint16_t FPUOS;
3681	/** 0x0a - Alignment word */
3682	uint16_t Dummy4;
3683	/** 0x1c - FPU register. */
3684	X86FPUREG2 regs[8];
3685	} X86FPUSTATE;
3686	# pragma pack()
3687	AssertCompileSize(X86FPUSTATE, 108);
3688	/** Pointer to a FPU state. */
3689	typedef X86FPUSTATE *PX86FPUSTATE;
3690	/** Pointer to a const FPU state. */
3691	typedef const X86FPUSTATE *PCX86FPUSTATE;
3692
3693	/**
3694	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3695	*/
3696	# pragma pack(1)
3697	typedef struct X86FXSTATE
3698	{
3699	/** 0x00 - Control word. */
3700	uint16_t FCW;
3701	/** 0x02 - Status word. */
3702	uint16_t FSW;
3703	/** 0x04 - Tag word. (The upper byte is always zero.) */
3704	uint16_t FTW;
3705	/** 0x06 - Opcode. */
3706	uint16_t FOP;
3707	/** 0x08 - Instruction pointer. */
3708	uint32_t FPUIP;
3709	/** 0x0c - Code selector. */
3710	uint16_t CS;
3711	uint16_t Rsrvd1;
3712	/** 0x10 - Data pointer. */
3713	uint32_t FPUDP;
3714	/** 0x14 - Data segment */
3715	uint16_t DS;
3716	/** 0x16 */
3717	uint16_t Rsrvd2;
3718	/** 0x18 */
3719	uint32_t MXCSR;
3720	/** 0x1c */
3721	uint32_t MXCSR_MASK;
3722	/** 0x20 - FPU registers. */
3723	X86FPUREG aRegs[8];
3724	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3725	X86XMMREG aXMM[16];
3726	/* - offset 416 - */
3727	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3728	/* - offset 464 - Software usable reserved bits. */
3729	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3730	} X86FXSTATE;
3731	# pragma pack()
3732	/** Pointer to a FPU Extended state. */
3733	typedef X86FXSTATE *PX86FXSTATE;
3734	/** Pointer to a const FPU Extended state. */
3735	typedef const X86FXSTATE *PCX86FXSTATE;
3736
3737	#endif /* !__ASSEMBLER__ */
3738
3739
3740	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3741	* magic. Don't forget to update x86.mac if you change this! */
3742	#define X86_OFF_FXSTATE_RSVD 0x1d0
3743	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3744	* forget to update x86.mac if you change this!
3745	* @todo r=bird: This has nothing what-so-ever to do here.... */
3746	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3747	#ifndef VBOX_FOR_DTRACE_LIB
3748	AssertCompileSize(X86FXSTATE, 512);
3749	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3750	#endif
3751
3752	/** @name FPU status word flags.
3753	* @{ */
3754	/** Exception Flag: Invalid operation. */
3755	#define X86_FSW_IE RT_BIT_32(0)
3756	#define X86_FSW_IE_BIT 0
3757	/** Exception Flag: Denormalized operand. */
3758	#define X86_FSW_DE RT_BIT_32(1)
3759	#define X86_FSW_DE_BIT 1
3760	/** Exception Flag: Zero divide. */
3761	#define X86_FSW_ZE RT_BIT_32(2)
3762	#define X86_FSW_ZE_BIT 2
3763	/** Exception Flag: Overflow. */
3764	#define X86_FSW_OE RT_BIT_32(3)
3765	#define X86_FSW_OE_BIT 3
3766	/** Exception Flag: Underflow. */
3767	#define X86_FSW_UE RT_BIT_32(4)
3768	#define X86_FSW_UE_BIT 4
3769	/** Exception Flag: Precision. */
3770	#define X86_FSW_PE RT_BIT_32(5)
3771	#define X86_FSW_PE_BIT 5
3772	/** Stack fault. */
3773	#define X86_FSW_SF RT_BIT_32(6)
3774	#define X86_FSW_SF_BIT 6
3775	/** Error summary status. */
3776	#define X86_FSW_ES RT_BIT_32(7)
3777	#define X86_FSW_ES_BIT 7
3778	/** Mask of exceptions flags, excluding the summary bit. */
3779	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3780	/** Mask of exceptions flags, including the summary bit. */
3781	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3782	/** Condition code 0. */
3783	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3784	#define X86_FSW_C0_BIT 8
3785	/** Condition code 1. */
3786	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3787	#define X86_FSW_C1_BIT 9
3788	/** Condition code 2. */
3789	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3790	#define X86_FSW_C2_BIT 10
3791	/** Top of the stack mask. */
3792	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3793	/** TOP shift value. */
3794	#define X86_FSW_TOP_SHIFT 11
3795	/** Mask for getting TOP value after shifting it right. */
3796	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3797	/** Get the TOP value. */
3798	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3799	/** Get the TOP value offsetted by a_iSt (0-7). */
3800	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3801	/** Condition code 3. */
3802	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3803	#define X86_FSW_C3_BIT 14
3804	/** Mask of exceptions flags, including the summary bit. */
3805	#define X86_FSW_C_MASK UINT16_C(0x4700)
3806	/** FPU busy. */
3807	#define X86_FSW_B RT_BIT_32(15)
3808	/** For use with FPREM and FPREM1. */
3809	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3810	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3811	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3812	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3813	/** For use with FPREM and FPREM1. */
3814	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3815	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3816	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3817	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3818	/** @} */
3819
3820
3821	/** @name FPU control word flags.
3822	* @{ */
3823	/** Exception Mask: Invalid operation. */
3824	#define X86_FCW_IM RT_BIT_32(0)
3825	#define X86_FCW_IM_BIT 0
3826	/** Exception Mask: Denormalized operand. */
3827	#define X86_FCW_DM RT_BIT_32(1)
3828	#define X86_FCW_DM_BIT 1
3829	/** Exception Mask: Zero divide. */
3830	#define X86_FCW_ZM RT_BIT_32(2)
3831	#define X86_FCW_ZM_BIT 2
3832	/** Exception Mask: Overflow. */
3833	#define X86_FCW_OM RT_BIT_32(3)
3834	#define X86_FCW_OM_BIT 3
3835	/** Exception Mask: Underflow. */
3836	#define X86_FCW_UM RT_BIT_32(4)
3837	#define X86_FCW_UM_BIT 4
3838	/** Exception Mask: Precision. */
3839	#define X86_FCW_PM RT_BIT_32(5)
3840	#define X86_FCW_PM_BIT 5
3841	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3842	* @remarks This includes reserved bit 6. */
3843	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3844	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3845	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3846	/** Precision control mask. */
3847	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3848	/** Precision control shift. */
3849	#define X86_FCW_PC_SHIFT 8
3850	/** Precision control: 24-bit. */
3851	#define X86_FCW_PC_24 UINT16_C(0x0000)
3852	/** Precision control: Reserved. */
3853	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3854	/** Precision control: 53-bit. */
3855	#define X86_FCW_PC_53 UINT16_C(0x0200)
3856	/** Precision control: 64-bit. */
3857	#define X86_FCW_PC_64 UINT16_C(0x0300)
3858	/** Rounding control mask. */
3859	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3860	/** Rounding control shift. */
3861	#define X86_FCW_RC_SHIFT 10
3862	/** Rounding control: To nearest. */
3863	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3864	/** Rounding control: Down. */
3865	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3866	/** Rounding control: Up. */
3867	#define X86_FCW_RC_UP UINT16_C(0x0800)
3868	/** Rounding control: Towards zero. */
3869	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3870	/** Infinity control mask - obsolete, 8087 & 287 only. */
3871	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3872	/** Infinity control: Affine - positive infinity is distictly different from
3873	* negative infinity.
3874	* @note 8087, 287 only */
3875	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3876	/** Infinity control: Projective - positive and negative infinity are the
3877	* same (sign ignored).
3878	* @note 8087, 287 only */
3879	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3880	/** Bits which should be zero, apparently. */
3881	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3882	/** @} */
3883
3884	/** @name SSE MXCSR
3885	* @{ */
3886	/** Exception Flag: Invalid operation. */
3887	#define X86_MXCSR_IE RT_BIT_32(0)
3888	#define X86_MXCSR_IE_BIT 0
3889	/** Exception Flag: Denormalized operand. */
3890	#define X86_MXCSR_DE RT_BIT_32(1)
3891	#define X86_MXCSR_DE_BIT 1
3892	/** Exception Flag: Zero divide. */
3893	#define X86_MXCSR_ZE RT_BIT_32(2)
3894	#define X86_MXCSR_ZE_BIT 2
3895	/** Exception Flag: Overflow. */
3896	#define X86_MXCSR_OE RT_BIT_32(3)
3897	#define X86_MXCSR_OE_BIT 3
3898	/** Exception Flag: Underflow. */
3899	#define X86_MXCSR_UE RT_BIT_32(4)
3900	#define X86_MXCSR_UE_BIT 4
3901	/** Exception Flag: Precision. */
3902	#define X86_MXCSR_PE RT_BIT_32(5)
3903	#define X86_MXCSR_PE_BIT 5
3904	/** Exception Flags: mask */
3905	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3906
3907	/** Denormals are zero. */
3908	#define X86_MXCSR_DAZ RT_BIT_32(6)
3909	#define X86_MXCSR_DAZ_BIT 6
3910
3911	/** Exception Mask: Invalid operation. */
3912	#define X86_MXCSR_IM RT_BIT_32(7)
3913	#define X86_MXCSR_IM_BIT 7
3914	/** Exception Mask: Denormalized operand. */
3915	#define X86_MXCSR_DM RT_BIT_32(8)
3916	#define X86_MXCSR_DM_BIT 8
3917	/** Exception Mask: Zero divide. */
3918	#define X86_MXCSR_ZM RT_BIT_32(9)
3919	#define X86_MXCSR_ZM_BIT 9
3920	/** Exception Mask: Overflow. */
3921	#define X86_MXCSR_OM RT_BIT_32(10)
3922	#define X86_MXCSR_OM_BIT 10
3923	/** Exception Mask: Underflow. */
3924	#define X86_MXCSR_UM RT_BIT_32(11)
3925	#define X86_MXCSR_UM_BIT 11
3926	/** Exception Mask: Precision. */
3927	#define X86_MXCSR_PM RT_BIT_32(12)
3928	#define X86_MXCSR_PM_BIT 12
3929	/** Exception Mask: mask. */
3930	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3931	/** Exception Mask: shift. */
3932	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3933
3934	/** Rounding control mask. */
3935	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3936	/** Rounding control shift. */
3937	#define X86_MXCSR_RC_SHIFT 13
3938	/** Rounding control: To nearest. */
3939	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3940	/** Rounding control: Down. */
3941	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3942	/** Rounding control: Up. */
3943	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3944	/** Rounding control: Towards zero. */
3945	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3946
3947	/** Flush-to-zero for masked underflow. */
3948	#define X86_MXCSR_FZ RT_BIT_32(15)
3949	#define X86_MXCSR_FZ_BIT 15
3950
3951	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3952	#define X86_MXCSR_MM RT_BIT_32(17)
3953	#define X86_MXCSR_MM_BIT 17
3954	/** Bits which should be zero, apparently. */
3955	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3956	/** @} */
3957
3958	#ifndef __ASSEMBLER__
3959
3960	/**
3961	* XSAVE header.
3962	*/
3963	typedef struct X86XSAVEHDR
3964	{
3965	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3966	uint64_t bmXState;
3967	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3968	uint64_t bmXComp;
3969	/** Reserved for furture extensions, probably MBZ. */
3970	uint64_t au64Reserved[6];
3971	} X86XSAVEHDR;
3972	# ifndef VBOX_FOR_DTRACE_LIB
3973	AssertCompileSize(X86XSAVEHDR, 64);
3974	# endif
3975	/** Pointer to an XSAVE header. */
3976	typedef X86XSAVEHDR *PX86XSAVEHDR;
3977	/** Pointer to a const XSAVE header. */
3978	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3979
3980
3981	/**
3982	* The high 128-bit YMM register state (XSAVE_C_YMM).
3983	* (The lower 128-bits being in X86FXSTATE.)
3984	*/
3985	typedef struct X86XSAVEYMMHI
3986	{
3987	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3988	X86XMMREG aYmmHi[16];
3989	} X86XSAVEYMMHI;
3990	# ifndef VBOX_FOR_DTRACE_LIB
3991	AssertCompileSize(X86XSAVEYMMHI, 256);
3992	# endif
3993	/** Pointer to a high 128-bit YMM register state. */
3994	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3995	/** Pointer to a const high 128-bit YMM register state. */
3996	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3997
3998	/**
3999	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
4000	*/
4001	typedef struct X86XSAVEBNDREGS
4002	{
4003	/** Array of registers (BND0...BND3). */
4004	struct
4005	{
4006	/** Lower bound. */
4007	uint64_t uLowerBound;
4008	/** Upper bound. */
4009	uint64_t uUpperBound;
4010	} aRegs[4];
4011	} X86XSAVEBNDREGS;
4012	# ifndef VBOX_FOR_DTRACE_LIB
4013	AssertCompileSize(X86XSAVEBNDREGS, 64);
4014	# endif
4015	/** Pointer to a MPX bound register state. */
4016	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
4017	/** Pointer to a const MPX bound register state. */
4018	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
4019
4020	/**
4021	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
4022	*/
4023	typedef struct X86XSAVEBNDCFG
4024	{
4025	uint64_t fConfig;
4026	uint64_t fStatus;
4027	} X86XSAVEBNDCFG;
4028	# ifndef VBOX_FOR_DTRACE_LIB
4029	AssertCompileSize(X86XSAVEBNDCFG, 16);
4030	# endif
4031	/** Pointer to a MPX bound config and status register state. */
4032	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
4033	/** Pointer to a const MPX bound config and status register state. */
4034	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
4035
4036	/**
4037	* AVX-512 opmask state (XSAVE_C_OPMASK).
4038	*/
4039	typedef struct X86XSAVEOPMASK
4040	{
4041	/** The K0..K7 values. */
4042	uint64_t aKRegs[8];
4043	} X86XSAVEOPMASK;
4044	# ifndef VBOX_FOR_DTRACE_LIB
4045	AssertCompileSize(X86XSAVEOPMASK, 64);
4046	# endif
4047	/** Pointer to a AVX-512 opmask state. */
4048	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
4049	/** Pointer to a const AVX-512 opmask state. */
4050	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
4051
4052	/**
4053	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
4054	*/
4055	typedef struct X86XSAVEZMMHI256
4056	{
4057	/** Upper 256-bits of ZMM0-15. */
4058	X86YMMREG aHi256Regs[16];
4059	} X86XSAVEZMMHI256;
4060	# ifndef VBOX_FOR_DTRACE_LIB
4061	AssertCompileSize(X86XSAVEZMMHI256, 512);
4062	# endif
4063	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
4064	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
4065	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
4066	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
4067
4068	/**
4069	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
4070	*/
4071	typedef struct X86XSAVEZMM16HI
4072	{
4073	/** ZMM16 thru ZMM31. */
4074	X86ZMMREG aRegs[16];
4075	} X86XSAVEZMM16HI;
4076	# ifndef VBOX_FOR_DTRACE_LIB
4077	AssertCompileSize(X86XSAVEZMM16HI, 1024);
4078	# endif
4079	/** Pointer to a state comprising ZMM16-32. */
4080	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
4081	/** Pointer to a const state comprising ZMM16-32. */
4082	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
4083
4084	/**
4085	* AMD Light weight profiling state (XSAVE_C_LWP).
4086	*
4087	* We probably won't play with this as AMD seems to be dropping from their "zen"
4088	* processor micro architecture.
4089	*/
4090	typedef struct X86XSAVELWP
4091	{
4092	/** Details when needed. */
4093	uint64_t auLater[128/8];
4094	} X86XSAVELWP;
4095	# ifndef VBOX_FOR_DTRACE_LIB
4096	AssertCompileSize(X86XSAVELWP, 128);
4097	# endif
4098
4099
4100	/**
4101	* x86 FPU/SSE/AVX/XXXX state.
4102	*
4103	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
4104	* changes to this structure.
4105	*/
4106	typedef struct X86XSAVEAREA
4107	{
4108	/** The x87 and SSE region (or legacy region if you like). */
4109	X86FXSTATE x87;
4110	/** The XSAVE header. */
4111	X86XSAVEHDR Hdr;
4112	/** Beyond the header, there isn't really a fixed layout, but we can
4113	generally assume the YMM (AVX) register extensions are present and
4114	follows immediately. */
4115	union
4116	{
4117	/** The high 128-bit AVX registers for easy access by IEM.
4118	* @note This ASSUMES they will always be here... */
4119	X86XSAVEYMMHI YmmHi;
4120
4121	/** This is a typical layout on intel CPUs (good for debuggers). */
4122	struct
4123	{
4124	X86XSAVEYMMHI YmmHi;
4125	X86XSAVEBNDREGS BndRegs;
4126	X86XSAVEBNDCFG BndCfg;
4127	uint8_t abFudgeToMatchDocs[0xB0];
4128	X86XSAVEOPMASK Opmask;
4129	X86XSAVEZMMHI256 ZmmHi256;
4130	X86XSAVEZMM16HI Zmm16Hi;
4131	} Intel;
4132
4133	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
4134	struct
4135	{
4136	X86XSAVEYMMHI YmmHi;
4137	X86XSAVELWP Lwp;
4138	} AmdBd;
4139
4140	/** To enbling static deployments that have a reasonable chance of working for
4141	* the next 3-6 CPU generations without running short on space, we allocate a
4142	* lot of extra space here, making the structure a round 8KB in size. This
4143	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4144	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4145	uint8_t ab[8192 - 512 - 64];
4146	} u;
4147	} X86XSAVEAREA;
4148	# ifndef VBOX_FOR_DTRACE_LIB
4149	AssertCompileSize(X86XSAVEAREA, 8192);
4150	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
4151	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4152	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4153	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4154	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4155	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4156	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4157	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4158	# endif
4159	/** Pointer to a XSAVE area. */
4160	typedef X86XSAVEAREA *PX86XSAVEAREA;
4161	/** Pointer to a const XSAVE area. */
4162	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4163
4164	#endif /* __ASSEMBLER__ */
4165
4166
4167	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4168	* @{ */
4169	/** Bit 0 - x87 - Legacy FPU state (bit number) */
4170	#define XSAVE_C_X87_BIT 0
4171	/** Bit 0 - x87 - Legacy FPU state. */
4172	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4173	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4174	#define XSAVE_C_SSE_BIT 1
4175	/** Bit 1 - SSE - 128-bit SSE state. */
4176	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4177	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4178	#define XSAVE_C_YMM_BIT 2
4179	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4180	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4181	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4182	#define XSAVE_C_BNDREGS_BIT 3
4183	/** Bit 3 - BNDREGS - MPX bound register state. */
4184	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4185	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4186	#define XSAVE_C_BNDCSR_BIT 4
4187	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4188	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4189	/** Bit 5 - Opmask - opmask state (bit number). */
4190	#define XSAVE_C_OPMASK_BIT 5
4191	/** Bit 5 - Opmask - opmask state. */
4192	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4193	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4194	#define XSAVE_C_ZMM_HI256_BIT 6
4195	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4196	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4197	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4198	#define XSAVE_C_ZMM_16HI_BIT 7
4199	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4200	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4201	/** Bit 9 - PKRU - Protection-key state (bit number). */
4202	#define XSAVE_C_PKRU_BIT 9
4203	/** Bit 9 - PKRU - Protection-key state. */
4204	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4205	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4206	#define XSAVE_C_LWP_BIT 62
4207	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4208	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4209	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4210	#define XSAVE_C_X_BIT 63
4211	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4212	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4213	/** @} */
4214
4215
4216
4217	/** @name Selector Descriptor
4218	* @{
4219	*/
4220
4221	#ifndef __ASSEMBLER__
4222	# ifndef VBOX_FOR_DTRACE_LIB
4223	/**
4224	* Descriptor attributes (as seen by VT-x).
4225	*/
4226	typedef struct X86DESCATTRBITS
4227	{
4228	/** 00 - Segment Type. */
4229	unsigned u4Type : 4;
4230	/** 04 - Descriptor Type. System(=0) or code/data selector */
4231	unsigned u1DescType : 1;
4232	/** 05 - Descriptor Privilege level. */
4233	unsigned u2Dpl : 2;
4234	/** 07 - Flags selector present(=1) or not. */
4235	unsigned u1Present : 1;
4236	/** 08 - Segment limit 16-19. */
4237	unsigned u4LimitHigh : 4;
4238	/** 0c - Available for system software. */
4239	unsigned u1Available : 1;
4240	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4241	unsigned u1Long : 1;
4242	/** 0e - This flags meaning depends on the segment type. Try make sense out
4243	* of the intel manual yourself. */
4244	unsigned u1DefBig : 1;
4245	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4246	* clear byte. */
4247	unsigned u1Granularity : 1;
4248	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4249	unsigned u1Unusable : 1;
4250	} X86DESCATTRBITS;
4251	# endif /* !VBOX_FOR_DTRACE_LIB */
4252	#endif /* !__ASSEMBLER__ */
4253
4254	/** @name X86DESCATTR masks
4255	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4256	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4257	* @{ */
4258	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4259	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4260	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4261	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4262	#define X86DESCATTR_P UINT32_C(0x00000080)
4263	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4264	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4265	#define X86DESCATTR_L UINT32_C(0x00002000)
4266	#define X86DESCATTR_D UINT32_C(0x00004000)
4267	#define X86DESCATTR_G UINT32_C(0x00008000)
4268	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4269	/** @} */
4270
4271
4272	#ifndef __ASSEMBLER__
4273	# pragma pack(1)
4274	typedef union X86DESCATTR
4275	{
4276	/** Unsigned integer view. */
4277	uint32_t u;
4278	# ifndef VBOX_FOR_DTRACE_LIB
4279	/** Normal view. */
4280	X86DESCATTRBITS n;
4281	# endif
4282	} X86DESCATTR;
4283	# pragma pack()
4284	/** Pointer to descriptor attributes. */
4285	typedef X86DESCATTR *PX86DESCATTR;
4286	/** Pointer to const descriptor attributes. */
4287	typedef const X86DESCATTR *PCX86DESCATTR;
4288	#endif /* !__ASSEMBLER__ */
4289
4290	#ifndef VBOX_FOR_DTRACE_LIB
4291
4292	#ifndef __ASSEMBLER__
4293	/**
4294	* Generic descriptor table entry
4295	*/
4296	# pragma pack(1)
4297	typedef struct X86DESCGENERIC
4298	{
4299	/** 00 - Limit - Low word. */
4300	unsigned u16LimitLow : 16;
4301	/** 10 - Base address - low word.
4302	* Don't try set this to 24 because MSC is doing stupid things then. */
4303	unsigned u16BaseLow : 16;
4304	/** 20 - Base address - first 8 bits of high word. */
4305	unsigned u8BaseHigh1 : 8;
4306	/** 28 - Segment Type. */
4307	unsigned u4Type : 4;
4308	/** 2c - Descriptor Type. System(=0) or code/data selector */
4309	unsigned u1DescType : 1;
4310	/** 2d - Descriptor Privilege level. */
4311	unsigned u2Dpl : 2;
4312	/** 2f - Flags selector present(=1) or not. */
4313	unsigned u1Present : 1;
4314	/** 30 - Segment limit 16-19. */
4315	unsigned u4LimitHigh : 4;
4316	/** 34 - Available for system software. */
4317	unsigned u1Available : 1;
4318	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4319	unsigned u1Long : 1;
4320	/** 36 - This flags meaning depends on the segment type. Try make sense out
4321	* of the intel manual yourself. */
4322	unsigned u1DefBig : 1;
4323	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4324	* clear byte. */
4325	unsigned u1Granularity : 1;
4326	/** 38 - Base address - highest 8 bits. */
4327	unsigned u8BaseHigh2 : 8;
4328	} X86DESCGENERIC;
4329	# pragma pack()
4330	/** Pointer to a generic descriptor entry. */
4331	typedef X86DESCGENERIC *PX86DESCGENERIC;
4332	/** Pointer to a const generic descriptor entry. */
4333	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4334	# endif /* !__ASSEMBLER__ */
4335
4336
4337	/** @name Bit offsets of X86DESCGENERIC members.
4338	* @{*/
4339	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4340	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4341	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4342	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4343	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4344	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4345	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4346	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4347	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4348	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4349	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4350	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4351	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4352	/** @} */
4353
4354
4355	/** @name LAR mask
4356	* @{ */
4357	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4358	# define X86LAR_F_DT UINT16_C( 0x1000)
4359	# define X86LAR_F_DPL UINT16_C( 0x6000)
4360	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4361	# define X86LAR_F_P UINT16_C( 0x8000)
4362	# define X86LAR_F_AVL UINT32_C(0x00100000)
4363	# define X86LAR_F_L UINT32_C(0x00200000)
4364	# define X86LAR_F_D UINT32_C(0x00400000)
4365	# define X86LAR_F_G UINT32_C(0x00800000)
4366	/** @} */
4367
4368
4369	# ifndef __ASSEMBLER__
4370	/**
4371	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4372	*/
4373	typedef struct X86DESCGATE
4374	{
4375	/** 00 - Target code segment offset - Low word.
4376	* Ignored if task-gate. */
4377	unsigned u16OffsetLow : 16;
4378	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4379	* TSS selector if task-gate. */
4380	unsigned u16Sel : 16;
4381	/** 20 - Number of parameters for a call-gate.
4382	* Ignored if interrupt-, trap- or task-gate. */
4383	unsigned u5ParmCount : 5;
4384	/** 25 - Reserved / ignored. */
4385	unsigned u3Reserved : 3;
4386	/** 28 - Segment Type. */
4387	unsigned u4Type : 4;
4388	/** 2c - Descriptor Type (0 = system). */
4389	unsigned u1DescType : 1;
4390	/** 2d - Descriptor Privilege level. */
4391	unsigned u2Dpl : 2;
4392	/** 2f - Flags selector present(=1) or not. */
4393	unsigned u1Present : 1;
4394	/** 30 - Target code segment offset - High word.
4395	* Ignored if task-gate. */
4396	unsigned u16OffsetHigh : 16;
4397	} X86DESCGATE;
4398	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4399	typedef X86DESCGATE *PX86DESCGATE;
4400	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4401	typedef const X86DESCGATE *PCX86DESCGATE;
4402	# endif /* !__ASSEMBLER__ */
4403
4404	#endif /* VBOX_FOR_DTRACE_LIB */
4405
4406	#ifndef __ASSEMBLER__
4407	/**
4408	* Descriptor table entry.
4409	*/
4410	# pragma pack(1)
4411	typedef union X86DESC
4412	{
4413	# ifndef VBOX_FOR_DTRACE_LIB
4414	/** Generic descriptor view. */
4415	X86DESCGENERIC Gen;
4416	/** Gate descriptor view. */
4417	X86DESCGATE Gate;
4418	# endif
4419	/** 8 bit unsigned integer view. */
4420	uint8_t au8[8];
4421	/** 16 bit unsigned integer view. */
4422	uint16_t au16[4];
4423	/** 32 bit unsigned integer view. */
4424	uint32_t au32[2];
4425	/** 64 bit unsigned integer view. */
4426	uint64_t au64[1];
4427	/** Unsigned integer view. */
4428	uint64_t u;
4429	} X86DESC;
4430	# ifndef VBOX_FOR_DTRACE_LIB
4431	AssertCompileSize(X86DESC, 8);
4432	# endif
4433	# pragma pack()
4434	/** Pointer to descriptor table entry. */
4435	typedef X86DESC *PX86DESC;
4436	/** Pointer to const descriptor table entry. */
4437	typedef const X86DESC *PCX86DESC;
4438	#endif /* !__ASSEMBLER__ */
4439
4440	/** @def X86DESC_BASE
4441	* Return the base address of a descriptor.
4442	*/
4443	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4444	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4445	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4446	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4447
4448	/** @def X86DESC_LIMIT
4449	* Return the limit of a descriptor.
4450	*/
4451	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4452	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4453	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4454
4455	/** @def X86DESC_LIMIT_G
4456	* Return the limit of a descriptor with the granularity bit taken into account.
4457	* @returns Selector limit (uint32_t).
4458	* @param a_pDesc Pointer to the descriptor.
4459	*/
4460	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4461	( (a_pDesc)->Gen.u1Granularity \
4462	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4463	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4464	)
4465
4466	/** @def X86DESC_GET_HID_ATTR
4467	* Get the descriptor attributes for the hidden register.
4468	*/
4469	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4470	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4471
4472	#ifndef __ASSEMBLER__
4473	# ifndef VBOX_FOR_DTRACE_LIB
4474
4475	/**
4476	* 64 bits generic descriptor table entry
4477	* Note: most of these bits have no meaning in long mode.
4478	*/
4479	# pragma pack(1)
4480	typedef struct X86DESC64GENERIC
4481	{
4482	/** Limit - Low word - IGNORED. */
4483	uint32_t u16LimitLow : 16;
4484	/** Base address - low word. - IGNORED
4485	* Don't try set this to 24 because MSC is doing stupid things then. */
4486	uint32_t u16BaseLow : 16;
4487	/** Base address - first 8 bits of high word. - IGNORED */
4488	uint32_t u8BaseHigh1 : 8;
4489	/** Segment Type. */
4490	uint32_t u4Type : 4;
4491	/** Descriptor Type. System(=0) or code/data selector */
4492	uint32_t u1DescType : 1;
4493	/** Descriptor Privilege level. */
4494	uint32_t u2Dpl : 2;
4495	/** Flags selector present(=1) or not. */
4496	uint32_t u1Present : 1;
4497	/** Segment limit 16-19. - IGNORED */
4498	uint32_t u4LimitHigh : 4;
4499	/** Available for system software. - IGNORED */
4500	uint32_t u1Available : 1;
4501	/** Long mode flag. */
4502	uint32_t u1Long : 1;
4503	/** This flags meaning depends on the segment type. Try make sense out
4504	* of the intel manual yourself. */
4505	uint32_t u1DefBig : 1;
4506	/** Granularity of the limit. If set 4KB granularity is used, if
4507	* clear byte. - IGNORED */
4508	uint32_t u1Granularity : 1;
4509	/** Base address - highest 8 bits. - IGNORED */
4510	uint32_t u8BaseHigh2 : 8;
4511	/** Base address - bits 63-32. */
4512	uint32_t u32BaseHigh3 : 32;
4513	uint32_t u8Reserved : 8;
4514	uint32_t u5Zeros : 5;
4515	uint32_t u19Reserved : 19;
4516	} X86DESC64GENERIC;
4517	# pragma pack()
4518	/** Pointer to a generic descriptor entry. */
4519	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4520	/** Pointer to a const generic descriptor entry. */
4521	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4522
4523	/**
4524	* System descriptor table entry (64 bits)
4525	*
4526	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4527	*/
4528	# pragma pack(1)
4529	typedef struct X86DESC64SYSTEM
4530	{
4531	/** Limit - Low word. */
4532	uint32_t u16LimitLow : 16;
4533	/** Base address - low word.
4534	* Don't try set this to 24 because MSC is doing stupid things then. */
4535	uint32_t u16BaseLow : 16;
4536	/** Base address - first 8 bits of high word. */
4537	uint32_t u8BaseHigh1 : 8;
4538	/** Segment Type. */
4539	uint32_t u4Type : 4;
4540	/** Descriptor Type. System(=0) or code/data selector */
4541	uint32_t u1DescType : 1;
4542	/** Descriptor Privilege level. */
4543	uint32_t u2Dpl : 2;
4544	/** Flags selector present(=1) or not. */
4545	uint32_t u1Present : 1;
4546	/** Segment limit 16-19. */
4547	uint32_t u4LimitHigh : 4;
4548	/** Available for system software. */
4549	uint32_t u1Available : 1;
4550	/** Reserved - 0. */
4551	uint32_t u1Reserved : 1;
4552	/** This flags meaning depends on the segment type. Try make sense out
4553	* of the intel manual yourself. */
4554	uint32_t u1DefBig : 1;
4555	/** Granularity of the limit. If set 4KB granularity is used, if
4556	* clear byte. */
4557	uint32_t u1Granularity : 1;
4558	/** Base address - bits 31-24. */
4559	uint32_t u8BaseHigh2 : 8;
4560	/** Base address - bits 63-32. */
4561	uint32_t u32BaseHigh3 : 32;
4562	uint32_t u8Reserved : 8;
4563	uint32_t u5Zeros : 5;
4564	uint32_t u19Reserved : 19;
4565	} X86DESC64SYSTEM;
4566	# pragma pack()
4567	/** Pointer to a system descriptor entry. */
4568	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4569	/** Pointer to a const system descriptor entry. */
4570	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4571
4572	/**
4573	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4574	*/
4575	typedef struct X86DESC64GATE
4576	{
4577	/** Target code segment offset - Low word. */
4578	uint32_t u16OffsetLow : 16;
4579	/** Target code segment selector. */
4580	uint32_t u16Sel : 16;
4581	/** Interrupt stack table for interrupt- and trap-gates.
4582	* Ignored by call-gates. */
4583	uint32_t u3IST : 3;
4584	/** Reserved / ignored. */
4585	uint32_t u5Reserved : 5;
4586	/** Segment Type. */
4587	uint32_t u4Type : 4;
4588	/** Descriptor Type (0 = system). */
4589	uint32_t u1DescType : 1;
4590	/** Descriptor Privilege level. */
4591	uint32_t u2Dpl : 2;
4592	/** Flags selector present(=1) or not. */
4593	uint32_t u1Present : 1;
4594	/** Target code segment offset - High word.
4595	* Ignored if task-gate. */
4596	uint32_t u16OffsetHigh : 16;
4597	/** Target code segment offset - Top dword.
4598	* Ignored if task-gate. */
4599	uint32_t u32OffsetTop : 32;
4600	/** Reserved / ignored / must be zero.
4601	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4602	uint32_t u32Reserved : 32;
4603	} X86DESC64GATE;
4604	AssertCompileSize(X86DESC64GATE, 16);
4605	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4606	typedef X86DESC64GATE *PX86DESC64GATE;
4607	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4608	typedef const X86DESC64GATE *PCX86DESC64GATE;
4609
4610	# endif /* VBOX_FOR_DTRACE_LIB */
4611
4612	/**
4613	* Descriptor table entry.
4614	*/
4615	# pragma pack(1)
4616	typedef union X86DESC64
4617	{
4618	# ifndef VBOX_FOR_DTRACE_LIB
4619	/** Generic descriptor view. */
4620	X86DESC64GENERIC Gen;
4621	/** System descriptor view. */
4622	X86DESC64SYSTEM System;
4623	/** Gate descriptor view. */
4624	X86DESC64GATE Gate;
4625	# endif
4626
4627	/** 8 bit unsigned integer view. */
4628	uint8_t au8[16];
4629	/** 16 bit unsigned integer view. */
4630	uint16_t au16[8];
4631	/** 32 bit unsigned integer view. */
4632	uint32_t au32[4];
4633	/** 64 bit unsigned integer view. */
4634	uint64_t au64[2];
4635	} X86DESC64;
4636	# ifndef VBOX_FOR_DTRACE_LIB
4637	AssertCompileSize(X86DESC64, 16);
4638	# endif
4639	# pragma pack()
4640	/** Pointer to descriptor table entry. */
4641	typedef X86DESC64 *PX86DESC64;
4642	/** Pointer to const descriptor table entry. */
4643	typedef const X86DESC64 *PCX86DESC64;
4644
4645	/** @def X86DESC64_BASE
4646	* Return the base of a 64-bit descriptor.
4647	*/
4648	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4649	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4650	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4651	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4652	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4653
4654
4655
4656	/** @name Host system descriptor table entry - Use with care!
4657	* @{ */
4658	/** Host system descriptor table entry. */
4659	#if HC_ARCH_BITS == 64
4660	typedef X86DESC64 X86DESCHC;
4661	#else
4662	typedef X86DESC X86DESCHC;
4663	#endif
4664	/** Pointer to a host system descriptor table entry. */
4665	#if HC_ARCH_BITS == 64
4666	typedef PX86DESC64 PX86DESCHC;
4667	#else
4668	typedef PX86DESC PX86DESCHC;
4669	#endif
4670	/** Pointer to a const host system descriptor table entry. */
4671	#if HC_ARCH_BITS == 64
4672	typedef PCX86DESC64 PCX86DESCHC;
4673	#else
4674	typedef PCX86DESC PCX86DESCHC;
4675	#endif
4676	/** @} */
4677
4678	#endif /* !__ASSEMBLER__ */
4679
4680
4681	/** @name Selector Descriptor Types.
4682	* @{
4683	*/
4684
4685	/** @name Non-System Selector Types.
4686	* @{ */
4687	/** Code(=set)/Data(=clear) bit. */
4688	#define X86_SEL_TYPE_CODE 8
4689	/** Memory(=set)/System(=clear) bit. */
4690	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4691	/** Accessed bit. */
4692	#define X86_SEL_TYPE_ACCESSED 1
4693	/** Expand down bit (for data selectors only). */
4694	#define X86_SEL_TYPE_DOWN 4
4695	/** Conforming bit (for code selectors only). */
4696	#define X86_SEL_TYPE_CONF 4
4697	/** Write bit (for data selectors only). */
4698	#define X86_SEL_TYPE_WRITE 2
4699	/** Read bit (for code selectors only). */
4700	#define X86_SEL_TYPE_READ 2
4701	/** The bit number of the code segment read bit (relative to u4Type). */
4702	#define X86_SEL_TYPE_READ_BIT 1
4703
4704	/** Read only selector type. */
4705	#define X86_SEL_TYPE_RO 0
4706	/** Accessed read only selector type. */
4707	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4708	/** Read write selector type. */
4709	#define X86_SEL_TYPE_RW 2
4710	/** Accessed read write selector type. */
4711	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4712	/** Expand down read only selector type. */
4713	#define X86_SEL_TYPE_RO_DOWN 4
4714	/** Accessed expand down read only selector type. */
4715	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4716	/** Expand down read write selector type. */
4717	#define X86_SEL_TYPE_RW_DOWN 6
4718	/** Accessed expand down read write selector type. */
4719	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4720	/** Execute only selector type. */
4721	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4722	/** Accessed execute only selector type. */
4723	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4724	/** Execute and read selector type. */
4725	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4726	/** Accessed execute and read selector type. */
4727	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4728	/** Conforming execute only selector type. */
4729	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4730	/** Accessed Conforming execute only selector type. */
4731	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4732	/** Conforming execute and write selector type. */
4733	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4734	/** Accessed Conforming execute and write selector type. */
4735	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4736	/** @} */
4737
4738
4739	/** @name System Selector Types.
4740	* @{ */
4741	/** The TSS busy bit mask. */
4742	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4743
4744	/** Undefined system selector type. */
4745	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4746	/** 286 TSS selector. */
4747	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4748	/** LDT selector. */
4749	#define X86_SEL_TYPE_SYS_LDT 2
4750	/** 286 TSS selector - Busy. */
4751	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4752	/** 286 Callgate selector. */
4753	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4754	/** Taskgate selector. */
4755	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4756	/** 286 Interrupt gate selector. */
4757	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4758	/** 286 Trapgate selector. */
4759	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4760	/** Undefined system selector. */
4761	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4762	/** 386 TSS selector. */
4763	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4764	/** Undefined system selector. */
4765	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4766	/** 386 TSS selector - Busy. */
4767	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4768	/** 386 Callgate selector. */
4769	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4770	/** Undefined system selector. */
4771	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4772	/** 386 Interruptgate selector. */
4773	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4774	/** 386 Trapgate selector. */
4775	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4776	/** @} */
4777
4778	/** @name AMD64 System Selector Types.
4779	* @{ */
4780	/** LDT selector. */
4781	#define AMD64_SEL_TYPE_SYS_LDT 2
4782	/** TSS selector - Busy. */
4783	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4784	/** TSS selector - Busy. */
4785	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4786	/** Callgate selector. */
4787	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4788	/** Interruptgate selector. */
4789	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4790	/** Trapgate selector. */
4791	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4792	/** @} */
4793
4794	/** @} */
4795
4796
4797	/** @name Descriptor Table Entry Flag Masks.
4798	* These are for the 2nd 32-bit word of a descriptor.
4799	* @{ */
4800	/** Bits 8-11 - TYPE - Descriptor type mask. */
4801	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4802	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4803	#define X86_DESC_S RT_BIT_32(12)
4804	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4805	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4806	/** Bit 15 - P - Present. */
4807	#define X86_DESC_P RT_BIT_32(15)
4808	/** Bit 20 - AVL - Available for system software. */
4809	#define X86_DESC_AVL RT_BIT_32(20)
4810	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4811	#define X86_DESC_DB RT_BIT_32(22)
4812	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4813	* used, if clear byte. */
4814	#define X86_DESC_G RT_BIT_32(23)
4815	/** @} */
4816
4817	/** @} */
4818
4819
4820	/** @name Task Segments.
4821	* @{
4822	*/
4823
4824	/**
4825	* The minimum TSS descriptor limit for 286 tasks.
4826	*/
4827	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4828
4829	/**
4830	* The minimum TSS descriptor segment limit for 386 tasks.
4831	*/
4832	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4833
4834	#ifndef __ASSEMBLER__
4835
4836	/**
4837	* 16-bit Task Segment (TSS).
4838	*/
4839	# pragma pack(1)
4840	typedef struct X86TSS16
4841	{
4842	/** Back link to previous task. (static) */
4843	RTSEL selPrev;
4844	/** Ring-0 stack pointer. (static) */
4845	uint16_t sp0;
4846	/** Ring-0 stack segment. (static) */
4847	RTSEL ss0;
4848	/** Ring-1 stack pointer. (static) */
4849	uint16_t sp1;
4850	/** Ring-1 stack segment. (static) */
4851	RTSEL ss1;
4852	/** Ring-2 stack pointer. (static) */
4853	uint16_t sp2;
4854	/** Ring-2 stack segment. (static) */
4855	RTSEL ss2;
4856	/** IP before task switch. */
4857	uint16_t ip;
4858	/** FLAGS before task switch. */
4859	uint16_t flags;
4860	/** AX before task switch. */
4861	uint16_t ax;
4862	/** CX before task switch. */
4863	uint16_t cx;
4864	/** DX before task switch. */
4865	uint16_t dx;
4866	/** BX before task switch. */
4867	uint16_t bx;
4868	/** SP before task switch. */
4869	uint16_t sp;
4870	/** BP before task switch. */
4871	uint16_t bp;
4872	/** SI before task switch. */
4873	uint16_t si;
4874	/** DI before task switch. */
4875	uint16_t di;
4876	/** ES before task switch. */
4877	RTSEL es;
4878	/** CS before task switch. */
4879	RTSEL cs;
4880	/** SS before task switch. */
4881	RTSEL ss;
4882	/** DS before task switch. */
4883	RTSEL ds;
4884	/** LDTR before task switch. */
4885	RTSEL selLdt;
4886	} X86TSS16;
4887	# ifndef VBOX_FOR_DTRACE_LIB
4888	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4889	# endif
4890	# pragma pack()
4891	/** Pointer to a 16-bit task segment. */
4892	typedef X86TSS16 *PX86TSS16;
4893	/** Pointer to a const 16-bit task segment. */
4894	typedef const X86TSS16 *PCX86TSS16;
4895
4896
4897	/**
4898	* 32-bit Task Segment (TSS).
4899	*/
4900	# pragma pack(1)
4901	typedef struct X86TSS32
4902	{
4903	/** Back link to previous task. (static) */
4904	RTSEL selPrev;
4905	uint16_t padding1;
4906	/** Ring-0 stack pointer. (static) */
4907	uint32_t esp0;
4908	/** Ring-0 stack segment. (static) */
4909	RTSEL ss0;
4910	uint16_t padding_ss0;
4911	/** Ring-1 stack pointer. (static) */
4912	uint32_t esp1;
4913	/** Ring-1 stack segment. (static) */
4914	RTSEL ss1;
4915	uint16_t padding_ss1;
4916	/** Ring-2 stack pointer. (static) */
4917	uint32_t esp2;
4918	/** Ring-2 stack segment. (static) */
4919	RTSEL ss2;
4920	uint16_t padding_ss2;
4921	/** Page directory for the task. (static) */
4922	uint32_t cr3;
4923	/** EIP before task switch. */
4924	uint32_t eip;
4925	/** EFLAGS before task switch. */
4926	uint32_t eflags;
4927	/** EAX before task switch. */
4928	uint32_t eax;
4929	/** ECX before task switch. */
4930	uint32_t ecx;
4931	/** EDX before task switch. */
4932	uint32_t edx;
4933	/** EBX before task switch. */
4934	uint32_t ebx;
4935	/** ESP before task switch. */
4936	uint32_t esp;
4937	/** EBP before task switch. */
4938	uint32_t ebp;
4939	/** ESI before task switch. */
4940	uint32_t esi;
4941	/** EDI before task switch. */
4942	uint32_t edi;
4943	/** ES before task switch. */
4944	RTSEL es;
4945	uint16_t padding_es;
4946	/** CS before task switch. */
4947	RTSEL cs;
4948	uint16_t padding_cs;
4949	/** SS before task switch. */
4950	RTSEL ss;
4951	uint16_t padding_ss;
4952	/** DS before task switch. */
4953	RTSEL ds;
4954	uint16_t padding_ds;
4955	/** FS before task switch. */
4956	RTSEL fs;
4957	uint16_t padding_fs;
4958	/** GS before task switch. */
4959	RTSEL gs;
4960	uint16_t padding_gs;
4961	/** LDTR before task switch. */
4962	RTSEL selLdt;
4963	uint16_t padding_ldt;
4964	/** Debug trap flag */
4965	uint16_t fDebugTrap;
4966	/** Offset relative to the TSS of the start of the I/O Bitmap
4967	* and the end of the interrupt redirection bitmap. */
4968	uint16_t offIoBitmap;
4969	} X86TSS32;
4970	# pragma pack()
4971	/** Pointer to task segment. */
4972	typedef X86TSS32 *PX86TSS32;
4973	/** Pointer to const task segment. */
4974	typedef const X86TSS32 *PCX86TSS32;
4975	# ifndef VBOX_FOR_DTRACE_LIB
4976	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4977	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4978	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4979	# endif
4980
4981	/**
4982	* 64-bit Task segment.
4983	*/
4984	# pragma pack(1)
4985	typedef struct X86TSS64
4986	{
4987	/** Reserved. */
4988	uint32_t u32Reserved;
4989	/** Ring-0 stack pointer. (static) */
4990	uint64_t rsp0;
4991	/** Ring-1 stack pointer. (static) */
4992	uint64_t rsp1;
4993	/** Ring-2 stack pointer. (static) */
4994	uint64_t rsp2;
4995	/** Reserved. */
4996	uint32_t u32Reserved2[2];
4997	/* IST */
4998	uint64_t ist1;
4999	uint64_t ist2;
5000	uint64_t ist3;
5001	uint64_t ist4;
5002	uint64_t ist5;
5003	uint64_t ist6;
5004	uint64_t ist7;
5005	/* Reserved. */
5006	uint16_t u16Reserved[5];
5007	/** Offset relative to the TSS of the start of the I/O Bitmap
5008	* and the end of the interrupt redirection bitmap. */
5009	uint16_t offIoBitmap;
5010	} X86TSS64;
5011	# pragma pack()
5012	/** Pointer to a 64-bit task segment. */
5013	typedef X86TSS64 *PX86TSS64;
5014	/** Pointer to a const 64-bit task segment. */
5015	typedef const X86TSS64 *PCX86TSS64;
5016	# ifndef VBOX_FOR_DTRACE_LIB
5017	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
5018	# endif
5019
5020	#endif /* !__ASSEMBLER__ */
5021
5022	/** @} */
5023
5024
5025	/** @name Selectors.
5026	* @{
5027	*/
5028
5029	/**
5030	* The shift used to convert a selector from and to index an index (C).
5031	*/
5032	#define X86_SEL_SHIFT 3
5033
5034	/**
5035	* The mask used to mask off the table indicator and RPL of an selector.
5036	*/
5037	#define X86_SEL_MASK 0xfff8U
5038
5039	/**
5040	* The mask used to mask off the RPL of an selector.
5041	* This is suitable for checking for NULL selectors.
5042	*/
5043	#define X86_SEL_MASK_OFF_RPL 0xfffcU
5044
5045	/**
5046	* The bit indicating that a selector is in the LDT and not in the GDT.
5047	*/
5048	#define X86_SEL_LDT 0x0004U
5049
5050	/**
5051	* The bit mask for getting the RPL of a selector.
5052	*/
5053	#define X86_SEL_RPL 0x0003U
5054
5055	/**
5056	* The mask covering both RPL and LDT.
5057	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
5058	* checks.
5059	*/
5060	#define X86_SEL_RPL_LDT 0x0007U
5061
5062	/** @} */
5063
5064
5065	#ifndef __ASSEMBLER__
5066	/**
5067	* x86 Exceptions/Faults/Traps.
5068	*/
5069	typedef enum X86XCPT
5070	{
5071	/** \#DE - Divide error. */
5072	X86_XCPT_DE = 0x00,
5073	/** \#DB - Debug event (single step, DRx, ..) */
5074	X86_XCPT_DB = 0x01,
5075	/** NMI - Non-Maskable Interrupt */
5076	X86_XCPT_NMI = 0x02,
5077	/** \#BP - Breakpoint (INT3). */
5078	X86_XCPT_BP = 0x03,
5079	/** \#OF - Overflow (INTO). */
5080	X86_XCPT_OF = 0x04,
5081	/** \#BR - Bound range exceeded (BOUND). */
5082	X86_XCPT_BR = 0x05,
5083	/** \#UD - Undefined opcode. */
5084	X86_XCPT_UD = 0x06,
5085	/** \#NM - Device not available (math coprocessor device). */
5086	X86_XCPT_NM = 0x07,
5087	/** \#DF - Double fault. */
5088	X86_XCPT_DF = 0x08,
5089	/** ??? - Coprocessor segment overrun (obsolete). */
5090	X86_XCPT_CO_SEG_OVERRUN = 0x09,
5091	/** \#TS - Taskswitch (TSS). */
5092	X86_XCPT_TS = 0x0a,
5093	/** \#NP - Segment no present. */
5094	X86_XCPT_NP = 0x0b,
5095	/** \#SS - Stack segment fault. */
5096	X86_XCPT_SS = 0x0c,
5097	/** \#GP - General protection fault. */
5098	X86_XCPT_GP = 0x0d,
5099	/** \#PF - Page fault. */
5100	X86_XCPT_PF = 0x0e,
5101	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
5102	/** \#MF - Math fault (FPU). */
5103	X86_XCPT_MF = 0x10,
5104	/** \#AC - Alignment check. */
5105	X86_XCPT_AC = 0x11,
5106	/** \#MC - Machine check. */
5107	X86_XCPT_MC = 0x12,
5108	/** \#XF - SIMD Floating-Point Exception. */
5109	X86_XCPT_XF = 0x13,
5110	/** \#VE - Virtualization Exception (Intel only). */
5111	X86_XCPT_VE = 0x14,
5112	/** \#CP - Control Protection Exception. */
5113	X86_XCPT_CP = 0x15,
5114	/** \#VC - VMM Communication Exception (AMD only). */
5115	X86_XCPT_VC = 0x1d,
5116	/** \#SX - Security Exception (AMD only). */
5117	X86_XCPT_SX = 0x1e
5118	} X86XCPT;
5119	/** Pointer to a x86 exception code. */
5120	typedef X86XCPT *PX86XCPT;
5121	/** Pointer to a const x86 exception code. */
5122	typedef const X86XCPT *PCX86XCPT;
5123	#endif /* !__ASSEMBLER__ */
5124	/** The last valid (currently reserved) exception value. */
5125	#define X86_XCPT_LAST 0x1f
5126
5127
5128	/** @name Trap Error Codes
5129	* @{
5130	*/
5131	/** External indicator. */
5132	#define X86_TRAP_ERR_EXTERNAL 1
5133	/** IDT indicator. */
5134	#define X86_TRAP_ERR_IDT 2
5135	/** Descriptor table indicator - If set LDT, if clear GDT. */
5136	#define X86_TRAP_ERR_TI 4
5137	/** Mask for getting the selector. */
5138	#define X86_TRAP_ERR_SEL_MASK 0xfff8
5139	/** Shift for getting the selector table index (C type index). */
5140	#define X86_TRAP_ERR_SEL_SHIFT 3
5141	/** @} */
5142
5143
5144	/** @name \#PF Trap Error Codes
5145	* @{
5146	*/
5147	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5148	#define X86_TRAP_PF_P RT_BIT_32(0)
5149	/** Bit 1 - R/W - Read (clear) or write (set) access. */
5150	#define X86_TRAP_PF_RW RT_BIT_32(1)
5151	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5152	#define X86_TRAP_PF_US RT_BIT_32(2)
5153	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5154	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5155	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5156	#define X86_TRAP_PF_ID RT_BIT_32(4)
5157	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5158	#define X86_TRAP_PF_PK RT_BIT_32(5)
5159	/** @} */
5160
5161	#ifndef __ASSEMBLER__
5162
5163	# pragma pack(1)
5164	/**
5165	* 16-bit IDTR.
5166	*/
5167	typedef struct X86IDTR16
5168	{
5169	/** Offset. */
5170	uint16_t offSel;
5171	/** Selector. */
5172	uint16_t uSel;
5173	} X86IDTR16, *PX86IDTR16;
5174	# pragma pack()
5175
5176	# pragma pack(1)
5177	/**
5178	* 32-bit IDTR/GDTR.
5179	*/
5180	typedef struct X86XDTR32
5181	{
5182	/** Size of the descriptor table. */
5183	uint16_t cb;
5184	/** Address of the descriptor table. */
5185	# ifndef VBOX_FOR_DTRACE_LIB
5186	uint32_t uAddr;
5187	# else
5188	uint16_t au16Addr[2];
5189	# endif
5190	} X86XDTR32, *PX86XDTR32;
5191	# pragma pack()
5192
5193	# pragma pack(1)
5194	/**
5195	* 64-bit IDTR/GDTR.
5196	*/
5197	typedef struct X86XDTR64
5198	{
5199	/** Size of the descriptor table. */
5200	uint16_t cb;
5201	/** Address of the descriptor table. */
5202	# ifndef VBOX_FOR_DTRACE_LIB
5203	uint64_t uAddr;
5204	# else
5205	uint16_t au16Addr[4];
5206	# endif
5207	} X86XDTR64, *PX86XDTR64;
5208	# pragma pack()
5209
5210	#endif /* !__ASSEMBLER__ */
5211
5212
5213	/** @name ModR/M
5214	* @{ */
5215	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5216	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5217	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5218	#define X86_MODRM_REG_SHIFT 3
5219	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5220	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5221	#define X86_MODRM_MOD_SHIFT 6
5222
5223	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5224	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5225	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5226	#define X86_MOD_REG 3 /*< Registers. /
5227
5228	#ifndef VBOX_FOR_DTRACE_LIB
5229	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5230	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5231	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5232	/** @def X86_MODRM_MAKE
5233	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5234	* @param a_Reg The register value (0..7).
5235	* @param a_RegMem The register or memory value (0..7). */
5236	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5237	#endif
5238
5239	/** @} */
5240
5241	/** @name SIB
5242	* @{ */
5243	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5244	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5245	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5246	#define X86_SIB_INDEX_SHIFT 3
5247	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5248	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5249	#define X86_SIB_SCALE_SHIFT 6
5250	#ifndef VBOX_FOR_DTRACE_LIB
5251	/** @def X86_SIB_MAKE
5252	* @param a_BaseReg The base register value (0..7).
5253	* @param a_IndexReg The index register value (0..7).
5254	* @param a_Scale The left shift (0..3) to be applied to the index
5255	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5256	* */
5257	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5258	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5259
5260	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5261	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5262	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5263	#endif
5264	/** @} */
5265
5266	/** @name General register indexes.
5267	* @{ */
5268	#define X86_GREG_xAX 0
5269	#define X86_GREG_xCX 1
5270	#define X86_GREG_xDX 2
5271	#define X86_GREG_xBX 3
5272	#define X86_GREG_xSP 4
5273	#define X86_GREG_xBP 5
5274	#define X86_GREG_xSI 6
5275	#define X86_GREG_xDI 7
5276	#define X86_GREG_x8 8
5277	#define X86_GREG_x9 9
5278	#define X86_GREG_x10 10
5279	#define X86_GREG_x11 11
5280	#define X86_GREG_x12 12
5281	#define X86_GREG_x13 13
5282	#define X86_GREG_x14 14
5283	#define X86_GREG_x15 15
5284	/** @} */
5285	/** General register count. */
5286	#define X86_GREG_COUNT 16
5287
5288	/** @name X86_SREG_XXX - Segment register indexes.
5289	* @{ */
5290	#define X86_SREG_ES 0
5291	#define X86_SREG_CS 1
5292	#define X86_SREG_SS 2
5293	#define X86_SREG_DS 3
5294	#define X86_SREG_FS 4
5295	#define X86_SREG_GS 5
5296	/** @} */
5297	/** Segment register count. */
5298	#define X86_SREG_COUNT 6
5299
5300
5301	/** @name X86_OP_XXX - Prefixes
5302	* @{ */
5303	#define X86_OP_PRF_CS UINT8_C(0x2e)
5304	#define X86_OP_PRF_SS UINT8_C(0x36)
5305	#define X86_OP_PRF_DS UINT8_C(0x3e)
5306	#define X86_OP_PRF_ES UINT8_C(0x26)
5307	#define X86_OP_PRF_FS UINT8_C(0x64)
5308	#define X86_OP_PRF_GS UINT8_C(0x65)
5309	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5310	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5311	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5312	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5313	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5314	#define X86_OP_REX UINT8_C(0x40)
5315	#define X86_OP_REX_B UINT8_C(0x41)
5316	#define X86_OP_REX_X UINT8_C(0x42)
5317	#define X86_OP_REX_R UINT8_C(0x44)
5318	#define X86_OP_REX_W UINT8_C(0x48)
5319	#define X86_OP_VEX3 UINT8_C(0xc4)
5320	#define X86_OP_VEX2 UINT8_C(0xc5)
5321	/** @} */
5322
5323	/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5324	* @{ */
5325	#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5326	# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5327	# define X86_OP_VEX2_BYTE1_P_066H 1
5328	# define X86_OP_VEX2_BYTE1_P_0F3H 2
5329	# define X86_OP_VEX2_BYTE1_P_0F2H 3
5330	#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5331	#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5332	#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5333	#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5334	#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5335
5336	#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5337	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5338	\| (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5339	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5340	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5341
5342	#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5343	( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5344	\| (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5345	\| ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5346	\| ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5347	/** @} */
5348
5349	/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5350	* @{ */
5351	#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5352	#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5353	#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5354	#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5355	#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5356	( (uint8_t)(a_idxMap) \
5357	\| ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5358	\| ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5359	\| ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5360
5361	#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5362	# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5363	# define X86_OP_VEX3_BYTE2_P_066H 1
5364	# define X86_OP_VEX3_BYTE2_P_0F3H 2
5365	# define X86_OP_VEX3_BYTE2_P_0F2H 3
5366	#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5367	#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5368	#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5369	#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5370	#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5371
5372	/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5373	* shifting. */
5374	#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5375	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5376	\| ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5377	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5378	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5379
5380	#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5381	( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5382	\| (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5383	\| ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5384	\| ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5385	/** @} */
5386
5387	/** @} */
5388
5389	#endif /* !IPRT_INCLUDED_x86_h */
5390

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source: vbox/trunk/include/iprt/x86.h@ 107729

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