x86.h@ 103224

Last change on this file since 103224 was 103002, checked in by vboxsync, 9 months ago
iprt/x86.h: Made this header usable with the assembler on darwin/arm64. bugref:10376
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 196.3 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# ifndef __ASSEMBLER__
46	# include <iprt/types.h>
47	# include <iprt/assert.h>
48	# else
49	# include <iprt/stdint.h>
50	# include <iprt/assertcompile.h>
51	# endif
52	#else
53	# pragma D depends_on library vbox-types.d
54	#endif
55
56	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57	* defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58	#ifdef RT_OS_SOLARIS
59	# undef CS
60	# undef DS
61	# undef MSR_IA32_FLUSH_CMD
62	# undef MSR_AMD_VIRT_SPEC_CTL
63	#endif
64
65	/** @defgroup grp_rt_x86 x86 Types and Definitions
66	* @ingroup grp_rt
67	* @{
68	*/
69
70	#ifndef __ASSEMBLER__
71
72	# ifndef VBOX_FOR_DTRACE_LIB
73	/**
74	* EFLAGS Bits.
75	*/
76	typedef struct X86EFLAGSBITS
77	{
78	/** Bit 0 - CF - Carry flag - Status flag. */
79	unsigned u1CF : 1;
80	/** Bit 1 - 1 - Reserved flag. */
81	unsigned u1Reserved0 : 1;
82	/** Bit 2 - PF - Parity flag - Status flag. */
83	unsigned u1PF : 1;
84	/** Bit 3 - 0 - Reserved flag. */
85	unsigned u1Reserved1 : 1;
86	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87	unsigned u1AF : 1;
88	/** Bit 5 - 0 - Reserved flag. */
89	unsigned u1Reserved2 : 1;
90	/** Bit 6 - ZF - Zero flag - Status flag. */
91	unsigned u1ZF : 1;
92	/** Bit 7 - SF - Signed flag - Status flag. */
93	unsigned u1SF : 1;
94	/** Bit 8 - TF - Trap flag - System flag. */
95	unsigned u1TF : 1;
96	/** Bit 9 - IF - Interrupt flag - System flag. */
97	unsigned u1IF : 1;
98	/** Bit 10 - DF - Direction flag - Control flag. */
99	unsigned u1DF : 1;
100	/** Bit 11 - OF - Overflow flag - Status flag. */
101	unsigned u1OF : 1;
102	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103	unsigned u2IOPL : 2;
104	/** Bit 14 - NT - Nested task flag - System flag. */
105	unsigned u1NT : 1;
106	/** Bit 15 - 0 - Reserved flag. */
107	unsigned u1Reserved3 : 1;
108	/** Bit 16 - RF - Resume flag - System flag. */
109	unsigned u1RF : 1;
110	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
111	unsigned u1VM : 1;
112	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113	unsigned u1AC : 1;
114	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115	unsigned u1VIF : 1;
116	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117	unsigned u1VIP : 1;
118	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119	unsigned u1ID : 1;
120	/** Bit 22-31 - 0 - Reserved flag. */
121	unsigned u10Reserved4 : 10;
122	} X86EFLAGSBITS;
123	/** Pointer to EFLAGS bits. */
124	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125	/** Pointer to const EFLAGS bits. */
126	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127	# endif /* !VBOX_FOR_DTRACE_LIB */
128
129	/**
130	* EFLAGS.
131	*/
132	typedef union X86EFLAGS
133	{
134	/** The plain unsigned view. */
135	uint32_t u;
136	# ifndef VBOX_FOR_DTRACE_LIB
137	/** The bitfield view. */
138	X86EFLAGSBITS Bits;
139	# endif
140	/** The 8-bit view. */
141	uint8_t au8[4];
142	/** The 16-bit view. */
143	uint16_t au16[2];
144	/** The 32-bit view. */
145	uint32_t au32[1];
146	/** The 32-bit view. */
147	uint32_t u32;
148	} X86EFLAGS;
149	/** Pointer to EFLAGS. */
150	typedef X86EFLAGS *PX86EFLAGS;
151	/** Pointer to const EFLAGS. */
152	typedef const X86EFLAGS *PCX86EFLAGS;
153
154	/**
155	* RFLAGS (32 upper bits are reserved).
156	*/
157	typedef union X86RFLAGS
158	{
159	/** The plain unsigned view. */
160	uint64_t u;
161	# ifndef VBOX_FOR_DTRACE_LIB
162	/** The bitfield view. */
163	X86EFLAGSBITS Bits;
164	# endif
165	/** The 8-bit view. */
166	uint8_t au8[8];
167	/** The 16-bit view. */
168	uint16_t au16[4];
169	/** The 32-bit view. */
170	uint32_t au32[2];
171	/** The 64-bit view. */
172	uint64_t au64[1];
173	/** The 64-bit view. */
174	uint64_t u64;
175	} X86RFLAGS;
176	/** Pointer to RFLAGS. */
177	typedef X86RFLAGS *PX86RFLAGS;
178	/** Pointer to const RFLAGS. */
179	typedef const X86RFLAGS *PCX86RFLAGS;
180
181	#endif /* !__ASSEMBLER__ */
182
183
184	/** @name EFLAGS
185	* @{
186	*/
187	/** Bit 0 - CF - Carry flag - Status flag. */
188	#define X86_EFL_CF RT_BIT_32(0)
189	#define X86_EFL_CF_BIT 0
190	/** Bit 1 - Reserved, reads as 1. */
191	#define X86_EFL_1 RT_BIT_32(1)
192	/** Bit 2 - PF - Parity flag - Status flag. */
193	#define X86_EFL_PF RT_BIT_32(2)
194	#define X86_EFL_PF_BIT 2
195	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
196	#define X86_EFL_AF RT_BIT_32(4)
197	#define X86_EFL_AF_BIT 4
198	/** Bit 6 - ZF - Zero flag - Status flag. */
199	#define X86_EFL_ZF RT_BIT_32(6)
200	#define X86_EFL_ZF_BIT 6
201	/** Bit 7 - SF - Signed flag - Status flag. */
202	#define X86_EFL_SF RT_BIT_32(7)
203	#define X86_EFL_SF_BIT 7
204	/** Bit 8 - TF - Trap flag - System flag. */
205	#define X86_EFL_TF RT_BIT_32(8)
206	#define X86_EFL_TF_BIT 8
207	/** Bit 9 - IF - Interrupt flag - System flag. */
208	#define X86_EFL_IF RT_BIT_32(9)
209	#define X86_EFL_IF_BIT 9
210	/** Bit 10 - DF - Direction flag - Control flag. */
211	#define X86_EFL_DF RT_BIT_32(10)
212	#define X86_EFL_DF_BIT 10
213	/** Bit 11 - OF - Overflow flag - Status flag. */
214	#define X86_EFL_OF RT_BIT_32(11)
215	#define X86_EFL_OF_BIT 11
216	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
217	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
218	/** Bit 14 - NT - Nested task flag - System flag. */
219	#define X86_EFL_NT RT_BIT_32(14)
220	#define X86_EFL_NT_BIT 14
221	/** Bit 16 - RF - Resume flag - System flag. */
222	#define X86_EFL_RF RT_BIT_32(16)
223	#define X86_EFL_RF_BIT 16
224	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
225	#define X86_EFL_VM RT_BIT_32(17)
226	#define X86_EFL_VM_BIT 17
227	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
228	#define X86_EFL_AC RT_BIT_32(18)
229	#define X86_EFL_AC_BIT 18
230	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
231	#define X86_EFL_VIF RT_BIT_32(19)
232	#define X86_EFL_VIF_BIT 19
233	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
234	#define X86_EFL_VIP RT_BIT_32(20)
235	#define X86_EFL_VIP_BIT 20
236	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
237	#define X86_EFL_ID RT_BIT_32(21)
238	#define X86_EFL_ID_BIT 21
239	/** All live bits. */
240	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
241	/** Read as 1 bits. */
242	#define X86_EFL_RA1_MASK RT_BIT_32(1)
243	/** Read as 0 bits, excluding bits 31:22.
244	* Bits 3, 5, 15, and 22 thru 31. */
245	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
246	/** Read as 0 bits, excluding bits 31:22.
247	* Bits 3, 5 and 15. */
248	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
249	/** IOPL shift. */
250	#define X86_EFL_IOPL_SHIFT 12
251	/** The IOPL level from the flags. */
252	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
253	/** Bits restored by popf */
254	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
255	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
256	/** Bits restored by popf */
257	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
258	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
259	/** The status bits commonly updated by arithmetic instructions. */
260	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
261	/** @} */
262
263
264	#ifndef __ASSEMBLER__
265
266	/** CPUID Feature information - ECX.
267	* CPUID query with EAX=1.
268	*/
269	# ifndef VBOX_FOR_DTRACE_LIB
270	typedef struct X86CPUIDFEATECX
271	{
272	/** Bit 0 - SSE3 - Supports SSE3 or not. */
273	unsigned u1SSE3 : 1;
274	/** Bit 1 - PCLMULQDQ. */
275	unsigned u1PCLMULQDQ : 1;
276	/** Bit 2 - DS Area 64-bit layout. */
277	unsigned u1DTE64 : 1;
278	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
279	unsigned u1Monitor : 1;
280	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
281	unsigned u1CPLDS : 1;
282	/** Bit 5 - VMX - Virtual Machine Technology. */
283	unsigned u1VMX : 1;
284	/** Bit 6 - SMX: Safer Mode Extensions. */
285	unsigned u1SMX : 1;
286	/** Bit 7 - EST - Enh. SpeedStep Tech. */
287	unsigned u1EST : 1;
288	/** Bit 8 - TM2 - Terminal Monitor 2. */
289	unsigned u1TM2 : 1;
290	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
291	unsigned u1SSSE3 : 1;
292	/** Bit 10 - CNTX-ID - L1 Context ID. */
293	unsigned u1CNTXID : 1;
294	/** Bit 11 - Reserved. */
295	unsigned u1Reserved1 : 1;
296	/** Bit 12 - FMA. */
297	unsigned u1FMA : 1;
298	/** Bit 13 - CX16 - CMPXCHG16B. */
299	unsigned u1CX16 : 1;
300	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
301	unsigned u1TPRUpdate : 1;
302	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
303	unsigned u1PDCM : 1;
304	/** Bit 16 - Reserved. */
305	unsigned u1Reserved2 : 1;
306	/** Bit 17 - PCID - Process-context identifiers. */
307	unsigned u1PCID : 1;
308	/** Bit 18 - Direct Cache Access. */
309	unsigned u1DCA : 1;
310	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
311	unsigned u1SSE4_1 : 1;
312	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
313	unsigned u1SSE4_2 : 1;
314	/** Bit 21 - x2APIC. */
315	unsigned u1x2APIC : 1;
316	/** Bit 22 - MOVBE - Supports MOVBE. */
317	unsigned u1MOVBE : 1;
318	/** Bit 23 - POPCNT - Supports POPCNT. */
319	unsigned u1POPCNT : 1;
320	/** Bit 24 - TSC-Deadline. */
321	unsigned u1TSCDEADLINE : 1;
322	/** Bit 25 - AES. */
323	unsigned u1AES : 1;
324	/** Bit 26 - XSAVE - Supports XSAVE. */
325	unsigned u1XSAVE : 1;
326	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
327	unsigned u1OSXSAVE : 1;
328	/** Bit 28 - AVX - Supports AVX instruction extensions. */
329	unsigned u1AVX : 1;
330	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
331	unsigned u1F16C : 1;
332	/** Bit 30 - RDRAND - Supports RDRAND. */
333	unsigned u1RDRAND : 1;
334	/** Bit 31 - Hypervisor present (we're a guest). */
335	unsigned u1HVP : 1;
336	} X86CPUIDFEATECX;
337	# else /* VBOX_FOR_DTRACE_LIB */
338	typedef uint32_t X86CPUIDFEATECX;
339	# endif /* VBOX_FOR_DTRACE_LIB */
340	/** Pointer to CPUID Feature Information - ECX. */
341	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
342	/** Pointer to const CPUID Feature Information - ECX. */
343	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
344
345
346	/** CPUID Feature Information - EDX.
347	* CPUID query with EAX=1.
348	*/
349	# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
350	typedef struct X86CPUIDFEATEDX
351	{
352	/** Bit 0 - FPU - x87 FPU on Chip. */
353	unsigned u1FPU : 1;
354	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
355	unsigned u1VME : 1;
356	/** Bit 2 - DE - Debugging extensions. */
357	unsigned u1DE : 1;
358	/** Bit 3 - PSE - Page Size Extension. */
359	unsigned u1PSE : 1;
360	/** Bit 4 - TSC - Time Stamp Counter. */
361	unsigned u1TSC : 1;
362	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
363	unsigned u1MSR : 1;
364	/** Bit 6 - PAE - Physical Address Extension. */
365	unsigned u1PAE : 1;
366	/** Bit 7 - MCE - Machine Check Exception. */
367	unsigned u1MCE : 1;
368	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
369	unsigned u1CX8 : 1;
370	/** Bit 9 - APIC - APIC On-Chip. */
371	unsigned u1APIC : 1;
372	/** Bit 10 - Reserved. */
373	unsigned u1Reserved1 : 1;
374	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
375	unsigned u1SEP : 1;
376	/** Bit 12 - MTRR - Memory Type Range Registers. */
377	unsigned u1MTRR : 1;
378	/** Bit 13 - PGE - PTE Global Bit. */
379	unsigned u1PGE : 1;
380	/** Bit 14 - MCA - Machine Check Architecture. */
381	unsigned u1MCA : 1;
382	/** Bit 15 - CMOV - Conditional Move Instructions. */
383	unsigned u1CMOV : 1;
384	/** Bit 16 - PAT - Page Attribute Table. */
385	unsigned u1PAT : 1;
386	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
387	unsigned u1PSE36 : 1;
388	/** Bit 18 - PSN - Processor Serial Number. */
389	unsigned u1PSN : 1;
390	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
391	unsigned u1CLFSH : 1;
392	/** Bit 20 - Reserved. */
393	unsigned u1Reserved2 : 1;
394	/** Bit 21 - DS - Debug Store. */
395	unsigned u1DS : 1;
396	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
397	unsigned u1ACPI : 1;
398	/** Bit 23 - MMX - Intel MMX 'Technology'. */
399	unsigned u1MMX : 1;
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	unsigned u1FXSR : 1;
402	/** Bit 25 - SSE - SSE Support. */
403	unsigned u1SSE : 1;
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	unsigned u1SSE2 : 1;
406	/** Bit 27 - SS - Self Snoop. */
407	unsigned u1SS : 1;
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	unsigned u1HTT : 1;
410	/** Bit 29 - TM - Thermal Monitor. */
411	unsigned u1TM : 1;
412	/** Bit 30 - Reserved - . */
413	unsigned u1Reserved3 : 1;
414	/** Bit 31 - PBE - Pending Break Enabled. */
415	unsigned u1PBE : 1;
416	} X86CPUIDFEATEDX;
417	# else /* VBOX_FOR_DTRACE_LIB */
418	typedef uint32_t X86CPUIDFEATEDX;
419	# endif /* VBOX_FOR_DTRACE_LIB */
420	/** Pointer to CPUID Feature Information - EDX. */
421	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
422	/** Pointer to const CPUID Feature Information - EDX. */
423	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
424
425	#endif /* !__ASSEMBLER__ */
426
427
428	/** @name CPUID Vendor information.
429	* CPUID query with EAX=0.
430	* @{
431	*/
432	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
433	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
434	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
435
436	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
437	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
438	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
439
440	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
441	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
442	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
443
444	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
445	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
446	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
447
448	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
449	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
450	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
451	/** @} */
452
453
454	/** @name CPUID Feature information.
455	* CPUID query with EAX=1.
456	* @{
457	*/
458	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
459	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
460	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
461	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
462	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
463	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
464	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
465	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
466	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
467	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
468	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
469	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
470	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
471	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
472	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
473	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
474	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
475	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
476	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
477	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
478	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
479	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
480	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
481	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
482	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
483	/** ECX Bit 12 - FMA. */
484	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
485	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
486	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
487	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
488	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
489	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
490	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
491	/** ECX Bit 17 - PCID - Process-context identifiers. */
492	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
493	/** ECX Bit 18 - DCA - Direct Cache Access. */
494	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
495	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
496	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
497	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
498	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
499	/** ECX Bit 21 - x2APIC support. */
500	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
501	/** ECX Bit 22 - MOVBE instruction. */
502	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
503	/** ECX Bit 23 - POPCNT instruction. */
504	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
505	/** ECX Bir 24 - TSC-Deadline. */
506	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
507	/** ECX Bit 25 - AES instructions. */
508	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
509	/** ECX Bit 26 - XSAVE instruction. */
510	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
511	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
512	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
513	/** ECX Bit 28 - AVX. */
514	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
515	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
516	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
517	/** ECX Bit 30 - RDRAND instruction. */
518	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
519	/** ECX Bit 31 - Hypervisor Present (software only). */
520	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
521
522
523	/** Bit 0 - FPU - x87 FPU on Chip. */
524	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
525	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
526	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
527	/** Bit 2 - DE - Debugging extensions. */
528	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
529	/** Bit 3 - PSE - Page Size Extension. */
530	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
531	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
532	/** Bit 4 - TSC - Time Stamp Counter. */
533	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
534	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
535	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
536	/** Bit 6 - PAE - Physical Address Extension. */
537	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
538	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
539	/** Bit 7 - MCE - Machine Check Exception. */
540	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
541	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
542	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
543	/** Bit 9 - APIC - APIC On-Chip. */
544	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
545	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
546	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
547	/** Bit 12 - MTRR - Memory Type Range Registers. */
548	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
549	/** Bit 13 - PGE - PTE Global Bit. */
550	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
551	/** Bit 14 - MCA - Machine Check Architecture. */
552	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
553	/** Bit 15 - CMOV - Conditional Move Instructions. */
554	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
555	/** Bit 16 - PAT - Page Attribute Table. */
556	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
557	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
558	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
559	/** Bit 18 - PSN - Processor Serial Number. */
560	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
561	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
562	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
563	/** Bit 21 - DS - Debug Store. */
564	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
565	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
566	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
567	/** Bit 23 - MMX - Intel MMX Technology. */
568	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
569	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
570	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
571	/** Bit 25 - SSE - SSE Support. */
572	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
573	/** Bit 26 - SSE2 - SSE2 Support. */
574	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
575	/** Bit 27 - SS - Self Snoop. */
576	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
577	/** Bit 28 - HTT - Hyper-Threading Technology. */
578	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
579	/** Bit 29 - TM - Therm. Monitor. */
580	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
581	/** Bit 31 - PBE - Pending Break Enabled. */
582	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
583	/** @} */
584
585	/** @name CPUID mwait/monitor information.
586	* CPUID query with EAX=5.
587	* @{
588	*/
589	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
590	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
591	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
592	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
593	/** @} */
594
595
596	/** @name CPUID Thermal and Power Management information.
597	* Generally Intel only unless noted otherwise.
598	* CPUID query with EAX=5. @{
599	*/
600	/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
601	#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
602	/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
603	#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
604	/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
605	#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
606	/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
607	#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
608	/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
609	#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
610	/** EAX Bit 6 - PTM - Package Thermal Management supported. */
611	#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
612	/** EAX Bit 7 - HWP - HWP base MSRs supported. */
613	#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
614	/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
615	#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
616	/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
617	#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
618	/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
619	#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
620	/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
621	#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
622	/** EAX Bit 13 - HDC - HDC base MSRs supported. */
623	#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
624	/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
625	#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
626	/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
627	#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
628	/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
629	#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
630	/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
631	#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
632
633	/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
634	#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
635	/** @} */
636
637
638	/** @name CPUID Structured Extended Feature information.
639	* CPUID query with EAX=7.
640	* @{
641	*/
642	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
643	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
644	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
645	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
646	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
647	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
648	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
649	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
650	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
651	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
652	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
653	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
654	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
655	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
656	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
657	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
658	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
659	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
660	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
661	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
662	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
663	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
664	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
665	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
666	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
667	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
668	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
669	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
670	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
671	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
672	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
673	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
674	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
675	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
676	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
677	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
678	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
679	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
680	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
681	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
682	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
683	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
684	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
685	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
686	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
687	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
688	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
689	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
690	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
691	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
692	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
693	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
694
695	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
696	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
697	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
698	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
699	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
700	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
701	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
702	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
703	/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
704	#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
705	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
706	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
707	/** ECX Bit 22 - RDPID - Support pread process ID. */
708	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
709	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
710	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
711
712	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
713	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
714	/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
715	#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
716	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
717	* IBPB command in IA32_PRED_CMD. */
718	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
719	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
720	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
721	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
722	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
723	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
724	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
725	/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
726	#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
727	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
728	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
729
730	/** @} */
731
732
733	/** @name CPUID Extended Feature information.
734	* CPUID query with EAX=0x80000001.
735	* @{
736	*/
737	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
738	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
739
740	/** EDX Bit 11 - SYSCALL/SYSRET. */
741	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
742	/** EDX Bit 20 - No-Execute/Execute-Disable. */
743	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
744	/** EDX Bit 26 - 1 GB large page. */
745	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
746	/** EDX Bit 27 - RDTSCP. */
747	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
748	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
749	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
750	/** @}*/
751
752	/** @name CPUID AMD Feature information.
753	* CPUID query with EAX=0x80000001.
754	* @{
755	*/
756	/** Bit 0 - FPU - x87 FPU on Chip. */
757	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
758	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
759	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
760	/** Bit 2 - DE - Debugging extensions. */
761	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
762	/** Bit 3 - PSE - Page Size Extension. */
763	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
764	/** Bit 4 - TSC - Time Stamp Counter. */
765	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
766	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
767	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
768	/** Bit 6 - PAE - Physical Address Extension. */
769	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
770	/** Bit 7 - MCE - Machine Check Exception. */
771	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
772	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
773	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
774	/** Bit 9 - APIC - APIC On-Chip. */
775	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
776	/** Bit 12 - MTRR - Memory Type Range Registers. */
777	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
778	/** Bit 13 - PGE - PTE Global Bit. */
779	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
780	/** Bit 14 - MCA - Machine Check Architecture. */
781	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
782	/** Bit 15 - CMOV - Conditional Move Instructions. */
783	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
784	/** Bit 16 - PAT - Page Attribute Table. */
785	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
786	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
787	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
788	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
789	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
790	/** Bit 23 - MMX - Intel MMX Technology. */
791	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
792	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
793	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
794	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
795	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
796	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
797	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
798	/** Bit 31 - 3DNOW - AMD 3DNow. */
799	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
800
801	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
802	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
803	/** Bit 2 - SVM - AMD VM extensions. */
804	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
805	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
806	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
807	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
808	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
809	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
810	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
811	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
812	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
813	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
814	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
815	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
816	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
817	/** Bit 9 - OSVW - AMD OS visible workaround. */
818	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
819	/** Bit 10 - IBS - Instruct based sampling. */
820	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
821	/** Bit 11 - XOP - Extended operation support (see APM6). */
822	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
823	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
824	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
825	/** Bit 13 - WDT - AMD Watchdog timer support. */
826	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
827	/** Bit 15 - LWP - Lightweight profiling support. */
828	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
829	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
830	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
831	/** Bit 19 - NodeId - Indicates support for
832	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
833	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
834	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
835	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
836	/** Bit 22 - TopologyExtensions - . */
837	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
838	/** @} */
839
840
841	/** @name CPUID AMD Feature information.
842	* CPUID query with EAX=0x80000007.
843	* @{
844	*/
845	/** Bit 0 - TS - Temperature Sensor. */
846	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
847	/** Bit 1 - FID - Frequency ID Control. */
848	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
849	/** Bit 2 - VID - Voltage ID Control. */
850	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
851	/** Bit 3 - TTP - THERMTRIP. */
852	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
853	/** Bit 4 - TM - Hardware Thermal Control. */
854	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
855	/** Bit 5 - STC - Software Thermal Control. */
856	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
857	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
858	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
859	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
860	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
861	/** Bit 8 - TSCINVAR - TSC Invariant. */
862	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
863	/** Bit 9 - CPB - TSC Invariant. */
864	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
865	/** Bit 10 - EffFreqRO - MPERF/APERF. */
866	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
867	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
868	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
869	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
870	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
871	/** @} */
872
873
874	/** @name CPUID AMD extended feature extensions ID (EBX).
875	* CPUID query with EAX=0x80000008.
876	* @{
877	*/
878	/** Bit 0 - CLZERO - Clear zero instruction. */
879	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
880	/** Bit 1 - IRPerf - Instructions retired count support. */
881	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
882	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
883	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
884	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
885	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
886	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
887	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
888	/* AMD pipeline length: 9 feature bits ;-) */
889	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
890	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
891	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
892	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
893	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
894	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
895	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
896	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
897	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
898	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
899	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
900	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
901	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
902	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
903	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
904	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
905	/** Bit 26 - Speculative Store Bypass Disable not required. */
906	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
907	/** @} */
908
909
910	/** @name CPUID AMD SVM Feature information.
911	* CPUID query with EAX=0x8000000a.
912	* @{
913	*/
914	/** Bit 0 - NP - Nested Paging supported. */
915	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
916	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
917	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
918	/** Bit 2 - SVML - SVM locking bit supported. */
919	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
920	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
921	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
922	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
923	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
924	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
925	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
926	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
927	* VMCB.TLB_Control is supported. */
928	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
929	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
930	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
931	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
932	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
933	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
934	* intercept filter cycle count threshold. */
935	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
936	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
937	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
938	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
939	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
940	/** Bit 16 - VGIF - Supports virtualized GIF. */
941	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
942	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
943	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
944	/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
945	* mode. */
946	#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
947	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
948	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
949	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
950	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
951	/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
952	#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
953	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
954	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
955	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
956	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
957	/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
958	#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
959	/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
960	#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
961	/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
962	#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
963	/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
964	#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
965	/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
966	#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
967
968	/** @} */
969
970
971	/** @name CR0
972	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
973	* reserved flags.
974	* @{ */
975	/** Bit 0 - PE - Protection Enabled */
976	#define X86_CR0_PE RT_BIT_32(0)
977	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
978	/** Bit 1 - MP - Monitor Coprocessor */
979	#define X86_CR0_MP RT_BIT_32(1)
980	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
981	/** Bit 2 - EM - Emulation. */
982	#define X86_CR0_EM RT_BIT_32(2)
983	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
984	/** Bit 3 - TS - Task Switch. */
985	#define X86_CR0_TS RT_BIT_32(3)
986	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
987	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
988	#define X86_CR0_ET RT_BIT_32(4)
989	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
990	/** Bit 5 - NE - Numeric error (486+). */
991	#define X86_CR0_NE RT_BIT_32(5)
992	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
993	/** Bit 16 - WP - Write Protect (486+). */
994	#define X86_CR0_WP RT_BIT_32(16)
995	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
996	/** Bit 18 - AM - Alignment Mask (486+). */
997	#define X86_CR0_AM RT_BIT_32(18)
998	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
999	/** Bit 29 - NW - Not Write-though (486+). */
1000	#define X86_CR0_NW RT_BIT_32(29)
1001	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1002	/** Bit 30 - WP - Cache Disable (486+). */
1003	#define X86_CR0_CD RT_BIT_32(30)
1004	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1005	/** Bit 31 - PG - Paging. */
1006	#define X86_CR0_PG RT_BIT_32(31)
1007	#define X86_CR0_PAGING RT_BIT_32(31)
1008	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
1009	/** @} */
1010
1011
1012	/** @name CR3
1013	* @{ */
1014	/** Bit 3 - PWT - Page-level Writes Transparent. */
1015	#define X86_CR3_PWT RT_BIT_32(3)
1016	/** Bit 4 - PCD - Page-level Cache Disable. */
1017	#define X86_CR3_PCD RT_BIT_32(4)
1018	/** Bits 12-31 - - Page directory page number. */
1019	#define X86_CR3_PAGE_MASK (0xfffff000)
1020	/** Bits 5-31 - - PAE Page directory page number. */
1021	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1022	/** Bits 12-51 - - AMD64 PML4 page number.
1023	* @note This is a maxed out mask, the actual acceptable CR3 value can
1024	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1025	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1026	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1027	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1028	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1029	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1030	/** @} */
1031
1032
1033	/** @name CR4
1034	* @{ */
1035	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1036	#define X86_CR4_VME RT_BIT_32(0)
1037	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1038	#define X86_CR4_PVI RT_BIT_32(1)
1039	/** Bit 2 - TSD - Time Stamp Disable. */
1040	#define X86_CR4_TSD RT_BIT_32(2)
1041	/** Bit 3 - DE - Debugging Extensions. */
1042	#define X86_CR4_DE RT_BIT_32(3)
1043	/** Bit 4 - PSE - Page Size Extension. */
1044	#define X86_CR4_PSE RT_BIT_32(4)
1045	/** Bit 5 - PAE - Physical Address Extension. */
1046	#define X86_CR4_PAE RT_BIT_32(5)
1047	/** Bit 6 - MCE - Machine-Check Enable. */
1048	#define X86_CR4_MCE RT_BIT_32(6)
1049	/** Bit 7 - PGE - Page Global Enable. */
1050	#define X86_CR4_PGE RT_BIT_32(7)
1051	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1052	#define X86_CR4_PCE RT_BIT_32(8)
1053	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1054	#define X86_CR4_OSFXSR RT_BIT_32(9)
1055	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1056	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1057	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1058	#define X86_CR4_UMIP RT_BIT_32(11)
1059	/** Bit 13 - VMXE - VMX mode is enabled. */
1060	#define X86_CR4_VMXE RT_BIT_32(13)
1061	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1062	#define X86_CR4_SMXE RT_BIT_32(14)
1063	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1064	#define X86_CR4_FSGSBASE RT_BIT_32(16)
1065	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1066	#define X86_CR4_PCIDE RT_BIT_32(17)
1067	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1068	* extended states. */
1069	#define X86_CR4_OSXSAVE RT_BIT_32(18)
1070	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1071	#define X86_CR4_SMEP RT_BIT_32(20)
1072	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1073	#define X86_CR4_SMAP RT_BIT_32(21)
1074	/** Bit 22 - PKE - Protection Key Enable. */
1075	#define X86_CR4_PKE RT_BIT_32(22)
1076	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1077	#define X86_CR4_CET RT_BIT_32(23)
1078	/** @} */
1079
1080
1081	/** @name DR6
1082	* @{ */
1083	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1084	#define X86_DR6_B0 RT_BIT_32(0)
1085	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1086	#define X86_DR6_B1 RT_BIT_32(1)
1087	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1088	#define X86_DR6_B2 RT_BIT_32(2)
1089	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1090	#define X86_DR6_B3 RT_BIT_32(3)
1091	/** Mask of all the Bx bits. */
1092	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1093	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1094	#define X86_DR6_BD RT_BIT_32(13)
1095	/** Bit 14 - BS - Single step */
1096	#define X86_DR6_BS RT_BIT_32(14)
1097	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1098	#define X86_DR6_BT RT_BIT_32(15)
1099	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1100	#define X86_DR6_RTM RT_BIT_32(16)
1101	/** Value of DR6 after powerup/reset. */
1102	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1103	/** Bits which must be 1s in DR6. */
1104	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1105	/** Bits which must be 1s in DR6, when RTM is supported. */
1106	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1107	/** Bits which must be 0s in DR6. */
1108	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1109	/** Bits which must be 0s on writes to DR6. */
1110	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1111	/** @} */
1112
1113	/** Get the DR6.Bx bit for a the given breakpoint. */
1114	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1115
1116
1117	/** @name DR7
1118	* @{ */
1119	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1120	#define X86_DR7_L0 RT_BIT_32(0)
1121	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1122	#define X86_DR7_G0 RT_BIT_32(1)
1123	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1124	#define X86_DR7_L1 RT_BIT_32(2)
1125	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1126	#define X86_DR7_G1 RT_BIT_32(3)
1127	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1128	#define X86_DR7_L2 RT_BIT_32(4)
1129	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1130	#define X86_DR7_G2 RT_BIT_32(5)
1131	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1132	#define X86_DR7_L3 RT_BIT_32(6)
1133	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1134	#define X86_DR7_G3 RT_BIT_32(7)
1135	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1136	#define X86_DR7_LE RT_BIT_32(8)
1137	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1138	#define X86_DR7_GE RT_BIT_32(9)
1139
1140	/** L0, L1, L2, and L3. */
1141	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1142	/** L0, L1, L2, and L3. */
1143	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1144
1145	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1146	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1147	#define X86_DR7_RTM RT_BIT_32(11)
1148	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1149	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1150	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1151	* instruction is executed.
1152	* @see http://www.rcollins.org/secrets/DR7.html */
1153	#define X86_DR7_ICE_IR RT_BIT_32(12)
1154	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1155	* any DR register is accessed. */
1156	#define X86_DR7_GD RT_BIT_32(13)
1157	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1158	* Pentium. */
1159	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1160	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1161	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1162	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1163	#define X86_DR7_RW0_MASK (3 << 16)
1164	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1165	#define X86_DR7_LEN0_MASK (3 << 18)
1166	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1167	#define X86_DR7_RW1_MASK (3 << 20)
1168	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1169	#define X86_DR7_LEN1_MASK (3 << 22)
1170	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1171	#define X86_DR7_RW2_MASK (3 << 24)
1172	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1173	#define X86_DR7_LEN2_MASK (3 << 26)
1174	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1175	#define X86_DR7_RW3_MASK (3 << 28)
1176	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1177	#define X86_DR7_LEN3_MASK (3 << 30)
1178
1179	/** Bits which reads as 1s. */
1180	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1181	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1182	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1183	/** Bits which must be 0s when writing to DR7. */
1184	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1185
1186	/** Calcs the L bit of Nth breakpoint.
1187	* @param iBp The breakpoint number [0..3].
1188	*/
1189	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1190
1191	/** Calcs the G bit of Nth breakpoint.
1192	* @param iBp The breakpoint number [0..3].
1193	*/
1194	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1195
1196	/** Calcs the L and G bits of Nth breakpoint.
1197	* @param iBp The breakpoint number [0..3].
1198	*/
1199	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1200
1201	/** @name Read/Write values.
1202	* @{ */
1203	/** Break on instruction fetch only. */
1204	#define X86_DR7_RW_EO UINT32_C(0)
1205	/** Break on write only. */
1206	#define X86_DR7_RW_WO UINT32_C(1)
1207	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1208	#define X86_DR7_RW_IO UINT32_C(2)
1209	/** Break on read or write (but not instruction fetches). */
1210	#define X86_DR7_RW_RW UINT32_C(3)
1211	/** @} */
1212
1213	/** Shifts a X86_DR7_RW_* value to its right place.
1214	* @param iBp The breakpoint number [0..3].
1215	* @param fRw One of the X86_DR7_RW_* value.
1216	*/
1217	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1218
1219	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1220	* one of the X86_DR7_RW_XXX constants).
1221	*
1222	* @returns X86_DR7_RW_XXX
1223	* @param uDR7 DR7 value
1224	* @param iBp The breakpoint number [0..3].
1225	*/
1226	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1227
1228	/** R/W0, R/W1, R/W2, and R/W3. */
1229	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1230
1231	#ifndef VBOX_FOR_DTRACE_LIB
1232	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1233	* @note This does not check if it's enabled. */
1234	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1235	/** Checks if an instruction breakpoint is enabled and configured correctly.
1236	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1237	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1238	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1239	/** Checks if there are any instruction fetch breakpoint types configured in the
1240	* RW and LEN registers.
1241	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1242	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1243	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1244	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1245	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1246	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1247
1248	/** Checks if there are any I/O breakpoint types configured in the RW
1249	* registers. Does NOT check if these are enabled, sorry. */
1250	# define X86_DR7_ANY_RW_IO(uDR7) \
1251	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1252	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1253	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1254	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1255	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1256	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1257	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1258	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1259	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1260	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1261	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1262
1263	#endif /* !VBOX_FOR_DTRACE_LIB */
1264
1265	/** @name Length values.
1266	* @{ */
1267	#define X86_DR7_LEN_BYTE UINT32_C(0)
1268	#define X86_DR7_LEN_WORD UINT32_C(1)
1269	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1270	#define X86_DR7_LEN_DWORD UINT32_C(3)
1271	/** @} */
1272
1273	/** Shifts a X86_DR7_LEN_* value to its right place.
1274	* @param iBp The breakpoint number [0..3].
1275	* @param cb One of the X86_DR7_LEN_* values.
1276	*/
1277	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1278
1279	/** Fetch the breakpoint length bits from the DR7 value.
1280	* @param uDR7 DR7 value
1281	* @param iBp The breakpoint number [0..3].
1282	*/
1283	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1284
1285	/** Mask used to check if any breakpoints are enabled. */
1286	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1287
1288	/** LEN0, LEN1, LEN2, and LEN3. */
1289	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1290	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1291	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1292
1293	/** Value of DR7 after powerup/reset. */
1294	#define X86_DR7_INIT_VAL 0x400
1295	/** @} */
1296
1297
1298	/** @name Machine Specific Registers
1299	* @{
1300	*/
1301	/** Machine check address register (P5). */
1302	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1303	/** Machine check type register (P5). */
1304	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1305	/** Time Stamp Counter. */
1306	#define MSR_IA32_TSC 0x10
1307	#define MSR_IA32_CESR UINT32_C(0x00000011)
1308	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1309	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1310
1311	#define MSR_IA32_PLATFORM_ID 0x17
1312
1313	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1314	# define MSR_IA32_APICBASE 0x1b
1315	/** Local APIC enabled. */
1316	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1317	/** X2APIC enabled (requires the EN bit to be set). */
1318	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1319	/** The processor is the boot strap processor (BSP). */
1320	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1321	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1322	* width. */
1323	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1324	/** The default physical base address of the APIC. */
1325	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1326	/** Gets the physical base address from the MSR. */
1327	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1328	#endif
1329
1330	/** Memory Control (Intel-specific). */
1331	#define MSR_MEMORY_CTRL 0x33
1332	/** Memory Control - UC-store throttle. */
1333	#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1334	/** Memory Control - UC-lock disable. */
1335	#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1336	/** Memory Control - Split-lock disable. */
1337	#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1338
1339	/** Undocumented intel MSR for reporting thread and core counts.
1340	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1341	* first 16 bits is the thread count. The next 16 bits the core count, except
1342	* on Westmere where it seems it's only the next 4 bits for some reason. */
1343	#define MSR_CORE_THREAD_COUNT 0x35
1344
1345	/** CPU Feature control. */
1346	#define MSR_IA32_FEATURE_CONTROL 0x3A
1347	/** Feature control - Lock MSR from writes (R/W0). */
1348	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1349	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1350	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1351	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1352	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1353	/** Feature control - SENTER local functions enable (R/WL). */
1354	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1355	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1356	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1357	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1358	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1359	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1360	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1361	/** Feature control - SENTER global enable (R/WL). */
1362	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1363	/** Feature control - SGX launch control enable (R/WL). */
1364	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1365	/** Feature control - SGX global enable (R/WL). */
1366	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1367	/** Feature control - LMCE on (R/WL). */
1368	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1369
1370	/** Per-processor TSC adjust MSR. */
1371	#define MSR_IA32_TSC_ADJUST 0x3B
1372
1373	/** Spectre control register.
1374	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1375	#define MSR_IA32_SPEC_CTRL 0x48
1376	/** IBRS - Indirect branch restricted speculation. */
1377	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1378	/** STIBP - Single thread indirect branch predictors. */
1379	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1380	/** SSBD - Speculative Store Bypass Disable. */
1381	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1382
1383	/** Prediction command register.
1384	* Write only, logical processor scope, no state since write only. */
1385	#define MSR_IA32_PRED_CMD 0x49
1386	/** IBPB - Indirect branch prediction barrie when written as 1. */
1387	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1388
1389	/** BIOS update trigger (microcode update). */
1390	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1391
1392	/** BIOS update signature (microcode). */
1393	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1394
1395	/** SMM monitor control. */
1396	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1397	/** SMM control - Valid. */
1398	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1399	/** SMM control - VMXOFF unblocks SMI. */
1400	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1401	/** SMM control - MSEG base physical address. */
1402	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1403
1404	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1405	#define MSR_IA32_SMBASE 0x9E
1406
1407	/** General performance counter no. 0. */
1408	#define MSR_IA32_PMC0 0xC1
1409	/** General performance counter no. 1. */
1410	#define MSR_IA32_PMC1 0xC2
1411	/** General performance counter no. 2. */
1412	#define MSR_IA32_PMC2 0xC3
1413	/** General performance counter no. 3. */
1414	#define MSR_IA32_PMC3 0xC4
1415	/** General performance counter no. 4. */
1416	#define MSR_IA32_PMC4 0xC5
1417	/** General performance counter no. 5. */
1418	#define MSR_IA32_PMC5 0xC6
1419	/** General performance counter no. 6. */
1420	#define MSR_IA32_PMC6 0xC7
1421	/** General performance counter no. 7. */
1422	#define MSR_IA32_PMC7 0xC8
1423
1424	/** Nehalem power control. */
1425	#define MSR_IA32_PLATFORM_INFO 0xCE
1426
1427	/** Core Capabilities (Intel-specific). */
1428	#define MSR_IA32_CORE_CAPABILITIES 0xCF
1429	/** STLB QoS feature supported. */
1430	#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1431	/** FUSA feature supported. */
1432	#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1433	/** RSM instruction only allowed in CPL 0. */
1434	#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1435	/** UC lock disable supported. */
1436	#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1437	/** Split-lock disable supported. */
1438	#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1439	/** Snoop filter QoS Mask MSRs supported. */
1440	#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1441	/** UC store throttling supported. */
1442	#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1443
1444	/** Get FSB clock status (Intel-specific). */
1445	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1446
1447	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1448	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1449
1450	/** C0 Maximum Frequency Clock Count */
1451	#define MSR_IA32_MPERF 0xE7
1452	/** C0 Actual Frequency Clock Count */
1453	#define MSR_IA32_APERF 0xE8
1454
1455	/** MTRR Capabilities. */
1456	#define MSR_IA32_MTRR_CAP 0xFE
1457	/** Bits 0-7 - VCNT - Variable range registers count. */
1458	#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1459	/** Bit 8 - FIX - Fixed range registers supported. */
1460	#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1461	/** Bit 10 - WC - Write-Combining memory type supported. */
1462	#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1463	/** Bit 11 - SMRR - System Management Range Register supported. */
1464	#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1465	/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1466	#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1467
1468
1469	#ifndef __ASSEMBLER__
1470	/**
1471	* Variable-range MTRR MSR pair.
1472	*/
1473	typedef struct X86MTRRVAR
1474	{
1475	uint64_t MtrrPhysBase; /*< IA32_MTRR_PHYSBASEn /
1476	uint64_t MtrrPhysMask; /*< IA32_MTRR_PHYSMASKn /
1477	} X86MTRRVAR;
1478	# ifndef VBOX_FOR_DTRACE_LIB
1479	AssertCompileSize(X86MTRRVAR, 16);
1480	# endif
1481	/** Pointer to a variable-range MTRR MSR pair. */
1482	typedef X86MTRRVAR *PX86MTRRVAR;
1483	/** Pointer to a const variable-range MTRR MSR pair. */
1484	typedef const X86MTRRVAR *PCX86MTRRVAR;
1485	#endif /* __ASSEMBLER__ */
1486
1487
1488	/** Memory types that can be encoded in MTRRs.
1489	* @{ */
1490	/** Uncacheable. */
1491	#define X86_MTRR_MT_UC 0
1492	/** Write Combining. */
1493	#define X86_MTRR_MT_WC 1
1494	/** Write-through. */
1495	#define X86_MTRR_MT_WT 4
1496	/** Write-protected. */
1497	#define X86_MTRR_MT_WP 5
1498	/** Writeback. */
1499	#define X86_MTRR_MT_WB 6
1500	/** @}*/
1501
1502	/** Architecture capabilities (bugfixes). */
1503	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1504	/** CPU is no subject to meltdown problems. */
1505	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1506	/** CPU has better IBRS and you can leave it on all the time. */
1507	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1508	/** CPU has return stack buffer (RSB) override. */
1509	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1510	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1511	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1512	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1513	/** CPU does not suffer from MDS issues. */
1514	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1515
1516	/** Flush command register. */
1517	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1518	/** Flush the level 1 data cache when this bit is written. */
1519	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1520
1521	/** Cache control/info. */
1522	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1523
1524	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1525	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1526	* R0 SS == CS + 8
1527	* R3 CS == CS + 16
1528	* R3 SS == CS + 24
1529	*/
1530	#define MSR_IA32_SYSENTER_CS 0x174
1531	/** SYSENTER_ESP - the R0 ESP. */
1532	#define MSR_IA32_SYSENTER_ESP 0x175
1533	/** SYSENTER_EIP - the R0 EIP. */
1534	#define MSR_IA32_SYSENTER_EIP 0x176
1535	#endif
1536
1537	/** Machine Check Global Capabilities Register. */
1538	#define MSR_IA32_MCG_CAP 0x179
1539	/** Machine Check Global Status Register. */
1540	#define MSR_IA32_MCG_STATUS 0x17A
1541	/** Machine Check Global Control Register. */
1542	#define MSR_IA32_MCG_CTRL 0x17B
1543
1544	/** Page Attribute Table. */
1545	#define MSR_IA32_CR_PAT 0x277
1546	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1547	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1548	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1549
1550	/** Memory types that can be encoded in the IA32_PAT MSR.
1551	* @{ */
1552	/** Uncacheable. */
1553	#define MSR_IA32_PAT_MT_UC 0
1554	/** Write Combining. */
1555	#define MSR_IA32_PAT_MT_WC 1
1556	/** Reserved value 2. */
1557	#define MSR_IA32_PAT_MT_RSVD_2 2
1558	/** Reserved value 3. */
1559	#define MSR_IA32_PAT_MT_RSVD_3 3
1560	/** Write-through. */
1561	#define MSR_IA32_PAT_MT_WT 4
1562	/** Write-protected. */
1563	#define MSR_IA32_PAT_MT_WP 5
1564	/** Writeback. */
1565	#define MSR_IA32_PAT_MT_WB 6
1566	/** Uncached (UC-). */
1567	#define MSR_IA32_PAT_MT_UCD 7
1568	/** @}*/
1569
1570
1571	/** Performance event select MSRs. (Intel only) */
1572	#define MSR_IA32_PERFEVTSEL0 0x186
1573	#define MSR_IA32_PERFEVTSEL1 0x187
1574	#define MSR_IA32_PERFEVTSEL2 0x188
1575	#define MSR_IA32_PERFEVTSEL3 0x189
1576
1577	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1578	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1579	* holds a ratio that Apple takes for TSC granularity.
1580	*
1581	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1582	#define MSR_FLEX_RATIO 0x194
1583	/** Performance state value and starting with Intel core more.
1584	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1585	#define MSR_IA32_PERF_STATUS 0x198
1586	#define MSR_IA32_PERF_CTL 0x199
1587	#define MSR_IA32_THERM_STATUS 0x19c
1588
1589	/** Offcore response event select registers. */
1590	#define MSR_OFFCORE_RSP_0 0x1a6
1591	#define MSR_OFFCORE_RSP_1 0x1a7
1592
1593	/** Enable misc. processor features (R/W). */
1594	#define MSR_IA32_MISC_ENABLE 0x1A0
1595	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1596	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1597	/** Automatic Thermal Control Circuit Enable (R/W). */
1598	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1599	/** Performance Monitoring Available (R). */
1600	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1601	/** Branch Trace Storage Unavailable (R/O). */
1602	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1603	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1604	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1605	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1606	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1607	/** If MONITOR/MWAIT is supported (R/W). */
1608	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1609	/** Limit CPUID Maxval to 3 leafs (R/W). */
1610	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1611	/** When set to 1, xTPR messages are disabled (R/W). */
1612	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1613	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1614	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1615
1616	/** Trace/Profile Resource Control (R/W) */
1617	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1618	/** Last branch record. */
1619	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1620	/** Branch trace flag (single step on branches). */
1621	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1622	/** Performance monitoring pin control (AMD only). */
1623	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1624	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1625	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1626	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1627	/** Trace message enable (Intel only). */
1628	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1629	/** Branch trace store (Intel only). */
1630	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1631	/** Branch trace interrupt (Intel only). */
1632	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1633	/** Branch trace off in privileged code (Intel only). */
1634	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1635	/** Branch trace off in user code (Intel only). */
1636	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1637	/** Freeze LBR on PMI flag (Intel only). */
1638	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1639	/** Freeze PERFMON on PMI flag (Intel only). */
1640	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1641	/** Freeze while SMM enabled (Intel only). */
1642	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1643	/** Advanced debugging of RTM regions (Intel only). */
1644	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1645	/** Debug control MSR valid bits (Intel only). */
1646	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1647	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1648	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1649	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1650	\| MSR_IA32_DEBUGCTL_RTM)
1651
1652	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1653	* @{ */
1654	#define MSR_P4_LASTBRANCH_0 0x1db
1655	#define MSR_P4_LASTBRANCH_1 0x1dc
1656	#define MSR_P4_LASTBRANCH_2 0x1dd
1657	#define MSR_P4_LASTBRANCH_3 0x1de
1658
1659	/** LBR Top-of-stack MSR (index to most recent record). */
1660	#define MSR_P4_LASTBRANCH_TOS 0x1da
1661	/** @} */
1662
1663	/** @name Last branch registers for Core 2 and related Xeons.
1664	* @{ */
1665	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1666	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1667	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1668	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1669
1670	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1671	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1672	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1673	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1674
1675	/** LBR Top-of-stack MSR (index to most recent record). */
1676	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1677	/** @} */
1678
1679	/** @name Last branch registers.
1680	* @{ */
1681	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1682	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1683	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1684	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1685	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1686	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1687	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1688	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1689	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1690	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1691	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1692	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1693	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1694	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1695	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1696	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1697	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1698	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1699	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1700	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1701	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1702	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1703	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1704	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1705	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1706	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1707	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1708	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1709	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1710	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1711	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1712	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1713
1714	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1715	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1716	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1717	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1718	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1719	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1720	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1721	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1722	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1723	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1724	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1725	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1726	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1727	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1728	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1729	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1730	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1731	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1732	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1733	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1734	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1735	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1736	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1737	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1738	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1739	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1740	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1741	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1742	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1743	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1744	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1745	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1746
1747	#define MSR_LASTBRANCH_0_INFO 0xdc0
1748	#define MSR_LASTBRANCH_1_INFO 0xdc1
1749	#define MSR_LASTBRANCH_2_INFO 0xdc2
1750	#define MSR_LASTBRANCH_3_INFO 0xdc3
1751	#define MSR_LASTBRANCH_4_INFO 0xdc4
1752	#define MSR_LASTBRANCH_5_INFO 0xdc5
1753	#define MSR_LASTBRANCH_6_INFO 0xdc6
1754	#define MSR_LASTBRANCH_7_INFO 0xdc7
1755	#define MSR_LASTBRANCH_8_INFO 0xdc8
1756	#define MSR_LASTBRANCH_9_INFO 0xdc9
1757	#define MSR_LASTBRANCH_10_INFO 0xdca
1758	#define MSR_LASTBRANCH_11_INFO 0xdcb
1759	#define MSR_LASTBRANCH_12_INFO 0xdcc
1760	#define MSR_LASTBRANCH_13_INFO 0xdcd
1761	#define MSR_LASTBRANCH_14_INFO 0xdce
1762	#define MSR_LASTBRANCH_15_INFO 0xdcf
1763	#define MSR_LASTBRANCH_16_INFO 0xdd0
1764	#define MSR_LASTBRANCH_17_INFO 0xdd1
1765	#define MSR_LASTBRANCH_18_INFO 0xdd2
1766	#define MSR_LASTBRANCH_19_INFO 0xdd3
1767	#define MSR_LASTBRANCH_20_INFO 0xdd4
1768	#define MSR_LASTBRANCH_21_INFO 0xdd5
1769	#define MSR_LASTBRANCH_22_INFO 0xdd6
1770	#define MSR_LASTBRANCH_23_INFO 0xdd7
1771	#define MSR_LASTBRANCH_24_INFO 0xdd8
1772	#define MSR_LASTBRANCH_25_INFO 0xdd9
1773	#define MSR_LASTBRANCH_26_INFO 0xdda
1774	#define MSR_LASTBRANCH_27_INFO 0xddb
1775	#define MSR_LASTBRANCH_28_INFO 0xddc
1776	#define MSR_LASTBRANCH_29_INFO 0xddd
1777	#define MSR_LASTBRANCH_30_INFO 0xdde
1778	#define MSR_LASTBRANCH_31_INFO 0xddf
1779
1780	/** LBR branch tracking selection MSR. */
1781	#define MSR_LASTBRANCH_SELECT 0x1c8
1782	/** LBR Top-of-stack MSR (index to most recent record). */
1783	#define MSR_LASTBRANCH_TOS 0x1c9
1784	/** @} */
1785
1786	/** @name Last event record registers.
1787	* @{ */
1788	/** Last event record source IP register. */
1789	#define MSR_LER_FROM_IP 0x1dd
1790	/** Last event record destination IP register. */
1791	#define MSR_LER_TO_IP 0x1de
1792	/** @} */
1793
1794	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1795	#define MSR_IA32_TSX_CTRL 0x122
1796
1797	/** Variable range MTRRs.
1798	* @{ */
1799	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1800	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1801	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1802	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1803	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1804	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1805	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1806	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1807	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1808	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1809	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1810	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1811	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1812	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1813	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1814	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1815	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1816	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1817	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1818	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1819	/** @} */
1820
1821	/** Fixed range MTRRs.
1822	* @{ */
1823	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1824	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1825	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1826	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1827	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1828	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1829	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1830	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1831	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1832	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1833	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1834	/** @} */
1835
1836	/** MTRR Default Type.
1837	* @{ */
1838	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1839	#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1840	#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1841	#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1842	#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1843	\| MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1844	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1845	/** @} */
1846
1847	/** Variable-range MTRR physical mask valid. */
1848	#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1849
1850	/** Variable-range MTRR memory type mask. */
1851	#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1852
1853	/** Global performance counter control facilities (Intel only). */
1854	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1855	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1856	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1857
1858	/** Precise Event Based sampling (Intel only). */
1859	#define MSR_IA32_PEBS_ENABLE 0x3F1
1860
1861	#define MSR_IA32_MC0_CTL 0x400
1862	#define MSR_IA32_MC0_STATUS 0x401
1863
1864	/** Basic VMX information. */
1865	#define MSR_IA32_VMX_BASIC 0x480
1866	/** Allowed settings for pin-based VM execution controls. */
1867	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1868	/** Allowed settings for proc-based VM execution controls. */
1869	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1870	/** Allowed settings for the VM-exit controls. */
1871	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1872	/** Allowed settings for the VM-entry controls. */
1873	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1874	/** Misc VMX info. */
1875	#define MSR_IA32_VMX_MISC 0x485
1876	/** Fixed cleared bits in CR0. */
1877	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1878	/** Fixed set bits in CR0. */
1879	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1880	/** Fixed cleared bits in CR4. */
1881	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1882	/** Fixed set bits in CR4. */
1883	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1884	/** Information for enumerating fields in the VMCS. */
1885	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1886	/** Allowed settings for secondary processor-based VM-execution controls. */
1887	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1888	/** EPT capabilities. */
1889	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1890	/** Allowed settings of all pin-based VM execution controls. */
1891	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1892	/** Allowed settings of all proc-based VM execution controls. */
1893	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1894	/** Allowed settings of all VMX exit controls. */
1895	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1896	/** Allowed settings of all VMX entry controls. */
1897	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1898	/** Allowed settings for the VM-function controls. */
1899	#define MSR_IA32_VMX_VMFUNC 0x491
1900	/** Tertiary processor-based VM execution controls. */
1901	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1902	/** Secondary VM-exit controls. */
1903	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1904
1905	/** Intel PT - Enable and control for trace packet generation. */
1906	#define MSR_IA32_RTIT_CTL 0x570
1907
1908	/** DS Save Area (R/W). */
1909	#define MSR_IA32_DS_AREA 0x600
1910	/** Running Average Power Limit (RAPL) power units. */
1911	#define MSR_RAPL_POWER_UNIT 0x606
1912	/** Package C3 Interrupt Response Limit. */
1913	#define MSR_PKGC3_IRTL 0x60a
1914	/** Package C6/C7S Interrupt Response Limit 1. */
1915	#define MSR_PKGC_IRTL1 0x60b
1916	/** Package C6/C7S Interrupt Response Limit 2. */
1917	#define MSR_PKGC_IRTL2 0x60c
1918	/** Package C2 Residency Counter. */
1919	#define MSR_PKG_C2_RESIDENCY 0x60d
1920	/** PKG RAPL Power Limit Control. */
1921	#define MSR_PKG_POWER_LIMIT 0x610
1922	/** PKG Energy Status. */
1923	#define MSR_PKG_ENERGY_STATUS 0x611
1924	/** PKG Perf Status. */
1925	#define MSR_PKG_PERF_STATUS 0x613
1926	/** PKG RAPL Parameters. */
1927	#define MSR_PKG_POWER_INFO 0x614
1928	/** DRAM RAPL Power Limit Control. */
1929	#define MSR_DRAM_POWER_LIMIT 0x618
1930	/** DRAM Energy Status. */
1931	#define MSR_DRAM_ENERGY_STATUS 0x619
1932	/** DRAM Performance Throttling Status. */
1933	#define MSR_DRAM_PERF_STATUS 0x61b
1934	/** DRAM RAPL Parameters. */
1935	#define MSR_DRAM_POWER_INFO 0x61c
1936	/** Package C10 Residency Counter. */
1937	#define MSR_PKG_C10_RESIDENCY 0x632
1938	/** PP0 Energy Status. */
1939	#define MSR_PP0_ENERGY_STATUS 0x639
1940	/** PP1 Energy Status. */
1941	#define MSR_PP1_ENERGY_STATUS 0x641
1942	/** Turbo Activation Ratio. */
1943	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1944	/** Core Performance Limit Reasons. */
1945	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1946
1947	/** Userspace Control flow Enforcement Technology setting. */
1948	#define MSR_IA32_U_CET 0x6a0
1949	/** Supervisor space Control flow Enforcement Technology setting. */
1950	#define MSR_IA32_S_CET 0x6a2
1951	/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1952	* @{ */
1953	/** Enables the Shadow stack. */
1954	# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1955	/** Enables WRSS{D,Q}W instructions. */
1956	# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1957	/** Enables indirect branch tracking. */
1958	# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1959	/** Enable legacy compatibility treatment for indirect branch tracking. */
1960	# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1961	/** Enables the use of no-track prefix for indirect branch tracking. */
1962	# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1963	/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1964	# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1965	/** Suppresses indirect branch tracking. */
1966	# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1967	/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1968	# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1969	/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1970	* on a ENDBRANCH instruction. */
1971	# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1972	/** @} */
1973
1974	/** X2APIC MSR range start. */
1975	#define MSR_IA32_X2APIC_START 0x800
1976	/** X2APIC MSR - APIC ID Register. */
1977	#define MSR_IA32_X2APIC_ID 0x802
1978	/** X2APIC MSR - APIC Version Register. */
1979	#define MSR_IA32_X2APIC_VERSION 0x803
1980	/** X2APIC MSR - Task Priority Register. */
1981	#define MSR_IA32_X2APIC_TPR 0x808
1982	/** X2APIC MSR - Processor Priority register. */
1983	#define MSR_IA32_X2APIC_PPR 0x80A
1984	/** X2APIC MSR - End Of Interrupt register. */
1985	#define MSR_IA32_X2APIC_EOI 0x80B
1986	/** X2APIC MSR - Logical Destination Register. */
1987	#define MSR_IA32_X2APIC_LDR 0x80D
1988	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1989	#define MSR_IA32_X2APIC_SVR 0x80F
1990	/** X2APIC MSR - In-service Register (bits 31:0). */
1991	#define MSR_IA32_X2APIC_ISR0 0x810
1992	/** X2APIC MSR - In-service Register (bits 63:32). */
1993	#define MSR_IA32_X2APIC_ISR1 0x811
1994	/** X2APIC MSR - In-service Register (bits 95:64). */
1995	#define MSR_IA32_X2APIC_ISR2 0x812
1996	/** X2APIC MSR - In-service Register (bits 127:96). */
1997	#define MSR_IA32_X2APIC_ISR3 0x813
1998	/** X2APIC MSR - In-service Register (bits 159:128). */
1999	#define MSR_IA32_X2APIC_ISR4 0x814
2000	/** X2APIC MSR - In-service Register (bits 191:160). */
2001	#define MSR_IA32_X2APIC_ISR5 0x815
2002	/** X2APIC MSR - In-service Register (bits 223:192). */
2003	#define MSR_IA32_X2APIC_ISR6 0x816
2004	/** X2APIC MSR - In-service Register (bits 255:224). */
2005	#define MSR_IA32_X2APIC_ISR7 0x817
2006	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2007	#define MSR_IA32_X2APIC_TMR0 0x818
2008	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2009	#define MSR_IA32_X2APIC_TMR1 0x819
2010	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2011	#define MSR_IA32_X2APIC_TMR2 0x81A
2012	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2013	#define MSR_IA32_X2APIC_TMR3 0x81B
2014	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2015	#define MSR_IA32_X2APIC_TMR4 0x81C
2016	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2017	#define MSR_IA32_X2APIC_TMR5 0x81D
2018	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2019	#define MSR_IA32_X2APIC_TMR6 0x81E
2020	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2021	#define MSR_IA32_X2APIC_TMR7 0x81F
2022	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2023	#define MSR_IA32_X2APIC_IRR0 0x820
2024	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2025	#define MSR_IA32_X2APIC_IRR1 0x821
2026	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2027	#define MSR_IA32_X2APIC_IRR2 0x822
2028	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2029	#define MSR_IA32_X2APIC_IRR3 0x823
2030	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2031	#define MSR_IA32_X2APIC_IRR4 0x824
2032	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2033	#define MSR_IA32_X2APIC_IRR5 0x825
2034	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2035	#define MSR_IA32_X2APIC_IRR6 0x826
2036	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2037	#define MSR_IA32_X2APIC_IRR7 0x827
2038	/** X2APIC MSR - Error Status Register. */
2039	#define MSR_IA32_X2APIC_ESR 0x828
2040	/** X2APIC MSR - LVT CMCI Register. */
2041	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2042	/** X2APIC MSR - Interrupt Command Register. */
2043	#define MSR_IA32_X2APIC_ICR 0x830
2044	/** X2APIC MSR - LVT Timer Register. */
2045	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2046	/** X2APIC MSR - LVT Thermal Sensor Register. */
2047	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2048	/** X2APIC MSR - LVT Performance Counter Register. */
2049	#define MSR_IA32_X2APIC_LVT_PERF 0x834
2050	/** X2APIC MSR - LVT LINT0 Register. */
2051	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2052	/** X2APIC MSR - LVT LINT1 Register. */
2053	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2054	/** X2APIC MSR - LVT Error Register . */
2055	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2056	/** X2APIC MSR - Timer Initial Count Register. */
2057	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2058	/** X2APIC MSR - Timer Current Count Register. */
2059	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2060	/** X2APIC MSR - Timer Divide Configuration Register. */
2061	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2062	/** X2APIC MSR - Self IPI. */
2063	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2064	/** X2APIC MSR range end. */
2065	#define MSR_IA32_X2APIC_END 0x8FF
2066	/** X2APIC MSR - LVT start range. */
2067	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2068	/** X2APIC MSR - LVT end range (inclusive). */
2069	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2070
2071	/** K6 EFER - Extended Feature Enable Register. */
2072	#define MSR_K6_EFER UINT32_C(0xc0000080)
2073	/** @todo document EFER */
2074	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2075	#define MSR_K6_EFER_SCE RT_BIT_32(0)
2076	/** Bit 8 - LME - Long mode enabled. (R/W) */
2077	#define MSR_K6_EFER_LME RT_BIT_32(8)
2078	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
2079	/** Bit 10 - LMA - Long mode active. (R) */
2080	#define MSR_K6_EFER_LMA RT_BIT_32(10)
2081	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
2082	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2083	#define MSR_K6_EFER_NXE RT_BIT_32(11)
2084	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
2085	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2086	#define MSR_K6_EFER_SVME RT_BIT_32(12)
2087	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2088	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2089	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
2090	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2091	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2092	#define MSR_K6_EFER_TCE RT_BIT_32(15)
2093	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2094	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2095
2096	/** K6 STAR - SYSCALL/RET targets. */
2097	#define MSR_K6_STAR UINT32_C(0xc0000081)
2098	/** Shift value for getting the SYSRET CS and SS value. */
2099	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2100	/** Shift value for getting the SYSCALL CS and SS value. */
2101	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2102	/** Selector mask for use after shifting. */
2103	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2104	/** The mask which give the SYSCALL EIP. */
2105	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2106	/** K6 WHCR - Write Handling Control Register. */
2107	#define MSR_K6_WHCR UINT32_C(0xc0000082)
2108	/** K6 UWCCR - UC/WC Cacheability Control Register. */
2109	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2110	/** K6 PSOR - Processor State Observability Register. */
2111	#define MSR_K6_PSOR UINT32_C(0xc0000087)
2112	/** K6 PFIR - Page Flush/Invalidate Register. */
2113	#define MSR_K6_PFIR UINT32_C(0xc0000088)
2114
2115	/** Performance counter MSRs. (AMD only) */
2116	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2117	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2118	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2119	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2120	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2121	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2122	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2123	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2124
2125	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2126	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2127	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2128	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2129	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2130	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2131	/** K8 FS.base - The 64-bit base FS register. */
2132	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2133	/** K8 GS.base - The 64-bit base GS register. */
2134	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2135	/** K8 KernelGSbase - Used with SWAPGS. */
2136	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2137	/** K8 TSC_AUX - Used with RDTSCP. */
2138	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2139	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2140	#define MSR_K8_HWCR UINT32_C(0xc0010015)
2141	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2142	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2143	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2144	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2145	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2146	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2147
2148	/** SMM MSRs. */
2149	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2150	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2151	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2152
2153	/** North bridge config? See BIOS & Kernel dev guides for
2154	* details. */
2155	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2156
2157	/** Hypertransport interrupt pending register.
2158	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2159	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2160
2161	/** SVM Control. */
2162	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2163	/** Disables HDT (Hardware Debug Tool) and certain internal debug
2164	* features. */
2165	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2166	/** If set, non-intercepted INIT signals are converted to \#SX
2167	* exceptions. */
2168	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2169	/** Disables A20 masking. */
2170	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2171	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2172	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2173	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2174	* clear, EFER.SVME can be written normally. */
2175	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2176
2177	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2178	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2179	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2180	* host state during world switch. */
2181	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2182
2183	/** Virtualized speculation control for AMD processors.
2184	*
2185	* Unified interface among different CPU generations.
2186	* The VMM will set any architectural MSRs based on the CPU.
2187	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2188	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2189	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2190	/** Speculative Store Bypass Disable. */
2191	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2192
2193	/** @} */
2194
2195
2196	/** @name Page Table / Directory / Directory Pointers / L4.
2197	* @{
2198	*/
2199
2200	#ifndef __ASSEMBLER__
2201	/** Page table/directory entry as an unsigned integer. */
2202	typedef uint32_t X86PGUINT;
2203	/** Pointer to a page table/directory table entry as an unsigned integer. */
2204	typedef X86PGUINT *PX86PGUINT;
2205	/** Pointer to an const page table/directory table entry as an unsigned integer. */
2206	typedef X86PGUINT const *PCX86PGUINT;
2207	#endif
2208
2209	/** Number of entries in a 32-bit PT/PD. */
2210	#define X86_PG_ENTRIES 1024
2211
2212
2213	#ifndef __ASSEMBLER__
2214	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2215	typedef uint64_t X86PGPAEUINT;
2216	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2217	typedef X86PGPAEUINT *PX86PGPAEUINT;
2218	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2219	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2220	#endif
2221
2222	/** Number of entries in a PAE PT/PD. */
2223	#define X86_PG_PAE_ENTRIES 512
2224	/** Number of entries in a PAE PDPT. */
2225	#define X86_PG_PAE_PDPE_ENTRIES 4
2226
2227	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2228	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2229	/** Number of entries in an AMD64 PDPT.
2230	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2231	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2232
2233	/** The size of a default page. */
2234	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2235	/** The page shift of a default page. */
2236	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2237	/** The default page offset mask. */
2238	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2239	/** The default page base mask for virtual addresses. */
2240	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2241	/** The default page base mask for virtual addresses - 32bit version. */
2242	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2243
2244	/** The size of a 4KB page. */
2245	#define X86_PAGE_4K_SIZE _4K
2246	/** The page shift of a 4KB page. */
2247	#define X86_PAGE_4K_SHIFT 12
2248	/** The 4KB page offset mask. */
2249	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2250	/** The 4KB page base mask for virtual addresses. */
2251	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2252	/** The 4KB page base mask for virtual addresses - 32bit version. */
2253	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2254
2255	/** The size of a 2MB page. */
2256	#define X86_PAGE_2M_SIZE _2M
2257	/** The page shift of a 2MB page. */
2258	#define X86_PAGE_2M_SHIFT 21
2259	/** The 2MB page offset mask. */
2260	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2261	/** The 2MB page base mask for virtual addresses. */
2262	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2263	/** The 2MB page base mask for virtual addresses - 32bit version. */
2264	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2265
2266	/** The size of a 4MB page. */
2267	#define X86_PAGE_4M_SIZE _4M
2268	/** The page shift of a 4MB page. */
2269	#define X86_PAGE_4M_SHIFT 22
2270	/** The 4MB page offset mask. */
2271	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2272	/** The 4MB page base mask for virtual addresses. */
2273	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2274	/** The 4MB page base mask for virtual addresses - 32bit version. */
2275	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2276
2277	/** The size of a 1GB page. */
2278	#define X86_PAGE_1G_SIZE _1G
2279	/** The page shift of a 1GB page. */
2280	#define X86_PAGE_1G_SHIFT 30
2281	/** The 1GB page offset mask. */
2282	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2283	/** The 1GB page base mask for virtual addresses. */
2284	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2285
2286	/**
2287	* Check if the given address is canonical.
2288	*/
2289	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2290
2291	/**
2292	* Gets the page base mask given the page shift.
2293	*/
2294	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2295
2296	/**
2297	* Gets the page offset mask given the page shift.
2298	*/
2299	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2300
2301
2302	/** @name Page Table Entry
2303	* @{
2304	*/
2305	/** Bit 0 - P - Present bit. */
2306	#define X86_PTE_BIT_P 0
2307	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2308	#define X86_PTE_BIT_RW 1
2309	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2310	#define X86_PTE_BIT_US 2
2311	/** Bit 3 - PWT - Page level write thru bit. */
2312	#define X86_PTE_BIT_PWT 3
2313	/** Bit 4 - PCD - Page level cache disable bit. */
2314	#define X86_PTE_BIT_PCD 4
2315	/** Bit 5 - A - Access bit. */
2316	#define X86_PTE_BIT_A 5
2317	/** Bit 6 - D - Dirty bit. */
2318	#define X86_PTE_BIT_D 6
2319	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2320	#define X86_PTE_BIT_PAT 7
2321	/** Bit 8 - G - Global flag. */
2322	#define X86_PTE_BIT_G 8
2323	/** Bits 63 - NX - PAE/LM - No execution flag. */
2324	#define X86_PTE_PAE_BIT_NX 63
2325
2326	/** Bit 0 - P - Present bit mask. */
2327	#define X86_PTE_P RT_BIT_32(0)
2328	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2329	#define X86_PTE_RW RT_BIT_32(1)
2330	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2331	#define X86_PTE_US RT_BIT_32(2)
2332	/** Bit 3 - PWT - Page level write thru bit mask. */
2333	#define X86_PTE_PWT RT_BIT_32(3)
2334	/** Bit 4 - PCD - Page level cache disable bit mask. */
2335	#define X86_PTE_PCD RT_BIT_32(4)
2336	/** Bit 5 - A - Access bit mask. */
2337	#define X86_PTE_A RT_BIT_32(5)
2338	/** Bit 6 - D - Dirty bit mask. */
2339	#define X86_PTE_D RT_BIT_32(6)
2340	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2341	#define X86_PTE_PAT RT_BIT_32(7)
2342	/** Bit 8 - G - Global bit mask. */
2343	#define X86_PTE_G RT_BIT_32(8)
2344
2345	/** Bits 9-11 - - Available for use to system software. */
2346	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2347	/** Bits 12-31 - - Physical Page number of the next level. */
2348	#define X86_PTE_PG_MASK ( 0xfffff000 )
2349
2350	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2351	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2352	/** Bits 63 - NX - PAE/LM - No execution flag. */
2353	#define X86_PTE_PAE_NX RT_BIT_64(63)
2354	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2355	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2356	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2357	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2358	/** No bits - - LM - MBZ bits when NX is active. */
2359	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2360	/** Bits 63 - - LM - MBZ bits when no NX. */
2361	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2362
2363	#ifndef __ASSEMBLER__
2364
2365	/**
2366	* Page table entry.
2367	*/
2368	typedef struct X86PTEBITS
2369	{
2370	/** Flags whether(=1) or not the page is present. */
2371	uint32_t u1Present : 1;
2372	/** Read(=0) / Write(=1) flag. */
2373	uint32_t u1Write : 1;
2374	/** User(=1) / Supervisor (=0) flag. */
2375	uint32_t u1User : 1;
2376	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2377	uint32_t u1WriteThru : 1;
2378	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2379	uint32_t u1CacheDisable : 1;
2380	/** Accessed flag.
2381	* Indicates that the page have been read or written to. */
2382	uint32_t u1Accessed : 1;
2383	/** Dirty flag.
2384	* Indicates that the page has been written to. */
2385	uint32_t u1Dirty : 1;
2386	/** Reserved / If PAT enabled, bit 2 of the index. */
2387	uint32_t u1PAT : 1;
2388	/** Global flag. (Ignored in all but final level.) */
2389	uint32_t u1Global : 1;
2390	/** Available for use to system software. */
2391	uint32_t u3Available : 3;
2392	/** Physical Page number of the next level. */
2393	uint32_t u20PageNo : 20;
2394	} X86PTEBITS;
2395	# ifndef VBOX_FOR_DTRACE_LIB
2396	AssertCompileSize(X86PTEBITS, 4);
2397	# endif
2398	/** Pointer to a page table entry. */
2399	typedef X86PTEBITS *PX86PTEBITS;
2400	/** Pointer to a const page table entry. */
2401	typedef const X86PTEBITS *PCX86PTEBITS;
2402
2403	/**
2404	* Page table entry.
2405	*/
2406	typedef union X86PTE
2407	{
2408	/** Unsigned integer view */
2409	X86PGUINT u;
2410	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2411	/** Bit field view. */
2412	X86PTEBITS n;
2413	# endif
2414	/** 32-bit view. */
2415	uint32_t au32[1];
2416	/** 16-bit view. */
2417	uint16_t au16[2];
2418	/** 8-bit view. */
2419	uint8_t au8[4];
2420	} X86PTE;
2421	# ifndef VBOX_FOR_DTRACE_LIB
2422	AssertCompileSize(X86PTE, 4);
2423	# endif
2424	/** Pointer to a page table entry. */
2425	typedef X86PTE *PX86PTE;
2426	/** Pointer to a const page table entry. */
2427	typedef const X86PTE *PCX86PTE;
2428
2429
2430	/**
2431	* PAE page table entry.
2432	*/
2433	typedef struct X86PTEPAEBITS
2434	{
2435	/** Flags whether(=1) or not the page is present. */
2436	uint32_t u1Present : 1;
2437	/** Read(=0) / Write(=1) flag. */
2438	uint32_t u1Write : 1;
2439	/** User(=1) / Supervisor(=0) flag. */
2440	uint32_t u1User : 1;
2441	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2442	uint32_t u1WriteThru : 1;
2443	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2444	uint32_t u1CacheDisable : 1;
2445	/** Accessed flag.
2446	* Indicates that the page have been read or written to. */
2447	uint32_t u1Accessed : 1;
2448	/** Dirty flag.
2449	* Indicates that the page has been written to. */
2450	uint32_t u1Dirty : 1;
2451	/** Reserved / If PAT enabled, bit 2 of the index. */
2452	uint32_t u1PAT : 1;
2453	/** Global flag. (Ignored in all but final level.) */
2454	uint32_t u1Global : 1;
2455	/** Available for use to system software. */
2456	uint32_t u3Available : 3;
2457	/** Physical Page number of the next level - Low Part. Don't use this. */
2458	uint32_t u20PageNoLow : 20;
2459	/** Physical Page number of the next level - High Part. Don't use this. */
2460	uint32_t u20PageNoHigh : 20;
2461	/** MBZ bits */
2462	uint32_t u11Reserved : 11;
2463	/** No Execute flag. */
2464	uint32_t u1NoExecute : 1;
2465	} X86PTEPAEBITS;
2466	# ifndef VBOX_FOR_DTRACE_LIB
2467	AssertCompileSize(X86PTEPAEBITS, 8);
2468	# endif
2469	/** Pointer to a page table entry. */
2470	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2471	/** Pointer to a page table entry. */
2472	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2473
2474	/**
2475	* PAE Page table entry.
2476	*/
2477	typedef union X86PTEPAE
2478	{
2479	/** Unsigned integer view */
2480	X86PGPAEUINT u;
2481	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2482	/** Bit field view. */
2483	X86PTEPAEBITS n;
2484	# endif
2485	/** 32-bit view. */
2486	uint32_t au32[2];
2487	/** 16-bit view. */
2488	uint16_t au16[4];
2489	/** 8-bit view. */
2490	uint8_t au8[8];
2491	} X86PTEPAE;
2492	# ifndef VBOX_FOR_DTRACE_LIB
2493	AssertCompileSize(X86PTEPAE, 8);
2494	# endif
2495	/** Pointer to a PAE page table entry. */
2496	typedef X86PTEPAE *PX86PTEPAE;
2497	/** Pointer to a const PAE page table entry. */
2498	typedef const X86PTEPAE *PCX86PTEPAE;
2499	/** @} */
2500
2501	/**
2502	* Page table.
2503	*/
2504	typedef struct X86PT
2505	{
2506	/** PTE Array. */
2507	X86PTE a[X86_PG_ENTRIES];
2508	} X86PT;
2509	# ifndef VBOX_FOR_DTRACE_LIB
2510	AssertCompileSize(X86PT, 4096);
2511	# endif
2512	/** Pointer to a page table. */
2513	typedef X86PT *PX86PT;
2514	/** Pointer to a const page table. */
2515	typedef const X86PT *PCX86PT;
2516
2517	#endif /* !__ASSEMBLER__ */
2518
2519	/** The page shift to get the PT index. */
2520	#define X86_PT_SHIFT 12
2521	/** The PT index mask (apply to a shifted page address). */
2522	#define X86_PT_MASK 0x3ff
2523
2524
2525	#ifndef __ASSEMBLER__
2526	/**
2527	* Page directory.
2528	*/
2529	typedef struct X86PTPAE
2530	{
2531	/** PTE Array. */
2532	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2533	} X86PTPAE;
2534	# ifndef VBOX_FOR_DTRACE_LIB
2535	AssertCompileSize(X86PTPAE, 4096);
2536	# endif
2537	/** Pointer to a page table. */
2538	typedef X86PTPAE *PX86PTPAE;
2539	/** Pointer to a const page table. */
2540	typedef const X86PTPAE *PCX86PTPAE;
2541	#endif /* !__ASSEMBLY__ */
2542
2543	/** The page shift to get the PA PTE index. */
2544	#define X86_PT_PAE_SHIFT 12
2545	/** The PAE PT index mask (apply to a shifted page address). */
2546	#define X86_PT_PAE_MASK 0x1ff
2547
2548
2549	/** @name 4KB Page Directory Entry
2550	* @{
2551	*/
2552	/** Bit 0 - P - Present bit. */
2553	#define X86_PDE_P RT_BIT_32(0)
2554	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2555	#define X86_PDE_RW RT_BIT_32(1)
2556	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2557	#define X86_PDE_US RT_BIT_32(2)
2558	/** Bit 3 - PWT - Page level write thru bit. */
2559	#define X86_PDE_PWT RT_BIT_32(3)
2560	/** Bit 4 - PCD - Page level cache disable bit. */
2561	#define X86_PDE_PCD RT_BIT_32(4)
2562	/** Bit 5 - A - Access bit. */
2563	#define X86_PDE_A RT_BIT_32(5)
2564	/** Bit 7 - PS - Page size attribute.
2565	* Clear mean 4KB pages, set means large pages (2/4MB). */
2566	#define X86_PDE_PS RT_BIT_32(7)
2567	/** Bits 9-11 - - Available for use to system software. */
2568	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2569	/** Bits 12-31 - - Physical Page number of the next level. */
2570	#define X86_PDE_PG_MASK ( 0xfffff000 )
2571
2572	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2573	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2574	/** Bits 63 - NX - PAE/LM - No execution flag. */
2575	#define X86_PDE_PAE_NX RT_BIT_64(63)
2576	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2577	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2578	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2579	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2580	/** Bit 7 - - LM - MBZ bits when NX is active. */
2581	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2582	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2583	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2584
2585	#ifndef __ASSEMBLER__
2586
2587	/**
2588	* Page directory entry.
2589	*/
2590	typedef struct X86PDEBITS
2591	{
2592	/** Flags whether(=1) or not the page is present. */
2593	uint32_t u1Present : 1;
2594	/** Read(=0) / Write(=1) flag. */
2595	uint32_t u1Write : 1;
2596	/** User(=1) / Supervisor (=0) flag. */
2597	uint32_t u1User : 1;
2598	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2599	uint32_t u1WriteThru : 1;
2600	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2601	uint32_t u1CacheDisable : 1;
2602	/** Accessed flag.
2603	* Indicates that the page has been read or written to. */
2604	uint32_t u1Accessed : 1;
2605	/** Reserved / Ignored (dirty bit). */
2606	uint32_t u1Reserved0 : 1;
2607	/** Size bit if PSE is enabled - in any event it's 0. */
2608	uint32_t u1Size : 1;
2609	/** Reserved / Ignored (global bit). */
2610	uint32_t u1Reserved1 : 1;
2611	/** Available for use to system software. */
2612	uint32_t u3Available : 3;
2613	/** Physical Page number of the next level. */
2614	uint32_t u20PageNo : 20;
2615	} X86PDEBITS;
2616	# ifndef VBOX_FOR_DTRACE_LIB
2617	AssertCompileSize(X86PDEBITS, 4);
2618	# endif
2619	/** Pointer to a page directory entry. */
2620	typedef X86PDEBITS *PX86PDEBITS;
2621	/** Pointer to a const page directory entry. */
2622	typedef const X86PDEBITS *PCX86PDEBITS;
2623
2624
2625	/**
2626	* PAE page directory entry.
2627	*/
2628	typedef struct X86PDEPAEBITS
2629	{
2630	/** Flags whether(=1) or not the page is present. */
2631	uint32_t u1Present : 1;
2632	/** Read(=0) / Write(=1) flag. */
2633	uint32_t u1Write : 1;
2634	/** User(=1) / Supervisor (=0) flag. */
2635	uint32_t u1User : 1;
2636	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2637	uint32_t u1WriteThru : 1;
2638	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2639	uint32_t u1CacheDisable : 1;
2640	/** Accessed flag.
2641	* Indicates that the page has been read or written to. */
2642	uint32_t u1Accessed : 1;
2643	/** Reserved / Ignored (dirty bit). */
2644	uint32_t u1Reserved0 : 1;
2645	/** Size bit if PSE is enabled - in any event it's 0. */
2646	uint32_t u1Size : 1;
2647	/** Reserved / Ignored (global bit). / */
2648	uint32_t u1Reserved1 : 1;
2649	/** Available for use to system software. */
2650	uint32_t u3Available : 3;
2651	/** Physical Page number of the next level - Low Part. Don't use! */
2652	uint32_t u20PageNoLow : 20;
2653	/** Physical Page number of the next level - High Part. Don't use! */
2654	uint32_t u20PageNoHigh : 20;
2655	/** MBZ bits */
2656	uint32_t u11Reserved : 11;
2657	/** No Execute flag. */
2658	uint32_t u1NoExecute : 1;
2659	} X86PDEPAEBITS;
2660	# ifndef VBOX_FOR_DTRACE_LIB
2661	AssertCompileSize(X86PDEPAEBITS, 8);
2662	# endif
2663	/** Pointer to a page directory entry. */
2664	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2665	/** Pointer to a const page directory entry. */
2666	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2667
2668	#endif /* !__ASSEMBLER__ */
2669
2670	/** @} */
2671
2672
2673	/** @name 2/4MB Page Directory Entry
2674	* @{
2675	*/
2676	/** Bit 0 - P - Present bit. */
2677	#define X86_PDE4M_P RT_BIT_32(0)
2678	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2679	#define X86_PDE4M_RW RT_BIT_32(1)
2680	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2681	#define X86_PDE4M_US RT_BIT_32(2)
2682	/** Bit 3 - PWT - Page level write thru bit. */
2683	#define X86_PDE4M_PWT RT_BIT_32(3)
2684	/** Bit 4 - PCD - Page level cache disable bit. */
2685	#define X86_PDE4M_PCD RT_BIT_32(4)
2686	/** Bit 5 - A - Access bit. */
2687	#define X86_PDE4M_A RT_BIT_32(5)
2688	/** Bit 6 - D - Dirty bit. */
2689	#define X86_PDE4M_D RT_BIT_32(6)
2690	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2691	#define X86_PDE4M_PS RT_BIT_32(7)
2692	/** Bit 8 - G - Global flag. */
2693	#define X86_PDE4M_G RT_BIT_32(8)
2694	/** Bits 9-11 - AVL - Available for use to system software. */
2695	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2696	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2697	#define X86_PDE4M_PAT RT_BIT_32(12)
2698	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2699	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2700	/** Bits 22-31 - - Physical Page number. */
2701	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2702	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2703	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2704	/** The number of bits to the high part of the page number. */
2705	#define X86_PDE4M_PG_HIGH_SHIFT 19
2706	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2707	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2708
2709	/** Bits 21-51 - - PAE/LM - Physical Page number.
2710	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2711	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2712	/** Bits 63 - NX - PAE/LM - No execution flag. */
2713	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2714	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2715	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2716	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2717	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2718	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2719	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2720	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2721	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2722
2723	#ifndef __ASSEMBLER__
2724
2725	/**
2726	* 4MB page directory entry.
2727	*/
2728	typedef struct X86PDE4MBITS
2729	{
2730	/** Flags whether(=1) or not the page is present. */
2731	uint32_t u1Present : 1;
2732	/** Read(=0) / Write(=1) flag. */
2733	uint32_t u1Write : 1;
2734	/** User(=1) / Supervisor (=0) flag. */
2735	uint32_t u1User : 1;
2736	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2737	uint32_t u1WriteThru : 1;
2738	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2739	uint32_t u1CacheDisable : 1;
2740	/** Accessed flag.
2741	* Indicates that the page have been read or written to. */
2742	uint32_t u1Accessed : 1;
2743	/** Dirty flag.
2744	* Indicates that the page has been written to. */
2745	uint32_t u1Dirty : 1;
2746	/** Page size flag - always 1 for 4MB entries. */
2747	uint32_t u1Size : 1;
2748	/** Global flag. */
2749	uint32_t u1Global : 1;
2750	/** Available for use to system software. */
2751	uint32_t u3Available : 3;
2752	/** Reserved / If PAT enabled, bit 2 of the index. */
2753	uint32_t u1PAT : 1;
2754	/** Bits 32-39 of the page number on AMD64.
2755	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2756	uint32_t u8PageNoHigh : 8;
2757	/** Reserved. */
2758	uint32_t u1Reserved : 1;
2759	/** Physical Page number of the page. */
2760	uint32_t u10PageNo : 10;
2761	} X86PDE4MBITS;
2762	# ifndef VBOX_FOR_DTRACE_LIB
2763	AssertCompileSize(X86PDE4MBITS, 4);
2764	# endif
2765	/** Pointer to a page table entry. */
2766	typedef X86PDE4MBITS *PX86PDE4MBITS;
2767	/** Pointer to a const page table entry. */
2768	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2769
2770
2771	/**
2772	* 2MB PAE page directory entry.
2773	*/
2774	typedef struct X86PDE2MPAEBITS
2775	{
2776	/** Flags whether(=1) or not the page is present. */
2777	uint32_t u1Present : 1;
2778	/** Read(=0) / Write(=1) flag. */
2779	uint32_t u1Write : 1;
2780	/** User(=1) / Supervisor(=0) flag. */
2781	uint32_t u1User : 1;
2782	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2783	uint32_t u1WriteThru : 1;
2784	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2785	uint32_t u1CacheDisable : 1;
2786	/** Accessed flag.
2787	* Indicates that the page have been read or written to. */
2788	uint32_t u1Accessed : 1;
2789	/** Dirty flag.
2790	* Indicates that the page has been written to. */
2791	uint32_t u1Dirty : 1;
2792	/** Page size flag - always 1 for 2MB entries. */
2793	uint32_t u1Size : 1;
2794	/** Global flag. */
2795	uint32_t u1Global : 1;
2796	/** Available for use to system software. */
2797	uint32_t u3Available : 3;
2798	/** Reserved / If PAT enabled, bit 2 of the index. */
2799	uint32_t u1PAT : 1;
2800	/** Reserved. */
2801	uint32_t u9Reserved : 9;
2802	/** Physical Page number of the next level - Low part. Don't use! */
2803	uint32_t u10PageNoLow : 10;
2804	/** Physical Page number of the next level - High part. Don't use! */
2805	uint32_t u20PageNoHigh : 20;
2806	/** MBZ bits */
2807	uint32_t u11Reserved : 11;
2808	/** No Execute flag. */
2809	uint32_t u1NoExecute : 1;
2810	} X86PDE2MPAEBITS;
2811	# ifndef VBOX_FOR_DTRACE_LIB
2812	AssertCompileSize(X86PDE2MPAEBITS, 8);
2813	# endif
2814	/** Pointer to a 2MB PAE page table entry. */
2815	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2816	/** Pointer to a 2MB PAE page table entry. */
2817	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2818
2819	#endif /* !__ASSEMBLER__ */
2820
2821	/** @} */
2822
2823	#ifndef __ASSEMBLER__
2824
2825	/**
2826	* Page directory entry.
2827	*/
2828	typedef union X86PDE
2829	{
2830	/** Unsigned integer view. */
2831	X86PGUINT u;
2832	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2833	/** Normal view. */
2834	X86PDEBITS n;
2835	/** 4MB view (big). */
2836	X86PDE4MBITS b;
2837	# endif
2838	/** 8 bit unsigned integer view. */
2839	uint8_t au8[4];
2840	/** 16 bit unsigned integer view. */
2841	uint16_t au16[2];
2842	/** 32 bit unsigned integer view. */
2843	uint32_t au32[1];
2844	} X86PDE;
2845	# ifndef VBOX_FOR_DTRACE_LIB
2846	AssertCompileSize(X86PDE, 4);
2847	# endif
2848	/** Pointer to a page directory entry. */
2849	typedef X86PDE *PX86PDE;
2850	/** Pointer to a const page directory entry. */
2851	typedef const X86PDE *PCX86PDE;
2852
2853	/**
2854	* PAE page directory entry.
2855	*/
2856	typedef union X86PDEPAE
2857	{
2858	/** Unsigned integer view. */
2859	X86PGPAEUINT u;
2860	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2861	/** Normal view. */
2862	X86PDEPAEBITS n;
2863	/** 2MB page view (big). */
2864	X86PDE2MPAEBITS b;
2865	# endif
2866	/** 8 bit unsigned integer view. */
2867	uint8_t au8[8];
2868	/** 16 bit unsigned integer view. */
2869	uint16_t au16[4];
2870	/** 32 bit unsigned integer view. */
2871	uint32_t au32[2];
2872	} X86PDEPAE;
2873	# ifndef VBOX_FOR_DTRACE_LIB
2874	AssertCompileSize(X86PDEPAE, 8);
2875	# endif
2876	/** Pointer to a page directory entry. */
2877	typedef X86PDEPAE *PX86PDEPAE;
2878	/** Pointer to a const page directory entry. */
2879	typedef const X86PDEPAE *PCX86PDEPAE;
2880
2881	/**
2882	* Page directory.
2883	*/
2884	typedef struct X86PD
2885	{
2886	/** PDE Array. */
2887	X86PDE a[X86_PG_ENTRIES];
2888	} X86PD;
2889	# ifndef VBOX_FOR_DTRACE_LIB
2890	AssertCompileSize(X86PD, 4096);
2891	# endif
2892	/** Pointer to a page directory. */
2893	typedef X86PD *PX86PD;
2894	/** Pointer to a const page directory. */
2895	typedef const X86PD *PCX86PD;
2896
2897	#endif /* !__ASSEMBLER__ */
2898
2899	/** The page shift to get the PD index. */
2900	#define X86_PD_SHIFT 22
2901	/** The PD index mask (apply to a shifted page address). */
2902	#define X86_PD_MASK 0x3ff
2903
2904
2905	#ifndef __ASSEMBLER__
2906	/**
2907	* PAE page directory.
2908	*/
2909	typedef struct X86PDPAE
2910	{
2911	/** PDE Array. */
2912	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2913	} X86PDPAE;
2914	# ifndef VBOX_FOR_DTRACE_LIB
2915	AssertCompileSize(X86PDPAE, 4096);
2916	# endif
2917	/** Pointer to a PAE page directory. */
2918	typedef X86PDPAE *PX86PDPAE;
2919	/** Pointer to a const PAE page directory. */
2920	typedef const X86PDPAE *PCX86PDPAE;
2921	#endif /* !__ASSEMBLER__ */
2922
2923	/** The page shift to get the PAE PD index. */
2924	#define X86_PD_PAE_SHIFT 21
2925	/** The PAE PD index mask (apply to a shifted page address). */
2926	#define X86_PD_PAE_MASK 0x1ff
2927
2928
2929	/** @name Page Directory Pointer Table Entry (PAE)
2930	* @{
2931	*/
2932	/** Bit 0 - P - Present bit. */
2933	#define X86_PDPE_P RT_BIT_32(0)
2934	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2935	#define X86_PDPE_RW RT_BIT_32(1)
2936	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2937	#define X86_PDPE_US RT_BIT_32(2)
2938	/** Bit 3 - PWT - Page level write thru bit. */
2939	#define X86_PDPE_PWT RT_BIT_32(3)
2940	/** Bit 4 - PCD - Page level cache disable bit. */
2941	#define X86_PDPE_PCD RT_BIT_32(4)
2942	/** Bit 5 - A - Access bit. Long Mode only. */
2943	#define X86_PDPE_A RT_BIT_32(5)
2944	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2945	#define X86_PDPE_LM_PS RT_BIT_32(7)
2946	/** Bits 9-11 - - Available for use to system software. */
2947	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2948	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2949	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2950	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2951	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2952	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2953	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2954	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2955	#define X86_PDPE_LM_NX RT_BIT_64(63)
2956	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2957	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2958	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2959	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2960	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2961	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2962	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2963	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2964
2965	#ifndef __ASSEMBLER__
2966
2967	/**
2968	* Page directory pointer table entry.
2969	*/
2970	typedef struct X86PDPEBITS
2971	{
2972	/** Flags whether(=1) or not the page is present. */
2973	uint32_t u1Present : 1;
2974	/** Chunk of reserved bits. */
2975	uint32_t u2Reserved : 2;
2976	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2977	uint32_t u1WriteThru : 1;
2978	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2979	uint32_t u1CacheDisable : 1;
2980	/** Chunk of reserved bits. */
2981	uint32_t u4Reserved : 4;
2982	/** Available for use to system software. */
2983	uint32_t u3Available : 3;
2984	/** Physical Page number of the next level - Low Part. Don't use! */
2985	uint32_t u20PageNoLow : 20;
2986	/** Physical Page number of the next level - High Part. Don't use! */
2987	uint32_t u20PageNoHigh : 20;
2988	/** MBZ bits */
2989	uint32_t u12Reserved : 12;
2990	} X86PDPEBITS;
2991	# ifndef VBOX_FOR_DTRACE_LIB
2992	AssertCompileSize(X86PDPEBITS, 8);
2993	# endif
2994	/** Pointer to a page directory pointer table entry. */
2995	typedef X86PDPEBITS *PX86PTPEBITS;
2996	/** Pointer to a const page directory pointer table entry. */
2997	typedef const X86PDPEBITS *PCX86PTPEBITS;
2998
2999	/**
3000	* Page directory pointer table entry. AMD64 version
3001	*/
3002	typedef struct X86PDPEAMD64BITS
3003	{
3004	/** Flags whether(=1) or not the page is present. */
3005	uint32_t u1Present : 1;
3006	/** Read(=0) / Write(=1) flag. */
3007	uint32_t u1Write : 1;
3008	/** User(=1) / Supervisor (=0) flag. */
3009	uint32_t u1User : 1;
3010	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3011	uint32_t u1WriteThru : 1;
3012	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3013	uint32_t u1CacheDisable : 1;
3014	/** Accessed flag.
3015	* Indicates that the page have been read or written to. */
3016	uint32_t u1Accessed : 1;
3017	/** Chunk of reserved bits. */
3018	uint32_t u3Reserved : 3;
3019	/** Available for use to system software. */
3020	uint32_t u3Available : 3;
3021	/** Physical Page number of the next level - Low Part. Don't use! */
3022	uint32_t u20PageNoLow : 20;
3023	/** Physical Page number of the next level - High Part. Don't use! */
3024	uint32_t u20PageNoHigh : 20;
3025	/** MBZ bits */
3026	uint32_t u11Reserved : 11;
3027	/** No Execute flag. */
3028	uint32_t u1NoExecute : 1;
3029	} X86PDPEAMD64BITS;
3030	# ifndef VBOX_FOR_DTRACE_LIB
3031	AssertCompileSize(X86PDPEAMD64BITS, 8);
3032	# endif
3033	/** Pointer to a page directory pointer table entry. */
3034	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3035	/** Pointer to a const page directory pointer table entry. */
3036	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3037
3038	/**
3039	* Page directory pointer table entry for 1GB page. (AMD64 only)
3040	*/
3041	typedef struct X86PDPE1GB
3042	{
3043	/** 0: Flags whether(=1) or not the page is present. */
3044	uint32_t u1Present : 1;
3045	/** 1: Read(=0) / Write(=1) flag. */
3046	uint32_t u1Write : 1;
3047	/** 2: User(=1) / Supervisor (=0) flag. */
3048	uint32_t u1User : 1;
3049	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3050	uint32_t u1WriteThru : 1;
3051	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3052	uint32_t u1CacheDisable : 1;
3053	/** 5: Accessed flag.
3054	* Indicates that the page have been read or written to. */
3055	uint32_t u1Accessed : 1;
3056	/** 6: Dirty flag for 1GB pages. */
3057	uint32_t u1Dirty : 1;
3058	/** 7: Indicates 1GB page if set. */
3059	uint32_t u1Size : 1;
3060	/** 8: Global 1GB page. */
3061	uint32_t u1Global: 1;
3062	/** 9-11: Available for use to system software. */
3063	uint32_t u3Available : 3;
3064	/** 12: PAT bit for 1GB page. */
3065	uint32_t u1PAT : 1;
3066	/** 13-29: MBZ bits. */
3067	uint32_t u17Reserved : 17;
3068	/** 30-31: Physical page number - Low Part. Don't use! */
3069	uint32_t u2PageNoLow : 2;
3070	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
3071	uint32_t u20PageNoHigh : 20;
3072	/** 52-62: MBZ bits */
3073	uint32_t u11Reserved : 11;
3074	/** 63: No Execute flag. */
3075	uint32_t u1NoExecute : 1;
3076	} X86PDPE1GB;
3077	# ifndef VBOX_FOR_DTRACE_LIB
3078	AssertCompileSize(X86PDPE1GB, 8);
3079	# endif
3080	/** Pointer to a page directory pointer table entry for a 1GB page. */
3081	typedef X86PDPE1GB *PX86PDPE1GB;
3082	/** Pointer to a const page directory pointer table entry for a 1GB page. */
3083	typedef const X86PDPE1GB *PCX86PDPE1GB;
3084
3085	/**
3086	* Page directory pointer table entry.
3087	*/
3088	typedef union X86PDPE
3089	{
3090	/** Unsigned integer view. */
3091	X86PGPAEUINT u;
3092	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3093	/** Normal view. */
3094	X86PDPEBITS n;
3095	/** AMD64 view. */
3096	X86PDPEAMD64BITS lm;
3097	/** AMD64 big view. */
3098	X86PDPE1GB b;
3099	# endif
3100	/** 8 bit unsigned integer view. */
3101	uint8_t au8[8];
3102	/** 16 bit unsigned integer view. */
3103	uint16_t au16[4];
3104	/** 32 bit unsigned integer view. */
3105	uint32_t au32[2];
3106	} X86PDPE;
3107	# ifndef VBOX_FOR_DTRACE_LIB
3108	AssertCompileSize(X86PDPE, 8);
3109	# endif
3110	/** Pointer to a page directory pointer table entry. */
3111	typedef X86PDPE *PX86PDPE;
3112	/** Pointer to a const page directory pointer table entry. */
3113	typedef const X86PDPE *PCX86PDPE;
3114
3115
3116	/**
3117	* Page directory pointer table.
3118	*/
3119	typedef struct X86PDPT
3120	{
3121	/** PDE Array. */
3122	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3123	} X86PDPT;
3124	# ifndef VBOX_FOR_DTRACE_LIB
3125	AssertCompileSize(X86PDPT, 4096);
3126	# endif
3127	/** Pointer to a page directory pointer table. */
3128	typedef X86PDPT *PX86PDPT;
3129	/** Pointer to a const page directory pointer table. */
3130	typedef const X86PDPT *PCX86PDPT;
3131
3132	#endif /* !__ASSEMBLER__ */
3133
3134	/** The page shift to get the PDPT index. */
3135	#define X86_PDPT_SHIFT 30
3136	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3137	#define X86_PDPT_MASK_PAE 0x3
3138	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3139	#define X86_PDPT_MASK_AMD64 0x1ff
3140
3141	/** @} */
3142
3143
3144	/** @name Page Map Level-4 Entry (Long Mode PAE)
3145	* @{
3146	*/
3147	/** Bit 0 - P - Present bit. */
3148	#define X86_PML4E_P RT_BIT_32(0)
3149	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3150	#define X86_PML4E_RW RT_BIT_32(1)
3151	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3152	#define X86_PML4E_US RT_BIT_32(2)
3153	/** Bit 3 - PWT - Page level write thru bit. */
3154	#define X86_PML4E_PWT RT_BIT_32(3)
3155	/** Bit 4 - PCD - Page level cache disable bit. */
3156	#define X86_PML4E_PCD RT_BIT_32(4)
3157	/** Bit 5 - A - Access bit. */
3158	#define X86_PML4E_A RT_BIT_32(5)
3159	/** Bits 9-11 - - Available for use to system software. */
3160	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
3161	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3162	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3163	/** Bits 8, 7 - - MBZ bits when NX is active. */
3164	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3165	/** Bits 63, 7 - - MBZ bits when no NX. */
3166	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3167	/** Bits 63 - NX - PAE - No execution flag. */
3168	#define X86_PML4E_NX RT_BIT_64(63)
3169
3170	#ifndef __ASSEMBLER__
3171
3172	/**
3173	* Page Map Level-4 Entry
3174	*/
3175	typedef struct X86PML4EBITS
3176	{
3177	/** Flags whether(=1) or not the page is present. */
3178	uint32_t u1Present : 1;
3179	/** Read(=0) / Write(=1) flag. */
3180	uint32_t u1Write : 1;
3181	/** User(=1) / Supervisor (=0) flag. */
3182	uint32_t u1User : 1;
3183	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
3184	uint32_t u1WriteThru : 1;
3185	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3186	uint32_t u1CacheDisable : 1;
3187	/** Accessed flag.
3188	* Indicates that the page have been read or written to. */
3189	uint32_t u1Accessed : 1;
3190	/** Chunk of reserved bits. */
3191	uint32_t u3Reserved : 3;
3192	/** Available for use to system software. */
3193	uint32_t u3Available : 3;
3194	/** Physical Page number of the next level - Low Part. Don't use! */
3195	uint32_t u20PageNoLow : 20;
3196	/** Physical Page number of the next level - High Part. Don't use! */
3197	uint32_t u20PageNoHigh : 20;
3198	/** MBZ bits */
3199	uint32_t u11Reserved : 11;
3200	/** No Execute flag. */
3201	uint32_t u1NoExecute : 1;
3202	} X86PML4EBITS;
3203	# ifndef VBOX_FOR_DTRACE_LIB
3204	AssertCompileSize(X86PML4EBITS, 8);
3205	# endif
3206	/** Pointer to a page map level-4 entry. */
3207	typedef X86PML4EBITS *PX86PML4EBITS;
3208	/** Pointer to a const page map level-4 entry. */
3209	typedef const X86PML4EBITS *PCX86PML4EBITS;
3210
3211	/**
3212	* Page Map Level-4 Entry.
3213	*/
3214	typedef union X86PML4E
3215	{
3216	/** Unsigned integer view. */
3217	X86PGPAEUINT u;
3218	# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3219	/** Normal view. */
3220	X86PML4EBITS n;
3221	# endif
3222	/** 8 bit unsigned integer view. */
3223	uint8_t au8[8];
3224	/** 16 bit unsigned integer view. */
3225	uint16_t au16[4];
3226	/** 32 bit unsigned integer view. */
3227	uint32_t au32[2];
3228	} X86PML4E;
3229	# ifndef VBOX_FOR_DTRACE_LIB
3230	AssertCompileSize(X86PML4E, 8);
3231	# endif
3232	/** Pointer to a page map level-4 entry. */
3233	typedef X86PML4E *PX86PML4E;
3234	/** Pointer to a const page map level-4 entry. */
3235	typedef const X86PML4E *PCX86PML4E;
3236
3237
3238	/**
3239	* Page Map Level-4.
3240	*/
3241	typedef struct X86PML4
3242	{
3243	/** PDE Array. */
3244	X86PML4E a[X86_PG_PAE_ENTRIES];
3245	} X86PML4;
3246	# ifndef VBOX_FOR_DTRACE_LIB
3247	AssertCompileSize(X86PML4, 4096);
3248	# endif
3249	/** Pointer to a page map level-4. */
3250	typedef X86PML4 *PX86PML4;
3251	/** Pointer to a const page map level-4. */
3252	typedef const X86PML4 *PCX86PML4;
3253
3254	#endif /* !__ASSEMBLER__ */
3255
3256	/** The page shift to get the PML4 index. */
3257	#define X86_PML4_SHIFT 39
3258	/** The PML4 index mask (apply to a shifted page address). */
3259	#define X86_PML4_MASK 0x1ff
3260
3261	/** @} */
3262
3263	/** @} */
3264
3265	/**
3266	* Intel PCID invalidation types.
3267	*/
3268	/** Individual address invalidation. */
3269	#define X86_INVPCID_TYPE_INDV_ADDR 0
3270	/** Single-context invalidation. */
3271	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3272	/** All-context including globals invalidation. */
3273	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3274	/** All-context excluding globals invalidation. */
3275	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3276	/** The maximum valid invalidation type value. */
3277	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3278
3279
3280	/** @name Special FPU integer values.
3281	* @{ */
3282	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3283	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3284	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3285	/** @} */
3286
3287	#ifndef __ASSEMBLER__
3288
3289	/**
3290	* 32-bit protected mode FSTENV image.
3291	*/
3292	typedef struct X86FSTENV32P
3293	{
3294	uint16_t FCW; /*< 0x00 /
3295	uint16_t padding1; /*< 0x02 /
3296	uint16_t FSW; /*< 0x04 /
3297	uint16_t padding2; /*< 0x06 /
3298	uint16_t FTW; /*< 0x08 /
3299	uint16_t padding3; /*< 0x0a /
3300	uint32_t FPUIP; /*< 0x0c /
3301	uint16_t FPUCS; /*< 0x10 /
3302	uint16_t FOP; /*< 0x12 /
3303	uint32_t FPUDP; /*< 0x14 /
3304	uint16_t FPUDS; /*< 0x18 /
3305	uint16_t padding4; /*< 0x1a /
3306	} X86FSTENV32P;
3307	# ifndef VBOX_FOR_DTRACE_LIB
3308	AssertCompileSize(X86FSTENV32P, 0x1c);
3309	# endif
3310	/** Pointer to a 32-bit protected mode FSTENV image. */
3311	typedef X86FSTENV32P *PX86FSTENV32P;
3312	/** Pointer to a const 32-bit protected mode FSTENV image. */
3313	typedef X86FSTENV32P const *PCX86FSTENV32P;
3314
3315
3316	/**
3317	* 80-bit MMX/FPU register type.
3318	*/
3319	typedef struct X86FPUMMX
3320	{
3321	uint8_t reg[10];
3322	} X86FPUMMX;
3323	# ifndef VBOX_FOR_DTRACE_LIB
3324	AssertCompileSize(X86FPUMMX, 10);
3325	# endif
3326	/** Pointer to a 80-bit MMX/FPU register type. */
3327	typedef X86FPUMMX *PX86FPUMMX;
3328	/** Pointer to a const 80-bit MMX/FPU register type. */
3329	typedef const X86FPUMMX *PCX86FPUMMX;
3330
3331	/** FPU (x87) register. */
3332	typedef union X86FPUREG
3333	{
3334	/** MMX view. */
3335	uint64_t mmx;
3336	/** FPU view - todo. */
3337	X86FPUMMX fpu;
3338	/** Extended precision floating point view. */
3339	RTFLOAT80U r80;
3340	/** Extended precision floating point view v2 */
3341	RTFLOAT80U2 r80Ex;
3342	/** 8-bit view. */
3343	uint8_t au8[16];
3344	/** 16-bit view. */
3345	uint16_t au16[8];
3346	/** 32-bit view. */
3347	uint32_t au32[4];
3348	/** 64-bit view. */
3349	uint64_t au64[2];
3350	/** 128-bit view. (yeah, very helpful) */
3351	uint128_t au128[1];
3352	} X86FPUREG;
3353	# ifndef VBOX_FOR_DTRACE_LIB
3354	AssertCompileSize(X86FPUREG, 16);
3355	# endif
3356	/** Pointer to a FPU register. */
3357	typedef X86FPUREG *PX86FPUREG;
3358	/** Pointer to a const FPU register. */
3359	typedef X86FPUREG const *PCX86FPUREG;
3360
3361	/** FPU (x87) register - v2 with correct size. */
3362	# pragma pack(1)
3363	typedef union X86FPUREG2
3364	{
3365	/** MMX view. */
3366	uint64_t mmx;
3367	/** FPU view - todo. */
3368	X86FPUMMX fpu;
3369	/** Extended precision floating point view. */
3370	RTFLOAT80U r80;
3371	/** 8-bit view. */
3372	uint8_t au8[10];
3373	/** 16-bit view. */
3374	uint16_t au16[5];
3375	/** 32-bit view. */
3376	uint32_t au32[2];
3377	/** 64-bit view. */
3378	uint64_t au64[1];
3379	} X86FPUREG2;
3380	# pragma pack()
3381	# ifndef VBOX_FOR_DTRACE_LIB
3382	AssertCompileSize(X86FPUREG2, 10);
3383	# endif
3384	/** Pointer to a FPU register - v2. */
3385	typedef X86FPUREG2 *PX86FPUREG2;
3386	/** Pointer to a const FPU register - v2. */
3387	typedef X86FPUREG2 const *PCX86FPUREG2;
3388
3389	/**
3390	* XMM register union.
3391	*/
3392	typedef union X86XMMREG
3393	{
3394	/** XMM Register view. */
3395	uint128_t xmm;
3396	/** 8-bit view. */
3397	uint8_t au8[16];
3398	/** 16-bit view. */
3399	uint16_t au16[8];
3400	/** 32-bit view. */
3401	uint32_t au32[4];
3402	/** 64-bit view. */
3403	uint64_t au64[2];
3404	/** Signed 8-bit view. */
3405	int8_t ai8[16];
3406	/** Signed 16-bit view. */
3407	int16_t ai16[8];
3408	/** Signed 32-bit view. */
3409	int32_t ai32[4];
3410	/** Signed 64-bit view. */
3411	int64_t ai64[2];
3412	/** 128-bit view. (yeah, very helpful) */
3413	uint128_t au128[1];
3414	/** Single precision floating point view. */
3415	RTFLOAT32U ar32[4];
3416	/** Double precision floating point view. */
3417	RTFLOAT64U ar64[2];
3418	# ifndef VBOX_FOR_DTRACE_LIB
3419	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3420	RTUINT128U uXmm;
3421	# endif
3422	} X86XMMREG;
3423	# ifndef VBOX_FOR_DTRACE_LIB
3424	AssertCompileSize(X86XMMREG, 16);
3425	# endif
3426	/** Pointer to an XMM register state. */
3427	typedef X86XMMREG *PX86XMMREG;
3428	/** Pointer to a const XMM register state. */
3429	typedef X86XMMREG const *PCX86XMMREG;
3430
3431	/**
3432	* YMM register union.
3433	*/
3434	typedef union X86YMMREG
3435	{
3436	/** YMM register view. */
3437	RTUINT256U ymm;
3438	/** 8-bit view. */
3439	uint8_t au8[32];
3440	/** 16-bit view. */
3441	uint16_t au16[16];
3442	/** 32-bit view. */
3443	uint32_t au32[8];
3444	/** 64-bit view. */
3445	uint64_t au64[4];
3446	/** 128-bit view. (yeah, very helpful) */
3447	uint128_t au128[2];
3448	/** Single precision floating point view. */
3449	RTFLOAT32U ar32[8];
3450	/** Double precision floating point view. */
3451	RTFLOAT64U ar64[4];
3452	/** XMM sub register view. */
3453	X86XMMREG aXmm[2];
3454	} X86YMMREG;
3455	# ifndef VBOX_FOR_DTRACE_LIB
3456	AssertCompileSize(X86YMMREG, 32);
3457	# endif
3458	/** Pointer to an YMM register state. */
3459	typedef X86YMMREG *PX86YMMREG;
3460	/** Pointer to a const YMM register state. */
3461	typedef X86YMMREG const *PCX86YMMREG;
3462
3463	/**
3464	* ZMM register union.
3465	*/
3466	typedef union X86ZMMREG
3467	{
3468	/** 8-bit view. */
3469	uint8_t au8[64];
3470	/** 16-bit view. */
3471	uint16_t au16[32];
3472	/** 32-bit view. */
3473	uint32_t au32[16];
3474	/** 64-bit view. */
3475	uint64_t au64[8];
3476	/** 128-bit view. (yeah, very helpful) */
3477	uint128_t au128[4];
3478	/** Single precision floating point view. */
3479	RTFLOAT32U ar32[16];
3480	/** Double precision floating point view. */
3481	RTFLOAT64U ar64[8];
3482	/** XMM sub register view. */
3483	X86XMMREG aXmm[4];
3484	/** YMM sub register view. */
3485	X86YMMREG aYmm[2];
3486	} X86ZMMREG;
3487	# ifndef VBOX_FOR_DTRACE_LIB
3488	AssertCompileSize(X86ZMMREG, 64);
3489	# endif
3490	/** Pointer to an ZMM register state. */
3491	typedef X86ZMMREG *PX86ZMMREG;
3492	/** Pointer to a const ZMM register state. */
3493	typedef X86ZMMREG const *PCX86ZMMREG;
3494
3495
3496	/**
3497	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3498	*/
3499	# pragma pack(1)
3500	typedef struct X86FPUSTATE
3501	{
3502	/** 0x00 - Control word. */
3503	uint16_t FCW;
3504	/** 0x02 - Alignment word */
3505	uint16_t Dummy1;
3506	/** 0x04 - Status word. */
3507	uint16_t FSW;
3508	/** 0x06 - Alignment word */
3509	uint16_t Dummy2;
3510	/** 0x08 - Tag word */
3511	uint16_t FTW;
3512	/** 0x0a - Alignment word */
3513	uint16_t Dummy3;
3514
3515	/** 0x0c - Instruction pointer. */
3516	uint32_t FPUIP;
3517	/** 0x10 - Code selector. */
3518	uint16_t CS;
3519	/** 0x12 - Opcode. */
3520	uint16_t FOP;
3521	/** 0x14 - Data pointer. */
3522	uint32_t FPUOO;
3523	/** 0x18 - FOS. */
3524	uint16_t FPUOS;
3525	/** 0x0a - Alignment word */
3526	uint16_t Dummy4;
3527	/** 0x1c - FPU register. */
3528	X86FPUREG2 regs[8];
3529	} X86FPUSTATE;
3530	# pragma pack()
3531	AssertCompileSize(X86FPUSTATE, 108);
3532	/** Pointer to a FPU state. */
3533	typedef X86FPUSTATE *PX86FPUSTATE;
3534	/** Pointer to a const FPU state. */
3535	typedef const X86FPUSTATE *PCX86FPUSTATE;
3536
3537	/**
3538	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3539	*/
3540	# pragma pack(1)
3541	typedef struct X86FXSTATE
3542	{
3543	/** 0x00 - Control word. */
3544	uint16_t FCW;
3545	/** 0x02 - Status word. */
3546	uint16_t FSW;
3547	/** 0x04 - Tag word. (The upper byte is always zero.) */
3548	uint16_t FTW;
3549	/** 0x06 - Opcode. */
3550	uint16_t FOP;
3551	/** 0x08 - Instruction pointer. */
3552	uint32_t FPUIP;
3553	/** 0x0c - Code selector. */
3554	uint16_t CS;
3555	uint16_t Rsrvd1;
3556	/** 0x10 - Data pointer. */
3557	uint32_t FPUDP;
3558	/** 0x14 - Data segment */
3559	uint16_t DS;
3560	/** 0x16 */
3561	uint16_t Rsrvd2;
3562	/** 0x18 */
3563	uint32_t MXCSR;
3564	/** 0x1c */
3565	uint32_t MXCSR_MASK;
3566	/** 0x20 - FPU registers. */
3567	X86FPUREG aRegs[8];
3568	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3569	X86XMMREG aXMM[16];
3570	/* - offset 416 - */
3571	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3572	/* - offset 464 - Software usable reserved bits. */
3573	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3574	} X86FXSTATE;
3575	# pragma pack()
3576	/** Pointer to a FPU Extended state. */
3577	typedef X86FXSTATE *PX86FXSTATE;
3578	/** Pointer to a const FPU Extended state. */
3579	typedef const X86FXSTATE *PCX86FXSTATE;
3580
3581	#endif /* !__ASSEMBLER__ */
3582
3583
3584	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3585	* magic. Don't forget to update x86.mac if you change this! */
3586	#define X86_OFF_FXSTATE_RSVD 0x1d0
3587	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3588	* forget to update x86.mac if you change this!
3589	* @todo r=bird: This has nothing what-so-ever to do here.... */
3590	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3591	#ifndef VBOX_FOR_DTRACE_LIB
3592	AssertCompileSize(X86FXSTATE, 512);
3593	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3594	#endif
3595
3596	/** @name FPU status word flags.
3597	* @{ */
3598	/** Exception Flag: Invalid operation. */
3599	#define X86_FSW_IE RT_BIT_32(0)
3600	#define X86_FSW_IE_BIT 0
3601	/** Exception Flag: Denormalized operand. */
3602	#define X86_FSW_DE RT_BIT_32(1)
3603	#define X86_FSW_DE_BIT 1
3604	/** Exception Flag: Zero divide. */
3605	#define X86_FSW_ZE RT_BIT_32(2)
3606	#define X86_FSW_ZE_BIT 2
3607	/** Exception Flag: Overflow. */
3608	#define X86_FSW_OE RT_BIT_32(3)
3609	#define X86_FSW_OE_BIT 3
3610	/** Exception Flag: Underflow. */
3611	#define X86_FSW_UE RT_BIT_32(4)
3612	#define X86_FSW_UE_BIT 4
3613	/** Exception Flag: Precision. */
3614	#define X86_FSW_PE RT_BIT_32(5)
3615	#define X86_FSW_PE_BIT 5
3616	/** Stack fault. */
3617	#define X86_FSW_SF RT_BIT_32(6)
3618	#define X86_FSW_SF_BIT 6
3619	/** Error summary status. */
3620	#define X86_FSW_ES RT_BIT_32(7)
3621	#define X86_FSW_ES_BIT 7
3622	/** Mask of exceptions flags, excluding the summary bit. */
3623	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3624	/** Mask of exceptions flags, including the summary bit. */
3625	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3626	/** Condition code 0. */
3627	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3628	#define X86_FSW_C0_BIT 8
3629	/** Condition code 1. */
3630	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3631	#define X86_FSW_C1_BIT 9
3632	/** Condition code 2. */
3633	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3634	#define X86_FSW_C2_BIT 10
3635	/** Top of the stack mask. */
3636	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3637	/** TOP shift value. */
3638	#define X86_FSW_TOP_SHIFT 11
3639	/** Mask for getting TOP value after shifting it right. */
3640	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3641	/** Get the TOP value. */
3642	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3643	/** Get the TOP value offsetted by a_iSt (0-7). */
3644	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3645	/** Condition code 3. */
3646	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3647	#define X86_FSW_C3_BIT 14
3648	/** Mask of exceptions flags, including the summary bit. */
3649	#define X86_FSW_C_MASK UINT16_C(0x4700)
3650	/** FPU busy. */
3651	#define X86_FSW_B RT_BIT_32(15)
3652	/** For use with FPREM and FPREM1. */
3653	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3654	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3655	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3656	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3657	/** For use with FPREM and FPREM1. */
3658	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3659	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3660	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3661	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3662	/** @} */
3663
3664
3665	/** @name FPU control word flags.
3666	* @{ */
3667	/** Exception Mask: Invalid operation. */
3668	#define X86_FCW_IM RT_BIT_32(0)
3669	#define X86_FCW_IM_BIT 0
3670	/** Exception Mask: Denormalized operand. */
3671	#define X86_FCW_DM RT_BIT_32(1)
3672	#define X86_FCW_DM_BIT 1
3673	/** Exception Mask: Zero divide. */
3674	#define X86_FCW_ZM RT_BIT_32(2)
3675	#define X86_FCW_ZM_BIT 2
3676	/** Exception Mask: Overflow. */
3677	#define X86_FCW_OM RT_BIT_32(3)
3678	#define X86_FCW_OM_BIT 3
3679	/** Exception Mask: Underflow. */
3680	#define X86_FCW_UM RT_BIT_32(4)
3681	#define X86_FCW_UM_BIT 4
3682	/** Exception Mask: Precision. */
3683	#define X86_FCW_PM RT_BIT_32(5)
3684	#define X86_FCW_PM_BIT 5
3685	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3686	* @remarks This includes reserved bit 6. */
3687	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3688	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3689	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3690	/** Precision control mask. */
3691	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3692	/** Precision control shift. */
3693	#define X86_FCW_PC_SHIFT 8
3694	/** Precision control: 24-bit. */
3695	#define X86_FCW_PC_24 UINT16_C(0x0000)
3696	/** Precision control: Reserved. */
3697	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3698	/** Precision control: 53-bit. */
3699	#define X86_FCW_PC_53 UINT16_C(0x0200)
3700	/** Precision control: 64-bit. */
3701	#define X86_FCW_PC_64 UINT16_C(0x0300)
3702	/** Rounding control mask. */
3703	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3704	/** Rounding control shift. */
3705	#define X86_FCW_RC_SHIFT 10
3706	/** Rounding control: To nearest. */
3707	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3708	/** Rounding control: Down. */
3709	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3710	/** Rounding control: Up. */
3711	#define X86_FCW_RC_UP UINT16_C(0x0800)
3712	/** Rounding control: Towards zero. */
3713	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3714	/** Infinity control mask - obsolete, 8087 & 287 only. */
3715	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3716	/** Infinity control: Affine - positive infinity is distictly different from
3717	* negative infinity.
3718	* @note 8087, 287 only */
3719	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3720	/** Infinity control: Projective - positive and negative infinity are the
3721	* same (sign ignored).
3722	* @note 8087, 287 only */
3723	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3724	/** Bits which should be zero, apparently. */
3725	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3726	/** @} */
3727
3728	/** @name SSE MXCSR
3729	* @{ */
3730	/** Exception Flag: Invalid operation. */
3731	#define X86_MXCSR_IE RT_BIT_32(0)
3732	/** Exception Flag: Denormalized operand. */
3733	#define X86_MXCSR_DE RT_BIT_32(1)
3734	/** Exception Flag: Zero divide. */
3735	#define X86_MXCSR_ZE RT_BIT_32(2)
3736	/** Exception Flag: Overflow. */
3737	#define X86_MXCSR_OE RT_BIT_32(3)
3738	/** Exception Flag: Underflow. */
3739	#define X86_MXCSR_UE RT_BIT_32(4)
3740	/** Exception Flag: Precision. */
3741	#define X86_MXCSR_PE RT_BIT_32(5)
3742	/** Exception Flags: mask */
3743	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3744
3745	/** Denormals are zero. */
3746	#define X86_MXCSR_DAZ RT_BIT_32(6)
3747
3748	/** Exception Mask: Invalid operation. */
3749	#define X86_MXCSR_IM RT_BIT_32(7)
3750	/** Exception Mask: Denormalized operand. */
3751	#define X86_MXCSR_DM RT_BIT_32(8)
3752	/** Exception Mask: Zero divide. */
3753	#define X86_MXCSR_ZM RT_BIT_32(9)
3754	/** Exception Mask: Overflow. */
3755	#define X86_MXCSR_OM RT_BIT_32(10)
3756	/** Exception Mask: Underflow. */
3757	#define X86_MXCSR_UM RT_BIT_32(11)
3758	/** Exception Mask: Precision. */
3759	#define X86_MXCSR_PM RT_BIT_32(12)
3760	/** Exception Mask: mask. */
3761	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3762	/** Exception Mask: shift. */
3763	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3764
3765	/** Rounding control mask. */
3766	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3767	/** Rounding control shift. */
3768	#define X86_MXCSR_RC_SHIFT 13
3769	/** Rounding control: To nearest. */
3770	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3771	/** Rounding control: Down. */
3772	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3773	/** Rounding control: Up. */
3774	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3775	/** Rounding control: Towards zero. */
3776	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3777
3778	/** Flush-to-zero for masked underflow. */
3779	#define X86_MXCSR_FZ RT_BIT_32(15)
3780
3781	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3782	#define X86_MXCSR_MM RT_BIT_32(17)
3783	/** Bits which should be zero, apparently. */
3784	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3785	/** @} */
3786
3787	#ifndef __ASSEMBLER__
3788
3789	/**
3790	* XSAVE header.
3791	*/
3792	typedef struct X86XSAVEHDR
3793	{
3794	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3795	uint64_t bmXState;
3796	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3797	uint64_t bmXComp;
3798	/** Reserved for furture extensions, probably MBZ. */
3799	uint64_t au64Reserved[6];
3800	} X86XSAVEHDR;
3801	# ifndef VBOX_FOR_DTRACE_LIB
3802	AssertCompileSize(X86XSAVEHDR, 64);
3803	# endif
3804	/** Pointer to an XSAVE header. */
3805	typedef X86XSAVEHDR *PX86XSAVEHDR;
3806	/** Pointer to a const XSAVE header. */
3807	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3808
3809
3810	/**
3811	* The high 128-bit YMM register state (XSAVE_C_YMM).
3812	* (The lower 128-bits being in X86FXSTATE.)
3813	*/
3814	typedef struct X86XSAVEYMMHI
3815	{
3816	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3817	X86XMMREG aYmmHi[16];
3818	} X86XSAVEYMMHI;
3819	# ifndef VBOX_FOR_DTRACE_LIB
3820	AssertCompileSize(X86XSAVEYMMHI, 256);
3821	# endif
3822	/** Pointer to a high 128-bit YMM register state. */
3823	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3824	/** Pointer to a const high 128-bit YMM register state. */
3825	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3826
3827	/**
3828	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3829	*/
3830	typedef struct X86XSAVEBNDREGS
3831	{
3832	/** Array of registers (BND0...BND3). */
3833	struct
3834	{
3835	/** Lower bound. */
3836	uint64_t uLowerBound;
3837	/** Upper bound. */
3838	uint64_t uUpperBound;
3839	} aRegs[4];
3840	} X86XSAVEBNDREGS;
3841	# ifndef VBOX_FOR_DTRACE_LIB
3842	AssertCompileSize(X86XSAVEBNDREGS, 64);
3843	# endif
3844	/** Pointer to a MPX bound register state. */
3845	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3846	/** Pointer to a const MPX bound register state. */
3847	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3848
3849	/**
3850	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3851	*/
3852	typedef struct X86XSAVEBNDCFG
3853	{
3854	uint64_t fConfig;
3855	uint64_t fStatus;
3856	} X86XSAVEBNDCFG;
3857	# ifndef VBOX_FOR_DTRACE_LIB
3858	AssertCompileSize(X86XSAVEBNDCFG, 16);
3859	# endif
3860	/** Pointer to a MPX bound config and status register state. */
3861	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3862	/** Pointer to a const MPX bound config and status register state. */
3863	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3864
3865	/**
3866	* AVX-512 opmask state (XSAVE_C_OPMASK).
3867	*/
3868	typedef struct X86XSAVEOPMASK
3869	{
3870	/** The K0..K7 values. */
3871	uint64_t aKRegs[8];
3872	} X86XSAVEOPMASK;
3873	# ifndef VBOX_FOR_DTRACE_LIB
3874	AssertCompileSize(X86XSAVEOPMASK, 64);
3875	# endif
3876	/** Pointer to a AVX-512 opmask state. */
3877	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3878	/** Pointer to a const AVX-512 opmask state. */
3879	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3880
3881	/**
3882	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3883	*/
3884	typedef struct X86XSAVEZMMHI256
3885	{
3886	/** Upper 256-bits of ZMM0-15. */
3887	X86YMMREG aHi256Regs[16];
3888	} X86XSAVEZMMHI256;
3889	# ifndef VBOX_FOR_DTRACE_LIB
3890	AssertCompileSize(X86XSAVEZMMHI256, 512);
3891	# endif
3892	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3893	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3894	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3895	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3896
3897	/**
3898	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3899	*/
3900	typedef struct X86XSAVEZMM16HI
3901	{
3902	/** ZMM16 thru ZMM31. */
3903	X86ZMMREG aRegs[16];
3904	} X86XSAVEZMM16HI;
3905	# ifndef VBOX_FOR_DTRACE_LIB
3906	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3907	# endif
3908	/** Pointer to a state comprising ZMM16-32. */
3909	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3910	/** Pointer to a const state comprising ZMM16-32. */
3911	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3912
3913	/**
3914	* AMD Light weight profiling state (XSAVE_C_LWP).
3915	*
3916	* We probably won't play with this as AMD seems to be dropping from their "zen"
3917	* processor micro architecture.
3918	*/
3919	typedef struct X86XSAVELWP
3920	{
3921	/** Details when needed. */
3922	uint64_t auLater[128/8];
3923	} X86XSAVELWP;
3924	# ifndef VBOX_FOR_DTRACE_LIB
3925	AssertCompileSize(X86XSAVELWP, 128);
3926	# endif
3927
3928
3929	/**
3930	* x86 FPU/SSE/AVX/XXXX state.
3931	*
3932	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3933	* changes to this structure.
3934	*/
3935	typedef struct X86XSAVEAREA
3936	{
3937	/** The x87 and SSE region (or legacy region if you like). */
3938	X86FXSTATE x87;
3939	/** The XSAVE header. */
3940	X86XSAVEHDR Hdr;
3941	/** Beyond the header, there isn't really a fixed layout, but we can
3942	generally assume the YMM (AVX) register extensions are present and
3943	follows immediately. */
3944	union
3945	{
3946	/** The high 128-bit AVX registers for easy access by IEM.
3947	* @note This ASSUMES they will always be here... */
3948	X86XSAVEYMMHI YmmHi;
3949
3950	/** This is a typical layout on intel CPUs (good for debuggers). */
3951	struct
3952	{
3953	X86XSAVEYMMHI YmmHi;
3954	X86XSAVEBNDREGS BndRegs;
3955	X86XSAVEBNDCFG BndCfg;
3956	uint8_t abFudgeToMatchDocs[0xB0];
3957	X86XSAVEOPMASK Opmask;
3958	X86XSAVEZMMHI256 ZmmHi256;
3959	X86XSAVEZMM16HI Zmm16Hi;
3960	} Intel;
3961
3962	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3963	struct
3964	{
3965	X86XSAVEYMMHI YmmHi;
3966	X86XSAVELWP Lwp;
3967	} AmdBd;
3968
3969	/** To enbling static deployments that have a reasonable chance of working for
3970	* the next 3-6 CPU generations without running short on space, we allocate a
3971	* lot of extra space here, making the structure a round 8KB in size. This
3972	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3973	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3974	uint8_t ab[8192 - 512 - 64];
3975	} u;
3976	} X86XSAVEAREA;
3977	# ifndef VBOX_FOR_DTRACE_LIB
3978	AssertCompileSize(X86XSAVEAREA, 8192);
3979	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3980	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3981	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3982	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3983	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3984	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3985	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3986	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3987	# endif
3988	/** Pointer to a XSAVE area. */
3989	typedef X86XSAVEAREA *PX86XSAVEAREA;
3990	/** Pointer to a const XSAVE area. */
3991	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3992
3993	#endif /* __ASSEMBLER__ */
3994
3995
3996	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3997	* @{ */
3998	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3999	#define XSAVE_C_X87_BIT 0
4000	/** Bit 0 - x87 - Legacy FPU state. */
4001	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4002	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4003	#define XSAVE_C_SSE_BIT 1
4004	/** Bit 1 - SSE - 128-bit SSE state. */
4005	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4006	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4007	#define XSAVE_C_YMM_BIT 2
4008	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4009	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4010	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4011	#define XSAVE_C_BNDREGS_BIT 3
4012	/** Bit 3 - BNDREGS - MPX bound register state. */
4013	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4014	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4015	#define XSAVE_C_BNDCSR_BIT 4
4016	/** Bit 4 - BNDCSR - MPX bound config and status state. */
4017	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4018	/** Bit 5 - Opmask - opmask state (bit number). */
4019	#define XSAVE_C_OPMASK_BIT 5
4020	/** Bit 5 - Opmask - opmask state. */
4021	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4022	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4023	#define XSAVE_C_ZMM_HI256_BIT 6
4024	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4025	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4026	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4027	#define XSAVE_C_ZMM_16HI_BIT 7
4028	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4029	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4030	/** Bit 9 - PKRU - Protection-key state (bit number). */
4031	#define XSAVE_C_PKRU_BIT 9
4032	/** Bit 9 - PKRU - Protection-key state. */
4033	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4034	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4035	#define XSAVE_C_LWP_BIT 62
4036	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4037	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4038	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4039	#define XSAVE_C_X_BIT 63
4040	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4041	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4042	/** @} */
4043
4044
4045
4046	/** @name Selector Descriptor
4047	* @{
4048	*/
4049
4050	#ifndef __ASSEMBLER__
4051	# ifndef VBOX_FOR_DTRACE_LIB
4052	/**
4053	* Descriptor attributes (as seen by VT-x).
4054	*/
4055	typedef struct X86DESCATTRBITS
4056	{
4057	/** 00 - Segment Type. */
4058	unsigned u4Type : 4;
4059	/** 04 - Descriptor Type. System(=0) or code/data selector */
4060	unsigned u1DescType : 1;
4061	/** 05 - Descriptor Privilege level. */
4062	unsigned u2Dpl : 2;
4063	/** 07 - Flags selector present(=1) or not. */
4064	unsigned u1Present : 1;
4065	/** 08 - Segment limit 16-19. */
4066	unsigned u4LimitHigh : 4;
4067	/** 0c - Available for system software. */
4068	unsigned u1Available : 1;
4069	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4070	unsigned u1Long : 1;
4071	/** 0e - This flags meaning depends on the segment type. Try make sense out
4072	* of the intel manual yourself. */
4073	unsigned u1DefBig : 1;
4074	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
4075	* clear byte. */
4076	unsigned u1Granularity : 1;
4077	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4078	unsigned u1Unusable : 1;
4079	} X86DESCATTRBITS;
4080	# endif /* !VBOX_FOR_DTRACE_LIB */
4081	#endif /* !__ASSEMBLER__ */
4082
4083	/** @name X86DESCATTR masks
4084	* Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4085	* bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4086	* @{ */
4087	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4088	#define X86DESCATTR_DT UINT32_C(0x00000010) /*< Descriptor type: 0=system, 1=code/data /
4089	#define X86DESCATTR_DPL UINT32_C(0x00000060)
4090	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL bitfield. /
4091	#define X86DESCATTR_P UINT32_C(0x00000080)
4092	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4093	#define X86DESCATTR_AVL UINT32_C(0x00001000)
4094	#define X86DESCATTR_L UINT32_C(0x00002000)
4095	#define X86DESCATTR_D UINT32_C(0x00004000)
4096	#define X86DESCATTR_G UINT32_C(0x00008000)
4097	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4098	/** @} */
4099
4100
4101	#ifndef __ASSEMBLER__
4102	# pragma pack(1)
4103	typedef union X86DESCATTR
4104	{
4105	/** Unsigned integer view. */
4106	uint32_t u;
4107	# ifndef VBOX_FOR_DTRACE_LIB
4108	/** Normal view. */
4109	X86DESCATTRBITS n;
4110	# endif
4111	} X86DESCATTR;
4112	# pragma pack()
4113	/** Pointer to descriptor attributes. */
4114	typedef X86DESCATTR *PX86DESCATTR;
4115	/** Pointer to const descriptor attributes. */
4116	typedef const X86DESCATTR *PCX86DESCATTR;
4117	#endif /* !__ASSEMBLER__ */
4118
4119	#ifndef VBOX_FOR_DTRACE_LIB
4120
4121	#ifndef __ASSEMBLER__
4122	/**
4123	* Generic descriptor table entry
4124	*/
4125	# pragma pack(1)
4126	typedef struct X86DESCGENERIC
4127	{
4128	/** 00 - Limit - Low word. */
4129	unsigned u16LimitLow : 16;
4130	/** 10 - Base address - low word.
4131	* Don't try set this to 24 because MSC is doing stupid things then. */
4132	unsigned u16BaseLow : 16;
4133	/** 20 - Base address - first 8 bits of high word. */
4134	unsigned u8BaseHigh1 : 8;
4135	/** 28 - Segment Type. */
4136	unsigned u4Type : 4;
4137	/** 2c - Descriptor Type. System(=0) or code/data selector */
4138	unsigned u1DescType : 1;
4139	/** 2d - Descriptor Privilege level. */
4140	unsigned u2Dpl : 2;
4141	/** 2f - Flags selector present(=1) or not. */
4142	unsigned u1Present : 1;
4143	/** 30 - Segment limit 16-19. */
4144	unsigned u4LimitHigh : 4;
4145	/** 34 - Available for system software. */
4146	unsigned u1Available : 1;
4147	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4148	unsigned u1Long : 1;
4149	/** 36 - This flags meaning depends on the segment type. Try make sense out
4150	* of the intel manual yourself. */
4151	unsigned u1DefBig : 1;
4152	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
4153	* clear byte. */
4154	unsigned u1Granularity : 1;
4155	/** 38 - Base address - highest 8 bits. */
4156	unsigned u8BaseHigh2 : 8;
4157	} X86DESCGENERIC;
4158	# pragma pack()
4159	/** Pointer to a generic descriptor entry. */
4160	typedef X86DESCGENERIC *PX86DESCGENERIC;
4161	/** Pointer to a const generic descriptor entry. */
4162	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4163	# endif /* !__ASSEMBLER__ */
4164
4165
4166	/** @name Bit offsets of X86DESCGENERIC members.
4167	* @{*/
4168	# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
4169	# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
4170	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
4171	# define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
4172	# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
4173	# define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
4174	# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
4175	# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
4176	# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
4177	# define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
4178	# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
4179	# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
4180	# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
4181	/** @} */
4182
4183
4184	/** @name LAR mask
4185	* @{ */
4186	# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4187	# define X86LAR_F_DT UINT16_C( 0x1000)
4188	# define X86LAR_F_DPL UINT16_C( 0x6000)
4189	# define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
4190	# define X86LAR_F_P UINT16_C( 0x8000)
4191	# define X86LAR_F_AVL UINT32_C(0x00100000)
4192	# define X86LAR_F_L UINT32_C(0x00200000)
4193	# define X86LAR_F_D UINT32_C(0x00400000)
4194	# define X86LAR_F_G UINT32_C(0x00800000)
4195	/** @} */
4196
4197
4198	# ifndef __ASSEMBLER__
4199	/**
4200	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4201	*/
4202	typedef struct X86DESCGATE
4203	{
4204	/** 00 - Target code segment offset - Low word.
4205	* Ignored if task-gate. */
4206	unsigned u16OffsetLow : 16;
4207	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4208	* TSS selector if task-gate. */
4209	unsigned u16Sel : 16;
4210	/** 20 - Number of parameters for a call-gate.
4211	* Ignored if interrupt-, trap- or task-gate. */
4212	unsigned u5ParmCount : 5;
4213	/** 25 - Reserved / ignored. */
4214	unsigned u3Reserved : 3;
4215	/** 28 - Segment Type. */
4216	unsigned u4Type : 4;
4217	/** 2c - Descriptor Type (0 = system). */
4218	unsigned u1DescType : 1;
4219	/** 2d - Descriptor Privilege level. */
4220	unsigned u2Dpl : 2;
4221	/** 2f - Flags selector present(=1) or not. */
4222	unsigned u1Present : 1;
4223	/** 30 - Target code segment offset - High word.
4224	* Ignored if task-gate. */
4225	unsigned u16OffsetHigh : 16;
4226	} X86DESCGATE;
4227	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4228	typedef X86DESCGATE *PX86DESCGATE;
4229	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4230	typedef const X86DESCGATE *PCX86DESCGATE;
4231	# endif /* !__ASSEMBLER__ */
4232
4233	#endif /* VBOX_FOR_DTRACE_LIB */
4234
4235	#ifndef __ASSEMBLER__
4236	/**
4237	* Descriptor table entry.
4238	*/
4239	# pragma pack(1)
4240	typedef union X86DESC
4241	{
4242	# ifndef VBOX_FOR_DTRACE_LIB
4243	/** Generic descriptor view. */
4244	X86DESCGENERIC Gen;
4245	/** Gate descriptor view. */
4246	X86DESCGATE Gate;
4247	# endif
4248	/** 8 bit unsigned integer view. */
4249	uint8_t au8[8];
4250	/** 16 bit unsigned integer view. */
4251	uint16_t au16[4];
4252	/** 32 bit unsigned integer view. */
4253	uint32_t au32[2];
4254	/** 64 bit unsigned integer view. */
4255	uint64_t au64[1];
4256	/** Unsigned integer view. */
4257	uint64_t u;
4258	} X86DESC;
4259	# ifndef VBOX_FOR_DTRACE_LIB
4260	AssertCompileSize(X86DESC, 8);
4261	# endif
4262	# pragma pack()
4263	/** Pointer to descriptor table entry. */
4264	typedef X86DESC *PX86DESC;
4265	/** Pointer to const descriptor table entry. */
4266	typedef const X86DESC *PCX86DESC;
4267	#endif /* !__ASSEMBLER__ */
4268
4269	/** @def X86DESC_BASE
4270	* Return the base address of a descriptor.
4271	*/
4272	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4273	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4274	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4275	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4276
4277	/** @def X86DESC_LIMIT
4278	* Return the limit of a descriptor.
4279	*/
4280	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4281	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4282	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4283
4284	/** @def X86DESC_LIMIT_G
4285	* Return the limit of a descriptor with the granularity bit taken into account.
4286	* @returns Selector limit (uint32_t).
4287	* @param a_pDesc Pointer to the descriptor.
4288	*/
4289	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4290	( (a_pDesc)->Gen.u1Granularity \
4291	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4292	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4293	)
4294
4295	/** @def X86DESC_GET_HID_ATTR
4296	* Get the descriptor attributes for the hidden register.
4297	*/
4298	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4299	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4300
4301	#ifndef __ASSEMBLER__
4302	# ifndef VBOX_FOR_DTRACE_LIB
4303
4304	/**
4305	* 64 bits generic descriptor table entry
4306	* Note: most of these bits have no meaning in long mode.
4307	*/
4308	# pragma pack(1)
4309	typedef struct X86DESC64GENERIC
4310	{
4311	/** Limit - Low word - IGNORED. */
4312	uint32_t u16LimitLow : 16;
4313	/** Base address - low word. - IGNORED
4314	* Don't try set this to 24 because MSC is doing stupid things then. */
4315	uint32_t u16BaseLow : 16;
4316	/** Base address - first 8 bits of high word. - IGNORED */
4317	uint32_t u8BaseHigh1 : 8;
4318	/** Segment Type. */
4319	uint32_t u4Type : 4;
4320	/** Descriptor Type. System(=0) or code/data selector */
4321	uint32_t u1DescType : 1;
4322	/** Descriptor Privilege level. */
4323	uint32_t u2Dpl : 2;
4324	/** Flags selector present(=1) or not. */
4325	uint32_t u1Present : 1;
4326	/** Segment limit 16-19. - IGNORED */
4327	uint32_t u4LimitHigh : 4;
4328	/** Available for system software. - IGNORED */
4329	uint32_t u1Available : 1;
4330	/** Long mode flag. */
4331	uint32_t u1Long : 1;
4332	/** This flags meaning depends on the segment type. Try make sense out
4333	* of the intel manual yourself. */
4334	uint32_t u1DefBig : 1;
4335	/** Granularity of the limit. If set 4KB granularity is used, if
4336	* clear byte. - IGNORED */
4337	uint32_t u1Granularity : 1;
4338	/** Base address - highest 8 bits. - IGNORED */
4339	uint32_t u8BaseHigh2 : 8;
4340	/** Base address - bits 63-32. */
4341	uint32_t u32BaseHigh3 : 32;
4342	uint32_t u8Reserved : 8;
4343	uint32_t u5Zeros : 5;
4344	uint32_t u19Reserved : 19;
4345	} X86DESC64GENERIC;
4346	# pragma pack()
4347	/** Pointer to a generic descriptor entry. */
4348	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4349	/** Pointer to a const generic descriptor entry. */
4350	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4351
4352	/**
4353	* System descriptor table entry (64 bits)
4354	*
4355	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4356	*/
4357	# pragma pack(1)
4358	typedef struct X86DESC64SYSTEM
4359	{
4360	/** Limit - Low word. */
4361	uint32_t u16LimitLow : 16;
4362	/** Base address - low word.
4363	* Don't try set this to 24 because MSC is doing stupid things then. */
4364	uint32_t u16BaseLow : 16;
4365	/** Base address - first 8 bits of high word. */
4366	uint32_t u8BaseHigh1 : 8;
4367	/** Segment Type. */
4368	uint32_t u4Type : 4;
4369	/** Descriptor Type. System(=0) or code/data selector */
4370	uint32_t u1DescType : 1;
4371	/** Descriptor Privilege level. */
4372	uint32_t u2Dpl : 2;
4373	/** Flags selector present(=1) or not. */
4374	uint32_t u1Present : 1;
4375	/** Segment limit 16-19. */
4376	uint32_t u4LimitHigh : 4;
4377	/** Available for system software. */
4378	uint32_t u1Available : 1;
4379	/** Reserved - 0. */
4380	uint32_t u1Reserved : 1;
4381	/** This flags meaning depends on the segment type. Try make sense out
4382	* of the intel manual yourself. */
4383	uint32_t u1DefBig : 1;
4384	/** Granularity of the limit. If set 4KB granularity is used, if
4385	* clear byte. */
4386	uint32_t u1Granularity : 1;
4387	/** Base address - bits 31-24. */
4388	uint32_t u8BaseHigh2 : 8;
4389	/** Base address - bits 63-32. */
4390	uint32_t u32BaseHigh3 : 32;
4391	uint32_t u8Reserved : 8;
4392	uint32_t u5Zeros : 5;
4393	uint32_t u19Reserved : 19;
4394	} X86DESC64SYSTEM;
4395	# pragma pack()
4396	/** Pointer to a system descriptor entry. */
4397	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4398	/** Pointer to a const system descriptor entry. */
4399	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4400
4401	/**
4402	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4403	*/
4404	typedef struct X86DESC64GATE
4405	{
4406	/** Target code segment offset - Low word. */
4407	uint32_t u16OffsetLow : 16;
4408	/** Target code segment selector. */
4409	uint32_t u16Sel : 16;
4410	/** Interrupt stack table for interrupt- and trap-gates.
4411	* Ignored by call-gates. */
4412	uint32_t u3IST : 3;
4413	/** Reserved / ignored. */
4414	uint32_t u5Reserved : 5;
4415	/** Segment Type. */
4416	uint32_t u4Type : 4;
4417	/** Descriptor Type (0 = system). */
4418	uint32_t u1DescType : 1;
4419	/** Descriptor Privilege level. */
4420	uint32_t u2Dpl : 2;
4421	/** Flags selector present(=1) or not. */
4422	uint32_t u1Present : 1;
4423	/** Target code segment offset - High word.
4424	* Ignored if task-gate. */
4425	uint32_t u16OffsetHigh : 16;
4426	/** Target code segment offset - Top dword.
4427	* Ignored if task-gate. */
4428	uint32_t u32OffsetTop : 32;
4429	/** Reserved / ignored / must be zero.
4430	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4431	uint32_t u32Reserved : 32;
4432	} X86DESC64GATE;
4433	AssertCompileSize(X86DESC64GATE, 16);
4434	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4435	typedef X86DESC64GATE *PX86DESC64GATE;
4436	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4437	typedef const X86DESC64GATE *PCX86DESC64GATE;
4438
4439	# endif /* VBOX_FOR_DTRACE_LIB */
4440
4441	/**
4442	* Descriptor table entry.
4443	*/
4444	# pragma pack(1)
4445	typedef union X86DESC64
4446	{
4447	# ifndef VBOX_FOR_DTRACE_LIB
4448	/** Generic descriptor view. */
4449	X86DESC64GENERIC Gen;
4450	/** System descriptor view. */
4451	X86DESC64SYSTEM System;
4452	/** Gate descriptor view. */
4453	X86DESC64GATE Gate;
4454	# endif
4455
4456	/** 8 bit unsigned integer view. */
4457	uint8_t au8[16];
4458	/** 16 bit unsigned integer view. */
4459	uint16_t au16[8];
4460	/** 32 bit unsigned integer view. */
4461	uint32_t au32[4];
4462	/** 64 bit unsigned integer view. */
4463	uint64_t au64[2];
4464	} X86DESC64;
4465	# ifndef VBOX_FOR_DTRACE_LIB
4466	AssertCompileSize(X86DESC64, 16);
4467	# endif
4468	# pragma pack()
4469	/** Pointer to descriptor table entry. */
4470	typedef X86DESC64 *PX86DESC64;
4471	/** Pointer to const descriptor table entry. */
4472	typedef const X86DESC64 *PCX86DESC64;
4473
4474	/** @def X86DESC64_BASE
4475	* Return the base of a 64-bit descriptor.
4476	*/
4477	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4478	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4479	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4480	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4481	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4482
4483
4484
4485	/** @name Host system descriptor table entry - Use with care!
4486	* @{ */
4487	/** Host system descriptor table entry. */
4488	#if HC_ARCH_BITS == 64
4489	typedef X86DESC64 X86DESCHC;
4490	#else
4491	typedef X86DESC X86DESCHC;
4492	#endif
4493	/** Pointer to a host system descriptor table entry. */
4494	#if HC_ARCH_BITS == 64
4495	typedef PX86DESC64 PX86DESCHC;
4496	#else
4497	typedef PX86DESC PX86DESCHC;
4498	#endif
4499	/** Pointer to a const host system descriptor table entry. */
4500	#if HC_ARCH_BITS == 64
4501	typedef PCX86DESC64 PCX86DESCHC;
4502	#else
4503	typedef PCX86DESC PCX86DESCHC;
4504	#endif
4505	/** @} */
4506
4507	#endif /* !__ASSEMBLER__ */
4508
4509
4510	/** @name Selector Descriptor Types.
4511	* @{
4512	*/
4513
4514	/** @name Non-System Selector Types.
4515	* @{ */
4516	/** Code(=set)/Data(=clear) bit. */
4517	#define X86_SEL_TYPE_CODE 8
4518	/** Memory(=set)/System(=clear) bit. */
4519	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4520	/** Accessed bit. */
4521	#define X86_SEL_TYPE_ACCESSED 1
4522	/** Expand down bit (for data selectors only). */
4523	#define X86_SEL_TYPE_DOWN 4
4524	/** Conforming bit (for code selectors only). */
4525	#define X86_SEL_TYPE_CONF 4
4526	/** Write bit (for data selectors only). */
4527	#define X86_SEL_TYPE_WRITE 2
4528	/** Read bit (for code selectors only). */
4529	#define X86_SEL_TYPE_READ 2
4530	/** The bit number of the code segment read bit (relative to u4Type). */
4531	#define X86_SEL_TYPE_READ_BIT 1
4532
4533	/** Read only selector type. */
4534	#define X86_SEL_TYPE_RO 0
4535	/** Accessed read only selector type. */
4536	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4537	/** Read write selector type. */
4538	#define X86_SEL_TYPE_RW 2
4539	/** Accessed read write selector type. */
4540	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4541	/** Expand down read only selector type. */
4542	#define X86_SEL_TYPE_RO_DOWN 4
4543	/** Accessed expand down read only selector type. */
4544	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4545	/** Expand down read write selector type. */
4546	#define X86_SEL_TYPE_RW_DOWN 6
4547	/** Accessed expand down read write selector type. */
4548	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4549	/** Execute only selector type. */
4550	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4551	/** Accessed execute only selector type. */
4552	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4553	/** Execute and read selector type. */
4554	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4555	/** Accessed execute and read selector type. */
4556	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4557	/** Conforming execute only selector type. */
4558	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4559	/** Accessed Conforming execute only selector type. */
4560	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4561	/** Conforming execute and write selector type. */
4562	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4563	/** Accessed Conforming execute and write selector type. */
4564	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4565	/** @} */
4566
4567
4568	/** @name System Selector Types.
4569	* @{ */
4570	/** The TSS busy bit mask. */
4571	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4572
4573	/** Undefined system selector type. */
4574	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4575	/** 286 TSS selector. */
4576	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4577	/** LDT selector. */
4578	#define X86_SEL_TYPE_SYS_LDT 2
4579	/** 286 TSS selector - Busy. */
4580	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4581	/** 286 Callgate selector. */
4582	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4583	/** Taskgate selector. */
4584	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4585	/** 286 Interrupt gate selector. */
4586	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4587	/** 286 Trapgate selector. */
4588	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4589	/** Undefined system selector. */
4590	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4591	/** 386 TSS selector. */
4592	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4593	/** Undefined system selector. */
4594	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4595	/** 386 TSS selector - Busy. */
4596	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4597	/** 386 Callgate selector. */
4598	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4599	/** Undefined system selector. */
4600	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4601	/** 386 Interruptgate selector. */
4602	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4603	/** 386 Trapgate selector. */
4604	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4605	/** @} */
4606
4607	/** @name AMD64 System Selector Types.
4608	* @{ */
4609	/** LDT selector. */
4610	#define AMD64_SEL_TYPE_SYS_LDT 2
4611	/** TSS selector - Busy. */
4612	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4613	/** TSS selector - Busy. */
4614	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4615	/** Callgate selector. */
4616	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4617	/** Interruptgate selector. */
4618	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4619	/** Trapgate selector. */
4620	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4621	/** @} */
4622
4623	/** @} */
4624
4625
4626	/** @name Descriptor Table Entry Flag Masks.
4627	* These are for the 2nd 32-bit word of a descriptor.
4628	* @{ */
4629	/** Bits 8-11 - TYPE - Descriptor type mask. */
4630	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4631	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4632	#define X86_DESC_S RT_BIT_32(12)
4633	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4634	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4635	/** Bit 15 - P - Present. */
4636	#define X86_DESC_P RT_BIT_32(15)
4637	/** Bit 20 - AVL - Available for system software. */
4638	#define X86_DESC_AVL RT_BIT_32(20)
4639	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4640	#define X86_DESC_DB RT_BIT_32(22)
4641	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4642	* used, if clear byte. */
4643	#define X86_DESC_G RT_BIT_32(23)
4644	/** @} */
4645
4646	/** @} */
4647
4648
4649	/** @name Task Segments.
4650	* @{
4651	*/
4652
4653	/**
4654	* The minimum TSS descriptor limit for 286 tasks.
4655	*/
4656	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4657
4658	/**
4659	* The minimum TSS descriptor segment limit for 386 tasks.
4660	*/
4661	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4662
4663	#ifndef __ASSEMBLER__
4664
4665	/**
4666	* 16-bit Task Segment (TSS).
4667	*/
4668	# pragma pack(1)
4669	typedef struct X86TSS16
4670	{
4671	/** Back link to previous task. (static) */
4672	RTSEL selPrev;
4673	/** Ring-0 stack pointer. (static) */
4674	uint16_t sp0;
4675	/** Ring-0 stack segment. (static) */
4676	RTSEL ss0;
4677	/** Ring-1 stack pointer. (static) */
4678	uint16_t sp1;
4679	/** Ring-1 stack segment. (static) */
4680	RTSEL ss1;
4681	/** Ring-2 stack pointer. (static) */
4682	uint16_t sp2;
4683	/** Ring-2 stack segment. (static) */
4684	RTSEL ss2;
4685	/** IP before task switch. */
4686	uint16_t ip;
4687	/** FLAGS before task switch. */
4688	uint16_t flags;
4689	/** AX before task switch. */
4690	uint16_t ax;
4691	/** CX before task switch. */
4692	uint16_t cx;
4693	/** DX before task switch. */
4694	uint16_t dx;
4695	/** BX before task switch. */
4696	uint16_t bx;
4697	/** SP before task switch. */
4698	uint16_t sp;
4699	/** BP before task switch. */
4700	uint16_t bp;
4701	/** SI before task switch. */
4702	uint16_t si;
4703	/** DI before task switch. */
4704	uint16_t di;
4705	/** ES before task switch. */
4706	RTSEL es;
4707	/** CS before task switch. */
4708	RTSEL cs;
4709	/** SS before task switch. */
4710	RTSEL ss;
4711	/** DS before task switch. */
4712	RTSEL ds;
4713	/** LDTR before task switch. */
4714	RTSEL selLdt;
4715	} X86TSS16;
4716	# ifndef VBOX_FOR_DTRACE_LIB
4717	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4718	# endif
4719	# pragma pack()
4720	/** Pointer to a 16-bit task segment. */
4721	typedef X86TSS16 *PX86TSS16;
4722	/** Pointer to a const 16-bit task segment. */
4723	typedef const X86TSS16 *PCX86TSS16;
4724
4725
4726	/**
4727	* 32-bit Task Segment (TSS).
4728	*/
4729	# pragma pack(1)
4730	typedef struct X86TSS32
4731	{
4732	/** Back link to previous task. (static) */
4733	RTSEL selPrev;
4734	uint16_t padding1;
4735	/** Ring-0 stack pointer. (static) */
4736	uint32_t esp0;
4737	/** Ring-0 stack segment. (static) */
4738	RTSEL ss0;
4739	uint16_t padding_ss0;
4740	/** Ring-1 stack pointer. (static) */
4741	uint32_t esp1;
4742	/** Ring-1 stack segment. (static) */
4743	RTSEL ss1;
4744	uint16_t padding_ss1;
4745	/** Ring-2 stack pointer. (static) */
4746	uint32_t esp2;
4747	/** Ring-2 stack segment. (static) */
4748	RTSEL ss2;
4749	uint16_t padding_ss2;
4750	/** Page directory for the task. (static) */
4751	uint32_t cr3;
4752	/** EIP before task switch. */
4753	uint32_t eip;
4754	/** EFLAGS before task switch. */
4755	uint32_t eflags;
4756	/** EAX before task switch. */
4757	uint32_t eax;
4758	/** ECX before task switch. */
4759	uint32_t ecx;
4760	/** EDX before task switch. */
4761	uint32_t edx;
4762	/** EBX before task switch. */
4763	uint32_t ebx;
4764	/** ESP before task switch. */
4765	uint32_t esp;
4766	/** EBP before task switch. */
4767	uint32_t ebp;
4768	/** ESI before task switch. */
4769	uint32_t esi;
4770	/** EDI before task switch. */
4771	uint32_t edi;
4772	/** ES before task switch. */
4773	RTSEL es;
4774	uint16_t padding_es;
4775	/** CS before task switch. */
4776	RTSEL cs;
4777	uint16_t padding_cs;
4778	/** SS before task switch. */
4779	RTSEL ss;
4780	uint16_t padding_ss;
4781	/** DS before task switch. */
4782	RTSEL ds;
4783	uint16_t padding_ds;
4784	/** FS before task switch. */
4785	RTSEL fs;
4786	uint16_t padding_fs;
4787	/** GS before task switch. */
4788	RTSEL gs;
4789	uint16_t padding_gs;
4790	/** LDTR before task switch. */
4791	RTSEL selLdt;
4792	uint16_t padding_ldt;
4793	/** Debug trap flag */
4794	uint16_t fDebugTrap;
4795	/** Offset relative to the TSS of the start of the I/O Bitmap
4796	* and the end of the interrupt redirection bitmap. */
4797	uint16_t offIoBitmap;
4798	} X86TSS32;
4799	# pragma pack()
4800	/** Pointer to task segment. */
4801	typedef X86TSS32 *PX86TSS32;
4802	/** Pointer to const task segment. */
4803	typedef const X86TSS32 *PCX86TSS32;
4804	# ifndef VBOX_FOR_DTRACE_LIB
4805	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4806	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4807	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4808	# endif
4809
4810	/**
4811	* 64-bit Task segment.
4812	*/
4813	# pragma pack(1)
4814	typedef struct X86TSS64
4815	{
4816	/** Reserved. */
4817	uint32_t u32Reserved;
4818	/** Ring-0 stack pointer. (static) */
4819	uint64_t rsp0;
4820	/** Ring-1 stack pointer. (static) */
4821	uint64_t rsp1;
4822	/** Ring-2 stack pointer. (static) */
4823	uint64_t rsp2;
4824	/** Reserved. */
4825	uint32_t u32Reserved2[2];
4826	/* IST */
4827	uint64_t ist1;
4828	uint64_t ist2;
4829	uint64_t ist3;
4830	uint64_t ist4;
4831	uint64_t ist5;
4832	uint64_t ist6;
4833	uint64_t ist7;
4834	/* Reserved. */
4835	uint16_t u16Reserved[5];
4836	/** Offset relative to the TSS of the start of the I/O Bitmap
4837	* and the end of the interrupt redirection bitmap. */
4838	uint16_t offIoBitmap;
4839	} X86TSS64;
4840	# pragma pack()
4841	/** Pointer to a 64-bit task segment. */
4842	typedef X86TSS64 *PX86TSS64;
4843	/** Pointer to a const 64-bit task segment. */
4844	typedef const X86TSS64 *PCX86TSS64;
4845	# ifndef VBOX_FOR_DTRACE_LIB
4846	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4847	# endif
4848
4849	#endif /* !__ASSEMBLER__ */
4850
4851	/** @} */
4852
4853
4854	/** @name Selectors.
4855	* @{
4856	*/
4857
4858	/**
4859	* The shift used to convert a selector from and to index an index (C).
4860	*/
4861	#define X86_SEL_SHIFT 3
4862
4863	/**
4864	* The mask used to mask off the table indicator and RPL of an selector.
4865	*/
4866	#define X86_SEL_MASK 0xfff8U
4867
4868	/**
4869	* The mask used to mask off the RPL of an selector.
4870	* This is suitable for checking for NULL selectors.
4871	*/
4872	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4873
4874	/**
4875	* The bit indicating that a selector is in the LDT and not in the GDT.
4876	*/
4877	#define X86_SEL_LDT 0x0004U
4878
4879	/**
4880	* The bit mask for getting the RPL of a selector.
4881	*/
4882	#define X86_SEL_RPL 0x0003U
4883
4884	/**
4885	* The mask covering both RPL and LDT.
4886	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4887	* checks.
4888	*/
4889	#define X86_SEL_RPL_LDT 0x0007U
4890
4891	/** @} */
4892
4893
4894	#ifndef __ASSEMBLER__
4895	/**
4896	* x86 Exceptions/Faults/Traps.
4897	*/
4898	typedef enum X86XCPT
4899	{
4900	/** \#DE - Divide error. */
4901	X86_XCPT_DE = 0x00,
4902	/** \#DB - Debug event (single step, DRx, ..) */
4903	X86_XCPT_DB = 0x01,
4904	/** NMI - Non-Maskable Interrupt */
4905	X86_XCPT_NMI = 0x02,
4906	/** \#BP - Breakpoint (INT3). */
4907	X86_XCPT_BP = 0x03,
4908	/** \#OF - Overflow (INTO). */
4909	X86_XCPT_OF = 0x04,
4910	/** \#BR - Bound range exceeded (BOUND). */
4911	X86_XCPT_BR = 0x05,
4912	/** \#UD - Undefined opcode. */
4913	X86_XCPT_UD = 0x06,
4914	/** \#NM - Device not available (math coprocessor device). */
4915	X86_XCPT_NM = 0x07,
4916	/** \#DF - Double fault. */
4917	X86_XCPT_DF = 0x08,
4918	/** ??? - Coprocessor segment overrun (obsolete). */
4919	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4920	/** \#TS - Taskswitch (TSS). */
4921	X86_XCPT_TS = 0x0a,
4922	/** \#NP - Segment no present. */
4923	X86_XCPT_NP = 0x0b,
4924	/** \#SS - Stack segment fault. */
4925	X86_XCPT_SS = 0x0c,
4926	/** \#GP - General protection fault. */
4927	X86_XCPT_GP = 0x0d,
4928	/** \#PF - Page fault. */
4929	X86_XCPT_PF = 0x0e,
4930	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4931	/** \#MF - Math fault (FPU). */
4932	X86_XCPT_MF = 0x10,
4933	/** \#AC - Alignment check. */
4934	X86_XCPT_AC = 0x11,
4935	/** \#MC - Machine check. */
4936	X86_XCPT_MC = 0x12,
4937	/** \#XF - SIMD Floating-Point Exception. */
4938	X86_XCPT_XF = 0x13,
4939	/** \#VE - Virtualization Exception (Intel only). */
4940	X86_XCPT_VE = 0x14,
4941	/** \#CP - Control Protection Exception. */
4942	X86_XCPT_CP = 0x15,
4943	/** \#VC - VMM Communication Exception (AMD only). */
4944	X86_XCPT_VC = 0x1d,
4945	/** \#SX - Security Exception (AMD only). */
4946	X86_XCPT_SX = 0x1e
4947	} X86XCPT;
4948	/** Pointer to a x86 exception code. */
4949	typedef X86XCPT *PX86XCPT;
4950	/** Pointer to a const x86 exception code. */
4951	typedef const X86XCPT *PCX86XCPT;
4952	#endif /* !__ASSEMBLER__ */
4953	/** The last valid (currently reserved) exception value. */
4954	#define X86_XCPT_LAST 0x1f
4955
4956
4957	/** @name Trap Error Codes
4958	* @{
4959	*/
4960	/** External indicator. */
4961	#define X86_TRAP_ERR_EXTERNAL 1
4962	/** IDT indicator. */
4963	#define X86_TRAP_ERR_IDT 2
4964	/** Descriptor table indicator - If set LDT, if clear GDT. */
4965	#define X86_TRAP_ERR_TI 4
4966	/** Mask for getting the selector. */
4967	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4968	/** Shift for getting the selector table index (C type index). */
4969	#define X86_TRAP_ERR_SEL_SHIFT 3
4970	/** @} */
4971
4972
4973	/** @name \#PF Trap Error Codes
4974	* @{
4975	*/
4976	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4977	#define X86_TRAP_PF_P RT_BIT_32(0)
4978	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4979	#define X86_TRAP_PF_RW RT_BIT_32(1)
4980	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4981	#define X86_TRAP_PF_US RT_BIT_32(2)
4982	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4983	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4984	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4985	#define X86_TRAP_PF_ID RT_BIT_32(4)
4986	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4987	#define X86_TRAP_PF_PK RT_BIT_32(5)
4988	/** @} */
4989
4990	#ifndef __ASSEMBLER__
4991
4992	# pragma pack(1)
4993	/**
4994	* 16-bit IDTR.
4995	*/
4996	typedef struct X86IDTR16
4997	{
4998	/** Offset. */
4999	uint16_t offSel;
5000	/** Selector. */
5001	uint16_t uSel;
5002	} X86IDTR16, *PX86IDTR16;
5003	# pragma pack()
5004
5005	# pragma pack(1)
5006	/**
5007	* 32-bit IDTR/GDTR.
5008	*/
5009	typedef struct X86XDTR32
5010	{
5011	/** Size of the descriptor table. */
5012	uint16_t cb;
5013	/** Address of the descriptor table. */
5014	# ifndef VBOX_FOR_DTRACE_LIB
5015	uint32_t uAddr;
5016	# else
5017	uint16_t au16Addr[2];
5018	# endif
5019	} X86XDTR32, *PX86XDTR32;
5020	# pragma pack()
5021
5022	# pragma pack(1)
5023	/**
5024	* 64-bit IDTR/GDTR.
5025	*/
5026	typedef struct X86XDTR64
5027	{
5028	/** Size of the descriptor table. */
5029	uint16_t cb;
5030	/** Address of the descriptor table. */
5031	# ifndef VBOX_FOR_DTRACE_LIB
5032	uint64_t uAddr;
5033	# else
5034	uint16_t au16Addr[4];
5035	# endif
5036	} X86XDTR64, *PX86XDTR64;
5037	# pragma pack()
5038
5039	#endif /* !__ASSEMBLER__ */
5040
5041
5042	/** @name ModR/M
5043	* @{ */
5044	#define X86_MODRM_RM_MASK UINT8_C(0x07)
5045	#define X86_MODRM_REG_MASK UINT8_C(0x38)
5046	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5047	#define X86_MODRM_REG_SHIFT 3
5048	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5049	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5050	#define X86_MODRM_MOD_SHIFT 6
5051
5052	#define X86_MOD_MEM0 0 /*< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). /
5053	#define X86_MOD_MEM1 1 /*< Indirect addressing with 8-bit displacement. /
5054	#define X86_MOD_MEM4 2 /*< Indirect addressing with 32-bit displacement. /
5055	#define X86_MOD_REG 3 /*< Registers. /
5056
5057	#ifndef VBOX_FOR_DTRACE_LIB
5058	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
5059	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5060	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5061	/** @def X86_MODRM_MAKE
5062	* @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5063	* @param a_Reg The register value (0..7).
5064	* @param a_RegMem The register or memory value (0..7). */
5065	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
5066	#endif
5067
5068	/** @} */
5069
5070	/** @name SIB
5071	* @{ */
5072	#define X86_SIB_BASE_MASK UINT8_C(0x07)
5073	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5074	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5075	#define X86_SIB_INDEX_SHIFT 3
5076	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5077	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5078	#define X86_SIB_SCALE_SHIFT 6
5079	#ifndef VBOX_FOR_DTRACE_LIB
5080	/** @def X86_SIB_MAKE
5081	* @param a_BaseReg The base register value (0..7).
5082	* @param a_IndexReg The index register value (0..7).
5083	* @param a_Scale The left shift (0..3) to be applied to the index
5084	* register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5085	* */
5086	# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5087	(((a_Scale) << X86_SIB_SCALE_SHIFT) \| ((a_IndexReg) << X86_SIB_INDEX_SHIFT) \| (a_BaseReg))
5088
5089	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
5090	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5091	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5092	#endif
5093	/** @} */
5094
5095	/** @name General register indexes.
5096	* @{ */
5097	#define X86_GREG_xAX 0
5098	#define X86_GREG_xCX 1
5099	#define X86_GREG_xDX 2
5100	#define X86_GREG_xBX 3
5101	#define X86_GREG_xSP 4
5102	#define X86_GREG_xBP 5
5103	#define X86_GREG_xSI 6
5104	#define X86_GREG_xDI 7
5105	#define X86_GREG_x8 8
5106	#define X86_GREG_x9 9
5107	#define X86_GREG_x10 10
5108	#define X86_GREG_x11 11
5109	#define X86_GREG_x12 12
5110	#define X86_GREG_x13 13
5111	#define X86_GREG_x14 14
5112	#define X86_GREG_x15 15
5113	/** @} */
5114	/** General register count. */
5115	#define X86_GREG_COUNT 16
5116
5117	/** @name X86_SREG_XXX - Segment register indexes.
5118	* @{ */
5119	#define X86_SREG_ES 0
5120	#define X86_SREG_CS 1
5121	#define X86_SREG_SS 2
5122	#define X86_SREG_DS 3
5123	#define X86_SREG_FS 4
5124	#define X86_SREG_GS 5
5125	/** @} */
5126	/** Segment register count. */
5127	#define X86_SREG_COUNT 6
5128
5129
5130	/** @name X86_OP_XXX - Prefixes
5131	* @{ */
5132	#define X86_OP_PRF_CS UINT8_C(0x2e)
5133	#define X86_OP_PRF_SS UINT8_C(0x36)
5134	#define X86_OP_PRF_DS UINT8_C(0x3e)
5135	#define X86_OP_PRF_ES UINT8_C(0x26)
5136	#define X86_OP_PRF_FS UINT8_C(0x64)
5137	#define X86_OP_PRF_GS UINT8_C(0x65)
5138	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5139	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5140	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5141	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5142	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5143	#define X86_OP_REX UINT8_C(0x40)
5144	#define X86_OP_REX_B UINT8_C(0x41)
5145	#define X86_OP_REX_X UINT8_C(0x42)
5146	#define X86_OP_REX_R UINT8_C(0x44)
5147	#define X86_OP_REX_W UINT8_C(0x48)
5148	/** @} */
5149
5150
5151	/** @} */
5152
5153	#endif /* !IPRT_INCLUDED_x86_h */
5154

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source: vbox/trunk/include/iprt/x86.h@ 103224

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