| 1 | /** @file
|
|---|
| 2 | * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
|
|---|
| 3 | */
|
|---|
| 4 |
|
|---|
| 5 | /*
|
|---|
| 6 | * Copyright (C) 2023 Oracle and/or its affiliates.
|
|---|
| 7 | *
|
|---|
| 8 | * This file is part of VirtualBox base platform packages, as
|
|---|
| 9 | * available from https://www.virtualbox.org.
|
|---|
| 10 | *
|
|---|
| 11 | * This program is free software; you can redistribute it and/or
|
|---|
| 12 | * modify it under the terms of the GNU General Public License
|
|---|
| 13 | * as published by the Free Software Foundation, in version 3 of the
|
|---|
| 14 | * License.
|
|---|
| 15 | *
|
|---|
| 16 | * This program is distributed in the hope that it will be useful, but
|
|---|
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|---|
| 19 | * General Public License for more details.
|
|---|
| 20 | *
|
|---|
| 21 | * You should have received a copy of the GNU General Public License
|
|---|
| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
|
|---|
| 23 | *
|
|---|
| 24 | * The contents of this file may alternatively be used under the terms
|
|---|
| 25 | * of the Common Development and Distribution License Version 1.0
|
|---|
| 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
|
|---|
| 27 | * in the VirtualBox distribution, in which case the provisions of the
|
|---|
| 28 | * CDDL are applicable instead of those of the GPL.
|
|---|
| 29 | *
|
|---|
| 30 | * You may elect to license modified versions of this file under the
|
|---|
| 31 | * terms and conditions of either the GPL or the CDDL or both.
|
|---|
| 32 | *
|
|---|
| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
|
|---|
| 34 | */
|
|---|
| 35 |
|
|---|
| 36 | #ifndef IPRT_INCLUDED_armv8_h
|
|---|
| 37 | #define IPRT_INCLUDED_armv8_h
|
|---|
| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
|
|---|
| 39 | # pragma once
|
|---|
| 40 | #endif
|
|---|
| 41 |
|
|---|
| 42 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 43 | # include <iprt/types.h>
|
|---|
| 44 | # include <iprt/assert.h>
|
|---|
| 45 | #else
|
|---|
| 46 | # pragma D depends_on library vbox-types.d
|
|---|
| 47 | #endif
|
|---|
| 48 |
|
|---|
| 49 | /** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
|
|---|
| 50 | * @ingroup grp_rt
|
|---|
| 51 | * @{
|
|---|
| 52 | */
|
|---|
| 53 |
|
|---|
| 54 | /**
|
|---|
| 55 | * SPSR_EL2 (according to chapter C5.2.19)
|
|---|
| 56 | */
|
|---|
| 57 | typedef union ARMV8SPSREL2
|
|---|
| 58 | {
|
|---|
| 59 | /** The plain unsigned view. */
|
|---|
| 60 | uint64_t u;
|
|---|
| 61 | /** The 8-bit view. */
|
|---|
| 62 | uint8_t au8[8];
|
|---|
| 63 | /** The 16-bit view. */
|
|---|
| 64 | uint16_t au16[4];
|
|---|
| 65 | /** The 32-bit view. */
|
|---|
| 66 | uint32_t au32[2];
|
|---|
| 67 | /** The 64-bit view. */
|
|---|
| 68 | uint64_t u64;
|
|---|
| 69 | } ARMV8SPSREL2;
|
|---|
| 70 | /** Pointer to SPSR_EL2. */
|
|---|
| 71 | typedef ARMV8SPSREL2 *PARMV8SPSREL2;
|
|---|
| 72 | /** Pointer to const SPSR_EL2. */
|
|---|
| 73 | typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
|
|---|
| 74 |
|
|---|
| 75 |
|
|---|
| 76 | /** @name SPSR_EL2 (When exception is taken from AArch64 state)
|
|---|
| 77 | * @{
|
|---|
| 78 | */
|
|---|
| 79 | /** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
|
|---|
| 80 | #define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
|
|---|
| 81 | #define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
|
|---|
| 82 | /** Bit 0 - SP - Selected stack pointer. */
|
|---|
| 83 | #define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
|
|---|
| 84 | #define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
|
|---|
| 85 | /** Bit 1 - Reserved (read as zero). */
|
|---|
| 86 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
|
|---|
| 87 | /** Bit 2 - 3 - EL - Exception level. */
|
|---|
| 88 | #define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
|
|---|
| 89 | #define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
|
|---|
| 90 | #define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
|
|---|
| 91 | #define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
|
|---|
| 92 | /** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
|
|---|
| 93 | #define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
|
|---|
| 94 | #define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
|
|---|
| 95 | /** Bit 5 - Reserved (read as zero). */
|
|---|
| 96 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_5 RT_BIT_64(5)
|
|---|
| 97 | /** Bit 6 - I - FIQ interrupt mask. */
|
|---|
| 98 | #define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
|
|---|
| 99 | #define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
|
|---|
| 100 | /** Bit 7 - I - IRQ interrupt mask. */
|
|---|
| 101 | #define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
|
|---|
| 102 | #define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
|
|---|
| 103 | /** Bit 8 - A - SError interrupt mask. */
|
|---|
| 104 | #define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
|
|---|
| 105 | #define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
|
|---|
| 106 | /** Bit 9 - D - Debug Exception mask. */
|
|---|
| 107 | #define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
|
|---|
| 108 | #define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
|
|---|
| 109 | /** Bit 10 - 11 - BTYPE - Branch Type indicator. */
|
|---|
| 110 | #define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
|
|---|
| 111 | #define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
|
|---|
| 112 | #define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
|
|---|
| 113 | /** Bit 12 - SSBS - Speculative Store Bypass. */
|
|---|
| 114 | #define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
|
|---|
| 115 | #define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
|
|---|
| 116 | /** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
|
|---|
| 117 | #define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
|
|---|
| 118 | #define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
|
|---|
| 119 | /** Bit 14 - 19 - Reserved (read as zero). */
|
|---|
| 120 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
|
|---|
| 121 | | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
|
|---|
| 122 | /** Bit 20 - IL - Illegal Execution State flag. */
|
|---|
| 123 | #define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
|
|---|
| 124 | #define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
|
|---|
| 125 | /** Bit 21 - SS - Software Step flag. */
|
|---|
| 126 | #define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
|
|---|
| 127 | #define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
|
|---|
| 128 | /** Bit 22 - PAN - Privileged Access Never flag. */
|
|---|
| 129 | #define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
|
|---|
| 130 | #define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
|
|---|
| 131 | /** Bit 23 - UAO - User Access Override flag. */
|
|---|
| 132 | #define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
|
|---|
| 133 | #define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
|
|---|
| 134 | /** Bit 24 - DIT - Data Independent Timing flag. */
|
|---|
| 135 | #define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
|
|---|
| 136 | #define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
|
|---|
| 137 | /** Bit 25 - TCO - Tag Check Override flag. */
|
|---|
| 138 | #define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
|
|---|
| 139 | #define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
|
|---|
| 140 | /** Bit 26 - 27 - Reserved (read as zero). */
|
|---|
| 141 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
|
|---|
| 142 | /** Bit 28 - V - Overflow condition flag. */
|
|---|
| 143 | #define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
|
|---|
| 144 | #define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
|
|---|
| 145 | /** Bit 29 - C - Carry condition flag. */
|
|---|
| 146 | #define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
|
|---|
| 147 | #define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
|
|---|
| 148 | /** Bit 30 - Z - Zero condition flag. */
|
|---|
| 149 | #define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
|
|---|
| 150 | #define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
|
|---|
| 151 | /** Bit 31 - N - Negative condition flag. */
|
|---|
| 152 | #define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
|
|---|
| 153 | #define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
|
|---|
| 154 | /** Bit 32 - 63 - Reserved (read as zero). */
|
|---|
| 155 | #define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
|
|---|
| 156 | /** Checks whether the given SPSR value contains a AARCH64 execution state. */
|
|---|
| 157 | #define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
|
|---|
| 158 | /** @} */
|
|---|
| 159 |
|
|---|
| 160 | /** @name Aarch64 Exception levels
|
|---|
| 161 | * @{ */
|
|---|
| 162 | /** Exception Level 0 - User mode. */
|
|---|
| 163 | #define ARMV8_AARCH64_EL_0 0
|
|---|
| 164 | /** Exception Level 1 - Supervisor mode. */
|
|---|
| 165 | #define ARMV8_AARCH64_EL_1 1
|
|---|
| 166 | /** Exception Level 2 - Hypervisor mode. */
|
|---|
| 167 | #define ARMV8_AARCH64_EL_2 2
|
|---|
| 168 | /** @} */
|
|---|
| 169 |
|
|---|
| 170 |
|
|---|
| 171 | /** @name ESR_EL2 (Exception Syndrome Register, EL2)
|
|---|
| 172 | * @{
|
|---|
| 173 | */
|
|---|
| 174 | /** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
|
|---|
| 175 | #define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
|
|---|
| 176 | #define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
|
|---|
| 177 | /** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
|
|---|
| 178 | #define ARMV8_ESR_EL2_IL RT_BIT_64(25)
|
|---|
| 179 | #define ARMV8_ESR_EL2_IL_BIT 25
|
|---|
| 180 | #define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
|
|---|
| 181 | #define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
|
|---|
| 182 | /** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
|
|---|
| 183 | #define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
|
|---|
| 184 | | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
|
|---|
| 185 | #define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
|
|---|
| 186 | /** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
|
|---|
| 187 | #define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
|
|---|
| 188 | | RT_BIT_64(35) | RT_BIT_64(36))
|
|---|
| 189 | #define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
|
|---|
| 190 | /*+ @} */
|
|---|
| 191 |
|
|---|
| 192 |
|
|---|
| 193 | /** @name ESR_EL2 Exception Classes (EC)
|
|---|
| 194 | * @{ */
|
|---|
| 195 | /** Unknown exception reason. */
|
|---|
| 196 | #define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
|
|---|
| 197 | /** Trapped WF* instruction. */
|
|---|
| 198 | #define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
|
|---|
| 199 | /** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
|
|---|
| 200 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
|
|---|
| 201 | /** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
|
|---|
| 202 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
|
|---|
| 203 | /** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
|
|---|
| 204 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
|
|---|
| 205 | /** AArch32 - Trapped LDC or STC access. */
|
|---|
| 206 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
|
|---|
| 207 | /** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
|
|---|
| 208 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
|
|---|
| 209 | /** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
|
|---|
| 210 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
|
|---|
| 211 | /** AArch32 - Trapped pointer authentication instruction. */
|
|---|
| 212 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
|
|---|
| 213 | /** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
|
|---|
| 214 | #define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
|
|---|
| 215 | /** AArch32 - Trapped MRRC access (coproc == 0b1110). */
|
|---|
| 216 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
|
|---|
| 217 | /** FEAT_BTI - Branch Target Exception. */
|
|---|
| 218 | #define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
|
|---|
| 219 | /** Illegal Execution State. */
|
|---|
| 220 | #define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
|
|---|
| 221 | /** AArch32 - SVC instruction execution. */
|
|---|
| 222 | #define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
|
|---|
| 223 | /** AArch32 - HVC instruction execution. */
|
|---|
| 224 | #define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
|
|---|
| 225 | /** AArch32 - SMC instruction execution. */
|
|---|
| 226 | #define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
|
|---|
| 227 | /** AArch64 - SVC instruction execution. */
|
|---|
| 228 | #define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
|
|---|
| 229 | /** AArch64 - HVC instruction execution. */
|
|---|
| 230 | #define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
|
|---|
| 231 | /** AArch64 - SMC instruction execution. */
|
|---|
| 232 | #define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
|
|---|
| 233 | /** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
|
|---|
| 234 | #define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
|
|---|
| 235 | /** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
|
|---|
| 236 | #define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
|
|---|
| 237 | /** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
|
|---|
| 238 | #define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
|
|---|
| 239 | /** FEAT_TME - Exception from TSTART instruction. */
|
|---|
| 240 | #define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
|
|---|
| 241 | /** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
|
|---|
| 242 | #define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
|
|---|
| 243 | /** FEAT_SME - Access to SME functionality trapped. */
|
|---|
| 244 | #define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
|
|---|
| 245 | /** FEAT_RME - Exception from Granule Protection Check. */
|
|---|
| 246 | #define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
|
|---|
| 247 | /** Instruction Abort from a lower Exception level. */
|
|---|
| 248 | #define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
|
|---|
| 249 | /** Instruction Abort from the same Exception level. */
|
|---|
| 250 | #define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
|
|---|
| 251 | /** PC alignment fault exception. */
|
|---|
| 252 | #define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
|
|---|
| 253 | /** Data Abort from a lower Exception level. */
|
|---|
| 254 | #define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
|
|---|
| 255 | /** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
|
|---|
| 256 | #define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
|
|---|
| 257 | /** SP alignment fault exception. */
|
|---|
| 258 | #define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
|
|---|
| 259 | /** FEAT_MOPS - Memory Operation Exception. */
|
|---|
| 260 | #define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
|
|---|
| 261 | /** AArch32 - Trapped floating point exception. */
|
|---|
| 262 | #define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
|
|---|
| 263 | /** AArch64 - Trapped floating point exception. */
|
|---|
| 264 | #define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
|
|---|
| 265 | /** SError interrupt. */
|
|---|
| 266 | #define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
|
|---|
| 267 | /** Breakpoint Exception from a lower Exception level. */
|
|---|
| 268 | #define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
|
|---|
| 269 | /** Breakpoint Exception from the same Exception level. */
|
|---|
| 270 | #define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
|
|---|
| 271 | /** Software Step Exception from a lower Exception level. */
|
|---|
| 272 | #define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
|
|---|
| 273 | /** Software Step Exception from the same Exception level. */
|
|---|
| 274 | #define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
|
|---|
| 275 | /** Watchpoint Exception from a lower Exception level. */
|
|---|
| 276 | #define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
|
|---|
| 277 | /** Watchpoint Exception from the same Exception level. */
|
|---|
| 278 | #define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
|
|---|
| 279 | /** AArch32 - BKPT instruction execution. */
|
|---|
| 280 | #define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
|
|---|
| 281 | /** AArch32 - Vector Catch exception. */
|
|---|
| 282 | #define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
|
|---|
| 283 | /** AArch64 - BRK instruction execution. */
|
|---|
| 284 | #define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
|
|---|
| 285 | /** @} */
|
|---|
| 286 |
|
|---|
| 287 |
|
|---|
| 288 | /** @name ISS encoding for Data Abort exceptions.
|
|---|
| 289 | * @{ */
|
|---|
| 290 | /** Bit 0 - 5 - DFSC - Data Fault Status Code. */
|
|---|
| 291 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
|
|---|
| 292 | | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
|
|---|
| 293 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
|
|---|
| 294 | /** Bit 6 - WnR - Write not Read. */
|
|---|
| 295 | #define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
|
|---|
| 296 | #define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
|
|---|
| 297 | /** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
|
|---|
| 298 | #define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
|
|---|
| 299 | #define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
|
|---|
| 300 | /** Bit 8 - CM - Cache maintenance instruction. */
|
|---|
| 301 | #define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
|
|---|
| 302 | #define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
|
|---|
| 303 | /** Bit 9 - EA - External abort type. */
|
|---|
| 304 | #define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
|
|---|
| 305 | #define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
|
|---|
| 306 | /** Bit 10 - FnV - FAR not Valid. */
|
|---|
| 307 | #define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
|
|---|
| 308 | #define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
|
|---|
| 309 | /** Bit 11 - 12 - LST - Load/Store Type. */
|
|---|
| 310 | #define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
|
|---|
| 311 | #define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
|
|---|
| 312 | /** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
|
|---|
| 313 | #define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
|
|---|
| 314 | #define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
|
|---|
| 315 | /** Bit 14 - AR - Acquire/Release semantics. */
|
|---|
| 316 | #define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
|
|---|
| 317 | #define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
|
|---|
| 318 | /** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
|
|---|
| 319 | #define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
|
|---|
| 320 | #define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
|
|---|
| 321 | /** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
|
|---|
| 322 | #define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
|
|---|
| 323 | | RT_BIT_32(19) | RT_BIT_32(20))
|
|---|
| 324 | #define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
|
|---|
| 325 | /** Bit 21 - SSE - Syndrome Sign Extend. */
|
|---|
| 326 | #define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
|
|---|
| 327 | #define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
|
|---|
| 328 | /** Bit 22 - 23 - SAS - Syndrome Access Size. */
|
|---|
| 329 | #define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
|
|---|
| 330 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
|
|---|
| 331 | /** Bit 24 - ISV - Instruction Syndrome Valid. */
|
|---|
| 332 | #define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
|
|---|
| 333 | #define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
|
|---|
| 334 |
|
|---|
| 335 |
|
|---|
| 336 | /** @name Data Fault Status Code (DFSC).
|
|---|
| 337 | * @{ */
|
|---|
| 338 | /** Address size fault, level 0 of translation or translation table base register. */
|
|---|
| 339 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
|
|---|
| 340 | /** Address size fault, level 1. */
|
|---|
| 341 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
|
|---|
| 342 | /** Address size fault, level 2. */
|
|---|
| 343 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
|
|---|
| 344 | /** Address size fault, level 3. */
|
|---|
| 345 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
|
|---|
| 346 | /** Translation fault, level 0. */
|
|---|
| 347 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
|
|---|
| 348 | /** Translation fault, level 1. */
|
|---|
| 349 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
|
|---|
| 350 | /** Translation fault, level 2. */
|
|---|
| 351 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
|
|---|
| 352 | /** Translation fault, level 3. */
|
|---|
| 353 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
|
|---|
| 354 | /** FEAT_LPA2 - Access flag fault, level 0. */
|
|---|
| 355 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
|
|---|
| 356 | /** Access flag fault, level 1. */
|
|---|
| 357 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
|
|---|
| 358 | /** Access flag fault, level 2. */
|
|---|
| 359 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
|
|---|
| 360 | /** Access flag fault, level 3. */
|
|---|
| 361 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
|
|---|
| 362 | /** FEAT_LPA2 - Permission fault, level 0. */
|
|---|
| 363 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
|
|---|
| 364 | /** Permission fault, level 1. */
|
|---|
| 365 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
|
|---|
| 366 | /** Permission fault, level 2. */
|
|---|
| 367 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
|
|---|
| 368 | /** Permission fault, level 3. */
|
|---|
| 369 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
|
|---|
| 370 | /** Synchronous External abort, not a translation table walk or hardware update of translation table. */
|
|---|
| 371 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
|
|---|
| 372 | /** FEAT_MTE2 - Synchronous Tag Check Fault. */
|
|---|
| 373 | #define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
|
|---|
| 374 | /** @todo Do the rest (lazy developer). */
|
|---|
| 375 | /** @} */
|
|---|
| 376 |
|
|---|
| 377 |
|
|---|
| 378 | /** @name SAS encoding. */
|
|---|
| 379 | /** Byte access. */
|
|---|
| 380 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
|
|---|
| 381 | /** Halfword access (uint16_t). */
|
|---|
| 382 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
|
|---|
| 383 | /** Word access (uint32_t). */
|
|---|
| 384 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
|
|---|
| 385 | /** Doubleword access (uint64_t). */
|
|---|
| 386 | #define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
|
|---|
| 387 | /** @} */
|
|---|
| 388 |
|
|---|
| 389 | /** @} */
|
|---|
| 390 |
|
|---|
| 391 | /** @} */
|
|---|
| 392 |
|
|---|
| 393 | #endif /* !IPRT_INCLUDED_armv8_h */
|
|---|
| 394 |
|
|---|
