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source: vbox/trunk/include/iprt/armv8.h@ 101246

Last change on this file since 101246 was 101246, checked in by vboxsync, 15 months ago

iprt/armv8.h,iprt/formats/dwarf.h: Arm register names. bugref:10370
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/types.h>
44# include <iprt/assert.h>
45#else
46# pragma D depends_on library vbox-types.d
47#endif
48
49/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
50 * @ingroup grp_rt
51 * @{
52 */
53
54/** @name The AArch64 register encoding - deprecated.
55 * @deprecated Use ARMV8_A64_REG_XXX instead.
56 * @todo correct code and drop these remaining ones.
57 * @{ */
58#define ARMV8_AARCH64_REG_X0 0
59#define ARMV8_AARCH64_REG_X1 1
60#define ARMV8_AARCH64_REG_X2 2
61#define ARMV8_AARCH64_REG_X3 3
62#define ARMV8_AARCH64_REG_ZR 31
63/** @} */
64
65/** @name The AArch64 general purpose register encoding.
66 * @{ */
67#define ARMV8_A64_REG_X0 0
68#define ARMV8_A64_REG_X1 1
69#define ARMV8_A64_REG_X2 2
70#define ARMV8_A64_REG_X3 3
71#define ARMV8_A64_REG_X4 4
72#define ARMV8_A64_REG_X5 5
73#define ARMV8_A64_REG_X6 6
74#define ARMV8_A64_REG_X7 7
75#define ARMV8_A64_REG_X8 8
76#define ARMV8_A64_REG_X9 9
77#define ARMV8_A64_REG_X10 10
78#define ARMV8_A64_REG_X11 11
79#define ARMV8_A64_REG_X12 12
80#define ARMV8_A64_REG_X13 13
81#define ARMV8_A64_REG_X14 14
82#define ARMV8_A64_REG_X15 15
83#define ARMV8_A64_REG_X16 16
84#define ARMV8_A64_REG_X17 17
85#define ARMV8_A64_REG_X18 18
86#define ARMV8_A64_REG_X19 19
87#define ARMV8_A64_REG_X20 20
88#define ARMV8_A64_REG_X21 21
89#define ARMV8_A64_REG_X22 22
90#define ARMV8_A64_REG_X23 23
91#define ARMV8_A64_REG_X24 24
92#define ARMV8_A64_REG_X25 25
93#define ARMV8_A64_REG_X26 26
94#define ARMV8_A64_REG_X27 27
95#define ARMV8_A64_REG_X28 28
96#define ARMV8_A64_REG_X29 29
97#define ARMV8_A64_REG_X30 30
98/** @} */
99
100/** @name The AArch64 32-bit general purpose register names.
101 * @{ */
102#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
103#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
104#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
105#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
106#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
107#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
108#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
109#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
110#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
111#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
112#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
113#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
114#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
115#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
116#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
117#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
118#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
119#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
120#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
121#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
122#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
123#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
124#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
125#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
126#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
127#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
128#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
129#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
130#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
131#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
132#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
133/** @} */
134
135/** @name The AArch64 register 31.
136 * @note Register 31 typically refers to the zero register, but can also in
137 * select case (by instruction and opecode field) refer the to stack
138 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
139 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
140 * 31 will be the zero register.
141 * @{ */
142/** The stack pointer. */
143#define ARMV8_A64_REG_SP 31
144/** The zero register. Reads as zero, writes ignored. */
145#define ARMV8_A64_REG_XZR 31
146/** The zero register, the 32-bit register name. */
147#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
148/** @} */
149
150/** @name AArch64 register aliases
151 * @{ */
152/** The link register is typically mapped to x30 as that's the default pick of
153 * the RET instruction. */
154#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
155/** Frame base pointer is typically mapped to x29. */
156#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
157/* @} */
158
159
160/** @name System register encoding.
161 * @{
162 */
163/** Mask for the op0 part of an MSR/MRS instruction */
164#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
165/** Shift for the op0 part of an MSR/MRS instruction */
166#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
167/** Returns the op0 part of the given MRS/MSR instruction. */
168#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
169/** Mask for the op1 part of an MSR/MRS instruction */
170#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
171/** Shift for the op1 part of an MSR/MRS instruction */
172#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
173/** Returns the op1 part of the given MRS/MSR instruction. */
174#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
175/** Mask for the CRn part of an MSR/MRS instruction */
176#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
177 | RT_BIT_32(15) )
178/** Shift for the CRn part of an MSR/MRS instruction */
179#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
180/** Returns the CRn part of the given MRS/MSR instruction. */
181#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
182/** Mask for the CRm part of an MSR/MRS instruction */
183#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
184 | RT_BIT_32(11) )
185/** Shift for the CRm part of an MSR/MRS instruction */
186#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
187/** Returns the CRn part of the given MRS/MSR instruction. */
188#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
189/** Mask for the op2 part of an MSR/MRS instruction */
190#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
191/** Shift for the op2 part of an MSR/MRS instruction */
192#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
193/** Returns the op2 part of the given MRS/MSR instruction. */
194#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
195/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
196#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
197 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
198 | ARMV8_AARCH64_SYSREG_OP2_MASK)
199/** @} */
200
201/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
202 * IPRT specific and not part of the ARMv8 specification. */
203#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
204 UINT16_C( (((a_Op0) & 0x3) << 14) \
205 | (((a_Op1) & 0x7) << 11) \
206 | (((a_CRn) & 0xf) << 7) \
207 | (((a_CRm) & 0xf) << 3) \
208 | ((a_Op2) & 0x7))
209/** Returns the internal system register ID from the given MRS/MSR instruction. */
210#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
211 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
212 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
213 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
214 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
215 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
216/** Encodes the given system register ID in the given MSR/MRS instruction. */
217#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
218 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
219/** @} */
220
221
222/** @name System register IDs.
223 * @{ */
224/** OSLAR_EL1 register - WO. */
225#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
226/** OSLSR_EL1 register - RO. */
227#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
228/** OSDLR_EL1 register - RW. */
229#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
230
231/** MIDR_EL1 register - RO. */
232#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
233/** MIPDR_EL1 register - RO. */
234#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
235/** REVIDR_EL1 register - RO. */
236#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
237/** ID_PFR0_EL1 register - RO. */
238#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
239/** ID_PFR1_EL1 register - RO. */
240#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
241/** ID_DFR0_EL1 register - RO. */
242#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
243/** ID_AFR0_EL1 register - RO. */
244#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
245/** ID_MMFR0_EL1 register - RO. */
246#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
247/** ID_MMFR1_EL1 register - RO. */
248#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
249/** ID_MMFR2_EL1 register - RO. */
250#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
251/** ID_MMFR3_EL1 register - RO. */
252#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
253
254/** ID_ISAR0_EL1 register - RO. */
255#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
256/** ID_ISAR1_EL1 register - RO. */
257#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
258/** ID_ISAR2_EL1 register - RO. */
259#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
260/** ID_ISAR3_EL1 register - RO. */
261#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
262/** ID_ISAR4_EL1 register - RO. */
263#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
264/** ID_ISAR5_EL1 register - RO. */
265#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
266/** ID_MMFR4_EL1 register - RO. */
267#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
268/** ID_ISAR6_EL1 register - RO. */
269#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
270
271/** MVFR0_EL1 register - RO. */
272#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
273/** MVFR1_EL1 register - RO. */
274#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
275/** MVFR2_EL1 register - RO. */
276#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
277/** ID_PFR2_EL1 register - RO. */
278#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
279/** ID_DFR1_EL1 register - RO. */
280#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
281/** ID_MMFR5_EL1 register - RO. */
282#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
283
284/** ID_AA64PFR0_EL1 register - RO. */
285#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
286/** ID_AA64PFR0_EL1 register - RO. */
287#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
288/** ID_AA64ZFR0_EL1 register - RO. */
289#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
290/** ID_AA64SMFR0_EL1 register - RO. */
291#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
292
293/** ID_AA64DFR0_EL1 register - RO. */
294#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
295/** ID_AA64DFR0_EL1 register - RO. */
296#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
297/** ID_AA64AFR0_EL1 register - RO. */
298#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
299/** ID_AA64AFR1_EL1 register - RO. */
300#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
301
302/** ID_AA64ISAR0_EL1 register - RO. */
303#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
304/** ID_AA64ISAR1_EL1 register - RO. */
305#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
306/** ID_AA64ISAR2_EL1 register - RO. */
307#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
308
309/** ID_AA64MMFR0_EL1 register - RO. */
310#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
311/** ID_AA64MMFR1_EL1 register - RO. */
312#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
313/** ID_AA64MMFR2_EL1 register - RO. */
314#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
315
316/** SCTRL_EL1 register - RW. */
317#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
318/** ACTRL_EL1 register - RW. */
319#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
320/** CPACR_EL1 register - RW. */
321#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
322/** RGSR_EL1 register - RW. */
323#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
324/** GCR_EL1 register - RW. */
325#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
326
327/** ZCR_EL1 register - RW. */
328#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
329/** TRFCR_EL1 register - RW. */
330#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
331/** SMPRI_EL1 register - RW. */
332#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
333/** SMCR_EL1 register - RW. */
334#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
335
336/** TTBR0_EL1 register - RW. */
337#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
338/** TTBR1_EL1 register - RW. */
339#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
340/** TCR_EL1 register - RW. */
341#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
342
343/** @todo APIA,APIB,APDA,APDB,APGA registers. */
344
345/** SPSR_EL1 register - RW. */
346#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
347/** ELR_EL1 register - RW. */
348#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
349
350/** SP_EL0 register - RW. */
351#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
352
353/** PSTATE.SPSel value. */
354#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
355/** PSTATE.CurrentEL value. */
356#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
357/** PSTATE.PAN value. */
358#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
359/** PSTATE.UAO value. */
360#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
361
362/** PSTATE.ALLINT value. */
363#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
364
365/** ICC_PMR_EL1 register - RW. */
366#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
367
368/** AFSR0_EL1 register - RW. */
369#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
370/** AFSR1_EL1 register - RW. */
371#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
372
373/** ESR_EL1 register - RW. */
374#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
375
376/** ERRIDR_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
378/** ERRSELR_EL1 register - RW. */
379#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
380
381/** ICC_IAR0_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
383/** ICC_EOIR0_EL1 register - WO. */
384#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
385/** ICC_HPPIR0_EL1 register - WO. */
386#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
387/** ICC_BPR0_EL1 register - RW. */
388#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
389/** ICC_AP0R0_EL1 register - RW. */
390#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
391/** ICC_AP0R1_EL1 register - RW. */
392#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
393/** ICC_AP0R2_EL1 register - RW. */
394#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
395/** ICC_AP0R3_EL1 register - RW. */
396#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
397
398/** ICC_AP1R0_EL1 register - RW. */
399#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
400/** ICC_AP1R1_EL1 register - RW. */
401#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
402/** ICC_AP1R2_EL1 register - RW. */
403#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
404/** ICC_AP1R3_EL1 register - RW. */
405#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
406/** ICC_NMIAR1_EL1 register - RO. */
407#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
408
409/** ICC_DIR_EL1 register - WO. */
410#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
411/** ICC_RPR_EL1 register - RO. */
412#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
413/** ICC_SGI1R_EL1 register - WO. */
414#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
415/** ICC_ASGI1R_EL1 register - WO. */
416#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
417/** ICC_SGI0R_EL1 register - WO. */
418#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
419
420/** ICC_IAR1_EL1 register - RO. */
421#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
422/** ICC_EOIR1_EL1 register - WO. */
423#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
424/** ICC_HPPIR1_EL1 register - RO. */
425#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
426/** ICC_BPR1_EL1 register - RW. */
427#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
428/** ICC_CTLR_EL1 register - RW. */
429#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
430/** ICC_SRE_EL1 register - RW. */
431#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
432/** ICC_IGRPEN0_EL1 register - RW. */
433#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
434/** ICC_IGRPEN1_EL1 register - RW. */
435#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
436
437/** CNTV_CTL_EL0 register - RW. */
438#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
439/** @} */
440
441
442/**
443 * SPSR_EL2 (according to chapter C5.2.19)
444 */
445typedef union ARMV8SPSREL2
446{
447 /** The plain unsigned view. */
448 uint64_t u;
449 /** The 8-bit view. */
450 uint8_t au8[8];
451 /** The 16-bit view. */
452 uint16_t au16[4];
453 /** The 32-bit view. */
454 uint32_t au32[2];
455 /** The 64-bit view. */
456 uint64_t u64;
457} ARMV8SPSREL2;
458/** Pointer to SPSR_EL2. */
459typedef ARMV8SPSREL2 *PARMV8SPSREL2;
460/** Pointer to const SPSR_EL2. */
461typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
462
463
464/** @name SPSR_EL2 (When exception is taken from AArch64 state)
465 * @{
466 */
467/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
468#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
469#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
470/** Bit 0 - SP - Selected stack pointer. */
471#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
472#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
473/** Bit 1 - Reserved (read as zero). */
474#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
475/** Bit 2 - 3 - EL - Exception level. */
476#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
477#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
478#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
479#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
480/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
481#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
482#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
483/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
484#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
485#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
486/** Bit 6 - I - FIQ interrupt mask. */
487#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
488#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
489/** Bit 7 - I - IRQ interrupt mask. */
490#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
491#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
492/** Bit 8 - A - SError interrupt mask. */
493#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
494#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
495/** Bit 9 - D - Debug Exception mask. */
496#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
497#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
498/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
499#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
500#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
501#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
502/** Bit 12 - SSBS - Speculative Store Bypass. */
503#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
504#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
505/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
506#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
507#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
508/** Bit 14 - 19 - Reserved (read as zero). */
509#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
510 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
511/** Bit 20 - IL - Illegal Execution State flag. */
512#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
513#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
514/** Bit 21 - SS - Software Step flag. */
515#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
516#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
517/** Bit 22 - PAN - Privileged Access Never flag. */
518#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
519#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
520/** Bit 23 - UAO - User Access Override flag. */
521#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
522#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
523/** Bit 24 - DIT - Data Independent Timing flag. */
524#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
525#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
526/** Bit 25 - TCO - Tag Check Override flag. */
527#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
528#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
529/** Bit 26 - 27 - Reserved (read as zero). */
530#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
531/** Bit 28 - V - Overflow condition flag. */
532#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
533#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
534/** Bit 29 - C - Carry condition flag. */
535#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
536#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
537/** Bit 30 - Z - Zero condition flag. */
538#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
539#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
540/** Bit 31 - N - Negative condition flag. */
541#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
542#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
543/** Bit 32 - 63 - Reserved (read as zero). */
544#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
545/** Checks whether the given SPSR value contains a AARCH64 execution state. */
546#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
547/** @} */
548
549/** @name Aarch64 Exception levels
550 * @{ */
551/** Exception Level 0 - User mode. */
552#define ARMV8_AARCH64_EL_0 0
553/** Exception Level 1 - Supervisor mode. */
554#define ARMV8_AARCH64_EL_1 1
555/** Exception Level 2 - Hypervisor mode. */
556#define ARMV8_AARCH64_EL_2 2
557/** @} */
558
559
560/** @name ESR_EL2 (Exception Syndrome Register, EL2)
561 * @{
562 */
563/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
564#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
565#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
566/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
567#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
568#define ARMV8_ESR_EL2_IL_BIT 25
569#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
570#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
571/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
572#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
573 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
574#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
575/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
576#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
577 | RT_BIT_64(35) | RT_BIT_64(36))
578#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
579/** @} */
580
581
582/** @name ESR_EL2 Exception Classes (EC)
583 * @{ */
584/** Unknown exception reason. */
585#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
586/** Trapped WF* instruction. */
587#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
588/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
589#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
590/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
591#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
592/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
593#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
594/** AArch32 - Trapped LDC or STC access. */
595#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
596/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
597#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
598/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
599#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
600/** AArch32 - Trapped pointer authentication instruction. */
601#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
602/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
603#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
604/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
605#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
606/** FEAT_BTI - Branch Target Exception. */
607#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
608/** Illegal Execution State. */
609#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
610/** AArch32 - SVC instruction execution. */
611#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
612/** AArch32 - HVC instruction execution. */
613#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
614/** AArch32 - SMC instruction execution. */
615#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
616/** AArch64 - SVC instruction execution. */
617#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
618/** AArch64 - HVC instruction execution. */
619#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
620/** AArch64 - SMC instruction execution. */
621#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
622/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
623#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
624/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
625#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
626/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
627#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
628/** FEAT_TME - Exception from TSTART instruction. */
629#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
630/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
631#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
632/** FEAT_SME - Access to SME functionality trapped. */
633#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
634/** FEAT_RME - Exception from Granule Protection Check. */
635#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
636/** Instruction Abort from a lower Exception level. */
637#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
638/** Instruction Abort from the same Exception level. */
639#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
640/** PC alignment fault exception. */
641#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
642/** Data Abort from a lower Exception level. */
643#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
644/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
645#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
646/** SP alignment fault exception. */
647#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
648/** FEAT_MOPS - Memory Operation Exception. */
649#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
650/** AArch32 - Trapped floating point exception. */
651#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
652/** AArch64 - Trapped floating point exception. */
653#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
654/** SError interrupt. */
655#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
656/** Breakpoint Exception from a lower Exception level. */
657#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
658/** Breakpoint Exception from the same Exception level. */
659#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
660/** Software Step Exception from a lower Exception level. */
661#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
662/** Software Step Exception from the same Exception level. */
663#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
664/** Watchpoint Exception from a lower Exception level. */
665#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
666/** Watchpoint Exception from the same Exception level. */
667#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
668/** AArch32 - BKPT instruction execution. */
669#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
670/** AArch32 - Vector Catch exception. */
671#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
672/** AArch64 - BRK instruction execution. */
673#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
674/** @} */
675
676
677/** @name ISS encoding for Data Abort exceptions.
678 * @{ */
679/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
680#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
681 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
682#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
683/** Bit 6 - WnR - Write not Read. */
684#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
685#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
686/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
687#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
688#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
689/** Bit 8 - CM - Cache maintenance instruction. */
690#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
691#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
692/** Bit 9 - EA - External abort type. */
693#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
694#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
695/** Bit 10 - FnV - FAR not Valid. */
696#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
697#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
698/** Bit 11 - 12 - LST - Load/Store Type. */
699#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
700#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
701/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
702#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
703#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
704/** Bit 14 - AR - Acquire/Release semantics. */
705#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
706#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
707/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
708#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
709#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
710/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
711#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
712 | RT_BIT_32(19) | RT_BIT_32(20))
713#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
714/** Bit 21 - SSE - Syndrome Sign Extend. */
715#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
716#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
717/** Bit 22 - 23 - SAS - Syndrome Access Size. */
718#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
719#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
720/** Bit 24 - ISV - Instruction Syndrome Valid. */
721#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
722#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
723
724
725/** @name Data Fault Status Code (DFSC).
726 * @{ */
727/** Address size fault, level 0 of translation or translation table base register. */
728#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
729/** Address size fault, level 1. */
730#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
731/** Address size fault, level 2. */
732#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
733/** Address size fault, level 3. */
734#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
735/** Translation fault, level 0. */
736#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
737/** Translation fault, level 1. */
738#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
739/** Translation fault, level 2. */
740#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
741/** Translation fault, level 3. */
742#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
743/** FEAT_LPA2 - Access flag fault, level 0. */
744#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
745/** Access flag fault, level 1. */
746#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
747/** Access flag fault, level 2. */
748#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
749/** Access flag fault, level 3. */
750#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
751/** FEAT_LPA2 - Permission fault, level 0. */
752#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
753/** Permission fault, level 1. */
754#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
755/** Permission fault, level 2. */
756#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
757/** Permission fault, level 3. */
758#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
759/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
760#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
761/** FEAT_MTE2 - Synchronous Tag Check Fault. */
762#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
763/** @todo Do the rest (lazy developer). */
764/** @} */
765
766
767/** @name SAS encoding.
768 * @{ */
769/** Byte access. */
770#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
771/** Halfword access (uint16_t). */
772#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
773/** Word access (uint32_t). */
774#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
775/** Doubleword access (uint64_t). */
776#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
777/** @} */
778
779
780/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
781 * @{ */
782/** Bit 0 - Direction flag. */
783#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
784#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
785/** Bit 1 - 4 - CRm value from the instruction. */
786#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
787 | RT_BIT_32(4))
788#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
789/** Bit 5 - 9 - Rt value from the instruction. */
790#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
791 | RT_BIT_32(8) | RT_BIT_32(9))
792#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
793/** Bit 10 - 13 - CRn value from the instruction. */
794#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
795 | RT_BIT_32(13))
796#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
797/** Bit 14 - 16 - Op2 value from the instruction. */
798#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
799#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
800/** Bit 17 - 19 - Op2 value from the instruction. */
801#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
802#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
803/** Bit 20 - 21 - Op0 value from the instruction. */
804#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
805#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
806/** Bit 22 - 24 - Reserved. */
807#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
808/** @} */
809
810
811/** @name ISS encoding for trapped HVC instruction exceptions.
812 * @{ */
813/** Bit 0 - 15 - imm16 value of the instruction. */
814#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
815#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
816/** @} */
817
818
819/** @name TCR_EL1 - Translation Control Register (EL1)
820 * @{
821 */
822/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
823#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
824 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
825#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
826/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
827#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
828#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
829/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
830#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
831#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
832/** Non cacheable. */
833# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
834/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
835# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
836/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
837# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
838/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
839# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
840/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
841#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
842#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
843/** Non cacheable. */
844# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
845/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
846# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
847/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
848# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
849/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
850# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
851/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
852#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
853#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
854/** Non shareable. */
855# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
856/** Invalid value. */
857# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
858/** Outer Shareable. */
859# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
860/** Inner Shareable. */
861# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
862/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
863#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
864#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
865/** Invalid granule size. */
866# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
867/** 16KiB granule size. */
868# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
869/** 4KiB granule size. */
870# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
871/** 64KiB granule size. */
872# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
873/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
874#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
875 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
876#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
877/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
878#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
879#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
880/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
881#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
882#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
883/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
884#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
885#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
886/** Non cacheable. */
887# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
888/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
889# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
890/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
891# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
892/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
893# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
894/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
895#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
896#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
897/** Non cacheable. */
898# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
899/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
900# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
901/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
902# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
903/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
904# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
905/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
906#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
907#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
908/** Non shareable. */
909# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
910/** Invalid value. */
911# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
912/** Outer Shareable. */
913# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
914/** Inner Shareable. */
915# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
916/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
917#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
918#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
919/** Invalid granule size. */
920# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
921/** 16KiB granule size. */
922# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
923/** 4KiB granule size. */
924# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
925/** 64KiB granule size. */
926# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
927/** Bit 32 - 34 - Intermediate Physical Address Size. */
928#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
929#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
930/** IPA - 32 bits, 4GiB. */
931# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
932/** IPA - 36 bits, 64GiB. */
933# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
934/** IPA - 40 bits, 1TiB. */
935# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
936/** IPA - 42 bits, 4TiB. */
937# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
938/** IPA - 44 bits, 16TiB. */
939# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
940/** IPA - 48 bits, 256TiB. */
941# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
942/** IPA - 52 bits, 4PiB. */
943# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
944/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
945#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
946#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
947/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
948#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
949#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
950/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
951#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
952#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
953/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
954#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
955#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
956/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
957#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
958#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
959/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
960#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
961#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
962/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
963#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
964#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
965/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
966#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
967#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
968/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
969#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
970#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
971/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
972#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
973#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
974/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
975#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
976#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
977/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
978#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
979#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
980/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
981#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
982#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
983/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
984#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
985#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
986/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
987#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
988#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
989/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
990#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
991#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
992/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
993#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
994#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
995/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
996#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
997#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
998/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
999#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1000#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1001/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1002#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1003#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1004/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1005#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1006#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1007/** Bit 57 - TCMA0 */
1008#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1009#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1010/** Bit 58 - TCMA1 */
1011#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1012#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1013/** Bit 59 - Data Sharing(?). */
1014#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1015#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1016/** @} */
1017
1018
1019/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1020 * @{
1021 */
1022/** Bit 0 - Common not Private (FEAT_TTCNP). */
1023#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1024#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1025/** Bit 1 - 47 - Translation table base address. */
1026#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1027#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1028/** Bit 48 - 63 - ASID. */
1029#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1030#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1031/** @} */
1032
1033
1034/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1035 * @{ */
1036/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1037#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1038#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1039#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1040/** @} */
1041
1042
1043/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1044 * @{ */
1045/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1046#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1047#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1048#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1049/** @} */
1050
1051
1052/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1053 * @{ */
1054/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1055#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1056#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1057#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1058/** @} */
1059
1060
1061/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1062 * @{ */
1063/** Bit 0 - Common Binary Pointer Register - RW. */
1064#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1065#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1066/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1067#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1068#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1069/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1070#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1071#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1072/** Bit 8 - 10 - Priority bits - RO. */
1073#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1074#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1075/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1076#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1077#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1078/** INTIDS are 16-bit wide. */
1079# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1080/** INTIDS are 24-bit wide. */
1081# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1082/** Bit 14 - SEI Supported - RO. */
1083#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1084#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1085/** Bit 15 - Affinity 3 Valid - RO. */
1086#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1087#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1088/** Bit 18 - Range Selector Support - RO. */
1089#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1090#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1091/** Bit 19 - Extended INTID range supported - RO. */
1092#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1093#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1094/** All RW bits. */
1095#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1096/** All RO bits (including Res0). */
1097#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1098/** @} */
1099
1100
1101/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1102 * @{ */
1103/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1104#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1105#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1106/** @} */
1107
1108
1109/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1110 * @{ */
1111/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1112#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1113#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1114/** @} */
1115
1116
1117/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1118 * @{ */
1119/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1120#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1121#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1122/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1123#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1124#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1125/** Bit 24 - 27 - The INTID of the SGI. */
1126#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1127#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1128/* Bit 28 - 31 - Reserved. */
1129/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1130#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1131#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1132/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1133#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1134#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1135/* Bit 41 - 43 - Reserved. */
1136/** Bit 44 - 47 - Range selector. */
1137#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1138#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1139/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1140#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1141#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1142/* Bit 56 - 63 - Reserved. */
1143/** @} */
1144
1145
1146/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1147 * @{ */
1148/** Bit 0 - Enables the timer. */
1149#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1150#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1151/** Bit 1 - Timer interrupt mask bit. */
1152#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1153#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1154/** Bit 2 - Timer status bit. */
1155#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1156#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1157/** @} */
1158
1159
1160/** @name OSLAR_EL1 - OS Lock Access Register.
1161 * @{ */
1162/** Bit 0 - The OS Lock status bit. */
1163#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1164#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1165/** @} */
1166
1167
1168/** @name OSLSR_EL1 - OS Lock Status Register.
1169 * @{ */
1170/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1171#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1172#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1173/** Bit 1 - The OS Lock status bit. */
1174#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1175#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1176/** Bit 2 - Not 32-bit access. */
1177#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1178#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1179/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1180#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1181#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1182/** @} */
1183
1184
1185/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1186 * @{ */
1187/* Bit 0 - 3 - Reserved. */
1188/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1189#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1190#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1191/** No AES instructions implemented. */
1192# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1193/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1194# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1195/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1196# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1197/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1198#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1199#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1200/** No SHA1 instructions implemented. */
1201# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1202/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1203# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1204/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1205#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1206#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1207/** No SHA2 instructions implemented. */
1208# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1209/** SHA256 instructions implemented (FEAT_SHA256). */
1210# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1211/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1212# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1213/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1214#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1215#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1216/** No CRC32 instructions implemented. */
1217# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1218/** CRC32 instructions implemented (FEAT_CRC32). */
1219# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1220/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1221#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1222#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1223/** No Atomic instructions implemented. */
1224# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1225/** Atomic instructions implemented (FEAT_LSE). */
1226# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1227/** Bit 24 - 27 - Indicates support for TME instructions. */
1228#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1229#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1230/** TME instructions are not implemented. */
1231# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1232/** TME instructions are implemented. */
1233# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1234/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1235#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1236#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1237/** No RDMA instructions implemented. */
1238# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1239/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1240# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1241/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1242#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1243#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1244/** No SHA3 instructions implemented. */
1245# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1246/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1247# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1248/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1249#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1250#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1251/** No SM3 instructions implemented. */
1252# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1253/** SM3 instructions implemented (FEAT_SM3). */
1254# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1255/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1256#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1257#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1258/** No SM4 instructions implemented. */
1259# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1260/** SM4 instructions implemented (FEAT_SM4). */
1261# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1262/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1263#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1264#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1265/** No Dot Product instructions implemented. */
1266# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1267/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1268# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1269/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1270#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1271#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1272/** FMLAL and FMLSL instructions are not implemented. */
1273# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1274/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1275# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1276/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1277#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1278#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1279/** No flag manipulation instructions implemented. */
1280# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1281/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1282# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1283/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1284# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1285/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1286#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1287#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1288/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1289# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1290/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1291# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1292/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1293# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1294/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1295#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1296#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1297/** No Random Number instructions implemented. */
1298# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1299/** RNDR and RDNRRS registers are implemented . */
1300# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1301/** @} */
1302
1303
1304/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1305 * @{ */
1306/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1307#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1308#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1309/** DC CVAP not supported. */
1310# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1311/** DC CVAP supported (FEAT_DPB). */
1312# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1313/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1314# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1315/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1316#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1317#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1318/** Address Authentication using the QARMA5 algorithm is not implemented. */
1319# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1320/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1321# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1322/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1323# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1324/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1325# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1326/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1327# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1328/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1329# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1330/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1331#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1332#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1333/** Address Authentication using the QARMA5 algorithm is not implemented. */
1334# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1335/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1336# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1337/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1338# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1339/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1340# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1341/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1342# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1343/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1344# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1345/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1346#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1347#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1348/** No FJCVTZS instruction implemented. */
1349# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1350/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1351# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1352/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1353#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1354#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1355/** No FCMLA and FCADD instructions implemented. */
1356# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1357/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1358# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1359/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1360#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1361#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1362/** No RCpc instructions implemented. */
1363# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1364/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1365# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1366/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1367# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1368/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1369#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1370#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1371/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1372# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1373/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1374# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1375/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1376#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1377#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1378/** Generic Authentication using an implementation defined algorithm is not implemented. */
1379# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1380/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1381# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1382/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1383#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1384#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1385/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1386# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1387/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1388# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1389/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1390#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1391#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1392/** No SB instructions implemented. */
1393# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1394/** SB instructions implemented (FEAT_SB). */
1395# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1396/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1397#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1398#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1399/** Prediction invalidation instructions are not implemented. */
1400# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1401/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1402# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1403/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1404#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1405#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1406/** BFloat16 instructions are not implemented. */
1407# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1408/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1409# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1410/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1411# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1412/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1413#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1414#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1415/** Data Gathering Hint instructions are not implemented. */
1416# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1417/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1418# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1419/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1420#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1421#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1422/** No Int8 matrix multiplication instructions implemented. */
1423# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1424/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1425# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1426/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1427#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1428#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1429/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1430# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1431/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1432# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1433/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1434#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1435#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1436/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1437# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1438/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1439# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1440/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1441# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1442/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1443# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1444/** @} */
1445
1446
1447/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1448 * @{ */
1449/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1450#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1451#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1452/** WFET and WFIT are not supported. */
1453# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1454/** WFET and WFIT are supported (FEAT_WFxT). */
1455# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1456/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1457#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1458#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1459/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1460# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1461/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1462# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1463/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1464#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1465#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1466/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1467# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1468/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1469# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1470/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1471#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1472#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1473/** Address Authentication using the QARMA3 algorithm is not implemented. */
1474# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1475/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1476# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1477/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1478# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1479/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1480# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1481/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1482# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1483/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1484# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1485/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1486#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1487#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1488/** No Memory Copy and Memory Set instructions implemented. */
1489# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1490/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1491# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1492/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1493#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1494#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1495/** BC instruction is not implemented. */
1496# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1497/** BC instruction is implemented (FEAT_HBC). */
1498# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1499/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1500#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1501#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1502/** ConstPACField() returns FALSE. */
1503# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1504/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1505# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1506/* Bit 28 - 63 - Reserved. */
1507/** @} */
1508
1509
1510/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1511 * @{ */
1512/** Bit 0 - 3 - EL0 Exception level handling. */
1513#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1514#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1515/** EL0 can be executed in AArch64 state only. */
1516# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1517/** EL0 can be executed in AArch64 and AArch32 state. */
1518# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1519/** Bit 4 - 7 - EL1 Exception level handling. */
1520#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1521#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1522/** EL1 can be executed in AArch64 state only. */
1523# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1524/** EL1 can be executed in AArch64 and AArch32 state. */
1525# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1526/** Bit 8 - 11 - EL2 Exception level handling. */
1527#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1528#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1529/** EL2 is not implemented. */
1530# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1531/** EL2 can be executed in AArch64 state only. */
1532# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1533/** EL2 can be executed in AArch64 and AArch32 state. */
1534# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1535/** Bit 12 - 15 - EL3 Exception level handling. */
1536#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1537#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1538/** EL3 is not implemented. */
1539# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1540/** EL3 can be executed in AArch64 state only. */
1541# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1542/** EL3 can be executed in AArch64 and AArch32 state. */
1543# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1544/** Bit 16 - 19 - Floating-point support. */
1545#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1546#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1547/** Floating-point is implemented and support single and double precision. */
1548# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1549/** Floating-point is implemented and support single, double and half precision. */
1550# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1551/** Floating-point is not implemented. */
1552# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1553/** Bit 20 - 23 - Advanced SIMD support. */
1554#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1555#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1556/** Advanced SIMD is implemented and support single and double precision. */
1557# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1558/** Advanced SIMD is implemented and support single, double and half precision. */
1559# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1560/** Advanced SIMD is not implemented. */
1561# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1562/** Bit 24 - 27 - System register GIC CPU interface support. */
1563#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1564#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1565/** GIC CPU interface system registers are not implemented. */
1566# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1567/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1568# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1569/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1570# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1571/** Bit 28 - 31 - RAS Extension version. */
1572#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1573#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1574/** No RAS extension. */
1575# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1576/** RAS Extension implemented. */
1577# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1578/** FEAT_RASv1p1 implemented. */
1579# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1580/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1581#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1582#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1583/** SVE is not supported. */
1584# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1585/** SVE is supported. */
1586# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1587/** Bit 36 - 39 - Secure EL2 support. */
1588#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1589#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1590/** Secure EL2 is not supported. */
1591# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1592/** Secure EL2 is implemented. */
1593# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1594/** Bit 40 - 43 - MPAM support. */
1595#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1596#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1597/** MPAM extension major version number is 0. */
1598# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1599/** MPAM extension major version number is 1. */
1600# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1601/** Bit 44 - 47 - Activity Monitor Extension support. */
1602#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1603#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1604/** Activity Monitor extension is not implemented. */
1605# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1606/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1607# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1608/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1609# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1610/** Bit 48 - 51 - Data Independent Timing support. */
1611#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1612#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1613/** AArch64 does not guarantee constant execution time of any instructions. */
1614# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1615/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1616# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1617/** Bit 52 - 55 - Realm Management Extension support. */
1618#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1619#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1620/** Realm Management Extension not implemented. */
1621# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1622/** RMEv1 is implemented (FEAT_RME). */
1623# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1624/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1625#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1626#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1627/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1628# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1629/** FEAT_CSV2 is implemented. */
1630# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1631/** FEAT_CSV2_2 is implemented. */
1632# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1633/** FEAT_CSV2_3 is implemented. */
1634# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1635/** Bit 60 - 63 - Speculative use of faulting data support. */
1636#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1637#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1638/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1639# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1640/** FEAT_CSV3 is supported . */
1641# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1642/** @} */
1643
1644
1645/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1646 * @{ */
1647/** Bit 0 - 3 - Branch Target Identification support. */
1648#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1649#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1650/** The Branch Target Identification mechanism is not implemented. */
1651# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1652/** The Branch Target Identifcation mechanism is implemented. */
1653# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1654/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1655#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1656#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1657/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1658# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1659/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1660# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1661/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1662 * to directly read and write the PSTATE.SSBS field. */
1663# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1664/** Bit 8 - 11 - Memory Tagging Extension support. */
1665#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1666#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1667/** MTE is not implemented. */
1668# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1669/** Instruction only Memory Tagging Extensions implemented. */
1670# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1671/** Full Memory Tagging Extension implemented. */
1672# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1673/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1674# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1675/** Bit 12 - 15 - RAS Extension fractional field. */
1676#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1677#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1678/** RAS Extension is implemented. */
1679# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1680/** FEAT_RASv1p1 is implemented. */
1681# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1682/** Bit 16 - 19 - MPAM minor version number. */
1683#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1684#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1685/** The minor version of number of the MPAM extension is 0. */
1686# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1687/** The minor version of number of the MPAM extension is 1. */
1688# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1689/* Bit 20 - 23 - Reserved. */
1690/** Bit 24 - 27 - Scalable Matrix Extension support. */
1691#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1692#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1693/** Scalable Matrix Extensions are not implemented. */
1694# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1695/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1696# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1697/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1698# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1699/** Bit 28 - 31 - Random Number trap to EL3 support. */
1700#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1701#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1702/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1703# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1704/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1705# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1706/** Bit 32 - 35 - CSV2 fractional field. */
1707#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1708#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1709/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1710# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1711/** FEAT_CSV2_1p1 is implemented. */
1712# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1713/** FEAT_CSV2_1p2 is implemented. */
1714# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1715/** Bit 36 - 39 - Non-maskable Interrupt support. */
1716#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1717#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1718/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1719# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1720/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1721# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1722/** @} */
1723
1724
1725/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1726 * @{ */
1727/** Bit 0 - 3 - Physical Address range supported. */
1728#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1729#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1730/** Physical Address range is 32 bits, 4GiB. */
1731# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1732/** Physical Address range is 36 bits, 64GiB. */
1733# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1734/** Physical Address range is 40 bits, 1TiB. */
1735# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1736/** Physical Address range is 42 bits, 4TiB. */
1737# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1738/** Physical Address range is 44 bits, 16TiB. */
1739# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1740/** Physical Address range is 48 bits, 256TiB. */
1741# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1742/** Physical Address range is 52 bits, 4PiB. */
1743# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1744/** Bit 4 - 7 - Number of ASID bits. */
1745#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1746#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1747/** ASID bits is 8. */
1748# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1749/** ASID bits is 16. */
1750# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1751/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1752#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1753#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1754/** No mixed-endian support. */
1755# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1756/** Mixed-endian supported. */
1757# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1758/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1759#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1760#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1761/** No distinction between Secure and Non-secure Memory supported. */
1762# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1763/** Distinction between Secure and Non-secure Memory supported. */
1764# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1765/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1766#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1767#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1768/** No mixed-endian support at EL0. */
1769# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1770/** Mixed-endian support at EL0. */
1771# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1772/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1773#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1774#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1775/** 16KiB granule size not supported. */
1776# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1777/** 16KiB granule size is supported. */
1778# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1779/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1780# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1781/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1782#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1783#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1784/** 64KiB granule supported. */
1785# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1786/** 64KiB granule not supported. */
1787# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1788/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1789#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1790#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1791/** 4KiB granule supported. */
1792# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1793/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1794# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1795/** 4KiB granule not supported. */
1796# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1797/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1798#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1799#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1800/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1801# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1802/** 16KiB granule not supported at stage 2. */
1803# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1804/** 16KiB granule supported at stage 2. */
1805# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1806/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1807# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1808/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1809#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1810#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1811/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1812# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1813/** 64KiB granule not supported at stage 2. */
1814# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1815/** 64KiB granule supported at stage 2. */
1816# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1817/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1818#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1819#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1820/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1821# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1822/** 4KiB granule not supported at stage 2. */
1823# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1824/** 4KiB granule supported at stage 2. */
1825# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1826/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1827# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1828/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1829#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1830#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1831/** All exception entries and exits are context synchronization events. */
1832# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1833/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1834# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1835/* Bit 48 - 55 - Reserved. */
1836/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1837#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1838#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
1839/** Fine-grained trap controls are not implemented. */
1840# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
1841/** Fine-grained trap controls are implemented (FEAT_FGT). */
1842# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
1843/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
1844#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1845#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
1846/** Enhanced Counter Virtualization is not implemented. */
1847# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
1848/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
1849# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
1850/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
1851# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
1852/** @} */
1853
1854
1855/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
1856 * @{ */
1857/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
1858#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1859#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
1860/** Hardware update of the Access flag and dirty state are not supported. */
1861# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
1862/** Support for hardware update of the Access flag for Block and Page descriptors. */
1863# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
1864/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
1865# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
1866/** Bit 4 - 7 - EL1 Exception level handling. */
1867#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1868#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
1869/** VMID bits is 8. */
1870# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
1871/** VMID bits is 16 (FEAT_VMID16). */
1872# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
1873/** Bit 8 - 11 - Virtualization Host Extensions support. */
1874#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1875#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
1876/** Virtualization Host Extensions are not supported. */
1877# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
1878/** Virtualization Host Extensions are supported. */
1879# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
1880/** Bit 12 - 15 - Hierarchical Permission Disables. */
1881#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1882#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
1883/** Disabling of hierarchical controls not supported. */
1884# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
1885/** Disabling of hierarchical controls supported (FEAT_HPDS). */
1886# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
1887/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
1888# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
1889/** Bit 16 - 19 - LORegions support. */
1890#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1891#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
1892/** LORegions not supported. */
1893# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
1894/** LORegions supported. */
1895# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
1896/** Bit 20 - 23 - Privileged Access Never support. */
1897#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1898#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
1899/** PAN not supported. */
1900# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
1901/** PAN supported (FEAT_PAN). */
1902# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
1903/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
1904# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
1905/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
1906# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
1907/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
1908#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1909#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
1910/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
1911# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
1912/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
1913# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
1914/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
1915#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1916#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
1917/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
1918# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
1919/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
1920# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
1921/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
1922#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1923#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
1924/** Configurable delayed trapping of WFE is not supported. */
1925# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
1926/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
1927# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
1928/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
1929#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1930#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
1931/** Enhanced Translation Synchronization is not supported. */
1932# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
1933/** Enhanced Translation Synchronization is implemented. */
1934# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
1935/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1936#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1937#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
1938/** HCRX_EL2 and its associated EL3 trap are not supported. */
1939# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
1940/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
1941# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
1942/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
1943#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1944#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
1945/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
1946# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
1947/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
1948# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
1949/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
1950#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1951#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
1952/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
1953# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
1954/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
1955# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
1956/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
1957#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1958#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
1959/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
1960# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
1961/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
1962# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
1963/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
1964#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1965#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
1966/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
1967# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
1968/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
1969# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
1970/* Bit 60 - 63 - Reserved. */
1971/** @} */
1972
1973
1974/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
1975 * @{ */
1976/** Bit 0 - 3 - Indicates support for Common not Private translations. */
1977#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1978#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
1979/** Common not Private translations are not supported. */
1980# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
1981/** Support for Common not Private translations (FEAT_TTNCP). */
1982# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
1983/** Bit 4 - 7 - Indicates support for User Access Override. */
1984#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1985#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
1986/** User Access Override is not supported. */
1987# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
1988/** User Access Override is supported (FEAT_UAO). */
1989# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
1990/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
1991#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1992#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
1993/** LSMAOE and nTLSMD bits are not supported. */
1994# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
1995/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
1996# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
1997/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
1998#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1999#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2000/** IESB bit is not supported. */
2001# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2002/** IESB bit is supported (FEAT_IESB). */
2003# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2004/** Bit 16 - 19 - Indicates support for larger virtual address. */
2005#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2006#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2007/** Virtual address range is 48 bits. */
2008# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2009/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2010# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2011/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2012#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2013#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2014/** CCSIDR_EL1 register format is 32-bit. */
2015# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2016/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2017# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2018/** Bit 24 - 27 - Indicates support for nested virtualization. */
2019#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2020#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2021/** Nested virtualization is not supported. */
2022# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2023/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2024# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2025/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2026# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2027/** Bit 28 - 31 - Indicates support for small translation tables. */
2028#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2029#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2030/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2031# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2032/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2033# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2034/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2035#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2036#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2037/** Unaligned single-copy atomicity and atomic functions are not supported. */
2038# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2039/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2040# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2041/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2042#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2043#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2044/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2045# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2046/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2047# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2048/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2049#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2050#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2051/** HCR_EL2.FWB bit is not supported. */
2052# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2053/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2054# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2055/* Bit 44 - 47 - Reserved. */
2056/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2057#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2058#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2059/** TLB maintenance instructions by address have bits [47:44] Res0. */
2060# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2061/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2062# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2063/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2064 * changing block size for a translation. */
2065#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2066#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2067/** Level 0 support for changing block size is supported (FEAT_BBM). */
2068# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2069/** Level 1 support for changing block size is supported (FEAT_BBM). */
2070# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2071/** Level 2 support for changing block size is supported (FEAT_BBM). */
2072# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2073/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2074#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2075#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2076/** Enhanced Virtualization Traps are not supported. */
2077# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2078/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2079# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2080/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2081# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2082/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2083#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2084#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2085/** E0PDx mechanism is not supported. */
2086# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2087/** E0PDx mechanism is supported (FEAT_E0PD). */
2088# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2089/** @} */
2090
2091
2092/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2093 * @{ */
2094/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2095#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2096#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2097/** Armv8 debug architecture version. */
2098# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2099/** Armv8 debug architecture version with virtualization host extensions. */
2100# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2101/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2102# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2103/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2104# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2105/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2106# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2107/** Bit 4 - 7 - Indicates trace support. */
2108#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2109#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2110/** Trace unit System registers not implemented. */
2111# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2112/** Trace unit System registers supported. */
2113# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2114/** Bit 8 - 11 - Performance Monitors Extension version. */
2115#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2116#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2117/** Performance Monitors Extension not supported. */
2118# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2119/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2120# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2121/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2122# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2123/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2124# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2125/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2126# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2127/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2128# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2129/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2130# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2131/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2132#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2133#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2134/* Bit 16 - 19 - Reserved 0. */
2135/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2136#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2137#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2138/* Bit 24 - 27 - Reserved 0. */
2139/** Bit 28 - 31 - Number of context-aware breakpoints. */
2140#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2141#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2142/** Bit 32 - 35 - Statistical Profiling Extension version. */
2143#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2144#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2145/** Statistical Profiling Extension not implemented. */
2146# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2147/** Statistical Profiling Extension supported (FEAT_SPE). */
2148# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2149/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2150# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2151/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2152# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2153/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2154# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2155/** Bit 36 - 39 - OS Double Lock implemented. */
2156#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2157#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2158/** OS Double Lock is not implemented. */
2159# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2160/** OS Double Lock is supported (FEAT_DoubleLock). */
2161# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2162/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2163#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2164#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2165/** Armv8.4 self-hosted Trace Extension not implemented. */
2166# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2167/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2168# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2169/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2170#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2171#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2172/** Trace Buffer Extension is not implemented. */
2173# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2174/** Trace Buffer Extension is supported (FEAT_TRBE). */
2175# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2176/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2177#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2178#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2179/** Multi-threaded PMU extension is not implemented. */
2180# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2181/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2182# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2183/** Multi-threaded PMU extension is not implemented. */
2184# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2185/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2186#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2187#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2188/** Branch Record Buffer extension is not implemented. */
2189# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2190/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2191# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2192/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2193# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2194/* Bit 56 - 59 - Reserved. */
2195/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2196#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2197#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2198/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2199# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2200/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2201# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2202/** @} */
2203
2204/** @} */
2205
2206#endif /* !IPRT_INCLUDED_armv8_h */
2207
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