[4720] | 1 | %define ___VBox_x86_h
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[5605] | 2 | %define X86_EFL_CF RT_BIT(0)
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| 3 | %define X86_EFL_PF RT_BIT(2)
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| 4 | %define X86_EFL_AF RT_BIT(4)
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| 5 | %define X86_EFL_ZF RT_BIT(6)
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| 6 | %define X86_EFL_SF RT_BIT(7)
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| 7 | %define X86_EFL_TF RT_BIT(8)
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| 8 | %define X86_EFL_IF RT_BIT(9)
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| 9 | %define X86_EFL_DF RT_BIT(10)
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| 10 | %define X86_EFL_OF RT_BIT(11)
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| 11 | %define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
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| 12 | %define X86_EFL_NT RT_BIT(14)
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| 13 | %define X86_EFL_RF RT_BIT(16)
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| 14 | %define X86_EFL_VM RT_BIT(17)
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| 15 | %define X86_EFL_AC RT_BIT(18)
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| 16 | %define X86_EFL_VIF RT_BIT(19)
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| 17 | %define X86_EFL_VIP RT_BIT(20)
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| 18 | %define X86_EFL_ID RT_BIT(21)
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[1] | 19 | %define X86_EFL_IOPL_SHIFT 12
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| 20 | %define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
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[4720] | 21 | %define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
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| 22 | %define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
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| 23 | %define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
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| 24 | %define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
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| 25 | %define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
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| 26 | %define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
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[5605] | 27 | %define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
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| 28 | %define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
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| 29 | %define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
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| 30 | %define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
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| 31 | %define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
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| 32 | %define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
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| 33 | %define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
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| 34 | %define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
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| 35 | %define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
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| 36 | %define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
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| 37 | %define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
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| 38 | %define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
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| 39 | %define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
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| 40 | %define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
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| 41 | %define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
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| 42 | %define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
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| 43 | %define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
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| 44 | %define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
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| 45 | %define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
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| 46 | %define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
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| 47 | %define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
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| 48 | %define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
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| 49 | %define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
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| 50 | %define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
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| 51 | %define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
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| 52 | %define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
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| 53 | %define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
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| 54 | %define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
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| 55 | %define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
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| 56 | %define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
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| 57 | %define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
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| 58 | %define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
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| 59 | %define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
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| 60 | %define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
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| 61 | %define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
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| 62 | %define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
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| 63 | %define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
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| 64 | %define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
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| 65 | %define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
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| 66 | %define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
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| 67 | %define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
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| 68 | %define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
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| 69 | %define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
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| 70 | %define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
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| 71 | %define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
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| 72 | %define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
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| 73 | %define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
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| 74 | %define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
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| 75 | %define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
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| 76 | %define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
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| 77 | %define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
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| 78 | %define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
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| 79 | %define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
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| 80 | %define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
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| 81 | %define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
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| 82 | %define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
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| 83 | %define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
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| 84 | %define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
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| 85 | %define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
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| 86 | %define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
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| 87 | %define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
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| 88 | %define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
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| 89 | %define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
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| 90 | %define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
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| 91 | %define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
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| 92 | %define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
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| 93 | %define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
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| 94 | %define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
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| 95 | %define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
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| 96 | %define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
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| 97 | %define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
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| 98 | %define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
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| 99 | %define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
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| 100 | %define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
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| 101 | %define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
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| 102 | %define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
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| 103 | %define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
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| 104 | %define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
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| 105 | %define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
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| 106 | %define X86_CR0_PE RT_BIT(0)
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| 107 | %define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
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| 108 | %define X86_CR0_MP RT_BIT(1)
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| 109 | %define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
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| 110 | %define X86_CR0_EM RT_BIT(2)
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| 111 | %define X86_CR0_EMULATE_FPU RT_BIT(2)
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| 112 | %define X86_CR0_TS RT_BIT(3)
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| 113 | %define X86_CR0_TASK_SWITCH RT_BIT(3)
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| 114 | %define X86_CR0_ET RT_BIT(4)
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| 115 | %define X86_CR0_EXTENSION_TYPE RT_BIT(4)
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| 116 | %define X86_CR0_NE RT_BIT(5)
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| 117 | %define X86_CR0_NUMERIC_ERROR RT_BIT(5)
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| 118 | %define X86_CR0_WP RT_BIT(16)
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| 119 | %define X86_CR0_WRITE_PROTECT RT_BIT(16)
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| 120 | %define X86_CR0_AM RT_BIT(18)
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| 121 | %define X86_CR0_ALIGMENT_MASK RT_BIT(18)
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| 122 | %define X86_CR0_NW RT_BIT(29)
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| 123 | %define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
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| 124 | %define X86_CR0_CD RT_BIT(30)
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| 125 | %define X86_CR0_CACHE_DISABLE RT_BIT(30)
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| 126 | %define X86_CR0_PG RT_BIT(31)
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| 127 | %define X86_CR0_PAGING RT_BIT(31)
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| 128 | %define X86_CR3_PWT RT_BIT(3)
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| 129 | %define X86_CR3_PCD RT_BIT(4)
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[1] | 130 | %define X86_CR3_PAGE_MASK (0xfffff000)
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| 131 | %define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
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[5605] | 132 | %define X86_CR4_VME RT_BIT(0)
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| 133 | %define X86_CR4_PVI RT_BIT(1)
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| 134 | %define X86_CR4_TSD RT_BIT(2)
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| 135 | %define X86_CR4_DE RT_BIT(3)
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| 136 | %define X86_CR4_PSE RT_BIT(4)
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| 137 | %define X86_CR4_PAE RT_BIT(5)
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| 138 | %define X86_CR4_MCE RT_BIT(6)
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| 139 | %define X86_CR4_PGE RT_BIT(7)
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| 140 | %define X86_CR4_PCE RT_BIT(8)
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| 141 | %define X86_CR4_OSFSXR RT_BIT(9)
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| 142 | %define X86_CR4_OSXMMEEXCPT RT_BIT(10)
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| 143 | %define X86_CR4_VMXE RT_BIT(13)
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| 144 | %define X86_DR6_B0 RT_BIT(0)
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| 145 | %define X86_DR6_B1 RT_BIT(1)
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| 146 | %define X86_DR6_B2 RT_BIT(2)
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| 147 | %define X86_DR6_B3 RT_BIT(3)
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| 148 | %define X86_DR6_BD RT_BIT(13)
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| 149 | %define X86_DR6_BS RT_BIT(14)
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| 150 | %define X86_DR6_BT RT_BIT(15)
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| 151 | %define X86_DR7_L0 RT_BIT(0)
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| 152 | %define X86_DR7_G0 RT_BIT(1)
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| 153 | %define X86_DR7_L1 RT_BIT(2)
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| 154 | %define X86_DR7_G1 RT_BIT(3)
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| 155 | %define X86_DR7_L2 RT_BIT(4)
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| 156 | %define X86_DR7_G2 RT_BIT(5)
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| 157 | %define X86_DR7_L3 RT_BIT(6)
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| 158 | %define X86_DR7_G3 RT_BIT(7)
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| 159 | %define X86_DR7_LE RT_BIT(8)
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| 160 | %define X86_DR7_GE RT_BIT(9)
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| 161 | %define X86_DR7_GD RT_BIT(13)
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[1] | 162 | %define X86_DR7_RW0_MASK (3 << 16)
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| 163 | %define X86_DR7_LEN0_MASK (3 << 18)
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| 164 | %define X86_DR7_RW1_MASK (3 << 20)
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| 165 | %define X86_DR7_LEN1_MASK (3 << 22)
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| 166 | %define X86_DR7_RW2_MASK (3 << 24)
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| 167 | %define X86_DR7_LEN2_MASK (3 << 26)
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| 168 | %define X86_DR7_RW3_MASK (3 << 28)
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| 169 | %define X86_DR7_LEN3_MASK (3 << 30)
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[5605] | 170 | %define X86_DR7_MB1_MASK (RT_BIT(10))
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[1] | 171 | %define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
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| 172 | %define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
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| 173 | %define X86_DR7_RW_EO 0
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| 174 | %define X86_DR7_RW_WO 1
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| 175 | %define X86_DR7_RW_IO 2
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| 176 | %define X86_DR7_RW_RW 3
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| 177 | %define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
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| 178 | %define X86_DR7_LEN_BYTE 0
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| 179 | %define X86_DR7_LEN_WORD 1
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| 180 | %define X86_DR7_LEN_QWORD 2 /**< AMD64 long mode only. */
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| 181 | %define X86_DR7_LEN_DWORD 3
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| 182 | %define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
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[5605] | 183 | %define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(6) | RT_BIT(7))
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[1] | 184 | %define MSR_IA32_FEATURE_CONTROL 0x3A
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[5605] | 185 | %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
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| 186 | %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
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[1] | 187 | %define MSR_IA32_SYSENTER_CS 0x174
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| 188 | %define MSR_IA32_SYSENTER_ESP 0x175
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| 189 | %define MSR_IA32_SYSENTER_EIP 0x176
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[7706] | 190 | %define IA32_CR_PAT 0x277
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[1] | 191 | %define MSR_IA32_VMX_BASIC_INFO 0x480
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| 192 | %define MSR_IA32_VMX_PINBASED_CTLS 0x481
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| 193 | %define MSR_IA32_VMX_PROCBASED_CTLS 0x482
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| 194 | %define MSR_IA32_VMX_EXIT_CTLS 0x483
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| 195 | %define MSR_IA32_VMX_ENTRY_CTLS 0x484
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| 196 | %define MSR_IA32_VMX_MISC 0x485
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| 197 | %define MSR_IA32_VMX_CR0_FIXED0 0x486
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| 198 | %define MSR_IA32_VMX_CR0_FIXED1 0x487
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| 199 | %define MSR_IA32_VMX_CR4_FIXED0 0x488
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| 200 | %define MSR_IA32_VMX_CR4_FIXED1 0x489
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| 201 | %define MSR_IA32_VMX_VMCS_ENUM 0x48A
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| 202 | %define MSR_K6_EFER 0xc0000080
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[5605] | 203 | %define MSR_K6_EFER_SCE RT_BIT(0)
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| 204 | %define MSR_K6_EFER_LME RT_BIT(8)
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| 205 | %define MSR_K6_EFER_LMA RT_BIT(10)
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| 206 | %define MSR_K6_EFER_NXE RT_BIT(11)
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| 207 | %define MSR_K6_EFER_SVME RT_BIT(12)
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| 208 | %define MSR_K6_EFER_LMSLE RT_BIT(13)
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| 209 | %define MSR_K6_EFER_FFXSR RT_BIT(14)
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[1] | 210 | %define MSR_K6_STAR 0xc0000081
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| 211 | %define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
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| 212 | %define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
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| 213 | %define MSR_K6_STAR_SEL_MASK 0xffff
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| 214 | %define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
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| 215 | %define MSR_K6_WHCR 0xc0000082
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| 216 | %define MSR_K6_UWCCR 0xc0000085
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| 217 | %define MSR_K6_PSOR 0xc0000087
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| 218 | %define MSR_K6_PFIR 0xc0000088
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| 219 | %define MSR_K7_EVNTSEL0 0xc0010000
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| 220 | %define MSR_K7_EVNTSEL1 0xc0010001
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| 221 | %define MSR_K7_EVNTSEL2 0xc0010002
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| 222 | %define MSR_K7_EVNTSEL3 0xc0010003
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| 223 | %define MSR_K7_PERFCTR0 0xc0010004
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| 224 | %define MSR_K7_PERFCTR1 0xc0010005
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| 225 | %define MSR_K7_PERFCTR2 0xc0010006
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| 226 | %define MSR_K7_PERFCTR3 0xc0010007
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| 227 | %define MSR_K8_LSTAR 0xc0000082
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| 228 | %define MSR_K8_CSTAR 0xc0000083
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| 229 | %define MSR_K8_SF_MASK 0xc0000084
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| 230 | %define MSR_K8_FS_BASE 0xc0000100
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| 231 | %define MSR_K8_GS_BASE 0xc0000101
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| 232 | %define MSR_K8_KERNEL_GS_BASE 0xc0000102
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| 233 | %define MSR_K8_TSC_AUX 0xc0000103
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| 234 | %define MSR_K8_SYSCFG 0xc0010010
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| 235 | %define MSR_K8_HWCR 0xc0010015
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| 236 | %define MSR_K8_IORRBASE0 0xc0010016
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| 237 | %define MSR_K8_IORRMASK0 0xc0010017
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| 238 | %define MSR_K8_IORRBASE1 0xc0010018
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| 239 | %define MSR_K8_IORRMASK1 0xc0010019
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| 240 | %define MSR_K8_TOP_MEM1 0xc001001a
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| 241 | %define MSR_K8_TOP_MEM2 0xc001001d
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| 242 | %define MSR_K8_VM_CR 0xc0010114
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[5605] | 243 | %define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
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[1] | 244 | %define MSR_K8_IGNNE 0xc0010115
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| 245 | %define MSR_K8_SMM_CTL 0xc0010116
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| 246 | %define MSR_K8_VM_HSAVE_PA 0xc0010117
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| 247 | %define X86_PG_ENTRIES 1024
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| 248 | %define X86_PG_PAE_ENTRIES 512
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[7706] | 249 | %define X86_PG_PAE_PDPE_ENTRIES 4
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| 250 | %define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
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| 251 | %define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
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[1] | 252 | %define X86_PAGE_4K_SIZE _4K
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| 253 | %define X86_PAGE_4K_SHIFT 12
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| 254 | %define X86_PAGE_4K_OFFSET_MASK 0xfff
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| 255 | %define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
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| 256 | %define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
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| 257 | %define X86_PAGE_2M_SIZE _2M
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| 258 | %define X86_PAGE_2M_SHIFT 21
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| 259 | %define X86_PAGE_2M_OFFSET_MASK 0x001fffff
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| 260 | %define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
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| 261 | %define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
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| 262 | %define X86_PAGE_4M_SIZE _4M
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| 263 | %define X86_PAGE_4M_SHIFT 22
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| 264 | %define X86_PAGE_4M_OFFSET_MASK 0x003fffff
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| 265 | %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
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| 266 | %define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
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[5605] | 267 | %define X86_PTE_P RT_BIT(0)
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| 268 | %define X86_PTE_RW RT_BIT(1)
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| 269 | %define X86_PTE_US RT_BIT(2)
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| 270 | %define X86_PTE_PWT RT_BIT(3)
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| 271 | %define X86_PTE_PCD RT_BIT(4)
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| 272 | %define X86_PTE_A RT_BIT(5)
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| 273 | %define X86_PTE_D RT_BIT(6)
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| 274 | %define X86_PTE_PAT RT_BIT(7)
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| 275 | %define X86_PTE_G RT_BIT(8)
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| 276 | %define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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[1] | 277 | %define X86_PTE_PG_MASK ( 0xfffff000 )
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| 278 | %define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
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| 279 | %define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
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[5605] | 280 | %define X86_PTE_PAE_NX RT_BIT_64(63)
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[1] | 281 | %define X86_PT_SHIFT 12
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| 282 | %define X86_PT_MASK 0x3ff
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| 283 | %define X86_PT_PAE_SHIFT 12
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| 284 | %define X86_PT_PAE_MASK 0x1ff
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[5605] | 285 | %define X86_PDE_P RT_BIT(0)
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| 286 | %define X86_PDE_RW RT_BIT(1)
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| 287 | %define X86_PDE_US RT_BIT(2)
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| 288 | %define X86_PDE_PWT RT_BIT(3)
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| 289 | %define X86_PDE_PCD RT_BIT(4)
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| 290 | %define X86_PDE_A RT_BIT(5)
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| 291 | %define X86_PDE_PS RT_BIT(7)
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| 292 | %define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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[1] | 293 | %define X86_PDE_PG_MASK ( 0xfffff000 )
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| 294 | %define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
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| 295 | %define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
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[5605] | 296 | %define X86_PDE_PAE_NX RT_BIT_64(63)
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| 297 | %define X86_PDE4M_P RT_BIT(0)
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| 298 | %define X86_PDE4M_RW RT_BIT(1)
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| 299 | %define X86_PDE4M_US RT_BIT(2)
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| 300 | %define X86_PDE4M_PWT RT_BIT(3)
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| 301 | %define X86_PDE4M_PCD RT_BIT(4)
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| 302 | %define X86_PDE4M_A RT_BIT(5)
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| 303 | %define X86_PDE4M_D RT_BIT(6)
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| 304 | %define X86_PDE4M_PS RT_BIT(7)
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| 305 | %define X86_PDE4M_G RT_BIT(8)
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| 306 | %define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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| 307 | %define X86_PDE4M_PAT RT_BIT(12)
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[1] | 308 | %define X86_PDE4M_PAT_SHIFT (12 - 7)
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| 309 | %define X86_PDE4M_PG_MASK ( 0xffc00000 )
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| 310 | %define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
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| 311 | %define X86_PDE4M_PG_HIGH_SHIFT 19
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[7706] | 312 | %define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
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| 313 | %define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
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[1] | 314 | %define X86_PD_SHIFT 22
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| 315 | %define X86_PD_MASK 0x3ff
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| 316 | %define X86_PD_PAE_SHIFT 21
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| 317 | %define X86_PD_PAE_MASK 0x1ff
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[5605] | 318 | %define X86_PDPE_P RT_BIT(0)
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| 319 | %define X86_PDPE_RW RT_BIT(1)
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| 320 | %define X86_PDPE_US RT_BIT(2)
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| 321 | %define X86_PDPE_PWT RT_BIT(3)
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| 322 | %define X86_PDPE_PCD RT_BIT(4)
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| 323 | %define X86_PDPE_A RT_BIT(5)
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| 324 | %define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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[1] | 325 | %define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
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| 326 | %define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
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[5605] | 327 | %define X86_PDPE_NX RT_BIT_64(63)
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[1] | 328 | %define X86_PDPTR_SHIFT 30
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| 329 | %define X86_PDPTR_MASK_32 0x3
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| 330 | %define X86_PDPTR_MASK 0x1ff
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[5605] | 331 | %define X86_PML4E_P RT_BIT(0)
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| 332 | %define X86_PML4E_RW RT_BIT(1)
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| 333 | %define X86_PML4E_US RT_BIT(2)
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| 334 | %define X86_PML4E_PWT RT_BIT(3)
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| 335 | %define X86_PML4E_PCD RT_BIT(4)
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| 336 | %define X86_PML4E_A RT_BIT(5)
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| 337 | %define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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[1] | 338 | %define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
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| 339 | %define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
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[5605] | 340 | %define X86_PML4E_NX RT_BIT_64(63)
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[1] | 341 | %define X86_PML4_SHIFT 39
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| 342 | %define X86_PML4_MASK 0x1ff
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| 343 | %define X86_SEL_TYPE_CODE 8
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[5605] | 344 | %define X86_SEL_TYPE_MEMORY RT_BIT(4)
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[1] | 345 | %define X86_SEL_TYPE_ACCESSED 1
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| 346 | %define X86_SEL_TYPE_DOWN 4
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| 347 | %define X86_SEL_TYPE_CONF 4
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| 348 | %define X86_SEL_TYPE_WRITE 2
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| 349 | %define X86_SEL_TYPE_READ 2
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| 350 | %define X86_SEL_TYPE_RO 0
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| 351 | %define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
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| 352 | %define X86_SEL_TYPE_RW 2
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| 353 | %define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
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| 354 | %define X86_SEL_TYPE_RO_DOWN 4
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| 355 | %define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
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| 356 | %define X86_SEL_TYPE_RW_DOWN 6
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| 357 | %define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
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| 358 | %define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
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| 359 | %define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
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| 360 | %define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
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| 361 | %define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
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| 362 | %define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
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| 363 | %define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
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| 364 | %define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
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| 365 | %define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
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[4720] | 366 | %define X86_SEL_TYPE_SYS_UNDEFINED 0
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| 367 | %define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
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| 368 | %define X86_SEL_TYPE_SYS_LDT 2
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| 369 | %define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
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| 370 | %define X86_SEL_TYPE_SYS_286_CALL_GATE 4
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| 371 | %define X86_SEL_TYPE_SYS_TASK_GATE 5
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| 372 | %define X86_SEL_TYPE_SYS_286_INT_GATE 6
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| 373 | %define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
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| 374 | %define X86_SEL_TYPE_SYS_UNDEFINED2 8
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| 375 | %define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
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| 376 | %define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
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| 377 | %define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
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| 378 | %define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
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| 379 | %define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
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| 380 | %define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
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| 381 | %define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
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| 382 | %define AMD64_SEL_TYPE_SYS_LDT 2
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| 383 | %define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
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| 384 | %define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
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| 385 | %define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
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| 386 | %define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
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| 387 | %define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
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[5605] | 388 | %define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
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| 389 | %define X86_DESC_S RT_BIT(12)
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| 390 | %define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
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| 391 | %define X86_DESC_P RT_BIT(15)
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| 392 | %define X86_DESC_AVL RT_BIT(20)
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| 393 | %define X86_DESC_DB RT_BIT(22)
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| 394 | %define X86_DESC_G RT_BIT(23)
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[4720] | 395 | %define X86_SEL_SHIFT 3
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| 396 | %define AMD64_SEL_SHIFT 4
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| 397 | %define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
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| 398 | %define X86_SEL_SHIFT_HC X86_SEL_SHIFT
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| 399 | %define X86_SEL_MASK 0xfff8
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| 400 | %define X86_SEL_LDT 0x0004
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| 401 | %define X86_SEL_RPL 0x0003
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[1] | 402 | %define X86_TRAP_ERR_EXTERNAL 1
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| 403 | %define X86_TRAP_ERR_IDT 2
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| 404 | %define X86_TRAP_ERR_TI 4
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| 405 | %define X86_TRAP_ERR_SEL_MASK 0xfff8
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| 406 | %define X86_TRAP_ERR_SEL_SHIFT 3
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[5605] | 407 | %define X86_TRAP_PF_P RT_BIT(0)
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| 408 | %define X86_TRAP_PF_RW RT_BIT(1)
|
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| 409 | %define X86_TRAP_PF_US RT_BIT(2)
|
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| 410 | %define X86_TRAP_PF_RSVD RT_BIT(3)
|
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| 411 | %define X86_TRAP_PF_ID RT_BIT(4)
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