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source: vbox/trunk/include/VBox/x86.h@ 28800

Last change on this file since 28800 was 28800, checked in by vboxsync, 14 years ago
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef ___VBox_x86_h
29	#define ___VBox_x86_h
30
31	#include <VBox/types.h>
32	#include <iprt/assert.h>
33
34	/* Workaround for Solaris sys/regset.h defining CS, DS */
35	#ifdef RT_OS_SOLARIS
36	# undef CS
37	# undef DS
38	#endif
39
40	/** @defgroup grp_x86 x86 Types and Definitions
41	* @{
42	*/
43
44	/**
45	* EFLAGS Bits.
46	*/
47	typedef struct X86EFLAGSBITS
48	{
49	/** Bit 0 - CF - Carry flag - Status flag. */
50	unsigned u1CF : 1;
51	/** Bit 1 - 1 - Reserved flag. */
52	unsigned u1Reserved0 : 1;
53	/** Bit 2 - PF - Parity flag - Status flag. */
54	unsigned u1PF : 1;
55	/** Bit 3 - 0 - Reserved flag. */
56	unsigned u1Reserved1 : 1;
57	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
58	unsigned u1AF : 1;
59	/** Bit 5 - 0 - Reserved flag. */
60	unsigned u1Reserved2 : 1;
61	/** Bit 6 - ZF - Zero flag - Status flag. */
62	unsigned u1ZF : 1;
63	/** Bit 7 - SF - Signed flag - Status flag. */
64	unsigned u1SF : 1;
65	/** Bit 8 - TF - Trap flag - System flag. */
66	unsigned u1TF : 1;
67	/** Bit 9 - IF - Interrupt flag - System flag. */
68	unsigned u1IF : 1;
69	/** Bit 10 - DF - Direction flag - Control flag. */
70	unsigned u1DF : 1;
71	/** Bit 11 - OF - Overflow flag - Status flag. */
72	unsigned u1OF : 1;
73	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
74	unsigned u2IOPL : 2;
75	/** Bit 14 - NT - Nested task flag - System flag. */
76	unsigned u1NT : 1;
77	/** Bit 15 - 0 - Reserved flag. */
78	unsigned u1Reserved3 : 1;
79	/** Bit 16 - RF - Resume flag - System flag. */
80	unsigned u1RF : 1;
81	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
82	unsigned u1VM : 1;
83	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
84	unsigned u1AC : 1;
85	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
86	unsigned u1VIF : 1;
87	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
88	unsigned u1VIP : 1;
89	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
90	unsigned u1ID : 1;
91	/** Bit 22-31 - 0 - Reserved flag. */
92	unsigned u10Reserved4 : 10;
93	} X86EFLAGSBITS;
94	/** Pointer to EFLAGS bits. */
95	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
96	/** Pointer to const EFLAGS bits. */
97	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
98
99	/**
100	* EFLAGS.
101	*/
102	typedef union X86EFLAGS
103	{
104	/** The plain unsigned view. */
105	uint32_t u;
106	/** The bitfield view. */
107	X86EFLAGSBITS Bits;
108	/** The 8-bit view. */
109	uint8_t au8[4];
110	/** The 16-bit view. */
111	uint16_t au16[2];
112	/** The 32-bit view. */
113	uint32_t au32[1];
114	/** The 32-bit view. */
115	uint32_t u32;
116	} X86EFLAGS;
117	/** Pointer to EFLAGS. */
118	typedef X86EFLAGS *PX86EFLAGS;
119	/** Pointer to const EFLAGS. */
120	typedef const X86EFLAGS *PCX86EFLAGS;
121
122	/**
123	* RFLAGS (32 upper bits are reserved).
124	*/
125	typedef union X86RFLAGS
126	{
127	/** The plain unsigned view. */
128	uint64_t u;
129	/** The bitfield view. */
130	X86EFLAGSBITS Bits;
131	/** The 8-bit view. */
132	uint8_t au8[8];
133	/** The 16-bit view. */
134	uint16_t au16[4];
135	/** The 32-bit view. */
136	uint32_t au32[2];
137	/** The 64-bit view. */
138	uint64_t au64[1];
139	/** The 64-bit view. */
140	uint64_t u64;
141	} X86RFLAGS;
142	/** Pointer to RFLAGS. */
143	typedef X86RFLAGS *PX86RFLAGS;
144	/** Pointer to const RFLAGS. */
145	typedef const X86RFLAGS *PCX86RFLAGS;
146
147
148	/** @name EFLAGS
149	* @{
150	*/
151	/** Bit 0 - CF - Carry flag - Status flag. */
152	#define X86_EFL_CF RT_BIT(0)
153	/** Bit 2 - PF - Parity flag - Status flag. */
154	#define X86_EFL_PF RT_BIT(2)
155	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
156	#define X86_EFL_AF RT_BIT(4)
157	/** Bit 6 - ZF - Zero flag - Status flag. */
158	#define X86_EFL_ZF RT_BIT(6)
159	/** Bit 7 - SF - Signed flag - Status flag. */
160	#define X86_EFL_SF RT_BIT(7)
161	/** Bit 8 - TF - Trap flag - System flag. */
162	#define X86_EFL_TF RT_BIT(8)
163	/** Bit 9 - IF - Interrupt flag - System flag. */
164	#define X86_EFL_IF RT_BIT(9)
165	/** Bit 10 - DF - Direction flag - Control flag. */
166	#define X86_EFL_DF RT_BIT(10)
167	/** Bit 11 - OF - Overflow flag - Status flag. */
168	#define X86_EFL_OF RT_BIT(11)
169	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
170	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
171	/** Bit 14 - NT - Nested task flag - System flag. */
172	#define X86_EFL_NT RT_BIT(14)
173	/** Bit 16 - RF - Resume flag - System flag. */
174	#define X86_EFL_RF RT_BIT(16)
175	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
176	#define X86_EFL_VM RT_BIT(17)
177	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
178	#define X86_EFL_AC RT_BIT(18)
179	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
180	#define X86_EFL_VIF RT_BIT(19)
181	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
182	#define X86_EFL_VIP RT_BIT(20)
183	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
184	#define X86_EFL_ID RT_BIT(21)
185	/** IOPL shift. */
186	#define X86_EFL_IOPL_SHIFT 12
187	/** The the IOPL level from the flags. */
188	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
189	/** Bits restored by popf */
190	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
191	/** @} */
192
193
194	/** CPUID Feature information - ECX.
195	* CPUID query with EAX=1.
196	*/
197	typedef struct X86CPUIDFEATECX
198	{
199	/** Bit 0 - SSE3 - Supports SSE3 or not. */
200	unsigned u1SSE3 : 1;
201	/** Reserved. */
202	unsigned u1Reserved1 : 1;
203	/** Bit 2 - DS Area 64-bit layout. */
204	unsigned u1DTE64 : 1;
205	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
206	unsigned u1Monitor : 1;
207	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
208	unsigned u1CPLDS : 1;
209	/** Bit 5 - VMX - Virtual Machine Technology. */
210	unsigned u1VMX : 1;
211	/** Bit 6 - SMX: Safer Mode Extensions. */
212	unsigned u1SMX : 1;
213	/** Bit 7 - EST - Enh. SpeedStep Tech. */
214	unsigned u1EST : 1;
215	/** Bit 8 - TM2 - Terminal Monitor 2. */
216	unsigned u1TM2 : 1;
217	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
218	unsigned u1SSSE3 : 1;
219	/** Bit 10 - CNTX-ID - L1 Context ID. */
220	unsigned u1CNTXID : 1;
221	/** Bit 11 - FMA. */
222	unsigned u1FMA : 1;
223	/** Bit 12 - Reserved. */
224	unsigned u1Reserved2 : 1;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
230	unsigned u1PDCM : 1;
231	/** Reserved. */
232	unsigned u2Reserved3 : 2;
233	/** Bit 18 - Direct Cache Access. */
234	unsigned u1DCA : 1;
235	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
236	unsigned u1SSE4_1 : 1;
237	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
238	unsigned u1SSE4_2 : 1;
239	/** Bit 21 - x2APIC. */
240	unsigned u1x2APIC : 1;
241	/** Bit 22 - MOVBE - Supports MOVBE. */
242	unsigned u1MOVBE : 1;
243	/** Bit 23 - POPCNT - Supports POPCNT. */
244	unsigned u1POPCNT : 1;
245	/** Bit 24 - Reserved. */
246	unsigned u1Reserved4 : 1;
247	/** Bit 25 - AES. */
248	unsigned u1AES : 1;
249	/** Bit 26 - XSAVE - Supports XSAVE. */
250	unsigned u1XSAVE : 1;
251	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
252	unsigned u1OSXSAVE : 1;
253	/** Reserved. */
254	unsigned u4Reserved5 : 4;
255	} X86CPUIDFEATECX;
256	/** Pointer to CPUID Feature Information - ECX. */
257	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
258	/** Pointer to const CPUID Feature Information - ECX. */
259	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
260
261
262	/** CPUID Feature Information - EDX.
263	* CPUID query with EAX=1.
264	*/
265	typedef struct X86CPUIDFEATEDX
266	{
267	/** Bit 0 - FPU - x87 FPU on Chip. */
268	unsigned u1FPU : 1;
269	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
270	unsigned u1VME : 1;
271	/** Bit 2 - DE - Debugging extensions. */
272	unsigned u1DE : 1;
273	/** Bit 3 - PSE - Page Size Extension. */
274	unsigned u1PSE : 1;
275	/** Bit 4 - TSC - Time Stamp Counter. */
276	unsigned u1TSC : 1;
277	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
278	unsigned u1MSR : 1;
279	/** Bit 6 - PAE - Physical Address Extension. */
280	unsigned u1PAE : 1;
281	/** Bit 7 - MCE - Machine Check Exception. */
282	unsigned u1MCE : 1;
283	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
284	unsigned u1CX8 : 1;
285	/** Bit 9 - APIC - APIC On-Chip. */
286	unsigned u1APIC : 1;
287	/** Bit 10 - Reserved. */
288	unsigned u1Reserved1 : 1;
289	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
290	unsigned u1SEP : 1;
291	/** Bit 12 - MTRR - Memory Type Range Registers. */
292	unsigned u1MTRR : 1;
293	/** Bit 13 - PGE - PTE Global Bit. */
294	unsigned u1PGE : 1;
295	/** Bit 14 - MCA - Machine Check Architecture. */
296	unsigned u1MCA : 1;
297	/** Bit 15 - CMOV - Conditional Move Instructions. */
298	unsigned u1CMOV : 1;
299	/** Bit 16 - PAT - Page Attribute Table. */
300	unsigned u1PAT : 1;
301	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
302	unsigned u1PSE36 : 1;
303	/** Bit 18 - PSN - Processor Serial Number. */
304	unsigned u1PSN : 1;
305	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
306	unsigned u1CLFSH : 1;
307	/** Bit 20 - Reserved. */
308	unsigned u1Reserved2 : 1;
309	/** Bit 21 - DS - Debug Store. */
310	unsigned u1DS : 1;
311	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
312	unsigned u1ACPI : 1;
313	/** Bit 23 - MMX - Intel MMX 'Technology'. */
314	unsigned u1MMX : 1;
315	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
316	unsigned u1FXSR : 1;
317	/** Bit 25 - SSE - SSE Support. */
318	unsigned u1SSE : 1;
319	/** Bit 26 - SSE2 - SSE2 Support. */
320	unsigned u1SSE2 : 1;
321	/** Bit 27 - SS - Self Snoop. */
322	unsigned u1SS : 1;
323	/** Bit 28 - HTT - Hyper-Threading Technology. */
324	unsigned u1HTT : 1;
325	/** Bit 29 - TM - Thermal Monitor. */
326	unsigned u1TM : 1;
327	/** Bit 30 - Reserved - . */
328	unsigned u1Reserved3 : 1;
329	/** Bit 31 - PBE - Pending Break Enabled. */
330	unsigned u1PBE : 1;
331	} X86CPUIDFEATEDX;
332	/** Pointer to CPUID Feature Information - EDX. */
333	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
334	/** Pointer to const CPUID Feature Information - EDX. */
335	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
336
337	/** @name CPUID Vendor information.
338	* CPUID query with EAX=0.
339	* @{
340	*/
341	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
342	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
343	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
344
345	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
346	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
347	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
348	/** @} */
349
350
351	/** @name CPUID Feature information.
352	* CPUID query with EAX=1.
353	* @{
354	*/
355	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
356	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
357	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
358	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
359	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
360	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
361	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
362	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
363	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
364	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
365	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
366	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
367	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
368	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
369	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
370	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
371	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
372	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
373	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
374	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
375	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
376	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
377	/** ECX Bit 12 - FMA. */
378	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
379	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
380	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
381	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
382	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
383	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
384	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
385	/** ECX Bit 18 - DCA - Direct Cache Access. */
386	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
387	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
388	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
389	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
390	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
391	/** ECX Bit 21 - x2APIC support. */
392	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
393	/** ECX Bit 22 - MOVBE instruction. */
394	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
395	/** ECX Bit 23 - POPCNT instruction. */
396	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
397	/** ECX Bit 25 - AES instructions. */
398	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
399	/** ECX Bit 26 - XSAVE instruction. */
400	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
401	/** ECX Bit 27 - OSXSAVE instruction. */
402	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
403	/** ECX Bit 28 - AVX. */
404	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
405
406
407	/** Bit 0 - FPU - x87 FPU on Chip. */
408	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
409	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
410	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
411	/** Bit 2 - DE - Debugging extensions. */
412	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
413	/** Bit 3 - PSE - Page Size Extension. */
414	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
415	/** Bit 4 - TSC - Time Stamp Counter. */
416	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
417	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
418	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
419	/** Bit 6 - PAE - Physical Address Extension. */
420	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
421	/** Bit 7 - MCE - Machine Check Exception. */
422	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
423	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
424	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
425	/** Bit 9 - APIC - APIC On-Chip. */
426	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
427	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
428	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
429	/** Bit 12 - MTRR - Memory Type Range Registers. */
430	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
431	/** Bit 13 - PGE - PTE Global Bit. */
432	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
433	/** Bit 14 - MCA - Machine Check Architecture. */
434	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
435	/** Bit 15 - CMOV - Conditional Move Instructions. */
436	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
437	/** Bit 16 - PAT - Page Attribute Table. */
438	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
439	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
440	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
441	/** Bit 18 - PSN - Processor Serial Number. */
442	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
443	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
444	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
445	/** Bit 21 - DS - Debug Store. */
446	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
447	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
448	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
449	/** Bit 23 - MMX - Intel MMX Technology. */
450	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
451	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
452	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
453	/** Bit 25 - SSE - SSE Support. */
454	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
455	/** Bit 26 - SSE2 - SSE2 Support. */
456	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
457	/** Bit 27 - SS - Self Snoop. */
458	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
459	/** Bit 28 - HTT - Hyper-Threading Technology. */
460	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
461	/** Bit 29 - TM - Therm. Monitor. */
462	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
463	/** Bit 31 - PBE - Pending Break Enabled. */
464	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
465	/** @} */
466
467	/** @name CPUID mwait/monitor information.
468	* CPUID query with EAX=5.
469	* @{
470	*/
471	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
472	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
473	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
474	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
475	/** @} */
476
477
478	/** @name CPUID AMD Feature information.
479	* CPUID query with EAX=0x80000001.
480	* @{
481	*/
482	/** Bit 0 - FPU - x87 FPU on Chip. */
483	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
484	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
485	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
486	/** Bit 2 - DE - Debugging extensions. */
487	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
488	/** Bit 3 - PSE - Page Size Extension. */
489	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
490	/** Bit 4 - TSC - Time Stamp Counter. */
491	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
492	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
493	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
494	/** Bit 6 - PAE - Physical Address Extension. */
495	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
496	/** Bit 7 - MCE - Machine Check Exception. */
497	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
498	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
499	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
500	/** Bit 9 - APIC - APIC On-Chip. */
501	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
502	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
503	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
504	/** Bit 12 - MTRR - Memory Type Range Registers. */
505	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
506	/** Bit 13 - PGE - PTE Global Bit. */
507	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
508	/** Bit 14 - MCA - Machine Check Architecture. */
509	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
510	/** Bit 15 - CMOV - Conditional Move Instructions. */
511	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
512	/** Bit 16 - PAT - Page Attribute Table. */
513	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
514	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
515	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
516	/** Bit 20 - NX - AMD No-Execute Page Protection. */
517	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
518	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
519	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
520	/** Bit 23 - MMX - Intel MMX Technology. */
521	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
522	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
523	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
524	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
525	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
526	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
527	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
528	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
529	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
530	/** Bit 29 - LM - AMD Long Mode. */
531	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
532	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
533	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
534	/** Bit 31 - 3DNOW - AMD 3DNow. */
535	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
536
537	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
538	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
539	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
540	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
541	/** Bit 2 - SVM - AMD VM extensions. */
542	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
543	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
544	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
545	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
546	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
547	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
548	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
549	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
550	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
551	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
552	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
553	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
554	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
555	/** Bit 9 - OSVW - AMD OS visible workaround. */
556	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
557	/** Bit 10 - IBS - Instruct based sampling. */
558	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
559	/** Bit 11 - SSE5 - SSE5 instruction support. */
560	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
561	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
562	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
563	/** Bit 13 - WDT - AMD Watchdog timer support. */
564	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
565
566	/** @} */
567
568
569	/** @name CPUID AMD Feature information.
570	* CPUID query with EAX=0x80000007.
571	* @{
572	*/
573	/** Bit 0 - TS - Temperature Sensor. */
574	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
575	/** Bit 1 - FID - Frequency ID Control. */
576	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
577	/** Bit 2 - VID - Voltage ID Control. */
578	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
579	/** Bit 3 - TTP - THERMTRIP. */
580	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
581	/** Bit 4 - TM - Hardware Thermal Control. */
582	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
583	/** Bit 5 - STC - Software Thermal Control. */
584	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
585	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
586	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
587	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
588	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
589	/** Bit 8 - TSCINVAR - TSC Invariant. */
590	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
591	/** @} */
592
593
594	/** @name CR0
595	* @{ */
596	/** Bit 0 - PE - Protection Enabled */
597	#define X86_CR0_PE RT_BIT(0)
598	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
599	/** Bit 1 - MP - Monitor Coprocessor */
600	#define X86_CR0_MP RT_BIT(1)
601	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
602	/** Bit 2 - EM - Emulation. */
603	#define X86_CR0_EM RT_BIT(2)
604	#define X86_CR0_EMULATE_FPU RT_BIT(2)
605	/** Bit 3 - TS - Task Switch. */
606	#define X86_CR0_TS RT_BIT(3)
607	#define X86_CR0_TASK_SWITCH RT_BIT(3)
608	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
609	#define X86_CR0_ET RT_BIT(4)
610	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
611	/** Bit 5 - NE - Numeric error. */
612	#define X86_CR0_NE RT_BIT(5)
613	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
614	/** Bit 16 - WP - Write Protect. */
615	#define X86_CR0_WP RT_BIT(16)
616	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
617	/** Bit 18 - AM - Alignment Mask. */
618	#define X86_CR0_AM RT_BIT(18)
619	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
620	/** Bit 29 - NW - Not Write-though. */
621	#define X86_CR0_NW RT_BIT(29)
622	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
623	/** Bit 30 - WP - Cache Disable. */
624	#define X86_CR0_CD RT_BIT(30)
625	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
626	/** Bit 31 - PG - Paging. */
627	#define X86_CR0_PG RT_BIT(31)
628	#define X86_CR0_PAGING RT_BIT(31)
629	/** @} */
630
631
632	/** @name CR3
633	* @{ */
634	/** Bit 3 - PWT - Page-level Writes Transparent. */
635	#define X86_CR3_PWT RT_BIT(3)
636	/** Bit 4 - PCD - Page-level Cache Disable. */
637	#define X86_CR3_PCD RT_BIT(4)
638	/** Bits 12-31 - - Page directory page number. */
639	#define X86_CR3_PAGE_MASK (0xfffff000)
640	/** Bits 5-31 - - PAE Page directory page number. */
641	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
642	/** Bits 12-51 - - AMD64 Page directory page number. */
643	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
644	/** @} */
645
646
647	/** @name CR4
648	* @{ */
649	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
650	#define X86_CR4_VME RT_BIT(0)
651	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
652	#define X86_CR4_PVI RT_BIT(1)
653	/** Bit 2 - TSD - Time Stamp Disable. */
654	#define X86_CR4_TSD RT_BIT(2)
655	/** Bit 3 - DE - Debugging Extensions. */
656	#define X86_CR4_DE RT_BIT(3)
657	/** Bit 4 - PSE - Page Size Extension. */
658	#define X86_CR4_PSE RT_BIT(4)
659	/** Bit 5 - PAE - Physical Address Extension. */
660	#define X86_CR4_PAE RT_BIT(5)
661	/** Bit 6 - MCE - Machine-Check Enable. */
662	#define X86_CR4_MCE RT_BIT(6)
663	/** Bit 7 - PGE - Page Global Enable. */
664	#define X86_CR4_PGE RT_BIT(7)
665	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
666	#define X86_CR4_PCE RT_BIT(8)
667	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
668	#define X86_CR4_OSFSXR RT_BIT(9)
669	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
670	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
671	/** Bit 13 - VMXE - VMX mode is enabled. */
672	#define X86_CR4_VMXE RT_BIT(13)
673	/** @} */
674
675
676	/** @name DR6
677	* @{ */
678	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
679	#define X86_DR6_B0 RT_BIT(0)
680	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
681	#define X86_DR6_B1 RT_BIT(1)
682	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
683	#define X86_DR6_B2 RT_BIT(2)
684	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
685	#define X86_DR6_B3 RT_BIT(3)
686	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
687	#define X86_DR6_BD RT_BIT(13)
688	/** Bit 14 - BS - Single step */
689	#define X86_DR6_BS RT_BIT(14)
690	/** Bit 15 - BT - Task switch. (TSS T bit.) */
691	#define X86_DR6_BT RT_BIT(15)
692	/** Value of DR6 after powerup/reset. */
693	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
694	/** @} */
695
696
697	/** @name DR7
698	* @{ */
699	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
700	#define X86_DR7_L0 RT_BIT(0)
701	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
702	#define X86_DR7_G0 RT_BIT(1)
703	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
704	#define X86_DR7_L1 RT_BIT(2)
705	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
706	#define X86_DR7_G1 RT_BIT(3)
707	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
708	#define X86_DR7_L2 RT_BIT(4)
709	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
710	#define X86_DR7_G2 RT_BIT(5)
711	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
712	#define X86_DR7_L3 RT_BIT(6)
713	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
714	#define X86_DR7_G3 RT_BIT(7)
715	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
716	#define X86_DR7_LE RT_BIT(8)
717	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
718	#define X86_DR7_GE RT_BIT(9)
719
720	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
721	* any DR register is accessed. */
722	#define X86_DR7_GD RT_BIT(13)
723	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
724	#define X86_DR7_RW0_MASK (3 << 16)
725	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
726	#define X86_DR7_LEN0_MASK (3 << 18)
727	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
728	#define X86_DR7_RW1_MASK (3 << 20)
729	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
730	#define X86_DR7_LEN1_MASK (3 << 22)
731	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
732	#define X86_DR7_RW2_MASK (3 << 24)
733	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
734	#define X86_DR7_LEN2_MASK (3 << 26)
735	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
736	#define X86_DR7_RW3_MASK (3 << 28)
737	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
738	#define X86_DR7_LEN3_MASK (3 << 30)
739
740	/** Bits which must be 1s. */
741	#define X86_DR7_MB1_MASK (RT_BIT(10))
742
743	/** Calcs the L bit of Nth breakpoint.
744	* @param iBp The breakpoint number [0..3].
745	*/
746	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
747
748	/** Calcs the G bit of Nth breakpoint.
749	* @param iBp The breakpoint number [0..3].
750	*/
751	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
752
753	/** @name Read/Write values.
754	* @{ */
755	/** Break on instruction fetch only. */
756	#define X86_DR7_RW_EO 0U
757	/** Break on write only. */
758	#define X86_DR7_RW_WO 1U
759	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
760	#define X86_DR7_RW_IO 2U
761	/** Break on read or write (but not instruction fetches). */
762	#define X86_DR7_RW_RW 3U
763	/** @} */
764
765	/** Shifts a X86_DR7_RW_* value to its right place.
766	* @param iBp The breakpoint number [0..3].
767	* @param fRw One of the X86_DR7_RW_* value.
768	*/
769	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
770
771	/** @name Length values.
772	* @{ */
773	#define X86_DR7_LEN_BYTE 0U
774	#define X86_DR7_LEN_WORD 1U
775	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
776	#define X86_DR7_LEN_DWORD 3U
777	/** @} */
778
779	/** Shifts a X86_DR7_LEN_* value to its right place.
780	* @param iBp The breakpoint number [0..3].
781	* @param cb One of the X86_DR7_LEN_* values.
782	*/
783	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
784
785	/** Fetch the breakpoint length bits from the DR7 value.
786	* @param uDR7 DR7 value
787	* @param iBp The breakpoint number [0..3].
788	*/
789	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
790
791	/** Mask used to check if any breakpoints are enabled. */
792	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
793
794	/** Mask used to check if any io breakpoints are set. */
795	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
796
797	/** Value of DR7 after powerup/reset. */
798	#define X86_DR7_INIT_VAL 0x400
799	/** @} */
800
801
802	/** @name Machine Specific Registers
803	* @{
804	*/
805
806	/** Time Stamp Counter. */
807	#define MSR_IA32_TSC 0x10
808
809	#define MSR_IA32_PLATFORM_ID 0x17
810
811	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
812	#define MSR_IA32_APICBASE 0x1b
813	#endif
814
815	/** CPU Feature control. */
816	#define MSR_IA32_FEATURE_CONTROL 0x3A
817	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
818	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
819
820	/** BIOS update trigger (microcode update). */
821	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
822
823	/** BIOS update signature (microcode). */
824	#define MSR_IA32_BIOS_SIGN_ID 0x8B
825
826	/** General performance counter no. 0. */
827	#define MSR_IA32_PMC0 0xC1
828	/** General performance counter no. 1. */
829	#define MSR_IA32_PMC1 0xC2
830	/** General performance counter no. 2. */
831	#define MSR_IA32_PMC2 0xC3
832	/** General performance counter no. 3. */
833	#define MSR_IA32_PMC3 0xC4
834
835	/** Nehalem power control. */
836	#define MSR_IA32_PLATFORM_INFO 0xCE
837
838	/** Get FSB clock status (Intel-specific). */
839	#define MSR_IA32_FSB_CLOCK_STS 0xCD
840
841	/** MTRR Capabilities. */
842	#define MSR_IA32_MTRR_CAP 0xFE
843
844
845	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
846	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
847	* R0 SS == CS + 8
848	* R3 CS == CS + 16
849	* R3 SS == CS + 24
850	*/
851	#define MSR_IA32_SYSENTER_CS 0x174
852	/** SYSENTER_ESP - the R0 ESP. */
853	#define MSR_IA32_SYSENTER_ESP 0x175
854	/** SYSENTER_EIP - the R0 EIP. */
855	#define MSR_IA32_SYSENTER_EIP 0x176
856	#endif
857
858	/** Machine Check Global Capabilities Register. */
859	#define MSR_IA32_MCP_CAP 0x179
860	/** Machine Check Global Status Register. */
861	#define MSR_IA32_MCP_STATUS 0x17A
862	/** Machine Check Global Control Register. */
863	#define MSR_IA32_MCP_CTRL 0x17B
864
865	/** Trace/Profile Resource Control (R/W) */
866	#define MSR_IA32_DEBUGCTL 0x1D9
867
868	/* Page Attribute Table. */
869	#define MSR_IA32_CR_PAT 0x277
870
871	/** Performance counter MSRs. (Intel only) */
872	#define MSR_IA32_PERFEVTSEL0 0x186
873	#define MSR_IA32_PERFEVTSEL1 0x187
874	#define MSR_IA32_FLEX_RATIO 0x194
875	#define MSR_IA32_PERF_STATUS 0x198
876	#define MSR_IA32_PERF_CTL 0x199
877	#define MSR_IA32_THERM_STATUS 0x19c
878
879	/** Enable misc. processor features (R/W). */
880	#define MSR_IA32_MISC_ENABLE 0x1A0
881
882	/** MTRR Default Range. */
883	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
884
885	#define MSR_IA32_MC0_CTL 0x400
886	#define MSR_IA32_MC0_STATUS 0x401
887
888	/** Basic VMX information. */
889	#define MSR_IA32_VMX_BASIC_INFO 0x480
890	/** Allowed settings for pin-based VM execution controls */
891	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
892	/** Allowed settings for proc-based VM execution controls */
893	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
894	/** Allowed settings for the VMX exit controls. */
895	#define MSR_IA32_VMX_EXIT_CTLS 0x483
896	/** Allowed settings for the VMX entry controls. */
897	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
898	/** Misc VMX info. */
899	#define MSR_IA32_VMX_MISC 0x485
900	/** Fixed cleared bits in CR0. */
901	#define MSR_IA32_VMX_CR0_FIXED0 0x486
902	/** Fixed set bits in CR0. */
903	#define MSR_IA32_VMX_CR0_FIXED1 0x487
904	/** Fixed cleared bits in CR4. */
905	#define MSR_IA32_VMX_CR4_FIXED0 0x488
906	/** Fixed set bits in CR4. */
907	#define MSR_IA32_VMX_CR4_FIXED1 0x489
908	/** Information for enumerating fields in the VMCS. */
909	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
910	/** Allowed settings for secondary proc-based VM execution controls */
911	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
912	/** EPT capabilities. */
913	#define MSR_IA32_VMX_EPT_CAPS 0x48C
914	/** DS Save Area (R/W). */
915	#define MSR_IA32_DS_AREA 0x600
916	/** X2APIC MSR ranges. */
917	#define MSR_IA32_APIC_START 0x800
918	#define MSR_IA32_APIC_END 0x900
919
920	/** K6 EFER - Extended Feature Enable Register. */
921	#define MSR_K6_EFER 0xc0000080
922	/** @todo document EFER */
923	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
924	#define MSR_K6_EFER_SCE RT_BIT(0)
925	/** Bit 8 - LME - Long mode enabled. (R/W) */
926	#define MSR_K6_EFER_LME RT_BIT(8)
927	/** Bit 10 - LMA - Long mode active. (R) */
928	#define MSR_K6_EFER_LMA RT_BIT(10)
929	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
930	#define MSR_K6_EFER_NXE RT_BIT(11)
931	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
932	#define MSR_K6_EFER_SVME RT_BIT(12)
933	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
934	#define MSR_K6_EFER_LMSLE RT_BIT(13)
935	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
936	#define MSR_K6_EFER_FFXSR RT_BIT(14)
937	/** K6 STAR - SYSCALL/RET targets. */
938	#define MSR_K6_STAR 0xc0000081
939	/** Shift value for getting the SYSRET CS and SS value. */
940	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
941	/** Shift value for getting the SYSCALL CS and SS value. */
942	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
943	/** Selector mask for use after shifting. */
944	#define MSR_K6_STAR_SEL_MASK 0xffff
945	/** The mask which give the SYSCALL EIP. */
946	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
947	/** K6 WHCR - Write Handling Control Register. */
948	#define MSR_K6_WHCR 0xc0000082
949	/** K6 UWCCR - UC/WC Cacheability Control Register. */
950	#define MSR_K6_UWCCR 0xc0000085
951	/** K6 PSOR - Processor State Observability Register. */
952	#define MSR_K6_PSOR 0xc0000087
953	/** K6 PFIR - Page Flush/Invalidate Register. */
954	#define MSR_K6_PFIR 0xc0000088
955
956	/** Performance counter MSRs. (AMD only) */
957	#define MSR_K7_EVNTSEL0 0xc0010000
958	#define MSR_K7_EVNTSEL1 0xc0010001
959	#define MSR_K7_EVNTSEL2 0xc0010002
960	#define MSR_K7_EVNTSEL3 0xc0010003
961	#define MSR_K7_PERFCTR0 0xc0010004
962	#define MSR_K7_PERFCTR1 0xc0010005
963	#define MSR_K7_PERFCTR2 0xc0010006
964	#define MSR_K7_PERFCTR3 0xc0010007
965
966	#define MSR_K8_HWCR 0xc0010015
967
968	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
969	#define MSR_K8_LSTAR 0xc0000082
970	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
971	#define MSR_K8_CSTAR 0xc0000083
972	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
973	#define MSR_K8_SF_MASK 0xc0000084
974	/** K8 FS.base - The 64-bit base FS register. */
975	#define MSR_K8_FS_BASE 0xc0000100
976	/** K8 GS.base - The 64-bit base GS register. */
977	#define MSR_K8_GS_BASE 0xc0000101
978	/** K8 KernelGSbase - Used with SWAPGS. */
979	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
980	#define MSR_K8_TSC_AUX 0xc0000103
981	#define MSR_K8_SYSCFG 0xc0010010
982	#define MSR_K8_HWCR 0xc0010015
983	#define MSR_K8_IORRBASE0 0xc0010016
984	#define MSR_K8_IORRMASK0 0xc0010017
985	#define MSR_K8_IORRBASE1 0xc0010018
986	#define MSR_K8_IORRMASK1 0xc0010019
987	#define MSR_K8_TOP_MEM1 0xc001001a
988	#define MSR_K8_TOP_MEM2 0xc001001d
989	#define MSR_K8_VM_CR 0xc0010114
990	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
991
992	#define MSR_K8_IGNNE 0xc0010115
993	#define MSR_K8_SMM_CTL 0xc0010116
994	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
995	* host state during world switch.
996	*/
997	#define MSR_K8_VM_HSAVE_PA 0xc0010117
998
999	/** @} */
1000
1001
1002	/** @name Page Table / Directory / Directory Pointers / L4.
1003	* @{
1004	*/
1005
1006	/** Page table/directory entry as an unsigned integer. */
1007	typedef uint32_t X86PGUINT;
1008	/** Pointer to a page table/directory table entry as an unsigned integer. */
1009	typedef X86PGUINT *PX86PGUINT;
1010	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1011	typedef X86PGUINT const *PCX86PGUINT;
1012
1013	/** Number of entries in a 32-bit PT/PD. */
1014	#define X86_PG_ENTRIES 1024
1015
1016
1017	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1018	typedef uint64_t X86PGPAEUINT;
1019	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1020	typedef X86PGPAEUINT *PX86PGPAEUINT;
1021	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1022	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1023
1024	/** Number of entries in a PAE PT/PD. */
1025	#define X86_PG_PAE_ENTRIES 512
1026	/** Number of entries in a PAE PDPT. */
1027	#define X86_PG_PAE_PDPE_ENTRIES 4
1028
1029	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1030	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1031	/** Number of entries in an AMD64 PDPT.
1032	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1033	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1034
1035	/** The size of a 4KB page. */
1036	#define X86_PAGE_4K_SIZE _4K
1037	/** The page shift of a 4KB page. */
1038	#define X86_PAGE_4K_SHIFT 12
1039	/** The 4KB page offset mask. */
1040	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1041	/** The 4KB page base mask for virtual addresses. */
1042	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1043	/** The 4KB page base mask for virtual addresses - 32bit version. */
1044	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1045
1046	/** The size of a 2MB page. */
1047	#define X86_PAGE_2M_SIZE _2M
1048	/** The page shift of a 2MB page. */
1049	#define X86_PAGE_2M_SHIFT 21
1050	/** The 2MB page offset mask. */
1051	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1052	/** The 2MB page base mask for virtual addresses. */
1053	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1054	/** The 2MB page base mask for virtual addresses - 32bit version. */
1055	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1056
1057	/** The size of a 4MB page. */
1058	#define X86_PAGE_4M_SIZE _4M
1059	/** The page shift of a 4MB page. */
1060	#define X86_PAGE_4M_SHIFT 22
1061	/** The 4MB page offset mask. */
1062	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1063	/** The 4MB page base mask for virtual addresses. */
1064	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1065	/** The 4MB page base mask for virtual addresses - 32bit version. */
1066	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1067
1068
1069
1070	/** @name Page Table Entry
1071	* @{
1072	*/
1073	/** Bit 0 - P - Present bit. */
1074	#define X86_PTE_BIT_P 0
1075	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1076	#define X86_PTE_BIT_RW 1
1077	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1078	#define X86_PTE_BIT_US 2
1079	/** Bit 3 - PWT - Page level write thru bit. */
1080	#define X86_PTE_BIT_PWT 3
1081	/** Bit 4 - PCD - Page level cache disable bit. */
1082	#define X86_PTE_BIT_PCD 4
1083	/** Bit 5 - A - Access bit. */
1084	#define X86_PTE_BIT_A 5
1085	/** Bit 6 - D - Dirty bit. */
1086	#define X86_PTE_BIT_D 6
1087	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1088	#define X86_PTE_BIT_PAT 7
1089	/** Bit 8 - G - Global flag. */
1090	#define X86_PTE_BIT_G 8
1091
1092	/** Bit 0 - P - Present bit mask. */
1093	#define X86_PTE_P RT_BIT(0)
1094	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1095	#define X86_PTE_RW RT_BIT(1)
1096	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1097	#define X86_PTE_US RT_BIT(2)
1098	/** Bit 3 - PWT - Page level write thru bit mask. */
1099	#define X86_PTE_PWT RT_BIT(3)
1100	/** Bit 4 - PCD - Page level cache disable bit mask. */
1101	#define X86_PTE_PCD RT_BIT(4)
1102	/** Bit 5 - A - Access bit mask. */
1103	#define X86_PTE_A RT_BIT(5)
1104	/** Bit 6 - D - Dirty bit mask. */
1105	#define X86_PTE_D RT_BIT(6)
1106	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1107	#define X86_PTE_PAT RT_BIT(7)
1108	/** Bit 8 - G - Global bit mask. */
1109	#define X86_PTE_G RT_BIT(8)
1110
1111	/** Bits 9-11 - - Available for use to system software. */
1112	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1113	/** Bits 12-31 - - Physical Page number of the next level. */
1114	#define X86_PTE_PG_MASK ( 0xfffff000 )
1115
1116	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1117	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1118	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1119	/** @todo Get rid of the above hack; makes code unreadable. */
1120	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1121	#else
1122	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1123	#endif
1124	/** Bits 63 - NX - PAE - No execution flag. */
1125	#define X86_PTE_PAE_NX RT_BIT_64(63)
1126
1127	/**
1128	* Page table entry.
1129	*/
1130	typedef struct X86PTEBITS
1131	{
1132	/** Flags whether(=1) or not the page is present. */
1133	unsigned u1Present : 1;
1134	/** Read(=0) / Write(=1) flag. */
1135	unsigned u1Write : 1;
1136	/** User(=1) / Supervisor (=0) flag. */
1137	unsigned u1User : 1;
1138	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1139	unsigned u1WriteThru : 1;
1140	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1141	unsigned u1CacheDisable : 1;
1142	/** Accessed flag.
1143	* Indicates that the page have been read or written to. */
1144	unsigned u1Accessed : 1;
1145	/** Dirty flag.
1146	* Indicates that the page has been written to. */
1147	unsigned u1Dirty : 1;
1148	/** Reserved / If PAT enabled, bit 2 of the index. */
1149	unsigned u1PAT : 1;
1150	/** Global flag. (Ignored in all but final level.) */
1151	unsigned u1Global : 1;
1152	/** Available for use to system software. */
1153	unsigned u3Available : 3;
1154	/** Physical Page number of the next level. */
1155	unsigned u20PageNo : 20;
1156	} X86PTEBITS;
1157	/** Pointer to a page table entry. */
1158	typedef X86PTEBITS *PX86PTEBITS;
1159	/** Pointer to a const page table entry. */
1160	typedef const X86PTEBITS *PCX86PTEBITS;
1161
1162	/**
1163	* Page table entry.
1164	*/
1165	typedef union X86PTE
1166	{
1167	/** Unsigned integer view */
1168	X86PGUINT u;
1169	/** Bit field view. */
1170	X86PTEBITS n;
1171	/** 32-bit view. */
1172	uint32_t au32[1];
1173	/** 16-bit view. */
1174	uint16_t au16[2];
1175	/** 8-bit view. */
1176	uint8_t au8[4];
1177	} X86PTE;
1178	/** Pointer to a page table entry. */
1179	typedef X86PTE *PX86PTE;
1180	/** Pointer to a const page table entry. */
1181	typedef const X86PTE *PCX86PTE;
1182
1183
1184	/**
1185	* PAE page table entry.
1186	*/
1187	typedef struct X86PTEPAEBITS
1188	{
1189	/** Flags whether(=1) or not the page is present. */
1190	uint32_t u1Present : 1;
1191	/** Read(=0) / Write(=1) flag. */
1192	uint32_t u1Write : 1;
1193	/** User(=1) / Supervisor(=0) flag. */
1194	uint32_t u1User : 1;
1195	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1196	uint32_t u1WriteThru : 1;
1197	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1198	uint32_t u1CacheDisable : 1;
1199	/** Accessed flag.
1200	* Indicates that the page have been read or written to. */
1201	uint32_t u1Accessed : 1;
1202	/** Dirty flag.
1203	* Indicates that the page has been written to. */
1204	uint32_t u1Dirty : 1;
1205	/** Reserved / If PAT enabled, bit 2 of the index. */
1206	uint32_t u1PAT : 1;
1207	/** Global flag. (Ignored in all but final level.) */
1208	uint32_t u1Global : 1;
1209	/** Available for use to system software. */
1210	uint32_t u3Available : 3;
1211	/** Physical Page number of the next level - Low Part. Don't use this. */
1212	uint32_t u20PageNoLow : 20;
1213	/** Physical Page number of the next level - High Part. Don't use this. */
1214	uint32_t u20PageNoHigh : 20;
1215	/** MBZ bits */
1216	uint32_t u11Reserved : 11;
1217	/** No Execute flag. */
1218	uint32_t u1NoExecute : 1;
1219	} X86PTEPAEBITS;
1220	/** Pointer to a page table entry. */
1221	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1222	/** Pointer to a page table entry. */
1223	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1224
1225	/**
1226	* PAE Page table entry.
1227	*/
1228	typedef union X86PTEPAE
1229	{
1230	/** Unsigned integer view */
1231	X86PGPAEUINT u;
1232	/** Bit field view. */
1233	X86PTEPAEBITS n;
1234	/** 32-bit view. */
1235	uint32_t au32[2];
1236	/** 16-bit view. */
1237	uint16_t au16[4];
1238	/** 8-bit view. */
1239	uint8_t au8[8];
1240	} X86PTEPAE;
1241	/** Pointer to a PAE page table entry. */
1242	typedef X86PTEPAE *PX86PTEPAE;
1243	/** Pointer to a const PAE page table entry. */
1244	typedef const X86PTEPAE *PCX86PTEPAE;
1245	/** @} */
1246
1247	/**
1248	* Page table.
1249	*/
1250	typedef struct X86PT
1251	{
1252	/** PTE Array. */
1253	X86PTE a[X86_PG_ENTRIES];
1254	} X86PT;
1255	/** Pointer to a page table. */
1256	typedef X86PT *PX86PT;
1257	/** Pointer to a const page table. */
1258	typedef const X86PT *PCX86PT;
1259
1260	/** The page shift to get the PT index. */
1261	#define X86_PT_SHIFT 12
1262	/** The PT index mask (apply to a shifted page address). */
1263	#define X86_PT_MASK 0x3ff
1264
1265
1266	/**
1267	* Page directory.
1268	*/
1269	typedef struct X86PTPAE
1270	{
1271	/** PTE Array. */
1272	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1273	} X86PTPAE;
1274	/** Pointer to a page table. */
1275	typedef X86PTPAE *PX86PTPAE;
1276	/** Pointer to a const page table. */
1277	typedef const X86PTPAE *PCX86PTPAE;
1278
1279	/** The page shift to get the PA PTE index. */
1280	#define X86_PT_PAE_SHIFT 12
1281	/** The PAE PT index mask (apply to a shifted page address). */
1282	#define X86_PT_PAE_MASK 0x1ff
1283
1284
1285	/** @name 4KB Page Directory Entry
1286	* @{
1287	*/
1288	/** Bit 0 - P - Present bit. */
1289	#define X86_PDE_P RT_BIT(0)
1290	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1291	#define X86_PDE_RW RT_BIT(1)
1292	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1293	#define X86_PDE_US RT_BIT(2)
1294	/** Bit 3 - PWT - Page level write thru bit. */
1295	#define X86_PDE_PWT RT_BIT(3)
1296	/** Bit 4 - PCD - Page level cache disable bit. */
1297	#define X86_PDE_PCD RT_BIT(4)
1298	/** Bit 5 - A - Access bit. */
1299	#define X86_PDE_A RT_BIT(5)
1300	/** Bit 7 - PS - Page size attribute.
1301	* Clear mean 4KB pages, set means large pages (2/4MB). */
1302	#define X86_PDE_PS RT_BIT(7)
1303	/** Bits 9-11 - - Available for use to system software. */
1304	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1305	/** Bits 12-31 - - Physical Page number of the next level. */
1306	#define X86_PDE_PG_MASK ( 0xfffff000 )
1307
1308	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1309	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1310	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1311	* we partly or that part into shadow page table entries. Will be corrected
1312	* soon.
1313	*/
1314	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1315	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1316	#else
1317	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1318	#endif
1319	/** Bits 63 - NX - PAE - No execution flag. */
1320	#define X86_PDE_PAE_NX RT_BIT_64(63)
1321
1322	/**
1323	* Page directory entry.
1324	*/
1325	typedef struct X86PDEBITS
1326	{
1327	/** Flags whether(=1) or not the page is present. */
1328	unsigned u1Present : 1;
1329	/** Read(=0) / Write(=1) flag. */
1330	unsigned u1Write : 1;
1331	/** User(=1) / Supervisor (=0) flag. */
1332	unsigned u1User : 1;
1333	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1334	unsigned u1WriteThru : 1;
1335	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1336	unsigned u1CacheDisable : 1;
1337	/** Accessed flag.
1338	* Indicates that the page has been read or written to. */
1339	unsigned u1Accessed : 1;
1340	/** Reserved / Ignored (dirty bit). */
1341	unsigned u1Reserved0 : 1;
1342	/** Size bit if PSE is enabled - in any event it's 0. */
1343	unsigned u1Size : 1;
1344	/** Reserved / Ignored (global bit). */
1345	unsigned u1Reserved1 : 1;
1346	/** Available for use to system software. */
1347	unsigned u3Available : 3;
1348	/** Physical Page number of the next level. */
1349	unsigned u20PageNo : 20;
1350	} X86PDEBITS;
1351	/** Pointer to a page directory entry. */
1352	typedef X86PDEBITS *PX86PDEBITS;
1353	/** Pointer to a const page directory entry. */
1354	typedef const X86PDEBITS *PCX86PDEBITS;
1355
1356
1357	/**
1358	* PAE page directory entry.
1359	*/
1360	typedef struct X86PDEPAEBITS
1361	{
1362	/** Flags whether(=1) or not the page is present. */
1363	uint32_t u1Present : 1;
1364	/** Read(=0) / Write(=1) flag. */
1365	uint32_t u1Write : 1;
1366	/** User(=1) / Supervisor (=0) flag. */
1367	uint32_t u1User : 1;
1368	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1369	uint32_t u1WriteThru : 1;
1370	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1371	uint32_t u1CacheDisable : 1;
1372	/** Accessed flag.
1373	* Indicates that the page has been read or written to. */
1374	uint32_t u1Accessed : 1;
1375	/** Reserved / Ignored (dirty bit). */
1376	uint32_t u1Reserved0 : 1;
1377	/** Size bit if PSE is enabled - in any event it's 0. */
1378	uint32_t u1Size : 1;
1379	/** Reserved / Ignored (global bit). / */
1380	uint32_t u1Reserved1 : 1;
1381	/** Available for use to system software. */
1382	uint32_t u3Available : 3;
1383	/** Physical Page number of the next level - Low Part. Don't use! */
1384	uint32_t u20PageNoLow : 20;
1385	/** Physical Page number of the next level - High Part. Don't use! */
1386	uint32_t u20PageNoHigh : 20;
1387	/** MBZ bits */
1388	uint32_t u11Reserved : 11;
1389	/** No Execute flag. */
1390	uint32_t u1NoExecute : 1;
1391	} X86PDEPAEBITS;
1392	/** Pointer to a page directory entry. */
1393	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1394	/** Pointer to a const page directory entry. */
1395	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1396
1397	/** @} */
1398
1399
1400	/** @name 2/4MB Page Directory Entry
1401	* @{
1402	*/
1403	/** Bit 0 - P - Present bit. */
1404	#define X86_PDE4M_P RT_BIT(0)
1405	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1406	#define X86_PDE4M_RW RT_BIT(1)
1407	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1408	#define X86_PDE4M_US RT_BIT(2)
1409	/** Bit 3 - PWT - Page level write thru bit. */
1410	#define X86_PDE4M_PWT RT_BIT(3)
1411	/** Bit 4 - PCD - Page level cache disable bit. */
1412	#define X86_PDE4M_PCD RT_BIT(4)
1413	/** Bit 5 - A - Access bit. */
1414	#define X86_PDE4M_A RT_BIT(5)
1415	/** Bit 6 - D - Dirty bit. */
1416	#define X86_PDE4M_D RT_BIT(6)
1417	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1418	#define X86_PDE4M_PS RT_BIT(7)
1419	/** Bit 8 - G - Global flag. */
1420	#define X86_PDE4M_G RT_BIT(8)
1421	/** Bits 9-11 - AVL - Available for use to system software. */
1422	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1423	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1424	#define X86_PDE4M_PAT RT_BIT(12)
1425	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1426	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1427	/** Bits 22-31 - - Physical Page number. */
1428	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1429	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1430	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1431	/** The number of bits to the high part of the page number. */
1432	#define X86_PDE4M_PG_HIGH_SHIFT 19
1433
1434	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1435	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1436	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1437	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1438	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1439
1440	/**
1441	* 4MB page directory entry.
1442	*/
1443	typedef struct X86PDE4MBITS
1444	{
1445	/** Flags whether(=1) or not the page is present. */
1446	unsigned u1Present : 1;
1447	/** Read(=0) / Write(=1) flag. */
1448	unsigned u1Write : 1;
1449	/** User(=1) / Supervisor (=0) flag. */
1450	unsigned u1User : 1;
1451	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1452	unsigned u1WriteThru : 1;
1453	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1454	unsigned u1CacheDisable : 1;
1455	/** Accessed flag.
1456	* Indicates that the page have been read or written to. */
1457	unsigned u1Accessed : 1;
1458	/** Dirty flag.
1459	* Indicates that the page has been written to. */
1460	unsigned u1Dirty : 1;
1461	/** Page size flag - always 1 for 4MB entries. */
1462	unsigned u1Size : 1;
1463	/** Global flag. */
1464	unsigned u1Global : 1;
1465	/** Available for use to system software. */
1466	unsigned u3Available : 3;
1467	/** Reserved / If PAT enabled, bit 2 of the index. */
1468	unsigned u1PAT : 1;
1469	/** Bits 32-39 of the page number on AMD64.
1470	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1471	unsigned u8PageNoHigh : 8;
1472	/** Reserved. */
1473	unsigned u1Reserved : 1;
1474	/** Physical Page number of the page. */
1475	unsigned u10PageNo : 10;
1476	} X86PDE4MBITS;
1477	/** Pointer to a page table entry. */
1478	typedef X86PDE4MBITS *PX86PDE4MBITS;
1479	/** Pointer to a const page table entry. */
1480	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1481
1482
1483	/**
1484	* 2MB PAE page directory entry.
1485	*/
1486	typedef struct X86PDE2MPAEBITS
1487	{
1488	/** Flags whether(=1) or not the page is present. */
1489	uint32_t u1Present : 1;
1490	/** Read(=0) / Write(=1) flag. */
1491	uint32_t u1Write : 1;
1492	/** User(=1) / Supervisor(=0) flag. */
1493	uint32_t u1User : 1;
1494	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1495	uint32_t u1WriteThru : 1;
1496	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1497	uint32_t u1CacheDisable : 1;
1498	/** Accessed flag.
1499	* Indicates that the page have been read or written to. */
1500	uint32_t u1Accessed : 1;
1501	/** Dirty flag.
1502	* Indicates that the page has been written to. */
1503	uint32_t u1Dirty : 1;
1504	/** Page size flag - always 1 for 2MB entries. */
1505	uint32_t u1Size : 1;
1506	/** Global flag. */
1507	uint32_t u1Global : 1;
1508	/** Available for use to system software. */
1509	uint32_t u3Available : 3;
1510	/** Reserved / If PAT enabled, bit 2 of the index. */
1511	uint32_t u1PAT : 1;
1512	/** Reserved. */
1513	uint32_t u9Reserved : 9;
1514	/** Physical Page number of the next level - Low part. Don't use! */
1515	uint32_t u10PageNoLow : 10;
1516	/** Physical Page number of the next level - High part. Don't use! */
1517	uint32_t u20PageNoHigh : 20;
1518	/** MBZ bits */
1519	uint32_t u11Reserved : 11;
1520	/** No Execute flag. */
1521	uint32_t u1NoExecute : 1;
1522	} X86PDE2MPAEBITS;
1523	/** Pointer to a 2MB PAE page table entry. */
1524	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1525	/** Pointer to a 2MB PAE page table entry. */
1526	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1527
1528	/** @} */
1529
1530	/**
1531	* Page directory entry.
1532	*/
1533	typedef union X86PDE
1534	{
1535	/** Unsigned integer view. */
1536	X86PGUINT u;
1537	/** Normal view. */
1538	X86PDEBITS n;
1539	/** 4MB view (big). */
1540	X86PDE4MBITS b;
1541	/** 8 bit unsigned integer view. */
1542	uint8_t au8[4];
1543	/** 16 bit unsigned integer view. */
1544	uint16_t au16[2];
1545	/** 32 bit unsigned integer view. */
1546	uint32_t au32[1];
1547	} X86PDE;
1548	/** Pointer to a page directory entry. */
1549	typedef X86PDE *PX86PDE;
1550	/** Pointer to a const page directory entry. */
1551	typedef const X86PDE *PCX86PDE;
1552
1553	/**
1554	* PAE page directory entry.
1555	*/
1556	typedef union X86PDEPAE
1557	{
1558	/** Unsigned integer view. */
1559	X86PGPAEUINT u;
1560	/** Normal view. */
1561	X86PDEPAEBITS n;
1562	/** 2MB page view (big). */
1563	X86PDE2MPAEBITS b;
1564	/** 8 bit unsigned integer view. */
1565	uint8_t au8[8];
1566	/** 16 bit unsigned integer view. */
1567	uint16_t au16[4];
1568	/** 32 bit unsigned integer view. */
1569	uint32_t au32[2];
1570	} X86PDEPAE;
1571	/** Pointer to a page directory entry. */
1572	typedef X86PDEPAE *PX86PDEPAE;
1573	/** Pointer to a const page directory entry. */
1574	typedef const X86PDEPAE *PCX86PDEPAE;
1575
1576	/**
1577	* Page directory.
1578	*/
1579	typedef struct X86PD
1580	{
1581	/** PDE Array. */
1582	X86PDE a[X86_PG_ENTRIES];
1583	} X86PD;
1584	/** Pointer to a page directory. */
1585	typedef X86PD *PX86PD;
1586	/** Pointer to a const page directory. */
1587	typedef const X86PD *PCX86PD;
1588
1589	/** The page shift to get the PD index. */
1590	#define X86_PD_SHIFT 22
1591	/** The PD index mask (apply to a shifted page address). */
1592	#define X86_PD_MASK 0x3ff
1593
1594
1595	/**
1596	* PAE page directory.
1597	*/
1598	typedef struct X86PDPAE
1599	{
1600	/** PDE Array. */
1601	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1602	} X86PDPAE;
1603	/** Pointer to a PAE page directory. */
1604	typedef X86PDPAE *PX86PDPAE;
1605	/** Pointer to a const PAE page directory. */
1606	typedef const X86PDPAE *PCX86PDPAE;
1607
1608	/** The page shift to get the PAE PD index. */
1609	#define X86_PD_PAE_SHIFT 21
1610	/** The PAE PD index mask (apply to a shifted page address). */
1611	#define X86_PD_PAE_MASK 0x1ff
1612
1613
1614	/** @name Page Directory Pointer Table Entry (PAE)
1615	* @{
1616	*/
1617	/** Bit 0 - P - Present bit. */
1618	#define X86_PDPE_P RT_BIT(0)
1619	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1620	#define X86_PDPE_RW RT_BIT(1)
1621	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1622	#define X86_PDPE_US RT_BIT(2)
1623	/** Bit 3 - PWT - Page level write thru bit. */
1624	#define X86_PDPE_PWT RT_BIT(3)
1625	/** Bit 4 - PCD - Page level cache disable bit. */
1626	#define X86_PDPE_PCD RT_BIT(4)
1627	/** Bit 5 - A - Access bit. Long Mode only. */
1628	#define X86_PDPE_A RT_BIT(5)
1629	/** Bits 9-11 - - Available for use to system software. */
1630	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1631	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1632	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1633	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1634	/** @todo Get rid of the above hack; makes code unreadable. */
1635	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1636	#else
1637	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1638	#endif
1639	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1640	#define X86_PDPE_NX RT_BIT_64(63)
1641
1642	/**
1643	* Page directory pointer table entry.
1644	*/
1645	typedef struct X86PDPEBITS
1646	{
1647	/** Flags whether(=1) or not the page is present. */
1648	uint32_t u1Present : 1;
1649	/** Chunk of reserved bits. */
1650	uint32_t u2Reserved : 2;
1651	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1652	uint32_t u1WriteThru : 1;
1653	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1654	uint32_t u1CacheDisable : 1;
1655	/** Chunk of reserved bits. */
1656	uint32_t u4Reserved : 4;
1657	/** Available for use to system software. */
1658	uint32_t u3Available : 3;
1659	/** Physical Page number of the next level - Low Part. Don't use! */
1660	uint32_t u20PageNoLow : 20;
1661	/** Physical Page number of the next level - High Part. Don't use! */
1662	uint32_t u20PageNoHigh : 20;
1663	/** MBZ bits */
1664	uint32_t u12Reserved : 12;
1665	} X86PDPEBITS;
1666	/** Pointer to a page directory pointer table entry. */
1667	typedef X86PDPEBITS *PX86PTPEBITS;
1668	/** Pointer to a const page directory pointer table entry. */
1669	typedef const X86PDPEBITS *PCX86PTPEBITS;
1670
1671	/**
1672	* Page directory pointer table entry. AMD64 version
1673	*/
1674	typedef struct X86PDPEAMD64BITS
1675	{
1676	/** Flags whether(=1) or not the page is present. */
1677	uint32_t u1Present : 1;
1678	/** Read(=0) / Write(=1) flag. */
1679	uint32_t u1Write : 1;
1680	/** User(=1) / Supervisor (=0) flag. */
1681	uint32_t u1User : 1;
1682	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1683	uint32_t u1WriteThru : 1;
1684	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1685	uint32_t u1CacheDisable : 1;
1686	/** Accessed flag.
1687	* Indicates that the page have been read or written to. */
1688	uint32_t u1Accessed : 1;
1689	/** Chunk of reserved bits. */
1690	uint32_t u3Reserved : 3;
1691	/** Available for use to system software. */
1692	uint32_t u3Available : 3;
1693	/** Physical Page number of the next level - Low Part. Don't use! */
1694	uint32_t u20PageNoLow : 20;
1695	/** Physical Page number of the next level - High Part. Don't use! */
1696	uint32_t u20PageNoHigh : 20;
1697	/** MBZ bits */
1698	uint32_t u11Reserved : 11;
1699	/** No Execute flag. */
1700	uint32_t u1NoExecute : 1;
1701	} X86PDPEAMD64BITS;
1702	/** Pointer to a page directory pointer table entry. */
1703	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1704	/** Pointer to a const page directory pointer table entry. */
1705	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1706
1707	/**
1708	* Page directory pointer table entry.
1709	*/
1710	typedef union X86PDPE
1711	{
1712	/** Unsigned integer view. */
1713	X86PGPAEUINT u;
1714	/** Normal view. */
1715	X86PDPEBITS n;
1716	/** AMD64 view. */
1717	X86PDPEAMD64BITS lm;
1718	/** 8 bit unsigned integer view. */
1719	uint8_t au8[8];
1720	/** 16 bit unsigned integer view. */
1721	uint16_t au16[4];
1722	/** 32 bit unsigned integer view. */
1723	uint32_t au32[2];
1724	} X86PDPE;
1725	/** Pointer to a page directory pointer table entry. */
1726	typedef X86PDPE *PX86PDPE;
1727	/** Pointer to a const page directory pointer table entry. */
1728	typedef const X86PDPE *PCX86PDPE;
1729
1730
1731	/**
1732	* Page directory pointer table.
1733	*/
1734	typedef struct X86PDPT
1735	{
1736	/** PDE Array. */
1737	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1738	} X86PDPT;
1739	/** Pointer to a page directory pointer table. */
1740	typedef X86PDPT *PX86PDPT;
1741	/** Pointer to a const page directory pointer table. */
1742	typedef const X86PDPT *PCX86PDPT;
1743
1744	/** The page shift to get the PDPT index. */
1745	#define X86_PDPT_SHIFT 30
1746	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1747	#define X86_PDPT_MASK_PAE 0x3
1748	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1749	#define X86_PDPT_MASK_AMD64 0x1ff
1750
1751	/** @} */
1752
1753
1754	/** @name Page Map Level-4 Entry (Long Mode PAE)
1755	* @{
1756	*/
1757	/** Bit 0 - P - Present bit. */
1758	#define X86_PML4E_P RT_BIT(0)
1759	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1760	#define X86_PML4E_RW RT_BIT(1)
1761	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1762	#define X86_PML4E_US RT_BIT(2)
1763	/** Bit 3 - PWT - Page level write thru bit. */
1764	#define X86_PML4E_PWT RT_BIT(3)
1765	/** Bit 4 - PCD - Page level cache disable bit. */
1766	#define X86_PML4E_PCD RT_BIT(4)
1767	/** Bit 5 - A - Access bit. */
1768	#define X86_PML4E_A RT_BIT(5)
1769	/** Bits 9-11 - - Available for use to system software. */
1770	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1771	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1772	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1773	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1774	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1775	#else
1776	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1777	#endif
1778	/** Bits 63 - NX - PAE - No execution flag. */
1779	#define X86_PML4E_NX RT_BIT_64(63)
1780
1781	/**
1782	* Page Map Level-4 Entry
1783	*/
1784	typedef struct X86PML4EBITS
1785	{
1786	/** Flags whether(=1) or not the page is present. */
1787	uint32_t u1Present : 1;
1788	/** Read(=0) / Write(=1) flag. */
1789	uint32_t u1Write : 1;
1790	/** User(=1) / Supervisor (=0) flag. */
1791	uint32_t u1User : 1;
1792	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1793	uint32_t u1WriteThru : 1;
1794	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1795	uint32_t u1CacheDisable : 1;
1796	/** Accessed flag.
1797	* Indicates that the page have been read or written to. */
1798	uint32_t u1Accessed : 1;
1799	/** Chunk of reserved bits. */
1800	uint32_t u3Reserved : 3;
1801	/** Available for use to system software. */
1802	uint32_t u3Available : 3;
1803	/** Physical Page number of the next level - Low Part. Don't use! */
1804	uint32_t u20PageNoLow : 20;
1805	/** Physical Page number of the next level - High Part. Don't use! */
1806	uint32_t u20PageNoHigh : 20;
1807	/** MBZ bits */
1808	uint32_t u11Reserved : 11;
1809	/** No Execute flag. */
1810	uint32_t u1NoExecute : 1;
1811	} X86PML4EBITS;
1812	/** Pointer to a page map level-4 entry. */
1813	typedef X86PML4EBITS *PX86PML4EBITS;
1814	/** Pointer to a const page map level-4 entry. */
1815	typedef const X86PML4EBITS *PCX86PML4EBITS;
1816
1817	/**
1818	* Page Map Level-4 Entry.
1819	*/
1820	typedef union X86PML4E
1821	{
1822	/** Unsigned integer view. */
1823	X86PGPAEUINT u;
1824	/** Normal view. */
1825	X86PML4EBITS n;
1826	/** 8 bit unsigned integer view. */
1827	uint8_t au8[8];
1828	/** 16 bit unsigned integer view. */
1829	uint16_t au16[4];
1830	/** 32 bit unsigned integer view. */
1831	uint32_t au32[2];
1832	} X86PML4E;
1833	/** Pointer to a page map level-4 entry. */
1834	typedef X86PML4E *PX86PML4E;
1835	/** Pointer to a const page map level-4 entry. */
1836	typedef const X86PML4E *PCX86PML4E;
1837
1838
1839	/**
1840	* Page Map Level-4.
1841	*/
1842	typedef struct X86PML4
1843	{
1844	/** PDE Array. */
1845	X86PML4E a[X86_PG_PAE_ENTRIES];
1846	} X86PML4;
1847	/** Pointer to a page map level-4. */
1848	typedef X86PML4 *PX86PML4;
1849	/** Pointer to a const page map level-4. */
1850	typedef const X86PML4 *PCX86PML4;
1851
1852	/** The page shift to get the PML4 index. */
1853	#define X86_PML4_SHIFT 39
1854	/** The PML4 index mask (apply to a shifted page address). */
1855	#define X86_PML4_MASK 0x1ff
1856
1857	/** @} */
1858
1859	/** @} */
1860
1861
1862	/**
1863	* 80-bit MMX/FPU register type.
1864	*/
1865	typedef struct X86FPUMMX
1866	{
1867	uint8_t reg[10];
1868	} X86FPUMMX;
1869	/** Pointer to a 80-bit MMX/FPU register type. */
1870	typedef X86FPUMMX *PX86FPUMMX;
1871	/** Pointer to a const 80-bit MMX/FPU register type. */
1872	typedef const X86FPUMMX *PCX86FPUMMX;
1873
1874	/**
1875	* FPU state (aka FSAVE/FRSTOR Memory Region).
1876	*/
1877	#pragma pack(1)
1878	typedef struct X86FPUSTATE
1879	{
1880	/** Control word. */
1881	uint16_t FCW;
1882	/** Alignment word */
1883	uint16_t Dummy1;
1884	/** Status word. */
1885	uint16_t FSW;
1886	/** Alignment word */
1887	uint16_t Dummy2;
1888	/** Tag word */
1889	uint16_t FTW;
1890	/** Alignment word */
1891	uint16_t Dummy3;
1892
1893	/** Instruction pointer. */
1894	uint32_t FPUIP;
1895	/** Code selector. */
1896	uint16_t CS;
1897	/** Opcode. */
1898	uint16_t FOP;
1899	/** FOO. */
1900	uint32_t FPUOO;
1901	/** FOS. */
1902	uint32_t FPUOS;
1903	/** FPU view - todo. */
1904	X86FPUMMX regs[8];
1905	} X86FPUSTATE;
1906	#pragma pack()
1907	/** Pointer to a FPU state. */
1908	typedef X86FPUSTATE *PX86FPUSTATE;
1909	/** Pointer to a const FPU state. */
1910	typedef const X86FPUSTATE *PCX86FPUSTATE;
1911
1912	/**
1913	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1914	*/
1915	#pragma pack(1)
1916	typedef struct X86FXSTATE
1917	{
1918	/** Control word. */
1919	uint16_t FCW;
1920	/** Status word. */
1921	uint16_t FSW;
1922	/** Tag word. (The upper byte is always zero.) */
1923	uint16_t FTW;
1924	/** Opcode. */
1925	uint16_t FOP;
1926	/** Instruction pointer. */
1927	uint32_t FPUIP;
1928	/** Code selector. */
1929	uint16_t CS;
1930	uint16_t Rsvrd1;
1931	/* - offset 16 - */
1932	/** Data pointer. */
1933	uint32_t FPUDP;
1934	/** Data segment */
1935	uint16_t DS;
1936	uint16_t Rsrvd2;
1937	uint32_t MXCSR;
1938	uint32_t MXCSR_MASK;
1939	/* - offset 32 - */
1940	union
1941	{
1942	/** MMX view. */
1943	uint64_t mmx;
1944	/** FPU view - todo. */
1945	X86FPUMMX fpu;
1946	/** 8-bit view. */
1947	uint8_t au8[16];
1948	/** 16-bit view. */
1949	uint16_t au16[8];
1950	/** 32-bit view. */
1951	uint32_t au32[4];
1952	/** 64-bit view. */
1953	uint64_t au64[2];
1954	/** 128-bit view. (yeah, very helpful) */
1955	uint128_t au128[1];
1956	} aRegs[8];
1957	/* - offset 160 - */
1958	union
1959	{
1960	/** XMM Register view . /
1961	uint128_t xmm;
1962	/** 8-bit view. */
1963	uint8_t au8[16];
1964	/** 16-bit view. */
1965	uint16_t au16[8];
1966	/** 32-bit view. */
1967	uint32_t au32[4];
1968	/** 64-bit view. */
1969	uint64_t au64[2];
1970	/** 128-bit view. (yeah, very helpful) */
1971	uint128_t au128[1];
1972	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1973	/* - offset 416 - */
1974	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1975	} X86FXSTATE;
1976	#pragma pack()
1977	/** Pointer to a FPU Extended state. */
1978	typedef X86FXSTATE *PX86FXSTATE;
1979	/** Pointer to a const FPU Extended state. */
1980	typedef const X86FXSTATE *PCX86FXSTATE;
1981
1982
1983	/** @name Selector Descriptor
1984	* @{
1985	*/
1986
1987	/**
1988	* Descriptor attributes.
1989	*/
1990	typedef struct X86DESCATTRBITS
1991	{
1992	/** 00 - Segment Type. */
1993	unsigned u4Type : 4;
1994	/** 04 - Descriptor Type. System(=0) or code/data selector */
1995	unsigned u1DescType : 1;
1996	/** 05 - Descriptor Privelege level. */
1997	unsigned u2Dpl : 2;
1998	/** 07 - Flags selector present(=1) or not. */
1999	unsigned u1Present : 1;
2000	/** 08 - Segment limit 16-19. */
2001	unsigned u4LimitHigh : 4;
2002	/** 0c - Available for system software. */
2003	unsigned u1Available : 1;
2004	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2005	unsigned u1Long : 1;
2006	/** 0e - This flags meaning depends on the segment type. Try make sense out
2007	* of the intel manual yourself. */
2008	unsigned u1DefBig : 1;
2009	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2010	* clear byte. */
2011	unsigned u1Granularity : 1;
2012	} X86DESCATTRBITS;
2013
2014
2015	#pragma pack(1)
2016	typedef union X86DESCATTR
2017	{
2018	/** Unsigned integer view. */
2019	uint32_t u;
2020	/** Normal view. */
2021	X86DESCATTRBITS n;
2022	} X86DESCATTR;
2023	#pragma pack()
2024	/** Pointer to descriptor attributes. */
2025	typedef X86DESCATTR *PX86DESCATTR;
2026	/** Pointer to const descriptor attributes. */
2027	typedef const X86DESCATTR *PCX86DESCATTR;
2028
2029
2030	/**
2031	* Generic descriptor table entry
2032	*/
2033	#pragma pack(1)
2034	typedef struct X86DESCGENERIC
2035	{
2036	/** Limit - Low word. */
2037	unsigned u16LimitLow : 16;
2038	/** Base address - lowe word.
2039	* Don't try set this to 24 because MSC is doing stupid things then. */
2040	unsigned u16BaseLow : 16;
2041	/** Base address - first 8 bits of high word. */
2042	unsigned u8BaseHigh1 : 8;
2043	/** Segment Type. */
2044	unsigned u4Type : 4;
2045	/** Descriptor Type. System(=0) or code/data selector */
2046	unsigned u1DescType : 1;
2047	/** Descriptor Privelege level. */
2048	unsigned u2Dpl : 2;
2049	/** Flags selector present(=1) or not. */
2050	unsigned u1Present : 1;
2051	/** Segment limit 16-19. */
2052	unsigned u4LimitHigh : 4;
2053	/** Available for system software. */
2054	unsigned u1Available : 1;
2055	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2056	unsigned u1Long : 1;
2057	/** This flags meaning depends on the segment type. Try make sense out
2058	* of the intel manual yourself. */
2059	unsigned u1DefBig : 1;
2060	/** Granularity of the limit. If set 4KB granularity is used, if
2061	* clear byte. */
2062	unsigned u1Granularity : 1;
2063	/** Base address - highest 8 bits. */
2064	unsigned u8BaseHigh2 : 8;
2065	} X86DESCGENERIC;
2066	#pragma pack()
2067	/** Pointer to a generic descriptor entry. */
2068	typedef X86DESCGENERIC *PX86DESCGENERIC;
2069	/** Pointer to a const generic descriptor entry. */
2070	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2071
2072	/**
2073	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2074	*/
2075	typedef struct X86DESCGATE
2076	{
2077	/** Target code segment offset - Low word.
2078	* Ignored if task-gate. */
2079	unsigned u16OffsetLow : 16;
2080	/** Target code segment selector for call-, interrupt- and trap-gates,
2081	* TSS selector if task-gate. */
2082	unsigned u16Sel : 16;
2083	/** Number of parameters for a call-gate.
2084	* Ignored if interrupt-, trap- or task-gate. */
2085	unsigned u4ParmCount : 4;
2086	/** Reserved / ignored. */
2087	unsigned u4Reserved : 4;
2088	/** Segment Type. */
2089	unsigned u4Type : 4;
2090	/** Descriptor Type (0 = system). */
2091	unsigned u1DescType : 1;
2092	/** Descriptor Privelege level. */
2093	unsigned u2Dpl : 2;
2094	/** Flags selector present(=1) or not. */
2095	unsigned u1Present : 1;
2096	/** Target code segment offset - High word.
2097	* Ignored if task-gate. */
2098	unsigned u16OffsetHigh : 16;
2099	} X86DESCGATE;
2100	AssertCompileSize(X86DESCGATE, 8);
2101	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2102	typedef X86DESCGATE *PX86DESCGATE;
2103	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2104	typedef const X86DESCGATE *PCX86DESCGATE;
2105
2106	/**
2107	* Descriptor table entry.
2108	*/
2109	#pragma pack(1)
2110	typedef union X86DESC
2111	{
2112	/** Generic descriptor view. */
2113	X86DESCGENERIC Gen;
2114	/** Gate descriptor view. */
2115	X86DESCGATE Gate;
2116
2117	/** 8 bit unsigned interger view. */
2118	uint8_t au8[8];
2119	/** 16 bit unsigned interger view. */
2120	uint16_t au16[4];
2121	/** 32 bit unsigned interger view. */
2122	uint32_t au32[2];
2123	} X86DESC;
2124	AssertCompileSize(X86DESC, 8);
2125	#pragma pack()
2126	/** Pointer to descriptor table entry. */
2127	typedef X86DESC *PX86DESC;
2128	/** Pointer to const descriptor table entry. */
2129	typedef const X86DESC *PCX86DESC;
2130
2131	/** @def X86DESC_BASE
2132	* Return the base address of a descriptor.
2133	*/
2134	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2135	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2136	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2137	\| ( (desc).Gen.u16BaseLow ) )
2138
2139	/** @def X86DESC_LIMIT
2140	* Return the limit of a descriptor.
2141	*/
2142	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2143	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2144	\| ( (desc).Gen.u16LimitLow ) )
2145
2146	/**
2147	* 64 bits generic descriptor table entry
2148	* Note: most of these bits have no meaning in long mode.
2149	*/
2150	#pragma pack(1)
2151	typedef struct X86DESC64GENERIC
2152	{
2153	/** Limit - Low word - IGNORED. */
2154	unsigned u16LimitLow : 16;
2155	/** Base address - lowe word. - IGNORED
2156	* Don't try set this to 24 because MSC is doing stupid things then. */
2157	unsigned u16BaseLow : 16;
2158	/** Base address - first 8 bits of high word. - IGNORED */
2159	unsigned u8BaseHigh1 : 8;
2160	/** Segment Type. */
2161	unsigned u4Type : 4;
2162	/** Descriptor Type. System(=0) or code/data selector */
2163	unsigned u1DescType : 1;
2164	/** Descriptor Privelege level. */
2165	unsigned u2Dpl : 2;
2166	/** Flags selector present(=1) or not. */
2167	unsigned u1Present : 1;
2168	/** Segment limit 16-19. - IGNORED */
2169	unsigned u4LimitHigh : 4;
2170	/** Available for system software. - IGNORED */
2171	unsigned u1Available : 1;
2172	/** Long mode flag. */
2173	unsigned u1Long : 1;
2174	/** This flags meaning depends on the segment type. Try make sense out
2175	* of the intel manual yourself. */
2176	unsigned u1DefBig : 1;
2177	/** Granularity of the limit. If set 4KB granularity is used, if
2178	* clear byte. - IGNORED */
2179	unsigned u1Granularity : 1;
2180	/** Base address - highest 8 bits. - IGNORED */
2181	unsigned u8BaseHigh2 : 8;
2182	/** Base address - bits 63-32. */
2183	unsigned u32BaseHigh3 : 32;
2184	unsigned u8Reserved : 8;
2185	unsigned u5Zeros : 5;
2186	unsigned u19Reserved : 19;
2187	} X86DESC64GENERIC;
2188	#pragma pack()
2189	/** Pointer to a generic descriptor entry. */
2190	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2191	/** Pointer to a const generic descriptor entry. */
2192	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2193
2194	/**
2195	* System descriptor table entry (64 bits)
2196	*
2197	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2198	*/
2199	#pragma pack(1)
2200	typedef struct X86DESC64SYSTEM
2201	{
2202	/** Limit - Low word. */
2203	unsigned u16LimitLow : 16;
2204	/** Base address - lowe word.
2205	* Don't try set this to 24 because MSC is doing stupid things then. */
2206	unsigned u16BaseLow : 16;
2207	/** Base address - first 8 bits of high word. */
2208	unsigned u8BaseHigh1 : 8;
2209	/** Segment Type. */
2210	unsigned u4Type : 4;
2211	/** Descriptor Type. System(=0) or code/data selector */
2212	unsigned u1DescType : 1;
2213	/** Descriptor Privelege level. */
2214	unsigned u2Dpl : 2;
2215	/** Flags selector present(=1) or not. */
2216	unsigned u1Present : 1;
2217	/** Segment limit 16-19. */
2218	unsigned u4LimitHigh : 4;
2219	/** Available for system software. */
2220	unsigned u1Available : 1;
2221	/** Reserved - 0. */
2222	unsigned u1Reserved : 1;
2223	/** This flags meaning depends on the segment type. Try make sense out
2224	* of the intel manual yourself. */
2225	unsigned u1DefBig : 1;
2226	/** Granularity of the limit. If set 4KB granularity is used, if
2227	* clear byte. */
2228	unsigned u1Granularity : 1;
2229	/** Base address - bits 31-24. */
2230	unsigned u8BaseHigh2 : 8;
2231	/** Base address - bits 63-32. */
2232	unsigned u32BaseHigh3 : 32;
2233	unsigned u8Reserved : 8;
2234	unsigned u5Zeros : 5;
2235	unsigned u19Reserved : 19;
2236	} X86DESC64SYSTEM;
2237	#pragma pack()
2238	/** Pointer to a system descriptor entry. */
2239	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2240	/** Pointer to a const system descriptor entry. */
2241	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2242
2243	/**
2244	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2245	*/
2246	typedef struct X86DESC64GATE
2247	{
2248	/** Target code segment offset - Low word. */
2249	unsigned u16OffsetLow : 16;
2250	/** Target code segment selector. */
2251	unsigned u16Sel : 16;
2252	/** Interrupt stack table for interrupt- and trap-gates.
2253	* Ignored by call-gates. */
2254	unsigned u3IST : 3;
2255	/** Reserved / ignored. */
2256	unsigned u5Reserved : 5;
2257	/** Segment Type. */
2258	unsigned u4Type : 4;
2259	/** Descriptor Type (0 = system). */
2260	unsigned u1DescType : 1;
2261	/** Descriptor Privelege level. */
2262	unsigned u2Dpl : 2;
2263	/** Flags selector present(=1) or not. */
2264	unsigned u1Present : 1;
2265	/** Target code segment offset - High word.
2266	* Ignored if task-gate. */
2267	unsigned u16OffsetHigh : 16;
2268	/** Target code segment offset - Top dword.
2269	* Ignored if task-gate. */
2270	unsigned u32OffsetTop : 32;
2271	/** Reserved / ignored / must be zero.
2272	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2273	unsigned u32Reserved : 32;
2274	} X86DESC64GATE;
2275	AssertCompileSize(X86DESC64GATE, 16);
2276	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2277	typedef X86DESC64GATE *PX86DESC64GATE;
2278	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2279	typedef const X86DESC64GATE *PCX86DESC64GATE;
2280
2281
2282	/**
2283	* Descriptor table entry.
2284	*/
2285	#pragma pack(1)
2286	typedef union X86DESC64
2287	{
2288	/** Generic descriptor view. */
2289	X86DESC64GENERIC Gen;
2290	/** System descriptor view. */
2291	X86DESC64SYSTEM System;
2292	/** Gate descriptor view. */
2293	X86DESC64GATE Gate;
2294
2295	/** 8 bit unsigned interger view. */
2296	uint8_t au8[16];
2297	/** 16 bit unsigned interger view. */
2298	uint16_t au16[8];
2299	/** 32 bit unsigned interger view. */
2300	uint32_t au32[4];
2301	/** 64 bit unsigned interger view. */
2302	uint64_t au64[2];
2303	} X86DESC64;
2304	AssertCompileSize(X86DESC64, 16);
2305	#pragma pack()
2306	/** Pointer to descriptor table entry. */
2307	typedef X86DESC64 *PX86DESC64;
2308	/** Pointer to const descriptor table entry. */
2309	typedef const X86DESC64 *PCX86DESC64;
2310
2311	/** @def X86DESC64_BASE
2312	* Return the base of a 64-bit descriptor.
2313	*/
2314	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2315	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2316	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2317	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2318	\| ( (desc).Gen.u16BaseLow ) )
2319
2320
2321
2322	/** @name Host system descriptor table entry - Use with care!
2323	* @{ */
2324	/** Host system descriptor table entry. */
2325	#if HC_ARCH_BITS == 64
2326	typedef X86DESC64 X86DESCHC;
2327	#else
2328	typedef X86DESC X86DESCHC;
2329	#endif
2330	/** Pointer to a host system descriptor table entry. */
2331	#if HC_ARCH_BITS == 64
2332	typedef PX86DESC64 PX86DESCHC;
2333	#else
2334	typedef PX86DESC PX86DESCHC;
2335	#endif
2336	/** Pointer to a const host system descriptor table entry. */
2337	#if HC_ARCH_BITS == 64
2338	typedef PCX86DESC64 PCX86DESCHC;
2339	#else
2340	typedef PCX86DESC PCX86DESCHC;
2341	#endif
2342	/** @} */
2343
2344
2345	/** @name Selector Descriptor Types.
2346	* @{
2347	*/
2348
2349	/** @name Non-System Selector Types.
2350	* @{ */
2351	/** Code(=set)/Data(=clear) bit. */
2352	#define X86_SEL_TYPE_CODE 8
2353	/** Memory(=set)/System(=clear) bit. */
2354	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2355	/** Accessed bit. */
2356	#define X86_SEL_TYPE_ACCESSED 1
2357	/** Expand down bit (for data selectors only). */
2358	#define X86_SEL_TYPE_DOWN 4
2359	/** Conforming bit (for code selectors only). */
2360	#define X86_SEL_TYPE_CONF 4
2361	/** Write bit (for data selectors only). */
2362	#define X86_SEL_TYPE_WRITE 2
2363	/** Read bit (for code selectors only). */
2364	#define X86_SEL_TYPE_READ 2
2365
2366	/** Read only selector type. */
2367	#define X86_SEL_TYPE_RO 0
2368	/** Accessed read only selector type. */
2369	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2370	/** Read write selector type. */
2371	#define X86_SEL_TYPE_RW 2
2372	/** Accessed read write selector type. */
2373	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2374	/** Expand down read only selector type. */
2375	#define X86_SEL_TYPE_RO_DOWN 4
2376	/** Accessed expand down read only selector type. */
2377	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2378	/** Expand down read write selector type. */
2379	#define X86_SEL_TYPE_RW_DOWN 6
2380	/** Accessed expand down read write selector type. */
2381	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2382	/** Execute only selector type. */
2383	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2384	/** Accessed execute only selector type. */
2385	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2386	/** Execute and read selector type. */
2387	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2388	/** Accessed execute and read selector type. */
2389	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2390	/** Conforming execute only selector type. */
2391	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2392	/** Accessed Conforming execute only selector type. */
2393	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2394	/** Conforming execute and write selector type. */
2395	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2396	/** Accessed Conforming execute and write selector type. */
2397	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2398	/** @} */
2399
2400
2401	/** @name System Selector Types.
2402	* @{ */
2403	/** Undefined system selector type. */
2404	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2405	/** 286 TSS selector. */
2406	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2407	/** LDT selector. */
2408	#define X86_SEL_TYPE_SYS_LDT 2
2409	/** 286 TSS selector - Busy. */
2410	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2411	/** 286 Callgate selector. */
2412	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2413	/** Taskgate selector. */
2414	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2415	/** 286 Interrupt gate selector. */
2416	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2417	/** 286 Trapgate selector. */
2418	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2419	/** Undefined system selector. */
2420	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2421	/** 386 TSS selector. */
2422	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2423	/** Undefined system selector. */
2424	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2425	/** 386 TSS selector - Busy. */
2426	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2427	/** 386 Callgate selector. */
2428	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2429	/** Undefined system selector. */
2430	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2431	/** 386 Interruptgate selector. */
2432	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2433	/** 386 Trapgate selector. */
2434	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2435	/** @} */
2436
2437	/** @name AMD64 System Selector Types.
2438	* @{ */
2439	#define AMD64_SEL_TYPE_SYS_LDT 2
2440	/** 286 TSS selector - Busy. */
2441	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2442	/** 386 TSS selector - Busy. */
2443	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2444	/** 386 Callgate selector. */
2445	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2446	/** 386 Interruptgate selector. */
2447	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2448	/** 386 Trapgate selector. */
2449	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2450	/** @} */
2451
2452	/** @} */
2453
2454
2455	/** @name Descriptor Table Entry Flag Masks.
2456	* These are for the 2nd 32-bit word of a descriptor.
2457	* @{ */
2458	/** Bits 8-11 - TYPE - Descriptor type mask. */
2459	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2460	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2461	#define X86_DESC_S RT_BIT(12)
2462	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2463	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2464	/** Bit 15 - P - Present. */
2465	#define X86_DESC_P RT_BIT(15)
2466	/** Bit 20 - AVL - Available for system software. */
2467	#define X86_DESC_AVL RT_BIT(20)
2468	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2469	#define X86_DESC_DB RT_BIT(22)
2470	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2471	* used, if clear byte. */
2472	#define X86_DESC_G RT_BIT(23)
2473	/** @} */
2474
2475	/** @} */
2476
2477	/** @name Task segment.
2478	* @{
2479	*/
2480	#pragma pack(1)
2481	typedef struct X86TSS32
2482	{
2483	/** Back link to previous task. (static) */
2484	RTSEL selPrev;
2485	uint16_t padding1;
2486	/** Ring-0 stack pointer. (static) */
2487	uint32_t esp0;
2488	/** Ring-0 stack segment. (static) */
2489	RTSEL ss0;
2490	uint16_t padding_ss0;
2491	/** Ring-1 stack pointer. (static) */
2492	uint32_t esp1;
2493	/** Ring-1 stack segment. (static) */
2494	RTSEL ss1;
2495	uint16_t padding_ss1;
2496	/** Ring-2 stack pointer. (static) */
2497	uint32_t esp2;
2498	/** Ring-2 stack segment. (static) */
2499	RTSEL ss2;
2500	uint16_t padding_ss2;
2501	/** Page directory for the task. (static) */
2502	uint32_t cr3;
2503	/** EIP before task switch. */
2504	uint32_t eip;
2505	/** EFLAGS before task switch. */
2506	uint32_t eflags;
2507	/** EAX before task switch. */
2508	uint32_t eax;
2509	/** ECX before task switch. */
2510	uint32_t ecx;
2511	/** EDX before task switch. */
2512	uint32_t edx;
2513	/** EBX before task switch. */
2514	uint32_t ebx;
2515	/** ESP before task switch. */
2516	uint32_t esp;
2517	/** EBP before task switch. */
2518	uint32_t ebp;
2519	/** ESI before task switch. */
2520	uint32_t esi;
2521	/** EDI before task switch. */
2522	uint32_t edi;
2523	/** ES before task switch. */
2524	RTSEL es;
2525	uint16_t padding_es;
2526	/** CS before task switch. */
2527	RTSEL cs;
2528	uint16_t padding_cs;
2529	/** SS before task switch. */
2530	RTSEL ss;
2531	uint16_t padding_ss;
2532	/** DS before task switch. */
2533	RTSEL ds;
2534	uint16_t padding_ds;
2535	/** FS before task switch. */
2536	RTSEL fs;
2537	uint16_t padding_fs;
2538	/** GS before task switch. */
2539	RTSEL gs;
2540	uint16_t padding_gs;
2541	/** LDTR before task switch. */
2542	RTSEL selLdt;
2543	uint16_t padding_ldt;
2544	/** Debug trap flag */
2545	uint16_t fDebugTrap;
2546	/** Offset relative to the TSS of the start of the I/O Bitmap
2547	* and the end of the interrupt redirection bitmap. */
2548	uint16_t offIoBitmap;
2549	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2550	uint8_t IntRedirBitmap[32];
2551	} X86TSS32;
2552	#pragma pack()
2553	/** Pointer to task segment. */
2554	typedef X86TSS32 *PX86TSS32;
2555	/** Pointer to const task segment. */
2556	typedef const X86TSS32 *PCX86TSS32;
2557	/** @} */
2558
2559
2560	/** @name 64 bits Task segment.
2561	* @{
2562	*/
2563	#pragma pack(1)
2564	typedef struct X86TSS64
2565	{
2566	/** Reserved. */
2567	uint32_t u32Reserved;
2568	/** Ring-0 stack pointer. (static) */
2569	uint64_t rsp0;
2570	/** Ring-1 stack pointer. (static) */
2571	uint64_t rsp1;
2572	/** Ring-2 stack pointer. (static) */
2573	uint64_t rsp2;
2574	/** Reserved. */
2575	uint32_t u32Reserved2[2];
2576	/* IST */
2577	uint64_t ist1;
2578	uint64_t ist2;
2579	uint64_t ist3;
2580	uint64_t ist4;
2581	uint64_t ist5;
2582	uint64_t ist6;
2583	uint64_t ist7;
2584	/* Reserved. */
2585	uint16_t u16Reserved[5];
2586	/** Offset relative to the TSS of the start of the I/O Bitmap
2587	* and the end of the interrupt redirection bitmap. */
2588	uint16_t offIoBitmap;
2589	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2590	uint8_t IntRedirBitmap[32];
2591	} X86TSS64;
2592	#pragma pack()
2593	/** Pointer to task segment. */
2594	typedef X86TSS64 *PX86TSS64;
2595	/** Pointer to const task segment. */
2596	typedef const X86TSS64 *PCX86TSS64;
2597	AssertCompileSize(X86TSS64, 136);
2598
2599	/** @} */
2600
2601
2602	/** @name Selectors.
2603	* @{
2604	*/
2605
2606	/**
2607	* The shift used to convert a selector from and to index an index (C).
2608	*/
2609	#define X86_SEL_SHIFT 3
2610
2611	/**
2612	* The mask used to mask off the table indicator and CPL of an selector.
2613	*/
2614	#define X86_SEL_MASK 0xfff8
2615
2616	/**
2617	* The bit indicating that a selector is in the LDT and not in the GDT.
2618	*/
2619	#define X86_SEL_LDT 0x0004
2620	/**
2621	* The bit mask for getting the RPL of a selector.
2622	*/
2623	#define X86_SEL_RPL 0x0003
2624
2625	/** @} */
2626
2627
2628	/**
2629	* x86 Exceptions/Faults/Traps.
2630	*/
2631	typedef enum X86XCPT
2632	{
2633	/** \#DE - Divide error. */
2634	X86_XCPT_DE = 0x00,
2635	/** \#DB - Debug event (single step, DRx, ..) */
2636	X86_XCPT_DB = 0x01,
2637	/** NMI - Non-Maskable Interrupt */
2638	X86_XCPT_NMI = 0x02,
2639	/** \#BP - Breakpoint (INT3). */
2640	X86_XCPT_BP = 0x03,
2641	/** \#OF - Overflow (INTO). */
2642	X86_XCPT_OF = 0x04,
2643	/** \#BR - Bound range exceeded (BOUND). */
2644	X86_XCPT_BR = 0x05,
2645	/** \#UD - Undefined opcode. */
2646	X86_XCPT_UD = 0x06,
2647	/** \#NM - Device not available (math coprocessor device). */
2648	X86_XCPT_NM = 0x07,
2649	/** \#DF - Double fault. */
2650	X86_XCPT_DF = 0x08,
2651	/** ??? - Coprocessor segment overrun (obsolete). */
2652	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2653	/** \#TS - Taskswitch (TSS). */
2654	X86_XCPT_TS = 0x0a,
2655	/** \#NP - Segment no present. */
2656	X86_XCPT_NP = 0x0b,
2657	/** \#SS - Stack segment fault. */
2658	X86_XCPT_SS = 0x0c,
2659	/** \#GP - General protection fault. */
2660	X86_XCPT_GP = 0x0d,
2661	/** \#PF - Page fault. */
2662	X86_XCPT_PF = 0x0e,
2663	/* 0x0f is reserved. */
2664	/** \#MF - Math fault (FPU). */
2665	X86_XCPT_MF = 0x10,
2666	/** \#AC - Alignment check. */
2667	X86_XCPT_AC = 0x11,
2668	/** \#MC - Machine check. */
2669	X86_XCPT_MC = 0x12,
2670	/** \#XF - SIMD Floating-Pointer Exception. */
2671	X86_XCPT_XF = 0x13
2672	} X86XCPT;
2673	/** Pointer to a x86 exception code. */
2674	typedef X86XCPT *PX86XCPT;
2675	/** Pointer to a const x86 exception code. */
2676	typedef const X86XCPT *PCX86XCPT;
2677
2678
2679	/** @name Trap Error Codes
2680	* @{
2681	*/
2682	/** External indicator. */
2683	#define X86_TRAP_ERR_EXTERNAL 1
2684	/** IDT indicator. */
2685	#define X86_TRAP_ERR_IDT 2
2686	/** Descriptor table indicator - If set LDT, if clear GDT. */
2687	#define X86_TRAP_ERR_TI 4
2688	/** Mask for getting the selector. */
2689	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2690	/** Shift for getting the selector table index (C type index). */
2691	#define X86_TRAP_ERR_SEL_SHIFT 3
2692	/** @} */
2693
2694
2695	/** @name \#PF Trap Error Codes
2696	* @{
2697	*/
2698	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2699	#define X86_TRAP_PF_P RT_BIT(0)
2700	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2701	#define X86_TRAP_PF_RW RT_BIT(1)
2702	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2703	#define X86_TRAP_PF_US RT_BIT(2)
2704	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2705	#define X86_TRAP_PF_RSVD RT_BIT(3)
2706	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2707	#define X86_TRAP_PF_ID RT_BIT(4)
2708	/** @} */
2709
2710	#pragma pack(1)
2711	/**
2712	* 32-bit IDTR/GDTR.
2713	*/
2714	typedef struct X86XDTR32
2715	{
2716	/** Size of the descriptor table. */
2717	uint16_t cb;
2718	/** Address of the descriptor table. */
2719	uint32_t uAddr;
2720	} X86XDTR32, *PX86XDTR32;
2721	#pragma pack()
2722
2723	#pragma pack(1)
2724	/**
2725	* 64-bit IDTR/GDTR.
2726	*/
2727	typedef struct X86XDTR64
2728	{
2729	/** Size of the descriptor table. */
2730	uint16_t cb;
2731	/** Address of the descriptor table. */
2732	uint64_t uAddr;
2733	} X86XDTR64, *PX86XDTR64;
2734	#pragma pack()
2735
2736	/** @} */
2737
2738	#endif
2739

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