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source: vbox/trunk/include/VBox/x86.h@ 21217

Last change on this file since 21217 was 21217, checked in by vboxsync, 15 years ago
include/VBox/*.h: Mark which components the header files relate to.
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File size: 92.6 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 21 - x2APIC support. */
353	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
354	/** ECX Bit 23 - POPCOUNT instruction. */
355	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
356
357
358	/** Bit 0 - FPU - x87 FPU on Chip. */
359	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
360	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
361	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
362	/** Bit 2 - DE - Debugging extensions. */
363	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
364	/** Bit 3 - PSE - Page Size Extension. */
365	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
366	/** Bit 4 - TSC - Time Stamp Counter. */
367	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
368	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
369	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
370	/** Bit 6 - PAE - Physical Address Extension. */
371	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
372	/** Bit 7 - MCE - Machine Check Exception. */
373	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
374	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
375	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
376	/** Bit 9 - APIC - APIC On-Chip. */
377	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
378	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
379	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
380	/** Bit 12 - MTRR - Memory Type Range Registers. */
381	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
382	/** Bit 13 - PGE - PTE Global Bit. */
383	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
384	/** Bit 14 - MCA - Machine Check Architecture. */
385	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
386	/** Bit 15 - CMOV - Conditional Move Instructions. */
387	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
388	/** Bit 16 - PAT - Page Attribute Table. */
389	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
390	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
391	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
392	/** Bit 18 - PSN - Processor Serial Number. */
393	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
394	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
395	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
396	/** Bit 21 - DS - Debug Store. */
397	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
398	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
399	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
400	/** Bit 23 - MMX - Intel MMX Technology. */
401	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
402	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
403	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
404	/** Bit 25 - SSE - SSE Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
406	/** Bit 26 - SSE2 - SSE2 Support. */
407	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
408	/** Bit 27 - SS - Self Snoop. */
409	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
410	/** Bit 28 - HTT - Hyper-Threading Technology. */
411	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
412	/** Bit 29 - TM - Therm. Monitor. */
413	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
414	/** Bit 31 - PBE - Pending Break Enabled. */
415	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
416	/** @} */
417
418
419	/** @name CPUID AMD Feature information.
420	* CPUID query with EAX=0x80000001.
421	* @{
422	*/
423	/** Bit 0 - FPU - x87 FPU on Chip. */
424	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
425	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
426	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
427	/** Bit 2 - DE - Debugging extensions. */
428	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
429	/** Bit 3 - PSE - Page Size Extension. */
430	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
431	/** Bit 4 - TSC - Time Stamp Counter. */
432	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
433	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
434	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
435	/** Bit 6 - PAE - Physical Address Extension. */
436	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
437	/** Bit 7 - MCE - Machine Check Exception. */
438	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
439	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
440	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
441	/** Bit 9 - APIC - APIC On-Chip. */
442	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
443	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
444	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
445	/** Bit 12 - MTRR - Memory Type Range Registers. */
446	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
447	/** Bit 13 - PGE - PTE Global Bit. */
448	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
449	/** Bit 14 - MCA - Machine Check Architecture. */
450	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
451	/** Bit 15 - CMOV - Conditional Move Instructions. */
452	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
453	/** Bit 16 - PAT - Page Attribute Table. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
455	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
456	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
457	/** Bit 20 - NX - AMD No-Execute Page Protection. */
458	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
459	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
460	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
461	/** Bit 23 - MMX - Intel MMX Technology. */
462	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
463	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
465	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
466	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
467	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
468	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
469	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
470	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
471	/** Bit 29 - LM - AMD Long Mode. */
472	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
473	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
475	/** Bit 31 - 3DNOW - AMD 3DNow. */
476	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
477
478	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
480	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
481	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
482	/** Bit 2 - SVM - AMD VM extensions. */
483	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
484	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
485	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
486	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
487	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
488	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
490	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
491	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
492	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
493	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
494	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
495	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
496	/** Bit 9 - OSVW - AMD OS visible workaround. */
497	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
498	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
500	/** Bit 13 - WDT - AMD Watchdog timer support. */
501	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
502
503	/** @} */
504
505
506	/** @name CPUID AMD Feature information.
507	* CPUID query with EAX=0x80000007.
508	* @{
509	*/
510	/** Bit 0 - TS - Temperature Sensor. */
511	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
512	/** Bit 1 - FID - Frequency ID Control. */
513	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
514	/** Bit 2 - VID - Voltage ID Control. */
515	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
516	/** Bit 3 - TTP - THERMTRIP. */
517	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
518	/** Bit 4 - TM - Hardware Thermal Control. */
519	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
520	/** Bit 5 - STC - Software Thermal Control. */
521	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
522	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
523	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
524	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
525	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
526	/** Bit 8 - TSCINVAR - TSC Invariant. */
527	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
528	/** @} */
529
530
531	/** @name CR0
532	* @{ */
533	/** Bit 0 - PE - Protection Enabled */
534	#define X86_CR0_PE RT_BIT(0)
535	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
536	/** Bit 1 - MP - Monitor Coprocessor */
537	#define X86_CR0_MP RT_BIT(1)
538	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
539	/** Bit 2 - EM - Emulation. */
540	#define X86_CR0_EM RT_BIT(2)
541	#define X86_CR0_EMULATE_FPU RT_BIT(2)
542	/** Bit 3 - TS - Task Switch. */
543	#define X86_CR0_TS RT_BIT(3)
544	#define X86_CR0_TASK_SWITCH RT_BIT(3)
545	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
546	#define X86_CR0_ET RT_BIT(4)
547	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
548	/** Bit 5 - NE - Numeric error. */
549	#define X86_CR0_NE RT_BIT(5)
550	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
551	/** Bit 16 - WP - Write Protect. */
552	#define X86_CR0_WP RT_BIT(16)
553	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
554	/** Bit 18 - AM - Alignment Mask. */
555	#define X86_CR0_AM RT_BIT(18)
556	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
557	/** Bit 29 - NW - Not Write-though. */
558	#define X86_CR0_NW RT_BIT(29)
559	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
560	/** Bit 30 - WP - Cache Disable. */
561	#define X86_CR0_CD RT_BIT(30)
562	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
563	/** Bit 31 - PG - Paging. */
564	#define X86_CR0_PG RT_BIT(31)
565	#define X86_CR0_PAGING RT_BIT(31)
566	/** @} */
567
568
569	/** @name CR3
570	* @{ */
571	/** Bit 3 - PWT - Page-level Writes Transparent. */
572	#define X86_CR3_PWT RT_BIT(3)
573	/** Bit 4 - PCD - Page-level Cache Disable. */
574	#define X86_CR3_PCD RT_BIT(4)
575	/** Bits 12-31 - - Page directory page number. */
576	#define X86_CR3_PAGE_MASK (0xfffff000)
577	/** Bits 5-31 - - PAE Page directory page number. */
578	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
579	/** Bits 12-51 - - AMD64 Page directory page number. */
580	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
581	/** @} */
582
583
584	/** @name CR4
585	* @{ */
586	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
587	#define X86_CR4_VME RT_BIT(0)
588	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
589	#define X86_CR4_PVI RT_BIT(1)
590	/** Bit 2 - TSD - Time Stamp Disable. */
591	#define X86_CR4_TSD RT_BIT(2)
592	/** Bit 3 - DE - Debugging Extensions. */
593	#define X86_CR4_DE RT_BIT(3)
594	/** Bit 4 - PSE - Page Size Extension. */
595	#define X86_CR4_PSE RT_BIT(4)
596	/** Bit 5 - PAE - Physical Address Extension. */
597	#define X86_CR4_PAE RT_BIT(5)
598	/** Bit 6 - MCE - Machine-Check Enable. */
599	#define X86_CR4_MCE RT_BIT(6)
600	/** Bit 7 - PGE - Page Global Enable. */
601	#define X86_CR4_PGE RT_BIT(7)
602	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
603	#define X86_CR4_PCE RT_BIT(8)
604	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
605	#define X86_CR4_OSFSXR RT_BIT(9)
606	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
607	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
608	/** Bit 13 - VMXE - VMX mode is enabled. */
609	#define X86_CR4_VMXE RT_BIT(13)
610	/** @} */
611
612
613	/** @name DR6
614	* @{ */
615	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
616	#define X86_DR6_B0 RT_BIT(0)
617	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
618	#define X86_DR6_B1 RT_BIT(1)
619	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
620	#define X86_DR6_B2 RT_BIT(2)
621	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
622	#define X86_DR6_B3 RT_BIT(3)
623	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
624	#define X86_DR6_BD RT_BIT(13)
625	/** Bit 14 - BS - Single step */
626	#define X86_DR6_BS RT_BIT(14)
627	/** Bit 15 - BT - Task switch. (TSS T bit.) */
628	#define X86_DR6_BT RT_BIT(15)
629	/** Value of DR6 after powerup/reset. */
630	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
631	/** @} */
632
633
634	/** @name DR7
635	* @{ */
636	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
637	#define X86_DR7_L0 RT_BIT(0)
638	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
639	#define X86_DR7_G0 RT_BIT(1)
640	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
641	#define X86_DR7_L1 RT_BIT(2)
642	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
643	#define X86_DR7_G1 RT_BIT(3)
644	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
645	#define X86_DR7_L2 RT_BIT(4)
646	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
647	#define X86_DR7_G2 RT_BIT(5)
648	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
649	#define X86_DR7_L3 RT_BIT(6)
650	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
651	#define X86_DR7_G3 RT_BIT(7)
652	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
653	#define X86_DR7_LE RT_BIT(8)
654	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
655	#define X86_DR7_GE RT_BIT(9)
656
657	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
658	* any DR register is accessed. */
659	#define X86_DR7_GD RT_BIT(13)
660	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
661	#define X86_DR7_RW0_MASK (3 << 16)
662	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
663	#define X86_DR7_LEN0_MASK (3 << 18)
664	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
665	#define X86_DR7_RW1_MASK (3 << 20)
666	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
667	#define X86_DR7_LEN1_MASK (3 << 22)
668	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
669	#define X86_DR7_RW2_MASK (3 << 24)
670	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
671	#define X86_DR7_LEN2_MASK (3 << 26)
672	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
673	#define X86_DR7_RW3_MASK (3 << 28)
674	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
675	#define X86_DR7_LEN3_MASK (3 << 30)
676
677	/** Bits which must be 1s. */
678	#define X86_DR7_MB1_MASK (RT_BIT(10))
679
680	/** Calcs the L bit of Nth breakpoint.
681	* @param iBp The breakpoint number [0..3].
682	*/
683	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
684
685	/** Calcs the G bit of Nth breakpoint.
686	* @param iBp The breakpoint number [0..3].
687	*/
688	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
689
690	/** @name Read/Write values.
691	* @{ */
692	/** Break on instruction fetch only. */
693	#define X86_DR7_RW_EO 0U
694	/** Break on write only. */
695	#define X86_DR7_RW_WO 1U
696	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
697	#define X86_DR7_RW_IO 2U
698	/** Break on read or write (but not instruction fetches). */
699	#define X86_DR7_RW_RW 3U
700	/** @} */
701
702	/** Shifts a X86_DR7_RW_* value to its right place.
703	* @param iBp The breakpoint number [0..3].
704	* @param fRw One of the X86_DR7_RW_* value.
705	*/
706	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
707
708	/** @name Length values.
709	* @{ */
710	#define X86_DR7_LEN_BYTE 0U
711	#define X86_DR7_LEN_WORD 1U
712	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
713	#define X86_DR7_LEN_DWORD 3U
714	/** @} */
715
716	/** Shifts a X86_DR7_LEN_* value to its right place.
717	* @param iBp The breakpoint number [0..3].
718	* @param cb One of the X86_DR7_LEN_* values.
719	*/
720	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
721
722	/** Fetch the breakpoint length bits from the DR7 value.
723	* @param uDR7 DR7 value
724	* @param iBp The breakpoint number [0..3].
725	*/
726	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
727
728	/** Mask used to check if any breakpoints are enabled. */
729	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
730
731	/** Mask used to check if any io breakpoints are set. */
732	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
733
734	/** Value of DR7 after powerup/reset. */
735	#define X86_DR7_INIT_VAL 0x400
736	/** @} */
737
738
739	/** @name Machine Specific Registers
740	* @{
741	*/
742
743	/** Time Stamp Counter. */
744	#define MSR_IA32_TSC 0x10
745
746	#define MSR_IA32_PLATFORM_ID 0x17
747
748	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
749	#define MSR_IA32_APICBASE 0x1b
750	#endif
751
752	/** CPU Feature control. */
753	#define MSR_IA32_FEATURE_CONTROL 0x3A
754	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
755	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
756
757	/** BIOS update trigger (microcode update). */
758	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
759
760	/** BIOS update signature (microcode). */
761	#define MSR_IA32_BIOS_SIGN_ID 0x8B
762
763	/** MTRR Capabilities. */
764	#define MSR_IA32_MTRR_CAP 0xFE
765
766
767	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
768	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
769	* R0 SS == CS + 8
770	* R3 CS == CS + 16
771	* R3 SS == CS + 24
772	*/
773	#define MSR_IA32_SYSENTER_CS 0x174
774	/** SYSENTER_ESP - the R0 ESP. */
775	#define MSR_IA32_SYSENTER_ESP 0x175
776	/** SYSENTER_EIP - the R0 EIP. */
777	#define MSR_IA32_SYSENTER_EIP 0x176
778	#endif
779
780	/** Machine Check Global Capabilities Register. */
781	#define MSR_IA32_MCP_CAP 0x179
782	/** Machine Check Global Status Register. */
783	#define MSR_IA32_MCP_STATUS 0x17A
784	/** Machine Check Global Control Register. */
785	#define MSR_IA32_MCP_CTRL 0x17B
786
787	/* Page Attribute Table. */
788	#define MSR_IA32_CR_PAT 0x277
789
790	/** Performance counter MSRs. (Intel only) */
791	#define MSR_IA32_PERFEVTSEL0 0x186
792	#define MSR_IA32_PERFEVTSEL1 0x187
793	#define MSR_IA32_PERF_STATUS 0x198
794	#define MSR_IA32_PERF_CTL 0x199
795
796	/** MTRR Default Range. */
797	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
798
799	#define MSR_IA32_MC0_CTL 0x400
800	#define MSR_IA32_MC0_STATUS 0x401
801
802	/** Basic VMX information. */
803	#define MSR_IA32_VMX_BASIC_INFO 0x480
804	/** Allowed settings for pin-based VM execution controls */
805	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
806	/** Allowed settings for proc-based VM execution controls */
807	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
808	/** Allowed settings for the VMX exit controls. */
809	#define MSR_IA32_VMX_EXIT_CTLS 0x483
810	/** Allowed settings for the VMX entry controls. */
811	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
812	/** Misc VMX info. */
813	#define MSR_IA32_VMX_MISC 0x485
814	/** Fixed cleared bits in CR0. */
815	#define MSR_IA32_VMX_CR0_FIXED0 0x486
816	/** Fixed set bits in CR0. */
817	#define MSR_IA32_VMX_CR0_FIXED1 0x487
818	/** Fixed cleared bits in CR4. */
819	#define MSR_IA32_VMX_CR4_FIXED0 0x488
820	/** Fixed set bits in CR4. */
821	#define MSR_IA32_VMX_CR4_FIXED1 0x489
822	/** Information for enumerating fields in the VMCS. */
823	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
824	/** Allowed settings for secondary proc-based VM execution controls */
825	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
826	/** EPT capabilities. */
827	#define MSR_IA32_VMX_EPT_CAPS 0x48C
828	/** X2APIC MSR ranges. */
829	#define MSR_IA32_APIC_START 0x800
830	#define MSR_IA32_APIC_END 0x900
831
832	/** K6 EFER - Extended Feature Enable Register. */
833	#define MSR_K6_EFER 0xc0000080
834	/** @todo document EFER */
835	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
836	#define MSR_K6_EFER_SCE RT_BIT(0)
837	/** Bit 8 - LME - Long mode enabled. (R/W) */
838	#define MSR_K6_EFER_LME RT_BIT(8)
839	/** Bit 10 - LMA - Long mode active. (R) */
840	#define MSR_K6_EFER_LMA RT_BIT(10)
841	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
842	#define MSR_K6_EFER_NXE RT_BIT(11)
843	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
844	#define MSR_K6_EFER_SVME RT_BIT(12)
845	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
846	#define MSR_K6_EFER_LMSLE RT_BIT(13)
847	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
848	#define MSR_K6_EFER_FFXSR RT_BIT(14)
849	/** K6 STAR - SYSCALL/RET targets. */
850	#define MSR_K6_STAR 0xc0000081
851	/** Shift value for getting the SYSRET CS and SS value. */
852	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
853	/** Shift value for getting the SYSCALL CS and SS value. */
854	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
855	/** Selector mask for use after shifting. */
856	#define MSR_K6_STAR_SEL_MASK 0xffff
857	/** The mask which give the SYSCALL EIP. */
858	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
859	/** K6 WHCR - Write Handling Control Register. */
860	#define MSR_K6_WHCR 0xc0000082
861	/** K6 UWCCR - UC/WC Cacheability Control Register. */
862	#define MSR_K6_UWCCR 0xc0000085
863	/** K6 PSOR - Processor State Observability Register. */
864	#define MSR_K6_PSOR 0xc0000087
865	/** K6 PFIR - Page Flush/Invalidate Register. */
866	#define MSR_K6_PFIR 0xc0000088
867
868	/** Performance counter MSRs. (AMD only) */
869	#define MSR_K7_EVNTSEL0 0xc0010000
870	#define MSR_K7_EVNTSEL1 0xc0010001
871	#define MSR_K7_EVNTSEL2 0xc0010002
872	#define MSR_K7_EVNTSEL3 0xc0010003
873	#define MSR_K7_PERFCTR0 0xc0010004
874	#define MSR_K7_PERFCTR1 0xc0010005
875	#define MSR_K7_PERFCTR2 0xc0010006
876	#define MSR_K7_PERFCTR3 0xc0010007
877
878	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
879	#define MSR_K8_LSTAR 0xc0000082
880	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
881	#define MSR_K8_CSTAR 0xc0000083
882	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
883	#define MSR_K8_SF_MASK 0xc0000084
884	/** K8 FS.base - The 64-bit base FS register. */
885	#define MSR_K8_FS_BASE 0xc0000100
886	/** K8 GS.base - The 64-bit base GS register. */
887	#define MSR_K8_GS_BASE 0xc0000101
888	/** K8 KernelGSbase - Used with SWAPGS. */
889	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
890	#define MSR_K8_TSC_AUX 0xc0000103
891	#define MSR_K8_SYSCFG 0xc0010010
892	#define MSR_K8_HWCR 0xc0010015
893	#define MSR_K8_IORRBASE0 0xc0010016
894	#define MSR_K8_IORRMASK0 0xc0010017
895	#define MSR_K8_IORRBASE1 0xc0010018
896	#define MSR_K8_IORRMASK1 0xc0010019
897	#define MSR_K8_TOP_MEM1 0xc001001a
898	#define MSR_K8_TOP_MEM2 0xc001001d
899	#define MSR_K8_VM_CR 0xc0010114
900	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
901
902	#define MSR_K8_IGNNE 0xc0010115
903	#define MSR_K8_SMM_CTL 0xc0010116
904	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
905	* host state during world switch.
906	*/
907	#define MSR_K8_VM_HSAVE_PA 0xc0010117
908
909	/** @} */
910
911
912	/** @name Page Table / Directory / Directory Pointers / L4.
913	* @{
914	*/
915
916	/** Page table/directory entry as an unsigned integer. */
917	typedef uint32_t X86PGUINT;
918	/** Pointer to a page table/directory table entry as an unsigned integer. */
919	typedef X86PGUINT *PX86PGUINT;
920	/** Pointer to an const page table/directory table entry as an unsigned integer. */
921	typedef X86PGUINT const *PCX86PGUINT;
922
923	/** Number of entries in a 32-bit PT/PD. */
924	#define X86_PG_ENTRIES 1024
925
926
927	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
928	typedef uint64_t X86PGPAEUINT;
929	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
930	typedef X86PGPAEUINT *PX86PGPAEUINT;
931	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
932	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
933
934	/** Number of entries in a PAE PT/PD. */
935	#define X86_PG_PAE_ENTRIES 512
936	/** Number of entries in a PAE PDPT. */
937	#define X86_PG_PAE_PDPE_ENTRIES 4
938
939	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
940	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
941	/** Number of entries in an AMD64 PDPT.
942	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
943	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
944
945	/** The size of a 4KB page. */
946	#define X86_PAGE_4K_SIZE _4K
947	/** The page shift of a 4KB page. */
948	#define X86_PAGE_4K_SHIFT 12
949	/** The 4KB page offset mask. */
950	#define X86_PAGE_4K_OFFSET_MASK 0xfff
951	/** The 4KB page base mask for virtual addresses. */
952	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
953	/** The 4KB page base mask for virtual addresses - 32bit version. */
954	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
955
956	/** The size of a 2MB page. */
957	#define X86_PAGE_2M_SIZE _2M
958	/** The page shift of a 2MB page. */
959	#define X86_PAGE_2M_SHIFT 21
960	/** The 2MB page offset mask. */
961	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
962	/** The 2MB page base mask for virtual addresses. */
963	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
964	/** The 2MB page base mask for virtual addresses - 32bit version. */
965	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
966
967	/** The size of a 4MB page. */
968	#define X86_PAGE_4M_SIZE _4M
969	/** The page shift of a 4MB page. */
970	#define X86_PAGE_4M_SHIFT 22
971	/** The 4MB page offset mask. */
972	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
973	/** The 4MB page base mask for virtual addresses. */
974	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
975	/** The 4MB page base mask for virtual addresses - 32bit version. */
976	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
977
978
979
980	/** @name Page Table Entry
981	* @{
982	*/
983	/** Bit 0 - P - Present bit. */
984	#define X86_PTE_BIT_P 0
985	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
986	#define X86_PTE_BIT_RW 1
987	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
988	#define X86_PTE_BIT_US 2
989	/** Bit 3 - PWT - Page level write thru bit. */
990	#define X86_PTE_BIT_PWT 3
991	/** Bit 4 - PCD - Page level cache disable bit. */
992	#define X86_PTE_BIT_PCD 4
993	/** Bit 5 - A - Access bit. */
994	#define X86_PTE_BIT_A 5
995	/** Bit 6 - D - Dirty bit. */
996	#define X86_PTE_BIT_D 6
997	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
998	#define X86_PTE_BIT_PAT 7
999	/** Bit 8 - G - Global flag. */
1000	#define X86_PTE_BIT_G 8
1001
1002	/** Bit 0 - P - Present bit mask. */
1003	#define X86_PTE_P RT_BIT(0)
1004	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1005	#define X86_PTE_RW RT_BIT(1)
1006	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1007	#define X86_PTE_US RT_BIT(2)
1008	/** Bit 3 - PWT - Page level write thru bit mask. */
1009	#define X86_PTE_PWT RT_BIT(3)
1010	/** Bit 4 - PCD - Page level cache disable bit mask. */
1011	#define X86_PTE_PCD RT_BIT(4)
1012	/** Bit 5 - A - Access bit mask. */
1013	#define X86_PTE_A RT_BIT(5)
1014	/** Bit 6 - D - Dirty bit mask. */
1015	#define X86_PTE_D RT_BIT(6)
1016	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1017	#define X86_PTE_PAT RT_BIT(7)
1018	/** Bit 8 - G - Global bit mask. */
1019	#define X86_PTE_G RT_BIT(8)
1020
1021	/** Bits 9-11 - - Available for use to system software. */
1022	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1023	/** Bits 12-31 - - Physical Page number of the next level. */
1024	#define X86_PTE_PG_MASK ( 0xfffff000 )
1025
1026	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1027	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1028	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1029	/** @todo Get rid of the above hack; makes code unreadable. */
1030	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1031	#else
1032	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1033	#endif
1034	/** Bits 63 - NX - PAE - No execution flag. */
1035	#define X86_PTE_PAE_NX RT_BIT_64(63)
1036
1037	/**
1038	* Page table entry.
1039	*/
1040	typedef struct X86PTEBITS
1041	{
1042	/** Flags whether(=1) or not the page is present. */
1043	unsigned u1Present : 1;
1044	/** Read(=0) / Write(=1) flag. */
1045	unsigned u1Write : 1;
1046	/** User(=1) / Supervisor (=0) flag. */
1047	unsigned u1User : 1;
1048	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1049	unsigned u1WriteThru : 1;
1050	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1051	unsigned u1CacheDisable : 1;
1052	/** Accessed flag.
1053	* Indicates that the page have been read or written to. */
1054	unsigned u1Accessed : 1;
1055	/** Dirty flag.
1056	* Indicates that the page have been written to. */
1057	unsigned u1Dirty : 1;
1058	/** Reserved / If PAT enabled, bit 2 of the index. */
1059	unsigned u1PAT : 1;
1060	/** Global flag. (Ignored in all but final level.) */
1061	unsigned u1Global : 1;
1062	/** Available for use to system software. */
1063	unsigned u3Available : 3;
1064	/** Physical Page number of the next level. */
1065	unsigned u20PageNo : 20;
1066	} X86PTEBITS;
1067	/** Pointer to a page table entry. */
1068	typedef X86PTEBITS *PX86PTEBITS;
1069	/** Pointer to a const page table entry. */
1070	typedef const X86PTEBITS *PCX86PTEBITS;
1071
1072	/**
1073	* Page table entry.
1074	*/
1075	typedef union X86PTE
1076	{
1077	/** Unsigned integer view */
1078	X86PGUINT u;
1079	/** Bit field view. */
1080	X86PTEBITS n;
1081	/** 32-bit view. */
1082	uint32_t au32[1];
1083	/** 16-bit view. */
1084	uint16_t au16[2];
1085	/** 8-bit view. */
1086	uint8_t au8[4];
1087	} X86PTE;
1088	/** Pointer to a page table entry. */
1089	typedef X86PTE *PX86PTE;
1090	/** Pointer to a const page table entry. */
1091	typedef const X86PTE *PCX86PTE;
1092
1093
1094	/**
1095	* PAE page table entry.
1096	*/
1097	typedef struct X86PTEPAEBITS
1098	{
1099	/** Flags whether(=1) or not the page is present. */
1100	uint32_t u1Present : 1;
1101	/** Read(=0) / Write(=1) flag. */
1102	uint32_t u1Write : 1;
1103	/** User(=1) / Supervisor(=0) flag. */
1104	uint32_t u1User : 1;
1105	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1106	uint32_t u1WriteThru : 1;
1107	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1108	uint32_t u1CacheDisable : 1;
1109	/** Accessed flag.
1110	* Indicates that the page have been read or written to. */
1111	uint32_t u1Accessed : 1;
1112	/** Dirty flag.
1113	* Indicates that the page have been written to. */
1114	uint32_t u1Dirty : 1;
1115	/** Reserved / If PAT enabled, bit 2 of the index. */
1116	uint32_t u1PAT : 1;
1117	/** Global flag. (Ignored in all but final level.) */
1118	uint32_t u1Global : 1;
1119	/** Available for use to system software. */
1120	uint32_t u3Available : 3;
1121	/** Physical Page number of the next level - Low Part. Don't use this. */
1122	uint32_t u20PageNoLow : 20;
1123	/** Physical Page number of the next level - High Part. Don't use this. */
1124	uint32_t u20PageNoHigh : 20;
1125	/** MBZ bits */
1126	uint32_t u11Reserved : 11;
1127	/** No Execute flag. */
1128	uint32_t u1NoExecute : 1;
1129	} X86PTEPAEBITS;
1130	/** Pointer to a page table entry. */
1131	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1132	/** Pointer to a page table entry. */
1133	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1134
1135	/**
1136	* PAE Page table entry.
1137	*/
1138	typedef union X86PTEPAE
1139	{
1140	/** Unsigned integer view */
1141	X86PGPAEUINT u;
1142	/** Bit field view. */
1143	X86PTEPAEBITS n;
1144	/** 32-bit view. */
1145	uint32_t au32[2];
1146	/** 16-bit view. */
1147	uint16_t au16[4];
1148	/** 8-bit view. */
1149	uint8_t au8[8];
1150	} X86PTEPAE;
1151	/** Pointer to a PAE page table entry. */
1152	typedef X86PTEPAE *PX86PTEPAE;
1153	/** Pointer to a const PAE page table entry. */
1154	typedef const X86PTEPAE *PCX86PTEPAE;
1155	/** @} */
1156
1157	/**
1158	* Page table.
1159	*/
1160	typedef struct X86PT
1161	{
1162	/** PTE Array. */
1163	X86PTE a[X86_PG_ENTRIES];
1164	} X86PT;
1165	/** Pointer to a page table. */
1166	typedef X86PT *PX86PT;
1167	/** Pointer to a const page table. */
1168	typedef const X86PT *PCX86PT;
1169
1170	/** The page shift to get the PT index. */
1171	#define X86_PT_SHIFT 12
1172	/** The PT index mask (apply to a shifted page address). */
1173	#define X86_PT_MASK 0x3ff
1174
1175
1176	/**
1177	* Page directory.
1178	*/
1179	typedef struct X86PTPAE
1180	{
1181	/** PTE Array. */
1182	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1183	} X86PTPAE;
1184	/** Pointer to a page table. */
1185	typedef X86PTPAE *PX86PTPAE;
1186	/** Pointer to a const page table. */
1187	typedef const X86PTPAE *PCX86PTPAE;
1188
1189	/** The page shift to get the PA PTE index. */
1190	#define X86_PT_PAE_SHIFT 12
1191	/** The PAE PT index mask (apply to a shifted page address). */
1192	#define X86_PT_PAE_MASK 0x1ff
1193
1194
1195	/** @name 4KB Page Directory Entry
1196	* @{
1197	*/
1198	/** Bit 0 - P - Present bit. */
1199	#define X86_PDE_P RT_BIT(0)
1200	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1201	#define X86_PDE_RW RT_BIT(1)
1202	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1203	#define X86_PDE_US RT_BIT(2)
1204	/** Bit 3 - PWT - Page level write thru bit. */
1205	#define X86_PDE_PWT RT_BIT(3)
1206	/** Bit 4 - PCD - Page level cache disable bit. */
1207	#define X86_PDE_PCD RT_BIT(4)
1208	/** Bit 5 - A - Access bit. */
1209	#define X86_PDE_A RT_BIT(5)
1210	/** Bit 7 - PS - Page size attribute.
1211	* Clear mean 4KB pages, set means large pages (2/4MB). */
1212	#define X86_PDE_PS RT_BIT(7)
1213	/** Bits 9-11 - - Available for use to system software. */
1214	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1215	/** Bits 12-31 - - Physical Page number of the next level. */
1216	#define X86_PDE_PG_MASK ( 0xfffff000 )
1217
1218	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1219	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1220	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1221	* we partly or that part into shadow page table entries. Will be corrected
1222	* soon.
1223	*/
1224	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1225	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1226	#else
1227	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1228	#endif
1229	/** Bits 63 - NX - PAE - No execution flag. */
1230	#define X86_PDE_PAE_NX RT_BIT_64(63)
1231
1232	/**
1233	* Page directory entry.
1234	*/
1235	typedef struct X86PDEBITS
1236	{
1237	/** Flags whether(=1) or not the page is present. */
1238	unsigned u1Present : 1;
1239	/** Read(=0) / Write(=1) flag. */
1240	unsigned u1Write : 1;
1241	/** User(=1) / Supervisor (=0) flag. */
1242	unsigned u1User : 1;
1243	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1244	unsigned u1WriteThru : 1;
1245	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1246	unsigned u1CacheDisable : 1;
1247	/** Accessed flag.
1248	* Indicates that the page have been read or written to. */
1249	unsigned u1Accessed : 1;
1250	/** Reserved / Ignored (dirty bit). */
1251	unsigned u1Reserved0 : 1;
1252	/** Size bit if PSE is enabled - in any event it's 0. */
1253	unsigned u1Size : 1;
1254	/** Reserved / Ignored (global bit). */
1255	unsigned u1Reserved1 : 1;
1256	/** Available for use to system software. */
1257	unsigned u3Available : 3;
1258	/** Physical Page number of the next level. */
1259	unsigned u20PageNo : 20;
1260	} X86PDEBITS;
1261	/** Pointer to a page directory entry. */
1262	typedef X86PDEBITS *PX86PDEBITS;
1263	/** Pointer to a const page directory entry. */
1264	typedef const X86PDEBITS *PCX86PDEBITS;
1265
1266
1267	/**
1268	* PAE page directory entry.
1269	*/
1270	typedef struct X86PDEPAEBITS
1271	{
1272	/** Flags whether(=1) or not the page is present. */
1273	uint32_t u1Present : 1;
1274	/** Read(=0) / Write(=1) flag. */
1275	uint32_t u1Write : 1;
1276	/** User(=1) / Supervisor (=0) flag. */
1277	uint32_t u1User : 1;
1278	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1279	uint32_t u1WriteThru : 1;
1280	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1281	uint32_t u1CacheDisable : 1;
1282	/** Accessed flag.
1283	* Indicates that the page have been read or written to. */
1284	uint32_t u1Accessed : 1;
1285	/** Reserved / Ignored (dirty bit). */
1286	uint32_t u1Reserved0 : 1;
1287	/** Size bit if PSE is enabled - in any event it's 0. */
1288	uint32_t u1Size : 1;
1289	/** Reserved / Ignored (global bit). / */
1290	uint32_t u1Reserved1 : 1;
1291	/** Available for use to system software. */
1292	uint32_t u3Available : 3;
1293	/** Physical Page number of the next level - Low Part. Don't use! */
1294	uint32_t u20PageNoLow : 20;
1295	/** Physical Page number of the next level - High Part. Don't use! */
1296	uint32_t u20PageNoHigh : 20;
1297	/** MBZ bits */
1298	uint32_t u11Reserved : 11;
1299	/** No Execute flag. */
1300	uint32_t u1NoExecute : 1;
1301	} X86PDEPAEBITS;
1302	/** Pointer to a page directory entry. */
1303	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1304	/** Pointer to a const page directory entry. */
1305	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1306
1307	/** @} */
1308
1309
1310	/** @name 2/4MB Page Directory Entry
1311	* @{
1312	*/
1313	/** Bit 0 - P - Present bit. */
1314	#define X86_PDE4M_P RT_BIT(0)
1315	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1316	#define X86_PDE4M_RW RT_BIT(1)
1317	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1318	#define X86_PDE4M_US RT_BIT(2)
1319	/** Bit 3 - PWT - Page level write thru bit. */
1320	#define X86_PDE4M_PWT RT_BIT(3)
1321	/** Bit 4 - PCD - Page level cache disable bit. */
1322	#define X86_PDE4M_PCD RT_BIT(4)
1323	/** Bit 5 - A - Access bit. */
1324	#define X86_PDE4M_A RT_BIT(5)
1325	/** Bit 6 - D - Dirty bit. */
1326	#define X86_PDE4M_D RT_BIT(6)
1327	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1328	#define X86_PDE4M_PS RT_BIT(7)
1329	/** Bit 8 - G - Global flag. */
1330	#define X86_PDE4M_G RT_BIT(8)
1331	/** Bits 9-11 - AVL - Available for use to system software. */
1332	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1333	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1334	#define X86_PDE4M_PAT RT_BIT(12)
1335	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1336	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1337	/** Bits 22-31 - - Physical Page number. */
1338	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1339	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1340	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1341	/** The number of bits to the high part of the page number. */
1342	#define X86_PDE4M_PG_HIGH_SHIFT 19
1343
1344	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1345	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1346	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1347	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1348	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1349
1350	/**
1351	* 4MB page directory entry.
1352	*/
1353	typedef struct X86PDE4MBITS
1354	{
1355	/** Flags whether(=1) or not the page is present. */
1356	unsigned u1Present : 1;
1357	/** Read(=0) / Write(=1) flag. */
1358	unsigned u1Write : 1;
1359	/** User(=1) / Supervisor (=0) flag. */
1360	unsigned u1User : 1;
1361	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1362	unsigned u1WriteThru : 1;
1363	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1364	unsigned u1CacheDisable : 1;
1365	/** Accessed flag.
1366	* Indicates that the page have been read or written to. */
1367	unsigned u1Accessed : 1;
1368	/** Dirty flag.
1369	* Indicates that the page have been written to. */
1370	unsigned u1Dirty : 1;
1371	/** Page size flag - always 1 for 4MB entries. */
1372	unsigned u1Size : 1;
1373	/** Global flag. */
1374	unsigned u1Global : 1;
1375	/** Available for use to system software. */
1376	unsigned u3Available : 3;
1377	/** Reserved / If PAT enabled, bit 2 of the index. */
1378	unsigned u1PAT : 1;
1379	/** Bits 32-39 of the page number on AMD64.
1380	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1381	unsigned u8PageNoHigh : 8;
1382	/** Reserved. */
1383	unsigned u1Reserved : 1;
1384	/** Physical Page number of the page. */
1385	unsigned u10PageNo : 10;
1386	} X86PDE4MBITS;
1387	/** Pointer to a page table entry. */
1388	typedef X86PDE4MBITS *PX86PDE4MBITS;
1389	/** Pointer to a const page table entry. */
1390	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1391
1392
1393	/**
1394	* 2MB PAE page directory entry.
1395	*/
1396	typedef struct X86PDE2MPAEBITS
1397	{
1398	/** Flags whether(=1) or not the page is present. */
1399	uint32_t u1Present : 1;
1400	/** Read(=0) / Write(=1) flag. */
1401	uint32_t u1Write : 1;
1402	/** User(=1) / Supervisor(=0) flag. */
1403	uint32_t u1User : 1;
1404	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1405	uint32_t u1WriteThru : 1;
1406	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1407	uint32_t u1CacheDisable : 1;
1408	/** Accessed flag.
1409	* Indicates that the page have been read or written to. */
1410	uint32_t u1Accessed : 1;
1411	/** Dirty flag.
1412	* Indicates that the page have been written to. */
1413	uint32_t u1Dirty : 1;
1414	/** Page size flag - always 1 for 2MB entries. */
1415	uint32_t u1Size : 1;
1416	/** Global flag. */
1417	uint32_t u1Global : 1;
1418	/** Available for use to system software. */
1419	uint32_t u3Available : 3;
1420	/** Reserved / If PAT enabled, bit 2 of the index. */
1421	uint32_t u1PAT : 1;
1422	/** Reserved. */
1423	uint32_t u9Reserved : 9;
1424	/** Physical Page number of the next level - Low part. Don't use! */
1425	uint32_t u10PageNoLow : 10;
1426	/** Physical Page number of the next level - High part. Don't use! */
1427	uint32_t u20PageNoHigh : 20;
1428	/** MBZ bits */
1429	uint32_t u11Reserved : 11;
1430	/** No Execute flag. */
1431	uint32_t u1NoExecute : 1;
1432	} X86PDE2MPAEBITS;
1433	/** Pointer to a 4MB PAE page table entry. */
1434	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1435	/** Pointer to a 4MB PAE page table entry. */
1436	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1437
1438	/** @} */
1439
1440	/**
1441	* Page directory entry.
1442	*/
1443	typedef union X86PDE
1444	{
1445	/** Unsigned integer view. */
1446	X86PGUINT u;
1447	/** Normal view. */
1448	X86PDEBITS n;
1449	/** 4MB view (big). */
1450	X86PDE4MBITS b;
1451	/** 8 bit unsigned integer view. */
1452	uint8_t au8[4];
1453	/** 16 bit unsigned integer view. */
1454	uint16_t au16[2];
1455	/** 32 bit unsigned integer view. */
1456	uint32_t au32[1];
1457	} X86PDE;
1458	/** Pointer to a page directory entry. */
1459	typedef X86PDE *PX86PDE;
1460	/** Pointer to a const page directory entry. */
1461	typedef const X86PDE *PCX86PDE;
1462
1463	/**
1464	* PAE page directory entry.
1465	*/
1466	typedef union X86PDEPAE
1467	{
1468	/** Unsigned integer view. */
1469	X86PGPAEUINT u;
1470	/** Normal view. */
1471	X86PDEPAEBITS n;
1472	/** 2MB page view (big). */
1473	X86PDE2MPAEBITS b;
1474	/** 8 bit unsigned integer view. */
1475	uint8_t au8[8];
1476	/** 16 bit unsigned integer view. */
1477	uint16_t au16[4];
1478	/** 32 bit unsigned integer view. */
1479	uint32_t au32[2];
1480	} X86PDEPAE;
1481	/** Pointer to a page directory entry. */
1482	typedef X86PDEPAE *PX86PDEPAE;
1483	/** Pointer to a const page directory entry. */
1484	typedef const X86PDEPAE *PCX86PDEPAE;
1485
1486	/**
1487	* Page directory.
1488	*/
1489	typedef struct X86PD
1490	{
1491	/** PDE Array. */
1492	X86PDE a[X86_PG_ENTRIES];
1493	} X86PD;
1494	/** Pointer to a page directory. */
1495	typedef X86PD *PX86PD;
1496	/** Pointer to a const page directory. */
1497	typedef const X86PD *PCX86PD;
1498
1499	/** The page shift to get the PD index. */
1500	#define X86_PD_SHIFT 22
1501	/** The PD index mask (apply to a shifted page address). */
1502	#define X86_PD_MASK 0x3ff
1503
1504
1505	/**
1506	* PAE page directory.
1507	*/
1508	typedef struct X86PDPAE
1509	{
1510	/** PDE Array. */
1511	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1512	} X86PDPAE;
1513	/** Pointer to a PAE page directory. */
1514	typedef X86PDPAE *PX86PDPAE;
1515	/** Pointer to a const PAE page directory. */
1516	typedef const X86PDPAE *PCX86PDPAE;
1517
1518	/** The page shift to get the PAE PD index. */
1519	#define X86_PD_PAE_SHIFT 21
1520	/** The PAE PD index mask (apply to a shifted page address). */
1521	#define X86_PD_PAE_MASK 0x1ff
1522
1523
1524	/** @name Page Directory Pointer Table Entry (PAE)
1525	* @{
1526	*/
1527	/** Bit 0 - P - Present bit. */
1528	#define X86_PDPE_P RT_BIT(0)
1529	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1530	#define X86_PDPE_RW RT_BIT(1)
1531	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1532	#define X86_PDPE_US RT_BIT(2)
1533	/** Bit 3 - PWT - Page level write thru bit. */
1534	#define X86_PDPE_PWT RT_BIT(3)
1535	/** Bit 4 - PCD - Page level cache disable bit. */
1536	#define X86_PDPE_PCD RT_BIT(4)
1537	/** Bit 5 - A - Access bit. Long Mode only. */
1538	#define X86_PDPE_A RT_BIT(5)
1539	/** Bits 9-11 - - Available for use to system software. */
1540	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1541	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1542	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1543	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1544	/** @todo Get rid of the above hack; makes code unreadable. */
1545	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1546	#else
1547	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1548	#endif
1549	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1550	#define X86_PDPE_NX RT_BIT_64(63)
1551
1552	/**
1553	* Page directory pointer table entry.
1554	*/
1555	typedef struct X86PDPEBITS
1556	{
1557	/** Flags whether(=1) or not the page is present. */
1558	uint32_t u1Present : 1;
1559	/** Chunk of reserved bits. */
1560	uint32_t u2Reserved : 2;
1561	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1562	uint32_t u1WriteThru : 1;
1563	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1564	uint32_t u1CacheDisable : 1;
1565	/** Chunk of reserved bits. */
1566	uint32_t u4Reserved : 4;
1567	/** Available for use to system software. */
1568	uint32_t u3Available : 3;
1569	/** Physical Page number of the next level - Low Part. Don't use! */
1570	uint32_t u20PageNoLow : 20;
1571	/** Physical Page number of the next level - High Part. Don't use! */
1572	uint32_t u20PageNoHigh : 20;
1573	/** MBZ bits */
1574	uint32_t u12Reserved : 12;
1575	} X86PDPEBITS;
1576	/** Pointer to a page directory pointer table entry. */
1577	typedef X86PDPEBITS *PX86PTPEBITS;
1578	/** Pointer to a const page directory pointer table entry. */
1579	typedef const X86PDPEBITS *PCX86PTPEBITS;
1580
1581	/**
1582	* Page directory pointer table entry. AMD64 version
1583	*/
1584	typedef struct X86PDPEAMD64BITS
1585	{
1586	/** Flags whether(=1) or not the page is present. */
1587	uint32_t u1Present : 1;
1588	/** Read(=0) / Write(=1) flag. */
1589	uint32_t u1Write : 1;
1590	/** User(=1) / Supervisor (=0) flag. */
1591	uint32_t u1User : 1;
1592	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1593	uint32_t u1WriteThru : 1;
1594	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1595	uint32_t u1CacheDisable : 1;
1596	/** Accessed flag.
1597	* Indicates that the page have been read or written to. */
1598	uint32_t u1Accessed : 1;
1599	/** Chunk of reserved bits. */
1600	uint32_t u3Reserved : 3;
1601	/** Available for use to system software. */
1602	uint32_t u3Available : 3;
1603	/** Physical Page number of the next level - Low Part. Don't use! */
1604	uint32_t u20PageNoLow : 20;
1605	/** Physical Page number of the next level - High Part. Don't use! */
1606	uint32_t u20PageNoHigh : 20;
1607	/** MBZ bits */
1608	uint32_t u11Reserved : 11;
1609	/** No Execute flag. */
1610	uint32_t u1NoExecute : 1;
1611	} X86PDPEAMD64BITS;
1612	/** Pointer to a page directory pointer table entry. */
1613	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1614	/** Pointer to a const page directory pointer table entry. */
1615	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1616
1617	/**
1618	* Page directory pointer table entry.
1619	*/
1620	typedef union X86PDPE
1621	{
1622	/** Unsigned integer view. */
1623	X86PGPAEUINT u;
1624	/** Normal view. */
1625	X86PDPEBITS n;
1626	/** AMD64 view. */
1627	X86PDPEAMD64BITS lm;
1628	/** 8 bit unsigned integer view. */
1629	uint8_t au8[8];
1630	/** 16 bit unsigned integer view. */
1631	uint16_t au16[4];
1632	/** 32 bit unsigned integer view. */
1633	uint32_t au32[2];
1634	} X86PDPE;
1635	/** Pointer to a page directory pointer table entry. */
1636	typedef X86PDPE *PX86PDPE;
1637	/** Pointer to a const page directory pointer table entry. */
1638	typedef const X86PDPE *PCX86PDPE;
1639
1640
1641	/**
1642	* Page directory pointer table.
1643	*/
1644	typedef struct X86PDPT
1645	{
1646	/** PDE Array. */
1647	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1648	} X86PDPT;
1649	/** Pointer to a page directory pointer table. */
1650	typedef X86PDPT *PX86PDPT;
1651	/** Pointer to a const page directory pointer table. */
1652	typedef const X86PDPT *PCX86PDPT;
1653
1654	/** The page shift to get the PDPT index. */
1655	#define X86_PDPT_SHIFT 30
1656	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1657	#define X86_PDPT_MASK_PAE 0x3
1658	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1659	#define X86_PDPT_MASK_AMD64 0x1ff
1660
1661	/** @} */
1662
1663
1664	/** @name Page Map Level-4 Entry (Long Mode PAE)
1665	* @{
1666	*/
1667	/** Bit 0 - P - Present bit. */
1668	#define X86_PML4E_P RT_BIT(0)
1669	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1670	#define X86_PML4E_RW RT_BIT(1)
1671	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1672	#define X86_PML4E_US RT_BIT(2)
1673	/** Bit 3 - PWT - Page level write thru bit. */
1674	#define X86_PML4E_PWT RT_BIT(3)
1675	/** Bit 4 - PCD - Page level cache disable bit. */
1676	#define X86_PML4E_PCD RT_BIT(4)
1677	/** Bit 5 - A - Access bit. */
1678	#define X86_PML4E_A RT_BIT(5)
1679	/** Bits 9-11 - - Available for use to system software. */
1680	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1681	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1682	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1683	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1684	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1685	#else
1686	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1687	#endif
1688	/** Bits 63 - NX - PAE - No execution flag. */
1689	#define X86_PML4E_NX RT_BIT_64(63)
1690
1691	/**
1692	* Page Map Level-4 Entry
1693	*/
1694	typedef struct X86PML4EBITS
1695	{
1696	/** Flags whether(=1) or not the page is present. */
1697	uint32_t u1Present : 1;
1698	/** Read(=0) / Write(=1) flag. */
1699	uint32_t u1Write : 1;
1700	/** User(=1) / Supervisor (=0) flag. */
1701	uint32_t u1User : 1;
1702	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1703	uint32_t u1WriteThru : 1;
1704	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1705	uint32_t u1CacheDisable : 1;
1706	/** Accessed flag.
1707	* Indicates that the page have been read or written to. */
1708	uint32_t u1Accessed : 1;
1709	/** Chunk of reserved bits. */
1710	uint32_t u3Reserved : 3;
1711	/** Available for use to system software. */
1712	uint32_t u3Available : 3;
1713	/** Physical Page number of the next level - Low Part. Don't use! */
1714	uint32_t u20PageNoLow : 20;
1715	/** Physical Page number of the next level - High Part. Don't use! */
1716	uint32_t u20PageNoHigh : 20;
1717	/** MBZ bits */
1718	uint32_t u11Reserved : 11;
1719	/** No Execute flag. */
1720	uint32_t u1NoExecute : 1;
1721	} X86PML4EBITS;
1722	/** Pointer to a page map level-4 entry. */
1723	typedef X86PML4EBITS *PX86PML4EBITS;
1724	/** Pointer to a const page map level-4 entry. */
1725	typedef const X86PML4EBITS *PCX86PML4EBITS;
1726
1727	/**
1728	* Page Map Level-4 Entry.
1729	*/
1730	typedef union X86PML4E
1731	{
1732	/** Unsigned integer view. */
1733	X86PGPAEUINT u;
1734	/** Normal view. */
1735	X86PML4EBITS n;
1736	/** 8 bit unsigned integer view. */
1737	uint8_t au8[8];
1738	/** 16 bit unsigned integer view. */
1739	uint16_t au16[4];
1740	/** 32 bit unsigned integer view. */
1741	uint32_t au32[2];
1742	} X86PML4E;
1743	/** Pointer to a page map level-4 entry. */
1744	typedef X86PML4E *PX86PML4E;
1745	/** Pointer to a const page map level-4 entry. */
1746	typedef const X86PML4E *PCX86PML4E;
1747
1748
1749	/**
1750	* Page Map Level-4.
1751	*/
1752	typedef struct X86PML4
1753	{
1754	/** PDE Array. */
1755	X86PML4E a[X86_PG_PAE_ENTRIES];
1756	} X86PML4;
1757	/** Pointer to a page map level-4. */
1758	typedef X86PML4 *PX86PML4;
1759	/** Pointer to a const page map level-4. */
1760	typedef const X86PML4 *PCX86PML4;
1761
1762	/** The page shift to get the PML4 index. */
1763	#define X86_PML4_SHIFT 39
1764	/** The PML4 index mask (apply to a shifted page address). */
1765	#define X86_PML4_MASK 0x1ff
1766
1767	/** @} */
1768
1769	/** @} */
1770
1771
1772	/**
1773	* 80-bit MMX/FPU register type.
1774	*/
1775	typedef struct X86FPUMMX
1776	{
1777	uint8_t reg[10];
1778	} X86FPUMMX;
1779	/** Pointer to a 80-bit MMX/FPU register type. */
1780	typedef X86FPUMMX *PX86FPUMMX;
1781	/** Pointer to a const 80-bit MMX/FPU register type. */
1782	typedef const X86FPUMMX *PCX86FPUMMX;
1783
1784	/**
1785	* FPU state (aka FSAVE/FRSTOR Memory Region).
1786	*/
1787	#pragma pack(1)
1788	typedef struct X86FPUSTATE
1789	{
1790	/** Control word. */
1791	uint16_t FCW;
1792	/** Alignment word */
1793	uint16_t Dummy1;
1794	/** Status word. */
1795	uint16_t FSW;
1796	/** Alignment word */
1797	uint16_t Dummy2;
1798	/** Tag word */
1799	uint16_t FTW;
1800	/** Alignment word */
1801	uint16_t Dummy3;
1802
1803	/** Instruction pointer. */
1804	uint32_t FPUIP;
1805	/** Code selector. */
1806	uint16_t CS;
1807	/** Opcode. */
1808	uint16_t FOP;
1809	/** FOO. */
1810	uint32_t FPUOO;
1811	/** FOS. */
1812	uint32_t FPUOS;
1813	/** FPU view - todo. */
1814	X86FPUMMX regs[8];
1815	} X86FPUSTATE;
1816	#pragma pack()
1817	/** Pointer to a FPU state. */
1818	typedef X86FPUSTATE *PX86FPUSTATE;
1819	/** Pointer to a const FPU state. */
1820	typedef const X86FPUSTATE *PCX86FPUSTATE;
1821
1822	/**
1823	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1824	*/
1825	#pragma pack(1)
1826	typedef struct X86FXSTATE
1827	{
1828	/** Control word. */
1829	uint16_t FCW;
1830	/** Status word. */
1831	uint16_t FSW;
1832	/** Tag word (it's a byte actually). */
1833	uint8_t FTW;
1834	uint8_t huh1;
1835	/** Opcode. */
1836	uint16_t FOP;
1837	/** Instruction pointer. */
1838	uint32_t FPUIP;
1839	/** Code selector. */
1840	uint16_t CS;
1841	uint16_t Rsvrd1;
1842	/* - offset 16 - */
1843	/** Data pointer. */
1844	uint32_t FPUDP;
1845	/** Data segment */
1846	uint16_t DS;
1847	uint16_t Rsrvd2;
1848	uint32_t MXCSR;
1849	uint32_t MXCSR_MASK;
1850	/* - offset 32 - */
1851	union
1852	{
1853	/** MMX view. */
1854	uint64_t mmx;
1855	/** FPU view - todo. */
1856	X86FPUMMX fpu;
1857	/** 8-bit view. */
1858	uint8_t au8[16];
1859	/** 16-bit view. */
1860	uint16_t au16[8];
1861	/** 32-bit view. */
1862	uint32_t au32[4];
1863	/** 64-bit view. */
1864	uint64_t au64[2];
1865	/** 128-bit view. (yeah, very helpful) */
1866	uint128_t au128[1];
1867	} aRegs[8];
1868	/* - offset 160 - */
1869	union
1870	{
1871	/** XMM Register view . /
1872	uint128_t xmm;
1873	/** 8-bit view. */
1874	uint8_t au8[16];
1875	/** 16-bit view. */
1876	uint16_t au16[8];
1877	/** 32-bit view. */
1878	uint32_t au32[4];
1879	/** 64-bit view. */
1880	uint64_t au64[2];
1881	/** 128-bit view. (yeah, very helpful) */
1882	uint128_t au128[1];
1883	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1884	/* - offset 416 - */
1885	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1886	} X86FXSTATE;
1887	#pragma pack()
1888	/** Pointer to a FPU Extended state. */
1889	typedef X86FXSTATE *PX86FXSTATE;
1890	/** Pointer to a const FPU Extended state. */
1891	typedef const X86FXSTATE *PCX86FXSTATE;
1892
1893
1894	/** @name Selector Descriptor
1895	* @{
1896	*/
1897
1898	/**
1899	* Descriptor attributes.
1900	*/
1901	typedef struct X86DESCATTRBITS
1902	{
1903	/** Segment Type. */
1904	unsigned u4Type : 4;
1905	/** Descriptor Type. System(=0) or code/data selector */
1906	unsigned u1DescType : 1;
1907	/** Descriptor Privelege level. */
1908	unsigned u2Dpl : 2;
1909	/** Flags selector present(=1) or not. */
1910	unsigned u1Present : 1;
1911	/** Segment limit 16-19. */
1912	unsigned u4LimitHigh : 4;
1913	/** Available for system software. */
1914	unsigned u1Available : 1;
1915	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1916	unsigned u1Long : 1;
1917	/** This flags meaning depends on the segment type. Try make sense out
1918	* of the intel manual yourself. */
1919	unsigned u1DefBig : 1;
1920	/** Granularity of the limit. If set 4KB granularity is used, if
1921	* clear byte. */
1922	unsigned u1Granularity : 1;
1923	} X86DESCATTRBITS;
1924
1925
1926	#pragma pack(1)
1927	typedef union X86DESCATTR
1928	{
1929	/** Unsigned integer view. */
1930	uint32_t u;
1931	/** Normal view. */
1932	X86DESCATTRBITS n;
1933	} X86DESCATTR;
1934	#pragma pack()
1935	/** Pointer to descriptor attributes. */
1936	typedef X86DESCATTR *PX86DESCATTR;
1937	/** Pointer to const descriptor attributes. */
1938	typedef const X86DESCATTR *PCX86DESCATTR;
1939
1940
1941	/**
1942	* Generic descriptor table entry
1943	*/
1944	#pragma pack(1)
1945	typedef struct X86DESCGENERIC
1946	{
1947	/** Limit - Low word. */
1948	unsigned u16LimitLow : 16;
1949	/** Base address - lowe word.
1950	* Don't try set this to 24 because MSC is doing stupid things then. */
1951	unsigned u16BaseLow : 16;
1952	/** Base address - first 8 bits of high word. */
1953	unsigned u8BaseHigh1 : 8;
1954	/** Segment Type. */
1955	unsigned u4Type : 4;
1956	/** Descriptor Type. System(=0) or code/data selector */
1957	unsigned u1DescType : 1;
1958	/** Descriptor Privelege level. */
1959	unsigned u2Dpl : 2;
1960	/** Flags selector present(=1) or not. */
1961	unsigned u1Present : 1;
1962	/** Segment limit 16-19. */
1963	unsigned u4LimitHigh : 4;
1964	/** Available for system software. */
1965	unsigned u1Available : 1;
1966	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1967	unsigned u1Long : 1;
1968	/** This flags meaning depends on the segment type. Try make sense out
1969	* of the intel manual yourself. */
1970	unsigned u1DefBig : 1;
1971	/** Granularity of the limit. If set 4KB granularity is used, if
1972	* clear byte. */
1973	unsigned u1Granularity : 1;
1974	/** Base address - highest 8 bits. */
1975	unsigned u8BaseHigh2 : 8;
1976	} X86DESCGENERIC;
1977	#pragma pack()
1978	/** Pointer to a generic descriptor entry. */
1979	typedef X86DESCGENERIC *PX86DESCGENERIC;
1980	/** Pointer to a const generic descriptor entry. */
1981	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1982
1983	/**
1984	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
1985	*/
1986	typedef struct X86DESCGATE
1987	{
1988	/** Target code segment offset - Low word.
1989	* Ignored if task-gate. */
1990	unsigned u16OffsetLow : 16;
1991	/** Target code segment selector for call-, interrupt- and trap-gates,
1992	* TSS selector if task-gate. */
1993	unsigned u16Sel : 16;
1994	/** Number of parameters for a call-gate.
1995	* Ignored if interrupt-, trap- or task-gate. */
1996	unsigned u4ParmCount : 4;
1997	/** Reserved / ignored. */
1998	unsigned u4Reserved : 4;
1999	/** Segment Type. */
2000	unsigned u4Type : 4;
2001	/** Descriptor Type (0 = system). */
2002	unsigned u1DescType : 1;
2003	/** Descriptor Privelege level. */
2004	unsigned u2Dpl : 2;
2005	/** Flags selector present(=1) or not. */
2006	unsigned u1Present : 1;
2007	/** Target code segment offset - High word.
2008	* Ignored if task-gate. */
2009	unsigned u16OffsetHigh : 16;
2010	} X86DESCGATE;
2011	AssertCompileSize(X86DESCGATE, 8);
2012	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2013	typedef X86DESCGATE *PX86DESCGATE;
2014	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2015	typedef const X86DESCGATE *PCX86DESCGATE;
2016
2017	/**
2018	* Descriptor table entry.
2019	*/
2020	#pragma pack(1)
2021	typedef union X86DESC
2022	{
2023	/** Generic descriptor view. */
2024	X86DESCGENERIC Gen;
2025	/** Gate descriptor view. */
2026	X86DESCGATE Gate;
2027
2028	/** 8 bit unsigned interger view. */
2029	uint8_t au8[8];
2030	/** 16 bit unsigned interger view. */
2031	uint16_t au16[4];
2032	/** 32 bit unsigned interger view. */
2033	uint32_t au32[2];
2034	} X86DESC;
2035	AssertCompileSize(X86DESC, 8);
2036	#pragma pack()
2037	/** Pointer to descriptor table entry. */
2038	typedef X86DESC *PX86DESC;
2039	/** Pointer to const descriptor table entry. */
2040	typedef const X86DESC *PCX86DESC;
2041
2042	/** @def X86DESC_BASE
2043	* Return the base address of a descriptor.
2044	*/
2045	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2046	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2047	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2048	\| ( (desc).Gen.u16BaseLow ) )
2049
2050	/** @def X86DESC_LIMIT
2051	* Return the limit of a descriptor.
2052	*/
2053	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2054	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2055	\| ( (desc).Gen.u16LimitLow ) )
2056
2057	/**
2058	* 64 bits generic descriptor table entry
2059	* Note: most of these bits have no meaning in long mode.
2060	*/
2061	#pragma pack(1)
2062	typedef struct X86DESC64GENERIC
2063	{
2064	/** Limit - Low word - IGNORED. */
2065	unsigned u16LimitLow : 16;
2066	/** Base address - lowe word. - IGNORED
2067	* Don't try set this to 24 because MSC is doing stupid things then. */
2068	unsigned u16BaseLow : 16;
2069	/** Base address - first 8 bits of high word. - IGNORED */
2070	unsigned u8BaseHigh1 : 8;
2071	/** Segment Type. */
2072	unsigned u4Type : 4;
2073	/** Descriptor Type. System(=0) or code/data selector */
2074	unsigned u1DescType : 1;
2075	/** Descriptor Privelege level. */
2076	unsigned u2Dpl : 2;
2077	/** Flags selector present(=1) or not. */
2078	unsigned u1Present : 1;
2079	/** Segment limit 16-19. - IGNORED */
2080	unsigned u4LimitHigh : 4;
2081	/** Available for system software. - IGNORED */
2082	unsigned u1Available : 1;
2083	/** Long mode flag. */
2084	unsigned u1Long : 1;
2085	/** This flags meaning depends on the segment type. Try make sense out
2086	* of the intel manual yourself. */
2087	unsigned u1DefBig : 1;
2088	/** Granularity of the limit. If set 4KB granularity is used, if
2089	* clear byte. - IGNORED */
2090	unsigned u1Granularity : 1;
2091	/** Base address - highest 8 bits. - IGNORED */
2092	unsigned u8BaseHigh2 : 8;
2093	/** Base address - bits 63-32. */
2094	unsigned u32BaseHigh3 : 32;
2095	unsigned u8Reserved : 8;
2096	unsigned u5Zeros : 5;
2097	unsigned u19Reserved : 19;
2098	} X86DESC64GENERIC;
2099	#pragma pack()
2100	/** Pointer to a generic descriptor entry. */
2101	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2102	/** Pointer to a const generic descriptor entry. */
2103	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2104
2105	/**
2106	* System descriptor table entry (64 bits)
2107	*
2108	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2109	*/
2110	#pragma pack(1)
2111	typedef struct X86DESC64SYSTEM
2112	{
2113	/** Limit - Low word. */
2114	unsigned u16LimitLow : 16;
2115	/** Base address - lowe word.
2116	* Don't try set this to 24 because MSC is doing stupid things then. */
2117	unsigned u16BaseLow : 16;
2118	/** Base address - first 8 bits of high word. */
2119	unsigned u8BaseHigh1 : 8;
2120	/** Segment Type. */
2121	unsigned u4Type : 4;
2122	/** Descriptor Type. System(=0) or code/data selector */
2123	unsigned u1DescType : 1;
2124	/** Descriptor Privelege level. */
2125	unsigned u2Dpl : 2;
2126	/** Flags selector present(=1) or not. */
2127	unsigned u1Present : 1;
2128	/** Segment limit 16-19. */
2129	unsigned u4LimitHigh : 4;
2130	/** Available for system software. */
2131	unsigned u1Available : 1;
2132	/** Reserved - 0. */
2133	unsigned u1Reserved : 1;
2134	/** This flags meaning depends on the segment type. Try make sense out
2135	* of the intel manual yourself. */
2136	unsigned u1DefBig : 1;
2137	/** Granularity of the limit. If set 4KB granularity is used, if
2138	* clear byte. */
2139	unsigned u1Granularity : 1;
2140	/** Base address - bits 31-24. */
2141	unsigned u8BaseHigh2 : 8;
2142	/** Base address - bits 63-32. */
2143	unsigned u32BaseHigh3 : 32;
2144	unsigned u8Reserved : 8;
2145	unsigned u5Zeros : 5;
2146	unsigned u19Reserved : 19;
2147	} X86DESC64SYSTEM;
2148	#pragma pack()
2149	/** Pointer to a system descriptor entry. */
2150	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2151	/** Pointer to a const system descriptor entry. */
2152	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2153
2154	/**
2155	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2156	*/
2157	typedef struct X86DESC64GATE
2158	{
2159	/** Target code segment offset - Low word. */
2160	unsigned u16OffsetLow : 16;
2161	/** Target code segment selector. */
2162	unsigned u16Sel : 16;
2163	/** Interrupt stack table for interrupt- and trap-gates.
2164	* Ignored by call-gates. */
2165	unsigned u3IST : 3;
2166	/** Reserved / ignored. */
2167	unsigned u5Reserved : 5;
2168	/** Segment Type. */
2169	unsigned u4Type : 4;
2170	/** Descriptor Type (0 = system). */
2171	unsigned u1DescType : 1;
2172	/** Descriptor Privelege level. */
2173	unsigned u2Dpl : 2;
2174	/** Flags selector present(=1) or not. */
2175	unsigned u1Present : 1;
2176	/** Target code segment offset - High word.
2177	* Ignored if task-gate. */
2178	unsigned u16OffsetHigh : 16;
2179	/** Target code segment offset - Top dword.
2180	* Ignored if task-gate. */
2181	unsigned u32OffsetTop : 32;
2182	/** Reserved / ignored / must be zero.
2183	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2184	unsigned u32Reserved : 32;
2185	} X86DESC64GATE;
2186	AssertCompileSize(X86DESC64GATE, 16);
2187	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2188	typedef X86DESC64GATE *PX86DESC64GATE;
2189	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2190	typedef const X86DESC64GATE *PCX86DESC64GATE;
2191
2192
2193	/**
2194	* Descriptor table entry.
2195	*/
2196	#pragma pack(1)
2197	typedef union X86DESC64
2198	{
2199	/** Generic descriptor view. */
2200	X86DESC64GENERIC Gen;
2201	/** System descriptor view. */
2202	X86DESC64SYSTEM System;
2203	/** Gate descriptor view. */
2204	X86DESC64GATE Gate;
2205
2206	/** 8 bit unsigned interger view. */
2207	uint8_t au8[16];
2208	/** 16 bit unsigned interger view. */
2209	uint16_t au16[8];
2210	/** 32 bit unsigned interger view. */
2211	uint32_t au32[4];
2212	/** 64 bit unsigned interger view. */
2213	uint64_t au64[2];
2214	} X86DESC64;
2215	AssertCompileSize(X86DESC64, 16);
2216	#pragma pack()
2217	/** Pointer to descriptor table entry. */
2218	typedef X86DESC64 *PX86DESC64;
2219	/** Pointer to const descriptor table entry. */
2220	typedef const X86DESC64 *PCX86DESC64;
2221
2222	#if HC_ARCH_BITS == 64
2223	typedef X86DESC64 X86DESCHC;
2224	typedef X86DESC64 *PX86DESCHC;
2225	#else
2226	typedef X86DESC X86DESCHC;
2227	typedef X86DESC *PX86DESCHC;
2228	#endif
2229
2230	/** @def X86DESC64_BASE
2231	* Return the base of a 64-bit descriptor.
2232	*/
2233	#define X86DESC64_BASE(desc) \
2234	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2235	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2236	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2237	\| ( (desc).Gen.u16BaseLow ) )
2238
2239
2240	/** @name Selector Descriptor Types.
2241	* @{
2242	*/
2243
2244	/** @name Non-System Selector Types.
2245	* @{ */
2246	/** Code(=set)/Data(=clear) bit. */
2247	#define X86_SEL_TYPE_CODE 8
2248	/** Memory(=set)/System(=clear) bit. */
2249	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2250	/** Accessed bit. */
2251	#define X86_SEL_TYPE_ACCESSED 1
2252	/** Expand down bit (for data selectors only). */
2253	#define X86_SEL_TYPE_DOWN 4
2254	/** Conforming bit (for code selectors only). */
2255	#define X86_SEL_TYPE_CONF 4
2256	/** Write bit (for data selectors only). */
2257	#define X86_SEL_TYPE_WRITE 2
2258	/** Read bit (for code selectors only). */
2259	#define X86_SEL_TYPE_READ 2
2260
2261	/** Read only selector type. */
2262	#define X86_SEL_TYPE_RO 0
2263	/** Accessed read only selector type. */
2264	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2265	/** Read write selector type. */
2266	#define X86_SEL_TYPE_RW 2
2267	/** Accessed read write selector type. */
2268	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2269	/** Expand down read only selector type. */
2270	#define X86_SEL_TYPE_RO_DOWN 4
2271	/** Accessed expand down read only selector type. */
2272	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2273	/** Expand down read write selector type. */
2274	#define X86_SEL_TYPE_RW_DOWN 6
2275	/** Accessed expand down read write selector type. */
2276	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2277	/** Execute only selector type. */
2278	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2279	/** Accessed execute only selector type. */
2280	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2281	/** Execute and read selector type. */
2282	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2283	/** Accessed execute and read selector type. */
2284	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2285	/** Conforming execute only selector type. */
2286	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2287	/** Accessed Conforming execute only selector type. */
2288	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2289	/** Conforming execute and write selector type. */
2290	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2291	/** Accessed Conforming execute and write selector type. */
2292	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2293	/** @} */
2294
2295
2296	/** @name System Selector Types.
2297	* @{ */
2298	/** Undefined system selector type. */
2299	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2300	/** 286 TSS selector. */
2301	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2302	/** LDT selector. */
2303	#define X86_SEL_TYPE_SYS_LDT 2
2304	/** 286 TSS selector - Busy. */
2305	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2306	/** 286 Callgate selector. */
2307	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2308	/** Taskgate selector. */
2309	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2310	/** 286 Interrupt gate selector. */
2311	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2312	/** 286 Trapgate selector. */
2313	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2314	/** Undefined system selector. */
2315	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2316	/** 386 TSS selector. */
2317	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2318	/** Undefined system selector. */
2319	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2320	/** 386 TSS selector - Busy. */
2321	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2322	/** 386 Callgate selector. */
2323	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2324	/** Undefined system selector. */
2325	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2326	/** 386 Interruptgate selector. */
2327	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2328	/** 386 Trapgate selector. */
2329	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2330	/** @} */
2331
2332	/** @name AMD64 System Selector Types.
2333	* @{ */
2334	#define AMD64_SEL_TYPE_SYS_LDT 2
2335	/** 286 TSS selector - Busy. */
2336	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2337	/** 386 TSS selector - Busy. */
2338	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2339	/** 386 Callgate selector. */
2340	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2341	/** 386 Interruptgate selector. */
2342	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2343	/** 386 Trapgate selector. */
2344	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2345	/** @} */
2346
2347	/** @} */
2348
2349
2350	/** @name Descriptor Table Entry Flag Masks.
2351	* These are for the 2nd 32-bit word of a descriptor.
2352	* @{ */
2353	/** Bits 8-11 - TYPE - Descriptor type mask. */
2354	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2355	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2356	#define X86_DESC_S RT_BIT(12)
2357	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2358	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2359	/** Bit 15 - P - Present. */
2360	#define X86_DESC_P RT_BIT(15)
2361	/** Bit 20 - AVL - Available for system software. */
2362	#define X86_DESC_AVL RT_BIT(20)
2363	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2364	#define X86_DESC_DB RT_BIT(22)
2365	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2366	* used, if clear byte. */
2367	#define X86_DESC_G RT_BIT(23)
2368	/** @} */
2369
2370	/** @} */
2371
2372	/** @name Task segment.
2373	* @{
2374	*/
2375	#pragma pack(1)
2376	typedef struct X86TSS32
2377	{
2378	/** Back link to previous task. (static) */
2379	RTSEL selPrev;
2380	uint16_t padding1;
2381	/** Ring-0 stack pointer. (static) */
2382	uint32_t esp0;
2383	/** Ring-0 stack segment. (static) */
2384	RTSEL ss0;
2385	uint16_t padding_ss0;
2386	/** Ring-1 stack pointer. (static) */
2387	uint32_t esp1;
2388	/** Ring-1 stack segment. (static) */
2389	RTSEL ss1;
2390	uint16_t padding_ss1;
2391	/** Ring-2 stack pointer. (static) */
2392	uint32_t esp2;
2393	/** Ring-2 stack segment. (static) */
2394	RTSEL ss2;
2395	uint16_t padding_ss2;
2396	/** Page directory for the task. (static) */
2397	uint32_t cr3;
2398	/** EIP before task switch. */
2399	uint32_t eip;
2400	/** EFLAGS before task switch. */
2401	uint32_t eflags;
2402	/** EAX before task switch. */
2403	uint32_t eax;
2404	/** ECX before task switch. */
2405	uint32_t ecx;
2406	/** EDX before task switch. */
2407	uint32_t edx;
2408	/** EBX before task switch. */
2409	uint32_t ebx;
2410	/** ESP before task switch. */
2411	uint32_t esp;
2412	/** EBP before task switch. */
2413	uint32_t ebp;
2414	/** ESI before task switch. */
2415	uint32_t esi;
2416	/** EDI before task switch. */
2417	uint32_t edi;
2418	/** ES before task switch. */
2419	RTSEL es;
2420	uint16_t padding_es;
2421	/** CS before task switch. */
2422	RTSEL cs;
2423	uint16_t padding_cs;
2424	/** SS before task switch. */
2425	RTSEL ss;
2426	uint16_t padding_ss;
2427	/** DS before task switch. */
2428	RTSEL ds;
2429	uint16_t padding_ds;
2430	/** FS before task switch. */
2431	RTSEL fs;
2432	uint16_t padding_fs;
2433	/** GS before task switch. */
2434	RTSEL gs;
2435	uint16_t padding_gs;
2436	/** LDTR before task switch. */
2437	RTSEL selLdt;
2438	uint16_t padding_ldt;
2439	/** Debug trap flag */
2440	uint16_t fDebugTrap;
2441	/** Offset relative to the TSS of the start of the I/O Bitmap
2442	* and the end of the interrupt redirection bitmap. */
2443	uint16_t offIoBitmap;
2444	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2445	uint8_t IntRedirBitmap[32];
2446	} X86TSS32;
2447	#pragma pack()
2448	/** Pointer to task segment. */
2449	typedef X86TSS32 *PX86TSS32;
2450	/** Pointer to const task segment. */
2451	typedef const X86TSS32 *PCX86TSS32;
2452	/** @} */
2453
2454
2455	/** @name 64 bits Task segment.
2456	* @{
2457	*/
2458	#pragma pack(1)
2459	typedef struct X86TSS64
2460	{
2461	/** Reserved. */
2462	uint32_t u32Reserved;
2463	/** Ring-0 stack pointer. (static) */
2464	uint64_t rsp0;
2465	/** Ring-1 stack pointer. (static) */
2466	uint64_t rsp1;
2467	/** Ring-2 stack pointer. (static) */
2468	uint64_t rsp2;
2469	/** Reserved. */
2470	uint32_t u32Reserved2[2];
2471	/* IST */
2472	uint64_t ist1;
2473	uint64_t ist2;
2474	uint64_t ist3;
2475	uint64_t ist4;
2476	uint64_t ist5;
2477	uint64_t ist6;
2478	uint64_t ist7;
2479	/* Reserved. */
2480	uint16_t u16Reserved[5];
2481	/** Offset relative to the TSS of the start of the I/O Bitmap
2482	* and the end of the interrupt redirection bitmap. */
2483	uint16_t offIoBitmap;
2484	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2485	uint8_t IntRedirBitmap[32];
2486	} X86TSS64;
2487	#pragma pack()
2488	/** Pointer to task segment. */
2489	typedef X86TSS64 *PX86TSS64;
2490	/** Pointer to const task segment. */
2491	typedef const X86TSS64 *PCX86TSS64;
2492	AssertCompileSize(X86TSS64, 136);
2493
2494	/** @} */
2495
2496
2497	/** @name Selectors.
2498	* @{
2499	*/
2500
2501	/**
2502	* The shift used to convert a selector from and to index an index (C).
2503	*/
2504	#define X86_SEL_SHIFT 3
2505
2506	/**
2507	* The shift used to convert a selector from and to index an index (C).
2508	*/
2509	#define AMD64_SEL_SHIFT 4
2510
2511	/** @def X86_SEL_SHIFT_HC
2512	* This is for use with X86DESCHC. */
2513	#if HC_ARCH_BITS == 64
2514	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2515	#else
2516	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2517	#endif
2518
2519	/**
2520	* The mask used to mask off the table indicator and CPL of an selector.
2521	*/
2522	#define X86_SEL_MASK 0xfff8
2523
2524	/**
2525	* The bit indicating that a selector is in the LDT and not in the GDT.
2526	*/
2527	#define X86_SEL_LDT 0x0004
2528	/**
2529	* The bit mask for getting the RPL of a selector.
2530	*/
2531	#define X86_SEL_RPL 0x0003
2532
2533	/** @} */
2534
2535
2536	/**
2537	* x86 Exceptions/Faults/Traps.
2538	*/
2539	typedef enum X86XCPT
2540	{
2541	/** \#DE - Divide error. */
2542	X86_XCPT_DE = 0x00,
2543	/** \#DB - Debug event (single step, DRx, ..) */
2544	X86_XCPT_DB = 0x01,
2545	/** NMI - Non-Maskable Interrupt */
2546	X86_XCPT_NMI = 0x02,
2547	/** \#BP - Breakpoint (INT3). */
2548	X86_XCPT_BP = 0x03,
2549	/** \#OF - Overflow (INTO). */
2550	X86_XCPT_OF = 0x04,
2551	/** \#BR - Bound range exceeded (BOUND). */
2552	X86_XCPT_BR = 0x05,
2553	/** \#UD - Undefined opcode. */
2554	X86_XCPT_UD = 0x06,
2555	/** \#NM - Device not available (math coprocessor device). */
2556	X86_XCPT_NM = 0x07,
2557	/** \#DF - Double fault. */
2558	X86_XCPT_DF = 0x08,
2559	/** ??? - Coprocessor segment overrun (obsolete). */
2560	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2561	/** \#TS - Taskswitch (TSS). */
2562	X86_XCPT_TS = 0x0a,
2563	/** \#NP - Segment no present. */
2564	X86_XCPT_NP = 0x0b,
2565	/** \#SS - Stack segment fault. */
2566	X86_XCPT_SS = 0x0c,
2567	/** \#GP - General protection fault. */
2568	X86_XCPT_GP = 0x0d,
2569	/** \#PF - Page fault. */
2570	X86_XCPT_PF = 0x0e,
2571	/* 0x0f is reserved. */
2572	/** \#MF - Math fault (FPU). */
2573	X86_XCPT_MF = 0x10,
2574	/** \#AC - Alignment check. */
2575	X86_XCPT_AC = 0x11,
2576	/** \#MC - Machine check. */
2577	X86_XCPT_MC = 0x12,
2578	/** \#XF - SIMD Floating-Pointer Exception. */
2579	X86_XCPT_XF = 0x13
2580	} X86XCPT;
2581	/** Pointer to a x86 exception code. */
2582	typedef X86XCPT *PX86XCPT;
2583	/** Pointer to a const x86 exception code. */
2584	typedef const X86XCPT *PCX86XCPT;
2585
2586
2587	/** @name Trap Error Codes
2588	* @{
2589	*/
2590	/** External indicator. */
2591	#define X86_TRAP_ERR_EXTERNAL 1
2592	/** IDT indicator. */
2593	#define X86_TRAP_ERR_IDT 2
2594	/** Descriptor table indicator - If set LDT, if clear GDT. */
2595	#define X86_TRAP_ERR_TI 4
2596	/** Mask for getting the selector. */
2597	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2598	/** Shift for getting the selector table index (C type index). */
2599	#define X86_TRAP_ERR_SEL_SHIFT 3
2600	/** @} */
2601
2602
2603	/** @name \#PF Trap Error Codes
2604	* @{
2605	*/
2606	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2607	#define X86_TRAP_PF_P RT_BIT(0)
2608	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2609	#define X86_TRAP_PF_RW RT_BIT(1)
2610	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2611	#define X86_TRAP_PF_US RT_BIT(2)
2612	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2613	#define X86_TRAP_PF_RSVD RT_BIT(3)
2614	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2615	#define X86_TRAP_PF_ID RT_BIT(4)
2616	/** @} */
2617
2618	#pragma pack(1)
2619	/**
2620	* 32-bit IDTR/GDTR.
2621	*/
2622	typedef struct X86XDTR32
2623	{
2624	/** Size of the descriptor table. */
2625	uint16_t cb;
2626	/** Address of the descriptor table. */
2627	uint32_t uAddr;
2628	} X86XDTR32, *PX86XDTR32;
2629	#pragma pack()
2630
2631	#pragma pack(1)
2632	/**
2633	* 64-bit IDTR/GDTR.
2634	*/
2635	typedef struct X86XDTR64
2636	{
2637	/** Size of the descriptor table. */
2638	uint16_t cb;
2639	/** Address of the descriptor table. */
2640	uint64_t uAddr;
2641	} X86XDTR64, *PX86XDTR64;
2642	#pragma pack()
2643
2644	/** @} */
2645
2646	#endif
2647

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