VirtualBox

source: vbox/trunk/include/VBox/x86.h@ 14741

Last change on this file since 14741 was 14741, checked in by vboxsync, 17 years ago

x86.h: Added X86_PTE_BIT_* for use with ASMAtomicBit*.
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File size: 85.7 KB
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1/** @file
2 * X86 (and AMD64) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30/*
31 * x86.mac is generated from this file using:
32 * sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33 */
34
35#ifndef ___VBox_x86_h
36#define ___VBox_x86_h
37
38#include <VBox/types.h>
39
40/* Workaround for Solaris sys/regset.h defining CS, DS */
41#if defined(RT_OS_SOLARIS)
42# undef CS
43# undef DS
44#endif
45
46/** @defgroup grp_x86 x86 Types and Definitions
47 * @{
48 */
49
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105/**
106 * EFLAGS.
107 */
108typedef union X86EFLAGS
109{
110 /** The plain unsigned view. */
111 uint32_t u;
112 /** The bitfield view. */
113 X86EFLAGSBITS Bits;
114 /** The 8-bit view. */
115 uint8_t au8[4];
116 /** The 16-bit view. */
117 uint16_t au16[2];
118 /** The 32-bit view. */
119 uint32_t au32[1];
120 /** The 32-bit view. */
121 uint32_t u32;
122} X86EFLAGS;
123/** Pointer to EFLAGS. */
124typedef X86EFLAGS *PX86EFLAGS;
125/** Pointer to const EFLAGS. */
126typedef const X86EFLAGS *PCX86EFLAGS;
127
128/**
129 * RFLAGS (32 upper bits are reserved).
130 */
131typedef union X86RFLAGS
132{
133 /** The plain unsigned view. */
134 uint64_t u;
135 /** The bitfield view. */
136 X86EFLAGSBITS Bits;
137 /** The 8-bit view. */
138 uint8_t au8[8];
139 /** The 16-bit view. */
140 uint16_t au16[4];
141 /** The 32-bit view. */
142 uint32_t au32[2];
143 /** The 64-bit view. */
144 uint64_t au64[1];
145 /** The 64-bit view. */
146 uint64_t u64;
147} X86RFLAGS;
148/** Pointer to RFLAGS. */
149typedef X86RFLAGS *PX86RFLAGS;
150/** Pointer to const RFLAGS. */
151typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154/** @name EFLAGS
155 * @{
156 */
157/** Bit 0 - CF - Carry flag - Status flag. */
158#define X86_EFL_CF RT_BIT(0)
159/** Bit 2 - PF - Parity flag - Status flag. */
160#define X86_EFL_PF RT_BIT(2)
161/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162#define X86_EFL_AF RT_BIT(4)
163/** Bit 6 - ZF - Zero flag - Status flag. */
164#define X86_EFL_ZF RT_BIT(6)
165/** Bit 7 - SF - Signed flag - Status flag. */
166#define X86_EFL_SF RT_BIT(7)
167/** Bit 8 - TF - Trap flag - System flag. */
168#define X86_EFL_TF RT_BIT(8)
169/** Bit 9 - IF - Interrupt flag - System flag. */
170#define X86_EFL_IF RT_BIT(9)
171/** Bit 10 - DF - Direction flag - Control flag. */
172#define X86_EFL_DF RT_BIT(10)
173/** Bit 11 - OF - Overflow flag - Status flag. */
174#define X86_EFL_OF RT_BIT(11)
175/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176#define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
177/** Bit 14 - NT - Nested task flag - System flag. */
178#define X86_EFL_NT RT_BIT(14)
179/** Bit 16 - RF - Resume flag - System flag. */
180#define X86_EFL_RF RT_BIT(16)
181/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182#define X86_EFL_VM RT_BIT(17)
183/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184#define X86_EFL_AC RT_BIT(18)
185/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186#define X86_EFL_VIF RT_BIT(19)
187/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188#define X86_EFL_VIP RT_BIT(20)
189/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190#define X86_EFL_ID RT_BIT(21)
191/** IOPL shift. */
192#define X86_EFL_IOPL_SHIFT 12
193/** The the IOPL level from the flags. */
194#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195/** @} */
196
197
198/** CPUID Feature information - ECX.
199 * CPUID query with EAX=1.
200 */
201typedef struct X86CPUIDFEATECX
202{
203 /** Bit 0 - SSE3 - Supports SSE3 or not. */
204 unsigned u1SSE3 : 1;
205 /** Reserved. */
206 unsigned u2Reserved1 : 2;
207 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208 unsigned u1Monitor : 1;
209 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210 unsigned u1CPLDS : 1;
211 /** Bit 5 - VMX - Virtual Machine Technology. */
212 unsigned u1VMX : 1;
213 /** Reserved. */
214 unsigned u1Reserved2 : 1;
215 /** Bit 7 - EST - Enh. SpeedStep Tech. */
216 unsigned u1EST : 1;
217 /** Bit 8 - TM2 - Terminal Monitor 2. */
218 unsigned u1TM2 : 1;
219 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220 unsigned u1SSSE3 : 1;
221 /** Bit 10 - CNTX-ID - L1 Context ID. */
222 unsigned u1CNTXID : 1;
223 /** Reserved. */
224 unsigned u2Reserved4 : 2;
225 /** Bit 13 - CX16 - CMPXCHG16B. */
226 unsigned u1CX16 : 1;
227 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228 unsigned u1TPRUpdate : 1;
229 /** Reserved. */
230 unsigned u17Reserved5 : 17;
231
232} X86CPUIDFEATECX;
233/** Pointer to CPUID Feature Information - ECX. */
234typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235/** Pointer to const CPUID Feature Information - ECX. */
236typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239/** CPUID Feature Information - EDX.
240 * CPUID query with EAX=1.
241 */
242typedef struct X86CPUIDFEATEDX
243{
244 /** Bit 0 - FPU - x87 FPU on Chip. */
245 unsigned u1FPU : 1;
246 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247 unsigned u1VME : 1;
248 /** Bit 2 - DE - Debugging extensions. */
249 unsigned u1DE : 1;
250 /** Bit 3 - PSE - Page Size Extension. */
251 unsigned u1PSE : 1;
252 /** Bit 4 - TSC - Time Stamp Counter. */
253 unsigned u1TSC : 1;
254 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255 unsigned u1MSR : 1;
256 /** Bit 6 - PAE - Physical Address Extension. */
257 unsigned u1PAE : 1;
258 /** Bit 7 - MCE - Machine Check Exception. */
259 unsigned u1MCE : 1;
260 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
261 unsigned u1CX8 : 1;
262 /** Bit 9 - APIC - APIC On-Chip. */
263 unsigned u1APIC : 1;
264 /** Bit 10 - Reserved. */
265 unsigned u1Reserved1 : 1;
266 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267 unsigned u1SEP : 1;
268 /** Bit 12 - MTRR - Memory Type Range Registers. */
269 unsigned u1MTRR : 1;
270 /** Bit 13 - PGE - PTE Global Bit. */
271 unsigned u1PGE : 1;
272 /** Bit 14 - MCA - Machine Check Architecture. */
273 unsigned u1MCA : 1;
274 /** Bit 15 - CMOV - Conditional Move Instructions. */
275 unsigned u1CMOV : 1;
276 /** Bit 16 - PAT - Page Attribute Table. */
277 unsigned u1PAT : 1;
278 /** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279 unsigned u1PSE36 : 1;
280 /** Bit 18 - PSN - Processor Serial Number. */
281 unsigned u1PSN : 1;
282 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
283 unsigned u1CLFSH : 1;
284 /** Bit 20 - Reserved. */
285 unsigned u1Reserved2 : 1;
286 /** Bit 21 - DS - Debug Store. */
287 unsigned u1DS : 1;
288 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289 unsigned u1ACPI : 1;
290 /** Bit 23 - MMX - Intel MMX 'Technology'. */
291 unsigned u1MMX : 1;
292 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293 unsigned u1FXSR : 1;
294 /** Bit 25 - SSE - SSE Support. */
295 unsigned u1SSE : 1;
296 /** Bit 26 - SSE2 - SSE2 Support. */
297 unsigned u1SSE2 : 1;
298 /** Bit 27 - SS - Self Snoop. */
299 unsigned u1SS : 1;
300 /** Bit 28 - HTT - Hyper-Threading Technology. */
301 unsigned u1HTT : 1;
302 /** Bit 29 - TM - Thermal Monitor. */
303 unsigned u1TM : 1;
304 /** Bit 30 - Reserved - . */
305 unsigned u1Reserved3 : 1;
306 /** Bit 31 - PBE - Pending Break Enabled. */
307 unsigned u1PBE : 1;
308} X86CPUIDFEATEDX;
309/** Pointer to CPUID Feature Information - EDX. */
310typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311/** Pointer to const CPUID Feature Information - EDX. */
312typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314/** @name CPUID Vendor information.
315 * CPUID query with EAX=0.
316 * @{
317 */
318#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325/** @} */
326
327
328/** @name CPUID Feature information.
329 * CPUID query with EAX=1.
330 * @{
331 */
332/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352/** ECX Bit 21 - x2APIC support. */
353#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
354/** ECX Bit 23 - POPCOUNT instruction. */
355#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
356
357
358/** Bit 0 - FPU - x87 FPU on Chip. */
359#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
360/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
361#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
362/** Bit 2 - DE - Debugging extensions. */
363#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
364/** Bit 3 - PSE - Page Size Extension. */
365#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
366/** Bit 4 - TSC - Time Stamp Counter. */
367#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
368/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
369#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
370/** Bit 6 - PAE - Physical Address Extension. */
371#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
372/** Bit 7 - MCE - Machine Check Exception. */
373#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
374/** Bit 8 - CX8 - CMPXCHG8B instruction. */
375#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
376/** Bit 9 - APIC - APIC On-Chip. */
377#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
378/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
379#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
380/** Bit 12 - MTRR - Memory Type Range Registers. */
381#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
382/** Bit 13 - PGE - PTE Global Bit. */
383#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
384/** Bit 14 - MCA - Machine Check Architecture. */
385#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
386/** Bit 15 - CMOV - Conditional Move Instructions. */
387#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
388/** Bit 16 - PAT - Page Attribute Table. */
389#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
390/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
391#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
392/** Bit 18 - PSN - Processor Serial Number. */
393#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
394/** Bit 19 - CLFSH - CLFLUSH Instruction. */
395#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
396/** Bit 21 - DS - Debug Store. */
397#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
398/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
399#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
400/** Bit 23 - MMX - Intel MMX Technology. */
401#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
402/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
403#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
404/** Bit 25 - SSE - SSE Support. */
405#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
406/** Bit 26 - SSE2 - SSE2 Support. */
407#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
408/** Bit 27 - SS - Self Snoop. */
409#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
410/** Bit 28 - HTT - Hyper-Threading Technology. */
411#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
412/** Bit 29 - TM - Therm. Monitor. */
413#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
414/** Bit 31 - PBE - Pending Break Enabled. */
415#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
416/** @} */
417
418
419/** @name CPUID AMD Feature information.
420 * CPUID query with EAX=0x80000001.
421 * @{
422 */
423/** Bit 0 - FPU - x87 FPU on Chip. */
424#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
425/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
426#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
427/** Bit 2 - DE - Debugging extensions. */
428#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
429/** Bit 3 - PSE - Page Size Extension. */
430#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
431/** Bit 4 - TSC - Time Stamp Counter. */
432#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
433/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
434#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
435/** Bit 6 - PAE - Physical Address Extension. */
436#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
437/** Bit 7 - MCE - Machine Check Exception. */
438#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
439/** Bit 8 - CX8 - CMPXCHG8B instruction. */
440#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
441/** Bit 9 - APIC - APIC On-Chip. */
442#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
443/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
444#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
445/** Bit 12 - MTRR - Memory Type Range Registers. */
446#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
447/** Bit 13 - PGE - PTE Global Bit. */
448#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
449/** Bit 14 - MCA - Machine Check Architecture. */
450#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
451/** Bit 15 - CMOV - Conditional Move Instructions. */
452#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
453/** Bit 16 - PAT - Page Attribute Table. */
454#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
455/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
456#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
457/** Bit 20 - NX - AMD No-Execute Page Protection. */
458#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
459/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
460#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
461/** Bit 23 - MMX - Intel MMX Technology. */
462#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
463/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
464#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
465/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
466#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
467/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
468#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
469/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
470#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
471/** Bit 29 - LM - AMD Long Mode. */
472#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
473/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
474#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
475/** Bit 31 - 3DNOW - AMD 3DNow. */
476#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
477
478/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
479#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
480/** Bit 1 - CMPL - Core multi-processing legacy mode. */
481#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
482/** Bit 2 - SVM - AMD VM extensions. */
483#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
484/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
485#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
486/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
487#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
488/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
489#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
490/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
491#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
492/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
493#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
494/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
495#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
496/** Bit 9 - OSVW - AMD OS visible workaround. */
497#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
498/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
499#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
500/** Bit 13 - WDT - AMD Watchdog timer support. */
501#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
502
503/** @} */
504
505
506/** @name CPUID AMD Feature information.
507 * CPUID query with EAX=0x80000007.
508 * @{
509 */
510/** Bit 0 - TS - Temperature Sensor. */
511#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
512/** Bit 1 - FID - Frequency ID Control. */
513#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
514/** Bit 2 - VID - Voltage ID Control. */
515#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
516/** Bit 3 - TTP - THERMTRIP. */
517#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
518/** Bit 4 - TM - Hardware Thermal Control. */
519#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
520/** Bit 5 - STC - Software Thermal Control. */
521#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
522/** Bit 6 - MC - 100 Mhz Multiplier Control. */
523#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
524/** Bit 7 - HWPSTATE - Hardware P-State Control. */
525#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
526/** Bit 8 - TSCINVAR - TSC Invariant. */
527#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
528/** @} */
529
530
531/** @name CR0
532 * @{ */
533/** Bit 0 - PE - Protection Enabled */
534#define X86_CR0_PE RT_BIT(0)
535#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
536/** Bit 1 - MP - Monitor Coprocessor */
537#define X86_CR0_MP RT_BIT(1)
538#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
539/** Bit 2 - EM - Emulation. */
540#define X86_CR0_EM RT_BIT(2)
541#define X86_CR0_EMULATE_FPU RT_BIT(2)
542/** Bit 3 - TS - Task Switch. */
543#define X86_CR0_TS RT_BIT(3)
544#define X86_CR0_TASK_SWITCH RT_BIT(3)
545/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
546#define X86_CR0_ET RT_BIT(4)
547#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
548/** Bit 5 - NE - Numeric error. */
549#define X86_CR0_NE RT_BIT(5)
550#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
551/** Bit 16 - WP - Write Protect. */
552#define X86_CR0_WP RT_BIT(16)
553#define X86_CR0_WRITE_PROTECT RT_BIT(16)
554/** Bit 18 - AM - Alignment Mask. */
555#define X86_CR0_AM RT_BIT(18)
556#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
557/** Bit 29 - NW - Not Write-though. */
558#define X86_CR0_NW RT_BIT(29)
559#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
560/** Bit 30 - WP - Cache Disable. */
561#define X86_CR0_CD RT_BIT(30)
562#define X86_CR0_CACHE_DISABLE RT_BIT(30)
563/** Bit 31 - PG - Paging. */
564#define X86_CR0_PG RT_BIT(31)
565#define X86_CR0_PAGING RT_BIT(31)
566/** @} */
567
568
569/** @name CR3
570 * @{ */
571/** Bit 3 - PWT - Page-level Writes Transparent. */
572#define X86_CR3_PWT RT_BIT(3)
573/** Bit 4 - PCD - Page-level Cache Disable. */
574#define X86_CR3_PCD RT_BIT(4)
575/** Bits 12-31 - - Page directory page number. */
576#define X86_CR3_PAGE_MASK (0xfffff000)
577/** Bits 5-31 - - PAE Page directory page number. */
578#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
579/** Bits 12-51 - - AMD64 Page directory page number. */
580#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
581/** @} */
582
583
584/** @name CR4
585 * @{ */
586/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
587#define X86_CR4_VME RT_BIT(0)
588/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
589#define X86_CR4_PVI RT_BIT(1)
590/** Bit 2 - TSD - Time Stamp Disable. */
591#define X86_CR4_TSD RT_BIT(2)
592/** Bit 3 - DE - Debugging Extensions. */
593#define X86_CR4_DE RT_BIT(3)
594/** Bit 4 - PSE - Page Size Extension. */
595#define X86_CR4_PSE RT_BIT(4)
596/** Bit 5 - PAE - Physical Address Extension. */
597#define X86_CR4_PAE RT_BIT(5)
598/** Bit 6 - MCE - Machine-Check Enable. */
599#define X86_CR4_MCE RT_BIT(6)
600/** Bit 7 - PGE - Page Global Enable. */
601#define X86_CR4_PGE RT_BIT(7)
602/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
603#define X86_CR4_PCE RT_BIT(8)
604/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
605#define X86_CR4_OSFSXR RT_BIT(9)
606/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
607#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
608/** Bit 13 - VMXE - VMX mode is enabled. */
609#define X86_CR4_VMXE RT_BIT(13)
610/** @} */
611
612
613/** @name DR6
614 * @{ */
615/** Bit 0 - B0 - Breakpoint 0 condition detected. */
616#define X86_DR6_B0 RT_BIT(0)
617/** Bit 1 - B1 - Breakpoint 1 condition detected. */
618#define X86_DR6_B1 RT_BIT(1)
619/** Bit 2 - B2 - Breakpoint 2 condition detected. */
620#define X86_DR6_B2 RT_BIT(2)
621/** Bit 3 - B3 - Breakpoint 3 condition detected. */
622#define X86_DR6_B3 RT_BIT(3)
623/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
624#define X86_DR6_BD RT_BIT(13)
625/** Bit 14 - BS - Single step */
626#define X86_DR6_BS RT_BIT(14)
627/** Bit 15 - BT - Task switch. (TSS T bit.) */
628#define X86_DR6_BT RT_BIT(15)
629/** Value of DR6 after powerup/reset. */
630#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
631/** @} */
632
633
634/** @name DR7
635 * @{ */
636/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
637#define X86_DR7_L0 RT_BIT(0)
638/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
639#define X86_DR7_G0 RT_BIT(1)
640/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
641#define X86_DR7_L1 RT_BIT(2)
642/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
643#define X86_DR7_G1 RT_BIT(3)
644/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
645#define X86_DR7_L2 RT_BIT(4)
646/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
647#define X86_DR7_G2 RT_BIT(5)
648/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
649#define X86_DR7_L3 RT_BIT(6)
650/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
651#define X86_DR7_G3 RT_BIT(7)
652/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
653#define X86_DR7_LE RT_BIT(8)
654/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
655#define X86_DR7_GE RT_BIT(9)
656
657/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
658 * any DR register is accessed. */
659#define X86_DR7_GD RT_BIT(13)
660/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
661#define X86_DR7_RW0_MASK (3 << 16)
662/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
663#define X86_DR7_LEN0_MASK (3 << 18)
664/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
665#define X86_DR7_RW1_MASK (3 << 20)
666/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
667#define X86_DR7_LEN1_MASK (3 << 22)
668/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
669#define X86_DR7_RW2_MASK (3 << 24)
670/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
671#define X86_DR7_LEN2_MASK (3 << 26)
672/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
673#define X86_DR7_RW3_MASK (3 << 28)
674/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
675#define X86_DR7_LEN3_MASK (3 << 30)
676
677/** Bits which must be 1s. */
678#define X86_DR7_MB1_MASK (RT_BIT(10))
679
680/** Calcs the L bit of Nth breakpoint.
681 * @param iBp The breakpoint number [0..3].
682 */
683#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
684
685/** Calcs the G bit of Nth breakpoint.
686 * @param iBp The breakpoint number [0..3].
687 */
688#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
689
690/** @name Read/Write values.
691 * @{ */
692/** Break on instruction fetch only. */
693#define X86_DR7_RW_EO 0U
694/** Break on write only. */
695#define X86_DR7_RW_WO 1U
696/** Break on I/O read/write. This is only defined if CR4.DE is set. */
697#define X86_DR7_RW_IO 2U
698/** Break on read or write (but not instruction fetches). */
699#define X86_DR7_RW_RW 3U
700/** @} */
701
702/** Shifts a X86_DR7_RW_* value to its right place.
703 * @param iBp The breakpoint number [0..3].
704 * @param fRw One of the X86_DR7_RW_* value.
705 */
706#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
707
708/** @name Length values.
709 * @{ */
710#define X86_DR7_LEN_BYTE 0U
711#define X86_DR7_LEN_WORD 1U
712#define X86_DR7_LEN_QWORD 2U /**< AMD64 long mode only. */
713#define X86_DR7_LEN_DWORD 3U
714/** @} */
715
716/** Shifts a X86_DR7_LEN_* value to its right place.
717 * @param iBp The breakpoint number [0..3].
718 * @param cb One of the X86_DR7_LEN_* values.
719 */
720#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
721
722/** Fetch the breakpoint length bits from the DR7 value.
723 * @param uDR7 DR7 value
724 * @param iBp The breakpoint number [0..3].
725 */
726#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
727
728/** Mask used to check if any breakpoints are enabled. */
729#define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
730
731/** Mask used to check if any io breakpoints are set. */
732#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
733
734/** Value of DR7 after powerup/reset. */
735#define X86_DR7_INIT_VAL 0x400
736/** @} */
737
738
739/** @name Machine Specific Registers
740 * @{
741 */
742
743/** Time Stamp Counter. */
744#define MSR_IA32_TSC 0x10
745
746#define MSR_IA32_PLATFORM_ID 0x17
747
748#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
749#define MSR_IA32_APICBASE 0x1b
750#endif
751
752/** CPU Feature control. */
753#define MSR_IA32_FEATURE_CONTROL 0x3A
754#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
755#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
756
757/** BIOS update trigger (microcode update). */
758#define MSR_IA32_BIOS_UPDT_TRIG 0x79
759
760/** BIOS update signature (microcode). */
761#define MSR_IA32_BIOS_SIGN_ID 0x8B
762
763/** MTRR Capabilities. */
764#define MSR_IA32_MTRR_CAP 0xFE
765
766
767#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
768/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
769 * R0 SS == CS + 8
770 * R3 CS == CS + 16
771 * R3 SS == CS + 24
772 */
773#define MSR_IA32_SYSENTER_CS 0x174
774/** SYSENTER_ESP - the R0 ESP. */
775#define MSR_IA32_SYSENTER_ESP 0x175
776/** SYSENTER_EIP - the R0 EIP. */
777#define MSR_IA32_SYSENTER_EIP 0x176
778#endif
779
780/** Machine Check Global Capabilities Register. */
781#define MSR_IA32_MCP_CAP 0x179
782/** Machine Check Global Status Register. */
783#define MSR_IA32_MCP_STATUS 0x17A
784/** Machine Check Global Control Register. */
785#define MSR_IA32_MCP_CTRL 0x17B
786
787/* Page Attribute Table. */
788#define MSR_IA32_CR_PAT 0x277
789
790/** MTRR Default Range. */
791#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
792
793#define MSR_IA32_MC0_CTL 0x400
794#define MSR_IA32_MC0_STATUS 0x401
795
796/** Basic VMX information. */
797#define MSR_IA32_VMX_BASIC_INFO 0x480
798/** Allowed settings for pin-based VM execution controls */
799#define MSR_IA32_VMX_PINBASED_CTLS 0x481
800/** Allowed settings for proc-based VM execution controls */
801#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
802/** Allowed settings for the VMX exit controls. */
803#define MSR_IA32_VMX_EXIT_CTLS 0x483
804/** Allowed settings for the VMX entry controls. */
805#define MSR_IA32_VMX_ENTRY_CTLS 0x484
806/** Misc VMX info. */
807#define MSR_IA32_VMX_MISC 0x485
808/** Fixed cleared bits in CR0. */
809#define MSR_IA32_VMX_CR0_FIXED0 0x486
810/** Fixed set bits in CR0. */
811#define MSR_IA32_VMX_CR0_FIXED1 0x487
812/** Fixed cleared bits in CR4. */
813#define MSR_IA32_VMX_CR4_FIXED0 0x488
814/** Fixed set bits in CR4. */
815#define MSR_IA32_VMX_CR4_FIXED1 0x489
816/** Information for enumerating fields in the VMCS. */
817#define MSR_IA32_VMX_VMCS_ENUM 0x48A
818/** Allowed settings for secondary proc-based VM execution controls */
819#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
820/** EPT capabilities. */
821#define MSR_IA32_VMX_EPT_CAPS 0x48C
822/** X2APIC MSR ranges. */
823#define MSR_IA32_APIC_START 0x800
824#define MSR_IA32_APIC_END 0x900
825
826/** K6 EFER - Extended Feature Enable Register. */
827#define MSR_K6_EFER 0xc0000080
828/** @todo document EFER */
829/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
830#define MSR_K6_EFER_SCE RT_BIT(0)
831/** Bit 8 - LME - Long mode enabled. (R/W) */
832#define MSR_K6_EFER_LME RT_BIT(8)
833/** Bit 10 - LMA - Long mode active. (R) */
834#define MSR_K6_EFER_LMA RT_BIT(10)
835/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
836#define MSR_K6_EFER_NXE RT_BIT(11)
837/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
838#define MSR_K6_EFER_SVME RT_BIT(12)
839/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
840#define MSR_K6_EFER_LMSLE RT_BIT(13)
841/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
842#define MSR_K6_EFER_FFXSR RT_BIT(14)
843/** K6 STAR - SYSCALL/RET targets. */
844#define MSR_K6_STAR 0xc0000081
845/** Shift value for getting the SYSRET CS and SS value. */
846#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
847/** Shift value for getting the SYSCALL CS and SS value. */
848#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
849/** Selector mask for use after shifting. */
850#define MSR_K6_STAR_SEL_MASK 0xffff
851/** The mask which give the SYSCALL EIP. */
852#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
853/** K6 WHCR - Write Handling Control Register. */
854#define MSR_K6_WHCR 0xc0000082
855/** K6 UWCCR - UC/WC Cacheability Control Register. */
856#define MSR_K6_UWCCR 0xc0000085
857/** K6 PSOR - Processor State Observability Register. */
858#define MSR_K6_PSOR 0xc0000087
859/** K6 PFIR - Page Flush/Invalidate Register. */
860#define MSR_K6_PFIR 0xc0000088
861
862#define MSR_K7_EVNTSEL0 0xc0010000
863#define MSR_K7_EVNTSEL1 0xc0010001
864#define MSR_K7_EVNTSEL2 0xc0010002
865#define MSR_K7_EVNTSEL3 0xc0010003
866#define MSR_K7_PERFCTR0 0xc0010004
867#define MSR_K7_PERFCTR1 0xc0010005
868#define MSR_K7_PERFCTR2 0xc0010006
869#define MSR_K7_PERFCTR3 0xc0010007
870
871/** K8 LSTAR - Long mode SYSCALL target (RIP). */
872#define MSR_K8_LSTAR 0xc0000082
873/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
874#define MSR_K8_CSTAR 0xc0000083
875/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
876#define MSR_K8_SF_MASK 0xc0000084
877/** K8 FS.base - The 64-bit base FS register. */
878#define MSR_K8_FS_BASE 0xc0000100
879/** K8 GS.base - The 64-bit base GS register. */
880#define MSR_K8_GS_BASE 0xc0000101
881/** K8 KernelGSbase - Used with SWAPGS. */
882#define MSR_K8_KERNEL_GS_BASE 0xc0000102
883#define MSR_K8_TSC_AUX 0xc0000103
884#define MSR_K8_SYSCFG 0xc0010010
885#define MSR_K8_HWCR 0xc0010015
886#define MSR_K8_IORRBASE0 0xc0010016
887#define MSR_K8_IORRMASK0 0xc0010017
888#define MSR_K8_IORRBASE1 0xc0010018
889#define MSR_K8_IORRMASK1 0xc0010019
890#define MSR_K8_TOP_MEM1 0xc001001a
891#define MSR_K8_TOP_MEM2 0xc001001d
892#define MSR_K8_VM_CR 0xc0010114
893#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
894
895#define MSR_K8_IGNNE 0xc0010115
896#define MSR_K8_SMM_CTL 0xc0010116
897/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
898 * host state during world switch.
899 */
900#define MSR_K8_VM_HSAVE_PA 0xc0010117
901
902/** @} */
903
904
905/** @name Page Table / Directory / Directory Pointers / L4.
906 * @{
907 */
908
909/** Page table/directory entry as an unsigned integer. */
910typedef uint32_t X86PGUINT;
911/** Pointer to a page table/directory table entry as an unsigned integer. */
912typedef X86PGUINT *PX86PGUINT;
913
914/** Number of entries in a 32-bit PT/PD. */
915#define X86_PG_ENTRIES 1024
916
917
918/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
919typedef uint64_t X86PGPAEUINT;
920/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
921typedef X86PGPAEUINT *PX86PGPAEUINT;
922
923/** Number of entries in a PAE PT/PD. */
924#define X86_PG_PAE_ENTRIES 512
925/** Number of entries in a PAE PDPT. */
926#define X86_PG_PAE_PDPE_ENTRIES 4
927
928/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
929#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
930/** Number of entries in an AMD64 PDPT.
931 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
932#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
933
934/** The size of a 4KB page. */
935#define X86_PAGE_4K_SIZE _4K
936/** The page shift of a 4KB page. */
937#define X86_PAGE_4K_SHIFT 12
938/** The 4KB page offset mask. */
939#define X86_PAGE_4K_OFFSET_MASK 0xfff
940/** The 4KB page base mask for virtual addresses. */
941#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
942/** The 4KB page base mask for virtual addresses - 32bit version. */
943#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
944
945/** The size of a 2MB page. */
946#define X86_PAGE_2M_SIZE _2M
947/** The page shift of a 2MB page. */
948#define X86_PAGE_2M_SHIFT 21
949/** The 2MB page offset mask. */
950#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
951/** The 2MB page base mask for virtual addresses. */
952#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
953/** The 2MB page base mask for virtual addresses - 32bit version. */
954#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
955
956/** The size of a 4MB page. */
957#define X86_PAGE_4M_SIZE _4M
958/** The page shift of a 4MB page. */
959#define X86_PAGE_4M_SHIFT 22
960/** The 4MB page offset mask. */
961#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
962/** The 4MB page base mask for virtual addresses. */
963#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
964/** The 4MB page base mask for virtual addresses - 32bit version. */
965#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
966
967
968
969/** @name Page Table Entry
970 * @{
971 */
972/** Bit 0 - P - Present bit. */
973#define X86_PTE_BIT_P 0
974/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
975#define X86_PTE_BIT_RW 1)
976/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
977#define X86_PTE_BIT_US 2
978/** Bit 3 - PWT - Page level write thru bit. */
979#define X86_PTE_BIT_PWT 3
980/** Bit 4 - PCD - Page level cache disable bit. */
981#define X86_PTE_BIT_PCD 4
982/** Bit 5 - A - Access bit. */
983#define X86_PTE_BIT_A 5
984/** Bit 6 - D - Dirty bit. */
985#define X86_PTE_BIT_D 6
986/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
987#define X86_PTE_BIT_PAT 7
988/** Bit 8 - G - Global flag. */
989#define X86_PTE_BIT_G 8
990
991/** Bit 0 - P - Present bit mask. */
992#define X86_PTE_P RT_BIT(0)
993/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
994#define X86_PTE_RW RT_BIT(1)
995/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
996#define X86_PTE_US RT_BIT(2)
997/** Bit 3 - PWT - Page level write thru bit mask. */
998#define X86_PTE_PWT RT_BIT(3)
999/** Bit 4 - PCD - Page level cache disable bit mask. */
1000#define X86_PTE_PCD RT_BIT(4)
1001/** Bit 5 - A - Access bit mask. */
1002#define X86_PTE_A RT_BIT(5)
1003/** Bit 6 - D - Dirty bit mask. */
1004#define X86_PTE_D RT_BIT(6)
1005/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1006#define X86_PTE_PAT RT_BIT(7)
1007/** Bit 8 - G - Global bit mask. */
1008#define X86_PTE_G RT_BIT(8)
1009
1010/** Bits 9-11 - - Available for use to system software. */
1011#define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1012/** Bits 12-31 - - Physical Page number of the next level. */
1013#define X86_PTE_PG_MASK ( 0xfffff000 )
1014
1015/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1016#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1017#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1018/** @todo Get rid of the above hack; makes code unreadable. */
1019#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1020#else
1021#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1022#endif
1023/** Bits 63 - NX - PAE - No execution flag. */
1024#define X86_PTE_PAE_NX RT_BIT_64(63)
1025
1026/**
1027 * Page table entry.
1028 */
1029typedef struct X86PTEBITS
1030{
1031 /** Flags whether(=1) or not the page is present. */
1032 unsigned u1Present : 1;
1033 /** Read(=0) / Write(=1) flag. */
1034 unsigned u1Write : 1;
1035 /** User(=1) / Supervisor (=0) flag. */
1036 unsigned u1User : 1;
1037 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1038 unsigned u1WriteThru : 1;
1039 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1040 unsigned u1CacheDisable : 1;
1041 /** Accessed flag.
1042 * Indicates that the page have been read or written to. */
1043 unsigned u1Accessed : 1;
1044 /** Dirty flag.
1045 * Indicates that the page have been written to. */
1046 unsigned u1Dirty : 1;
1047 /** Reserved / If PAT enabled, bit 2 of the index. */
1048 unsigned u1PAT : 1;
1049 /** Global flag. (Ignored in all but final level.) */
1050 unsigned u1Global : 1;
1051 /** Available for use to system software. */
1052 unsigned u3Available : 3;
1053 /** Physical Page number of the next level. */
1054 unsigned u20PageNo : 20;
1055} X86PTEBITS;
1056/** Pointer to a page table entry. */
1057typedef X86PTEBITS *PX86PTEBITS;
1058/** Pointer to a const page table entry. */
1059typedef const X86PTEBITS *PCX86PTEBITS;
1060
1061/**
1062 * Page table entry.
1063 */
1064typedef union X86PTE
1065{
1066 /** Unsigned integer view */
1067 X86PGUINT u;
1068 /** Bit field view. */
1069 X86PTEBITS n;
1070 /** 32-bit view. */
1071 uint32_t au32[1];
1072 /** 16-bit view. */
1073 uint16_t au16[2];
1074 /** 8-bit view. */
1075 uint8_t au8[4];
1076} X86PTE;
1077/** Pointer to a page table entry. */
1078typedef X86PTE *PX86PTE;
1079/** Pointer to a const page table entry. */
1080typedef const X86PTE *PCX86PTE;
1081
1082
1083/**
1084 * PAE page table entry.
1085 */
1086typedef struct X86PTEPAEBITS
1087{
1088 /** Flags whether(=1) or not the page is present. */
1089 uint32_t u1Present : 1;
1090 /** Read(=0) / Write(=1) flag. */
1091 uint32_t u1Write : 1;
1092 /** User(=1) / Supervisor(=0) flag. */
1093 uint32_t u1User : 1;
1094 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1095 uint32_t u1WriteThru : 1;
1096 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1097 uint32_t u1CacheDisable : 1;
1098 /** Accessed flag.
1099 * Indicates that the page have been read or written to. */
1100 uint32_t u1Accessed : 1;
1101 /** Dirty flag.
1102 * Indicates that the page have been written to. */
1103 uint32_t u1Dirty : 1;
1104 /** Reserved / If PAT enabled, bit 2 of the index. */
1105 uint32_t u1PAT : 1;
1106 /** Global flag. (Ignored in all but final level.) */
1107 uint32_t u1Global : 1;
1108 /** Available for use to system software. */
1109 uint32_t u3Available : 3;
1110 /** Physical Page number of the next level - Low Part. Don't use this. */
1111 uint32_t u20PageNoLow : 20;
1112 /** Physical Page number of the next level - High Part. Don't use this. */
1113 uint32_t u20PageNoHigh : 20;
1114 /** MBZ bits */
1115 uint32_t u11Reserved : 11;
1116 /** No Execute flag. */
1117 uint32_t u1NoExecute : 1;
1118} X86PTEPAEBITS;
1119/** Pointer to a page table entry. */
1120typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1121/** Pointer to a page table entry. */
1122typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1123
1124/**
1125 * PAE Page table entry.
1126 */
1127typedef union X86PTEPAE
1128{
1129 /** Unsigned integer view */
1130 X86PGPAEUINT u;
1131 /** Bit field view. */
1132 X86PTEPAEBITS n;
1133 /** 32-bit view. */
1134 uint32_t au32[2];
1135 /** 16-bit view. */
1136 uint16_t au16[4];
1137 /** 8-bit view. */
1138 uint8_t au8[8];
1139} X86PTEPAE;
1140/** Pointer to a PAE page table entry. */
1141typedef X86PTEPAE *PX86PTEPAE;
1142/** Pointer to a const PAE page table entry. */
1143typedef const X86PTEPAE *PCX86PTEPAE;
1144/** @} */
1145
1146/**
1147 * Page table.
1148 */
1149typedef struct X86PT
1150{
1151 /** PTE Array. */
1152 X86PTE a[X86_PG_ENTRIES];
1153} X86PT;
1154/** Pointer to a page table. */
1155typedef X86PT *PX86PT;
1156/** Pointer to a const page table. */
1157typedef const X86PT *PCX86PT;
1158
1159/** The page shift to get the PT index. */
1160#define X86_PT_SHIFT 12
1161/** The PT index mask (apply to a shifted page address). */
1162#define X86_PT_MASK 0x3ff
1163
1164
1165/**
1166 * Page directory.
1167 */
1168typedef struct X86PTPAE
1169{
1170 /** PTE Array. */
1171 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1172} X86PTPAE;
1173/** Pointer to a page table. */
1174typedef X86PTPAE *PX86PTPAE;
1175/** Pointer to a const page table. */
1176typedef const X86PTPAE *PCX86PTPAE;
1177
1178/** The page shift to get the PA PTE index. */
1179#define X86_PT_PAE_SHIFT 12
1180/** The PAE PT index mask (apply to a shifted page address). */
1181#define X86_PT_PAE_MASK 0x1ff
1182
1183
1184/** @name 4KB Page Directory Entry
1185 * @{
1186 */
1187/** Bit 0 - P - Present bit. */
1188#define X86_PDE_P RT_BIT(0)
1189/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1190#define X86_PDE_RW RT_BIT(1)
1191/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1192#define X86_PDE_US RT_BIT(2)
1193/** Bit 3 - PWT - Page level write thru bit. */
1194#define X86_PDE_PWT RT_BIT(3)
1195/** Bit 4 - PCD - Page level cache disable bit. */
1196#define X86_PDE_PCD RT_BIT(4)
1197/** Bit 5 - A - Access bit. */
1198#define X86_PDE_A RT_BIT(5)
1199/** Bit 7 - PS - Page size attribute.
1200 * Clear mean 4KB pages, set means large pages (2/4MB). */
1201#define X86_PDE_PS RT_BIT(7)
1202/** Bits 9-11 - - Available for use to system software. */
1203#define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1204/** Bits 12-31 - - Physical Page number of the next level. */
1205#define X86_PDE_PG_MASK ( 0xfffff000 )
1206
1207/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1208#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1209/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1210 * we partly or that part into shadow page table entries. Will be corrected
1211 * soon.
1212 */
1213#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1214#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1215#else
1216#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1217#endif
1218/** Bits 63 - NX - PAE - No execution flag. */
1219#define X86_PDE_PAE_NX RT_BIT_64(63)
1220
1221/**
1222 * Page directory entry.
1223 */
1224typedef struct X86PDEBITS
1225{
1226 /** Flags whether(=1) or not the page is present. */
1227 unsigned u1Present : 1;
1228 /** Read(=0) / Write(=1) flag. */
1229 unsigned u1Write : 1;
1230 /** User(=1) / Supervisor (=0) flag. */
1231 unsigned u1User : 1;
1232 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1233 unsigned u1WriteThru : 1;
1234 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1235 unsigned u1CacheDisable : 1;
1236 /** Accessed flag.
1237 * Indicates that the page have been read or written to. */
1238 unsigned u1Accessed : 1;
1239 /** Reserved / Ignored (dirty bit). */
1240 unsigned u1Reserved0 : 1;
1241 /** Size bit if PSE is enabled - in any event it's 0. */
1242 unsigned u1Size : 1;
1243 /** Reserved / Ignored (global bit). */
1244 unsigned u1Reserved1 : 1;
1245 /** Available for use to system software. */
1246 unsigned u3Available : 3;
1247 /** Physical Page number of the next level. */
1248 unsigned u20PageNo : 20;
1249} X86PDEBITS;
1250/** Pointer to a page directory entry. */
1251typedef X86PDEBITS *PX86PDEBITS;
1252/** Pointer to a const page directory entry. */
1253typedef const X86PDEBITS *PCX86PDEBITS;
1254
1255
1256/**
1257 * PAE page directory entry.
1258 */
1259typedef struct X86PDEPAEBITS
1260{
1261 /** Flags whether(=1) or not the page is present. */
1262 uint32_t u1Present : 1;
1263 /** Read(=0) / Write(=1) flag. */
1264 uint32_t u1Write : 1;
1265 /** User(=1) / Supervisor (=0) flag. */
1266 uint32_t u1User : 1;
1267 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1268 uint32_t u1WriteThru : 1;
1269 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1270 uint32_t u1CacheDisable : 1;
1271 /** Accessed flag.
1272 * Indicates that the page have been read or written to. */
1273 uint32_t u1Accessed : 1;
1274 /** Reserved / Ignored (dirty bit). */
1275 uint32_t u1Reserved0 : 1;
1276 /** Size bit if PSE is enabled - in any event it's 0. */
1277 uint32_t u1Size : 1;
1278 /** Reserved / Ignored (global bit). / */
1279 uint32_t u1Reserved1 : 1;
1280 /** Available for use to system software. */
1281 uint32_t u3Available : 3;
1282 /** Physical Page number of the next level - Low Part. Don't use! */
1283 uint32_t u20PageNoLow : 20;
1284 /** Physical Page number of the next level - High Part. Don't use! */
1285 uint32_t u20PageNoHigh : 20;
1286 /** MBZ bits */
1287 uint32_t u11Reserved : 11;
1288 /** No Execute flag. */
1289 uint32_t u1NoExecute : 1;
1290} X86PDEPAEBITS;
1291/** Pointer to a page directory entry. */
1292typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1293/** Pointer to a const page directory entry. */
1294typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1295
1296/** @} */
1297
1298
1299/** @name 2/4MB Page Directory Entry
1300 * @{
1301 */
1302/** Bit 0 - P - Present bit. */
1303#define X86_PDE4M_P RT_BIT(0)
1304/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1305#define X86_PDE4M_RW RT_BIT(1)
1306/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1307#define X86_PDE4M_US RT_BIT(2)
1308/** Bit 3 - PWT - Page level write thru bit. */
1309#define X86_PDE4M_PWT RT_BIT(3)
1310/** Bit 4 - PCD - Page level cache disable bit. */
1311#define X86_PDE4M_PCD RT_BIT(4)
1312/** Bit 5 - A - Access bit. */
1313#define X86_PDE4M_A RT_BIT(5)
1314/** Bit 6 - D - Dirty bit. */
1315#define X86_PDE4M_D RT_BIT(6)
1316/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1317#define X86_PDE4M_PS RT_BIT(7)
1318/** Bit 8 - G - Global flag. */
1319#define X86_PDE4M_G RT_BIT(8)
1320/** Bits 9-11 - AVL - Available for use to system software. */
1321#define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1322/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1323#define X86_PDE4M_PAT RT_BIT(12)
1324/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1325#define X86_PDE4M_PAT_SHIFT (12 - 7)
1326/** Bits 22-31 - - Physical Page number. */
1327#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1328/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1329#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1330/** The number of bits to the high part of the page number. */
1331#define X86_PDE4M_PG_HIGH_SHIFT 19
1332
1333/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1334 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1335#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1336/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1337#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1338
1339/**
1340 * 4MB page directory entry.
1341 */
1342typedef struct X86PDE4MBITS
1343{
1344 /** Flags whether(=1) or not the page is present. */
1345 unsigned u1Present : 1;
1346 /** Read(=0) / Write(=1) flag. */
1347 unsigned u1Write : 1;
1348 /** User(=1) / Supervisor (=0) flag. */
1349 unsigned u1User : 1;
1350 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1351 unsigned u1WriteThru : 1;
1352 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1353 unsigned u1CacheDisable : 1;
1354 /** Accessed flag.
1355 * Indicates that the page have been read or written to. */
1356 unsigned u1Accessed : 1;
1357 /** Dirty flag.
1358 * Indicates that the page have been written to. */
1359 unsigned u1Dirty : 1;
1360 /** Page size flag - always 1 for 4MB entries. */
1361 unsigned u1Size : 1;
1362 /** Global flag. */
1363 unsigned u1Global : 1;
1364 /** Available for use to system software. */
1365 unsigned u3Available : 3;
1366 /** Reserved / If PAT enabled, bit 2 of the index. */
1367 unsigned u1PAT : 1;
1368 /** Bits 32-39 of the page number on AMD64.
1369 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1370 unsigned u8PageNoHigh : 8;
1371 /** Reserved. */
1372 unsigned u1Reserved : 1;
1373 /** Physical Page number of the page. */
1374 unsigned u10PageNo : 10;
1375} X86PDE4MBITS;
1376/** Pointer to a page table entry. */
1377typedef X86PDE4MBITS *PX86PDE4MBITS;
1378/** Pointer to a const page table entry. */
1379typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1380
1381
1382/**
1383 * 2MB PAE page directory entry.
1384 */
1385typedef struct X86PDE2MPAEBITS
1386{
1387 /** Flags whether(=1) or not the page is present. */
1388 uint32_t u1Present : 1;
1389 /** Read(=0) / Write(=1) flag. */
1390 uint32_t u1Write : 1;
1391 /** User(=1) / Supervisor(=0) flag. */
1392 uint32_t u1User : 1;
1393 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1394 uint32_t u1WriteThru : 1;
1395 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1396 uint32_t u1CacheDisable : 1;
1397 /** Accessed flag.
1398 * Indicates that the page have been read or written to. */
1399 uint32_t u1Accessed : 1;
1400 /** Dirty flag.
1401 * Indicates that the page have been written to. */
1402 uint32_t u1Dirty : 1;
1403 /** Page size flag - always 1 for 2MB entries. */
1404 uint32_t u1Size : 1;
1405 /** Global flag. */
1406 uint32_t u1Global : 1;
1407 /** Available for use to system software. */
1408 uint32_t u3Available : 3;
1409 /** Reserved / If PAT enabled, bit 2 of the index. */
1410 uint32_t u1PAT : 1;
1411 /** Reserved. */
1412 uint32_t u9Reserved : 9;
1413 /** Physical Page number of the next level - Low part. Don't use! */
1414 uint32_t u10PageNoLow : 10;
1415 /** Physical Page number of the next level - High part. Don't use! */
1416 uint32_t u20PageNoHigh : 20;
1417 /** MBZ bits */
1418 uint32_t u11Reserved : 11;
1419 /** No Execute flag. */
1420 uint32_t u1NoExecute : 1;
1421} X86PDE2MPAEBITS;
1422/** Pointer to a 4MB PAE page table entry. */
1423typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1424/** Pointer to a 4MB PAE page table entry. */
1425typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1426
1427/** @} */
1428
1429/**
1430 * Page directory entry.
1431 */
1432typedef union X86PDE
1433{
1434 /** Unsigned integer view. */
1435 X86PGUINT u;
1436 /** Normal view. */
1437 X86PDEBITS n;
1438 /** 4MB view (big). */
1439 X86PDE4MBITS b;
1440 /** 8 bit unsigned integer view. */
1441 uint8_t au8[4];
1442 /** 16 bit unsigned integer view. */
1443 uint16_t au16[2];
1444 /** 32 bit unsigned integer view. */
1445 uint32_t au32[1];
1446} X86PDE;
1447/** Pointer to a page directory entry. */
1448typedef X86PDE *PX86PDE;
1449/** Pointer to a const page directory entry. */
1450typedef const X86PDE *PCX86PDE;
1451
1452/**
1453 * PAE page directory entry.
1454 */
1455typedef union X86PDEPAE
1456{
1457 /** Unsigned integer view. */
1458 X86PGPAEUINT u;
1459 /** Normal view. */
1460 X86PDEPAEBITS n;
1461 /** 2MB page view (big). */
1462 X86PDE2MPAEBITS b;
1463 /** 8 bit unsigned integer view. */
1464 uint8_t au8[8];
1465 /** 16 bit unsigned integer view. */
1466 uint16_t au16[4];
1467 /** 32 bit unsigned integer view. */
1468 uint32_t au32[2];
1469} X86PDEPAE;
1470/** Pointer to a page directory entry. */
1471typedef X86PDEPAE *PX86PDEPAE;
1472/** Pointer to a const page directory entry. */
1473typedef const X86PDEPAE *PCX86PDEPAE;
1474
1475/**
1476 * Page directory.
1477 */
1478typedef struct X86PD
1479{
1480 /** PDE Array. */
1481 X86PDE a[X86_PG_ENTRIES];
1482} X86PD;
1483/** Pointer to a page directory. */
1484typedef X86PD *PX86PD;
1485/** Pointer to a const page directory. */
1486typedef const X86PD *PCX86PD;
1487
1488/** The page shift to get the PD index. */
1489#define X86_PD_SHIFT 22
1490/** The PD index mask (apply to a shifted page address). */
1491#define X86_PD_MASK 0x3ff
1492
1493
1494/**
1495 * PAE page directory.
1496 */
1497typedef struct X86PDPAE
1498{
1499 /** PDE Array. */
1500 X86PDEPAE a[X86_PG_PAE_ENTRIES];
1501} X86PDPAE;
1502/** Pointer to a PAE page directory. */
1503typedef X86PDPAE *PX86PDPAE;
1504/** Pointer to a const PAE page directory. */
1505typedef const X86PDPAE *PCX86PDPAE;
1506
1507/** The page shift to get the PAE PD index. */
1508#define X86_PD_PAE_SHIFT 21
1509/** The PAE PD index mask (apply to a shifted page address). */
1510#define X86_PD_PAE_MASK 0x1ff
1511
1512
1513/** @name Page Directory Pointer Table Entry (PAE)
1514 * @{
1515 */
1516/** Bit 0 - P - Present bit. */
1517#define X86_PDPE_P RT_BIT(0)
1518/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1519#define X86_PDPE_RW RT_BIT(1)
1520/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1521#define X86_PDPE_US RT_BIT(2)
1522/** Bit 3 - PWT - Page level write thru bit. */
1523#define X86_PDPE_PWT RT_BIT(3)
1524/** Bit 4 - PCD - Page level cache disable bit. */
1525#define X86_PDPE_PCD RT_BIT(4)
1526/** Bit 5 - A - Access bit. Long Mode only. */
1527#define X86_PDPE_A RT_BIT(5)
1528/** Bits 9-11 - - Available for use to system software. */
1529#define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1530/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1531#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1532#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1533/** @todo Get rid of the above hack; makes code unreadable. */
1534#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1535#else
1536#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1537#endif
1538/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1539#define X86_PDPE_NX RT_BIT_64(63)
1540
1541/**
1542 * Page directory pointer table entry.
1543 */
1544typedef struct X86PDPEBITS
1545{
1546 /** Flags whether(=1) or not the page is present. */
1547 uint32_t u1Present : 1;
1548 /** Chunk of reserved bits. */
1549 uint32_t u2Reserved : 2;
1550 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1551 uint32_t u1WriteThru : 1;
1552 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1553 uint32_t u1CacheDisable : 1;
1554 /** Chunk of reserved bits. */
1555 uint32_t u4Reserved : 4;
1556 /** Available for use to system software. */
1557 uint32_t u3Available : 3;
1558 /** Physical Page number of the next level - Low Part. Don't use! */
1559 uint32_t u20PageNoLow : 20;
1560 /** Physical Page number of the next level - High Part. Don't use! */
1561 uint32_t u20PageNoHigh : 20;
1562 /** MBZ bits */
1563 uint32_t u12Reserved : 12;
1564} X86PDPEBITS;
1565/** Pointer to a page directory pointer table entry. */
1566typedef X86PDPEBITS *PX86PTPEBITS;
1567/** Pointer to a const page directory pointer table entry. */
1568typedef const X86PDPEBITS *PCX86PTPEBITS;
1569
1570/**
1571 * Page directory pointer table entry. AMD64 version
1572 */
1573typedef struct X86PDPEAMD64BITS
1574{
1575 /** Flags whether(=1) or not the page is present. */
1576 uint32_t u1Present : 1;
1577 /** Read(=0) / Write(=1) flag. */
1578 uint32_t u1Write : 1;
1579 /** User(=1) / Supervisor (=0) flag. */
1580 uint32_t u1User : 1;
1581 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1582 uint32_t u1WriteThru : 1;
1583 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1584 uint32_t u1CacheDisable : 1;
1585 /** Accessed flag.
1586 * Indicates that the page have been read or written to. */
1587 uint32_t u1Accessed : 1;
1588 /** Chunk of reserved bits. */
1589 uint32_t u3Reserved : 3;
1590 /** Available for use to system software. */
1591 uint32_t u3Available : 3;
1592 /** Physical Page number of the next level - Low Part. Don't use! */
1593 uint32_t u20PageNoLow : 20;
1594 /** Physical Page number of the next level - High Part. Don't use! */
1595 uint32_t u20PageNoHigh : 20;
1596 /** MBZ bits */
1597 uint32_t u11Reserved : 11;
1598 /** No Execute flag. */
1599 uint32_t u1NoExecute : 1;
1600} X86PDPEAMD64BITS;
1601/** Pointer to a page directory pointer table entry. */
1602typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1603/** Pointer to a const page directory pointer table entry. */
1604typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1605
1606/**
1607 * Page directory pointer table entry.
1608 */
1609typedef union X86PDPE
1610{
1611 /** Unsigned integer view. */
1612 X86PGPAEUINT u;
1613 /** Normal view. */
1614 X86PDPEBITS n;
1615 /** AMD64 view. */
1616 X86PDPEAMD64BITS lm;
1617 /** 8 bit unsigned integer view. */
1618 uint8_t au8[8];
1619 /** 16 bit unsigned integer view. */
1620 uint16_t au16[4];
1621 /** 32 bit unsigned integer view. */
1622 uint32_t au32[2];
1623} X86PDPE;
1624/** Pointer to a page directory pointer table entry. */
1625typedef X86PDPE *PX86PDPE;
1626/** Pointer to a const page directory pointer table entry. */
1627typedef const X86PDPE *PCX86PDPE;
1628
1629
1630/**
1631 * Page directory pointer table.
1632 */
1633typedef struct X86PDPT
1634{
1635 /** PDE Array. */
1636 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1637} X86PDPT;
1638/** Pointer to a page directory pointer table. */
1639typedef X86PDPT *PX86PDPT;
1640/** Pointer to a const page directory pointer table. */
1641typedef const X86PDPT *PCX86PDPT;
1642
1643/** The page shift to get the PDPT index. */
1644#define X86_PDPT_SHIFT 30
1645/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1646#define X86_PDPT_MASK_PAE 0x3
1647/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1648#define X86_PDPT_MASK_AMD64 0x1ff
1649
1650/** @} */
1651
1652
1653/** @name Page Map Level-4 Entry (Long Mode PAE)
1654 * @{
1655 */
1656/** Bit 0 - P - Present bit. */
1657#define X86_PML4E_P RT_BIT(0)
1658/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1659#define X86_PML4E_RW RT_BIT(1)
1660/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1661#define X86_PML4E_US RT_BIT(2)
1662/** Bit 3 - PWT - Page level write thru bit. */
1663#define X86_PML4E_PWT RT_BIT(3)
1664/** Bit 4 - PCD - Page level cache disable bit. */
1665#define X86_PML4E_PCD RT_BIT(4)
1666/** Bit 5 - A - Access bit. */
1667#define X86_PML4E_A RT_BIT(5)
1668/** Bits 9-11 - - Available for use to system software. */
1669#define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
1670/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1671#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1672#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1673#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1674#else
1675#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1676#endif
1677/** Bits 63 - NX - PAE - No execution flag. */
1678#define X86_PML4E_NX RT_BIT_64(63)
1679
1680/**
1681 * Page Map Level-4 Entry
1682 */
1683typedef struct X86PML4EBITS
1684{
1685 /** Flags whether(=1) or not the page is present. */
1686 uint32_t u1Present : 1;
1687 /** Read(=0) / Write(=1) flag. */
1688 uint32_t u1Write : 1;
1689 /** User(=1) / Supervisor (=0) flag. */
1690 uint32_t u1User : 1;
1691 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1692 uint32_t u1WriteThru : 1;
1693 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1694 uint32_t u1CacheDisable : 1;
1695 /** Accessed flag.
1696 * Indicates that the page have been read or written to. */
1697 uint32_t u1Accessed : 1;
1698 /** Chunk of reserved bits. */
1699 uint32_t u3Reserved : 3;
1700 /** Available for use to system software. */
1701 uint32_t u3Available : 3;
1702 /** Physical Page number of the next level - Low Part. Don't use! */
1703 uint32_t u20PageNoLow : 20;
1704 /** Physical Page number of the next level - High Part. Don't use! */
1705 uint32_t u20PageNoHigh : 20;
1706 /** MBZ bits */
1707 uint32_t u11Reserved : 11;
1708 /** No Execute flag. */
1709 uint32_t u1NoExecute : 1;
1710} X86PML4EBITS;
1711/** Pointer to a page map level-4 entry. */
1712typedef X86PML4EBITS *PX86PML4EBITS;
1713/** Pointer to a const page map level-4 entry. */
1714typedef const X86PML4EBITS *PCX86PML4EBITS;
1715
1716/**
1717 * Page Map Level-4 Entry.
1718 */
1719typedef union X86PML4E
1720{
1721 /** Unsigned integer view. */
1722 X86PGPAEUINT u;
1723 /** Normal view. */
1724 X86PML4EBITS n;
1725 /** 8 bit unsigned integer view. */
1726 uint8_t au8[8];
1727 /** 16 bit unsigned integer view. */
1728 uint16_t au16[4];
1729 /** 32 bit unsigned integer view. */
1730 uint32_t au32[2];
1731} X86PML4E;
1732/** Pointer to a page map level-4 entry. */
1733typedef X86PML4E *PX86PML4E;
1734/** Pointer to a const page map level-4 entry. */
1735typedef const X86PML4E *PCX86PML4E;
1736
1737
1738/**
1739 * Page Map Level-4.
1740 */
1741typedef struct X86PML4
1742{
1743 /** PDE Array. */
1744 X86PML4E a[X86_PG_PAE_ENTRIES];
1745} X86PML4;
1746/** Pointer to a page map level-4. */
1747typedef X86PML4 *PX86PML4;
1748/** Pointer to a const page map level-4. */
1749typedef const X86PML4 *PCX86PML4;
1750
1751/** The page shift to get the PML4 index. */
1752#define X86_PML4_SHIFT 39
1753/** The PML4 index mask (apply to a shifted page address). */
1754#define X86_PML4_MASK 0x1ff
1755
1756/** @} */
1757
1758/** @} */
1759
1760
1761/**
1762 * 80-bit MMX/FPU register type.
1763 */
1764typedef struct X86FPUMMX
1765{
1766 uint8_t reg[10];
1767} X86FPUMMX;
1768/** Pointer to a 80-bit MMX/FPU register type. */
1769typedef X86FPUMMX *PX86FPUMMX;
1770/** Pointer to a const 80-bit MMX/FPU register type. */
1771typedef const X86FPUMMX *PCX86FPUMMX;
1772
1773/**
1774 * FPU state (aka FSAVE/FRSTOR Memory Region).
1775 */
1776#pragma pack(1)
1777typedef struct X86FPUSTATE
1778{
1779 /** Control word. */
1780 uint16_t FCW;
1781 /** Alignment word */
1782 uint16_t Dummy1;
1783 /** Status word. */
1784 uint16_t FSW;
1785 /** Alignment word */
1786 uint16_t Dummy2;
1787 /** Tag word */
1788 uint16_t FTW;
1789 /** Alignment word */
1790 uint16_t Dummy3;
1791
1792 /** Instruction pointer. */
1793 uint32_t FPUIP;
1794 /** Code selector. */
1795 uint16_t CS;
1796 /** Opcode. */
1797 uint16_t FOP;
1798 /** FOO. */
1799 uint32_t FPUOO;
1800 /** FOS. */
1801 uint32_t FPUOS;
1802 /** FPU view - todo. */
1803 X86FPUMMX regs[8];
1804} X86FPUSTATE;
1805#pragma pack()
1806/** Pointer to a FPU state. */
1807typedef X86FPUSTATE *PX86FPUSTATE;
1808/** Pointer to a const FPU state. */
1809typedef const X86FPUSTATE *PCX86FPUSTATE;
1810
1811/**
1812 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1813 */
1814#pragma pack(1)
1815typedef struct X86FXSTATE
1816{
1817 /** Control word. */
1818 uint16_t FCW;
1819 /** Status word. */
1820 uint16_t FSW;
1821 /** Tag word (it's a byte actually). */
1822 uint8_t FTW;
1823 uint8_t huh1;
1824 /** Opcode. */
1825 uint16_t FOP;
1826 /** Instruction pointer. */
1827 uint32_t FPUIP;
1828 /** Code selector. */
1829 uint16_t CS;
1830 uint16_t Rsvrd1;
1831 /* - offset 16 - */
1832 /** Data pointer. */
1833 uint32_t FPUDP;
1834 /** Data segment */
1835 uint16_t DS;
1836 uint16_t Rsrvd2;
1837 uint32_t MXCSR;
1838 uint32_t MXCSR_MASK;
1839 /* - offset 32 - */
1840 union
1841 {
1842 /** MMX view. */
1843 uint64_t mmx;
1844 /** FPU view - todo. */
1845 X86FPUMMX fpu;
1846 /** 8-bit view. */
1847 uint8_t au8[16];
1848 /** 16-bit view. */
1849 uint16_t au16[8];
1850 /** 32-bit view. */
1851 uint32_t au32[4];
1852 /** 64-bit view. */
1853 uint64_t au64[2];
1854 /** 128-bit view. (yeah, very helpful) */
1855 uint128_t au128[1];
1856 } aRegs[8];
1857 /* - offset 160 - */
1858 union
1859 {
1860 /** XMM Register view *. */
1861 uint128_t xmm;
1862 /** 8-bit view. */
1863 uint8_t au8[16];
1864 /** 16-bit view. */
1865 uint16_t au16[8];
1866 /** 32-bit view. */
1867 uint32_t au32[4];
1868 /** 64-bit view. */
1869 uint64_t au64[2];
1870 /** 128-bit view. (yeah, very helpful) */
1871 uint128_t au128[1];
1872 } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1873 /* - offset 416 - */
1874 uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1875} X86FXSTATE;
1876#pragma pack()
1877/** Pointer to a FPU Extended state. */
1878typedef X86FXSTATE *PX86FXSTATE;
1879/** Pointer to a const FPU Extended state. */
1880typedef const X86FXSTATE *PCX86FXSTATE;
1881
1882
1883/** @name Selector Descriptor
1884 * @{
1885 */
1886
1887/**
1888 * Generic descriptor table entry
1889 */
1890#pragma pack(1)
1891typedef struct X86DESCGENERIC
1892{
1893 /** Limit - Low word. */
1894 unsigned u16LimitLow : 16;
1895 /** Base address - lowe word.
1896 * Don't try set this to 24 because MSC is doing studing things then. */
1897 unsigned u16BaseLow : 16;
1898 /** Base address - first 8 bits of high word. */
1899 unsigned u8BaseHigh1 : 8;
1900 /** Segment Type. */
1901 unsigned u4Type : 4;
1902 /** Descriptor Type. System(=0) or code/data selector */
1903 unsigned u1DescType : 1;
1904 /** Descriptor Privelege level. */
1905 unsigned u2Dpl : 2;
1906 /** Flags selector present(=1) or not. */
1907 unsigned u1Present : 1;
1908 /** Segment limit 16-19. */
1909 unsigned u4LimitHigh : 4;
1910 /** Available for system software. */
1911 unsigned u1Available : 1;
1912 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1913 unsigned u1Long : 1;
1914 /** This flags meaning depends on the segment type. Try make sense out
1915 * of the intel manual yourself. */
1916 unsigned u1DefBig : 1;
1917 /** Granularity of the limit. If set 4KB granularity is used, if
1918 * clear byte. */
1919 unsigned u1Granularity : 1;
1920 /** Base address - highest 8 bits. */
1921 unsigned u8BaseHigh2 : 8;
1922} X86DESCGENERIC;
1923#pragma pack()
1924/** Pointer to a generic descriptor entry. */
1925typedef X86DESCGENERIC *PX86DESCGENERIC;
1926/** Pointer to a const generic descriptor entry. */
1927typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1928
1929
1930/**
1931 * Descriptor attributes.
1932 */
1933typedef struct X86DESCATTRBITS
1934{
1935 /** Segment Type. */
1936 unsigned u4Type : 4;
1937 /** Descriptor Type. System(=0) or code/data selector */
1938 unsigned u1DescType : 1;
1939 /** Descriptor Privelege level. */
1940 unsigned u2Dpl : 2;
1941 /** Flags selector present(=1) or not. */
1942 unsigned u1Present : 1;
1943 /** Segment limit 16-19. */
1944 unsigned u4LimitHigh : 4;
1945 /** Available for system software. */
1946 unsigned u1Available : 1;
1947 /** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1948 unsigned u1Long : 1;
1949 /** This flags meaning depends on the segment type. Try make sense out
1950 * of the intel manual yourself. */
1951 unsigned u1DefBig : 1;
1952 /** Granularity of the limit. If set 4KB granularity is used, if
1953 * clear byte. */
1954 unsigned u1Granularity : 1;
1955} X86DESCATTRBITS;
1956
1957
1958#pragma pack(1)
1959typedef union X86DESCATTR
1960{
1961 /** Unsigned integer view. */
1962 uint32_t u;
1963 /** Normal view. */
1964 X86DESCATTRBITS n;
1965} X86DESCATTR;
1966#pragma pack()
1967
1968/** Pointer to descriptor attributes. */
1969typedef X86DESCATTR *PX86DESCATTR;
1970/** Pointer to const descriptor attributes. */
1971typedef const X86DESCATTR *PCX86DESCATTR;
1972
1973
1974/**
1975 * Descriptor table entry.
1976 */
1977#pragma pack(1)
1978typedef union X86DESC
1979{
1980 /** Generic descriptor view. */
1981 X86DESCGENERIC Gen;
1982#if 0
1983 /** IDT view. */
1984 VBOXIDTE Idt;
1985#endif
1986
1987 /** 8 bit unsigned interger view. */
1988 uint8_t au8[8];
1989 /** 16 bit unsigned interger view. */
1990 uint16_t au16[4];
1991 /** 32 bit unsigned interger view. */
1992 uint32_t au32[2];
1993} X86DESC;
1994#pragma pack()
1995/** Pointer to descriptor table entry. */
1996typedef X86DESC *PX86DESC;
1997/** Pointer to const descriptor table entry. */
1998typedef const X86DESC *PCX86DESC;
1999
2000
2001/** @def X86DESC_BASE
2002 * Return the base address of a descriptor.
2003 */
2004#define X86DESC_BASE(desc) \
2005 ( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2006 | ( (desc).Gen.u8BaseHigh1 << 16) \
2007 | ( (desc).Gen.u16BaseLow ) )
2008
2009/** @def X86DESC_LIMIT
2010 * Return the limit of a descriptor.
2011 */
2012#define X86DESC_LIMIT(desc) \
2013 ( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2014 | ( (desc).Gen.u16LimitLow ) )
2015
2016/**
2017 * 64 bits generic descriptor table entry
2018 * Note: most of these bits have no meaning in long mode.
2019 */
2020#pragma pack(1)
2021typedef struct X86DESC64GENERIC
2022{
2023 /** Limit - Low word - *IGNORED*. */
2024 unsigned u16LimitLow : 16;
2025 /** Base address - lowe word. - *IGNORED*
2026 * Don't try set this to 24 because MSC is doing studing things then. */
2027 unsigned u16BaseLow : 16;
2028 /** Base address - first 8 bits of high word. - *IGNORED* */
2029 unsigned u8BaseHigh1 : 8;
2030 /** Segment Type. */
2031 unsigned u4Type : 4;
2032 /** Descriptor Type. System(=0) or code/data selector */
2033 unsigned u1DescType : 1;
2034 /** Descriptor Privelege level. */
2035 unsigned u2Dpl : 2;
2036 /** Flags selector present(=1) or not. */
2037 unsigned u1Present : 1;
2038 /** Segment limit 16-19. - *IGNORED* */
2039 unsigned u4LimitHigh : 4;
2040 /** Available for system software. - *IGNORED* */
2041 unsigned u1Available : 1;
2042 /** Long mode flag. */
2043 unsigned u1Long : 1;
2044 /** This flags meaning depends on the segment type. Try make sense out
2045 * of the intel manual yourself. */
2046 unsigned u1DefBig : 1;
2047 /** Granularity of the limit. If set 4KB granularity is used, if
2048 * clear byte. - *IGNORED* */
2049 unsigned u1Granularity : 1;
2050 /** Base address - highest 8 bits. - *IGNORED* */
2051 unsigned u8BaseHigh2 : 8;
2052 /** Base address - bits 63-32. */
2053 unsigned u32BaseHigh3 : 32;
2054 unsigned u8Reserved : 8;
2055 unsigned u5Zeros : 5;
2056 unsigned u19Reserved : 19;
2057} X86DESC64GENERIC;
2058#pragma pack()
2059/** Pointer to a generic descriptor entry. */
2060typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2061/** Pointer to a const generic descriptor entry. */
2062typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2063
2064/**
2065 * System descriptor table entry (64 bits)
2066 */
2067#pragma pack(1)
2068typedef struct X86DESC64SYSTEM
2069{
2070 /** Limit - Low word. */
2071 unsigned u16LimitLow : 16;
2072 /** Base address - lowe word.
2073 * Don't try set this to 24 because MSC is doing studing things then. */
2074 unsigned u16BaseLow : 16;
2075 /** Base address - first 8 bits of high word. */
2076 unsigned u8BaseHigh1 : 8;
2077 /** Segment Type. */
2078 unsigned u4Type : 4;
2079 /** Descriptor Type. System(=0) or code/data selector */
2080 unsigned u1DescType : 1;
2081 /** Descriptor Privelege level. */
2082 unsigned u2Dpl : 2;
2083 /** Flags selector present(=1) or not. */
2084 unsigned u1Present : 1;
2085 /** Segment limit 16-19. */
2086 unsigned u4LimitHigh : 4;
2087 /** Available for system software. */
2088 unsigned u1Available : 1;
2089 /** Reserved - 0. */
2090 unsigned u1Reserved : 1;
2091 /** This flags meaning depends on the segment type. Try make sense out
2092 * of the intel manual yourself. */
2093 unsigned u1DefBig : 1;
2094 /** Granularity of the limit. If set 4KB granularity is used, if
2095 * clear byte. */
2096 unsigned u1Granularity : 1;
2097 /** Base address - bits 31-24. */
2098 unsigned u8BaseHigh2 : 8;
2099 /** Base address - bits 63-32. */
2100 unsigned u32BaseHigh3 : 32;
2101 unsigned u8Reserved : 8;
2102 unsigned u5Zeros : 5;
2103 unsigned u19Reserved : 19;
2104} X86DESC64SYSTEM;
2105#pragma pack()
2106/** Pointer to a generic descriptor entry. */
2107typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2108/** Pointer to a const generic descriptor entry. */
2109typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2110
2111
2112/**
2113 * Descriptor table entry.
2114 */
2115#pragma pack(1)
2116typedef union X86DESC64
2117{
2118 /** Generic descriptor view. */
2119 X86DESC64GENERIC Gen;
2120 /** System descriptor view. */
2121 X86DESC64SYSTEM System;
2122#if 0
2123 X86DESC64GATE Gate;
2124#endif
2125
2126 /** 8 bit unsigned interger view. */
2127 uint8_t au8[16];
2128 /** 16 bit unsigned interger view. */
2129 uint16_t au16[8];
2130 /** 32 bit unsigned interger view. */
2131 uint32_t au32[4];
2132 /** 64 bit unsigned interger view. */
2133 uint64_t au64[2];
2134} X86DESC64;
2135#pragma pack()
2136/** Pointer to descriptor table entry. */
2137typedef X86DESC64 *PX86DESC64;
2138/** Pointer to const descriptor table entry. */
2139typedef const X86DESC64 *PCX86DESC64;
2140
2141#if HC_ARCH_BITS == 64
2142typedef X86DESC64 X86DESCHC;
2143typedef X86DESC64 *PX86DESCHC;
2144#else
2145typedef X86DESC X86DESCHC;
2146typedef X86DESC *PX86DESCHC;
2147#endif
2148
2149/** @def X86DESC_LIMIT
2150 * Return the base of a 64-bit descriptor.
2151 */
2152#define X86DESC64_BASE(desc) \
2153 ( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2154 | ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2155 | ( (desc).Gen.u8BaseHigh1 << 16) \
2156 | ( (desc).Gen.u16BaseLow ) )
2157
2158
2159/** @name Selector Descriptor Types.
2160 * @{
2161 */
2162
2163/** @name Non-System Selector Types.
2164 * @{ */
2165/** Code(=set)/Data(=clear) bit. */
2166#define X86_SEL_TYPE_CODE 8
2167/** Memory(=set)/System(=clear) bit. */
2168#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2169/** Accessed bit. */
2170#define X86_SEL_TYPE_ACCESSED 1
2171/** Expand down bit (for data selectors only). */
2172#define X86_SEL_TYPE_DOWN 4
2173/** Conforming bit (for code selectors only). */
2174#define X86_SEL_TYPE_CONF 4
2175/** Write bit (for data selectors only). */
2176#define X86_SEL_TYPE_WRITE 2
2177/** Read bit (for code selectors only). */
2178#define X86_SEL_TYPE_READ 2
2179
2180/** Read only selector type. */
2181#define X86_SEL_TYPE_RO 0
2182/** Accessed read only selector type. */
2183#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
2184/** Read write selector type. */
2185#define X86_SEL_TYPE_RW 2
2186/** Accessed read write selector type. */
2187#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
2188/** Expand down read only selector type. */
2189#define X86_SEL_TYPE_RO_DOWN 4
2190/** Accessed expand down read only selector type. */
2191#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
2192/** Expand down read write selector type. */
2193#define X86_SEL_TYPE_RW_DOWN 6
2194/** Accessed expand down read write selector type. */
2195#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
2196/** Execute only selector type. */
2197#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
2198/** Accessed execute only selector type. */
2199#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2200/** Execute and read selector type. */
2201#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
2202/** Accessed execute and read selector type. */
2203#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2204/** Conforming execute only selector type. */
2205#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
2206/** Accessed Conforming execute only selector type. */
2207#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2208/** Conforming execute and write selector type. */
2209#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
2210/** Accessed Conforming execute and write selector type. */
2211#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
2212/** @} */
2213
2214
2215/** @name System Selector Types.
2216 * @{ */
2217/** Undefined system selector type. */
2218#define X86_SEL_TYPE_SYS_UNDEFINED 0
2219/** 286 TSS selector. */
2220#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2221/** LDT selector. */
2222#define X86_SEL_TYPE_SYS_LDT 2
2223/** 286 TSS selector - Busy. */
2224#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2225/** 286 Callgate selector. */
2226#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2227/** Taskgate selector. */
2228#define X86_SEL_TYPE_SYS_TASK_GATE 5
2229/** 286 Interrupt gate selector. */
2230#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2231/** 286 Trapgate selector. */
2232#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2233/** Undefined system selector. */
2234#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2235/** 386 TSS selector. */
2236#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2237/** Undefined system selector. */
2238#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2239/** 386 TSS selector - Busy. */
2240#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2241/** 386 Callgate selector. */
2242#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2243/** Undefined system selector. */
2244#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2245/** 386 Interruptgate selector. */
2246#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2247/** 386 Trapgate selector. */
2248#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2249/** @} */
2250
2251/** @name AMD64 System Selector Types.
2252 * @{ */
2253#define AMD64_SEL_TYPE_SYS_LDT 2
2254/** 286 TSS selector - Busy. */
2255#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2256/** 386 TSS selector - Busy. */
2257#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2258/** 386 Callgate selector. */
2259#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2260/** 386 Interruptgate selector. */
2261#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2262/** 386 Trapgate selector. */
2263#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2264/** @} */
2265
2266/** @} */
2267
2268
2269/** @name Descriptor Table Entry Flag Masks.
2270 * These are for the 2nd 32-bit word of a descriptor.
2271 * @{ */
2272/** Bits 8-11 - TYPE - Descriptor type mask. */
2273#define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
2274/** Bit 12 - S - System (=0) or Code/Data (=1). */
2275#define X86_DESC_S RT_BIT(12)
2276/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2277#define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
2278/** Bit 15 - P - Present. */
2279#define X86_DESC_P RT_BIT(15)
2280/** Bit 20 - AVL - Available for system software. */
2281#define X86_DESC_AVL RT_BIT(20)
2282/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2283#define X86_DESC_DB RT_BIT(22)
2284/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2285 * used, if clear byte. */
2286#define X86_DESC_G RT_BIT(23)
2287/** @} */
2288
2289/** @} */
2290
2291
2292/** @name Selectors.
2293 * @{
2294 */
2295
2296/**
2297 * The shift used to convert a selector from and to index an index (C).
2298 */
2299#define X86_SEL_SHIFT 3
2300
2301/**
2302 * The shift used to convert a selector from and to index an index (C).
2303 */
2304#define AMD64_SEL_SHIFT 4
2305
2306#if HC_ARCH_BITS == 64
2307#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2308#else
2309#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2310#endif
2311
2312/**
2313 * The mask used to mask off the table indicator and CPL of an selector.
2314 */
2315#define X86_SEL_MASK 0xfff8
2316
2317/**
2318 * The bit indicating that a selector is in the LDT and not in the GDT.
2319 */
2320#define X86_SEL_LDT 0x0004
2321/**
2322 * The bit mask for getting the RPL of a selector.
2323 */
2324#define X86_SEL_RPL 0x0003
2325
2326/** @} */
2327
2328
2329/**
2330 * x86 Exceptions/Faults/Traps.
2331 */
2332typedef enum X86XCPT
2333{
2334 /** \#DE - Divide error. */
2335 X86_XCPT_DE = 0x00,
2336 /** \#DB - Debug event (single step, DRx, ..) */
2337 X86_XCPT_DB = 0x01,
2338 /** NMI - Non-Maskable Interrupt */
2339 X86_XCPT_NMI = 0x02,
2340 /** \#BP - Breakpoint (INT3). */
2341 X86_XCPT_BP = 0x03,
2342 /** \#OF - Overflow (INTO). */
2343 X86_XCPT_OF = 0x04,
2344 /** \#BR - Bound range exceeded (BOUND). */
2345 X86_XCPT_BR = 0x05,
2346 /** \#UD - Undefined opcode. */
2347 X86_XCPT_UD = 0x06,
2348 /** \#NM - Device not available (math coprocessor device). */
2349 X86_XCPT_NM = 0x07,
2350 /** \#DF - Double fault. */
2351 X86_XCPT_DF = 0x08,
2352 /** ??? - Coprocessor segment overrun (obsolete). */
2353 X86_XCPT_CO_SEG_OVERRUN = 0x09,
2354 /** \#TS - Taskswitch (TSS). */
2355 X86_XCPT_TS = 0x0a,
2356 /** \#NP - Segment no present. */
2357 X86_XCPT_NP = 0x0b,
2358 /** \#SS - Stack segment fault. */
2359 X86_XCPT_SS = 0x0c,
2360 /** \#GP - General protection fault. */
2361 X86_XCPT_GP = 0x0d,
2362 /** \#PF - Page fault. */
2363 X86_XCPT_PF = 0x0e,
2364 /* 0x0f is reserved. */
2365 /** \#MF - Math fault (FPU). */
2366 X86_XCPT_MF = 0x10,
2367 /** \#AC - Alignment check. */
2368 X86_XCPT_AC = 0x11,
2369 /** \#MC - Machine check. */
2370 X86_XCPT_MC = 0x12,
2371 /** \#XF - SIMD Floating-Pointer Exception. */
2372 X86_XCPT_XF = 0x13
2373} X86XCPT;
2374/** Pointer to a x86 exception code. */
2375typedef X86XCPT *PX86XCPT;
2376/** Pointer to a const x86 exception code. */
2377typedef const X86XCPT *PCX86XCPT;
2378
2379
2380/** @name Trap Error Codes
2381 * @{
2382 */
2383/** External indicator. */
2384#define X86_TRAP_ERR_EXTERNAL 1
2385/** IDT indicator. */
2386#define X86_TRAP_ERR_IDT 2
2387/** Descriptor table indicator - If set LDT, if clear GDT. */
2388#define X86_TRAP_ERR_TI 4
2389/** Mask for getting the selector. */
2390#define X86_TRAP_ERR_SEL_MASK 0xfff8
2391/** Shift for getting the selector table index (C type index). */
2392#define X86_TRAP_ERR_SEL_SHIFT 3
2393/** @} */
2394
2395
2396/** @name \#PF Trap Error Codes
2397 * @{
2398 */
2399/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2400#define X86_TRAP_PF_P RT_BIT(0)
2401/** Bit 1 - R/W - Read (clear) or write (set) access. */
2402#define X86_TRAP_PF_RW RT_BIT(1)
2403/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2404#define X86_TRAP_PF_US RT_BIT(2)
2405/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2406#define X86_TRAP_PF_RSVD RT_BIT(3)
2407/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2408#define X86_TRAP_PF_ID RT_BIT(4)
2409/** @} */
2410
2411#pragma pack(1)
2412/**
2413 * 32-bit IDTR/GDTR.
2414 */
2415typedef struct X86XDTR32
2416{
2417 /** Size of the descriptor table. */
2418 uint16_t cb;
2419 /** Address of the descriptor table. */
2420 uint32_t uAddr;
2421} X86XDTR32, *PX86XDTR32;
2422#pragma pack()
2423
2424#pragma pack(1)
2425/**
2426 * 64-bit IDTR/GDTR.
2427 */
2428typedef struct X86XDTR64
2429{
2430 /** Size of the descriptor table. */
2431 uint16_t cb;
2432 /** Address of the descriptor table. */
2433 uint64_t uAddr;
2434} X86XDTR64, *PX86XDTR64;
2435#pragma pack()
2436
2437/** @} */
2438
2439#endif
2440
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