vm.h@ 105506

Last change on this file since 105506 was 105227, checked in by vboxsync, 10 months ago
VMM/IEM: Implement vmin{ps,pd,ss,sd} instruction emulations, bugref:9898 [build fix]
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_vm_h
37	#define VBOX_INCLUDED_vmm_vm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# ifndef USING_VMM_COMMON_DEFS
44	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45	# endif
46	# include <iprt/param.h>
47	# include <VBox/param.h>
48	# include <VBox/types.h>
49	# include <VBox/vmm/cpum.h>
50	# include <VBox/vmm/stam.h>
51	# include <VBox/vmm/vmapi.h>
52	# include <VBox/vmm/vmm.h>
53	# include <VBox/sup.h>
54	#else
55	# pragma D depends_on library vbox-types.d
56	# pragma D depends_on library CPUMInternal.d
57	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58	#endif
59
60
61
62	/** @defgroup grp_vm The Virtual Machine
63	* @ingroup grp_vmm
64	* @{
65	*/
66
67	/**
68	* The state of a Virtual CPU.
69	*
70	* The basic state indicated here is whether the CPU has been started or not. In
71	* addition, there are sub-states when started for assisting scheduling (GVMM
72	* mostly).
73	*
74	* The transition out of the STOPPED state is done by a vmR3PowerOn.
75	* The transition back to the STOPPED state is done by vmR3PowerOff.
76	*
77	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
78	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
79	*/
80	typedef enum VMCPUSTATE
81	{
82	/** The customary invalid zero. */
83	VMCPUSTATE_INVALID = 0,
84
85	/** Virtual CPU has not yet been started. */
86	VMCPUSTATE_STOPPED,
87
88	/** CPU started. */
89	VMCPUSTATE_STARTED,
90	/** CPU started in HM context. */
91	VMCPUSTATE_STARTED_HM,
92	/** Executing guest code and can be poked (RC or STI bits of HM). */
93	VMCPUSTATE_STARTED_EXEC,
94	/** Executing guest code using NEM. */
95	VMCPUSTATE_STARTED_EXEC_NEM,
96	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
97	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
98	/** Halted. */
99	VMCPUSTATE_STARTED_HALTED,
100
101	/** The end of valid virtual CPU states. */
102	VMCPUSTATE_END,
103
104	/** Ensure 32-bit type. */
105	VMCPUSTATE_32BIT_HACK = 0x7fffffff
106	} VMCPUSTATE;
107
108	/** Enables 64-bit FFs. */
109	#define VMCPU_WITH_64_BIT_FFS
110
111
112	/**
113	* The cross context virtual CPU structure.
114	*
115	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
116	*/
117	typedef struct VMCPU
118	{
119	/** @name Volatile per-cpu data.
120	* @{ */
121	/** Per CPU forced action.
122	* See the VMCPU_FF_* \#defines. Updated atomically. */
123	#ifdef VMCPU_WITH_64_BIT_FFS
124	uint64_t volatile fLocalForcedActions;
125	#else
126	uint32_t volatile fLocalForcedActions;
127	uint32_t fForLocalForcedActionsExpansion;
128	#endif
129	/** The CPU state. */
130	VMCPUSTATE volatile enmState;
131
132	#if defined(VBOX_VMM_TARGET_ARMV8)
133	uint32_t u32Alignment0;
134	/** The number of nano seconds when the vTimer of the associated vCPU is supposed to activate
135	* required to get out of a halt (due to wfi/wfe).
136	*
137	* @note This actually should go into TMCPU but this drags in a whole lot of padding changes
138	* and I'm not sure yet whether this will remain in this form anyway.
139	*/
140	uint64_t cNsVTimerActivate;
141	/** Padding up to 64 bytes. */
142	uint8_t abAlignment0[64 - 12 - 8 - 4];
143	#else
144	/** Padding up to 64 bytes. */
145	uint8_t abAlignment0[64 - 12];
146	#endif
147	/** @} */
148
149	/** IEM part.
150	* @remarks This comes first as it allows the use of 8-bit immediates for the
151	* first 64 bytes of the structure, reducing code size a wee bit. */
152	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h) /* For PDB hacking. */
153	union VMCPUUNIONIEMFULL
154	#else
155	union VMCPUUNIONIEMSTUB
156	#endif
157	{
158	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h)
159	struct IEMCPU s;
160	#endif
161	uint8_t padding[ 129984 /* The common base size. */
162	#ifdef RT_ARCH_AMD64
163	+ 32768 /* For 256 entries per TLBs. */
164	#else
165	+ 1048576 /* For 8192 entries per TLBs. */
166	#endif
167	]; /* multiple of 64 */
168	} iem;
169
170	/** @name Static per-cpu data.
171	* (Putting this after IEM, hoping that it's less frequently used than it.)
172	* @{ */
173	/** Ring-3 Host Context VM Pointer. */
174	PVMR3 pVMR3;
175	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
176	RTR0PTR pVCpuR0ForVtg;
177	/** Raw-mode Context VM Pointer. */
178	uint32_t pVMRC;
179	/** Padding for new raw-mode (long mode). */
180	uint32_t pVMRCPadding;
181	/** Pointer to the ring-3 UVMCPU structure. */
182	PUVMCPU pUVCpu;
183	/** The native thread handle. */
184	RTNATIVETHREAD hNativeThread;
185	/** The native R0 thread handle. (different from the R3 handle!) */
186	RTNATIVETHREAD hNativeThreadR0;
187	/** The IPRT thread handle (for VMMDevTesting). */
188	RTTHREAD hThread;
189	/** The CPU ID.
190	* This is the index into the VM::aCpu array. */
191	#ifdef IN_RING0
192	VMCPUID idCpuUnsafe;
193	#else
194	VMCPUID idCpu;
195	#endif
196
197	/** Align the structures below bit on a 64-byte boundary and make sure it starts
198	* at the same offset in both 64-bit and 32-bit builds.
199	*
200	* @remarks The alignments of the members that are larger than 48 bytes should be
201	* 64-byte for cache line reasons. structs containing small amounts of
202	* data could be lumped together at the end with a < 64 byte padding
203	* following it (to grow into and align the struct size).
204	*/
205	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
206	/** @} */
207
208	/** HM part. */
209	union VMCPUUNIONHM
210	{
211	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
212	struct HMCPU s;
213	#endif
214	uint8_t padding[9984]; /* multiple of 64 */
215	} hm;
216
217	/** NEM part. */
218	union VMCPUUNIONNEM
219	{
220	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
221	struct NEMCPU s;
222	#endif
223	uint8_t padding[4608]; /* multiple of 64 */
224	} nem;
225
226	/** TRPM part. */
227	union VMCPUUNIONTRPM
228	{
229	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
230	struct TRPMCPU s;
231	#endif
232	uint8_t padding[128]; /* multiple of 64 */
233	} trpm;
234
235	/** TM part. */
236	union VMCPUUNIONTM
237	{
238	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
239	struct TMCPU s;
240	#endif
241	uint8_t padding[5760]; /* multiple of 64 */
242	} tm;
243
244	/** VMM part. */
245	union VMCPUUNIONVMM
246	{
247	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
248	struct VMMCPU s;
249	#endif
250	uint8_t padding[9536]; /* multiple of 64 */
251	} vmm;
252
253	/** PDM part. */
254	union VMCPUUNIONPDM
255	{
256	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
257	struct PDMCPU s;
258	#endif
259	uint8_t padding[256]; /* multiple of 64 */
260	} pdm;
261
262	/** IOM part. */
263	union VMCPUUNIONIOM
264	{
265	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
266	struct IOMCPU s;
267	#endif
268	uint8_t padding[512]; /* multiple of 64 */
269	} iom;
270
271	/** DBGF part.
272	* @todo Combine this with other tiny structures. */
273	union VMCPUUNIONDBGF
274	{
275	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
276	struct DBGFCPU s;
277	#endif
278	uint8_t padding[512]; /* multiple of 64 */
279	} dbgf;
280
281	/** GIM part. */
282	union VMCPUUNIONGIM
283	{
284	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
285	struct GIMCPU s;
286	#endif
287	uint8_t padding[512]; /* multiple of 64 */
288	} gim;
289
290	#if defined(VBOX_VMM_TARGET_ARMV8)
291	/** GIC part. */
292	union VMCPUUNIONGIC
293	{
294	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
295	struct GICCPU s;
296	# endif
297	uint8_t padding[3840]; /* multiple of 64 */
298	} gic;
299	#else
300	/** APIC part. */
301	union VMCPUUNIONAPIC
302	{
303	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
304	struct APICCPU s;
305	# endif
306	uint8_t padding[3840]; /* multiple of 64 */
307	} apic;
308	#endif
309
310	/*
311	* Some less frequently used global members that doesn't need to take up
312	* precious space at the head of the structure.
313	*/
314
315	/** Trace groups enable flags. */
316	uint32_t fTraceGroups; /* 64 / 44 */
317	/** Number of collisions hashing the ring-0 EMT handle. */
318	uint8_t cEmtHashCollisions;
319	uint8_t abAdHoc[3];
320	/** Profiling samples for use by ad hoc profiling. */
321	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
322
323	/** Align the following members on page boundary. */
324	uint8_t abAlignment2[1848];
325
326	/** PGM part. */
327	union VMCPUUNIONPGM
328	{
329	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
330	struct PGMCPU s;
331	#endif
332	uint8_t padding[36864]; /* multiple of 4096 */
333	} pgm;
334
335	/** CPUM part. */
336	union VMCPUUNIONCPUM
337	{
338	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
339	struct CPUMCPU s;
340	#endif
341	#ifdef VMCPU_INCL_CPUM_GST_CTX
342	/** The guest CPUM context for direct use by execution engines.
343	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
344	* others. The rest will use the function based CPUM API. */
345	CPUMCTX GstCtx;
346	#endif
347	uint8_t padding[102400]; /* multiple of 4096 */
348	} cpum;
349
350	/** EM part. */
351	union VMCPUUNIONEM
352	{
353	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
354	struct EMCPU s;
355	#endif
356	uint8_t padding[40960]; /* multiple of 4096 */
357	} em;
358	uint8_t abPadding[12288];
359	} VMCPU;
360
361
362	#ifndef VBOX_FOR_DTRACE_LIB
363	# ifndef IN_TSTVMSTRUCT
364	/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
365	AssertCompileSizeAlignment(VMCPU, 16384);
366	# endif
367
368	/** @name Operations on VMCPU::enmState
369	* @{ */
370	/** Gets the VMCPU state. */
371	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
372	/** Sets the VMCPU state. */
373	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
374	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
375	/** Cmpares and sets the VMCPU state. */
376	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
377	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
378	/** Checks the VMCPU state. */
379	#ifdef VBOX_STRICT
380	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
381	do { \
382	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
383	AssertMsg(enmState == (enmExpectedState), \
384	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
385	enmState, enmExpectedState, (pVCpu)->idCpu)); \
386	} while (0)
387
388	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
389	do { \
390	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
391	AssertMsg( enmState == (enmExpectedState) \
392	\|\| enmState == (a_enmExpectedState2), \
393	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
394	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
395	} while (0)
396	#else
397	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
398	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
399	#endif
400	/** Tests if the state means that the CPU is started. */
401	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
402	/** Tests if the state means that the CPU is stopped. */
403	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
404	/** @} */
405
406
407	/** The name of the raw-mode context VMM Core module. */
408	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
409	/** The name of the ring-0 context VMM Core module. */
410	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
411
412
413	/** VM Forced Action Flags.
414	*
415	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
416	* action mask of a VM.
417	*
418	* Available VM bits:
419	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
420	*
421	*
422	* Available VMCPU bits:
423	* 14, 15, 36 to 63
424	*
425	* @todo If we run low on VMCPU, we may consider merging the SELM bits
426	*
427	* @{
428	*/
429	/** The virtual sync clock has been stopped, go to TM until it has been
430	* restarted... */
431	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
432	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
433	/** PDM Queues are pending. */
434	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
435	/** The bit number for VM_FF_PDM_QUEUES. */
436	#define VM_FF_PDM_QUEUES_BIT 3
437	/** PDM DMA transfers are pending. */
438	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
439	/** The bit number for VM_FF_PDM_DMA. */
440	#define VM_FF_PDM_DMA_BIT 4
441	/** This action forces the VM to call DBGF so DBGF can service debugger
442	* requests in the emulation thread.
443	* This action flag stays asserted till DBGF clears it.*/
444	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
445	/** The bit number for VM_FF_DBGF. */
446	#define VM_FF_DBGF_BIT 8
447	/** This action forces the VM to service pending requests from other
448	* thread or requests which must be executed in another context. */
449	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
450	#define VM_FF_REQUEST_BIT 9
451	/** Check for VM state changes and take appropriate action. */
452	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
453	/** The bit number for VM_FF_CHECK_VM_STATE. */
454	#define VM_FF_CHECK_VM_STATE_BIT 10
455	/** Reset the VM. (postponed) */
456	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
457	/** The bit number for VM_FF_RESET. */
458	#define VM_FF_RESET_BIT 11
459	/** EMT rendezvous in VMM. */
460	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
461	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
462	#define VM_FF_EMT_RENDEZVOUS_BIT 12
463
464	/** PGM needs to allocate handy pages. */
465	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
466	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
467	/** PGM is out of memory.
468	* Abandon all loops and code paths which can be resumed and get up to the EM
469	* loops. */
470	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
471	#define VM_FF_PGM_NO_MEMORY_BIT 19
472	/** PGM is about to perform a lightweight pool flush
473	* Guest SMP: all EMT threads should return to ring 3
474	*/
475	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
476	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
477	/** Suspend the VM - debug only. */
478	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
479	#define VM_FF_DEBUG_SUSPEND_BIT 31
480
481
482	#if defined(VBOX_VMM_TARGET_ARMV8)
483	/** This action forces the VM to inject an IRQ into the guest. */
484	# define VMCPU_FF_INTERRUPT_IRQ RT_BIT_64(VMCPU_FF_INTERRUPT_IRQ_BIT)
485	# define VMCPU_FF_INTERRUPT_IRQ_BIT 0
486	/** This action forces the VM to inject an FIQ into the guest. */
487	# define VMCPU_FF_INTERRUPT_FIQ RT_BIT_64(VMCPU_FF_INTERRUPT_FIQ_BIT)
488	# define VMCPU_FF_INTERRUPT_FIQ_BIT 1
489	#else
490	/** This action forces the VM to check any pending interrupts on the APIC. */
491	# define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
492	# define VMCPU_FF_INTERRUPT_APIC_BIT 0
493	/** This action forces the VM to check any pending interrups on the PIC. */
494	# define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
495	# define VMCPU_FF_INTERRUPT_PIC_BIT 1
496	#endif
497	/** This action forces the VM to schedule and run pending timer (TM).
498	* @remarks Don't move - PATM compatibility. */
499	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
500	#define VMCPU_FF_TIMER_BIT 2
501	/** This action forces the VM to check any pending NMIs. */
502	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
503	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
504	/** This action forces the VM to check any pending SMIs. */
505	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
506	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
507	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
508	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
509	#define VMCPU_FF_PDM_CRITSECT_BIT 5
510	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
511	* the virtual CPU out of the next (/current) halted state. It is not processed
512	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
513	* is cleared the next time EM leaves the HALTED state. */
514	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
515	#define VMCPU_FF_UNHALT_BIT 6
516	/** Pending IEM action (mask). */
517	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
518	/** Pending IEM action (bit number). */
519	#define VMCPU_FF_IEM_BIT 7
520	/** Pending APIC action (bit number). */
521	#define VMCPU_FF_UPDATE_APIC_BIT 8
522	/** This action forces the VM to update APIC's asynchronously arrived
523	* interrupts as pending interrupts. */
524	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
525	/** This action forces the VM to service pending requests from other
526	* thread or requests which must be executed in another context. */
527	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
528	#define VMCPU_FF_REQUEST_BIT 9
529	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
530	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
531	/** The bit number for VMCPU_FF_DBGF. */
532	#define VMCPU_FF_DBGF_BIT 10
533	/** Hardware virtualized nested-guest interrupt pending. */
534	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
535	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
536	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
537	* (when using nested paging). */
538	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
539	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
540	#if defined(VBOX_VMM_TARGET_ARMV8)
541	# define VMCPU_FF_VTIMER_ACTIVATED RT_BIT_64(VMCPU_FF_VTIMER_ACTIVATED_BIT)
542	# define VMCPU_FF_VTIMER_ACTIVATED_BIT 13
543	#else
544	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
545	#endif
546	/** This action forces the VM to resync the page tables before going
547	* back to execute guest code. (GLOBAL FLUSH) */
548	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
549	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
550	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
551	* (NON-GLOBAL FLUSH) */
552	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
553	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
554	/** Check for pending TLB shootdown actions (deprecated)
555	* Reserved for future HM re-use if necessary / safe.
556	* Consumer: HM */
557	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
558	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
559	/** Check for pending TLB flush action.
560	* Consumer: HM
561	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
562	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
563	/** The bit number for VMCPU_FF_TLB_FLUSH. */
564	#define VMCPU_FF_TLB_FLUSH_BIT 19
565	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
566	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
567	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
568	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
569	/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
570	/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
571	/** Force return to Ring-3. */
572	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
573	#define VMCPU_FF_TO_R3_BIT 28
574	/** Force return to ring-3 to service pending I/O or MMIO write.
575	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
576	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
577	* status codes to be propagated at the same time without loss. */
578	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
579	#define VMCPU_FF_IOM_BIT 29
580	/* 30 used to be VMCPU_FF_CPUM */
581	/** VMX-preemption timer expired. */
582	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
583	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
584	/** Pending MTF (Monitor Trap Flag) event. */
585	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
586	#define VMCPU_FF_VMX_MTF_BIT 32
587	/** VMX APIC-write emulation pending.
588	* @todo possible candidate for internal EFLAGS, or maybe just a summary bit
589	* (see also VMCPU_FF_VMX_INT_WINDOW). */
590	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
591	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
592	/** VMX interrupt-window event pending.
593	*
594	* "Pending" is misleading here, it would be better to say that the event need
595	* to be generated at the next opportunity and that this flag causes it to be
596	* polled for on every instruction boundrary and such.
597	*
598	* @todo Change the IEM side of this to not poll but to track down the places
599	* where it can be generated and set an internal EFLAGS bit that causes it
600	* to be checked out when finishing the current instruction. */
601	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
602	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
603	/** VMX NMI-window event pending.
604	* Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
605	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
606	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
607
608
609	/** Externally VM forced actions. Used to quit the idle/wait loop. */
610	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
611	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
612	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
613
614	/** Externally forced VM actions. Used to quit the idle/wait loop. */
615	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
616	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
617	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
618	#if defined(VBOX_VMM_TARGET_ARMV8)
619	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
620	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
621	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
622	\| VMCPU_FF_VTIMER_ACTIVATED)
623	#else
624	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
625	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
626	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
627	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
628	#endif
629
630	/** High priority VM pre-execution actions. */
631	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
632	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
633	\| VM_FF_EMT_RENDEZVOUS )
634	/** High priority VMCPU pre-execution actions. */
635	#if defined(VBOX_VMM_TARGET_ARMV8)
636	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
637	\| VMCPU_FF_DBGF )
638	#else
639	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
640	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_DBGF \
641	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
642	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
643	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
644	#endif
645
646	/** High priority VM pre raw-mode execution mask. */
647	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
648	/** High priority VMCPU pre raw-mode execution mask. */
649	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
650
651	/** High priority post-execution actions. */
652	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
653	/** High priority post-execution actions. */
654	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
655
656	/** Normal priority VM post-execution actions. */
657	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
658	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
659	/** Normal priority VMCPU post-execution actions. */
660	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
661
662	/** Normal priority VM actions. */
663	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
664	/** Normal priority VMCPU actions. */
665	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
666
667	/** Flags to clear before resuming guest execution. */
668	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
669
670
671	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
672	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
673	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
674	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
675	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
676	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
677	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
678	#ifdef IN_RING3
679	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF)
680	#else
681	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF)
682	#endif
683
684	#if !defined(VBOX_VMM_TARGET_ARMV8)
685	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
686	* enabled. */
687	# define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
688	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
689	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
690	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
691	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
692	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
693	* disabled. */
694	# define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
695	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
696	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
697	#endif
698
699	/** VM Flags that cause the HM loops to go back to ring-3. */
700	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
701	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
702	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
703	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
704	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
705
706	/** High priority ring-0 VM pre HM-mode execution mask. */
707	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
708	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
709	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
710	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
711	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
712	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
713	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
714	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
715	\| VM_FF_PDM_DMA) )
716	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
717	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
718	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
719
720	/** All the VMX nested-guest flags. */
721	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
722	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
723
724	/** All the forced VM flags. */
725	#define VM_FF_ALL_MASK (UINT32_MAX)
726	/** All the forced VMCPU flags. */
727	#define VMCPU_FF_ALL_MASK ( UINT32_MAX \
728	\| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_INT_WINDOW \
729	\| VMCPU_FF_VMX_NMI_WINDOW )
730
731	/** All the forced VM flags except those related to raw-mode and hardware
732	* assisted execution. */
733	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
734	/** All the forced VMCPU flags except those related to raw-mode and hardware
735	* assisted execution. */
736	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
737
738	#ifndef VBOX_FOR_DTRACE_LIB
739	AssertCompile( ((VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \| VM_FF_YIELD_REPSTR_MASK)
740	& (VM_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VM_FF_ALL_REM_MASK)) == 0);
741	AssertCompile((VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK & (VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VMCPU_FF_ALL_REM_MASK)) == 0);
742	#endif
743
744	/** @} */
745
746	/** @def VM_FF_SET
747	* Sets a single force action flag.
748	*
749	* @param pVM The cross context VM structure.
750	* @param fFlag The flag to set.
751	*/
752	#define VM_FF_SET(pVM, fFlag) do { \
753	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
754	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
755	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
756	} while (0)
757
758	/** @def VMCPU_FF_SET
759	* Sets a single force action flag for the given VCPU.
760	*
761	* @param pVCpu The cross context virtual CPU structure.
762	* @param fFlag The flag to set.
763	* @sa VMCPU_FF_SET_MASK
764	*/
765	#ifdef VMCPU_WITH_64_BIT_FFS
766	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
767	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
768	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
769	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
770	} while (0)
771	#else
772	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
773	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
774	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
775	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
776	} while (0)
777	#endif
778
779	/** @def VMCPU_FF_SET_MASK
780	* Sets a two or more force action flag for the given VCPU.
781	*
782	* @param pVCpu The cross context virtual CPU structure.
783	* @param fFlags The flags to set.
784	* @sa VMCPU_FF_SET
785	*/
786	#ifdef VMCPU_WITH_64_BIT_FFS
787	# if ARCH_BITS > 32
788	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
789	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
790	# else
791	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
792	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
793	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
794	} while (0)
795	# endif
796	#else
797	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
798	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
799	#endif
800
801	/** @def VM_FF_CLEAR
802	* Clears a single force action flag.
803	*
804	* @param pVM The cross context VM structure.
805	* @param fFlag The flag to clear.
806	*/
807	#define VM_FF_CLEAR(pVM, fFlag) do { \
808	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
809	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
810	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
811	} while (0)
812
813	/** @def VMCPU_FF_CLEAR
814	* Clears a single force action flag for the given VCPU.
815	*
816	* @param pVCpu The cross context virtual CPU structure.
817	* @param fFlag The flag to clear.
818	*/
819	#ifdef VMCPU_WITH_64_BIT_FFS
820	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
821	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
822	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
823	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
824	} while (0)
825	#else
826	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
827	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
828	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
829	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
830	} while (0)
831	#endif
832
833	/** @def VMCPU_FF_CLEAR_MASK
834	* Clears two or more force action flags for the given VCPU.
835	*
836	* @param pVCpu The cross context virtual CPU structure.
837	* @param fFlags The flags to clear.
838	*/
839	#ifdef VMCPU_WITH_64_BIT_FFS
840	# if ARCH_BITS > 32
841	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
842	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
843	# else
844	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
845	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
846	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
847	} while (0)
848	# endif
849	#else
850	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
851	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
852	#endif
853
854	/** @def VM_FF_IS_SET
855	* Checks if single a force action flag is set.
856	*
857	* @param pVM The cross context VM structure.
858	* @param fFlag The flag to check.
859	* @sa VM_FF_IS_ANY_SET
860	*/
861	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
862	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
863	#else
864	# define VM_FF_IS_SET(pVM, fFlag) \
865	([](PVM a_pVM) -> bool \
866	{ \
867	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
868	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
869	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
870	}(pVM))
871	#endif
872
873	/** @def VMCPU_FF_IS_SET
874	* Checks if a single force action flag is set for the given VCPU.
875	*
876	* @param pVCpu The cross context virtual CPU structure.
877	* @param fFlag The flag to check.
878	* @sa VMCPU_FF_IS_ANY_SET
879	*/
880	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
881	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
882	#else
883	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
884	([](PCVMCPU a_pVCpu) -> bool \
885	{ \
886	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
887	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
888	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
889	}(pVCpu))
890	#endif
891
892	/** @def VM_FF_IS_ANY_SET
893	* Checks if one or more force action in the specified set is pending.
894	*
895	* @param pVM The cross context VM structure.
896	* @param fFlags The flags to check for.
897	* @sa VM_FF_IS_SET
898	*/
899	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
900
901	/** @def VMCPU_FF_IS_ANY_SET
902	* Checks if two or more force action flags in the specified set is set for the given VCPU.
903	*
904	* @param pVCpu The cross context virtual CPU structure.
905	* @param fFlags The flags to check for.
906	* @sa VMCPU_FF_IS_SET
907	*/
908	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
909
910	/** @def VM_FF_TEST_AND_CLEAR
911	* Checks if one (!) force action in the specified set is pending and clears it atomically
912	*
913	* @returns true if the bit was set.
914	* @returns false if the bit was clear.
915	* @param pVM The cross context VM structure.
916	* @param fFlag Flag constant to check and clear (_BIT is appended).
917	*/
918	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
919
920	/** @def VMCPU_FF_TEST_AND_CLEAR
921	* Checks if one (!) force action in the specified set is pending and clears it atomically
922	*
923	* @returns true if the bit was set.
924	* @returns false if the bit was clear.
925	* @param pVCpu The cross context virtual CPU structure.
926	* @param fFlag Flag constant to check and clear (_BIT is appended).
927	*/
928	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
929
930	/** @def VM_FF_IS_PENDING_EXCEPT
931	* Checks if one or more force action in the specified set is pending while one
932	* or more other ones are not.
933	*
934	* @param pVM The cross context VM structure.
935	* @param fFlags The flags to check for.
936	* @param fExcpt The flags that should not be set.
937	*/
938	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
939	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
940
941	/** @def VM_IS_EMT
942	* Checks if the current thread is the emulation thread (EMT).
943	*
944	* @remark The ring-0 variation will need attention if we expand the ring-0
945	* code to let threads other than EMT mess around with the VM.
946	*/
947	#ifdef IN_RC
948	# define VM_IS_EMT(pVM) true
949	#else
950	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
951	#endif
952
953	/** @def VMCPU_IS_EMT
954	* Checks if the current thread is the emulation thread (EMT) for the specified
955	* virtual CPU.
956	*/
957	#ifdef IN_RC
958	# define VMCPU_IS_EMT(pVCpu) true
959	#else
960	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
961	#endif
962
963	/** @def VM_ASSERT_EMT
964	* Asserts that the current thread IS the emulation thread (EMT).
965	*/
966	#ifdef IN_RC
967	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
968	#elif defined(IN_RING0)
969	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
970	#else
971	# define VM_ASSERT_EMT(pVM) \
972	AssertMsg(VM_IS_EMT(pVM), \
973	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
974	#endif
975
976	/** @def VMCPU_ASSERT_EMT
977	* Asserts that the current thread IS the emulation thread (EMT) of the
978	* specified virtual CPU.
979	*/
980	#ifdef IN_RC
981	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
982	#elif defined(IN_RING0)
983	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
984	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
985	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
986	(pVCpu) ? (pVCpu)->idCpu : 0))
987	#else
988	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
989	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
990	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
991	#endif
992
993	/** @def VM_ASSERT_EMT_RETURN
994	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
995	*/
996	#ifdef IN_RC
997	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
998	#elif defined(IN_RING0)
999	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
1000	#else
1001	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
1002	AssertMsgReturn(VM_IS_EMT(pVM), \
1003	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
1004	(rc))
1005	#endif
1006
1007	/** @def VMCPU_ASSERT_EMT_RETURN
1008	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
1009	*/
1010	#ifdef IN_RC
1011	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1012	#elif defined(IN_RING0)
1013	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1014	#else
1015	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
1016	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
1017	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1018	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
1019	(rc))
1020	#endif
1021
1022	/** @def VMCPU_ASSERT_EMT_OR_GURU
1023	* Asserts that the current thread IS the emulation thread (EMT) of the
1024	* specified virtual CPU.
1025	*/
1026	#if defined(IN_RC) \|\| defined(IN_RING0)
1027	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
1028	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1029	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
1030	#else
1031	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
1032	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1033	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1034	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
1035	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1036	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1037	#endif
1038
1039	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
1040	* Asserts that the current thread IS the emulation thread (EMT) of the
1041	* specified virtual CPU or the VM is not running.
1042	*/
1043	#if defined(IN_RC) \|\| defined(IN_RING0)
1044	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1045	Assert( VMCPU_IS_EMT(pVCpu) \
1046	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
1047	#else
1048	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1049	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1050	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
1051	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1052	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1053	#endif
1054
1055	/** @def VMSTATE_IS_RUNNING
1056	* Checks if the given state indicates a running VM.
1057	*/
1058	#define VMSTATE_IS_RUNNING(a_enmVMState) \
1059	( (a_enmVMState) == VMSTATE_RUNNING \
1060	\|\| (a_enmVMState) == VMSTATE_RUNNING_LS )
1061
1062	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1063	* Checks if the VM is running.
1064	* @note This is only for pure debug assertions. No AssertReturn or similar!
1065	* @sa VMSTATE_IS_RUNNING
1066	*/
1067	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1068	( (pVM)->enmVMState == VMSTATE_RUNNING \
1069	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
1070
1071
1072	/** @def VMSTATE_IS_POWERED_ON
1073	* Checks if the given state indicates the VM is powered on.
1074	*
1075	* @note Excludes all error states, so a powered on VM that hit a fatal error,
1076	* guru meditation, state load failure or similar will not be considered
1077	* powered on by this test.
1078	*/
1079	#define VMSTATE_IS_POWERED_ON(a_enmVMState) \
1080	( (a_enmVMState) >= VMSTATE_RESUMING && (a_enmVMState) < VMSTATE_POWERING_OFF )
1081
1082	/** @def VM_ASSERT_IS_NOT_RUNNING
1083	* Asserts that the VM is not running.
1084	*/
1085	#if defined(IN_RC) \|\| defined(IN_RING0)
1086	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1087	#else
1088	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1089	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1090	#endif
1091
1092	/** @def VM_ASSERT_EMT0
1093	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1094	*/
1095	#ifdef IN_RING3
1096	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1097	#else
1098	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1099	#endif
1100
1101	/** @def VM_ASSERT_EMT0_RETURN
1102	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1103	* it isn't.
1104	*/
1105	#ifdef IN_RING3
1106	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1107	#else
1108	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1109	#endif
1110
1111
1112	/**
1113	* Asserts that the current thread is NOT the emulation thread.
1114	*/
1115	#define VM_ASSERT_OTHER_THREAD(pVM) \
1116	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1117
1118
1119	/** @def VM_ASSERT_STATE
1120	* Asserts a certain VM state.
1121	*/
1122	#define VM_ASSERT_STATE(pVM, _enmState) \
1123	AssertMsg((pVM)->enmVMState == (_enmState), \
1124	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1125
1126	/** @def VM_ASSERT_STATE_RETURN
1127	* Asserts a certain VM state and returns if it doesn't match.
1128	*/
1129	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1130	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1131	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1132	(rc))
1133
1134	/** @def VM_IS_VALID_EXT
1135	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1136	* or terminated. */
1137	#define VM_IS_VALID_EXT(pVM) \
1138	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1139	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1140	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1141	&& VM_IS_EMT(pVM))) )
1142
1143	/** @def VM_ASSERT_VALID_EXT_RETURN
1144	* Asserts a the VM handle is valid for external access, i.e. not being
1145	* destroy or terminated.
1146	*/
1147	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1148	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1149	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1150	? VMGetStateName(pVM->enmVMState) : ""), \
1151	(rc))
1152
1153	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1154	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1155	* destroy or terminated.
1156	*/
1157	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1158	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1159	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1160	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1161	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1162	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1163	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1164	(rc))
1165
1166	#endif /* !VBOX_FOR_DTRACE_LIB */
1167
1168
1169	/**
1170	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1171	*
1172	* ONLY HM and NEM MAY USE THIS!
1173	*
1174	* @param a_pVM The cross context VM structure.
1175	* @param a_bValue The new value.
1176	* @internal
1177	*/
1178	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1179	do { \
1180	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1181	ASMCompilerBarrier(); /* just to be on the safe side */ \
1182	} while (0)
1183
1184	/**
1185	* Checks whether iem-executes-all-mode is used.
1186	*
1187	* @retval true if IEM is used.
1188	* @retval false if not.
1189	*
1190	* @param a_pVM The cross context VM structure.
1191	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1192	* @internal
1193	*/
1194	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1195
1196	/**
1197	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1198	*
1199	* @retval true if either is used.
1200	* @retval false if software virtualization (raw-mode) is used.
1201	*
1202	* @param a_pVM The cross context VM structure.
1203	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1204	* @internal
1205	*/
1206	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1207
1208	/**
1209	* Checks whether HM is being used by this VM.
1210	*
1211	* @retval true if HM (VT-x/AMD-v) is used.
1212	* @retval false if not.
1213	*
1214	* @param a_pVM The cross context VM structure.
1215	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1216	* @internal
1217	*/
1218	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1219
1220	/**
1221	* Checks whether NEM is being used by this VM.
1222	*
1223	* @retval true if a native hypervisor API is used.
1224	* @retval false if not.
1225	*
1226	* @param a_pVM The cross context VM structure.
1227	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1228	* @internal
1229	*/
1230	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1231
1232
1233	/**
1234	* The cross context VM structure.
1235	*
1236	* It contains all the VM data which have to be available in all contexts.
1237	* Even if it contains all the data the idea is to use APIs not to modify all
1238	* the members all around the place. Therefore we make use of unions to hide
1239	* everything which isn't local to the current source module. This means we'll
1240	* have to pay a little bit of attention when adding new members to structures
1241	* in the unions and make sure to keep the padding sizes up to date.
1242	*
1243	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1244	*/
1245	typedef struct VM
1246	{
1247	/** The state of the VM.
1248	* This field is read only to everyone except the VM and EM. */
1249	VMSTATE volatile enmVMState;
1250	/** Forced action flags.
1251	* See the VM_FF_* \#defines. Updated atomically.
1252	*/
1253	volatile uint32_t fGlobalForcedActions;
1254	/** Pointer to the array of page descriptors for the VM structure allocation. */
1255	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1256	/** Session handle. For use when calling SUPR0 APIs. */
1257	#ifdef IN_RING0
1258	PSUPDRVSESSION pSessionUnsafe;
1259	#else
1260	PSUPDRVSESSION pSession;
1261	#endif
1262	/** Pointer to the ring-3 VM structure. */
1263	PUVM pUVM;
1264	/** Ring-3 Host Context VM Pointer. */
1265	#ifdef IN_RING0
1266	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1267	#else
1268	R3PTRTYPE(struct VM *) pVMR3;
1269	#endif
1270	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1271	R0PTRTYPE(struct VM *) pVMR0ForCall;
1272	/** Raw-mode Context VM Pointer. */
1273	uint32_t pVMRC;
1274	/** Padding for new raw-mode (long mode). */
1275	uint32_t pVMRCPadding;
1276
1277	/** The GVM VM handle. Only the GVM should modify this field. */
1278	#ifdef IN_RING0
1279	uint32_t hSelfUnsafe;
1280	#else
1281	uint32_t hSelf;
1282	#endif
1283	/** Number of virtual CPUs. */
1284	#ifdef IN_RING0
1285	uint32_t cCpusUnsafe;
1286	#else
1287	uint32_t cCpus;
1288	#endif
1289	/** CPU excution cap (1-100) */
1290	uint32_t uCpuExecutionCap;
1291
1292	/** Size of the VM structure. */
1293	uint32_t cbSelf;
1294	/** Size of the VMCPU structure. */
1295	uint32_t cbVCpu;
1296	/** Structure version number (TBD). */
1297	uint32_t uStructVersion;
1298
1299	/** @name Various items that are frequently accessed.
1300	* @{ */
1301	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1302	* This is set early during vmR3InitRing3 by HM or NEM. */
1303	uint8_t const bMainExecutionEngine;
1304
1305	/** Hardware VM support is available and enabled.
1306	* Determined very early during init.
1307	* This is placed here for performance reasons.
1308	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1309	bool fHMEnabled;
1310	/** @} */
1311
1312	/** Alignment padding. */
1313	uint8_t uPadding1[6];
1314
1315	/** @name Debugging
1316	* @{ */
1317	/** Ring-3 Host Context VM Pointer. */
1318	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1319	/** Ring-0 Host Context VM Pointer. */
1320	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1321	/** @} */
1322
1323	/** Max EMT hash lookup collisions (in GVMM). */
1324	uint8_t cMaxEmtHashCollisions;
1325
1326	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1327	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1328
1329	/** CPUM part. */
1330	union
1331	{
1332	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
1333	struct CPUM s;
1334	#endif
1335	#ifdef VBOX_INCLUDED_vmm_cpum_h
1336	/** Read only info exposed about the host and guest CPUs. */
1337	struct
1338	{
1339	/** Padding for hidden fields. */
1340	uint8_t abHidden0[64 + 48];
1341	/** Guest CPU feature information. */
1342	CPUMFEATURES GuestFeatures;
1343	} const ro;
1344	#endif
1345	/** @todo this is rather bloated because of static MSR range allocation.
1346	* Probably a good idea to move it to a separate R0 allocation... */
1347	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1348	} cpum;
1349
1350	/** PGM part.
1351	* @note Aligned on 16384 boundrary for zero and mmio page storage. */
1352	union
1353	{
1354	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1355	struct PGM s;
1356	#endif
1357	uint8_t padding[129728]; /* multiple of 64 */
1358	} pgm;
1359
1360	/** VMM part. */
1361	union
1362	{
1363	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1364	struct VMM s;
1365	#endif
1366	uint8_t padding[1600]; /* multiple of 64 */
1367	} vmm;
1368
1369	/** HM part. */
1370	union
1371	{
1372	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1373	struct HM s;
1374	#endif
1375	uint8_t padding[5504]; /* multiple of 64 */
1376	} hm;
1377
1378	/** TRPM part. */
1379	union
1380	{
1381	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1382	struct TRPM s;
1383	#endif
1384	uint8_t padding[2048]; /* multiple of 64 */
1385	} trpm;
1386
1387	/** SELM part. */
1388	union
1389	{
1390	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1391	struct SELM s;
1392	#endif
1393	uint8_t padding[768]; /* multiple of 64 */
1394	} selm;
1395
1396	/** MM part. */
1397	union
1398	{
1399	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1400	struct MM s;
1401	#endif
1402	uint8_t padding[192]; /* multiple of 64 */
1403	} mm;
1404
1405	/** PDM part. */
1406	union
1407	{
1408	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1409	struct PDM s;
1410	#endif
1411	uint8_t padding[22400]; /* multiple of 64 */
1412	} pdm;
1413
1414	/** IOM part. */
1415	union
1416	{
1417	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1418	struct IOM s;
1419	#endif
1420	uint8_t padding[1152]; /* multiple of 64 */
1421	} iom;
1422
1423	/** EM part. */
1424	union
1425	{
1426	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1427	struct EM s;
1428	#endif
1429	uint8_t padding[256]; /* multiple of 64 */
1430	} em;
1431
1432	/** NEM part. */
1433	union
1434	{
1435	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1436	struct NEM s;
1437	#endif
1438	uint8_t padding[4608]; /* multiple of 64 */
1439	} nem;
1440
1441	/** TM part. */
1442	union
1443	{
1444	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1445	struct TM s;
1446	#endif
1447	uint8_t padding[10112]; /* multiple of 64 */
1448	} tm;
1449
1450	/** DBGF part. */
1451	union
1452	{
1453	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1454	struct DBGF s;
1455	#endif
1456	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1457	/** Read only info exposed about interrupt breakpoints and selected events. */
1458	struct
1459	{
1460	/** Bitmap of enabled hardware interrupt breakpoints. */
1461	uint32_t bmHardIntBreakpoints[256 / 32];
1462	/** Bitmap of enabled software interrupt breakpoints. */
1463	uint32_t bmSoftIntBreakpoints[256 / 32];
1464	/** Bitmap of selected events.
1465	* This includes non-selectable events too for simplicity, we maintain the
1466	* state for some of these, as it may come in handy. */
1467	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1468	/** Enabled hardware interrupt breakpoints. */
1469	uint32_t cHardIntBreakpoints;
1470	/** Enabled software interrupt breakpoints. */
1471	uint32_t cSoftIntBreakpoints;
1472	/** The number of selected events. */
1473	uint32_t cSelectedEvents;
1474	/** The number of enabled hardware breakpoints. */
1475	uint8_t cEnabledHwBreakpoints;
1476	/** The number of enabled hardware I/O breakpoints. */
1477	uint8_t cEnabledHwIoBreakpoints;
1478	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1479	/** The number of enabled INT3 breakpoints. */
1480	uint32_t volatile cEnabledInt3Breakpoints;
1481	} const ro;
1482	#endif
1483	uint8_t padding[2432]; /* multiple of 64 */
1484	} dbgf;
1485
1486	/** SSM part. */
1487	union
1488	{
1489	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1490	struct SSM s;
1491	#endif
1492	uint8_t padding[128]; /* multiple of 64 */
1493	} ssm;
1494
1495	union
1496	{
1497	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1498	struct GIM s;
1499	#endif
1500	uint8_t padding[448]; /* multiple of 64 */
1501	} gim;
1502
1503	#if defined(VBOX_VMM_TARGET_ARMV8)
1504	union
1505	{
1506	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
1507	struct GIC s;
1508	# endif
1509	uint8_t padding[128]; /* multiple of 8 */
1510	} gic;
1511	#else
1512	union
1513	{
1514	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1515	struct APIC s;
1516	# endif
1517	uint8_t padding[128]; /* multiple of 8 */
1518	} apic;
1519	#endif
1520
1521	/* ---- begin small stuff ---- */
1522
1523	/** VM part. */
1524	union
1525	{
1526	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1527	struct VMINT s;
1528	#endif
1529	uint8_t padding[32]; /* multiple of 8 */
1530	} vm;
1531
1532	/** CFGM part. */
1533	union
1534	{
1535	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1536	struct CFGM s;
1537	#endif
1538	uint8_t padding[8]; /* multiple of 8 */
1539	} cfgm;
1540
1541	/** IEM part. */
1542	union
1543	{
1544	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1545	struct IEM s;
1546	#endif
1547	uint8_t padding[16]; /* multiple of 8 */
1548	} iem;
1549
1550	/** Statistics for ring-0 only components. */
1551	struct
1552	{
1553	/** GMMR0 stats. */
1554	struct
1555	{
1556	/** Chunk TLB hits. */
1557	uint64_t cChunkTlbHits;
1558	/** Chunk TLB misses. */
1559	uint64_t cChunkTlbMisses;
1560	} gmm;
1561	uint64_t au64Padding[6]; /* probably more comming here... */
1562	} R0Stats;
1563
1564	union
1565	{
1566	#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1567	struct GCM s;
1568	#endif
1569	uint8_t padding[8]; /* multiple of 8 */
1570	} gcm;
1571
1572	/** Padding for aligning the structure size on a page boundrary. */
1573	uint8_t abAlignment2[0x3A80 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1574
1575	/* ---- end small stuff ---- */
1576
1577	/** Array of VMCPU ring-3 pointers. */
1578	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1579
1580	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1581	} VM;
1582	#ifndef VBOX_FOR_DTRACE_LIB
1583	//AssertCompileSizeAlignment(VM, 16384);
1584	#endif
1585
1586
1587	#ifdef IN_RC
1588	RT_C_DECLS_BEGIN
1589
1590	/** The VM structure.
1591	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1592	* globals which we should avoid using.
1593	*/
1594	extern DECLIMPORT(VM) g_VM;
1595
1596	/** The VMCPU structure for virtual CPU \#0.
1597	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1598	* globals which we should avoid using.
1599	*/
1600	extern DECLIMPORT(VMCPU) g_VCpu0;
1601
1602	RT_C_DECLS_END
1603	#endif
1604
1605	/** @} */
1606
1607	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1608

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source: vbox/trunk/include/VBox/vmm/vm.h@ 105506

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