pdmdev.h@ 107113

Last change on this file since 107113 was 107113, checked in by vboxsync, 6 months ago
VMM: bugref:10759 Restructure the APIC to allow different backends to be used.
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1	/** @file
2	* PDM - Pluggable Device Manager, Devices.
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pdmdev_h
37	#define VBOX_INCLUDED_vmm_pdmdev_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmcritsectrw.h>
44	#include <VBox/vmm/pdmqueue.h>
45	#include <VBox/vmm/pdmtask.h>
46	#ifdef IN_RING3
47	# include <VBox/vmm/pdmthread.h>
48	#endif
49	#include <VBox/vmm/pdmifs.h>
50	#include <VBox/vmm/pdmins.h>
51	#include <VBox/vmm/pdmcommon.h>
52	#include <VBox/vmm/pdmpcidev.h>
53	#include <VBox/vmm/iom.h>
54	#include <VBox/vmm/mm.h>
55	#include <VBox/vmm/tm.h>
56	#include <VBox/vmm/ssm.h>
57	#include <VBox/vmm/cfgm.h>
58	#include <VBox/vmm/cpum.h>
59	#include <VBox/vmm/dbgf.h>
60	#include <VBox/vmm/pgm.h> /* PGMR3HandlerPhysicalTypeRegister() argument types. */
61	#include <VBox/vmm/gim.h>
62	#include <VBox/err.h> /* VINF_EM_DBG_STOP, also 120+ source files expecting this. */
63	#include <VBox/msi.h>
64	#include <iprt/stdarg.h>
65	#include <iprt/list.h>
66
67
68	RT_C_DECLS_BEGIN
69
70	/** @defgroup grp_pdm_device The PDM Devices API
71	* @ingroup grp_pdm
72	* @{
73	*/
74
75	/**
76	* Construct a device instance for a VM.
77	*
78	* @returns VBox status.
79	* @param pDevIns The device instance data. If the registration structure
80	* is needed, it can be accessed thru pDevIns->pReg.
81	* @param iInstance Instance number. Use this to figure out which registers
82	* and such to use. The instance number is also found in
83	* pDevIns->iInstance, but since it's likely to be
84	* frequently used PDM passes it as parameter.
85	* @param pCfg Configuration node handle for the driver. This is
86	* expected to be in high demand in the constructor and is
87	* therefore passed as an argument. When using it at other
88	* times, it can be found in pDevIns->pCfg.
89	*/
90	typedef DECLCALLBACKTYPE(int, FNPDMDEVCONSTRUCT,(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg));
91	/** Pointer to a FNPDMDEVCONSTRUCT() function. */
92	typedef FNPDMDEVCONSTRUCT *PFNPDMDEVCONSTRUCT;
93
94	/**
95	* Destruct a device instance.
96	*
97	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
98	* resources can be freed correctly.
99	*
100	* @returns VBox status.
101	* @param pDevIns The device instance data.
102	*
103	* @remarks The device critical section is not entered. The routine may delete
104	* the critical section, so the caller cannot exit it.
105	*/
106	typedef DECLCALLBACKTYPE(int, FNPDMDEVDESTRUCT,(PPDMDEVINS pDevIns));
107	/** Pointer to a FNPDMDEVDESTRUCT() function. */
108	typedef FNPDMDEVDESTRUCT *PFNPDMDEVDESTRUCT;
109
110	/**
111	* Device relocation callback.
112	*
113	* This is called when the instance data has been relocated in raw-mode context
114	* (RC). It is also called when the RC hypervisor selects changes. The device
115	* must fixup all necessary pointers and re-query all interfaces to other RC
116	* devices and drivers.
117	*
118	* Before the RC code is executed the first time, this function will be called
119	* with a 0 delta so RC pointer calculations can be one in one place.
120	*
121	* @param pDevIns Pointer to the device instance.
122	* @param offDelta The relocation delta relative to the old location.
123	*
124	* @remarks A relocation CANNOT fail.
125	*
126	* @remarks The device critical section is not entered. The relocations should
127	* not normally require any locking.
128	*/
129	typedef DECLCALLBACKTYPE(void, FNPDMDEVRELOCATE,(PPDMDEVINS pDevIns, RTGCINTPTR offDelta));
130	/** Pointer to a FNPDMDEVRELOCATE() function. */
131	typedef FNPDMDEVRELOCATE *PFNPDMDEVRELOCATE;
132
133	/**
134	* Power On notification.
135	*
136	* @param pDevIns The device instance data.
137	*
138	* @remarks Caller enters the device critical section.
139	*/
140	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWERON,(PPDMDEVINS pDevIns));
141	/** Pointer to a FNPDMDEVPOWERON() function. */
142	typedef FNPDMDEVPOWERON *PFNPDMDEVPOWERON;
143
144	/**
145	* Reset notification.
146	*
147	* @param pDevIns The device instance data.
148	*
149	* @remarks Caller enters the device critical section.
150	*/
151	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESET,(PPDMDEVINS pDevIns));
152	/** Pointer to a FNPDMDEVRESET() function. */
153	typedef FNPDMDEVRESET *PFNPDMDEVRESET;
154
155	/**
156	* Soft reset notification.
157	*
158	* This is mainly for emulating the 286 style protected mode exits, in which
159	* most devices should remain in their current state.
160	*
161	* @param pDevIns The device instance data.
162	* @param fFlags PDMVMRESET_F_XXX (only bits relevant to soft resets).
163	*
164	* @remarks Caller enters the device critical section.
165	*/
166	typedef DECLCALLBACKTYPE(void, FNPDMDEVSOFTRESET,(PPDMDEVINS pDevIns, uint32_t fFlags));
167	/** Pointer to a FNPDMDEVSOFTRESET() function. */
168	typedef FNPDMDEVSOFTRESET *PFNPDMDEVSOFTRESET;
169
170	/** @name PDMVMRESET_F_XXX - VM reset flags.
171	* These flags are used both for FNPDMDEVSOFTRESET and for hardware signalling
172	* reset via PDMDevHlpVMReset.
173	* @{ */
174	/** Unknown reason. */
175	#define PDMVMRESET_F_UNKNOWN UINT32_C(0x00000000)
176	/** GIM triggered reset. */
177	#define PDMVMRESET_F_GIM UINT32_C(0x00000001)
178	/** The last source always causing hard resets. */
179	#define PDMVMRESET_F_LAST_ALWAYS_HARD PDMVMRESET_F_GIM
180	/** ACPI triggered reset. */
181	#define PDMVMRESET_F_ACPI UINT32_C(0x0000000c)
182	/** PS/2 system port A (92h) reset. */
183	#define PDMVMRESET_F_PORT_A UINT32_C(0x0000000d)
184	/** Keyboard reset. */
185	#define PDMVMRESET_F_KBD UINT32_C(0x0000000e)
186	/** Tripple fault. */
187	#define PDMVMRESET_F_TRIPLE_FAULT UINT32_C(0x0000000f)
188	/** Reset source mask. */
189	#define PDMVMRESET_F_SRC_MASK UINT32_C(0x0000000f)
190	/** @} */
191
192	/**
193	* Suspend notification.
194	*
195	* @param pDevIns The device instance data.
196	* @thread EMT(0)
197	*
198	* @remarks Caller enters the device critical section.
199	*/
200	typedef DECLCALLBACKTYPE(void, FNPDMDEVSUSPEND,(PPDMDEVINS pDevIns));
201	/** Pointer to a FNPDMDEVSUSPEND() function. */
202	typedef FNPDMDEVSUSPEND *PFNPDMDEVSUSPEND;
203
204	/**
205	* Resume notification.
206	*
207	* @param pDevIns The device instance data.
208	*
209	* @remarks Caller enters the device critical section.
210	*/
211	typedef DECLCALLBACKTYPE(void, FNPDMDEVRESUME,(PPDMDEVINS pDevIns));
212	/** Pointer to a FNPDMDEVRESUME() function. */
213	typedef FNPDMDEVRESUME *PFNPDMDEVRESUME;
214
215	/**
216	* Power Off notification.
217	*
218	* This is always called when VMR3PowerOff is called.
219	* There will be no callback when hot plugging devices.
220	*
221	* @param pDevIns The device instance data.
222	* @thread EMT(0)
223	*
224	* @remarks Caller enters the device critical section.
225	*/
226	typedef DECLCALLBACKTYPE(void, FNPDMDEVPOWEROFF,(PPDMDEVINS pDevIns));
227	/** Pointer to a FNPDMDEVPOWEROFF() function. */
228	typedef FNPDMDEVPOWEROFF *PFNPDMDEVPOWEROFF;
229
230	/**
231	* Attach command.
232	*
233	* This is called to let the device attach to a driver for a specified LUN
234	* at runtime. This is not called during VM construction, the device
235	* constructor has to attach to all the available drivers.
236	*
237	* This is like plugging in the keyboard or mouse after turning on the PC.
238	*
239	* @returns VBox status code.
240	* @param pDevIns The device instance.
241	* @param iLUN The logical unit which is being attached.
242	* @param fFlags Flags, combination of the PDM_TACH_FLAGS_* \#defines.
243	*
244	* @remarks Caller enters the device critical section.
245	*/
246	typedef DECLCALLBACKTYPE(int, FNPDMDEVATTACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
247	/** Pointer to a FNPDMDEVATTACH() function. */
248	typedef FNPDMDEVATTACH *PFNPDMDEVATTACH;
249
250	/**
251	* Detach notification.
252	*
253	* This is called when a driver is detaching itself from a LUN of the device.
254	* The device should adjust its state to reflect this.
255	*
256	* This is like unplugging the network cable to use it for the laptop or
257	* something while the PC is still running.
258	*
259	* @param pDevIns The device instance.
260	* @param iLUN The logical unit which is being detached.
261	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
262	*
263	* @remarks Caller enters the device critical section.
264	*/
265	typedef DECLCALLBACKTYPE(void, FNPDMDEVDETACH,(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags));
266	/** Pointer to a FNPDMDEVDETACH() function. */
267	typedef FNPDMDEVDETACH *PFNPDMDEVDETACH;
268
269	/**
270	* Query the base interface of a logical unit.
271	*
272	* @returns VBOX status code.
273	* @param pDevIns The device instance.
274	* @param iLUN The logicial unit to query.
275	* @param ppBase Where to store the pointer to the base interface of the LUN.
276	*
277	* @remarks The device critical section is not entered.
278	*/
279	typedef DECLCALLBACKTYPE(int, FNPDMDEVQUERYINTERFACE,(PPDMDEVINS pDevIns, unsigned iLUN, PPDMIBASE *ppBase));
280	/** Pointer to a FNPDMDEVQUERYINTERFACE() function. */
281	typedef FNPDMDEVQUERYINTERFACE *PFNPDMDEVQUERYINTERFACE;
282
283	/**
284	* Init complete notification (after ring-0 & RC init since 5.1).
285	*
286	* This can be done to do communication with other devices and other
287	* initialization which requires everything to be in place.
288	*
289	* @returns VBOX status code.
290	* @param pDevIns The device instance.
291	*
292	* @remarks Caller enters the device critical section.
293	*/
294	typedef DECLCALLBACKTYPE(int, FNPDMDEVINITCOMPLETE,(PPDMDEVINS pDevIns));
295	/** Pointer to a FNPDMDEVINITCOMPLETE() function. */
296	typedef FNPDMDEVINITCOMPLETE *PFNPDMDEVINITCOMPLETE;
297
298
299	/**
300	* The context of a pfnMemSetup call.
301	*/
302	typedef enum PDMDEVMEMSETUPCTX
303	{
304	/** Invalid zero value. */
305	PDMDEVMEMSETUPCTX_INVALID = 0,
306	/** After construction. */
307	PDMDEVMEMSETUPCTX_AFTER_CONSTRUCTION,
308	/** After reset. */
309	PDMDEVMEMSETUPCTX_AFTER_RESET,
310	/** Type size hack. */
311	PDMDEVMEMSETUPCTX_32BIT_HACK = 0x7fffffff
312	} PDMDEVMEMSETUPCTX;
313
314
315	/**
316	* PDM Device Registration Structure.
317	*
318	* This structure is used when registering a device from VBoxInitDevices() in HC
319	* Ring-3. PDM will continue use till the VM is terminated.
320	*
321	* @note The first part is the same in every context.
322	*/
323	typedef struct PDMDEVREGR3
324	{
325	/** Structure version. PDM_DEVREGR3_VERSION defines the current version. */
326	uint32_t u32Version;
327	/** Reserved, must be zero. */
328	uint32_t uReserved0;
329	/** Device name, must match the ring-3 one. */
330	char szName[32];
331	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
332	uint32_t fFlags;
333	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
334	uint32_t fClass;
335	/** Maximum number of instances (per VM). */
336	uint32_t cMaxInstances;
337	/** The shared data structure version number. */
338	uint32_t uSharedVersion;
339	/** Size of the instance data. */
340	uint32_t cbInstanceShared;
341	/** Size of the ring-0 instance data. */
342	uint32_t cbInstanceCC;
343	/** Size of the raw-mode instance data. */
344	uint32_t cbInstanceRC;
345	/** Max number of PCI devices. */
346	uint16_t cMaxPciDevices;
347	/** Max number of MSI-X vectors in any of the PCI devices. */
348	uint16_t cMaxMsixVectors;
349	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
350	* remain unchanged from registration till VM destruction. */
351	const char *pszDescription;
352
353	/** Name of the raw-mode context module (no path).
354	* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
355	const char *pszRCMod;
356	/** Name of the ring-0 module (no path).
357	* Only evalutated if PDM_DEVREG_FLAGS_R0 is set. */
358	const char *pszR0Mod;
359
360	/** Construct instance - required. */
361	PFNPDMDEVCONSTRUCT pfnConstruct;
362	/** Destruct instance - optional.
363	* Critical section NOT entered (will be destroyed). */
364	PFNPDMDEVDESTRUCT pfnDestruct;
365	/** Relocation command - optional.
366	* Critical section NOT entered. */
367	PFNPDMDEVRELOCATE pfnRelocate;
368	/**
369	* Memory setup callback.
370	*
371	* @param pDevIns The device instance data.
372	* @param enmCtx Indicates the context of the call.
373	* @remarks The critical section is entered prior to calling this method.
374	*/
375	DECLR3CALLBACKMEMBER(void, pfnMemSetup, (PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx));
376	/** Power on notification - optional.
377	* Critical section is entered. */
378	PFNPDMDEVPOWERON pfnPowerOn;
379	/** Reset notification - optional.
380	* Critical section is entered. */
381	PFNPDMDEVRESET pfnReset;
382	/** Suspend notification - optional.
383	* Critical section is entered. */
384	PFNPDMDEVSUSPEND pfnSuspend;
385	/** Resume notification - optional.
386	* Critical section is entered. */
387	PFNPDMDEVRESUME pfnResume;
388	/** Attach command - optional.
389	* Critical section is entered. */
390	PFNPDMDEVATTACH pfnAttach;
391	/** Detach notification - optional.
392	* Critical section is entered. */
393	PFNPDMDEVDETACH pfnDetach;
394	/** Query a LUN base interface - optional.
395	* Critical section is NOT entered. */
396	PFNPDMDEVQUERYINTERFACE pfnQueryInterface;
397	/** Init complete notification - optional.
398	* Critical section is entered. */
399	PFNPDMDEVINITCOMPLETE pfnInitComplete;
400	/** Power off notification - optional.
401	* Critical section is entered. */
402	PFNPDMDEVPOWEROFF pfnPowerOff;
403	/** Software system reset notification - optional.
404	* Critical section is entered. */
405	PFNPDMDEVSOFTRESET pfnSoftReset;
406
407	/** @name Reserved for future extensions, must be zero.
408	* @{ */
409	DECLR3CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
410	DECLR3CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
411	DECLR3CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
412	DECLR3CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
413	DECLR3CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
414	DECLR3CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
415	DECLR3CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
416	DECLR3CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
417	/** @} */
418
419	/** Initialization safty marker. */
420	uint32_t u32VersionEnd;
421	} PDMDEVREGR3;
422	/** Pointer to a PDM Device Structure. */
423	typedef PDMDEVREGR3 *PPDMDEVREGR3;
424	/** Const pointer to a PDM Device Structure. */
425	typedef PDMDEVREGR3 const *PCPDMDEVREGR3;
426	/** Current DEVREGR3 version number. */
427	#define PDM_DEVREGR3_VERSION PDM_VERSION_MAKE(0xffff, 4, 0)
428
429
430	/** PDM Device Flags.
431	* @{ */
432	/** This flag is used to indicate that the device has a R0 component. */
433	#define PDM_DEVREG_FLAGS_R0 UINT32_C(0x00000001)
434	/** Requires the ring-0 component, ignore configuration values. */
435	#define PDM_DEVREG_FLAGS_REQUIRE_R0 UINT32_C(0x00000002)
436	/** Requires the ring-0 component, ignore configuration values. */
437	#define PDM_DEVREG_FLAGS_OPT_IN_R0 UINT32_C(0x00000004)
438
439	/** This flag is used to indicate that the device has a RC component. */
440	#define PDM_DEVREG_FLAGS_RC UINT32_C(0x00000010)
441	/** Requires the raw-mode component, ignore configuration values. */
442	#define PDM_DEVREG_FLAGS_REQUIRE_RC UINT32_C(0x00000020)
443	/** Requires the raw-mode component, ignore configuration values. */
444	#define PDM_DEVREG_FLAGS_OPT_IN_RC UINT32_C(0x00000040)
445
446	/** Convenience: PDM_DEVREG_FLAGS_R0 + PDM_DEVREG_FLAGS_RC */
447	#define PDM_DEVREG_FLAGS_RZ (PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC)
448
449	/** @def PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT
450	* The bit count for the current host.
451	* @note Superfluous, but still around for hysterical raisins. */
452	#if HC_ARCH_BITS == 32
453	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000100)
454	#elif HC_ARCH_BITS == 64
455	# define PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT UINT32_C(0x00000200)
456	#else
457	# error Unsupported HC_ARCH_BITS value.
458	#endif
459	/** The host bit count mask. */
460	#define PDM_DEVREG_FLAGS_HOST_BITS_MASK UINT32_C(0x00000300)
461
462	/** The device support only 32-bit guests. */
463	#define PDM_DEVREG_FLAGS_GUEST_BITS_32 UINT32_C(0x00001000)
464	/** The device support only 64-bit guests. */
465	#define PDM_DEVREG_FLAGS_GUEST_BITS_64 UINT32_C(0x00002000)
466	/** The device support both 32-bit & 64-bit guests. */
467	#define PDM_DEVREG_FLAGS_GUEST_BITS_32_64 UINT32_C(0x00003000)
468	/** @def PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT
469	* The guest bit count for the current compilation. */
470	#if GC_ARCH_BITS == 32
471	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32
472	#elif GC_ARCH_BITS == 64
473	# define PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT PDM_DEVREG_FLAGS_GUEST_BITS_32_64
474	#else
475	# error Unsupported GC_ARCH_BITS value.
476	#endif
477	/** The guest bit count mask. */
478	#define PDM_DEVREG_FLAGS_GUEST_BITS_MASK UINT32_C(0x00003000)
479
480	/** A convenience. */
481	#define PDM_DEVREG_FLAGS_DEFAULT_BITS (PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT)
482
483	/** Indicates that the device needs to be notified before the drivers when suspending. */
484	#define PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION UINT32_C(0x00010000)
485	/** Indicates that the device needs to be notified before the drivers when powering off. */
486	#define PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION UINT32_C(0x00020000)
487	/** Indicates that the device needs to be notified before the drivers when resetting. */
488	#define PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION UINT32_C(0x00040000)
489
490	/** This flag is used to indicate that the device has been converted to the
491	* new device style. */
492	#define PDM_DEVREG_FLAGS_NEW_STYLE UINT32_C(0x80000000)
493
494	/** @} */
495
496
497	/** PDM Device Classes.
498	* The order is important, lower bit earlier instantiation.
499	* @{ */
500	/** Architecture device. */
501	#define PDM_DEVREG_CLASS_ARCH RT_BIT(0)
502	/** Architecture BIOS device. */
503	#define PDM_DEVREG_CLASS_ARCH_BIOS RT_BIT(1)
504	/** PCI bus brigde. */
505	#define PDM_DEVREG_CLASS_BUS_PCI RT_BIT(2)
506	/** PCI built-in device (e.g. PCI root complex devices). */
507	#define PDM_DEVREG_CLASS_PCI_BUILTIN RT_BIT(3)
508	/** Input device (mouse, keyboard, joystick, HID, ...). */
509	#define PDM_DEVREG_CLASS_INPUT RT_BIT(4)
510	/** Interrupt controller (PIC). */
511	#define PDM_DEVREG_CLASS_PIC RT_BIT(5)
512	/** Interval controoler (PIT). */
513	#define PDM_DEVREG_CLASS_PIT RT_BIT(6)
514	/** RTC/CMOS. */
515	#define PDM_DEVREG_CLASS_RTC RT_BIT(7)
516	/** DMA controller. */
517	#define PDM_DEVREG_CLASS_DMA RT_BIT(8)
518	/** VMM Device. */
519	#define PDM_DEVREG_CLASS_VMM_DEV RT_BIT(9)
520	/** Graphics device, like VGA. */
521	#define PDM_DEVREG_CLASS_GRAPHICS RT_BIT(10)
522	/** Storage controller device. */
523	#define PDM_DEVREG_CLASS_STORAGE RT_BIT(11)
524	/** Network interface controller. */
525	#define PDM_DEVREG_CLASS_NETWORK RT_BIT(12)
526	/** Audio. */
527	#define PDM_DEVREG_CLASS_AUDIO RT_BIT(13)
528	/** USB HIC. */
529	#define PDM_DEVREG_CLASS_BUS_USB RT_BIT(14)
530	/** ACPI. */
531	#define PDM_DEVREG_CLASS_ACPI RT_BIT(15)
532	/** Serial controller device. */
533	#define PDM_DEVREG_CLASS_SERIAL RT_BIT(16)
534	/** Parallel controller device */
535	#define PDM_DEVREG_CLASS_PARALLEL RT_BIT(17)
536	/** Host PCI pass-through device */
537	#define PDM_DEVREG_CLASS_HOST_DEV RT_BIT(18)
538	/** GPIO device */
539	#define PDM_DEVREG_CLASS_GPIO RT_BIT(19)
540	/** Misc devices (always last). */
541	#define PDM_DEVREG_CLASS_MISC RT_BIT(31)
542	/** @} */
543
544
545	/**
546	* PDM Device Registration Structure, ring-0.
547	*
548	* This structure is used when registering a device from VBoxInitDevices() in HC
549	* Ring-0. PDM will continue use till the VM is terminated.
550	*/
551	typedef struct PDMDEVREGR0
552	{
553	/** Structure version. PDM_DEVREGR0_VERSION defines the current version. */
554	uint32_t u32Version;
555	/** Reserved, must be zero. */
556	uint32_t uReserved0;
557	/** Device name, must match the ring-3 one. */
558	char szName[32];
559	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
560	uint32_t fFlags;
561	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
562	uint32_t fClass;
563	/** Maximum number of instances (per VM). */
564	uint32_t cMaxInstances;
565	/** The shared data structure version number. */
566	uint32_t uSharedVersion;
567	/** Size of the instance data. */
568	uint32_t cbInstanceShared;
569	/** Size of the ring-0 instance data. */
570	uint32_t cbInstanceCC;
571	/** Size of the raw-mode instance data. */
572	uint32_t cbInstanceRC;
573	/** Max number of PCI devices. */
574	uint16_t cMaxPciDevices;
575	/** Max number of MSI-X vectors in any of the PCI devices. */
576	uint16_t cMaxMsixVectors;
577	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
578	* remain unchanged from registration till VM destruction. */
579	const char *pszDescription;
580
581	/**
582	* Early construction callback (optional).
583	*
584	* This is called right after the device instance structure has been allocated
585	* and before the ring-3 constructor gets called.
586	*
587	* @returns VBox status code.
588	* @param pDevIns The device instance data.
589	* @note The destructure is always called, regardless of the return status.
590	*/
591	DECLR0CALLBACKMEMBER(int, pfnEarlyConstruct, (PPDMDEVINS pDevIns));
592
593	/**
594	* Regular construction callback (optional).
595	*
596	* This is called after (or during) the ring-3 constructor.
597	*
598	* @returns VBox status code.
599	* @param pDevIns The device instance data.
600	* @note The destructure is always called, regardless of the return status.
601	*/
602	DECLR0CALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
603
604	/**
605	* Destructor (optional).
606	*
607	* This is called after the ring-3 destruction. This is not called if ring-3
608	* fails to trigger it (e.g. process is killed or crashes).
609	*
610	* @param pDevIns The device instance data.
611	*/
612	DECLR0CALLBACKMEMBER(void, pfnDestruct, (PPDMDEVINS pDevIns));
613
614	/**
615	* Final destructor (optional).
616	*
617	* This is called right before the memory is freed, which happens when the
618	* VM/GVM object is destroyed. This is always called.
619	*
620	* @param pDevIns The device instance data.
621	*/
622	DECLR0CALLBACKMEMBER(void, pfnFinalDestruct, (PPDMDEVINS pDevIns));
623
624	/**
625	* Generic request handler (optional).
626	*
627	* @param pDevIns The device instance data.
628	* @param uReq Device specific request.
629	* @param uArg Request argument.
630	*/
631	DECLR0CALLBACKMEMBER(int, pfnRequest, (PPDMDEVINS pDevIns, uint32_t uReq, uint64_t uArg));
632
633	/** @name Reserved for future extensions, must be zero.
634	* @{ */
635	DECLR0CALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
636	DECLR0CALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
637	DECLR0CALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
638	DECLR0CALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
639	DECLR0CALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
640	DECLR0CALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
641	DECLR0CALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
642	DECLR0CALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
643	/** @} */
644
645	/** Initialization safty marker. */
646	uint32_t u32VersionEnd;
647	} PDMDEVREGR0;
648	/** Pointer to a ring-0 PDM device registration structure. */
649	typedef PDMDEVREGR0 *PPDMDEVREGR0;
650	/** Pointer to a const ring-0 PDM device registration structure. */
651	typedef PDMDEVREGR0 const *PCPDMDEVREGR0;
652	/** Current DEVREGR0 version number. */
653	#define PDM_DEVREGR0_VERSION PDM_VERSION_MAKE(0xff80, 1, 0)
654
655
656	/**
657	* PDM Device Registration Structure, raw-mode
658	*
659	* At the moment, this structure is mostly here to match the other two contexts.
660	*/
661	typedef struct PDMDEVREGRC
662	{
663	/** Structure version. PDM_DEVREGRC_VERSION defines the current version. */
664	uint32_t u32Version;
665	/** Reserved, must be zero. */
666	uint32_t uReserved0;
667	/** Device name, must match the ring-3 one. */
668	char szName[32];
669	/** Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
670	uint32_t fFlags;
671	/** Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
672	uint32_t fClass;
673	/** Maximum number of instances (per VM). */
674	uint32_t cMaxInstances;
675	/** The shared data structure version number. */
676	uint32_t uSharedVersion;
677	/** Size of the instance data. */
678	uint32_t cbInstanceShared;
679	/** Size of the ring-0 instance data. */
680	uint32_t cbInstanceCC;
681	/** Size of the raw-mode instance data. */
682	uint32_t cbInstanceRC;
683	/** Max number of PCI devices. */
684	uint16_t cMaxPciDevices;
685	/** Max number of MSI-X vectors in any of the PCI devices. */
686	uint16_t cMaxMsixVectors;
687	/** The description of the device. The UTF-8 string pointed to shall, like this structure,
688	* remain unchanged from registration till VM destruction. */
689	const char *pszDescription;
690
691	/**
692	* Constructor callback.
693	*
694	* This is called much later than both the ring-0 and ring-3 constructors, since
695	* raw-mode v2 require a working VMM to run actual code.
696	*
697	* @returns VBox status code.
698	* @param pDevIns The device instance data.
699	* @note The destructure is always called, regardless of the return status.
700	*/
701	DECLRGCALLBACKMEMBER(int, pfnConstruct, (PPDMDEVINS pDevIns));
702
703	/** @name Reserved for future extensions, must be zero.
704	* @{ */
705	DECLRCCALLBACKMEMBER(int, pfnReserved0, (PPDMDEVINS pDevIns));
706	DECLRCCALLBACKMEMBER(int, pfnReserved1, (PPDMDEVINS pDevIns));
707	DECLRCCALLBACKMEMBER(int, pfnReserved2, (PPDMDEVINS pDevIns));
708	DECLRCCALLBACKMEMBER(int, pfnReserved3, (PPDMDEVINS pDevIns));
709	DECLRCCALLBACKMEMBER(int, pfnReserved4, (PPDMDEVINS pDevIns));
710	DECLRCCALLBACKMEMBER(int, pfnReserved5, (PPDMDEVINS pDevIns));
711	DECLRCCALLBACKMEMBER(int, pfnReserved6, (PPDMDEVINS pDevIns));
712	DECLRCCALLBACKMEMBER(int, pfnReserved7, (PPDMDEVINS pDevIns));
713	/** @} */
714
715	/** Initialization safty marker. */
716	uint32_t u32VersionEnd;
717	} PDMDEVREGRC;
718	/** Pointer to a raw-mode PDM device registration structure. */
719	typedef PDMDEVREGRC *PPDMDEVREGRC;
720	/** Pointer to a const raw-mode PDM device registration structure. */
721	typedef PDMDEVREGRC const *PCPDMDEVREGRC;
722	/** Current DEVREGRC version number. */
723	#define PDM_DEVREGRC_VERSION PDM_VERSION_MAKE(0xff81, 1, 0)
724
725
726
727	/** @def PDM_DEVREG_VERSION
728	* Current DEVREG version number. */
729	/** @typedef PDMDEVREGR3
730	* A current context PDM device registration structure. */
731	/** @typedef PPDMDEVREGR3
732	* Pointer to a current context PDM device registration structure. */
733	/** @typedef PCPDMDEVREGR3
734	* Pointer to a const current context PDM device registration structure. */
735	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
736	# define PDM_DEVREG_VERSION PDM_DEVREGR3_VERSION
737	typedef PDMDEVREGR3 PDMDEVREG;
738	typedef PPDMDEVREGR3 PPDMDEVREG;
739	typedef PCPDMDEVREGR3 PCPDMDEVREG;
740	#elif defined(IN_RING0)
741	# define PDM_DEVREG_VERSION PDM_DEVREGR0_VERSION
742	typedef PDMDEVREGR0 PDMDEVREG;
743	typedef PPDMDEVREGR0 PPDMDEVREG;
744	typedef PCPDMDEVREGR0 PCPDMDEVREG;
745	#elif defined(IN_RC)
746	# define PDM_DEVREG_VERSION PDM_DEVREGRC_VERSION
747	typedef PDMDEVREGRC PDMDEVREG;
748	typedef PPDMDEVREGRC PPDMDEVREG;
749	typedef PCPDMDEVREGRC PCPDMDEVREG;
750	#else
751	# error "Not IN_RING3, IN_RING0 or IN_RC"
752	#endif
753
754	/**
755	* The PDM APIC device registration structure.
756	*/
757	extern const PDMDEVREG g_DeviceAPIC;
758
759	/**
760	* Device registrations for ring-0 modules.
761	*
762	* This structure is used directly and must therefore reside in persistent
763	* memory (i.e. the data section).
764	*/
765	typedef struct PDMDEVMODREGR0
766	{
767	/** The structure version (PDM_DEVMODREGR0_VERSION). */
768	uint32_t u32Version;
769	/** Number of devices in the array papDevRegs points to. */
770	uint32_t cDevRegs;
771	/** Pointer to device registration structures. */
772	PCPDMDEVREGR0 *papDevRegs;
773	/** The ring-0 module handle - PDM internal, fingers off. */
774	void *hMod;
775	/** List entry - PDM internal, fingers off. */
776	RTLISTNODE ListEntry;
777	} PDMDEVMODREGR0;
778	/** Pointer to device registriations for a ring-0 module. */
779	typedef PDMDEVMODREGR0 *PPDMDEVMODREGR0;
780	/** Current PDMDEVMODREGR0 version number. */
781	#define PDM_DEVMODREGR0_VERSION PDM_VERSION_MAKE(0xff85, 1, 0)
782
783
784	/** @name IRQ Level for use with the *SetIrq APIs.
785	* @{
786	*/
787	/** Assert the IRQ (can assume value 1). */
788	#define PDM_IRQ_LEVEL_HIGH RT_BIT(0)
789	/** Deassert the IRQ (can assume value 0). */
790	#define PDM_IRQ_LEVEL_LOW 0
791	/** flip-flop - deassert and then assert the IRQ again immediately (PIC) /
792	* automatically deasserts it after delivery to the APIC (IOAPIC).
793	* @note Only suitable for edge trigger interrupts. */
794	#define PDM_IRQ_LEVEL_FLIP_FLOP (RT_BIT(1) \| PDM_IRQ_LEVEL_HIGH)
795	/** @} */
796
797	/**
798	* Registration record for MSI/MSI-X emulation.
799	*/
800	typedef struct PDMMSIREG
801	{
802	/** Number of MSI interrupt vectors, 0 if MSI not supported */
803	uint16_t cMsiVectors;
804	/** Offset of MSI capability */
805	uint8_t iMsiCapOffset;
806	/** Offset of next capability to MSI */
807	uint8_t iMsiNextOffset;
808	/** If we support 64-bit MSI addressing */
809	bool fMsi64bit;
810	/** If we do not support per-vector masking */
811	bool fMsiNoMasking;
812
813	/** Number of MSI-X interrupt vectors, 0 if MSI-X not supported */
814	uint16_t cMsixVectors;
815	/** Offset of MSI-X capability */
816	uint8_t iMsixCapOffset;
817	/** Offset of next capability to MSI-X */
818	uint8_t iMsixNextOffset;
819	/** Value of PCI BAR (base addresss register) assigned by device for MSI-X page access */
820	uint8_t iMsixBar;
821	} PDMMSIREG;
822	typedef PDMMSIREG *PPDMMSIREG;
823
824	/**
825	* PCI Bus registration structure.
826	* All the callbacks, except the PCIBIOS hack, are working on PCI devices.
827	*/
828	typedef struct PDMPCIBUSREGR3
829	{
830	/** Structure version number. PDM_PCIBUSREGR3_VERSION defines the current version. */
831	uint32_t u32Version;
832
833	/**
834	* Registers the device with the default PCI bus.
835	*
836	* @returns VBox status code.
837	* @param pDevIns Device instance of the PCI Bus.
838	* @param pPciDev The PCI device structure.
839	* @param fFlags Reserved for future use, PDMPCIDEVREG_F_MBZ.
840	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, or a specific
841	* device number (0-31).
842	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
843	* function number (0-7).
844	* @param pszName Device name (static but not unique).
845	*
846	* @remarks Caller enters the PDM critical section.
847	*/
848	DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
849	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
850
851	/**
852	* Initialize MSI or MSI-X emulation support in a PCI device.
853	*
854	* This cannot handle all corner cases of the MSI/MSI-X spec, but for the
855	* vast majority of device emulation it covers everything necessary. It's
856	* fully automatic, taking care of all BAR and config space requirements,
857	* and interrupt delivery is done using PDMDevHlpPCISetIrq and friends.
858	* When MSI/MSI-X is enabled then the iIrq parameter is redefined to take
859	* the vector number (otherwise it has the usual INTA-D meaning for PCI).
860	*
861	* A device not using this can still offer MSI/MSI-X. In this case it's
862	* completely up to the device (in the MSI-X case) to create/register the
863	* necessary MMIO BAR, handle all config space/BAR updating and take care
864	* of delivering the interrupts appropriately.
865	*
866	* @returns VBox status code.
867	* @param pDevIns Device instance of the PCI Bus.
868	* @param pPciDev The PCI device structure.
869	* @param pMsiReg MSI emulation registration structure
870	* @remarks Caller enters the PDM critical section.
871	*/
872	DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
873
874	/**
875	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
876	*
877	* @returns VBox status code.
878	* @param pDevIns Device instance of the PCI Bus.
879	* @param pPciDev The PCI device structure.
880	* @param iRegion The region number.
881	* @param cbRegion Size of the region.
882	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or
883	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally with
884	* PCI_ADDRESS_SPACE_BAR64 or'ed in.
885	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
886	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
887	* @a fFlags, UINT64_MAX if no handle is passed
888	* (old style).
889	* @param pfnMapUnmap Callback for doing the mapping. Optional if a handle
890	* is given.
891	* @remarks Caller enters the PDM critical section.
892	*/
893	DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
894	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
895	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
896
897	/**
898	* Register PCI configuration space read/write intercept callbacks.
899	*
900	* @param pDevIns Device instance of the PCI Bus.
901	* @param pPciDev The PCI device structure.
902	* @param pfnRead Pointer to the user defined PCI config read function.
903	* @param pfnWrite Pointer to the user defined PCI config write function.
904	* to call default PCI config write function. Can be NULL.
905	* @remarks Caller enters the PDM critical section.
906	* @thread EMT
907	*/
908	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
909	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
910
911	/**
912	* Perform a PCI configuration space write, bypassing interception.
913	*
914	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
915	*
916	* @returns Strict VBox status code (mainly DBGFSTOP).
917	* @param pDevIns Device instance of the PCI Bus.
918	* @param pPciDev The PCI device which config space is being read.
919	* @param uAddress The config space address.
920	* @param cb The size of the read: 1, 2 or 4 bytes.
921	* @param u32Value The value to write.
922	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
923	* that the (root) bus will have done that already.
924	*/
925	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
926	uint32_t uAddress, unsigned cb, uint32_t u32Value));
927
928	/**
929	* Perform a PCI configuration space read, bypassing interception.
930	*
931	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
932	*
933	* @returns Strict VBox status code (mainly DBGFSTOP).
934	* @param pDevIns Device instance of the PCI Bus.
935	* @param pPciDev The PCI device which config space is being read.
936	* @param uAddress The config space address.
937	* @param cb The size of the read: 1, 2 or 4 bytes.
938	* @param pu32Value Where to return the value.
939	* @note The caller (PDM) does not enter the PDM critsect, but it is possible
940	* that the (root) bus will have done that already.
941	*/
942	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
943	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
944
945	/**
946	* Set the IRQ for a PCI device.
947	*
948	* @param pDevIns Device instance of the PCI Bus.
949	* @param pPciDev The PCI device structure.
950	* @param iIrq IRQ number to set.
951	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
952	* @param uTagSrc The IRQ tag and source (for tracing).
953	* @remarks Caller enters the PDM critical section.
954	*/
955	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
956
957	/** Marks the end of the structure with PDM_PCIBUSREGR3_VERSION. */
958	uint32_t u32EndVersion;
959	} PDMPCIBUSREGR3;
960	/** Pointer to a PCI bus registration structure. */
961	typedef PDMPCIBUSREGR3 *PPDMPCIBUSREGR3;
962	/** Current PDMPCIBUSREGR3 version number. */
963	#define PDM_PCIBUSREGR3_VERSION PDM_VERSION_MAKE(0xff86, 2, 0)
964
965	/**
966	* PCI Bus registration structure for ring-0.
967	*/
968	typedef struct PDMPCIBUSREGR0
969	{
970	/** Structure version number. PDM_PCIBUSREGR0_VERSION defines the current version. */
971	uint32_t u32Version;
972	/** The PCI bus number (from ring-3 registration). */
973	uint32_t iBus;
974	/**
975	* Set the IRQ for a PCI device.
976	*
977	* @param pDevIns Device instance of the PCI Bus.
978	* @param pPciDev The PCI device structure.
979	* @param iIrq IRQ number to set.
980	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
981	* @param uTagSrc The IRQ tag and source (for tracing).
982	* @remarks Caller enters the PDM critical section.
983	*/
984	DECLR0CALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
985	/** Marks the end of the structure with PDM_PCIBUSREGR0_VERSION. */
986	uint32_t u32EndVersion;
987	} PDMPCIBUSREGR0;
988	/** Pointer to a PCI bus ring-0 registration structure. */
989	typedef PDMPCIBUSREGR0 *PPDMPCIBUSREGR0;
990	/** Current PDMPCIBUSREGR0 version number. */
991	#define PDM_PCIBUSREGR0_VERSION PDM_VERSION_MAKE(0xff87, 1, 0)
992
993	/**
994	* PCI Bus registration structure for raw-mode.
995	*/
996	typedef struct PDMPCIBUSREGRC
997	{
998	/** Structure version number. PDM_PCIBUSREGRC_VERSION defines the current version. */
999	uint32_t u32Version;
1000	/** The PCI bus number (from ring-3 registration). */
1001	uint32_t iBus;
1002	/**
1003	* Set the IRQ for a PCI device.
1004	*
1005	* @param pDevIns Device instance of the PCI Bus.
1006	* @param pPciDev The PCI device structure.
1007	* @param iIrq IRQ number to set.
1008	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1009	* @param uTagSrc The IRQ tag and source (for tracing).
1010	* @remarks Caller enters the PDM critical section.
1011	*/
1012	DECLRCCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
1013	/** Marks the end of the structure with PDM_PCIBUSREGRC_VERSION. */
1014	uint32_t u32EndVersion;
1015	} PDMPCIBUSREGRC;
1016	/** Pointer to a PCI bus raw-mode registration structure. */
1017	typedef PDMPCIBUSREGRC *PPDMPCIBUSREGRC;
1018	/** Current PDMPCIBUSREGRC version number. */
1019	#define PDM_PCIBUSREGRC_VERSION PDM_VERSION_MAKE(0xff88, 1, 0)
1020
1021	/** PCI bus registration structure for the current context. */
1022	typedef CTX_SUFF(PDMPCIBUSREG) PDMPCIBUSREGCC;
1023	/** Pointer to a PCI bus registration structure for the current context. */
1024	typedef CTX_SUFF(PPDMPCIBUSREG) PPDMPCIBUSREGCC;
1025	/** PCI bus registration structure version for the current context. */
1026	#define PDM_PCIBUSREGCC_VERSION CTX_MID(PDM_PCIBUSREG,_VERSION)
1027
1028
1029	/**
1030	* PCI Bus RC helpers.
1031	*/
1032	typedef struct PDMPCIHLPRC
1033	{
1034	/** Structure version. PDM_PCIHLPRC_VERSION defines the current version. */
1035	uint32_t u32Version;
1036
1037	/**
1038	* Set an ISA IRQ.
1039	*
1040	* @param pDevIns PCI device instance.
1041	* @param iIrq IRQ number to set.
1042	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1043	* @param uTagSrc The IRQ tag and source (for tracing).
1044	* @thread EMT only.
1045	*/
1046	DECLRCCALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1047
1048	/**
1049	* Set an I/O-APIC IRQ.
1050	*
1051	* @param pDevIns PCI device instance.
1052	* @param uBusDevFn The bus:device:function of the device initiating the
1053	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1054	* interrupt.
1055	* @param iIrq IRQ number to set.
1056	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1057	* @param uTagSrc The IRQ tag and source (for tracing).
1058	* @thread EMT only.
1059	*/
1060	DECLRCCALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1061
1062	/**
1063	* Send an MSI.
1064	*
1065	* @param pDevIns PCI device instance.
1066	* @param uBusDevFn The bus:device:function of the device initiating the
1067	* MSI. Cannot be NIL_PCIBDF.
1068	* @param pMsi The MSI to send.
1069	* @param uTagSrc The IRQ tag and source (for tracing).
1070	* @thread EMT only.
1071	*/
1072	DECLRCCALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1073
1074
1075	/**
1076	* Acquires the PDM lock.
1077	*
1078	* @returns VINF_SUCCESS on success.
1079	* @returns rc if we failed to acquire the lock.
1080	* @param pDevIns The PCI device instance.
1081	* @param rc What to return if we fail to acquire the lock.
1082	*
1083	* @sa PDMCritSectEnter
1084	*/
1085	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1086
1087	/**
1088	* Releases the PDM lock.
1089	*
1090	* @param pDevIns The PCI device instance.
1091	*/
1092	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1093
1094	/**
1095	* Gets a bus by it's PDM ordinal (typically the parent bus).
1096	*
1097	* @returns Pointer to the device instance of the bus.
1098	* @param pDevIns The PCI bus device instance.
1099	* @param idxPdmBus The PDM ordinal value of the bus to get.
1100	*/
1101	DECLRCCALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1102
1103	/** Just a safety precaution. */
1104	uint32_t u32TheEnd;
1105	} PDMPCIHLPRC;
1106	/** Pointer to PCI helpers. */
1107	typedef RCPTRTYPE(PDMPCIHLPRC *) PPDMPCIHLPRC;
1108	/** Pointer to const PCI helpers. */
1109	typedef RCPTRTYPE(const PDMPCIHLPRC *) PCPDMPCIHLPRC;
1110
1111	/** Current PDMPCIHLPRC version number. */
1112	#define PDM_PCIHLPRC_VERSION PDM_VERSION_MAKE(0xfffd, 4, 0)
1113
1114
1115	/**
1116	* PCI Bus R0 helpers.
1117	*/
1118	typedef struct PDMPCIHLPR0
1119	{
1120	/** Structure version. PDM_PCIHLPR0_VERSION defines the current version. */
1121	uint32_t u32Version;
1122
1123	/**
1124	* Set an ISA IRQ.
1125	*
1126	* @param pDevIns PCI device instance.
1127	* @param iIrq IRQ number to set.
1128	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1129	* @param uTagSrc The IRQ tag and source (for tracing).
1130	* @thread EMT only.
1131	*/
1132	DECLR0CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1133
1134	/**
1135	* Set an I/O-APIC IRQ.
1136	*
1137	* @param pDevIns PCI device instance.
1138	* @param uBusDevFn The bus:device:function of the device initiating the
1139	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1140	* interrupt.
1141	* @param iIrq IRQ number to set.
1142	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1143	* @param uTagSrc The IRQ tag and source (for tracing).
1144	* @thread EMT only.
1145	*/
1146	DECLR0CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1147
1148	/**
1149	* Send an MSI.
1150	*
1151	* @param pDevIns PCI device instance.
1152	* @param uBusDevFn The bus:device:function of the device initiating the
1153	* MSI. Cannot be NIL_PCIBDF.
1154	* @param pMsi The MSI to send.
1155	* @param uTagSrc The IRQ tag and source (for tracing).
1156	* @thread EMT only.
1157	*/
1158	DECLR0CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1159
1160	/**
1161	* Acquires the PDM lock.
1162	*
1163	* @returns VINF_SUCCESS on success.
1164	* @returns rc if we failed to acquire the lock.
1165	* @param pDevIns The PCI device instance.
1166	* @param rc What to return if we fail to acquire the lock.
1167	*
1168	* @sa PDMCritSectEnter
1169	*/
1170	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1171
1172	/**
1173	* Releases the PDM lock.
1174	*
1175	* @param pDevIns The PCI device instance.
1176	*/
1177	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1178
1179	/**
1180	* Gets a bus by it's PDM ordinal (typically the parent bus).
1181	*
1182	* @returns Pointer to the device instance of the bus.
1183	* @param pDevIns The PCI bus device instance.
1184	* @param idxPdmBus The PDM ordinal value of the bus to get.
1185	*/
1186	DECLR0CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1187
1188	/** Just a safety precaution. */
1189	uint32_t u32TheEnd;
1190	} PDMPCIHLPR0;
1191	/** Pointer to PCI helpers. */
1192	typedef R0PTRTYPE(PDMPCIHLPR0 *) PPDMPCIHLPR0;
1193	/** Pointer to const PCI helpers. */
1194	typedef R0PTRTYPE(const PDMPCIHLPR0 *) PCPDMPCIHLPR0;
1195
1196	/** Current PDMPCIHLPR0 version number. */
1197	#define PDM_PCIHLPR0_VERSION PDM_VERSION_MAKE(0xfffc, 6, 0)
1198
1199	/**
1200	* PCI device helpers.
1201	*/
1202	typedef struct PDMPCIHLPR3
1203	{
1204	/** Structure version. PDM_PCIHLPR3_VERSION defines the current version. */
1205	uint32_t u32Version;
1206
1207	/**
1208	* Set an ISA IRQ.
1209	*
1210	* @param pDevIns The PCI device instance.
1211	* @param iIrq IRQ number to set.
1212	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1213	* @param uTagSrc The IRQ tag and source (for tracing).
1214	*/
1215	DECLR3CALLBACKMEMBER(void, pfnIsaSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1216
1217	/**
1218	* Set an I/O-APIC IRQ.
1219	*
1220	* @param pDevIns The PCI device instance.
1221	* @param uBusDevFn The bus:device:function of the device initiating the
1222	* IRQ. Pass NIL_PCIBDF when it's not a PCI device or
1223	* interrupt.
1224	* @param iIrq IRQ number to set.
1225	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1226	* @param uTagSrc The IRQ tag and source (for tracing).
1227	*/
1228	DECLR3CALLBACKMEMBER(void, pfnIoApicSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1229
1230	/**
1231	* Send an MSI.
1232	*
1233	* @param pDevIns PCI device instance.
1234	* @param uBusDevFn The bus:device:function of the device initiating the
1235	* MSI. Cannot be NIL_PCIBDF.
1236	* @param pMsi The MSI to send.
1237	* @param uTagSrc The IRQ tag and source (for tracing).
1238	*/
1239	DECLR3CALLBACKMEMBER(void, pfnIoApicSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1240
1241	/**
1242	* Acquires the PDM lock.
1243	*
1244	* @returns VINF_SUCCESS on success.
1245	* @returns Fatal error on failure.
1246	* @param pDevIns The PCI device instance.
1247	* @param rc Dummy for making the interface identical to the RC and R0 versions.
1248	*
1249	* @sa PDMCritSectEnter
1250	*/
1251	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1252
1253	/**
1254	* Releases the PDM lock.
1255	*
1256	* @param pDevIns The PCI device instance.
1257	*/
1258	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1259
1260	/**
1261	* Gets a bus by it's PDM ordinal (typically the parent bus).
1262	*
1263	* @returns Pointer to the device instance of the bus.
1264	* @param pDevIns The PCI bus device instance.
1265	* @param idxPdmBus The PDM ordinal value of the bus to get.
1266	*/
1267	DECLR3CALLBACKMEMBER(PPDMDEVINS, pfnGetBusByNo,(PPDMDEVINS pDevIns, uint32_t idxPdmBus));
1268
1269	/** Just a safety precaution. */
1270	uint32_t u32TheEnd;
1271	} PDMPCIHLPR3;
1272	/** Pointer to PCI helpers. */
1273	typedef R3PTRTYPE(PDMPCIHLPR3 *) PPDMPCIHLPR3;
1274	/** Pointer to const PCI helpers. */
1275	typedef R3PTRTYPE(const PDMPCIHLPR3 *) PCPDMPCIHLPR3;
1276
1277	/** Current PDMPCIHLPR3 version number. */
1278	#define PDM_PCIHLPR3_VERSION PDM_VERSION_MAKE(0xfffb, 5, 0)
1279
1280
1281	/** @name PDMIOMMU_MEM_F_XXX - IOMMU memory access transaction flags.
1282	* These flags are used for memory access transactions via the IOMMU interface.
1283	* @{ */
1284	/** Memory read. */
1285	#define PDMIOMMU_MEM_F_READ RT_BIT_32(0)
1286	/** Memory write. */
1287	#define PDMIOMMU_MEM_F_WRITE RT_BIT_32(1)
1288	/** Valid flag mask. */
1289	#define PDMIOMMU_MEM_F_VALID_MASK (PDMIOMMU_MEM_F_READ \| PDMIOMMU_MEM_F_WRITE)
1290	/** @} */
1291
1292	/**
1293	* IOMMU registration structure for ring-0.
1294	*/
1295	typedef struct PDMIOMMUREGR0
1296	{
1297	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1298	* version. */
1299	uint32_t u32Version;
1300	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1301	uint32_t idxIommu;
1302
1303	/**
1304	* Translates the physical address for a memory transaction through the IOMMU.
1305	*
1306	* @returns VBox status code.
1307	* @param pDevIns The IOMMU device instance.
1308	* @param idDevice The device identifier (bus, device, function).
1309	* @param uIova The I/O virtual address being accessed.
1310	* @param cbIova The size of the access.
1311	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1312	* @param pGCPhysSpa Where to store the translated system physical address.
1313	* @param pcbContiguous Where to store the number of contiguous bytes translated
1314	* and permission-checked.
1315	*
1316	* @thread Any.
1317	*/
1318	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1319	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1320
1321	/**
1322	* Translates in bulk physical page addresses for memory transactions through the
1323	* IOMMU.
1324	*
1325	* @returns VBox status code.
1326	* @param pDevIns The IOMMU device instance.
1327	* @param idDevice The device identifier (bus, device, function).
1328	* @param cIovas The number of I/O virtual addresses being accessed.
1329	* @param pauIovas The I/O virtual addresses being accessed.
1330	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1331	* @param paGCPhysSpa Where to store the translated system physical page
1332	* addresses.
1333	*
1334	* @thread Any.
1335	*/
1336	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1337	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1338
1339	/**
1340	* Performs an interrupt remap request through the IOMMU.
1341	*
1342	* @returns VBox status code.
1343	* @param pDevIns The IOMMU device instance.
1344	* @param idDevice The device identifier (bus, device, function).
1345	* @param pMsiIn The source MSI.
1346	* @param pMsiOut Where to store the remapped MSI.
1347	*
1348	* @thread Any.
1349	*/
1350	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1351
1352	/** Just a safety precaution. */
1353	uint32_t u32TheEnd;
1354	} PDMIOMMUREGR0;
1355	/** Pointer to a IOMMU registration structure. */
1356	typedef PDMIOMMUREGR0 *PPDMIOMMUREGR0;
1357
1358	/** Current PDMIOMMUREG version number. */
1359	#define PDM_IOMMUREGR0_VERSION PDM_VERSION_MAKE(0xff10, 3, 0)
1360
1361
1362	/**
1363	* IOMMU registration structure for raw-mode.
1364	*/
1365	typedef struct PDMIOMMUREGRC
1366	{
1367	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1368	* version. */
1369	uint32_t u32Version;
1370	/** Index into the PDM IOMMU array (PDM::aIommus) from ring-3. */
1371	uint32_t idxIommu;
1372
1373	/**
1374	* Translates the physical address for a memory transaction through the IOMMU.
1375	*
1376	* @returns VBox status code.
1377	* @param pDevIns The IOMMU device instance.
1378	* @param idDevice The device identifier (bus, device, function).
1379	* @param uIova The I/O virtual address being accessed.
1380	* @param cbIova The size of the access.
1381	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1382	* @param pGCPhysSpa Where to store the translated system physical address.
1383	* @param pcbContiguous Where to store the number of contiguous bytes translated
1384	* and permission-checked.
1385	*
1386	* @thread Any.
1387	*/
1388	DECLRCCALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1389	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1390
1391	/**
1392	* Translates in bulk physical page addresses for memory transactions through the
1393	* IOMMU.
1394	*
1395	* @returns VBox status code.
1396	* @param pDevIns The IOMMU device instance.
1397	* @param idDevice The device identifier (bus, device, function).
1398	* @param cIovas The number of I/O virtual addresses being accessed.
1399	* @param pauIovas The I/O virtual addresses being accessed.
1400	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1401	* @param paGCPhysSpa Where to store the translated system physical page
1402	* addresses.
1403	*
1404	* @thread Any.
1405	*/
1406	DECLRCCALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1407	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1408
1409	/**
1410	* Performs an interrupt remap request through the IOMMU.
1411	*
1412	* @returns VBox status code.
1413	* @param pDevIns The IOMMU device instance.
1414	* @param idDevice The device identifier (bus, device, function).
1415	* @param pMsiIn The source MSI.
1416	* @param pMsiOut Where to store the remapped MSI.
1417	*
1418	* @thread Any.
1419	*/
1420	DECLRCCALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1421
1422	/** Just a safety precaution. */
1423	uint32_t u32TheEnd;
1424	} PDMIOMMUREGRC;
1425	/** Pointer to a IOMMU registration structure. */
1426	typedef PDMIOMMUREGRC *PPDMIOMMUREGRC;
1427
1428	/** Current PDMIOMMUREG version number. */
1429	#define PDM_IOMMUREGRC_VERSION PDM_VERSION_MAKE(0xff11, 3, 0)
1430
1431
1432	/**
1433	* IOMMU registration structure for ring-3.
1434	*/
1435	typedef struct PDMIOMMUREGR3
1436	{
1437	/** Structure version number. PDM_IOMMUREG_VERSION defines the current
1438	* version. */
1439	uint32_t u32Version;
1440	/** Padding. */
1441	uint32_t uPadding0;
1442
1443	/**
1444	* Translates the physical address for a memory transaction through the IOMMU.
1445	*
1446	* @returns VBox status code.
1447	* @param pDevIns The IOMMU device instance.
1448	* @param idDevice The device identifier (bus, device, function).
1449	* @param uIova The I/O virtual address being accessed.
1450	* @param cbIova The size of the access.
1451	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1452	* @param pGCPhysSpa Where to store the translated system physical address.
1453	* @param pcbContiguous Where to store the number of contiguous bytes translated
1454	* and permission-checked.
1455	*
1456	* @thread Any.
1457	*/
1458	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1459	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous));
1460
1461	/**
1462	* Translates in bulk physical page addresses for memory transactions through the
1463	* IOMMU.
1464	*
1465	* @returns VBox status code.
1466	* @param pDevIns The IOMMU device instance.
1467	* @param idDevice The device identifier (bus, device, function).
1468	* @param cIovas The number of I/O virtual addresses being accessed.
1469	* @param pauIovas The I/O virtual addresses being accessed.
1470	* @param fFlags Access flags, see PDMIOMMU_MEM_F_XXX.
1471	* @param paGCPhysSpa Where to store the translated system physical page
1472	* addresses.
1473	*
1474	* @thread Any.
1475	*/
1476	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1477	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
1478
1479	/**
1480	* Performs an interrupt remap request through the IOMMU.
1481	*
1482	* @returns VBox status code.
1483	* @param pDevIns The IOMMU device instance.
1484	* @param idDevice The device identifier (bus, device, function).
1485	* @param pMsiIn The source MSI.
1486	* @param pMsiOut Where to store the remapped MSI.
1487	*
1488	* @thread Any.
1489	*/
1490	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1491
1492	/** Just a safety precaution. */
1493	uint32_t u32TheEnd;
1494	} PDMIOMMUREGR3;
1495	/** Pointer to a IOMMU registration structure. */
1496	typedef PDMIOMMUREGR3 *PPDMIOMMUREGR3;
1497
1498	/** Current PDMIOMMUREG version number. */
1499	#define PDM_IOMMUREGR3_VERSION PDM_VERSION_MAKE(0xff12, 3, 0)
1500
1501	/** IOMMU registration structure for the current context. */
1502	typedef CTX_SUFF(PDMIOMMUREG) PDMIOMMUREGCC;
1503	/** Pointer to an IOMMU registration structure for the current context. */
1504	typedef CTX_SUFF(PPDMIOMMUREG) PPDMIOMMUREGCC;
1505	/** IOMMU registration structure version for the current context. */
1506	#define PDM_IOMMUREGCC_VERSION CTX_MID(PDM_IOMMUREG,_VERSION)
1507
1508
1509	/**
1510	* IOMMU helpers for ring-0.
1511	*/
1512	typedef struct PDMIOMMUHLPR0
1513	{
1514	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1515	uint32_t u32Version;
1516
1517	/**
1518	* Acquires the PDM lock.
1519	*
1520	* @returns VINF_SUCCESS on success.
1521	* @returns rc if we failed to acquire the lock.
1522	* @param pDevIns The PCI device instance.
1523	* @param rc What to return if we fail to acquire the lock.
1524	*
1525	* @sa PDMCritSectEnter
1526	*/
1527	DECLR0CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1528
1529	/**
1530	* Releases the PDM lock.
1531	*
1532	* @param pDevIns The PCI device instance.
1533	*/
1534	DECLR0CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1535
1536	/**
1537	* Check whether the calling thread owns the PDM lock.
1538	*
1539	* @returns @c true if the PDM lock is owned, @c false otherwise.
1540	* @param pDevIns The PCI device instance.
1541	*/
1542	DECLR0CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1543
1544	/**
1545	* Send an MSI (when generated by the IOMMU device itself).
1546	*
1547	* @param pDevIns PCI device instance.
1548	* @param pMsi The MSI to send.
1549	* @param uTagSrc The IRQ tag and source (for tracing).
1550	*/
1551	DECLR0CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1552
1553	/** Just a safety precaution. */
1554	uint32_t u32TheEnd;
1555	} PDMIOMMUHLPR0;
1556	/** Pointer to IOMMU helpers for ring-0. */
1557	typedef PDMIOMMUHLPR0 *PPDMIOMMUHLPR0;
1558	/** Pointer to const IOMMU helpers for ring-0. */
1559	typedef const PDMIOMMUHLPR0 *PCPDMIOMMUHLPR0;
1560
1561	/** Current PDMIOMMUHLPR0 version number. */
1562	#define PDM_IOMMUHLPR0_VERSION PDM_VERSION_MAKE(0xff13, 5, 0)
1563
1564
1565	/**
1566	* IOMMU helpers for raw-mode.
1567	*/
1568	typedef struct PDMIOMMUHLPRC
1569	{
1570	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1571	uint32_t u32Version;
1572
1573	/**
1574	* Acquires the PDM lock.
1575	*
1576	* @returns VINF_SUCCESS on success.
1577	* @returns rc if we failed to acquire the lock.
1578	* @param pDevIns The PCI device instance.
1579	* @param rc What to return if we fail to acquire the lock.
1580	*
1581	* @sa PDMCritSectEnter
1582	*/
1583	DECLRCCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1584
1585	/**
1586	* Releases the PDM lock.
1587	*
1588	* @param pDevIns The PCI device instance.
1589	*/
1590	DECLRCCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1591
1592	/**
1593	* Check whether the threads owns the PDM lock.
1594	*
1595	* @returns @c true if the PDM lock is owned, @c false otherwise.
1596	* @param pDevIns The PCI device instance.
1597	*/
1598	DECLRCCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1599
1600	/**
1601	* Send an MSI (when generated by the IOMMU device itself).
1602	*
1603	* @param pDevIns PCI device instance.
1604	* @param pMsi The MSI to send.
1605	* @param uTagSrc The IRQ tag and source (for tracing).
1606	*/
1607	DECLRCCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1608
1609	/** Just a safety precaution. */
1610	uint32_t u32TheEnd;
1611	} PDMIOMMUHLPRC;
1612	/** Pointer to IOMMU helpers for raw-mode. */
1613	typedef PDMIOMMUHLPRC *PPDMIOMMUHLPRC;
1614	/** Pointer to const IOMMU helpers for raw-mode. */
1615	typedef const PDMIOMMUHLPRC *PCPDMIOMMUHLPRC;
1616
1617	/** Current PDMIOMMUHLPRC version number. */
1618	#define PDM_IOMMUHLPRC_VERSION PDM_VERSION_MAKE(0xff14, 5, 0)
1619
1620
1621	/**
1622	* IOMMU helpers for ring-3.
1623	*/
1624	typedef struct PDMIOMMUHLPR3
1625	{
1626	/** Structure version. PDM_IOMMUHLP_VERSION defines the current version. */
1627	uint32_t u32Version;
1628
1629	/**
1630	* Acquires the PDM lock.
1631	*
1632	* @returns VINF_SUCCESS on success.
1633	* @returns rc if we failed to acquire the lock.
1634	* @param pDevIns The PCI device instance.
1635	* @param rc What to return if we fail to acquire the lock.
1636	*
1637	* @sa PDMCritSectEnter
1638	*/
1639	DECLR3CALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1640
1641	/**
1642	* Releases the PDM lock.
1643	*
1644	* @param pDevIns The PCI device instance.
1645	*/
1646	DECLR3CALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1647
1648	/**
1649	* Check whether the threads owns the PDM lock.
1650	*
1651	* @returns @c true if the PDM lock is owned, @c false otherwise.
1652	* @param pDevIns The PCI device instance.
1653	*/
1654	DECLR3CALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1655
1656	/**
1657	* Send an MSI (when generated by the IOMMU device itself).
1658	*
1659	* @param pDevIns PCI device instance.
1660	* @param pMsi The MSI to send.
1661	* @param uTagSrc The IRQ tag and source (for tracing).
1662	*/
1663	DECLR3CALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc));
1664
1665	/** Just a safety precaution. */
1666	uint32_t u32TheEnd;
1667	} PDMIOMMUHLPR3;
1668	/** Pointer to IOMMU helpers for raw-mode. */
1669	typedef PDMIOMMUHLPR3 *PPDMIOMMUHLPR3;
1670	/** Pointer to const IOMMU helpers for raw-mode. */
1671	typedef const PDMIOMMUHLPR3 *PCPDMIOMMUHLPR3;
1672
1673	/** Current PDMIOMMUHLPR3 version number. */
1674	#define PDM_IOMMUHLPR3_VERSION PDM_VERSION_MAKE(0xff15, 5, 0)
1675
1676
1677	/**
1678	* Programmable Interrupt Controller registration structure (all contexts).
1679	*/
1680	typedef struct PDMPICREG
1681	{
1682	/** Structure version number. PDM_PICREG_VERSION defines the current version. */
1683	uint32_t u32Version;
1684
1685	/**
1686	* Set the an IRQ.
1687	*
1688	* @param pDevIns Device instance of the PIC.
1689	* @param iIrq IRQ number to set.
1690	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1691	* @param uTagSrc The IRQ tag and source (for tracing).
1692	* @remarks Caller enters the PDM critical section.
1693	*/
1694	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
1695
1696	/**
1697	* Get a pending interrupt.
1698	*
1699	* @returns Pending interrupt number.
1700	* @param pDevIns Device instance of the PIC.
1701	* @param puTagSrc Where to return the IRQ tag and source.
1702	* @remarks Caller enters the PDM critical section.
1703	*/
1704	DECLCALLBACKMEMBER(int, pfnGetInterrupt,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
1705
1706	/** Just a safety precaution. */
1707	uint32_t u32TheEnd;
1708	} PDMPICREG;
1709	/** Pointer to a PIC registration structure. */
1710	typedef PDMPICREG *PPDMPICREG;
1711
1712	/** Current PDMPICREG version number. */
1713	#define PDM_PICREG_VERSION PDM_VERSION_MAKE(0xfffa, 3, 0)
1714
1715	/**
1716	* PIC helpers, same in all contexts.
1717	*/
1718	typedef struct PDMPICHLP
1719	{
1720	/** Structure version. PDM_PICHLP_VERSION defines the current version. */
1721	uint32_t u32Version;
1722
1723	/**
1724	* Set the interrupt force action flag.
1725	*
1726	* @param pDevIns Device instance of the PIC.
1727	*/
1728	DECLCALLBACKMEMBER(void, pfnSetInterruptFF,(PPDMDEVINS pDevIns));
1729
1730	/**
1731	* Clear the interrupt force action flag.
1732	*
1733	* @param pDevIns Device instance of the PIC.
1734	*/
1735	DECLCALLBACKMEMBER(void, pfnClearInterruptFF,(PPDMDEVINS pDevIns));
1736
1737	/**
1738	* Acquires the PDM lock.
1739	*
1740	* @returns VINF_SUCCESS on success.
1741	* @returns rc if we failed to acquire the lock.
1742	* @param pDevIns The PIC device instance.
1743	* @param rc What to return if we fail to acquire the lock.
1744	*
1745	* @sa PDMCritSectEnter
1746	*/
1747	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1748
1749	/**
1750	* Releases the PDM lock.
1751	*
1752	* @param pDevIns The PIC device instance.
1753	*/
1754	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1755
1756	/** Just a safety precaution. */
1757	uint32_t u32TheEnd;
1758	} PDMPICHLP;
1759	/** Pointer to PIC helpers. */
1760	typedef PDMPICHLP *PPDMPICHLP;
1761	/** Pointer to const PIC helpers. */
1762	typedef const PDMPICHLP *PCPDMPICHLP;
1763
1764	/** Current PDMPICHLP version number. */
1765	#define PDM_PICHLP_VERSION PDM_VERSION_MAKE(0xfff9, 3, 0)
1766
1767
1768	/**
1769	* Firmware registration structure.
1770	*/
1771	typedef struct PDMFWREG
1772	{
1773	/** Struct version+magic number (PDM_FWREG_VERSION). */
1774	uint32_t u32Version;
1775
1776	/**
1777	* Checks whether this is a hard or soft reset.
1778	*
1779	* The current definition of soft reset is what the PC BIOS does when CMOS[0xF]
1780	* is 5, 9 or 0xA.
1781	*
1782	* @returns true if hard reset, false if soft.
1783	* @param pDevIns Device instance of the firmware.
1784	* @param fFlags PDMRESET_F_XXX passed to the PDMDevHlpVMReset API.
1785	*/
1786	DECLR3CALLBACKMEMBER(bool, pfnIsHardReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
1787
1788	/** Just a safety precaution. */
1789	uint32_t u32TheEnd;
1790	} PDMFWREG;
1791	/** Pointer to a FW registration structure. */
1792	typedef PDMFWREG *PPDMFWREG;
1793	/** Pointer to a const FW registration structure. */
1794	typedef PDMFWREG const *PCPDMFWREG;
1795
1796	/** Current PDMFWREG version number. */
1797	#define PDM_FWREG_VERSION PDM_VERSION_MAKE(0xffdd, 1, 0)
1798
1799	/**
1800	* Firmware R3 helpers.
1801	*/
1802	typedef struct PDMFWHLPR3
1803	{
1804	/** Structure version. PDM_FWHLP_VERSION defines the current version. */
1805	uint32_t u32Version;
1806
1807	/** Just a safety precaution. */
1808	uint32_t u32TheEnd;
1809	} PDMFWHLPR3;
1810
1811	/** Pointer to FW R3 helpers. */
1812	typedef R3PTRTYPE(PDMFWHLPR3 *) PPDMFWHLPR3;
1813	/** Pointer to const FW R3 helpers. */
1814	typedef R3PTRTYPE(const PDMFWHLPR3 *) PCPDMFWHLPR3;
1815
1816	/** Current PDMFWHLPR3 version number. */
1817	#define PDM_FWHLPR3_VERSION PDM_VERSION_MAKE(0xffdb, 1, 0)
1818
1819
1820	/**
1821	* I/O APIC registration structure (all contexts).
1822	*/
1823	typedef struct PDMIOAPICREG
1824	{
1825	/** Struct version+magic number (PDM_IOAPICREG_VERSION). */
1826	uint32_t u32Version;
1827
1828	/**
1829	* Set an IRQ.
1830	*
1831	* @param pDevIns Device instance of the I/O APIC.
1832	* @param uBusDevFn The bus:device:function of the device initiating the
1833	* IRQ. Can be NIL_PCIBDF.
1834	* @param iIrq IRQ number to set.
1835	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
1836	* @param uTagSrc The IRQ tag and source (for tracing).
1837	*
1838	* @remarks Caller enters the PDM critical section
1839	* Actually, as per 2018-07-21 this isn't true (bird).
1840	*/
1841	DECLCALLBACKMEMBER(void, pfnSetIrq,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
1842
1843	/**
1844	* Send a MSI.
1845	*
1846	* @param pDevIns Device instance of the I/O APIC.
1847	* @param uBusDevFn The bus:device:function of the device initiating the
1848	* MSI. Cannot be NIL_PCIBDF.
1849	* @param pMsi The MSI to send.
1850	* @param uTagSrc The IRQ tag and source (for tracing).
1851	*
1852	* @remarks Caller enters the PDM critical section
1853	* Actually, as per 2018-07-21 this isn't true (bird).
1854	*/
1855	DECLCALLBACKMEMBER(void, pfnSendMsi,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
1856
1857	/**
1858	* Set the EOI for an interrupt vector.
1859	*
1860	* @param pDevIns Device instance of the I/O APIC.
1861	* @param u8Vector The vector.
1862	*
1863	* @remarks Caller enters the PDM critical section
1864	* Actually, as per 2018-07-21 this isn't true (bird).
1865	*/
1866	DECLCALLBACKMEMBER(void, pfnSetEoi,(PPDMDEVINS pDevIns, uint8_t u8Vector));
1867
1868	/** Just a safety precaution. */
1869	uint32_t u32TheEnd;
1870	} PDMIOAPICREG;
1871	/** Pointer to an APIC registration structure. */
1872	typedef PDMIOAPICREG *PPDMIOAPICREG;
1873
1874	/** Current PDMAPICREG version number. */
1875	#define PDM_IOAPICREG_VERSION PDM_VERSION_MAKE(0xfff2, 8, 0)
1876
1877
1878	/**
1879	* IOAPIC helpers, same in all contexts.
1880	*/
1881	typedef struct PDMIOAPICHLP
1882	{
1883	/** Structure version. PDM_IOAPICHLP_VERSION defines the current version. */
1884	uint32_t u32Version;
1885
1886	/**
1887	* Private interface between the IOAPIC and APIC.
1888	*
1889	* @returns status code.
1890	* @param pDevIns Device instance of the IOAPIC.
1891	* @param u8Dest See APIC implementation.
1892	* @param u8DestMode See APIC implementation.
1893	* @param u8DeliveryMode See APIC implementation.
1894	* @param uVector See APIC implementation.
1895	* @param u8Polarity See APIC implementation.
1896	* @param u8TriggerMode See APIC implementation.
1897	* @param uTagSrc The IRQ tag and source (for tracing).
1898	*
1899	* @sa PDMApicBusDeliver()
1900	*/
1901	DECLCALLBACKMEMBER(int, pfnApicBusDeliver,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
1902	uint8_t uVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
1903
1904	/**
1905	* Acquires the PDM lock.
1906	*
1907	* @returns VINF_SUCCESS on success.
1908	* @returns rc if we failed to acquire the lock.
1909	* @param pDevIns The IOAPIC device instance.
1910	* @param rc What to return if we fail to acquire the lock.
1911	*
1912	* @sa PDMCritSectEnter
1913	*/
1914	DECLCALLBACKMEMBER(int, pfnLock,(PPDMDEVINS pDevIns, int rc));
1915
1916	/**
1917	* Releases the PDM lock.
1918	*
1919	* @param pDevIns The IOAPIC device instance.
1920	*/
1921	DECLCALLBACKMEMBER(void, pfnUnlock,(PPDMDEVINS pDevIns));
1922
1923	/**
1924	* Checks if the calling thread owns the PDM lock.
1925	*
1926	* @param pDevIns The IOAPIC device instance.
1927	*/
1928	DECLCALLBACKMEMBER(bool, pfnLockIsOwner,(PPDMDEVINS pDevIns));
1929
1930	/**
1931	* Private interface between the IOAPIC and IOMMU.
1932	*
1933	* @returns status code.
1934	* @param pDevIns Device instance of the IOAPIC.
1935	* @param idDevice The device identifier (bus, device, function).
1936	* @param pMsiIn The source MSI.
1937	* @param pMsiOut Where to store the remapped MSI (only updated when
1938	* VINF_SUCCESS is returned).
1939	*/
1940	DECLCALLBACKMEMBER(int, pfnIommuMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
1941
1942	/** Just a safety precaution. */
1943	uint32_t u32TheEnd;
1944	} PDMIOAPICHLP;
1945	/** Pointer to IOAPIC helpers. */
1946	typedef PDMIOAPICHLP * PPDMIOAPICHLP;
1947	/** Pointer to const IOAPIC helpers. */
1948	typedef const PDMIOAPICHLP * PCPDMIOAPICHLP;
1949
1950	/** Current PDMIOAPICHLP version number. */
1951	#define PDM_IOAPICHLP_VERSION PDM_VERSION_MAKE(0xfff0, 3, 1)
1952
1953
1954	/**
1955	* HPET registration structure.
1956	*/
1957	typedef struct PDMHPETREG
1958	{
1959	/** Struct version+magic number (PDM_HPETREG_VERSION). */
1960	uint32_t u32Version;
1961	} PDMHPETREG;
1962	/** Pointer to an HPET registration structure. */
1963	typedef PDMHPETREG *PPDMHPETREG;
1964
1965	/** Current PDMHPETREG version number. */
1966	#define PDM_HPETREG_VERSION PDM_VERSION_MAKE(0xffe2, 1, 0)
1967
1968	/**
1969	* HPET RC helpers.
1970	*
1971	* @remarks Keep this around in case HPET will need PDM interaction in again RC
1972	* at some later point.
1973	*/
1974	typedef struct PDMHPETHLPRC
1975	{
1976	/** Structure version. PDM_HPETHLPRC_VERSION defines the current version. */
1977	uint32_t u32Version;
1978
1979	/** Just a safety precaution. */
1980	uint32_t u32TheEnd;
1981	} PDMHPETHLPRC;
1982
1983	/** Pointer to HPET RC helpers. */
1984	typedef RCPTRTYPE(PDMHPETHLPRC *) PPDMHPETHLPRC;
1985	/** Pointer to const HPET RC helpers. */
1986	typedef RCPTRTYPE(const PDMHPETHLPRC *) PCPDMHPETHLPRC;
1987
1988	/** Current PDMHPETHLPRC version number. */
1989	#define PDM_HPETHLPRC_VERSION PDM_VERSION_MAKE(0xffee, 2, 0)
1990
1991
1992	/**
1993	* HPET R0 helpers.
1994	*
1995	* @remarks Keep this around in case HPET will need PDM interaction in again R0
1996	* at some later point.
1997	*/
1998	typedef struct PDMHPETHLPR0
1999	{
2000	/** Structure version. PDM_HPETHLPR0_VERSION defines the current version. */
2001	uint32_t u32Version;
2002
2003	/** Just a safety precaution. */
2004	uint32_t u32TheEnd;
2005	} PDMHPETHLPR0;
2006
2007	/** Pointer to HPET R0 helpers. */
2008	typedef R0PTRTYPE(PDMHPETHLPR0 *) PPDMHPETHLPR0;
2009	/** Pointer to const HPET R0 helpers. */
2010	typedef R0PTRTYPE(const PDMHPETHLPR0 *) PCPDMHPETHLPR0;
2011
2012	/** Current PDMHPETHLPR0 version number. */
2013	#define PDM_HPETHLPR0_VERSION PDM_VERSION_MAKE(0xffed, 2, 0)
2014
2015	/**
2016	* HPET R3 helpers.
2017	*/
2018	typedef struct PDMHPETHLPR3
2019	{
2020	/** Structure version. PDM_HPETHLP_VERSION defines the current version. */
2021	uint32_t u32Version;
2022
2023	/**
2024	* Set legacy mode on PIT and RTC.
2025	*
2026	* @returns VINF_SUCCESS on success.
2027	* @returns rc if we failed to set legacy mode.
2028	* @param pDevIns Device instance of the HPET.
2029	* @param fActivated Whether legacy mode is activated or deactivated.
2030	*/
2031	DECLR3CALLBACKMEMBER(int, pfnSetLegacyMode,(PPDMDEVINS pDevIns, bool fActivated));
2032
2033
2034	/**
2035	* Set IRQ, bypassing ISA bus override rules.
2036	*
2037	* @returns VINF_SUCCESS on success.
2038	* @returns rc if we failed to set legacy mode.
2039	* @param pDevIns Device instance of the HPET.
2040	* @param iIrq IRQ number to set.
2041	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
2042	*/
2043	DECLR3CALLBACKMEMBER(int, pfnSetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
2044
2045	/** Just a safety precaution. */
2046	uint32_t u32TheEnd;
2047	} PDMHPETHLPR3;
2048
2049	/** Pointer to HPET R3 helpers. */
2050	typedef R3PTRTYPE(PDMHPETHLPR3 *) PPDMHPETHLPR3;
2051	/** Pointer to const HPET R3 helpers. */
2052	typedef R3PTRTYPE(const PDMHPETHLPR3 *) PCPDMHPETHLPR3;
2053
2054	/** Current PDMHPETHLPR3 version number. */
2055	#define PDM_HPETHLPR3_VERSION PDM_VERSION_MAKE(0xffec, 3, 0)
2056
2057
2058	/**
2059	* Raw PCI device registration structure.
2060	*/
2061	typedef struct PDMPCIRAWREG
2062	{
2063	/** Struct version+magic number (PDM_PCIRAWREG_VERSION). */
2064	uint32_t u32Version;
2065	/** Just a safety precaution. */
2066	uint32_t u32TheEnd;
2067	} PDMPCIRAWREG;
2068	/** Pointer to a raw PCI registration structure. */
2069	typedef PDMPCIRAWREG *PPDMPCIRAWREG;
2070
2071	/** Current PDMPCIRAWREG version number. */
2072	#define PDM_PCIRAWREG_VERSION PDM_VERSION_MAKE(0xffe1, 1, 0)
2073
2074	/**
2075	* Raw PCI device raw-mode context helpers.
2076	*/
2077	typedef struct PDMPCIRAWHLPRC
2078	{
2079	/** Structure version and magic number (PDM_PCIRAWHLPRC_VERSION). */
2080	uint32_t u32Version;
2081	/** Just a safety precaution. */
2082	uint32_t u32TheEnd;
2083	} PDMPCIRAWHLPRC;
2084	/** Pointer to a raw PCI deviec raw-mode context helper structure. */
2085	typedef RCPTRTYPE(PDMPCIRAWHLPRC *) PPDMPCIRAWHLPRC;
2086	/** Pointer to a const raw PCI deviec raw-mode context helper structure. */
2087	typedef RCPTRTYPE(const PDMPCIRAWHLPRC *) PCPDMPCIRAWHLPRC;
2088
2089	/** Current PDMPCIRAWHLPRC version number. */
2090	#define PDM_PCIRAWHLPRC_VERSION PDM_VERSION_MAKE(0xffe0, 1, 0)
2091
2092	/**
2093	* Raw PCI device ring-0 context helpers.
2094	*/
2095	typedef struct PDMPCIRAWHLPR0
2096	{
2097	/** Structure version and magic number (PDM_PCIRAWHLPR0_VERSION). */
2098	uint32_t u32Version;
2099	/** Just a safety precaution. */
2100	uint32_t u32TheEnd;
2101	} PDMPCIRAWHLPR0;
2102	/** Pointer to a raw PCI deviec ring-0 context helper structure. */
2103	typedef R0PTRTYPE(PDMPCIRAWHLPR0 *) PPDMPCIRAWHLPR0;
2104	/** Pointer to a const raw PCI deviec ring-0 context helper structure. */
2105	typedef R0PTRTYPE(const PDMPCIRAWHLPR0 *) PCPDMPCIRAWHLPR0;
2106
2107	/** Current PDMPCIRAWHLPR0 version number. */
2108	#define PDM_PCIRAWHLPR0_VERSION PDM_VERSION_MAKE(0xffdf, 1, 0)
2109
2110
2111	/**
2112	* Raw PCI device ring-3 context helpers.
2113	*/
2114	typedef struct PDMPCIRAWHLPR3
2115	{
2116	/** Undefined structure version and magic number. */
2117	uint32_t u32Version;
2118
2119	/**
2120	* Gets the address of the RC raw PCI device helpers.
2121	*
2122	* This should be called at both construction and relocation time to obtain
2123	* the correct address of the RC helpers.
2124	*
2125	* @returns RC pointer to the raw PCI device helpers.
2126	* @param pDevIns Device instance of the raw PCI device.
2127	*/
2128	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPRC, pfnGetRCHelpers,(PPDMDEVINS pDevIns));
2129
2130	/**
2131	* Gets the address of the R0 raw PCI device helpers.
2132	*
2133	* This should be called at both construction and relocation time to obtain
2134	* the correct address of the R0 helpers.
2135	*
2136	* @returns R0 pointer to the raw PCI device helpers.
2137	* @param pDevIns Device instance of the raw PCI device.
2138	*/
2139	DECLR3CALLBACKMEMBER(PCPDMPCIRAWHLPR0, pfnGetR0Helpers,(PPDMDEVINS pDevIns));
2140
2141	/** Just a safety precaution. */
2142	uint32_t u32TheEnd;
2143	} PDMPCIRAWHLPR3;
2144	/** Pointer to raw PCI R3 helpers. */
2145	typedef R3PTRTYPE(PDMPCIRAWHLPR3 *) PPDMPCIRAWHLPR3;
2146	/** Pointer to const raw PCI R3 helpers. */
2147	typedef R3PTRTYPE(const PDMPCIRAWHLPR3 *) PCPDMPCIRAWHLPR3;
2148
2149	/** Current PDMPCIRAWHLPR3 version number. */
2150	#define PDM_PCIRAWHLPR3_VERSION PDM_VERSION_MAKE(0xffde, 1, 0)
2151
2152
2153	#ifdef IN_RING3
2154
2155	/**
2156	* DMA Transfer Handler.
2157	*
2158	* @returns Number of bytes transferred.
2159	* @param pDevIns The device instance that registered the handler.
2160	* @param pvUser User pointer.
2161	* @param uChannel Channel number.
2162	* @param off DMA position.
2163	* @param cb Block size.
2164	* @remarks The device lock is take before the callback (in fact, the locks of
2165	* DMA devices and the DMA controller itself are taken).
2166	*/
2167	typedef DECLCALLBACKTYPE(uint32_t, FNDMATRANSFERHANDLER,(PPDMDEVINS pDevIns, void *pvUser, unsigned uChannel,
2168	uint32_t off, uint32_t cb));
2169	/** Pointer to a FNDMATRANSFERHANDLER(). */
2170	typedef FNDMATRANSFERHANDLER *PFNDMATRANSFERHANDLER;
2171
2172	/**
2173	* DMA Controller registration structure.
2174	*/
2175	typedef struct PDMDMAREG
2176	{
2177	/** Structure version number. PDM_DMACREG_VERSION defines the current version. */
2178	uint32_t u32Version;
2179
2180	/**
2181	* Execute pending transfers.
2182	*
2183	* @returns A more work indiciator. I.e. 'true' if there is more to be done, and 'false' if all is done.
2184	* @param pDevIns Device instance of the DMAC.
2185	* @remarks No locks held, called on EMT(0) as a form of serialization.
2186	*/
2187	DECLR3CALLBACKMEMBER(bool, pfnRun,(PPDMDEVINS pDevIns));
2188
2189	/**
2190	* Register transfer function for DMA channel.
2191	*
2192	* @param pDevIns Device instance of the DMAC.
2193	* @param uChannel Channel number.
2194	* @param pDevInsHandler The device instance of the device making the
2195	* regstration (will be passed to the callback).
2196	* @param pfnTransferHandler Device specific transfer function.
2197	* @param pvUser User pointer to be passed to the callback.
2198	* @remarks No locks held, called on an EMT.
2199	*/
2200	DECLR3CALLBACKMEMBER(void, pfnRegister,(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
2201	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
2202
2203	/**
2204	* Read memory
2205	*
2206	* @returns Number of bytes read.
2207	* @param pDevIns Device instance of the DMAC.
2208	* @param uChannel Channel number.
2209	* @param pvBuffer Pointer to target buffer.
2210	* @param off DMA position.
2211	* @param cbBlock Block size.
2212	* @remarks No locks held, called on an EMT.
2213	*/
2214	DECLR3CALLBACKMEMBER(uint32_t, pfnReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock));
2215
2216	/**
2217	* Write memory
2218	*
2219	* @returns Number of bytes written.
2220	* @param pDevIns Device instance of the DMAC.
2221	* @param uChannel Channel number.
2222	* @param pvBuffer Memory to write.
2223	* @param off DMA position.
2224	* @param cbBlock Block size.
2225	* @remarks No locks held, called on an EMT.
2226	*/
2227	DECLR3CALLBACKMEMBER(uint32_t, pfnWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock));
2228
2229	/**
2230	* Set the DREQ line.
2231	*
2232	* @param pDevIns Device instance of the DMAC.
2233	* @param uChannel Channel number.
2234	* @param uLevel Level of the line.
2235	* @remarks No locks held, called on an EMT.
2236	*/
2237	DECLR3CALLBACKMEMBER(void, pfnSetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
2238
2239	/**
2240	* Get channel mode
2241	*
2242	* @returns Channel mode.
2243	* @param pDevIns Device instance of the DMAC.
2244	* @param uChannel Channel number.
2245	* @remarks No locks held, called on an EMT.
2246	*/
2247	DECLR3CALLBACKMEMBER(uint8_t, pfnGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
2248
2249	} PDMDMACREG;
2250	/** Pointer to a DMAC registration structure. */
2251	typedef PDMDMACREG *PPDMDMACREG;
2252
2253	/** Current PDMDMACREG version number. */
2254	#define PDM_DMACREG_VERSION PDM_VERSION_MAKE(0xffeb, 2, 0)
2255
2256
2257	/**
2258	* DMA Controller device helpers.
2259	*/
2260	typedef struct PDMDMACHLP
2261	{
2262	/** Structure version. PDM_DMACHLP_VERSION defines the current version. */
2263	uint32_t u32Version;
2264
2265	/* to-be-defined */
2266
2267	} PDMDMACHLP;
2268	/** Pointer to DMAC helpers. */
2269	typedef PDMDMACHLP *PPDMDMACHLP;
2270	/** Pointer to const DMAC helpers. */
2271	typedef const PDMDMACHLP *PCPDMDMACHLP;
2272
2273	/** Current PDMDMACHLP version number. */
2274	#define PDM_DMACHLP_VERSION PDM_VERSION_MAKE(0xffea, 1, 0)
2275
2276	#endif /* IN_RING3 */
2277
2278
2279
2280	/**
2281	* RTC registration structure.
2282	*/
2283	typedef struct PDMRTCREG
2284	{
2285	/** Structure version number. PDM_RTCREG_VERSION defines the current version. */
2286	uint32_t u32Version;
2287	uint32_t u32Alignment; /*< structure size alignment. /
2288
2289	/**
2290	* Write to a CMOS register and update the checksum if necessary.
2291	*
2292	* @returns VBox status code.
2293	* @param pDevIns Device instance of the RTC.
2294	* @param iReg The CMOS register index.
2295	* @param u8Value The CMOS register value.
2296	* @remarks Caller enters the device critical section.
2297	*/
2298	DECLR3CALLBACKMEMBER(int, pfnWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
2299
2300	/**
2301	* Read a CMOS register.
2302	*
2303	* @returns VBox status code.
2304	* @param pDevIns Device instance of the RTC.
2305	* @param iReg The CMOS register index.
2306	* @param pu8Value Where to store the CMOS register value.
2307	* @remarks Caller enters the device critical section.
2308	*/
2309	DECLR3CALLBACKMEMBER(int, pfnRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
2310
2311	} PDMRTCREG;
2312	/** Pointer to a RTC registration structure. */
2313	typedef PDMRTCREG *PPDMRTCREG;
2314	/** Pointer to a const RTC registration structure. */
2315	typedef const PDMRTCREG *PCPDMRTCREG;
2316
2317	/** Current PDMRTCREG version number. */
2318	#define PDM_RTCREG_VERSION PDM_VERSION_MAKE(0xffe9, 2, 0)
2319
2320
2321	/**
2322	* RTC device helpers.
2323	*/
2324	typedef struct PDMRTCHLP
2325	{
2326	/** Structure version. PDM_RTCHLP_VERSION defines the current version. */
2327	uint32_t u32Version;
2328
2329	/* to-be-defined */
2330
2331	} PDMRTCHLP;
2332	/** Pointer to RTC helpers. */
2333	typedef PDMRTCHLP *PPDMRTCHLP;
2334	/** Pointer to const RTC helpers. */
2335	typedef const PDMRTCHLP *PCPDMRTCHLP;
2336
2337	/** Current PDMRTCHLP version number. */
2338	#define PDM_RTCHLP_VERSION PDM_VERSION_MAKE(0xffe8, 1, 0)
2339
2340
2341
2342	/** @name Flags for PCI I/O region registration
2343	* @{ */
2344	/** No handle is passed. */
2345	#define PDMPCIDEV_IORGN_F_NO_HANDLE UINT32_C(0x00000000)
2346	/** An I/O port handle is passed. */
2347	#define PDMPCIDEV_IORGN_F_IOPORT_HANDLE UINT32_C(0x00000001)
2348	/** An MMIO range handle is passed. */
2349	#define PDMPCIDEV_IORGN_F_MMIO_HANDLE UINT32_C(0x00000002)
2350	/** An MMIO2 handle is passed. */
2351	#define PDMPCIDEV_IORGN_F_MMIO2_HANDLE UINT32_C(0x00000003)
2352	/** Handle type mask. */
2353	#define PDMPCIDEV_IORGN_F_HANDLE_MASK UINT32_C(0x00000003)
2354	/** New-style (mostly wrt callbacks). */
2355	#define PDMPCIDEV_IORGN_F_NEW_STYLE UINT32_C(0x00000004)
2356	/** Mask of valid flags. */
2357	#define PDMPCIDEV_IORGN_F_VALID_MASK UINT32_C(0x00000007)
2358	/** @} */
2359
2360
2361	/** @name Flags for the guest physical read/write helpers
2362	* @{ */
2363	/** Default flag with no indication whether the data is processed by the device or just passed through. */
2364	#define PDM_DEVHLP_PHYS_RW_F_DEFAULT UINT32_C(0x00000000)
2365	/** The data is user data which is just passed through between the guest and the source or destination and not processed
2366	* by the device in any way. */
2367	#define PDM_DEVHLP_PHYS_RW_F_DATA_USER RT_BIT_32(0)
2368	/** The data is metadata and being processed by the device in some way. */
2369	#define PDM_DEVHLP_PHYS_RW_F_DATA_META RT_BIT_32(1)
2370	/** @} */
2371
2372
2373	#ifdef IN_RING3
2374
2375	/** @name Special values for PDMDEVHLPR3::pfnPCIRegister parameters.
2376	* @{ */
2377	/** Same device number (and bus) as the previous PCI device registered with the PDM device.
2378	* This is handy when registering multiple PCI device functions and the device
2379	* number is left up to the PCI bus. In order to facilitate one PDM device
2380	* instance for each PCI function, this searches earlier PDM device
2381	* instances as well. */
2382	# define PDMPCIDEVREG_DEV_NO_SAME_AS_PREV UINT8_C(0xfd)
2383	/** Use the first unused device number (all functions must be unused). */
2384	# define PDMPCIDEVREG_DEV_NO_FIRST_UNUSED UINT8_C(0xfe)
2385	/** Use the first unused device function. */
2386	# define PDMPCIDEVREG_FUN_NO_FIRST_UNUSED UINT8_C(0xff)
2387
2388	/** The device and function numbers are not mandatory, just suggestions. */
2389	# define PDMPCIDEVREG_F_NOT_MANDATORY_NO RT_BIT_32(0)
2390	/** Registering a PCI bridge device. */
2391	# define PDMPCIDEVREG_F_PCI_BRIDGE RT_BIT_32(1)
2392	/** Valid flag mask. */
2393	# define PDMPCIDEVREG_F_VALID_MASK UINT32_C(0x00000003)
2394	/** @} */
2395
2396	/** Current PDMDEVHLPR3 version number. */
2397	#define PDM_DEVHLPR3_VERSION PDM_VERSION_MAKE_PP(0xffe7, 66, 0)
2398
2399	/**
2400	* PDM Device API.
2401	*/
2402	typedef struct PDMDEVHLPR3
2403	{
2404	/** Structure version. PDM_DEVHLPR3_VERSION defines the current version. */
2405	uint32_t u32Version;
2406
2407	/** @name I/O ports
2408	* @{ */
2409	/**
2410	* Creates a range of I/O ports for a device.
2411	*
2412	* The I/O port range must be mapped in a separately call. Any ring-0 and
2413	* raw-mode context callback handlers needs to be set up in the respective
2414	* contexts.
2415	*
2416	* @returns VBox status.
2417	* @param pDevIns The device instance to register the ports with.
2418	* @param cPorts Number of ports to register.
2419	* @param fFlags IOM_IOPORT_F_XXX.
2420	* @param pPciDev The PCI device the range is associated with, if
2421	* applicable.
2422	* @param iPciRegion The PCI device region in the high 16-bit word and
2423	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2424	* @param pfnOut Pointer to function which is gonna handle OUT
2425	* operations. Optional.
2426	* @param pfnIn Pointer to function which is gonna handle IN operations.
2427	* Optional.
2428	* @param pfnOutStr Pointer to function which is gonna handle string OUT
2429	* operations. Optional.
2430	* @param pfnInStr Pointer to function which is gonna handle string IN
2431	* operations. Optional.
2432	* @param pvUser User argument to pass to the callbacks.
2433	* @param pszDesc Pointer to description string. This must not be freed.
2434	* @param paExtDescs Extended per-port descriptions, optional. Partial range
2435	* coverage is allowed. This must not be freed.
2436	* @param phIoPorts Where to return the I/O port range handle.
2437	*
2438	* @remarks Caller enters the device critical section prior to invoking the
2439	* registered callback methods.
2440	*
2441	* @sa PDMDevHlpIoPortSetUpContext, PDMDevHlpIoPortMap,
2442	* PDMDevHlpIoPortUnmap.
2443	*/
2444	DECLR3CALLBACKMEMBER(int, pfnIoPortCreateEx,(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
2445	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
2446	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
2447	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts));
2448
2449	/**
2450	* Maps an I/O port range.
2451	*
2452	* @returns VBox status.
2453	* @param pDevIns The device instance to register the ports with.
2454	* @param hIoPorts The I/O port range handle.
2455	* @param Port Where to map the range.
2456	* @sa PDMDevHlpIoPortUnmap, PDMDevHlpIoPortSetUpContext,
2457	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2458	*/
2459	DECLR3CALLBACKMEMBER(int, pfnIoPortMap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port));
2460
2461	/**
2462	* Unmaps an I/O port range.
2463	*
2464	* @returns VBox status.
2465	* @param pDevIns The device instance to register the ports with.
2466	* @param hIoPorts The I/O port range handle.
2467	* @sa PDMDevHlpIoPortMap, PDMDevHlpIoPortSetUpContext,
2468	* PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx.
2469	*/
2470	DECLR3CALLBACKMEMBER(int, pfnIoPortUnmap,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2471
2472	/**
2473	* Gets the mapping address of the I/O port range @a hIoPorts.
2474	*
2475	* @returns Mapping address (0..65535) or UINT32_MAX if not mapped (or invalid
2476	* parameters).
2477	* @param pDevIns The device instance to register the ports with.
2478	* @param hIoPorts The I/O port range handle.
2479	*/
2480	DECLR3CALLBACKMEMBER(uint32_t, pfnIoPortGetMappingAddress,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts));
2481
2482	/**
2483	* Reads from an I/O port register.
2484	*
2485	* @returns Strict VBox status code. Informational status codes other than the one documented
2486	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2487	* @retval VINF_SUCCESS Success.
2488	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2489	* status code must be passed on to EM.
2490	*
2491	* @param pDevIns The device instance to register the ports with.
2492	* @param Port The port to read from.
2493	* @param pu32Value Where to store the read value.
2494	* @param cbValue The size of the register to read in bytes. 1, 2 or 4 bytes.
2495	*
2496	* @thread EMT
2497	*
2498	* @note This is required for the ARM platform in order to emulate PIO accesses through a dedicated MMIO region.
2499	*/
2500	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortRead,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue));
2501
2502	/**
2503	* Writes to an I/O port register.
2504	*
2505	* @returns Strict VBox status code. Informational status codes other than the one documented
2506	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2507	* @retval VINF_SUCCESS Success.
2508	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2509	* status code must be passed on to EM.
2510	*
2511	* @param pDevIns The device instance to register the ports with.
2512	* @param Port The port to write to.
2513	* @param u32Value The value to write.
2514	* @param cbValue The size of the register to write in bytes. 1, 2 or 4 bytes.
2515	*
2516	* @thread EMT
2517	*
2518	* @note This is required for the ARM platform in order to emulate PIO accesses through a dedicated MMIO region.
2519	*/
2520	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnIoPortWrite,(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue));
2521	/** @} */
2522
2523	/** @name MMIO
2524	* @{ */
2525	/**
2526	* Creates a memory mapped I/O (MMIO) region for a device.
2527	*
2528	* The MMIO region must be mapped in a separately call. Any ring-0 and
2529	* raw-mode context callback handlers needs to be set up in the respective
2530	* contexts.
2531	*
2532	* @returns VBox status.
2533	* @param pDevIns The device instance to register the ports with.
2534	* @param cbRegion The size of the region in bytes.
2535	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
2536	* @param pPciDev The PCI device the range is associated with, if
2537	* applicable.
2538	* @param iPciRegion The PCI device region in the high 16-bit word and
2539	* sub-region in the low 16-bit word. UINT32_MAX if NA.
2540	* @param pfnWrite Pointer to function which is gonna handle Write
2541	* operations.
2542	* @param pfnRead Pointer to function which is gonna handle Read
2543	* operations.
2544	* @param pfnFill Pointer to function which is gonna handle Fill/memset
2545	* operations. (optional)
2546	* @param pvUser User argument to pass to the callbacks.
2547	* @param pszDesc Pointer to description string. This must not be freed.
2548	* @param phRegion Where to return the MMIO region handle.
2549	*
2550	* @remarks Caller enters the device critical section prior to invoking the
2551	* registered callback methods.
2552	*
2553	* @sa PDMDevHlpMmioSetUpContext, PDMDevHlpMmioMap, PDMDevHlpMmioUnmap.
2554	*/
2555	DECLR3CALLBACKMEMBER(int, pfnMmioCreateEx,(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
2556	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
2557	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
2558	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion));
2559
2560	/**
2561	* Maps a memory mapped I/O (MMIO) region (into the guest physical address space).
2562	*
2563	* @returns VBox status.
2564	* @param pDevIns The device instance the region is associated with.
2565	* @param hRegion The MMIO region handle.
2566	* @param GCPhys Where to map the region.
2567	* @note An MMIO range may overlap with base memory if a lot of RAM is
2568	* configured for the VM, in which case we'll drop the base memory
2569	* pages. Presently we will make no attempt to preserve anything that
2570	* happens to be present in the base memory that is replaced, this is
2571	* technically incorrect but it's just not worth the effort to do
2572	* right, at least not at this point.
2573	* @sa PDMDevHlpMmioUnmap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2574	* PDMDevHlpMmioSetUpContext
2575	*/
2576	DECLR3CALLBACKMEMBER(int, pfnMmioMap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys));
2577
2578	/**
2579	* Unmaps a memory mapped I/O (MMIO) region.
2580	*
2581	* @returns VBox status.
2582	* @param pDevIns The device instance the region is associated with.
2583	* @param hRegion The MMIO region handle.
2584	* @sa PDMDevHlpMmioMap, PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx,
2585	* PDMDevHlpMmioSetUpContext
2586	*/
2587	DECLR3CALLBACKMEMBER(int, pfnMmioUnmap,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2588
2589	/**
2590	* Reduces the length of a MMIO range.
2591	*
2592	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2593	* only work during saved state restore. It will not call the PCI bus code, as
2594	* that is expected to restore the saved resource configuration.
2595	*
2596	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2597	* called it will only map @a cbRegion bytes and not the value set during
2598	* registration.
2599	*
2600	* @return VBox status code.
2601	* @param pDevIns The device owning the range.
2602	* @param hRegion The MMIO region handle.
2603	* @param cbRegion The new size, must be smaller.
2604	*/
2605	DECLR3CALLBACKMEMBER(int, pfnMmioReduce,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion));
2606
2607	/**
2608	* Gets the mapping address of the MMIO region @a hRegion.
2609	*
2610	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2611	* @param pDevIns The device instance to register the ports with.
2612	* @param hRegion The MMIO region handle.
2613	*/
2614	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmioGetMappingAddress,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2615	/** @} */
2616
2617	/** @name MMIO2
2618	* @{ */
2619	/**
2620	* Creates a MMIO2 region.
2621	*
2622	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's RAM
2623	* associated with a device. It is also non-shared memory with a permanent
2624	* ring-3 mapping and page backing (presently).
2625	*
2626	* @returns VBox status.
2627	* @param pDevIns The device instance.
2628	* @param pPciDev The PCI device the region is associated with, or
2629	* NULL if no PCI device association.
2630	* @param iPciRegion The region number. Use the PCI region number as
2631	* this must be known to the PCI bus device too. If
2632	* it's not associated with the PCI device, then
2633	* any number up to UINT8_MAX is fine.
2634	* @param cbRegion The size (in bytes) of the region.
2635	* @param fFlags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
2636	* @param pszDesc Pointer to description string. This must not be
2637	* freed.
2638	* @param ppvMapping Where to store the address of the ring-3 mapping
2639	* of the memory.
2640	* @param phRegion Where to return the MMIO2 region handle.
2641	*
2642	* @thread EMT(0)
2643	*/
2644	DECLR3CALLBACKMEMBER(int, pfnMmio2Create,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
2645	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion));
2646
2647	/**
2648	* Destroys a MMIO2 region, unmapping it and freeing the memory.
2649	*
2650	* Any physical access handlers registered for the region must be deregistered
2651	* before calling this function.
2652	*
2653	* @returns VBox status code.
2654	* @param pDevIns The device instance.
2655	* @param hRegion The MMIO2 region handle.
2656	* @thread EMT.
2657	*/
2658	DECLR3CALLBACKMEMBER(int, pfnMmio2Destroy,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2659
2660	/**
2661	* Maps a MMIO2 region (into the guest physical address space).
2662	*
2663	* @returns VBox status.
2664	* @param pDevIns The device instance the region is associated with.
2665	* @param hRegion The MMIO2 region handle.
2666	* @param GCPhys Where to map the region.
2667	* @note A MMIO2 region overlap with base memory if a lot of RAM is
2668	* configured for the VM, in which case we'll drop the base memory
2669	* pages. Presently we will make no attempt to preserve anything that
2670	* happens to be present in the base memory that is replaced, this is
2671	* technically incorrect but it's just not worth the effort to do
2672	* right, at least not at this point.
2673	* @sa PDMDevHlpMmio2Unmap, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2674	*/
2675	DECLR3CALLBACKMEMBER(int, pfnMmio2Map,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys));
2676
2677	/**
2678	* Unmaps a MMIO2 region.
2679	*
2680	* @returns VBox status.
2681	* @param pDevIns The device instance the region is associated with.
2682	* @param hRegion The MMIO2 region handle.
2683	* @sa PDMDevHlpMmio2Map, PDMDevHlpMmio2Create, PDMDevHlpMmio2SetUpContext
2684	*/
2685	DECLR3CALLBACKMEMBER(int, pfnMmio2Unmap,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2686
2687	/**
2688	* Reduces the length of a MMIO range.
2689	*
2690	* This is for implementations of PDMPCIDEV::pfnRegionLoadChangeHookR3 and will
2691	* only work during saved state restore. It will not call the PCI bus code, as
2692	* that is expected to restore the saved resource configuration.
2693	*
2694	* It just adjusts the mapping length of the region so that when pfnMmioMap is
2695	* called it will only map @a cbRegion bytes and not the value set during
2696	* registration.
2697	*
2698	* @return VBox status code.
2699	* @param pDevIns The device owning the range.
2700	* @param hRegion The MMIO2 region handle.
2701	* @param cbRegion The new size, must be smaller.
2702	*/
2703	DECLR3CALLBACKMEMBER(int, pfnMmio2Reduce,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion));
2704
2705	/**
2706	* Gets the mapping address of the MMIO region @a hRegion.
2707	*
2708	* @returns Mapping address, NIL_RTGCPHYS if not mapped (or invalid parameters).
2709	* @param pDevIns The device instance to register the ports with.
2710	* @param hRegion The MMIO2 region handle.
2711	*/
2712	DECLR3CALLBACKMEMBER(RTGCPHYS, pfnMmio2GetMappingAddress,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion));
2713
2714	/**
2715	* Queries and resets the dirty bitmap for an MMIO2 region.
2716	*
2717	* The MMIO2 region must have been created with the
2718	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2719	*
2720	* @returns VBox status code.
2721	* @param pDevIns The device instance.
2722	* @param hRegion The MMIO2 region handle.
2723	* @param pvBitmap Where to return the bitmap. Must be 8-byte aligned.
2724	* Can be NULL if only resetting the tracking is desired.
2725	* @param cbBitmap The bitmap size. One bit per page in the region,
2726	* rounded up to 8-bytes. If pvBitmap is NULL this must
2727	* also be zero.
2728	*/
2729	DECLR3CALLBACKMEMBER(int, pfnMmio2QueryAndResetDirtyBitmap, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
2730	void *pvBitmap, size_t cbBitmap));
2731
2732	/**
2733	* Controls the dirty page tracking for an MMIO2 region.
2734	*
2735	* The MMIO2 region must have been created with the
2736	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
2737	*
2738	* @returns VBox status code.
2739	* @param pDevIns The device instance.
2740	* @param hRegion The MMIO2 region handle.
2741	* @param fEnabled When set to @c true the dirty page tracking will be
2742	* enabled if currently disabled (bitmap is reset). When
2743	* set to @c false the dirty page tracking will be
2744	* disabled.
2745	*/
2746	DECLR3CALLBACKMEMBER(int, pfnMmio2ControlDirtyPageTracking, (PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled));
2747
2748	/**
2749	* Changes the number of an MMIO2 or pre-registered MMIO region.
2750	*
2751	* This should only be used to deal with saved state problems, so there is no
2752	* convenience inline wrapper for this method.
2753	*
2754	* @returns VBox status code.
2755	* @param pDevIns The device instance.
2756	* @param hRegion The MMIO2 region handle.
2757	* @param iNewRegion The new region index.
2758	*
2759	* @sa @bugref{9359}
2760	*/
2761	DECLR3CALLBACKMEMBER(int, pfnMmio2ChangeRegionNo,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, uint32_t iNewRegion));
2762
2763	/**
2764	* Mapping an MMIO2 page in place of an MMIO page for direct access.
2765	*
2766	* This is a special optimization used by the VGA device. Call
2767	* PDMDevHlpMmioResetRegion() to undo the mapping.
2768	*
2769	* @returns VBox status code. This API may return VINF_SUCCESS even if no
2770	* remapping is made.
2771	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
2772	*
2773	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
2774	* associated with.
2775	* @param hRegion The handle to the MMIO region.
2776	* @param offRegion The offset into @a hRegion of the page to be
2777	* remapped.
2778	* @param hMmio2 The MMIO2 handle.
2779	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
2780	* mapping.
2781	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
2782	* for the time being.
2783	*/
2784	DECLR3CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
2785	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
2786
2787	/**
2788	* Reset a previously modified MMIO region; restore the access flags.
2789	*
2790	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
2791	* intended for some ancient VGA hack. However, it would be great to extend it
2792	* beyond VT-x and/or nested-paging.
2793	*
2794	* @returns VBox status code.
2795	*
2796	* @param pDevIns The device instance @a hRegion is associated with.
2797	* @param hRegion The handle to the MMIO region.
2798	*/
2799	DECLR3CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
2800	/** @} */
2801
2802	/**
2803	* Register a ROM (BIOS) region.
2804	*
2805	* It goes without saying that this is read-only memory. The memory region must be
2806	* in unassigned memory. I.e. from the top of the address space or on the PC in
2807	* the 0xa0000-0xfffff range.
2808	*
2809	* @returns VBox status.
2810	* @param pDevIns The device instance owning the ROM region.
2811	* @param GCPhysStart First physical address in the range.
2812	* Must be page aligned!
2813	* @param cbRange The size of the range (in bytes).
2814	* Must be page aligned!
2815	* @param pvBinary Pointer to the binary data backing the ROM image.
2816	* @param cbBinary The size of the binary pointer. This must
2817	* be equal or smaller than @a cbRange.
2818	* @param fFlags PGMPHYS_ROM_FLAGS_XXX (see pgm.h).
2819	* @param pszDesc Pointer to description string. This must not be freed.
2820	*
2821	* @remark There is no way to remove the rom, automatically on device cleanup or
2822	* manually from the device yet. At present I doubt we need such features...
2823	*/
2824	DECLR3CALLBACKMEMBER(int, pfnROMRegister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
2825	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc));
2826
2827	/**
2828	* Changes the protection of shadowed ROM mapping.
2829	*
2830	* This is intented for use by the system BIOS, chipset or device in question to
2831	* change the protection of shadowed ROM code after init and on reset.
2832	*
2833	* @param pDevIns The device instance.
2834	* @param GCPhysStart Where the mapping starts.
2835	* @param cbRange The size of the mapping.
2836	* @param enmProt The new protection type.
2837	*/
2838	DECLR3CALLBACKMEMBER(int, pfnROMProtectShadow,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt));
2839
2840	/**
2841	* Register a save state data unit.
2842	*
2843	* @returns VBox status.
2844	* @param pDevIns The device instance.
2845	* @param uVersion Data layout version number.
2846	* @param cbGuess The approximate amount of data in the unit.
2847	* Only for progress indicators.
2848	* @param pszBefore Name of data unit which we should be put in
2849	* front of. Optional (NULL).
2850	*
2851	* @param pfnLivePrep Prepare live save callback, optional.
2852	* @param pfnLiveExec Execute live save callback, optional.
2853	* @param pfnLiveVote Vote live save callback, optional.
2854	*
2855	* @param pfnSavePrep Prepare save callback, optional.
2856	* @param pfnSaveExec Execute save callback, optional.
2857	* @param pfnSaveDone Done save callback, optional.
2858	*
2859	* @param pfnLoadPrep Prepare load callback, optional.
2860	* @param pfnLoadExec Execute load callback, optional.
2861	* @param pfnLoadDone Done load callback, optional.
2862	* @remarks Caller enters the device critical section prior to invoking the
2863	* registered callback methods.
2864	*/
2865	DECLR3CALLBACKMEMBER(int, pfnSSMRegister,(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
2866	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
2867	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
2868	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2869
2870	/**
2871	* Register a save state data unit for backward compatibility.
2872	*
2873	* This is for migrating from an old device name to a new one or for merging
2874	* devices. It will only help loading old saved states.
2875	*
2876	* @returns VBox status.
2877	* @param pDevIns The device instance.
2878	* @param pszOldName The old unit name.
2879	* @param pfnLoadPrep Prepare load callback, optional.
2880	* @param pfnLoadExec Execute load callback, optional.
2881	* @param pfnLoadDone Done load callback, optional.
2882	* @remarks Caller enters the device critical section prior to invoking the
2883	* registered callback methods.
2884	*/
2885	DECLR3CALLBACKMEMBER(int, pfnSSMRegisterLegacy,(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
2886	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone));
2887
2888	/** @name Exported SSM Functions
2889	* @{ */
2890	DECLR3CALLBACKMEMBER(int, pfnSSMPutStruct,(PSSMHANDLE pSSM, const void *pvStruct, PCSSMFIELD paFields));
2891	DECLR3CALLBACKMEMBER(int, pfnSSMPutStructEx,(PSSMHANDLE pSSM, const void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2892	DECLR3CALLBACKMEMBER(int, pfnSSMPutBool,(PSSMHANDLE pSSM, bool fBool));
2893	DECLR3CALLBACKMEMBER(int, pfnSSMPutU8,(PSSMHANDLE pSSM, uint8_t u8));
2894	DECLR3CALLBACKMEMBER(int, pfnSSMPutS8,(PSSMHANDLE pSSM, int8_t i8));
2895	DECLR3CALLBACKMEMBER(int, pfnSSMPutU16,(PSSMHANDLE pSSM, uint16_t u16));
2896	DECLR3CALLBACKMEMBER(int, pfnSSMPutS16,(PSSMHANDLE pSSM, int16_t i16));
2897	DECLR3CALLBACKMEMBER(int, pfnSSMPutU32,(PSSMHANDLE pSSM, uint32_t u32));
2898	DECLR3CALLBACKMEMBER(int, pfnSSMPutS32,(PSSMHANDLE pSSM, int32_t i32));
2899	DECLR3CALLBACKMEMBER(int, pfnSSMPutU64,(PSSMHANDLE pSSM, uint64_t u64));
2900	DECLR3CALLBACKMEMBER(int, pfnSSMPutS64,(PSSMHANDLE pSSM, int64_t i64));
2901	DECLR3CALLBACKMEMBER(int, pfnSSMPutU128,(PSSMHANDLE pSSM, uint128_t u128));
2902	DECLR3CALLBACKMEMBER(int, pfnSSMPutS128,(PSSMHANDLE pSSM, int128_t i128));
2903	DECLR3CALLBACKMEMBER(int, pfnSSMPutUInt,(PSSMHANDLE pSSM, RTUINT u));
2904	DECLR3CALLBACKMEMBER(int, pfnSSMPutSInt,(PSSMHANDLE pSSM, RTINT i));
2905	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUInt,(PSSMHANDLE pSSM, RTGCUINT u));
2906	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntReg,(PSSMHANDLE pSSM, RTGCUINTREG u));
2907	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys32,(PSSMHANDLE pSSM, RTGCPHYS32 GCPhys));
2908	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys64,(PSSMHANDLE pSSM, RTGCPHYS64 GCPhys));
2909	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPhys,(PSSMHANDLE pSSM, RTGCPHYS GCPhys));
2910	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCPtr,(PSSMHANDLE pSSM, RTGCPTR GCPtr));
2911	DECLR3CALLBACKMEMBER(int, pfnSSMPutGCUIntPtr,(PSSMHANDLE pSSM, RTGCUINTPTR GCPtr));
2912	DECLR3CALLBACKMEMBER(int, pfnSSMPutRCPtr,(PSSMHANDLE pSSM, RTRCPTR RCPtr));
2913	DECLR3CALLBACKMEMBER(int, pfnSSMPutIOPort,(PSSMHANDLE pSSM, RTIOPORT IOPort));
2914	DECLR3CALLBACKMEMBER(int, pfnSSMPutSel,(PSSMHANDLE pSSM, RTSEL Sel));
2915	DECLR3CALLBACKMEMBER(int, pfnSSMPutMem,(PSSMHANDLE pSSM, const void *pv, size_t cb));
2916	DECLR3CALLBACKMEMBER(int, pfnSSMPutStrZ,(PSSMHANDLE pSSM, const char *psz));
2917	DECLR3CALLBACKMEMBER(int, pfnSSMGetStruct,(PSSMHANDLE pSSM, void *pvStruct, PCSSMFIELD paFields));
2918	DECLR3CALLBACKMEMBER(int, pfnSSMGetStructEx,(PSSMHANDLE pSSM, void pvStruct, size_t cbStruct, uint32_t fFlags, PCSSMFIELD paFields, void pvUser));
2919	DECLR3CALLBACKMEMBER(int, pfnSSMGetBool,(PSSMHANDLE pSSM, bool *pfBool));
2920	DECLR3CALLBACKMEMBER(int, pfnSSMGetBoolV,(PSSMHANDLE pSSM, bool volatile *pfBool));
2921	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8,(PSSMHANDLE pSSM, uint8_t *pu8));
2922	DECLR3CALLBACKMEMBER(int, pfnSSMGetU8V,(PSSMHANDLE pSSM, uint8_t volatile *pu8));
2923	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8,(PSSMHANDLE pSSM, int8_t *pi8));
2924	DECLR3CALLBACKMEMBER(int, pfnSSMGetS8V,(PSSMHANDLE pSSM, int8_t volatile *pi8));
2925	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16,(PSSMHANDLE pSSM, uint16_t *pu16));
2926	DECLR3CALLBACKMEMBER(int, pfnSSMGetU16V,(PSSMHANDLE pSSM, uint16_t volatile *pu16));
2927	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16,(PSSMHANDLE pSSM, int16_t *pi16));
2928	DECLR3CALLBACKMEMBER(int, pfnSSMGetS16V,(PSSMHANDLE pSSM, int16_t volatile *pi16));
2929	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32,(PSSMHANDLE pSSM, uint32_t *pu32));
2930	DECLR3CALLBACKMEMBER(int, pfnSSMGetU32V,(PSSMHANDLE pSSM, uint32_t volatile *pu32));
2931	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32,(PSSMHANDLE pSSM, int32_t *pi32));
2932	DECLR3CALLBACKMEMBER(int, pfnSSMGetS32V,(PSSMHANDLE pSSM, int32_t volatile *pi32));
2933	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64,(PSSMHANDLE pSSM, uint64_t *pu64));
2934	DECLR3CALLBACKMEMBER(int, pfnSSMGetU64V,(PSSMHANDLE pSSM, uint64_t volatile *pu64));
2935	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64,(PSSMHANDLE pSSM, int64_t *pi64));
2936	DECLR3CALLBACKMEMBER(int, pfnSSMGetS64V,(PSSMHANDLE pSSM, int64_t volatile *pi64));
2937	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128,(PSSMHANDLE pSSM, uint128_t *pu128));
2938	DECLR3CALLBACKMEMBER(int, pfnSSMGetU128V,(PSSMHANDLE pSSM, uint128_t volatile *pu128));
2939	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128,(PSSMHANDLE pSSM, int128_t *pi128));
2940	DECLR3CALLBACKMEMBER(int, pfnSSMGetS128V,(PSSMHANDLE pSSM, int128_t volatile *pi128));
2941	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32,(PSSMHANDLE pSSM, PRTGCPHYS32 pGCPhys));
2942	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys32V,(PSSMHANDLE pSSM, RTGCPHYS32 volatile *pGCPhys));
2943	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64,(PSSMHANDLE pSSM, PRTGCPHYS64 pGCPhys));
2944	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys64V,(PSSMHANDLE pSSM, RTGCPHYS64 volatile *pGCPhys));
2945	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhys,(PSSMHANDLE pSSM, PRTGCPHYS pGCPhys));
2946	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPhysV,(PSSMHANDLE pSSM, RTGCPHYS volatile *pGCPhys));
2947	DECLR3CALLBACKMEMBER(int, pfnSSMGetUInt,(PSSMHANDLE pSSM, PRTUINT pu));
2948	DECLR3CALLBACKMEMBER(int, pfnSSMGetSInt,(PSSMHANDLE pSSM, PRTINT pi));
2949	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUInt,(PSSMHANDLE pSSM, PRTGCUINT pu));
2950	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntReg,(PSSMHANDLE pSSM, PRTGCUINTREG pu));
2951	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCPtr,(PSSMHANDLE pSSM, PRTGCPTR pGCPtr));
2952	DECLR3CALLBACKMEMBER(int, pfnSSMGetGCUIntPtr,(PSSMHANDLE pSSM, PRTGCUINTPTR pGCPtr));
2953	DECLR3CALLBACKMEMBER(int, pfnSSMGetRCPtr,(PSSMHANDLE pSSM, PRTRCPTR pRCPtr));
2954	DECLR3CALLBACKMEMBER(int, pfnSSMGetIOPort,(PSSMHANDLE pSSM, PRTIOPORT pIOPort));
2955	DECLR3CALLBACKMEMBER(int, pfnSSMGetSel,(PSSMHANDLE pSSM, PRTSEL pSel));
2956	DECLR3CALLBACKMEMBER(int, pfnSSMGetMem,(PSSMHANDLE pSSM, void *pv, size_t cb));
2957	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZ,(PSSMHANDLE pSSM, char *psz, size_t cbMax));
2958	DECLR3CALLBACKMEMBER(int, pfnSSMGetStrZEx,(PSSMHANDLE pSSM, char psz, size_t cbMax, size_t pcbStr));
2959	DECLR3CALLBACKMEMBER(int, pfnSSMSkip,(PSSMHANDLE pSSM, size_t cb));
2960	DECLR3CALLBACKMEMBER(int, pfnSSMSkipToEndOfUnit,(PSSMHANDLE pSSM));
2961	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadError,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(6, 7));
2962	DECLR3CALLBACKMEMBER(int, pfnSSMSetLoadErrorV,(PSSMHANDLE pSSM, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
2963	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgError,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, ...) RT_IPRT_FORMAT_ATTR(5, 6));
2964	DECLR3CALLBACKMEMBER(int, pfnSSMSetCfgErrorV,(PSSMHANDLE pSSM, RT_SRC_POS_DECL, const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(5, 0));
2965	DECLR3CALLBACKMEMBER(int, pfnSSMHandleGetStatus,(PSSMHANDLE pSSM));
2966	DECLR3CALLBACKMEMBER(SSMAFTER, pfnSSMHandleGetAfter,(PSSMHANDLE pSSM));
2967	DECLR3CALLBACKMEMBER(bool, pfnSSMHandleIsLiveSave,(PSSMHANDLE pSSM));
2968	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleMaxDowntime,(PSSMHANDLE pSSM));
2969	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleHostBits,(PSSMHANDLE pSSM));
2970	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleRevision,(PSSMHANDLE pSSM));
2971	DECLR3CALLBACKMEMBER(uint32_t, pfnSSMHandleVersion,(PSSMHANDLE pSSM));
2972	DECLR3CALLBACKMEMBER(const char *, pfnSSMHandleHostOSAndArch,(PSSMHANDLE pSSM));
2973	/** @} */
2974
2975	/**
2976	* Creates a timer w/ a cross context handle.
2977	*
2978	* @returns VBox status.
2979	* @param pDevIns The device instance.
2980	* @param enmClock The clock to use on this timer.
2981	* @param pfnCallback Callback function.
2982	* @param pvUser User argument for the callback.
2983	* @param fFlags Flags, see TMTIMER_FLAGS_*.
2984	* @param pszDesc Pointer to description string which must stay around
2985	* until the timer is fully destroyed (i.e. a bit after TMTimerDestroy()).
2986	* @param phTimer Where to store the timer handle on success.
2987	* @remarks Caller enters the device critical section prior to invoking the
2988	* callback.
2989	*/
2990	DECLR3CALLBACKMEMBER(int, pfnTimerCreate,(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback,
2991	void pvUser, uint32_t fFlags, const char pszDesc, PTMTIMERHANDLE phTimer));
2992
2993	/** @name Timer handle method wrappers
2994	* @{ */
2995	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
2996	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
2997	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
2998	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
2999	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3000	DECLR3CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3001	DECLR3CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3002	DECLR3CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3003	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
3004	/** Takes the clock lock then enters the specified critical section. */
3005	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
3006	DECLR3CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
3007	DECLR3CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
3008	DECLR3CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
3009	DECLR3CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
3010	DECLR3CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
3011	DECLR3CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
3012	DECLR3CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3013	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3014	DECLR3CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3015	DECLR3CALLBACKMEMBER(int, pfnTimerSetCritSect,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
3016	DECLR3CALLBACKMEMBER(int, pfnTimerSave,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3017	DECLR3CALLBACKMEMBER(int, pfnTimerLoad,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM));
3018	DECLR3CALLBACKMEMBER(int, pfnTimerDestroy,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
3019	/** @sa TMR3TimerSkip */
3020	DECLR3CALLBACKMEMBER(int, pfnTimerSkipLoad,(PSSMHANDLE pSSM, bool *pfActive));
3021	/** @} */
3022
3023	/**
3024	* Get the real world UTC time adjusted for VM lag, user offset and warpdrive.
3025	*
3026	* @returns pTime.
3027	* @param pDevIns The device instance.
3028	* @param pTime Where to store the time.
3029	*/
3030	DECLR3CALLBACKMEMBER(PRTTIMESPEC, pfnTMUtcNow,(PPDMDEVINS pDevIns, PRTTIMESPEC pTime));
3031
3032	/** @name Exported CFGM Functions.
3033	* @{ */
3034	DECLR3CALLBACKMEMBER(bool, pfnCFGMExists,( PCFGMNODE pNode, const char *pszName));
3035	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryType,( PCFGMNODE pNode, const char *pszName, PCFGMVALUETYPE penmType));
3036	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySize,( PCFGMNODE pNode, const char pszName, size_t pcb));
3037	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryInteger,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3038	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryIntegerDef,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3039	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryString,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3040	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3041	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPassword,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString));
3042	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPasswordDef,( PCFGMNODE pNode, const char pszName, char pszString, size_t cchString, const char *pszDef));
3043	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBytes,( PCFGMNODE pNode, const char pszName, void pvData, size_t cbData));
3044	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64,( PCFGMNODE pNode, const char pszName, uint64_t pu64));
3045	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU64Def,( PCFGMNODE pNode, const char pszName, uint64_t pu64, uint64_t u64Def));
3046	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64,( PCFGMNODE pNode, const char pszName, int64_t pi64));
3047	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS64Def,( PCFGMNODE pNode, const char pszName, int64_t pi64, int64_t i64Def));
3048	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32,( PCFGMNODE pNode, const char pszName, uint32_t pu32));
3049	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU32Def,( PCFGMNODE pNode, const char pszName, uint32_t pu32, uint32_t u32Def));
3050	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32,( PCFGMNODE pNode, const char pszName, int32_t pi32));
3051	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS32Def,( PCFGMNODE pNode, const char pszName, int32_t pi32, int32_t i32Def));
3052	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16,( PCFGMNODE pNode, const char pszName, uint16_t pu16));
3053	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU16Def,( PCFGMNODE pNode, const char pszName, uint16_t pu16, uint16_t u16Def));
3054	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16,( PCFGMNODE pNode, const char pszName, int16_t pi16));
3055	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS16Def,( PCFGMNODE pNode, const char pszName, int16_t pi16, int16_t i16Def));
3056	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8,( PCFGMNODE pNode, const char pszName, uint8_t pu8));
3057	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryU8Def,( PCFGMNODE pNode, const char pszName, uint8_t pu8, uint8_t u8Def));
3058	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8,( PCFGMNODE pNode, const char pszName, int8_t pi8));
3059	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryS8Def,( PCFGMNODE pNode, const char pszName, int8_t pi8, int8_t i8Def));
3060	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBool,( PCFGMNODE pNode, const char pszName, bool pf));
3061	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryBoolDef,( PCFGMNODE pNode, const char pszName, bool pf, bool fDef));
3062	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPort,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort));
3063	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryPortDef,( PCFGMNODE pNode, const char *pszName, PRTIOPORT pPort, RTIOPORT PortDef));
3064	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUInt,( PCFGMNODE pNode, const char pszName, unsigned int pu));
3065	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryUIntDef,( PCFGMNODE pNode, const char pszName, unsigned int pu, unsigned int uDef));
3066	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySInt,( PCFGMNODE pNode, const char pszName, signed int pi));
3067	DECLR3CALLBACKMEMBER(int, pfnCFGMQuerySIntDef,( PCFGMNODE pNode, const char pszName, signed int pi, signed int iDef));
3068	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtr,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr));
3069	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrDef,( PCFGMNODE pNode, const char *pszName, PRTGCPTR pGCPtr, RTGCPTR GCPtrDef));
3070	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrU,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr));
3071	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrUDef,( PCFGMNODE pNode, const char *pszName, PRTGCUINTPTR pGCPtr, RTGCUINTPTR GCPtrDef));
3072	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrS,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr));
3073	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryGCPtrSDef,( PCFGMNODE pNode, const char *pszName, PRTGCINTPTR pGCPtr, RTGCINTPTR GCPtrDef));
3074	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAlloc,( PCFGMNODE pNode, const char pszName, char *ppszString));
3075	DECLR3CALLBACKMEMBER(int, pfnCFGMQueryStringAllocDef,(PCFGMNODE pNode, const char pszName, char ppszString, const char pszDef));
3076	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetParent,(PCFGMNODE pNode));
3077	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChild,(PCFGMNODE pNode, const char *pszPath));
3078	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildF,(PCFGMNODE pNode, const char *pszPathFormat, ...) RT_IPRT_FORMAT_ATTR(2, 3));
3079	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetChildFV,(PCFGMNODE pNode, const char *pszPathFormat, va_list Args) RT_IPRT_FORMAT_ATTR(3, 0));
3080	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetFirstChild,(PCFGMNODE pNode));
3081	DECLR3CALLBACKMEMBER(PCFGMNODE, pfnCFGMGetNextChild,(PCFGMNODE pCur));
3082	DECLR3CALLBACKMEMBER(int, pfnCFGMGetName,(PCFGMNODE pCur, char *pszName, size_t cchName));
3083	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetNameLen,(PCFGMNODE pCur));
3084	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreChildrenValid,(PCFGMNODE pNode, const char *pszzValid));
3085	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetFirstValue,(PCFGMNODE pCur));
3086	DECLR3CALLBACKMEMBER(PCFGMLEAF, pfnCFGMGetNextValue,(PCFGMLEAF pCur));
3087	DECLR3CALLBACKMEMBER(int, pfnCFGMGetValueName,(PCFGMLEAF pCur, char *pszName, size_t cchName));
3088	DECLR3CALLBACKMEMBER(size_t, pfnCFGMGetValueNameLen,(PCFGMLEAF pCur));
3089	DECLR3CALLBACKMEMBER(CFGMVALUETYPE, pfnCFGMGetValueType,(PCFGMLEAF pCur));
3090	DECLR3CALLBACKMEMBER(bool, pfnCFGMAreValuesValid,(PCFGMNODE pNode, const char *pszzValid));
3091	DECLR3CALLBACKMEMBER(int, pfnCFGMValidateConfig,(PCFGMNODE pNode, const char *pszNode,
3092	const char pszValidValues, const char pszValidNodes,
3093	const char *pszWho, uint32_t uInstance));
3094	/** @} */
3095
3096	/**
3097	* Read physical memory.
3098	*
3099	* @returns VINF_SUCCESS (for now).
3100	* @param pDevIns The device instance.
3101	* @param GCPhys Physical address start reading from.
3102	* @param pvBuf Where to put the read bits.
3103	* @param cbRead How many bytes to read.
3104	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3105	* @thread Any thread, but the call may involve the emulation thread.
3106	*/
3107	DECLR3CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3108
3109	/**
3110	* Write to physical memory.
3111	*
3112	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
3113	* @param pDevIns The device instance.
3114	* @param GCPhys Physical address to write to.
3115	* @param pvBuf What to write.
3116	* @param cbWrite How many bytes to write.
3117	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3118	* @thread Any thread, but the call may involve the emulation thread.
3119	*/
3120	DECLR3CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3121
3122	/**
3123	* Requests the mapping of a guest page into ring-3.
3124	*
3125	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3126	* release it.
3127	*
3128	* This API will assume your intention is to write to the page, and will
3129	* therefore replace shared and zero pages. If you do not intend to modify the
3130	* page, use the pfnPhysGCPhys2CCPtrReadOnly() API.
3131	*
3132	* @returns VBox status code.
3133	* @retval VINF_SUCCESS on success.
3134	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3135	* backing or if the page has any active access handlers. The caller
3136	* must fall back on using PGMR3PhysWriteExternal.
3137	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3138	*
3139	* @param pDevIns The device instance.
3140	* @param GCPhys The guest physical address of the page that
3141	* should be mapped.
3142	* @param fFlags Flags reserved for future use, MBZ.
3143	* @param ppv Where to store the address corresponding to
3144	* GCPhys.
3145	* @param pLock Where to store the lock information that
3146	* pfnPhysReleasePageMappingLock needs.
3147	*
3148	* @remark Avoid calling this API from within critical sections (other than the
3149	* PGM one) because of the deadlock risk when we have to delegating the
3150	* task to an EMT.
3151	* @thread Any.
3152	*/
3153	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv,
3154	PPGMPAGEMAPLOCK pLock));
3155
3156	/**
3157	* Requests the mapping of a guest page into ring-3, external threads.
3158	*
3159	* When you're done with the page, call pfnPhysReleasePageMappingLock() ASAP to
3160	* release it.
3161	*
3162	* @returns VBox status code.
3163	* @retval VINF_SUCCESS on success.
3164	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
3165	* backing or if the page as an active ALL access handler. The caller
3166	* must fall back on using PGMPhysRead.
3167	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3168	*
3169	* @param pDevIns The device instance.
3170	* @param GCPhys The guest physical address of the page that
3171	* should be mapped.
3172	* @param fFlags Flags reserved for future use, MBZ.
3173	* @param ppv Where to store the address corresponding to
3174	* GCPhys.
3175	* @param pLock Where to store the lock information that
3176	* pfnPhysReleasePageMappingLock needs.
3177	*
3178	* @remark Avoid calling this API from within critical sections.
3179	* @thread Any.
3180	*/
3181	DECLR3CALLBACKMEMBER(int, pfnPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags,
3182	void const **ppv, PPGMPAGEMAPLOCK pLock));
3183
3184	/**
3185	* Release the mapping of a guest page.
3186	*
3187	* This is the counter part of pfnPhysGCPhys2CCPtr and
3188	* pfnPhysGCPhys2CCPtrReadOnly.
3189	*
3190	* @param pDevIns The device instance.
3191	* @param pLock The lock structure initialized by the mapping
3192	* function.
3193	*/
3194	DECLR3CALLBACKMEMBER(void, pfnPhysReleasePageMappingLock,(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock));
3195
3196	/**
3197	* Read guest physical memory by virtual address.
3198	*
3199	* @param pDevIns The device instance.
3200	* @param pvDst Where to put the read bits.
3201	* @param GCVirtSrc Guest virtual address to start reading from.
3202	* @param cb How many bytes to read.
3203	* @thread The emulation thread.
3204	*/
3205	DECLR3CALLBACKMEMBER(int, pfnPhysReadGCVirt,(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb));
3206
3207	/**
3208	* Write to guest physical memory by virtual address.
3209	*
3210	* @param pDevIns The device instance.
3211	* @param GCVirtDst Guest virtual address to write to.
3212	* @param pvSrc What to write.
3213	* @param cb How many bytes to write.
3214	* @thread The emulation thread.
3215	*/
3216	DECLR3CALLBACKMEMBER(int, pfnPhysWriteGCVirt,(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb));
3217
3218	/**
3219	* Convert a guest virtual address to a guest physical address.
3220	*
3221	* @returns VBox status code.
3222	* @param pDevIns The device instance.
3223	* @param GCPtr Guest virtual address.
3224	* @param pGCPhys Where to store the GC physical address
3225	* corresponding to GCPtr.
3226	* @thread The emulation thread.
3227	* @remark Careful with page boundaries.
3228	*/
3229	DECLR3CALLBACKMEMBER(int, pfnPhysGCPtr2GCPhys, (PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys));
3230
3231	/**
3232	* Checks if a GC physical address is a normal page,
3233	* i.e. not ROM, MMIO or reserved.
3234	*
3235	* @returns true if normal.
3236	* @returns false if invalid, ROM, MMIO or reserved page.
3237	* @param pDevIns The device instance.
3238	* @param GCPhys The physical address to check.
3239	*/
3240	DECLR3CALLBACKMEMBER(bool, pfnPhysIsGCPhysNormal,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
3241
3242	/**
3243	* Inflate or deflate a memory balloon
3244	*
3245	* @returns VBox status code.
3246	* @param pDevIns The device instance.
3247	* @param fInflate Inflate or deflate memory balloon
3248	* @param cPages Number of pages to free
3249	* @param paPhysPage Array of guest physical addresses
3250	*/
3251	DECLR3CALLBACKMEMBER(int, pfnPhysChangeMemBalloon,(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage));
3252
3253	/**
3254	* Allocate memory which is associated with current VM instance
3255	* and automatically freed on it's destruction.
3256	*
3257	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3258	* @param pDevIns The device instance.
3259	* @param cb Number of bytes to allocate.
3260	*/
3261	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAlloc,(PPDMDEVINS pDevIns, size_t cb));
3262
3263	/**
3264	* Allocate memory which is associated with current VM instance
3265	* and automatically freed on it's destruction. The memory is ZEROed.
3266	*
3267	* @returns Pointer to allocated memory. The memory is NOT zero-ed.
3268	* @param pDevIns The device instance.
3269	* @param cb Number of bytes to allocate.
3270	*/
3271	DECLR3CALLBACKMEMBER(void *, pfnMMHeapAllocZ,(PPDMDEVINS pDevIns, size_t cb));
3272
3273	/**
3274	* Allocating string printf.
3275	*
3276	* @returns Pointer to the string.
3277	* @param pDevIns The device instance.
3278	* @param enmTag The statistics tag.
3279	* @param pszFormat The format string.
3280	* @param va Format arguments.
3281	*/
3282	DECLR3CALLBACKMEMBER(char , pfnMMHeapAPrintfV,(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, va_list va));
3283
3284	/**
3285	* Free memory allocated with pfnMMHeapAlloc() and pfnMMHeapAllocZ().
3286	*
3287	* @param pDevIns The device instance.
3288	* @param pv Pointer to the memory to free.
3289	*/
3290	DECLR3CALLBACKMEMBER(void, pfnMMHeapFree,(PPDMDEVINS pDevIns, void *pv));
3291
3292	/**
3293	* Returns the physical RAM size of the VM.
3294	*
3295	* @returns RAM size in bytes.
3296	* @param pDevIns The device instance.
3297	*/
3298	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSize,(PPDMDEVINS pDevIns));
3299
3300	/**
3301	* Returns the physical RAM size of the VM below the 4GB boundary.
3302	*
3303	* @returns RAM size in bytes.
3304	* @param pDevIns The device instance.
3305	*/
3306	DECLR3CALLBACKMEMBER(uint32_t, pfnMMPhysGetRamSizeBelow4GB,(PPDMDEVINS pDevIns));
3307
3308	/**
3309	* Returns the physical RAM size of the VM above the 4GB boundary.
3310	*
3311	* @returns RAM size in bytes.
3312	* @param pDevIns The device instance.
3313	*/
3314	DECLR3CALLBACKMEMBER(uint64_t, pfnMMPhysGetRamSizeAbove4GB,(PPDMDEVINS pDevIns));
3315
3316	/**
3317	* Gets the VM state.
3318	*
3319	* @returns VM state.
3320	* @param pDevIns The device instance.
3321	* @thread Any thread (just keep in mind that it's volatile info).
3322	*/
3323	DECLR3CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
3324
3325	/**
3326	* Checks if the VM was teleported and hasn't been fully resumed yet.
3327	*
3328	* @returns true / false.
3329	* @param pDevIns The device instance.
3330	* @thread Any thread.
3331	*/
3332	DECLR3CALLBACKMEMBER(bool, pfnVMTeleportedAndNotFullyResumedYet,(PPDMDEVINS pDevIns));
3333
3334	/**
3335	* Set the VM error message
3336	*
3337	* @returns rc.
3338	* @param pDevIns The device instance.
3339	* @param rc VBox status code.
3340	* @param SRC_POS Use RT_SRC_POS.
3341	* @param pszFormat Error message format string.
3342	* @param va Error message arguments.
3343	*/
3344	DECLR3CALLBACKMEMBER(int, pfnVMSetErrorV,(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL,
3345	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
3346
3347	/**
3348	* Set the VM runtime error message
3349	*
3350	* @returns VBox status code.
3351	* @param pDevIns The device instance.
3352	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
3353	* @param pszErrorId Error ID string.
3354	* @param pszFormat Error message format string.
3355	* @param va Error message arguments.
3356	*/
3357	DECLR3CALLBACKMEMBER(int, pfnVMSetRuntimeErrorV,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
3358	const char *pszFormat, va_list va) RT_IPRT_FORMAT_ATTR(4, 0));
3359
3360	/**
3361	* Special interface for implementing a HLT-like port on a device.
3362	*
3363	* This can be called directly from device code, provide the device is trusted
3364	* to access the VMM directly. Since we may not have an accurate register set
3365	* and the caller certainly shouldn't (device code does not access CPU
3366	* registers), this function will return when interrupts are pending regardless
3367	* of the actual EFLAGS.IF state.
3368	*
3369	* @returns VBox error status (never informational statuses).
3370	* @param pDevIns The device instance.
3371	* @param idCpu The id of the calling EMT.
3372	*/
3373	DECLR3CALLBACKMEMBER(int, pfnVMWaitForDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3374
3375	/**
3376	* Wakes up a CPU that has called PDMDEVHLPR3::pfnVMWaitForDeviceReady.
3377	*
3378	* @returns VBox error status (never informational statuses).
3379	* @param pDevIns The device instance.
3380	* @param idCpu The id of the calling EMT.
3381	*/
3382	DECLR3CALLBACKMEMBER(int, pfnVMNotifyCpuDeviceReady,(PPDMDEVINS pDevIns, VMCPUID idCpu));
3383
3384	/**
3385	* Convenience wrapper for VMR3ReqCallU.
3386	*
3387	* This assumes (1) you're calling a function that returns an VBox status code
3388	* and that you do not wish to wait for it to complete.
3389	*
3390	* @returns VBox status code returned by VMR3ReqCallVU.
3391	*
3392	* @param pDevIns The device instance.
3393	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3394	* one of the following special values:
3395	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3396	* @param pfnFunction Pointer to the function to call.
3397	* @param cArgs Number of arguments following in the ellipsis.
3398	* @param Args Argument vector.
3399	*
3400	* @remarks See remarks on VMR3ReqCallVU.
3401	*/
3402	DECLR3CALLBACKMEMBER(int, pfnVMReqCallNoWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs,
3403	va_list Args)) RT_IPRT_CALLREQ_ATTR(3, 4, 0);
3404
3405	/**
3406	* Convenience wrapper for VMR3ReqCallU.
3407	*
3408	* This assumes (1) you're calling a function that returns void, (2) that you
3409	* wish to wait for ever for it to return, and (3) that it's priority request
3410	* that can be safely be handled during async suspend and power off.
3411	*
3412	* @returns VBox status code of VMR3ReqCallVU.
3413	*
3414	* @param pDevIns The device instance.
3415	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
3416	* one of the following special values:
3417	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
3418	* @param pfnFunction Pointer to the function to call.
3419	* @param cArgs Number of arguments following in the ellipsis.
3420	* @param Args Argument vector.
3421	*
3422	* @remarks See remarks on VMR3ReqCallVU.
3423	*/
3424	DECLR3CALLBACKMEMBER(int, pfnVMReqPriorityCallWaitV,(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs,
3425	va_list Args)) RT_IPRT_CALLREQ_ATTR(3, 4, 0);
3426
3427	/**
3428	* Stops the VM and enters the debugger to look at the guest state.
3429	*
3430	* Use the PDMDeviceDBGFStop() inline function with the RT_SRC_POS macro instead of
3431	* invoking this function directly.
3432	*
3433	* @returns VBox status code which must be passed up to the VMM.
3434	* @param pDevIns The device instance.
3435	* @param pszFile Filename of the assertion location.
3436	* @param iLine The linenumber of the assertion location.
3437	* @param pszFunction Function of the assertion location.
3438	* @param pszFormat Message. (optional)
3439	* @param args Message parameters.
3440	*/
3441	DECLR3CALLBACKMEMBER(int, pfnDBGFStopV,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction,
3442	const char *pszFormat, va_list args) RT_IPRT_FORMAT_ATTR(5, 0));
3443
3444	/**
3445	* Register a info handler with DBGF.
3446	*
3447	* @returns VBox status code.
3448	* @param pDevIns The device instance.
3449	* @param pszName The identifier of the info.
3450	* @param pszDesc The description of the info and any arguments
3451	* the handler may take.
3452	* @param pfnHandler The handler function to be called to display the
3453	* info.
3454	*/
3455	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegister,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler));
3456
3457	/**
3458	* Register a info handler with DBGF, argv style.
3459	*
3460	* @returns VBox status code.
3461	* @param pDevIns The device instance.
3462	* @param pszName The identifier of the info.
3463	* @param pszDesc The description of the info and any arguments
3464	* the handler may take.
3465	* @param pfnHandler The handler function to be called to display the
3466	* info.
3467	*/
3468	DECLR3CALLBACKMEMBER(int, pfnDBGFInfoRegisterArgv,(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler));
3469
3470	/**
3471	* Registers a set of registers for a device.
3472	*
3473	* The @a pvUser argument of the getter and setter callbacks will be
3474	* @a pDevIns. The register names will be prefixed by the device name followed
3475	* immediately by the instance number.
3476	*
3477	* @returns VBox status code.
3478	* @param pDevIns The device instance.
3479	* @param paRegisters The register descriptors.
3480	*
3481	* @remarks The device critical section is NOT entered prior to working the
3482	* callbacks registered via this helper!
3483	*/
3484	DECLR3CALLBACKMEMBER(int, pfnDBGFRegRegister,(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters));
3485
3486	/**
3487	* Gets the trace buffer handle.
3488	*
3489	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
3490	* really inteded for direct usage, thus no inline wrapper function.
3491	*
3492	* @returns Trace buffer handle or NIL_RTTRACEBUF.
3493	* @param pDevIns The device instance.
3494	*/
3495	DECLR3CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
3496
3497	/**
3498	* Report a bug check.
3499	*
3500	* @returns
3501	* @param pDevIns The device instance.
3502	* @param enmEvent The kind of BSOD event this is.
3503	* @param uBugCheck The bug check number.
3504	* @param uP1 The bug check parameter \#1.
3505	* @param uP2 The bug check parameter \#2.
3506	* @param uP3 The bug check parameter \#3.
3507	* @param uP4 The bug check parameter \#4.
3508	*
3509	* @thread EMT
3510	*/
3511	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnDBGFReportBugCheck,(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
3512	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4));
3513
3514	/**
3515	* Write core dump of the guest.
3516	*
3517	* @returns VBox status code.
3518	* @param pDevIns The device instance.
3519	* @param pszFilename The name of the file to which the guest core
3520	* dump should be written.
3521	* @param fReplaceFile Whether to replace the file or not.
3522	*
3523	* @remarks The VM may need to be suspended before calling this function in
3524	* order to truly stop all device threads and drivers. This function
3525	* only synchronizes EMTs.
3526	*/
3527	DECLR3CALLBACKMEMBER(int, pfnDBGFCoreWrite,(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile));
3528
3529	/**
3530	* Gets the logger info helper.
3531	* The returned info helper will unconditionally write all output to the log.
3532	*
3533	* @returns Pointer to the logger info helper.
3534	* @param pDevIns The device instance.
3535	*/
3536	DECLR3CALLBACKMEMBER(PCDBGFINFOHLP, pfnDBGFInfoLogHlp,(PPDMDEVINS pDevIns));
3537
3538	/**
3539	* Queries a 64-bit register value.
3540	*
3541	* @retval VINF_SUCCESS
3542	* @retval VERR_INVALID_VM_HANDLE
3543	* @retval VERR_INVALID_CPU_ID
3544	* @retval VERR_DBGF_REGISTER_NOT_FOUND
3545	* @retval VERR_DBGF_UNSUPPORTED_CAST
3546	* @retval VINF_DBGF_TRUNCATED_REGISTER
3547	* @retval VINF_DBGF_ZERO_EXTENDED_REGISTER
3548	*
3549	* @param pDevIns The device instance.
3550	* @param idDefCpu The default target CPU ID, VMCPUID_ANY if not
3551	* applicable. Can be OR'ed with
3552	* DBGFREG_HYPER_VMCPUID.
3553	* @param pszReg The register that's being queried. Except for
3554	* CPU registers, this must be on the form
3555	* "set.reg[.sub]".
3556	* @param pu64 Where to store the register value.
3557	*/
3558	DECLR3CALLBACKMEMBER(int, pfnDBGFRegNmQueryU64,(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64));
3559
3560	/**
3561	* Format a set of registers.
3562	*
3563	* This is restricted to registers from one CPU, that specified by @a idCpu.
3564	*
3565	* @returns VBox status code.
3566	* @param pDevIns The device instance.
3567	* @param idCpu The CPU ID of any CPU registers that may be
3568	* printed, pass VMCPUID_ANY if not applicable.
3569	* @param pszBuf The output buffer.
3570	* @param cbBuf The size of the output buffer.
3571	* @param pszFormat The format string. Register names are given by
3572	* %VR{name}, they take no arguments.
3573	* @param va Other format arguments.
3574	*/
3575	DECLR3CALLBACKMEMBER(int, pfnDBGFRegPrintfV,(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
3576	const char *pszFormat, va_list va));
3577
3578	/**
3579	* Registers a statistics sample.
3580	*
3581	* @param pDevIns Device instance of the DMA.
3582	* @param pvSample Pointer to the sample.
3583	* @param enmType Sample type. This indicates what pvSample is
3584	* pointing at.
3585	* @param pszName Sample name, unix path style. If this does not
3586	* start with a '/', the default prefix will be
3587	* prepended, otherwise it will be used as-is.
3588	* @param enmUnit Sample unit.
3589	* @param pszDesc Sample description.
3590	*/
3591	DECLR3CALLBACKMEMBER(void, pfnSTAMRegister,(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc));
3592
3593	/**
3594	* Same as pfnSTAMRegister except that the name is specified in a
3595	* RTStrPrintfV like fashion.
3596	*
3597	* @param pDevIns Device instance of the DMA.
3598	* @param pvSample Pointer to the sample.
3599	* @param enmType Sample type. This indicates what pvSample is
3600	* pointing at.
3601	* @param enmVisibility Visibility type specifying whether unused
3602	* statistics should be visible or not.
3603	* @param enmUnit Sample unit.
3604	* @param pszDesc Sample description.
3605	* @param pszName Sample name format string, unix path style. If
3606	* this does not start with a '/', the default
3607	* prefix will be prepended, otherwise it will be
3608	* used as-is.
3609	* @param args Arguments to the format string.
3610	*/
3611	DECLR3CALLBACKMEMBER(void, pfnSTAMRegisterV,(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
3612	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, const char *pszDesc,
3613	const char *pszName, va_list args) RT_IPRT_FORMAT_ATTR(7, 0));
3614
3615	/**
3616	* Registers a PCI device with the default PCI bus.
3617	*
3618	* If a PDM device has more than one PCI device, they must be registered in the
3619	* order of PDMDEVINSR3::apPciDevs.
3620	*
3621	* @returns VBox status code.
3622	* @param pDevIns The device instance.
3623	* @param pPciDev The PCI device structure.
3624	* This must be kept in the instance data.
3625	* The PCI configuration must be initialized before registration.
3626	* @param fFlags 0, PDMPCIDEVREG_F_PCI_BRIDGE or
3627	* PDMPCIDEVREG_F_NOT_MANDATORY_NO.
3628	* @param uPciDevNo PDMPCIDEVREG_DEV_NO_FIRST_UNUSED,
3629	* PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, or a specific
3630	* device number (0-31). This will be ignored if
3631	* the CFGM configuration contains a PCIDeviceNo
3632	* value.
3633	* @param uPciFunNo PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, or a specific
3634	* function number (0-7). This will be ignored if
3635	* the CFGM configuration contains a PCIFunctionNo
3636	* value.
3637	* @param pszName Device name, if NULL PDMDEVREG::szName is used.
3638	* The pointer is saved, so don't free or changed.
3639	* @note The PCI device configuration is now implicit from the apPciDevs
3640	* index, meaning that the zero'th entry is the primary one and
3641	* subsequent uses CFGM subkeys "PciDev1", "PciDev2" and so on.
3642	*/
3643	DECLR3CALLBACKMEMBER(int, pfnPCIRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
3644	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
3645
3646	/**
3647	* Initialize MSI or MSI-X emulation support for the given PCI device.
3648	*
3649	* @see PDMPCIBUSREG::pfnRegisterMsiR3 for details.
3650	*
3651	* @returns VBox status code.
3652	* @param pDevIns The device instance.
3653	* @param pPciDev The PCI device. NULL is an alias for the first
3654	* one registered.
3655	* @param pMsiReg MSI emulation registration structure.
3656	*/
3657	DECLR3CALLBACKMEMBER(int, pfnPCIRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
3658
3659	/**
3660	* Registers a I/O region (memory mapped or I/O ports) for a PCI device.
3661	*
3662	* @returns VBox status code.
3663	* @param pDevIns The device instance.
3664	* @param pPciDev The PCI device structure. If NULL the default
3665	* PCI device for this device instance is used.
3666	* @param iRegion The region number.
3667	* @param cbRegion Size of the region.
3668	* @param enmType PCI_ADDRESS_SPACE_MEM, PCI_ADDRESS_SPACE_IO or PCI_ADDRESS_SPACE_MEM_PREFETCH.
3669	* @param fFlags PDMPCIDEV_IORGN_F_XXX.
3670	* @param hHandle An I/O port, MMIO or MMIO2 handle according to
3671	* @a fFlags, UINT64_MAX if no handle is passed
3672	* (old style).
3673	* @param pfnMapUnmap Callback for doing the mapping, optional when a
3674	* handle is specified. The callback will be
3675	* invoked holding only the PDM lock. The device
3676	* lock will _not_ be taken (due to lock order).
3677	*/
3678	DECLR3CALLBACKMEMBER(int, pfnPCIIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3679	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
3680	uint64_t hHandle, PFNPCIIOREGIONMAP pfnMapUnmap));
3681
3682	/**
3683	* Register PCI configuration space read/write callbacks.
3684	*
3685	* @returns VBox status code.
3686	* @param pDevIns The device instance.
3687	* @param pPciDev The PCI device structure. If NULL the default
3688	* PCI device for this device instance is used.
3689	* @param pfnRead Pointer to the user defined PCI config read function.
3690	* to call default PCI config read function. Can be NULL.
3691	* @param pfnWrite Pointer to the user defined PCI config write function.
3692	* @remarks The callbacks will be invoked holding the PDM lock. The device lock
3693	* is NOT take because that is very likely be a lock order violation.
3694	* @thread EMT(0)
3695	* @note Only callable during VM creation.
3696	* @sa PDMDevHlpPCIConfigRead, PDMDevHlpPCIConfigWrite
3697	*/
3698	DECLR3CALLBACKMEMBER(int, pfnPCIInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3699	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
3700
3701	/**
3702	* Perform a PCI configuration space write.
3703	*
3704	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3705	*
3706	* @returns Strict VBox status code (mainly DBGFSTOP).
3707	* @param pDevIns The device instance.
3708	* @param pPciDev The PCI device which config space is being read.
3709	* @param uAddress The config space address.
3710	* @param cb The size of the read: 1, 2 or 4 bytes.
3711	* @param u32Value The value to write.
3712	*/
3713	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3714	uint32_t uAddress, unsigned cb, uint32_t u32Value));
3715
3716	/**
3717	* Perform a PCI configuration space read.
3718	*
3719	* This is for devices that make use of PDMDevHlpPCIInterceptConfigAccesses().
3720	*
3721	* @returns Strict VBox status code (mainly DBGFSTOP).
3722	* @param pDevIns The device instance.
3723	* @param pPciDev The PCI device which config space is being read.
3724	* @param uAddress The config space address.
3725	* @param cb The size of the read: 1, 2 or 4 bytes.
3726	* @param pu32Value Where to return the value.
3727	*/
3728	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnPCIConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3729	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
3730
3731	/**
3732	* Bus master physical memory read.
3733	*
3734	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
3735	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3736	* @param pDevIns The device instance.
3737	* @param pPciDev The PCI device structure. If NULL the default
3738	* PCI device for this device instance is used.
3739	* @param GCPhys Physical address start reading from.
3740	* @param pvBuf Where to put the read bits.
3741	* @param cbRead How many bytes to read.
3742	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3743	* @thread Any thread, but the call may involve the emulation thread.
3744	*/
3745	DECLR3CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
3746
3747	/**
3748	* Bus master physical memory write.
3749	*
3750	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
3751	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
3752	* @param pDevIns The device instance.
3753	* @param pPciDev The PCI device structure. If NULL the default
3754	* PCI device for this device instance is used.
3755	* @param GCPhys Physical address to write to.
3756	* @param pvBuf What to write.
3757	* @param cbWrite How many bytes to write.
3758	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
3759	* @thread Any thread, but the call may involve the emulation thread.
3760	*/
3761	DECLR3CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
3762
3763	/**
3764	* Requests the mapping of a guest page into ring-3 in preparation for a bus master
3765	* physical memory write operation.
3766	*
3767	* Refer pfnPhysGCPhys2CCPtr() for further details.
3768	*
3769	* @returns VBox status code.
3770	* @param pDevIns The device instance.
3771	* @param pPciDev The PCI device structure. If NULL the default
3772	* PCI device for this device instance is used.
3773	* @param GCPhys The guest physical address of the page that should be
3774	* mapped.
3775	* @param fFlags Flags reserved for future use, MBZ.
3776	* @param ppv Where to store the address corresponding to GCPhys.
3777	* @param pLock Where to store the lock information that
3778	* pfnPhysReleasePageMappingLock needs.
3779	*
3780	* @remarks Avoid calling this API from within critical sections (other than the PGM
3781	* one) because of the deadlock risk when we have to delegating the task to
3782	* an EMT.
3783	* @thread Any.
3784	*/
3785	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
3786	void **ppv, PPGMPAGEMAPLOCK pLock));
3787
3788	/**
3789	* Requests the mapping of a guest page into ring-3, external threads, in prepartion
3790	* for a bus master physical memory read operation.
3791	*
3792	* Refer pfnPhysGCPhys2CCPtrReadOnly() for further details.
3793	*
3794	* @returns VBox status code.
3795	* @param pDevIns The device instance.
3796	* @param pPciDev The PCI device structure. If NULL the default
3797	* PCI device for this device instance is used.
3798	* @param GCPhys The guest physical address of the page that
3799	* should be mapped.
3800	* @param fFlags Flags reserved for future use, MBZ.
3801	* @param ppv Where to store the address corresponding to
3802	* GCPhys.
3803	* @param pLock Where to store the lock information that
3804	* pfnPhysReleasePageMappingLock needs.
3805	*
3806	* @remarks Avoid calling this API from within critical sections.
3807	* @thread Any.
3808	*/
3809	DECLR3CALLBACKMEMBER(int, pfnPCIPhysGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
3810	uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock));
3811
3812	/**
3813	* Requests the mapping of multiple guest pages into ring-3 in prepartion for a bus
3814	* master physical memory write operation.
3815	*
3816	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3817	* ASAP to release them.
3818	*
3819	* Refer pfnPhysBulkGCPhys2CCPtr() for further details.
3820	*
3821	* @returns VBox status code.
3822	* @param pDevIns The device instance.
3823	* @param pPciDev The PCI device structure. If NULL the default
3824	* PCI device for this device instance is used.
3825	* @param cPages Number of pages to lock.
3826	* @param paGCPhysPages The guest physical address of the pages that
3827	* should be mapped (@a cPages entries).
3828	* @param fFlags Flags reserved for future use, MBZ.
3829	* @param papvPages Where to store the ring-3 mapping addresses
3830	* corresponding to @a paGCPhysPages.
3831	* @param paLocks Where to store the locking information that
3832	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
3833	* in length).
3834	*/
3835	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3836	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
3837	PPGMPAGEMAPLOCK paLocks));
3838
3839	/**
3840	* Requests the mapping of multiple guest pages into ring-3 in preparation for a bus
3841	* master physical memory read operation.
3842	*
3843	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
3844	* ASAP to release them.
3845	*
3846	* Refer pfnPhysBulkGCPhys2CCPtrReadOnly() for further details.
3847	*
3848	* @returns VBox status code.
3849	* @param pDevIns The device instance.
3850	* @param pPciDev The PCI device structure. If NULL the default
3851	* PCI device for this device instance is used.
3852	* @param cPages Number of pages to lock.
3853	* @param paGCPhysPages The guest physical address of the pages that
3854	* should be mapped (@a cPages entries).
3855	* @param fFlags Flags reserved for future use, MBZ.
3856	* @param papvPages Where to store the ring-3 mapping addresses
3857	* corresponding to @a paGCPhysPages.
3858	* @param paLocks Where to store the lock information that
3859	* pfnPhysReleasePageMappingLock needs (@a cPages
3860	* in length).
3861	*/
3862	DECLR3CALLBACKMEMBER(int, pfnPCIPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
3863	PCRTGCPHYS paGCPhysPages, uint32_t fFlags,
3864	void const **papvPages, PPGMPAGEMAPLOCK paLocks));
3865
3866	/**
3867	* Sets the IRQ for the given PCI device.
3868	*
3869	* @param pDevIns The device instance.
3870	* @param pPciDev The PCI device structure. If NULL the default
3871	* PCI device for this device instance is used.
3872	* @param iIrq IRQ number to set.
3873	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3874	* @thread Any thread, but will involve the emulation thread.
3875	*/
3876	DECLR3CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3877
3878	/**
3879	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
3880	* the request when not called from EMT.
3881	*
3882	* @param pDevIns The device instance.
3883	* @param pPciDev The PCI device structure. If NULL the default
3884	* PCI device for this device instance is used.
3885	* @param iIrq IRQ number to set.
3886	* @param iLevel IRQ level.
3887	* @thread Any thread, but will involve the emulation thread.
3888	*/
3889	DECLR3CALLBACKMEMBER(void, pfnPCISetIrqNoWait,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
3890
3891	/**
3892	* Set ISA IRQ for a device.
3893	*
3894	* @param pDevIns The device instance.
3895	* @param iIrq IRQ number to set.
3896	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3897	* @thread Any thread, but will involve the emulation thread.
3898	*/
3899	DECLR3CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3900
3901	/**
3902	* Set the ISA IRQ for a device, but don't wait for EMT to process
3903	* the request when not called from EMT.
3904	*
3905	* @param pDevIns The device instance.
3906	* @param iIrq IRQ number to set.
3907	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
3908	* @thread Any thread, but will involve the emulation thread.
3909	*/
3910	DECLR3CALLBACKMEMBER(void, pfnISASetIrqNoWait,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
3911
3912	/**
3913	* Attaches a driver (chain) to the device.
3914	*
3915	* The first call for a LUN this will serve as a registration of the LUN. The pBaseInterface and
3916	* the pszDesc string will be registered with that LUN and kept around for PDMR3QueryDeviceLun().
3917	*
3918	* @returns VBox status code.
3919	* @param pDevIns The device instance.
3920	* @param iLun The logical unit to attach.
3921	* @param pBaseInterface Pointer to the base interface for that LUN. (device side / down)
3922	* @param ppBaseInterface Where to store the pointer to the base interface. (driver side / up)
3923	* @param pszDesc Pointer to a string describing the LUN. This string must remain valid
3924	* for the live of the device instance.
3925	*/
3926	DECLR3CALLBACKMEMBER(int, pfnDriverAttach,(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface,
3927	PPDMIBASE ppBaseInterface, const char pszDesc));
3928
3929	/**
3930	* Detaches an attached driver (chain) from the device again.
3931	*
3932	* @returns VBox status code.
3933	* @param pDevIns The device instance.
3934	* @param pDrvIns The driver instance to detach.
3935	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3936	*/
3937	DECLR3CALLBACKMEMBER(int, pfnDriverDetach,(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags));
3938
3939	/**
3940	* Reconfigures the driver chain for a LUN, detaching any driver currently
3941	* present there.
3942	*
3943	* Caller will have attach it, of course.
3944	*
3945	* @returns VBox status code.
3946	* @param pDevIns The device instance.
3947	* @param iLun The logical unit to reconfigure.
3948	* @param cDepth The depth of the driver chain. Determins the
3949	* size of @a papszDrivers and @a papConfigs.
3950	* @param papszDrivers The names of the drivers to configure in the
3951	* chain, first entry is the one immediately
3952	* below the device/LUN
3953	* @param papConfigs The configurations for each of the drivers
3954	* in @a papszDrivers array. NULL entries
3955	* corresponds to empty 'Config' nodes. This
3956	* function will take ownership of non-NULL
3957	* CFGM sub-trees and set the array member to
3958	* NULL, so the caller can do cleanups on
3959	* failure. This parameter is optional.
3960	* @param fFlags Reserved, MBZ.
3961	*/
3962	DECLR3CALLBACKMEMBER(int, pfnDriverReconfigure,(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
3963	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags));
3964
3965	/** @name Exported PDM Queue Functions
3966	* @{ */
3967	/**
3968	* Create a queue.
3969	*
3970	* @returns VBox status code.
3971	* @param pDevIns The device instance.
3972	* @param cbItem The size of a queue item.
3973	* @param cItems The number of items in the queue.
3974	* @param cMilliesInterval The number of milliseconds between polling the queue.
3975	* If 0 then the emulation thread will be notified whenever an item arrives.
3976	* @param pfnCallback The consumer function.
3977	* @param fRZEnabled Set if the queue should work in RC and R0.
3978	* @param pszName The queue base name. The instance number will be
3979	* appended automatically.
3980	* @param phQueue Where to store the queue handle on success.
3981	* @thread EMT(0)
3982	* @remarks The device critical section will NOT be entered before calling the
3983	* callback. No locks will be held, but for now it's safe to assume
3984	* that only one EMT will do queue callbacks at any one time.
3985	*/
3986	DECLR3CALLBACKMEMBER(int, pfnQueueCreate,(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
3987	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName,
3988	PDMQUEUEHANDLE *phQueue));
3989
3990	DECLR3CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3991	DECLR3CALLBACKMEMBER(int, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
3992	DECLR3CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
3993	/** @} */
3994
3995	/** @name PDM Task
3996	* @{ */
3997	/**
3998	* Create an asynchronous ring-3 task.
3999	*
4000	* @returns VBox status code.
4001	* @param pDevIns The device instance.
4002	* @param fFlags PDMTASK_F_XXX
4003	* @param pszName The function name or similar. Used for statistics,
4004	* so no slashes.
4005	* @param pfnCallback The task function.
4006	* @param pvUser User argument for the task function.
4007	* @param phTask Where to return the task handle.
4008	* @thread EMT(0)
4009	*/
4010	DECLR3CALLBACKMEMBER(int, pfnTaskCreate,(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
4011	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask));
4012	/**
4013	* Triggers the running the given task.
4014	*
4015	* @returns VBox status code.
4016	* @retval VINF_ALREADY_POSTED is the task is already pending.
4017	* @param pDevIns The device instance.
4018	* @param hTask The task to trigger.
4019	* @thread Any thread.
4020	*/
4021	DECLR3CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
4022	/** @} */
4023
4024	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
4025	* These semaphores can be signalled from ring-0.
4026	* @{ */
4027	/** @sa SUPSemEventCreate */
4028	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent));
4029	/** @sa SUPSemEventClose */
4030	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventClose,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4031	/** @sa SUPSemEventSignal */
4032	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
4033	/** @sa SUPSemEventWaitNoResume */
4034	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
4035	/** @sa SUPSemEventWaitNsAbsIntr */
4036	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
4037	/** @sa SUPSemEventWaitNsRelIntr */
4038	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
4039	/** @sa SUPSemEventGetResolution */
4040	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
4041	/** @} */
4042
4043	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
4044	* These semaphores can be signalled from ring-0.
4045	* @{ */
4046	/** @sa SUPSemEventMultiCreate */
4047	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiCreate,(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti));
4048	/** @sa SUPSemEventMultiClose */
4049	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiClose,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4050	/** @sa SUPSemEventMultiSignal */
4051	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4052	/** @sa SUPSemEventMultiReset */
4053	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
4054	/** @sa SUPSemEventMultiWaitNoResume */
4055	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
4056	/** @sa SUPSemEventMultiWaitNsAbsIntr */
4057	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
4058	/** @sa SUPSemEventMultiWaitNsRelIntr */
4059	DECLR3CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
4060	/** @sa SUPSemEventMultiGetResolution */
4061	DECLR3CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
4062	/** @} */
4063
4064	/**
4065	* Initializes a PDM critical section.
4066	*
4067	* The PDM critical sections are derived from the IPRT critical sections, but
4068	* works in RC and R0 as well.
4069	*
4070	* @returns VBox status code.
4071	* @param pDevIns The device instance.
4072	* @param pCritSect Pointer to the critical section.
4073	* @param SRC_POS Use RT_SRC_POS.
4074	* @param pszNameFmt Format string for naming the critical section.
4075	* For statistics and lock validation.
4076	* @param va Arguments for the format string.
4077	*/
4078	DECLR3CALLBACKMEMBER(int, pfnCritSectInit,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
4079	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4080
4081	/**
4082	* Gets the NOP critical section.
4083	*
4084	* @returns The ring-3 address of the NOP critical section.
4085	* @param pDevIns The device instance.
4086	*/
4087	DECLR3CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
4088
4089	/**
4090	* Changes the device level critical section from the automatically created
4091	* default to one desired by the device constructor.
4092	*
4093	* For ring-0 and raw-mode capable devices, the call must be repeated in each of
4094	* the additional contexts.
4095	*
4096	* @returns VBox status code.
4097	* @param pDevIns The device instance.
4098	* @param pCritSect The critical section to use. NULL is not
4099	* valid, instead use the NOP critical
4100	* section.
4101	*/
4102	DECLR3CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4103
4104	/** @name Exported PDM Critical Section Functions
4105	* @{ */
4106	DECLR3CALLBACKMEMBER(bool, pfnCritSectYield,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4107	DECLR3CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
4108	DECLR3CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4109	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4110	DECLR3CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4111	DECLR3CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4112	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4113	DECLR3CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4114	DECLR3CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4115	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
4116	DECLR3CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
4117	DECLR3CALLBACKMEMBER(int, pfnCritSectDelete,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
4118	/** @} */
4119
4120	/** @name Exported PDM Read/Write Critical Section Functions
4121	* @{ */
4122	DECLR3CALLBACKMEMBER(int, pfnCritSectRwInit,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
4123	const char *pszNameFmt, va_list va) RT_IPRT_FORMAT_ATTR(6, 0));
4124	DECLR3CALLBACKMEMBER(int, pfnCritSectRwDelete,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4125
4126	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4127	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4128	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4129	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4130	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4131
4132	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
4133	DECLR3CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4134	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4135	DECLR3CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
4136	DECLR3CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4137
4138	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4139	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
4140	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4141	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4142	DECLR3CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4143	DECLR3CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
4144	/** @} */
4145
4146	/**
4147	* Creates a PDM thread.
4148	*
4149	* This differs from the RTThreadCreate() API in that PDM takes care of suspending,
4150	* resuming, and destroying the thread as the VM state changes.
4151	*
4152	* @returns VBox status code.
4153	* @param pDevIns The device instance.
4154	* @param ppThread Where to store the thread 'handle'.
4155	* @param pvUser The user argument to the thread function.
4156	* @param pfnThread The thread function.
4157	* @param pfnWakeup The wakup callback. This is called on the EMT
4158	* thread when a state change is pending.
4159	* @param cbStack See RTThreadCreate.
4160	* @param enmType See RTThreadCreate.
4161	* @param pszName See RTThreadCreate.
4162	* @remarks The device critical section will NOT be entered prior to invoking
4163	* the function pointers.
4164	*/
4165	DECLR3CALLBACKMEMBER(int, pfnThreadCreate,(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
4166	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName));
4167
4168	/** @name Exported PDM Thread Functions
4169	* @{ */
4170	DECLR3CALLBACKMEMBER(int, pfnThreadDestroy,(PPDMTHREAD pThread, int *pRcThread));
4171	DECLR3CALLBACKMEMBER(int, pfnThreadIAmSuspending,(PPDMTHREAD pThread));
4172	DECLR3CALLBACKMEMBER(int, pfnThreadIAmRunning,(PPDMTHREAD pThread));
4173	DECLR3CALLBACKMEMBER(int, pfnThreadSleep,(PPDMTHREAD pThread, RTMSINTERVAL cMillies));
4174	DECLR3CALLBACKMEMBER(int, pfnThreadSuspend,(PPDMTHREAD pThread));
4175	DECLR3CALLBACKMEMBER(int, pfnThreadResume,(PPDMTHREAD pThread));
4176	/** @} */
4177
4178	/**
4179	* Set up asynchronous handling of a suspend, reset or power off notification.
4180	*
4181	* This shall only be called when getting the notification. It must be called
4182	* for each one.
4183	*
4184	* @returns VBox status code.
4185	* @param pDevIns The device instance.
4186	* @param pfnAsyncNotify The callback.
4187	* @thread EMT(0)
4188	* @remarks The caller will enter the device critical section prior to invoking
4189	* the callback.
4190	*/
4191	DECLR3CALLBACKMEMBER(int, pfnSetAsyncNotification, (PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify));
4192
4193	/**
4194	* Notify EMT(0) that the device has completed the asynchronous notification
4195	* handling.
4196	*
4197	* This can be called at any time, spurious calls will simply be ignored.
4198	*
4199	* @param pDevIns The device instance.
4200	* @thread Any
4201	*/
4202	DECLR3CALLBACKMEMBER(void, pfnAsyncNotificationCompleted, (PPDMDEVINS pDevIns));
4203
4204	/**
4205	* Register the RTC device.
4206	*
4207	* @returns VBox status code.
4208	* @param pDevIns The device instance.
4209	* @param pRtcReg Pointer to a RTC registration structure.
4210	* @param ppRtcHlp Where to store the pointer to the helper
4211	* functions.
4212	*/
4213	DECLR3CALLBACKMEMBER(int, pfnRTCRegister,(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp));
4214
4215	/**
4216	* Register a PCI Bus.
4217	*
4218	* @returns VBox status code, but the positive values 0..31 are used to indicate
4219	* bus number rather than informational status codes.
4220	* @param pDevIns The device instance.
4221	* @param pPciBusReg Pointer to PCI bus registration structure.
4222	* @param ppPciHlp Where to store the pointer to the PCI Bus
4223	* helpers.
4224	* @param piBus Where to return the PDM bus number. Optional.
4225	*/
4226	DECLR3CALLBACKMEMBER(int, pfnPCIBusRegister,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg,
4227	PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus));
4228
4229	/**
4230	* Register the IOMMU device.
4231	*
4232	* @returns VBox status code.
4233	* @param pDevIns The device instance.
4234	* @param pIommuReg Pointer to a IOMMU registration structure.
4235	* @param ppIommuHlp Where to store the pointer to the ring-3 IOMMU
4236	* helpers.
4237	* @param pidxIommu Where to return the IOMMU index. Optional.
4238	*/
4239	DECLR3CALLBACKMEMBER(int, pfnIommuRegister,(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 *ppIommuHlp,
4240	uint32_t *pidxIommu));
4241
4242	/**
4243	* Register the PIC device.
4244	*
4245	* @returns VBox status code.
4246	* @param pDevIns The device instance.
4247	* @param pPicReg Pointer to a PIC registration structure.
4248	* @param ppPicHlp Where to store the pointer to the ring-3 PIC
4249	* helpers.
4250	* @sa PDMDevHlpPICSetUpContext
4251	*/
4252	DECLR3CALLBACKMEMBER(int, pfnPICRegister,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
4253
4254	/**
4255	* Register the APIC device.
4256	*
4257	* @returns VBox status code.
4258	* @param pDevIns The device instance.
4259	*/
4260	DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
4261
4262	/**
4263	* Register the I/O APIC device.
4264	*
4265	* @returns VBox status code.
4266	* @param pDevIns The device instance.
4267	* @param pIoApicReg Pointer to a I/O APIC registration structure.
4268	* @param ppIoApicHlp Where to store the pointer to the IOAPIC
4269	* helpers.
4270	*/
4271	DECLR3CALLBACKMEMBER(int, pfnIoApicRegister,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
4272
4273	/**
4274	* Register the HPET device.
4275	*
4276	* @returns VBox status code.
4277	* @param pDevIns The device instance.
4278	* @param pHpetReg Pointer to a HPET registration structure.
4279	* @param ppHpetHlpR3 Where to store the pointer to the HPET
4280	* helpers.
4281	*/
4282	DECLR3CALLBACKMEMBER(int, pfnHpetRegister,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3));
4283
4284	/**
4285	* Register a raw PCI device.
4286	*
4287	* @returns VBox status code.
4288	* @param pDevIns The device instance.
4289	* @param pPciRawReg Pointer to a raw PCI registration structure.
4290	* @param ppPciRawHlpR3 Where to store the pointer to the raw PCI
4291	* device helpers.
4292	*/
4293	DECLR3CALLBACKMEMBER(int, pfnPciRawRegister,(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3));
4294
4295	/**
4296	* Register the DMA device.
4297	*
4298	* @returns VBox status code.
4299	* @param pDevIns The device instance.
4300	* @param pDmacReg Pointer to a DMAC registration structure.
4301	* @param ppDmacHlp Where to store the pointer to the DMA helpers.
4302	*/
4303	DECLR3CALLBACKMEMBER(int, pfnDMACRegister,(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp));
4304
4305	/**
4306	* Register transfer function for DMA channel.
4307	*
4308	* @returns VBox status code.
4309	* @param pDevIns The device instance.
4310	* @param uChannel Channel number.
4311	* @param pfnTransferHandler Device specific transfer callback function.
4312	* @param pvUser User pointer to pass to the callback.
4313	* @thread EMT
4314	*/
4315	DECLR3CALLBACKMEMBER(int, pfnDMARegister,(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser));
4316
4317	/**
4318	* Read memory.
4319	*
4320	* @returns VBox status code.
4321	* @param pDevIns The device instance.
4322	* @param uChannel Channel number.
4323	* @param pvBuffer Pointer to target buffer.
4324	* @param off DMA position.
4325	* @param cbBlock Block size.
4326	* @param pcbRead Where to store the number of bytes which was
4327	* read. optional.
4328	* @thread EMT
4329	*/
4330	DECLR3CALLBACKMEMBER(int, pfnDMAReadMemory,(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead));
4331
4332	/**
4333	* Write memory.
4334	*
4335	* @returns VBox status code.
4336	* @param pDevIns The device instance.
4337	* @param uChannel Channel number.
4338	* @param pvBuffer Memory to write.
4339	* @param off DMA position.
4340	* @param cbBlock Block size.
4341	* @param pcbWritten Where to store the number of bytes which was
4342	* written. optional.
4343	* @thread EMT
4344	*/
4345	DECLR3CALLBACKMEMBER(int, pfnDMAWriteMemory,(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten));
4346
4347	/**
4348	* Set the DREQ line.
4349	*
4350	* @returns VBox status code.
4351	* @param pDevIns Device instance.
4352	* @param uChannel Channel number.
4353	* @param uLevel Level of the line.
4354	* @thread EMT
4355	*/
4356	DECLR3CALLBACKMEMBER(int, pfnDMASetDREQ,(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel));
4357
4358	/**
4359	* Get channel mode.
4360	*
4361	* @returns Channel mode. See specs.
4362	* @param pDevIns The device instance.
4363	* @param uChannel Channel number.
4364	* @thread EMT
4365	*/
4366	DECLR3CALLBACKMEMBER(uint8_t, pfnDMAGetChannelMode,(PPDMDEVINS pDevIns, unsigned uChannel));
4367
4368	/**
4369	* Schedule DMA execution.
4370	*
4371	* @param pDevIns The device instance.
4372	* @thread Any thread.
4373	*/
4374	DECLR3CALLBACKMEMBER(void, pfnDMASchedule,(PPDMDEVINS pDevIns));
4375
4376	/**
4377	* Write CMOS value and update the checksum(s).
4378	*
4379	* @returns VBox status code.
4380	* @param pDevIns The device instance.
4381	* @param iReg The CMOS register index.
4382	* @param u8Value The CMOS register value.
4383	* @thread EMT
4384	*/
4385	DECLR3CALLBACKMEMBER(int, pfnCMOSWrite,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value));
4386
4387	/**
4388	* Read CMOS value.
4389	*
4390	* @returns VBox status code.
4391	* @param pDevIns The device instance.
4392	* @param iReg The CMOS register index.
4393	* @param pu8Value Where to store the CMOS register value.
4394	* @thread EMT
4395	*/
4396	DECLR3CALLBACKMEMBER(int, pfnCMOSRead,(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value));
4397
4398	/**
4399	* Assert that the current thread is the emulation thread.
4400	*
4401	* @returns True if correct.
4402	* @returns False if wrong.
4403	* @param pDevIns The device instance.
4404	* @param pszFile Filename of the assertion location.
4405	* @param iLine The linenumber of the assertion location.
4406	* @param pszFunction Function of the assertion location.
4407	*/
4408	DECLR3CALLBACKMEMBER(bool, pfnAssertEMT,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4409
4410	/**
4411	* Assert that the current thread is NOT the emulation thread.
4412	*
4413	* @returns True if correct.
4414	* @returns False if wrong.
4415	* @param pDevIns The device instance.
4416	* @param pszFile Filename of the assertion location.
4417	* @param iLine The linenumber of the assertion location.
4418	* @param pszFunction Function of the assertion location.
4419	*/
4420	DECLR3CALLBACKMEMBER(bool, pfnAssertOther,(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction));
4421
4422	/**
4423	* Resolves the symbol for a raw-mode context interface.
4424	*
4425	* @returns VBox status code.
4426	* @param pDevIns The device instance.
4427	* @param pvInterface The interface structure.
4428	* @param cbInterface The size of the interface structure.
4429	* @param pszSymPrefix What to prefix the symbols in the list with
4430	* before resolving them. This must start with
4431	* 'dev' and contain the driver name.
4432	* @param pszSymList List of symbols corresponding to the interface.
4433	* There is generally a there is generally a define
4434	* holding this list associated with the interface
4435	* definition (INTERFACE_SYM_LIST). For more
4436	* details see PDMR3LdrGetInterfaceSymbols.
4437	* @thread EMT
4438	*/
4439	DECLR3CALLBACKMEMBER(int, pfnLdrGetRCInterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4440	const char pszSymPrefix, const char pszSymList));
4441
4442	/**
4443	* Resolves the symbol for a ring-0 context interface.
4444	*
4445	* @returns VBox status code.
4446	* @param pDevIns The device instance.
4447	* @param pvInterface The interface structure.
4448	* @param cbInterface The size of the interface structure.
4449	* @param pszSymPrefix What to prefix the symbols in the list with
4450	* before resolving them. This must start with
4451	* 'dev' and contain the driver name.
4452	* @param pszSymList List of symbols corresponding to the interface.
4453	* There is generally a there is generally a define
4454	* holding this list associated with the interface
4455	* definition (INTERFACE_SYM_LIST). For more
4456	* details see PDMR3LdrGetInterfaceSymbols.
4457	* @thread EMT
4458	*/
4459	DECLR3CALLBACKMEMBER(int, pfnLdrGetR0InterfaceSymbols,(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
4460	const char pszSymPrefix, const char pszSymList));
4461
4462	/**
4463	* Calls the PDMDEVREGR0::pfnRequest callback (in ring-0 context).
4464	*
4465	* @returns VBox status code.
4466	* @retval VERR_INVALID_FUNCTION if the callback member is NULL.
4467	* @retval VERR_ACCESS_DENIED if the device isn't ring-0 capable.
4468	*
4469	* @param pDevIns The device instance.
4470	* @param uOperation The operation to perform.
4471	* @param u64Arg 64-bit integer argument.
4472	* @thread EMT
4473	*/
4474	DECLR3CALLBACKMEMBER(int, pfnCallR0,(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg));
4475
4476	/**
4477	* Gets the reason for the most recent VM suspend.
4478	*
4479	* @returns The suspend reason. VMSUSPENDREASON_INVALID is returned if no
4480	* suspend has been made or if the pDevIns is invalid.
4481	* @param pDevIns The device instance.
4482	*/
4483	DECLR3CALLBACKMEMBER(VMSUSPENDREASON, pfnVMGetSuspendReason,(PPDMDEVINS pDevIns));
4484
4485	/**
4486	* Gets the reason for the most recent VM resume.
4487	*
4488	* @returns The resume reason. VMRESUMEREASON_INVALID is returned if no
4489	* resume has been made or if the pDevIns is invalid.
4490	* @param pDevIns The device instance.
4491	*/
4492	DECLR3CALLBACKMEMBER(VMRESUMEREASON, pfnVMGetResumeReason,(PPDMDEVINS pDevIns));
4493
4494	/**
4495	* Requests the mapping of multiple guest page into ring-3.
4496	*
4497	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4498	* ASAP to release them.
4499	*
4500	* This API will assume your intention is to write to the pages, and will
4501	* therefore replace shared and zero pages. If you do not intend to modify the
4502	* pages, use the pfnPhysBulkGCPhys2CCPtrReadOnly() API.
4503	*
4504	* @returns VBox status code.
4505	* @retval VINF_SUCCESS on success.
4506	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4507	* backing or if any of the pages the page has any active access
4508	* handlers. The caller must fall back on using PGMR3PhysWriteExternal.
4509	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4510	* an invalid physical address.
4511	*
4512	* @param pDevIns The device instance.
4513	* @param cPages Number of pages to lock.
4514	* @param paGCPhysPages The guest physical address of the pages that
4515	* should be mapped (@a cPages entries).
4516	* @param fFlags Flags reserved for future use, MBZ.
4517	* @param papvPages Where to store the ring-3 mapping addresses
4518	* corresponding to @a paGCPhysPages.
4519	* @param paLocks Where to store the locking information that
4520	* pfnPhysBulkReleasePageMappingLock needs (@a cPages
4521	* in length).
4522	*
4523	* @remark Avoid calling this API from within critical sections (other than the
4524	* PGM one) because of the deadlock risk when we have to delegating the
4525	* task to an EMT.
4526	* @thread Any.
4527	* @since 6.0.6
4528	*/
4529	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtr,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4530	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks));
4531
4532	/**
4533	* Requests the mapping of multiple guest page into ring-3, for reading only.
4534	*
4535	* When you're done with the pages, call pfnPhysBulkReleasePageMappingLocks()
4536	* ASAP to release them.
4537	*
4538	* @returns VBox status code.
4539	* @retval VINF_SUCCESS on success.
4540	* @retval VERR_PGM_PHYS_PAGE_RESERVED if any of the pages has no physical
4541	* backing or if any of the pages the page has an active ALL access
4542	* handler. The caller must fall back on using PGMR3PhysWriteExternal.
4543	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if @a paGCPhysPages contains
4544	* an invalid physical address.
4545	*
4546	* @param pDevIns The device instance.
4547	* @param cPages Number of pages to lock.
4548	* @param paGCPhysPages The guest physical address of the pages that
4549	* should be mapped (@a cPages entries).
4550	* @param fFlags Flags reserved for future use, MBZ.
4551	* @param papvPages Where to store the ring-3 mapping addresses
4552	* corresponding to @a paGCPhysPages.
4553	* @param paLocks Where to store the lock information that
4554	* pfnPhysReleasePageMappingLock needs (@a cPages
4555	* in length).
4556	*
4557	* @remark Avoid calling this API from within critical sections.
4558	* @thread Any.
4559	* @since 6.0.6
4560	*/
4561	DECLR3CALLBACKMEMBER(int, pfnPhysBulkGCPhys2CCPtrReadOnly,(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
4562	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks));
4563
4564	/**
4565	* Release the mappings of multiple guest pages.
4566	*
4567	* This is the counter part of pfnPhysBulkGCPhys2CCPtr and
4568	* pfnPhysBulkGCPhys2CCPtrReadOnly.
4569	*
4570	* @param pDevIns The device instance.
4571	* @param cPages Number of pages to unlock.
4572	* @param paLocks The lock structures initialized by the mapping
4573	* function (@a cPages in length).
4574	* @thread Any.
4575	* @since 6.0.6
4576	*/
4577	DECLR3CALLBACKMEMBER(void, pfnPhysBulkReleasePageMappingLocks,(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks));
4578
4579	/**
4580	* Returns the architecture used for the guest.
4581	*
4582	* @returns CPU architecture enum.
4583	* @param pDevIns The device instance.
4584	*/
4585	DECLR3CALLBACKMEMBER(CPUMARCH, pfnCpuGetGuestArch,(PPDMDEVINS pDevIns));
4586
4587	/**
4588	* Returns the micro architecture used for the guest.
4589	*
4590	* @returns CPU micro architecture enum.
4591	* @param pDevIns The device instance.
4592	*/
4593	DECLR3CALLBACKMEMBER(CPUMMICROARCH, pfnCpuGetGuestMicroarch,(PPDMDEVINS pDevIns));
4594
4595	/**
4596	* Get the number of physical and linear address bits supported by the guest.
4597	*
4598	* @param pDevIns The device instance.
4599	* @param pcPhysAddrWidth Where to store the number of physical address bits
4600	* supported by the guest.
4601	* @param pcLinearAddrWidth Where to store the number of linear address bits
4602	* supported by the guest.
4603	*/
4604	DECLR3CALLBACKMEMBER(void, pfnCpuGetGuestAddrWidths,(PPDMDEVINS pDevIns, uint8_t *pcPhysAddrWidth,
4605	uint8_t *pcLinearAddrWidth));
4606
4607	/**
4608	* Gets the scalable bus frequency.
4609	*
4610	* The bus frequency is used as a base in several MSRs that gives the CPU and
4611	* other frequency ratios.
4612	*
4613	* @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
4614	* @param pDevIns The device instance.
4615	*/
4616	DECLR3CALLBACKMEMBER(uint64_t, pfnCpuGetGuestScalableBusFrequency,(PPDMDEVINS pDevIns));
4617
4618	/** Space reserved for future members.
4619	* @{ */
4620	/**
4621	* Deregister zero or more samples given their name prefix.
4622	*
4623	* @returns VBox status code.
4624	* @param pDevIns The device instance.
4625	* @param pszPrefix The name prefix of the samples to remove. If this does
4626	* not start with a '/', the default prefix will be
4627	* prepended, otherwise it will be used as-is.
4628	*/
4629	DECLR3CALLBACKMEMBER(int, pfnSTAMDeregisterByPrefix,(PPDMDEVINS pDevIns, const char *pszPrefix));
4630	DECLR3CALLBACKMEMBER(void, pfnReserved2,(void));
4631	DECLR3CALLBACKMEMBER(void, pfnReserved3,(void));
4632	DECLR3CALLBACKMEMBER(void, pfnReserved4,(void));
4633	DECLR3CALLBACKMEMBER(void, pfnReserved5,(void));
4634	DECLR3CALLBACKMEMBER(void, pfnReserved6,(void));
4635	DECLR3CALLBACKMEMBER(void, pfnReserved7,(void));
4636	DECLR3CALLBACKMEMBER(void, pfnReserved8,(void));
4637	DECLR3CALLBACKMEMBER(void, pfnReserved9,(void));
4638	DECLR3CALLBACKMEMBER(void, pfnReserved10,(void));
4639	/** @} */
4640
4641
4642	/** API available to trusted devices only.
4643	*
4644	* These APIs are providing unrestricted access to the guest and the VM,
4645	* or they are interacting intimately with PDM.
4646	*
4647	* @{
4648	*/
4649
4650	/**
4651	* Gets the user mode VM handle. Restricted API.
4652	*
4653	* @returns User mode VM Handle.
4654	* @param pDevIns The device instance.
4655	*/
4656	DECLR3CALLBACKMEMBER(PUVM, pfnGetUVM,(PPDMDEVINS pDevIns));
4657
4658	/**
4659	* Gets the global VM handle. Restricted API.
4660	*
4661	* @returns VM Handle.
4662	* @param pDevIns The device instance.
4663	*/
4664	DECLR3CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
4665
4666	/**
4667	* Gets the VMCPU handle. Restricted API.
4668	*
4669	* @returns VMCPU Handle.
4670	* @param pDevIns The device instance.
4671	*/
4672	DECLR3CALLBACKMEMBER(PVMCPU, pfnGetVMCPU,(PPDMDEVINS pDevIns));
4673
4674	/**
4675	* The the VM CPU ID of the current thread (restricted API).
4676	*
4677	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
4678	* @param pDevIns The device instance.
4679	*/
4680	DECLR3CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
4681
4682	/**
4683	* Registers the VMM device heap or notifies about mapping/unmapping.
4684	*
4685	* This interface serves three purposes:
4686	*
4687	* -# Register the VMM device heap during device construction
4688	* for the HM to use.
4689	* -# Notify PDM/HM that it's mapped into guest address
4690	* space (i.e. usable).
4691	* -# Notify PDM/HM that it is being unmapped from the guest
4692	* address space (i.e. not usable).
4693	*
4694	* @returns VBox status code.
4695	* @param pDevIns The device instance.
4696	* @param GCPhys The physical address if mapped, NIL_RTGCPHYS if
4697	* not mapped.
4698	* @param pvHeap Ring 3 heap pointer.
4699	* @param cbHeap Size of the heap.
4700	* @thread EMT.
4701	*/
4702	DECLR3CALLBACKMEMBER(int, pfnRegisterVMMDevHeap,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap));
4703
4704	/**
4705	* Registers the firmware (BIOS, EFI) device with PDM.
4706	*
4707	* The firmware provides a callback table and gets a special PDM helper table.
4708	* There can only be one firmware device for a VM.
4709	*
4710	* @returns VBox status code.
4711	* @param pDevIns The device instance.
4712	* @param pFwReg Firmware registration structure.
4713	* @param ppFwHlp Where to return the firmware helper structure.
4714	* @remarks Only valid during device construction.
4715	* @thread EMT(0)
4716	*/
4717	DECLR3CALLBACKMEMBER(int, pfnFirmwareRegister,(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp));
4718
4719	/**
4720	* Resets the VM.
4721	*
4722	* @returns The appropriate VBox status code to pass around on reset.
4723	* @param pDevIns The device instance.
4724	* @param fFlags PDMVMRESET_F_XXX flags.
4725	* @thread The emulation thread.
4726	*/
4727	DECLR3CALLBACKMEMBER(int, pfnVMReset,(PPDMDEVINS pDevIns, uint32_t fFlags));
4728
4729	/**
4730	* Suspends the VM.
4731	*
4732	* @returns The appropriate VBox status code to pass around on suspend.
4733	* @param pDevIns The device instance.
4734	* @thread The emulation thread.
4735	*/
4736	DECLR3CALLBACKMEMBER(int, pfnVMSuspend,(PPDMDEVINS pDevIns));
4737
4738	/**
4739	* Suspends, saves and powers off the VM.
4740	*
4741	* @returns The appropriate VBox status code to pass around.
4742	* @param pDevIns The device instance.
4743	* @thread An emulation thread.
4744	*/
4745	DECLR3CALLBACKMEMBER(int, pfnVMSuspendSaveAndPowerOff,(PPDMDEVINS pDevIns));
4746
4747	/**
4748	* Power off the VM.
4749	*
4750	* @returns The appropriate VBox status code to pass around on power off.
4751	* @param pDevIns The device instance.
4752	* @thread The emulation thread.
4753	*/
4754	DECLR3CALLBACKMEMBER(int, pfnVMPowerOff,(PPDMDEVINS pDevIns));
4755
4756	/**
4757	* Checks if the Gate A20 is enabled or not.
4758	*
4759	* @returns true if A20 is enabled.
4760	* @returns false if A20 is disabled.
4761	* @param pDevIns The device instance.
4762	* @thread The emulation thread.
4763	*/
4764	DECLR3CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
4765
4766	/**
4767	* Enables or disables the Gate A20.
4768	*
4769	* @param pDevIns The device instance.
4770	* @param fEnable Set this flag to enable the Gate A20; clear it
4771	* to disable.
4772	* @thread The emulation thread.
4773	*/
4774	DECLR3CALLBACKMEMBER(void, pfnA20Set,(PPDMDEVINS pDevIns, bool fEnable));
4775
4776	/**
4777	* Get the specified CPUID leaf for the virtual CPU associated with the calling
4778	* thread.
4779	*
4780	* @param pDevIns The device instance.
4781	* @param iLeaf The CPUID leaf to get.
4782	* @param pEax Where to store the EAX value.
4783	* @param pEbx Where to store the EBX value.
4784	* @param pEcx Where to store the ECX value.
4785	* @param pEdx Where to store the EDX value.
4786	* @thread EMT.
4787	*/
4788	DECLR3CALLBACKMEMBER(void, pfnGetCpuId,(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx));
4789
4790	/**
4791	* Gets the main execution engine for the VM.
4792	*
4793	* @returns VM_EXEC_ENGINE_XXX
4794	* @param pDevIns The device instance.
4795	*/
4796	DECLR3CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
4797
4798	/**
4799	* Get the current virtual clock time in a VM. The clock frequency must be
4800	* queried separately.
4801	*
4802	* @returns Current clock time.
4803	* @param pDevIns The device instance.
4804	*/
4805	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
4806
4807	/**
4808	* Get the frequency of the virtual clock.
4809	*
4810	* @returns The clock frequency (not variable at run-time).
4811	* @param pDevIns The device instance.
4812	*/
4813	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
4814
4815	/**
4816	* Get the current virtual clock time in a VM, in nanoseconds.
4817	*
4818	* @returns Current clock time (in ns).
4819	* @param pDevIns The device instance.
4820	*/
4821	DECLR3CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
4822
4823	/**
4824	* Get the timestamp frequency.
4825	*
4826	* @returns Number of ticks per second.
4827	* @param pDevIns The device instance.
4828	*/
4829	DECLR3CALLBACKMEMBER(uint64_t, pfnTMCpuTicksPerSecond,(PPDMDEVINS pDevIns));
4830
4831	/**
4832	* Gets the support driver session.
4833	*
4834	* This is intended for working with the semaphore API.
4835	*
4836	* @returns Support driver session handle.
4837	* @param pDevIns The device instance.
4838	*/
4839	DECLR3CALLBACKMEMBER(PSUPDRVSESSION, pfnGetSupDrvSession,(PPDMDEVINS pDevIns));
4840
4841	/**
4842	* Queries a generic object from the VMM user.
4843	*
4844	* @returns Pointer to the object if found, NULL if not.
4845	* @param pDevIns The device instance.
4846	* @param pUuid The UUID of what's being queried. The UUIDs and
4847	* the usage conventions are defined by the user.
4848	*
4849	* @note It is strictly forbidden to call this internally in VBox! This
4850	* interface is exclusively for hacks in externally developed devices.
4851	*/
4852	DECLR3CALLBACKMEMBER(void *, pfnQueryGenericUserObject,(PPDMDEVINS pDevIns, PCRTUUID pUuid));
4853
4854	/**
4855	* Register a physical page access handler type.
4856	*
4857	* @returns VBox status code.
4858	* @param pDevIns The device instance.
4859	* @param enmKind The kind of access handler.
4860	* @param pfnHandler Pointer to the ring-3 handler callback.
4861	* @param pszDesc The type description.
4862	* @param phType Where to return the type handle (cross context safe).
4863	* @sa PDMDevHlpPGMHandlerPhysicalTypeSetUpContext
4864	*/
4865	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeRegister, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
4866	PFNPGMPHYSHANDLER pfnHandler,
4867	const char *pszDesc, PPGMPHYSHANDLERTYPE phType));
4868
4869	/**
4870	* Register a access handler for a physical range.
4871	*
4872	* @returns VBox status code.
4873	* @retval VINF_SUCCESS when successfully installed.
4874	* @retval VINF_PGM_GCPHYS_ALIASED when the shadow PTs could be updated because
4875	* the guest page aliased or/and mapped by multiple PTs. A CR3 sync has been
4876	* flagged together with a pool clearing.
4877	* @retval VERR_PGM_HANDLER_PHYSICAL_CONFLICT if the range conflicts with an existing
4878	* one. A debug assertion is raised.
4879	*
4880	* @param pDevIns The device instance.
4881	* @param GCPhys Start physical address.
4882	* @param GCPhysLast Last physical address. (inclusive)
4883	* @param hType The handler type registration handle.
4884	* @param pszDesc Description of this handler. If NULL, the type
4885	* description will be used instead.
4886	* @note There is no @a uUser argument, because it will be set to the pDevIns
4887	* in the context the handler is called.
4888	*/
4889	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalRegister, (PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
4890	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc));
4891
4892	/**
4893	* Deregister a physical page access handler.
4894	*
4895	* @returns VBox status code.
4896	* @param pDevIns The device instance.
4897	* @param GCPhys Start physical address.
4898	*/
4899	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalDeregister,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4900
4901	/**
4902	* Temporarily turns off the access monitoring of a page within a monitored
4903	* physical write/all page access handler region.
4904	*
4905	* Use this when no further \#PFs are required for that page. Be aware that
4906	* a page directory sync might reset the flags, and turn on access monitoring
4907	* for the page.
4908	*
4909	* The caller must do required page table modifications.
4910	*
4911	* @returns VBox status code.
4912	* @param pDevIns The device instance.
4913	* @param GCPhys The start address of the access handler. This
4914	* must be a fully page aligned range or we risk
4915	* messing up other handlers installed for the
4916	* start and end pages.
4917	* @param GCPhysPage The physical address of the page to turn off
4918	* access monitoring for.
4919	*/
4920	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
4921
4922	/**
4923	* Resets any modifications to individual pages in a physical page access
4924	* handler region.
4925	*
4926	* This is used in pair with PGMHandlerPhysicalPageTempOff(),
4927	* PGMHandlerPhysicalPageAliasMmio2() or PGMHandlerPhysicalPageAliasHC().
4928	*
4929	* @returns VBox status code.
4930	* @param pDevIns The device instance.
4931	* @param GCPhys The start address of the handler regions, i.e. what you
4932	* passed to PGMR3HandlerPhysicalRegister(),
4933	* PGMHandlerPhysicalRegisterEx() or
4934	* PGMHandlerPhysicalModify().
4935	*/
4936	DECLR3CALLBACKMEMBER(int, pfnPGMHandlerPhysicalReset,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys));
4937
4938	/**
4939	* Registers the guest memory range that can be used for patching.
4940	*
4941	* @returns VBox status code.
4942	* @param pDevIns The device instance.
4943	* @param GCPtrPatchMem Patch memory range.
4944	* @param cbPatchMem Size of the memory range.
4945	*/
4946	DECLR3CALLBACKMEMBER(int, pfnVMMRegisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4947
4948	/**
4949	* Deregisters the guest memory range that can be used for patching.
4950	*
4951	* @returns VBox status code.
4952	* @param pDevIns The device instance.
4953	* @param GCPtrPatchMem Patch memory range.
4954	* @param cbPatchMem Size of the memory range.
4955	*/
4956	DECLR3CALLBACKMEMBER(int, pfnVMMDeregisterPatchMemory, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem));
4957
4958	/**
4959	* Registers a new shared module for the VM
4960	*
4961	* @returns VBox status code.
4962	* @param pDevIns The device instance.
4963	* @param enmGuestOS Guest OS type.
4964	* @param pszModuleName Module name.
4965	* @param pszVersion Module version.
4966	* @param GCBaseAddr Module base address.
4967	* @param cbModule Module size.
4968	* @param cRegions Number of shared region descriptors.
4969	* @param paRegions Shared region(s).
4970	*/
4971	DECLR3CALLBACKMEMBER(int, pfnSharedModuleRegister,(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
4972	RTGCPTR GCBaseAddr, uint32_t cbModule,
4973	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions));
4974
4975	/**
4976	* Unregisters a shared module for the VM
4977	*
4978	* @returns VBox status code.
4979	* @param pDevIns The device instance.
4980	* @param pszModuleName Module name.
4981	* @param pszVersion Module version.
4982	* @param GCBaseAddr Module base address.
4983	* @param cbModule Module size.
4984	*/
4985	DECLR3CALLBACKMEMBER(int, pfnSharedModuleUnregister,(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
4986	RTGCPTR GCBaseAddr, uint32_t cbModule));
4987
4988	/**
4989	* Query the state of a page in a shared module
4990	*
4991	* @returns VBox status code.
4992	* @param pDevIns The device instance.
4993	* @param GCPtrPage Page address.
4994	* @param pfShared Shared status (out).
4995	* @param pfPageFlags Page flags (out).
4996	*/
4997	DECLR3CALLBACKMEMBER(int, pfnSharedModuleGetPageState, (PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags));
4998
4999	/**
5000	* Check all registered modules for changes.
5001	*
5002	* @returns VBox status code.
5003	* @param pDevIns The device instance.
5004	*/
5005	DECLR3CALLBACKMEMBER(int, pfnSharedModuleCheckAll,(PPDMDEVINS pDevIns));
5006
5007	/**
5008	* Query the interface of the top level driver on a LUN.
5009	*
5010	* @returns VBox status code.
5011	* @param pDevIns The device instance.
5012	* @param pszDevice Device name.
5013	* @param iInstance Device instance.
5014	* @param iLun The Logical Unit to obtain the interface of.
5015	* @param ppBase Where to store the base interface pointer.
5016	*
5017	* @remark We're not doing any locking ATM, so don't try call this at times when the
5018	* device chain is known to be updated.
5019	*/
5020	DECLR3CALLBACKMEMBER(int, pfnQueryLun,(PPDMDEVINS pDevIns, const char *pszDevice, unsigned iInstance, unsigned iLun, PPPDMIBASE ppBase));
5021
5022	/**
5023	* Registers the GIM device with VMM.
5024	*
5025	* @param pDevIns Pointer to the GIM device instance.
5026	* @param pDbg Pointer to the GIM device debug structure, can be
5027	* NULL.
5028	*/
5029	DECLR3CALLBACKMEMBER(void, pfnGIMDeviceRegister,(PPDMDEVINS pDevIns, PGIMDEBUG pDbg));
5030
5031	/**
5032	* Gets debug setup specified by the provider.
5033	*
5034	* @returns VBox status code.
5035	* @param pDevIns Pointer to the GIM device instance.
5036	* @param pDbgSetup Where to store the debug setup details.
5037	*/
5038	DECLR3CALLBACKMEMBER(int, pfnGIMGetDebugSetup,(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup));
5039
5040	/**
5041	* Returns the array of MMIO2 regions that are expected to be registered and
5042	* later mapped into the guest-physical address space for the GIM provider
5043	* configured for the VM.
5044	*
5045	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
5046	* @param pDevIns Pointer to the GIM device instance.
5047	* @param pcRegions Where to store the number of items in the array.
5048	*
5049	* @remarks The caller does not own and therefore must -NOT- try to free the
5050	* returned pointer.
5051	*/
5052	DECLR3CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
5053
5054	/** @} */
5055
5056	/** Just a safety precaution. (PDM_DEVHLPR3_VERSION) */
5057	uint32_t u32TheEnd;
5058	} PDMDEVHLPR3;
5059	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
5060	/** Pointer to the R3 PDM Device API. */
5061	typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3;
5062	/** Pointer to the R3 PDM Device API, const variant. */
5063	typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3;
5064
5065
5066	/**
5067	* PDM Device API - RC Variant.
5068	*/
5069	typedef struct PDMDEVHLPRC
5070	{
5071	/** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */
5072	uint32_t u32Version;
5073
5074	/**
5075	* Sets up raw-mode context callback handlers for an I/O port range.
5076	*
5077	* The range must have been registered in ring-3 first using
5078	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5079	*
5080	* @returns VBox status.
5081	* @param pDevIns The device instance to register the ports with.
5082	* @param hIoPorts The I/O port range handle.
5083	* @param pfnOut Pointer to function which is gonna handle OUT
5084	* operations. Optional.
5085	* @param pfnIn Pointer to function which is gonna handle IN operations.
5086	* Optional.
5087	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5088	* operations. Optional.
5089	* @param pfnInStr Pointer to function which is gonna handle string IN
5090	* operations. Optional.
5091	* @param pvUser User argument to pass to the callbacks.
5092	*
5093	* @remarks Caller enters the device critical section prior to invoking the
5094	* registered callback methods.
5095	*
5096	* @sa PDMDevHlpIoPortCreate, PDMDevHlpIoPortCreateEx, PDMDevHlpIoPortMap,
5097	* PDMDevHlpIoPortUnmap.
5098	*/
5099	DECLRCCALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5100	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5101	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5102	void *pvUser));
5103
5104	/**
5105	* Sets up raw-mode context callback handlers for an MMIO region.
5106	*
5107	* The region must have been registered in ring-3 first using
5108	* PDMDevHlpMmioCreate() or PDMDevHlpMmioCreateEx().
5109	*
5110	* @returns VBox status.
5111	* @param pDevIns The device instance to register the ports with.
5112	* @param hRegion The MMIO region handle.
5113	* @param pfnWrite Pointer to function which is gonna handle Write
5114	* operations.
5115	* @param pfnRead Pointer to function which is gonna handle Read
5116	* operations.
5117	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5118	* operations. (optional)
5119	* @param pvUser User argument to pass to the callbacks.
5120	*
5121	* @remarks Caller enters the device critical section prior to invoking the
5122	* registered callback methods.
5123	*
5124	* @sa PDMDevHlpMmioCreate, PDMDevHlpMmioCreateEx, PDMDevHlpMmioMap,
5125	* PDMDevHlpMmioUnmap.
5126	*/
5127	DECLRCCALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5128	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5129
5130	/**
5131	* Sets up a raw-mode mapping for an MMIO2 region.
5132	*
5133	* The region must have been created in ring-3 first using
5134	* PDMDevHlpMmio2Create().
5135	*
5136	* @returns VBox status.
5137	* @param pDevIns The device instance to register the ports with.
5138	* @param hRegion The MMIO2 region handle.
5139	* @param offSub Start of what to map into raw-mode. Must be page aligned.
5140	* @param cbSub Number of bytes to map into raw-mode. Must be page
5141	* aligned. Zero is an alias for everything.
5142	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5143	* @thread EMT(0)
5144	* @note Only available at VM creation time.
5145	*
5146	* @sa PDMDevHlpMmio2Create().
5147	*/
5148	DECLRCCALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
5149	size_t offSub, size_t cbSub, void **ppvMapping));
5150
5151	/**
5152	* Bus master physical memory read from the given PCI device.
5153	*
5154	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
5155	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5156	* @param pDevIns The device instance.
5157	* @param pPciDev The PCI device structure. If NULL the default
5158	* PCI device for this device instance is used.
5159	* @param GCPhys Physical address start reading from.
5160	* @param pvBuf Where to put the read bits.
5161	* @param cbRead How many bytes to read.
5162	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5163	* @thread Any thread, but the call may involve the emulation thread.
5164	*/
5165	DECLRCCALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5166	void *pvBuf, size_t cbRead, uint32_t fFlags));
5167
5168	/**
5169	* Bus master physical memory write from the given PCI device.
5170	*
5171	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
5172	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
5173	* @param pDevIns The device instance.
5174	* @param pPciDev The PCI device structure. If NULL the default
5175	* PCI device for this device instance is used.
5176	* @param GCPhys Physical address to write to.
5177	* @param pvBuf What to write.
5178	* @param cbWrite How many bytes to write.
5179	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5180	* @thread Any thread, but the call may involve the emulation thread.
5181	*/
5182	DECLRCCALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5183	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5184
5185	/**
5186	* Set the IRQ for the given PCI device.
5187	*
5188	* @param pDevIns Device instance.
5189	* @param pPciDev The PCI device structure. If NULL the default
5190	* PCI device for this device instance is used.
5191	* @param iIrq IRQ number to set.
5192	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5193	* @thread Any thread, but will involve the emulation thread.
5194	*/
5195	DECLRCCALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5196
5197	/**
5198	* Set ISA IRQ for a device.
5199	*
5200	* @param pDevIns Device instance.
5201	* @param iIrq IRQ number to set.
5202	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5203	* @thread Any thread, but will involve the emulation thread.
5204	*/
5205	DECLRCCALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5206
5207	/**
5208	* Read physical memory.
5209	*
5210	* @returns VINF_SUCCESS (for now).
5211	* @param pDevIns Device instance.
5212	* @param GCPhys Physical address start reading from.
5213	* @param pvBuf Where to put the read bits.
5214	* @param cbRead How many bytes to read.
5215	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5216	*/
5217	DECLRCCALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5218
5219	/**
5220	* Write to physical memory.
5221	*
5222	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5223	* @param pDevIns Device instance.
5224	* @param GCPhys Physical address to write to.
5225	* @param pvBuf What to write.
5226	* @param cbWrite How many bytes to write.
5227	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5228	*/
5229	DECLRCCALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5230
5231	/**
5232	* Checks if the Gate A20 is enabled or not.
5233	*
5234	* @returns true if A20 is enabled.
5235	* @returns false if A20 is disabled.
5236	* @param pDevIns Device instance.
5237	* @thread The emulation thread.
5238	*/
5239	DECLRCCALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5240
5241	/**
5242	* Gets the VM state.
5243	*
5244	* @returns VM state.
5245	* @param pDevIns The device instance.
5246	* @thread Any thread (just keep in mind that it's volatile info).
5247	*/
5248	DECLRCCALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5249
5250	/**
5251	* Gets the VM handle. Restricted API.
5252	*
5253	* @returns VM Handle.
5254	* @param pDevIns Device instance.
5255	*/
5256	DECLRCCALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5257
5258	/**
5259	* Gets the VMCPU handle. Restricted API.
5260	*
5261	* @returns VMCPU Handle.
5262	* @param pDevIns The device instance.
5263	*/
5264	DECLRCCALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5265
5266	/**
5267	* The the VM CPU ID of the current thread (restricted API).
5268	*
5269	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5270	* @param pDevIns The device instance.
5271	*/
5272	DECLRCCALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5273
5274	/**
5275	* Gets the main execution engine for the VM.
5276	*
5277	* @returns VM_EXEC_ENGINE_XXX
5278	* @param pDevIns The device instance.
5279	*/
5280	DECLRCCALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5281
5282	/**
5283	* Get the current virtual clock time in a VM. The clock frequency must be
5284	* queried separately.
5285	*
5286	* @returns Current clock time.
5287	* @param pDevIns The device instance.
5288	*/
5289	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5290
5291	/**
5292	* Get the frequency of the virtual clock.
5293	*
5294	* @returns The clock frequency (not variable at run-time).
5295	* @param pDevIns The device instance.
5296	*/
5297	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5298
5299	/**
5300	* Get the current virtual clock time in a VM, in nanoseconds.
5301	*
5302	* @returns Current clock time (in ns).
5303	* @param pDevIns The device instance.
5304	*/
5305	DECLRCCALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5306
5307	/**
5308	* Gets the NOP critical section.
5309	*
5310	* @returns The ring-3 address of the NOP critical section.
5311	* @param pDevIns The device instance.
5312	*/
5313	DECLRCCALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5314
5315	/**
5316	* Changes the device level critical section from the automatically created
5317	* default to one desired by the device constructor.
5318	*
5319	* Must first be done in ring-3.
5320	*
5321	* @returns VBox status code.
5322	* @param pDevIns The device instance.
5323	* @param pCritSect The critical section to use. NULL is not
5324	* valid, instead use the NOP critical
5325	* section.
5326	*/
5327	DECLRCCALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5328
5329	/** @name Exported PDM Critical Section Functions
5330	* @{ */
5331	DECLRCCALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5332	DECLRCCALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5333	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5334	DECLRCCALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5335	DECLRCCALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5336	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5337	DECLRCCALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5338	DECLRCCALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5339	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5340	/** @} */
5341
5342	/** @name Exported PDM Read/Write Critical Section Functions
5343	* @{ */
5344	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5345	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5346	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5347	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5348	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5349
5350	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5351	DECLRCCALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5352	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5353	DECLRCCALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5354	DECLRCCALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5355
5356	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5357	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5358	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5359	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5360	DECLRCCALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5361	DECLRCCALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5362	/** @} */
5363
5364	/**
5365	* Gets the trace buffer handle.
5366	*
5367	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5368	* really inteded for direct usage, thus no inline wrapper function.
5369	*
5370	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5371	* @param pDevIns The device instance.
5372	*/
5373	DECLRCCALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5374
5375	/**
5376	* Sets up the PCI bus for the raw-mode context.
5377	*
5378	* This must be called after ring-3 has registered the PCI bus using
5379	* PDMDevHlpPCIBusRegister().
5380	*
5381	* @returns VBox status code.
5382	* @param pDevIns The device instance.
5383	* @param pPciBusReg The PCI bus registration information for raw-mode,
5384	* considered volatile.
5385	* @param ppPciHlp Where to return the raw-mode PCI bus helpers.
5386	*/
5387	DECLRCCALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGRC pPciBusReg, PCPDMPCIHLPRC *ppPciHlp));
5388
5389	/**
5390	* Sets up the IOMMU for the raw-mode context.
5391	*
5392	* This must be called after ring-3 has registered the IOMMU using
5393	* PDMDevHlpIommuRegister().
5394	*
5395	* @returns VBox status code.
5396	* @param pDevIns The device instance.
5397	* @param pIommuReg The IOMMU registration information for raw-mode,
5398	* considered volatile.
5399	* @param ppIommuHlp Where to return the raw-mode IOMMU helpers.
5400	*/
5401	DECLRCCALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGRC pIommuReg, PCPDMIOMMUHLPRC *ppIommuHlp));
5402
5403	/**
5404	* Sets up the PIC for the ring-0 context.
5405	*
5406	* This must be called after ring-3 has registered the PIC using
5407	* PDMDevHlpPICRegister().
5408	*
5409	* @returns VBox status code.
5410	* @param pDevIns The device instance.
5411	* @param pPicReg The PIC registration information for ring-0,
5412	* considered volatile and copied.
5413	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5414	*/
5415	DECLRCCALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5416
5417	/**
5418	* Sets up the APIC for the raw-mode context.
5419	*
5420	* This must be called after ring-3 has registered the APIC using
5421	* PDMDevHlpApicRegister().
5422	*
5423	* @returns VBox status code.
5424	* @param pDevIns The device instance.
5425	*/
5426	DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5427
5428	/**
5429	* Sets up the IOAPIC for the ring-0 context.
5430	*
5431	* This must be called after ring-3 has registered the PIC using
5432	* PDMDevHlpIoApicRegister().
5433	*
5434	* @returns VBox status code.
5435	* @param pDevIns The device instance.
5436	* @param pIoApicReg The PIC registration information for ring-0,
5437	* considered volatile and copied.
5438	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5439	*/
5440	DECLRCCALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5441
5442	/**
5443	* Sets up the HPET for the raw-mode context.
5444	*
5445	* This must be called after ring-3 has registered the PIC using
5446	* PDMDevHlpHpetRegister().
5447	*
5448	* @returns VBox status code.
5449	* @param pDevIns The device instance.
5450	* @param pHpetReg The PIC registration information for raw-mode,
5451	* considered volatile and copied.
5452	* @param ppHpetHlp Where to return the raw-mode HPET helpers.
5453	*/
5454	DECLRCCALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPRC *ppHpetHlp));
5455
5456	/** Space reserved for future members.
5457	* @{ */
5458	DECLRCCALLBACKMEMBER(void, pfnReserved1,(void));
5459	DECLRCCALLBACKMEMBER(void, pfnReserved2,(void));
5460	DECLRCCALLBACKMEMBER(void, pfnReserved3,(void));
5461	DECLRCCALLBACKMEMBER(void, pfnReserved4,(void));
5462	DECLRCCALLBACKMEMBER(void, pfnReserved5,(void));
5463	DECLRCCALLBACKMEMBER(void, pfnReserved6,(void));
5464	DECLRCCALLBACKMEMBER(void, pfnReserved7,(void));
5465	DECLRCCALLBACKMEMBER(void, pfnReserved8,(void));
5466	DECLRCCALLBACKMEMBER(void, pfnReserved9,(void));
5467	DECLRCCALLBACKMEMBER(void, pfnReserved10,(void));
5468	/** @} */
5469
5470	/** Just a safety precaution. */
5471	uint32_t u32TheEnd;
5472	} PDMDEVHLPRC;
5473	/** Pointer PDM Device RC API. */
5474	typedef RGPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC;
5475	/** Pointer PDM Device RC API. */
5476	typedef RGPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC;
5477
5478	/** Current PDMDEVHLP version number. */
5479	#define PDM_DEVHLPRC_VERSION PDM_VERSION_MAKE(0xffe6, 19, 0)
5480
5481
5482	/**
5483	* PDM Device API - R0 Variant.
5484	*/
5485	typedef struct PDMDEVHLPR0
5486	{
5487	/** Structure version. PDM_DEVHLPR0_VERSION defines the current version. */
5488	uint32_t u32Version;
5489
5490	/**
5491	* Sets up ring-0 callback handlers for an I/O port range.
5492	*
5493	* The range must have been created in ring-3 first using
5494	* PDMDevHlpIoPortCreate() or PDMDevHlpIoPortCreateEx().
5495	*
5496	* @returns VBox status.
5497	* @param pDevIns The device instance to register the ports with.
5498	* @param hIoPorts The I/O port range handle.
5499	* @param pfnOut Pointer to function which is gonna handle OUT
5500	* operations. Optional.
5501	* @param pfnIn Pointer to function which is gonna handle IN operations.
5502	* Optional.
5503	* @param pfnOutStr Pointer to function which is gonna handle string OUT
5504	* operations. Optional.
5505	* @param pfnInStr Pointer to function which is gonna handle string IN
5506	* operations. Optional.
5507	* @param pvUser User argument to pass to the callbacks.
5508	*
5509	* @remarks Caller enters the device critical section prior to invoking the
5510	* registered callback methods.
5511	*
5512	* @sa PDMDevHlpIoPortCreate(), PDMDevHlpIoPortCreateEx(),
5513	* PDMDevHlpIoPortMap(), PDMDevHlpIoPortUnmap().
5514	*/
5515	DECLR0CALLBACKMEMBER(int, pfnIoPortSetUpContextEx,(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
5516	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
5517	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
5518	void *pvUser));
5519
5520	/**
5521	* Sets up ring-0 callback handlers for an MMIO region.
5522	*
5523	* The region must have been created in ring-3 first using
5524	* PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioCreateAndMap(),
5525	* PDMDevHlpMmioCreateExAndMap() or PDMDevHlpPCIIORegionCreateMmio().
5526	*
5527	* @returns VBox status.
5528	* @param pDevIns The device instance to register the ports with.
5529	* @param hRegion The MMIO region handle.
5530	* @param pfnWrite Pointer to function which is gonna handle Write
5531	* operations.
5532	* @param pfnRead Pointer to function which is gonna handle Read
5533	* operations.
5534	* @param pfnFill Pointer to function which is gonna handle Fill/memset
5535	* operations. (optional)
5536	* @param pvUser User argument to pass to the callbacks.
5537	*
5538	* @remarks Caller enters the device critical section prior to invoking the
5539	* registered callback methods.
5540	*
5541	* @sa PDMDevHlpMmioCreate(), PDMDevHlpMmioCreateEx(), PDMDevHlpMmioMap(),
5542	* PDMDevHlpMmioUnmap().
5543	*/
5544	DECLR0CALLBACKMEMBER(int, pfnMmioSetUpContextEx,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
5545	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser));
5546
5547	/**
5548	* Sets up a ring-0 mapping for an MMIO2 region.
5549	*
5550	* The region must have been created in ring-3 first using
5551	* PDMDevHlpMmio2Create().
5552	*
5553	* @returns VBox status.
5554	* @param pDevIns The device instance to register the ports with.
5555	* @param hRegion The MMIO2 region handle.
5556	* @param offSub Start of what to map into ring-0. Must be page aligned.
5557	* @param cbSub Number of bytes to map into ring-0. Must be page
5558	* aligned. Zero is an alias for everything.
5559	* @param ppvMapping Where to return the mapping corresponding to @a offSub.
5560	*
5561	* @thread EMT(0)
5562	* @note Only available at VM creation time.
5563	*
5564	* @sa PDMDevHlpMmio2Create().
5565	*/
5566	DECLR0CALLBACKMEMBER(int, pfnMmio2SetUpContext,(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, size_t offSub, size_t cbSub,
5567	void **ppvMapping));
5568
5569	/**
5570	* Bus master physical memory read from the given PCI device.
5571	*
5572	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5573	* VERR_EM_MEMORY.
5574	* @param pDevIns The device instance.
5575	* @param pPciDev The PCI device structure. If NULL the default
5576	* PCI device for this device instance is used.
5577	* @param GCPhys Physical address start reading from.
5578	* @param pvBuf Where to put the read bits.
5579	* @param cbRead How many bytes to read.
5580	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5581	* @thread Any thread, but the call may involve the emulation thread.
5582	*/
5583	DECLR0CALLBACKMEMBER(int, pfnPCIPhysRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5584	void *pvBuf, size_t cbRead, uint32_t fFlags));
5585
5586	/**
5587	* Bus master physical memory write from the given PCI device.
5588	*
5589	* @returns VINF_SUCCESS or VERR_PDM_NOT_PCI_BUS_MASTER, later maybe
5590	* VERR_EM_MEMORY.
5591	* @param pDevIns The device instance.
5592	* @param pPciDev The PCI device structure. If NULL the default
5593	* PCI device for this device instance is used.
5594	* @param GCPhys Physical address to write to.
5595	* @param pvBuf What to write.
5596	* @param cbWrite How many bytes to write.
5597	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5598	* @thread Any thread, but the call may involve the emulation thread.
5599	*/
5600	DECLR0CALLBACKMEMBER(int, pfnPCIPhysWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
5601	const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5602
5603	/**
5604	* Set the IRQ for the given PCI device.
5605	*
5606	* @param pDevIns Device instance.
5607	* @param pPciDev The PCI device structure. If NULL the default
5608	* PCI device for this device instance is used.
5609	* @param iIrq IRQ number to set.
5610	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5611	* @thread Any thread, but will involve the emulation thread.
5612	*/
5613	DECLR0CALLBACKMEMBER(void, pfnPCISetIrq,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel));
5614
5615	/**
5616	* Set ISA IRQ for a device.
5617	*
5618	* @param pDevIns Device instance.
5619	* @param iIrq IRQ number to set.
5620	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
5621	* @thread Any thread, but will involve the emulation thread.
5622	*/
5623	DECLR0CALLBACKMEMBER(void, pfnISASetIrq,(PPDMDEVINS pDevIns, int iIrq, int iLevel));
5624
5625	/**
5626	* Read physical memory.
5627	*
5628	* @returns VINF_SUCCESS (for now).
5629	* @param pDevIns Device instance.
5630	* @param GCPhys Physical address start reading from.
5631	* @param pvBuf Where to put the read bits.
5632	* @param cbRead How many bytes to read.
5633	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5634	*/
5635	DECLR0CALLBACKMEMBER(int, pfnPhysRead,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags));
5636
5637	/**
5638	* Write to physical memory.
5639	*
5640	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
5641	* @param pDevIns Device instance.
5642	* @param GCPhys Physical address to write to.
5643	* @param pvBuf What to write.
5644	* @param cbWrite How many bytes to write.
5645	* @param fFlags Combination of PDM_DEVHLP_PHYS_RW_F_XXX.
5646	*/
5647	DECLR0CALLBACKMEMBER(int, pfnPhysWrite,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags));
5648
5649	/**
5650	* Checks if the Gate A20 is enabled or not.
5651	*
5652	* @returns true if A20 is enabled.
5653	* @returns false if A20 is disabled.
5654	* @param pDevIns Device instance.
5655	* @thread The emulation thread.
5656	*/
5657	DECLR0CALLBACKMEMBER(bool, pfnA20IsEnabled,(PPDMDEVINS pDevIns));
5658
5659	/**
5660	* Gets the VM state.
5661	*
5662	* @returns VM state.
5663	* @param pDevIns The device instance.
5664	* @thread Any thread (just keep in mind that it's volatile info).
5665	*/
5666	DECLR0CALLBACKMEMBER(VMSTATE, pfnVMState, (PPDMDEVINS pDevIns));
5667
5668	/**
5669	* Gets the VM handle. Restricted API.
5670	*
5671	* @returns VM Handle.
5672	* @param pDevIns Device instance.
5673	*/
5674	DECLR0CALLBACKMEMBER(PVMCC, pfnGetVM,(PPDMDEVINS pDevIns));
5675
5676	/**
5677	* Gets the VMCPU handle. Restricted API.
5678	*
5679	* @returns VMCPU Handle.
5680	* @param pDevIns The device instance.
5681	*/
5682	DECLR0CALLBACKMEMBER(PVMCPUCC, pfnGetVMCPU,(PPDMDEVINS pDevIns));
5683
5684	/**
5685	* The the VM CPU ID of the current thread (restricted API).
5686	*
5687	* @returns The VMCPUID of the calling thread, NIL_VMCPUID if not EMT.
5688	* @param pDevIns The device instance.
5689	*/
5690	DECLR0CALLBACKMEMBER(VMCPUID, pfnGetCurrentCpuId,(PPDMDEVINS pDevIns));
5691
5692	/**
5693	* Gets the main execution engine for the VM.
5694	*
5695	* @returns VM_EXEC_ENGINE_XXX
5696	* @param pDevIns The device instance.
5697	*/
5698	DECLR0CALLBACKMEMBER(uint8_t, pfnGetMainExecutionEngine,(PPDMDEVINS pDevIns));
5699
5700	/** @name Timer handle method wrappers
5701	* @{ */
5702	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs));
5703	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromMilli,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs));
5704	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerFromNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs));
5705	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5706	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetFreq,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5707	DECLR0CALLBACKMEMBER(uint64_t, pfnTimerGetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5708	DECLR0CALLBACKMEMBER(bool, pfnTimerIsActive,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5709	DECLR0CALLBACKMEMBER(bool, pfnTimerIsLockOwner,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5710	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy));
5711	/** Takes the clock lock then enters the specified critical section. */
5712	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnTimerLockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy));
5713	DECLR0CALLBACKMEMBER(int, pfnTimerSet,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire));
5714	DECLR0CALLBACKMEMBER(int, pfnTimerSetFrequencyHint,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz));
5715	DECLR0CALLBACKMEMBER(int, pfnTimerSetMicro,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext));
5716	DECLR0CALLBACKMEMBER(int, pfnTimerSetMillies,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext));
5717	DECLR0CALLBACKMEMBER(int, pfnTimerSetNano,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext));
5718	DECLR0CALLBACKMEMBER(int, pfnTimerSetRelative,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now));
5719	DECLR0CALLBACKMEMBER(int, pfnTimerStop,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5720	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer));
5721	DECLR0CALLBACKMEMBER(void, pfnTimerUnlockClock2,(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect));
5722	/** @} */
5723
5724	/**
5725	* Get the current virtual clock time in a VM. The clock frequency must be
5726	* queried separately.
5727	*
5728	* @returns Current clock time.
5729	* @param pDevIns The device instance.
5730	*/
5731	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGet,(PPDMDEVINS pDevIns));
5732
5733	/**
5734	* Get the frequency of the virtual clock.
5735	*
5736	* @returns The clock frequency (not variable at run-time).
5737	* @param pDevIns The device instance.
5738	*/
5739	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetFreq,(PPDMDEVINS pDevIns));
5740
5741	/**
5742	* Get the current virtual clock time in a VM, in nanoseconds.
5743	*
5744	* @returns Current clock time (in ns).
5745	* @param pDevIns The device instance.
5746	*/
5747	DECLR0CALLBACKMEMBER(uint64_t, pfnTMTimeVirtGetNano,(PPDMDEVINS pDevIns));
5748
5749	/** @name Exported PDM Queue Functions
5750	* @{ */
5751	DECLR0CALLBACKMEMBER(PPDMQUEUEITEMCORE, pfnQueueAlloc,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5752	DECLR0CALLBACKMEMBER(int, pfnQueueInsert,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem));
5753	DECLR0CALLBACKMEMBER(bool, pfnQueueFlushIfNecessary,(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue));
5754	/** @} */
5755
5756	/** @name PDM Task
5757	* @{ */
5758	/**
5759	* Triggers the running the given task.
5760	*
5761	* @returns VBox status code.
5762	* @retval VINF_ALREADY_POSTED is the task is already pending.
5763	* @param pDevIns The device instance.
5764	* @param hTask The task to trigger.
5765	* @thread Any thread.
5766	*/
5767	DECLR0CALLBACKMEMBER(int, pfnTaskTrigger,(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask));
5768	/** @} */
5769
5770	/** @name SUP Event Semaphore Wrappers (single release / auto reset)
5771	* These semaphores can be signalled from ring-0.
5772	* @{ */
5773	/** @sa SUPSemEventSignal */
5774	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventSignal,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent));
5775	/** @sa SUPSemEventWaitNoResume */
5776	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies));
5777	/** @sa SUPSemEventWaitNsAbsIntr */
5778	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout));
5779	/** @sa SUPSemEventWaitNsRelIntr */
5780	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout));
5781	/** @sa SUPSemEventGetResolution */
5782	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventGetResolution,(PPDMDEVINS pDevIns));
5783	/** @} */
5784
5785	/** @name SUP Multi Event Semaphore Wrappers (multiple release / manual reset)
5786	* These semaphores can be signalled from ring-0.
5787	* @{ */
5788	/** @sa SUPSemEventMultiSignal */
5789	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiSignal,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5790	/** @sa SUPSemEventMultiReset */
5791	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiReset,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti));
5792	/** @sa SUPSemEventMultiWaitNoResume */
5793	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNoResume,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies));
5794	/** @sa SUPSemEventMultiWaitNsAbsIntr */
5795	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsAbsIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout));
5796	/** @sa SUPSemEventMultiWaitNsRelIntr */
5797	DECLR0CALLBACKMEMBER(int, pfnSUPSemEventMultiWaitNsRelIntr,(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout));
5798	/** @sa SUPSemEventMultiGetResolution */
5799	DECLR0CALLBACKMEMBER(uint32_t, pfnSUPSemEventMultiGetResolution,(PPDMDEVINS pDevIns));
5800	/** @} */
5801
5802	/**
5803	* Gets the NOP critical section.
5804	*
5805	* @returns The ring-3 address of the NOP critical section.
5806	* @param pDevIns The device instance.
5807	*/
5808	DECLR0CALLBACKMEMBER(PPDMCRITSECT, pfnCritSectGetNop,(PPDMDEVINS pDevIns));
5809
5810	/**
5811	* Changes the device level critical section from the automatically created
5812	* default to one desired by the device constructor.
5813	*
5814	* Must first be done in ring-3.
5815	*
5816	* @returns VBox status code.
5817	* @param pDevIns The device instance.
5818	* @param pCritSect The critical section to use. NULL is not
5819	* valid, instead use the NOP critical
5820	* section.
5821	*/
5822	DECLR0CALLBACKMEMBER(int, pfnSetDeviceCritSect,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5823
5824	/** @name Exported PDM Critical Section Functions
5825	* @{ */
5826	DECLR0CALLBACKMEMBER(int, pfnCritSectEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy));
5827	DECLR0CALLBACKMEMBER(int, pfnCritSectEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5828	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnter,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5829	DECLR0CALLBACKMEMBER(int, pfnCritSectTryEnterDebug,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5830	DECLR0CALLBACKMEMBER(int, pfnCritSectLeave,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect));
5831	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsOwner,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5832	DECLR0CALLBACKMEMBER(bool, pfnCritSectIsInitialized,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5833	DECLR0CALLBACKMEMBER(bool, pfnCritSectHasWaiters,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5834	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectGetRecursion,(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect));
5835	DECLR0CALLBACKMEMBER(int, pfnCritSectScheduleExitEvent,(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal));
5836	/** @} */
5837
5838	/** @name Exported PDM Read/Write Critical Section Functions
5839	* @{ */
5840	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5841	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5842	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5843	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterSharedDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5844	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveShared,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5845
5846	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy));
5847	DECLR0CALLBACKMEMBER(int, pfnCritSectRwEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5848	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5849	DECLR0CALLBACKMEMBER(int, pfnCritSectRwTryEnterExclDebug,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL));
5850	DECLR0CALLBACKMEMBER(int, pfnCritSectRwLeaveExcl,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5851
5852	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsWriteOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5853	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsReadOwner,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear));
5854	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriteRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5855	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetWriterReadRecursion,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5856	DECLR0CALLBACKMEMBER(uint32_t, pfnCritSectRwGetReadCount,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5857	DECLR0CALLBACKMEMBER(bool, pfnCritSectRwIsInitialized,(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect));
5858	/** @} */
5859
5860	/**
5861	* Gets the trace buffer handle.
5862	*
5863	* This is used by the macros found in VBox/vmm/dbgftrace.h and is not
5864	* really inteded for direct usage, thus no inline wrapper function.
5865	*
5866	* @returns Trace buffer handle or NIL_RTTRACEBUF.
5867	* @param pDevIns The device instance.
5868	*/
5869	DECLR0CALLBACKMEMBER(RTTRACEBUF, pfnDBGFTraceBuf,(PPDMDEVINS pDevIns));
5870
5871	/**
5872	* Sets up the PCI bus for the ring-0 context.
5873	*
5874	* This must be called after ring-3 has registered the PCI bus using
5875	* PDMDevHlpPCIBusRegister().
5876	*
5877	* @returns VBox status code.
5878	* @param pDevIns The device instance.
5879	* @param pPciBusReg The PCI bus registration information for ring-0,
5880	* considered volatile and copied.
5881	* @param ppPciHlp Where to return the ring-0 PCI bus helpers.
5882	*/
5883	DECLR0CALLBACKMEMBER(int, pfnPCIBusSetUpContext,(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp));
5884
5885	/**
5886	* Sets up the IOMMU for the ring-0 context.
5887	*
5888	* This must be called after ring-3 has registered the IOMMU using
5889	* PDMDevHlpIommuRegister().
5890	*
5891	* @returns VBox status code.
5892	* @param pDevIns The device instance.
5893	* @param pIommuReg The IOMMU registration information for ring-0,
5894	* considered volatile and copied.
5895	* @param ppIommuHlp Where to return the ring-0 IOMMU helpers.
5896	*/
5897	DECLR0CALLBACKMEMBER(int, pfnIommuSetUpContext,(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp));
5898
5899	/**
5900	* Sets up the PIC for the ring-0 context.
5901	*
5902	* This must be called after ring-3 has registered the PIC using
5903	* PDMDevHlpPICRegister().
5904	*
5905	* @returns VBox status code.
5906	* @param pDevIns The device instance.
5907	* @param pPicReg The PIC registration information for ring-0,
5908	* considered volatile and copied.
5909	* @param ppPicHlp Where to return the ring-0 PIC helpers.
5910	*/
5911	DECLR0CALLBACKMEMBER(int, pfnPICSetUpContext,(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp));
5912
5913	/**
5914	* Sets up the APIC for the ring-0 context.
5915	*
5916	* This must be called after ring-3 has registered the APIC using
5917	* PDMDevHlpApicRegister().
5918	*
5919	* @returns VBox status code.
5920	* @param pDevIns The device instance.
5921	*/
5922	DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
5923
5924	/**
5925	* Sets up the IOAPIC for the ring-0 context.
5926	*
5927	* This must be called after ring-3 has registered the PIC using
5928	* PDMDevHlpIoApicRegister().
5929	*
5930	* @returns VBox status code.
5931	* @param pDevIns The device instance.
5932	* @param pIoApicReg The PIC registration information for ring-0,
5933	* considered volatile and copied.
5934	* @param ppIoApicHlp Where to return the ring-0 IOAPIC helpers.
5935	*/
5936	DECLR0CALLBACKMEMBER(int, pfnIoApicSetUpContext,(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp));
5937
5938	/**
5939	* Sets up the HPET for the ring-0 context.
5940	*
5941	* This must be called after ring-3 has registered the PIC using
5942	* PDMDevHlpHpetRegister().
5943	*
5944	* @returns VBox status code.
5945	* @param pDevIns The device instance.
5946	* @param pHpetReg The PIC registration information for ring-0,
5947	* considered volatile and copied.
5948	* @param ppHpetHlp Where to return the ring-0 HPET helpers.
5949	*/
5950	DECLR0CALLBACKMEMBER(int, pfnHpetSetUpContext,(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp));
5951
5952	/**
5953	* Sets up a physical page access handler type for ring-0 callbacks.
5954	*
5955	* @returns VBox status code.
5956	* @param pDevIns The device instance.
5957	* @param enmKind The kind of access handler.
5958	* @param pfnHandler Pointer to the ring-0 handler callback. NULL if
5959	* the ring-3 handler should be called.
5960	* @param pfnPfHandler The name of the ring-0 \#PF handler, NULL if the
5961	* ring-3 handler should be called.
5962	* @param pszDesc The type description.
5963	* @param hType The type handle registered in ring-3 already.
5964	* @sa PDMDevHlpPGMHandlerPhysicalTypeRegister
5965	*/
5966	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalTypeSetUpContext, (PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
5967	PFNPGMPHYSHANDLER pfnHandler,
5968	PFNPGMRZPHYSPFHANDLER pfnPfHandler,
5969	const char *pszDesc, PGMPHYSHANDLERTYPE hType));
5970
5971	/**
5972	* Temporarily turns off the access monitoring of a page within a monitored
5973	* physical write/all page access handler region.
5974	*
5975	* Use this when no further \#PFs are required for that page. Be aware that
5976	* a page directory sync might reset the flags, and turn on access monitoring
5977	* for the page.
5978	*
5979	* The caller must do required page table modifications.
5980	*
5981	* @returns VBox status code.
5982	* @param pDevIns The device instance.
5983	* @param GCPhys The start address of the access handler. This
5984	* must be a fully page aligned range or we risk
5985	* messing up other handlers installed for the
5986	* start and end pages.
5987	* @param GCPhysPage The physical address of the page to turn off
5988	* access monitoring for.
5989	*/
5990	DECLR0CALLBACKMEMBER(int, pfnPGMHandlerPhysicalPageTempOff,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage));
5991
5992	/**
5993	* Mapping an MMIO2 page in place of an MMIO page for direct access.
5994	*
5995	* This is a special optimization used by the VGA device. Call
5996	* PDMDevHlpMmioResetRegion() to undo the mapping.
5997	*
5998	* @returns VBox status code. This API may return VINF_SUCCESS even if no
5999	* remapping is made.
6000	* @retval VERR_SEM_BUSY in ring-0 if we cannot get the IOM lock.
6001	*
6002	* @param pDevIns The device instance @a hRegion and @a hMmio2 are
6003	* associated with.
6004	* @param hRegion The handle to the MMIO region.
6005	* @param offRegion The offset into @a hRegion of the page to be
6006	* remapped.
6007	* @param hMmio2 The MMIO2 handle.
6008	* @param offMmio2 Offset into @a hMmio2 of the page to be use for the
6009	* mapping.
6010	* @param fPageFlags Page flags to set. Must be (X86_PTE_RW \| X86_PTE_P)
6011	* for the time being.
6012	*/
6013	DECLR0CALLBACKMEMBER(int, pfnMmioMapMmio2Page,(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6014	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags));
6015
6016	/**
6017	* Reset a previously modified MMIO region; restore the access flags.
6018	*
6019	* This undoes the effects of PDMDevHlpMmioMapMmio2Page() and is currently only
6020	* intended for some ancient VGA hack. However, it would be great to extend it
6021	* beyond VT-x and/or nested-paging.
6022	*
6023	* @returns VBox status code.
6024	*
6025	* @param pDevIns The device instance @a hRegion is associated with.
6026	* @param hRegion The handle to the MMIO region.
6027	*/
6028	DECLR0CALLBACKMEMBER(int, pfnMmioResetRegion, (PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion));
6029
6030	/**
6031	* Returns the array of MMIO2 regions that are expected to be registered and
6032	* later mapped into the guest-physical address space for the GIM provider
6033	* configured for the VM.
6034	*
6035	* @returns Pointer to an array of GIM MMIO2 regions, may return NULL.
6036	* @param pDevIns Pointer to the GIM device instance.
6037	* @param pcRegions Where to store the number of items in the array.
6038	*
6039	* @remarks The caller does not own and therefore must -NOT- try to free the
6040	* returned pointer.
6041	*/
6042	DECLR0CALLBACKMEMBER(PGIMMMIO2REGION, pfnGIMGetMmio2Regions,(PPDMDEVINS pDevIns, uint32_t *pcRegions));
6043
6044	/** Space reserved for future members.
6045	* @{ */
6046	DECLR0CALLBACKMEMBER(void, pfnReserved1,(void));
6047	DECLR0CALLBACKMEMBER(void, pfnReserved2,(void));
6048	DECLR0CALLBACKMEMBER(void, pfnReserved3,(void));
6049	DECLR0CALLBACKMEMBER(void, pfnReserved4,(void));
6050	DECLR0CALLBACKMEMBER(void, pfnReserved5,(void));
6051	DECLR0CALLBACKMEMBER(void, pfnReserved6,(void));
6052	DECLR0CALLBACKMEMBER(void, pfnReserved7,(void));
6053	DECLR0CALLBACKMEMBER(void, pfnReserved8,(void));
6054	DECLR0CALLBACKMEMBER(void, pfnReserved9,(void));
6055	DECLR0CALLBACKMEMBER(void, pfnReserved10,(void));
6056	/** @} */
6057
6058	/** Just a safety precaution. */
6059	uint32_t u32TheEnd;
6060	} PDMDEVHLPR0;
6061	/** Pointer PDM Device R0 API. */
6062	typedef R0PTRTYPE(struct PDMDEVHLPR0 *) PPDMDEVHLPR0;
6063	/** Pointer PDM Device GC API. */
6064	typedef R0PTRTYPE(const struct PDMDEVHLPR0 *) PCPDMDEVHLPR0;
6065
6066	/** Current PDMDEVHLP version number. */
6067	#define PDM_DEVHLPR0_VERSION PDM_VERSION_MAKE(0xffe5, 27, 0)
6068
6069
6070	/**
6071	* PDM Device Instance.
6072	*/
6073	typedef struct PDMDEVINSR3
6074	{
6075	/** Structure version. PDM_DEVINSR3_VERSION defines the current version. */
6076	uint32_t u32Version;
6077	/** Device instance number. */
6078	uint32_t iInstance;
6079	/** Size of the ring-3, raw-mode and shared bits. */
6080	uint32_t cbRing3;
6081	/** Set if ring-0 context is enabled. */
6082	bool fR0Enabled;
6083	/** Set if raw-mode context is enabled. */
6084	bool fRCEnabled;
6085	/** Alignment padding. */
6086	bool afReserved[2];
6087	/** Pointer the HC PDM Device API. */
6088	PCPDMDEVHLPR3 pHlpR3;
6089	/** Pointer to the shared device instance data. */
6090	RTR3PTR pvInstanceDataR3;
6091	/** Pointer to the device instance data for ring-3. */
6092	RTR3PTR pvInstanceDataForR3;
6093	/** The critical section for the device.
6094	*
6095	* TM and IOM will enter this critical section before calling into the device
6096	* code. PDM will when doing power on, power off, reset, suspend and resume
6097	* notifications. SSM will currently not, but this will be changed later on.
6098	*
6099	* The device gets a critical section automatically assigned to it before
6100	* the constructor is called. If the constructor wishes to use a different
6101	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6102	* very early on.
6103	*/
6104	R3PTRTYPE(PPDMCRITSECT) pCritSectRoR3;
6105	/** Pointer to device registration structure. */
6106	R3PTRTYPE(PCPDMDEVREG) pReg;
6107	/** Configuration handle. */
6108	R3PTRTYPE(PCFGMNODE) pCfg;
6109	/** The base interface of the device.
6110	*
6111	* The device constructor initializes this if it has any
6112	* device level interfaces to export. To obtain this interface
6113	* call PDMR3QueryDevice(). */
6114	PDMIBASE IBase;
6115
6116	/** Tracing indicator. */
6117	uint32_t fTracing;
6118	/** The tracing ID of this device. */
6119	uint32_t idTracing;
6120
6121	/** Ring-3 pointer to the raw-mode device instance. */
6122	R3PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR3;
6123	/** Raw-mode address of the raw-mode device instance. */
6124	RTRGPTR pDevInsForRC;
6125	/** Ring-3 pointer to the raw-mode instance data. */
6126	RTR3PTR pvInstanceDataForRCR3;
6127
6128	/** PCI device structure size. */
6129	uint32_t cbPciDev;
6130	/** Number of PCI devices in apPciDevs. */
6131	uint32_t cPciDevs;
6132	/** Pointer to the PCI devices for this device.
6133	* (Allocated after the shared instance data.)
6134	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6135	* two devices ever needing it can use cbPciDev and do the address
6136	* calculations that for entries 8+. */
6137	R3PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6138
6139	/** Temporarily. */
6140	R0PTRTYPE(struct PDMDEVINSR0 *) pDevInsR0RemoveMe;
6141	/** Temporarily. */
6142	RTR0PTR pvInstanceDataR0;
6143	/** Temporarily. */
6144	RTRCPTR pvInstanceDataRC;
6145	/** Align the internal data more naturally. */
6146	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 13 : 11];
6147
6148	/** Internal data. */
6149	union
6150	{
6151	#ifdef PDMDEVINSINT_DECLARED
6152	PDMDEVINSINTR3 s;
6153	#endif
6154	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x90];
6155	} Internal;
6156
6157	/** Device instance data for ring-3. The size of this area is defined
6158	* in the PDMDEVREG::cbInstanceR3 field. */
6159	char achInstanceData[8];
6160	} PDMDEVINSR3;
6161
6162	/** Current PDMDEVINSR3 version number. */
6163	#define PDM_DEVINSR3_VERSION PDM_VERSION_MAKE(0xff82, 4, 0)
6164
6165	/** Converts a pointer to the PDMDEVINSR3::IBase to a pointer to PDMDEVINS. */
6166	#define PDMIBASE_2_PDMDEV(pInterface) ( (PPDMDEVINS)((char *)(pInterface) - RT_UOFFSETOF(PDMDEVINS, IBase)) )
6167
6168
6169	/**
6170	* PDM ring-0 device instance.
6171	*/
6172	typedef struct PDMDEVINSR0
6173	{
6174	/** Structure version. PDM_DEVINSR0_VERSION defines the current version. */
6175	uint32_t u32Version;
6176	/** Device instance number. */
6177	uint32_t iInstance;
6178
6179	/** Pointer the HC PDM Device API. */
6180	PCPDMDEVHLPR0 pHlpR0;
6181	/** Pointer to the shared device instance data. */
6182	RTR0PTR pvInstanceDataR0;
6183	/** Pointer to the device instance data for ring-0. */
6184	RTR0PTR pvInstanceDataForR0;
6185	/** The critical section for the device.
6186	*
6187	* TM and IOM will enter this critical section before calling into the device
6188	* code. PDM will when doing power on, power off, reset, suspend and resume
6189	* notifications. SSM will currently not, but this will be changed later on.
6190	*
6191	* The device gets a critical section automatically assigned to it before
6192	* the constructor is called. If the constructor wishes to use a different
6193	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6194	* very early on.
6195	*/
6196	R0PTRTYPE(PPDMCRITSECT) pCritSectRoR0;
6197	/** Pointer to the ring-0 device registration structure. */
6198	R0PTRTYPE(PCPDMDEVREGR0) pReg;
6199	/** Ring-3 address of the ring-3 device instance. */
6200	R3PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3;
6201	/** Ring-0 pointer to the ring-3 device instance. */
6202	R0PTRTYPE(struct PDMDEVINSR3 *) pDevInsForR3R0;
6203	/** Ring-0 pointer to the ring-3 instance data. */
6204	RTR0PTR pvInstanceDataForR3R0;
6205	/** Raw-mode address of the raw-mode device instance. */
6206	RGPTRTYPE(struct PDMDEVINSRC *) pDevInsForRC;
6207	/** Ring-0 pointer to the raw-mode device instance. */
6208	R0PTRTYPE(struct PDMDEVINSRC *) pDevInsForRCR0;
6209	/** Ring-0 pointer to the raw-mode instance data. */
6210	RTR0PTR pvInstanceDataForRCR0;
6211
6212	/** PCI device structure size. */
6213	uint32_t cbPciDev;
6214	/** Number of PCI devices in apPciDevs. */
6215	uint32_t cPciDevs;
6216	/** Pointer to the PCI devices for this device.
6217	* (Allocated after the shared instance data.)
6218	* @note If we want to extend this beyond 8 sub-functions/devices, those 1 or
6219	* two devices ever needing it can use cbPciDev and do the address
6220	* calculations that for entries 8+. */
6221	R0PTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6222
6223	/** Align the internal data more naturally. */
6224	uint32_t au32Padding[HC_ARCH_BITS == 32 ? 3 : 2 + 4];
6225
6226	/** Internal data. */
6227	union
6228	{
6229	#ifdef PDMDEVINSINT_DECLARED
6230	PDMDEVINSINTR0 s;
6231	#endif
6232	uint8_t padding[HC_ARCH_BITS == 32 ? 0x40 : 0x80];
6233	} Internal;
6234
6235	/** Device instance data for ring-0. The size of this area is defined
6236	* in the PDMDEVREG::cbInstanceR0 field. */
6237	char achInstanceData[8];
6238	} PDMDEVINSR0;
6239
6240	/** Current PDMDEVINSR0 version number. */
6241	#define PDM_DEVINSR0_VERSION PDM_VERSION_MAKE(0xff83, 4, 0)
6242
6243
6244	/**
6245	* PDM raw-mode device instance.
6246	*/
6247	typedef struct PDMDEVINSRC
6248	{
6249	/** Structure version. PDM_DEVINSRC_VERSION defines the current version. */
6250	uint32_t u32Version;
6251	/** Device instance number. */
6252	uint32_t iInstance;
6253
6254	/** Pointer the HC PDM Device API. */
6255	PCPDMDEVHLPRC pHlpRC;
6256	/** Pointer to the shared device instance data. */
6257	RTRGPTR pvInstanceDataRC;
6258	/** Pointer to the device instance data for raw-mode. */
6259	RTRGPTR pvInstanceDataForRC;
6260	/** The critical section for the device.
6261	*
6262	* TM and IOM will enter this critical section before calling into the device
6263	* code. PDM will when doing power on, power off, reset, suspend and resume
6264	* notifications. SSM will currently not, but this will be changed later on.
6265	*
6266	* The device gets a critical section automatically assigned to it before
6267	* the constructor is called. If the constructor wishes to use a different
6268	* critical section, it calls PDMDevHlpSetDeviceCritSect() to change it
6269	* very early on.
6270	*/
6271	RGPTRTYPE(PPDMCRITSECT) pCritSectRoRC;
6272	/** Pointer to the raw-mode device registration structure. */
6273	RGPTRTYPE(PCPDMDEVREGRC) pReg;
6274
6275	/** PCI device structure size. */
6276	uint32_t cbPciDev;
6277	/** Number of PCI devices in apPciDevs. */
6278	uint32_t cPciDevs;
6279	/** Pointer to the PCI devices for this device.
6280	* (Allocated after the shared instance data.) */
6281	RGPTRTYPE(struct PDMPCIDEV *) apPciDevs[8];
6282
6283	/** Align the internal data more naturally. */
6284	uint32_t au32Padding[14];
6285
6286	/** Internal data. */
6287	union
6288	{
6289	#ifdef PDMDEVINSINT_DECLARED
6290	PDMDEVINSINTRC s;
6291	#endif
6292	uint8_t padding[0x10];
6293	} Internal;
6294
6295	/** Device instance data for ring-0. The size of this area is defined
6296	* in the PDMDEVREG::cbInstanceR0 field. */
6297	char achInstanceData[8];
6298	} PDMDEVINSRC;
6299
6300	/** Current PDMDEVINSR0 version number. */
6301	#define PDM_DEVINSRC_VERSION PDM_VERSION_MAKE(0xff84, 4, 0)
6302
6303
6304	/** @def PDM_DEVINS_VERSION
6305	* Current PDMDEVINS version number. */
6306	/** @typedef PDMDEVINS
6307	* The device instance structure for the current context. */
6308	#ifdef IN_RING3
6309	# define PDM_DEVINS_VERSION PDM_DEVINSR3_VERSION
6310	typedef PDMDEVINSR3 PDMDEVINS;
6311	#elif defined(IN_RING0)
6312	# define PDM_DEVINS_VERSION PDM_DEVINSR0_VERSION
6313	typedef PDMDEVINSR0 PDMDEVINS;
6314	#elif defined(IN_RC)
6315	# define PDM_DEVINS_VERSION PDM_DEVINSRC_VERSION
6316	typedef PDMDEVINSRC PDMDEVINS;
6317	#else
6318	# error "Missing context defines: IN_RING0, IN_RING3, IN_RC"
6319	#endif
6320
6321	/**
6322	* Get the pointer to an PCI device.
6323	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6324	*/
6325	#define PDMDEV_GET_PPCIDEV(a_pDevIns, a_idxPciDev) \
6326	( (uintptr_t)(a_idxPciDev) < RT_ELEMENTS((a_pDevIns)->apPciDevs) ? (a_pDevIns)->apPciDevs[(uintptr_t)(a_idxPciDev)] \
6327	: PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) )
6328
6329	/**
6330	* Calc the pointer to of a given PCI device.
6331	* @note Returns NULL if @a a_idxPciDev is out of bounds.
6332	*/
6333	#define PDMDEV_CALC_PPCIDEV(a_pDevIns, a_idxPciDev) \
6334	( (uintptr_t)(a_idxPciDev) < (a_pDevIns)->cPciDevs \
6335	? (PPDMPCIDEV)((uint8_t )((a_pDevIns)->apPciDevs[0]) + (a_pDevIns->cbPciDev) (uintptr_t)(a_idxPciDev)) \
6336	: (PPDMPCIDEV)NULL )
6337
6338
6339	/**
6340	* Checks the structure versions of the device instance and device helpers,
6341	* returning if they are incompatible.
6342	*
6343	* This is for use in the constructor.
6344	*
6345	* @param pDevIns The device instance pointer.
6346	*/
6347	#define PDMDEV_CHECK_VERSIONS_RETURN(pDevIns) \
6348	do \
6349	{ \
6350	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6351	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6352	("DevIns=%#x mine=%#x\n", (pDevIns)->u32Version, PDM_DEVINS_VERSION), \
6353	VERR_PDM_DEVINS_VERSION_MISMATCH); \
6354	AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6355	("DevHlp=%#x mine=%#x\n", (pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)), \
6356	VERR_PDM_DEVHLP_VERSION_MISMATCH); \
6357	} while (0)
6358
6359	/**
6360	* Quietly checks the structure versions of the device instance and device
6361	* helpers, returning if they are incompatible.
6362	*
6363	* This is for use in the destructor.
6364	*
6365	* @param pDevIns The device instance pointer.
6366	*/
6367	#define PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns) \
6368	do \
6369	{ \
6370	PPDMDEVINS pDevInsTypeCheck = (pDevIns); NOREF(pDevInsTypeCheck); \
6371	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->u32Version, PDM_DEVINS_VERSION) )) \
6372	{ /* likely */ } else return VERR_PDM_DEVINS_VERSION_MISMATCH; \
6373	if (RT_LIKELY(PDM_VERSION_ARE_COMPATIBLE((pDevIns)->CTX_SUFF(pHlp)->u32Version, CTX_MID(PDM_DEVHLP,_VERSION)) )) \
6374	{ /* likely */ } else return VERR_PDM_DEVHLP_VERSION_MISMATCH; \
6375	} while (0)
6376
6377	/**
6378	* Wrapper around CFGMR3ValidateConfig for the root config for use in the
6379	* constructor - returns on failure.
6380	*
6381	* This should be invoked after having initialized the instance data
6382	* sufficiently for the correct operation of the destructor. The destructor is
6383	* always called!
6384	*
6385	* @param pDevIns Pointer to the PDM device instance.
6386	* @param pszValidValues Patterns describing the valid value names. See
6387	* RTStrSimplePatternMultiMatch for details on the
6388	* pattern syntax.
6389	* @param pszValidNodes Patterns describing the valid node (key) names.
6390	* Pass empty string if no valid nodes.
6391	*/
6392	#define PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, pszValidValues, pszValidNodes) \
6393	do \
6394	{ \
6395	int rcValCfg = pDevIns->pHlpR3->pfnCFGMValidateConfig((pDevIns)->pCfg, "/", pszValidValues, pszValidNodes, \
6396	(pDevIns)->pReg->szName, (pDevIns)->iInstance); \
6397	if (RT_SUCCESS(rcValCfg)) \
6398	{ /* likely */ } else return rcValCfg; \
6399	} while (0)
6400
6401	/** @def PDMDEV_ASSERT_EMT
6402	* Assert that the current thread is the emulation thread.
6403	*/
6404	#ifdef VBOX_STRICT
6405	# define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6406	#else
6407	# define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0)
6408	#endif
6409
6410	/** @def PDMDEV_ASSERT_OTHER
6411	* Assert that the current thread is NOT the emulation thread.
6412	*/
6413	#ifdef VBOX_STRICT
6414	# define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6415	#else
6416	# define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0)
6417	#endif
6418
6419	/** @def PDMDEV_ASSERT_VMLOCK_OWNER
6420	* Assert that the current thread is owner of the VM lock.
6421	*/
6422	#ifdef VBOX_STRICT
6423	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)
6424	#else
6425	# define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0)
6426	#endif
6427
6428	/** @def PDMDEV_SET_ERROR
6429	* Set the VM error. See PDMDevHlpVMSetError() for printf like message formatting.
6430	*/
6431	#define PDMDEV_SET_ERROR(pDevIns, rc, pszError) \
6432	PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, "%s", pszError)
6433
6434	/** @def PDMDEV_SET_RUNTIME_ERROR
6435	* Set the VM runtime error. See PDMDevHlpVMSetRuntimeError() for printf like message formatting.
6436	*/
6437	#define PDMDEV_SET_RUNTIME_ERROR(pDevIns, fFlags, pszErrorId, pszError) \
6438	PDMDevHlpVMSetRuntimeError(pDevIns, fFlags, pszErrorId, "%s", pszError)
6439
6440	/** @def PDMDEVINS_2_RCPTR
6441	* Converts a PDM Device instance pointer to a RC PDM Device instance pointer.
6442	*/
6443	#ifdef IN_RC
6444	# define PDMDEVINS_2_RCPTR(pDevIns) (pDevIns)
6445	#else
6446	# define PDMDEVINS_2_RCPTR(pDevIns) ( (pDevIns)->pDevInsForRC )
6447	#endif
6448
6449	/** @def PDMDEVINS_2_R3PTR
6450	* Converts a PDM Device instance pointer to a R3 PDM Device instance pointer.
6451	*/
6452	#ifdef IN_RING3
6453	# define PDMDEVINS_2_R3PTR(pDevIns) (pDevIns)
6454	#else
6455	# define PDMDEVINS_2_R3PTR(pDevIns) ( (pDevIns)->pDevInsForR3 )
6456	#endif
6457
6458	/** @def PDMDEVINS_2_R0PTR
6459	* Converts a PDM Device instance pointer to a R0 PDM Device instance pointer.
6460	*/
6461	#ifdef IN_RING0
6462	# define PDMDEVINS_2_R0PTR(pDevIns) (pDevIns)
6463	#else
6464	# define PDMDEVINS_2_R0PTR(pDevIns) ( (pDevIns)->pDevInsR0RemoveMe )
6465	#endif
6466
6467	/** @def PDMDEVINS_DATA_2_R0_REMOVE_ME
6468	* Converts a PDM device instance data pointer to a ring-0 one.
6469	* @deprecated
6470	*/
6471	#ifdef IN_RING0
6472	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) (pvCC)
6473	#else
6474	# define PDMDEVINS_DATA_2_R0_REMOVE_ME(pDevIns, pvCC) ( (pDevIns)->pvInstanceDataR0 + (uintptr_t)(pvCC) - (uintptr_t)(pDevIns)->CTX_SUFF(pvInstanceData) )
6475	#endif
6476
6477
6478	/** @def PDMDEVINS_2_DATA
6479	* This is a safer edition of PDMINS_2_DATA that checks that the size of the
6480	* target type is same as PDMDEVREG::cbInstanceShared in strict builds.
6481	*
6482	* @note Do no use this macro in common code working on a core structure which
6483	* device specific code has expanded.
6484	*/
6485	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6486	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) \
6487	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6488	{ \
6489	a_PtrType pLambdaRet = (a_PtrType)(a_pLambdaDevIns)->CTX_SUFF(pvInstanceData); \
6490	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceShared); \
6491	return pLambdaRet; \
6492	}(a_pDevIns))
6493	#else
6494	# define PDMDEVINS_2_DATA(a_pDevIns, a_PtrType) ( (a_PtrType)(a_pDevIns)->CTX_SUFF(pvInstanceData) )
6495	#endif
6496
6497	/** @def PDMDEVINS_2_DATA_CC
6498	* This is a safer edition of PDMINS_2_DATA_CC that checks that the size of the
6499	* target type is same as PDMDEVREG::cbInstanceCC in strict builds.
6500	*
6501	* @note Do no use this macro in common code working on a core structure which
6502	* device specific code has expanded.
6503	*/
6504	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
6505	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) \
6506	([](PPDMDEVINS a_pLambdaDevIns) -> a_PtrType \
6507	{ \
6508	a_PtrType pLambdaRet = (a_PtrType)&(a_pLambdaDevIns)->achInstanceData[0]; \
6509	Assert(sizeof(*pLambdaRet) == a_pLambdaDevIns->pReg->cbInstanceCC); \
6510	return pLambdaRet; \
6511	}(a_pDevIns))
6512	#else
6513	# define PDMDEVINS_2_DATA_CC(a_pDevIns, a_PtrType) ( (a_PtrType)(void *)&(a_pDevIns)->achInstanceData[0] )
6514	#endif
6515
6516
6517	#ifdef IN_RING3
6518
6519	/**
6520	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap().
6521	*/
6522	DECLINLINE(int) PDMDevHlpIoPortCreateAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6523	PFNIOMIOPORTNEWIN pfnIn, const char *pszDesc, PCIOMIOPORTDESC paExtDescs,
6524	PIOMIOPORTHANDLE phIoPorts)
6525	{
6526	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6527	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6528	if (RT_SUCCESS(rc))
6529	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6530	return rc;
6531	}
6532
6533	/**
6534	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with pvUser.
6535	*/
6536	DECLINLINE(int) PDMDevHlpIoPortCreateUAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6537	PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
6538	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6539	{
6540	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6541	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6542	if (RT_SUCCESS(rc))
6543	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6544	return rc;
6545	}
6546
6547	/**
6548	* Combines PDMDevHlpIoPortCreate() & PDMDevHlpIoPortMap(), but with flags.
6549	*/
6550	DECLINLINE(int) PDMDevHlpIoPortCreateFlagsAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6551	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6552	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6553	{
6554	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6555	pfnOut, pfnIn, NULL, NULL, NULL, pszDesc, paExtDescs, phIoPorts);
6556	if (RT_SUCCESS(rc))
6557	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6558	return rc;
6559	}
6560
6561	/**
6562	* Combines PDMDevHlpIoPortCreateEx() & PDMDevHlpIoPortMap().
6563	*/
6564	DECLINLINE(int) PDMDevHlpIoPortCreateExAndMap(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, uint32_t fFlags,
6565	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6566	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6567	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6568	{
6569	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, NULL, UINT32_MAX,
6570	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6571	if (RT_SUCCESS(rc))
6572	rc = pDevIns->pHlpR3->pfnIoPortMap(pDevIns, *phIoPorts, Port);
6573	return rc;
6574	}
6575
6576	/**
6577	* @sa PDMDevHlpIoPortCreateEx
6578	*/
6579	DECLINLINE(int) PDMDevHlpIoPortCreate(PPDMDEVINS pDevIns, RTIOPORT cPorts, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6580	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6581	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6582	{
6583	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, pPciDev, iPciRegion,
6584	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6585	}
6586
6587
6588	/**
6589	* @sa PDMDevHlpIoPortCreateEx
6590	*/
6591	DECLINLINE(int) PDMDevHlpIoPortCreateIsa(PPDMDEVINS pDevIns, RTIOPORT cPorts, PFNIOMIOPORTNEWOUT pfnOut,
6592	PFNIOMIOPORTNEWIN pfnIn, void pvUser, const char pszDesc,
6593	PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6594	{
6595	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0, NULL, UINT32_MAX,
6596	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
6597	}
6598
6599	/**
6600	* @copydoc PDMDEVHLPR3::pfnIoPortCreateEx
6601	*/
6602	DECLINLINE(int) PDMDevHlpIoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
6603	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6604	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser,
6605	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
6606	{
6607	return pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, fFlags, pPciDev, iPciRegion,
6608	pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser, pszDesc, paExtDescs, phIoPorts);
6609	}
6610
6611	/**
6612	* @copydoc PDMDEVHLPR3::pfnIoPortMap
6613	*/
6614	DECLINLINE(int) PDMDevHlpIoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port)
6615	{
6616	return pDevIns->pHlpR3->pfnIoPortMap(pDevIns, hIoPorts, Port);
6617	}
6618
6619	/**
6620	* @copydoc PDMDEVHLPR3::pfnIoPortUnmap
6621	*/
6622	DECLINLINE(int) PDMDevHlpIoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6623	{
6624	return pDevIns->pHlpR3->pfnIoPortUnmap(pDevIns, hIoPorts);
6625	}
6626
6627	/**
6628	* @copydoc PDMDEVHLPR3::pfnIoPortGetMappingAddress
6629	*/
6630	DECLINLINE(uint32_t) PDMDevHlpIoPortGetMappingAddress(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
6631	{
6632	return pDevIns->pHlpR3->pfnIoPortGetMappingAddress(pDevIns, hIoPorts);
6633	}
6634
6635	/**
6636	* @copydoc PDMDEVHLPR3::pfnIoPortRead
6637	*/
6638	DECLINLINE(VBOXSTRICTRC) PDMDevHlpIoPortRead(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)
6639	{
6640	return pDevIns->pHlpR3->pfnIoPortRead(pDevIns, Port, pu32Value, cbValue);
6641	}
6642
6643	/**
6644	* @copydoc PDMDEVHLPR3::pfnIoPortWrite
6645	*/
6646	DECLINLINE(VBOXSTRICTRC) PDMDevHlpIoPortWrite(PPDMDEVINS pDevIns, RTIOPORT Port, uint32_t u32Value, size_t cbValue)
6647	{
6648	return pDevIns->pHlpR3->pfnIoPortWrite(pDevIns, Port, u32Value, cbValue);
6649	}
6650
6651
6652	#endif /* IN_RING3 */
6653	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6654
6655	/**
6656	* @sa PDMDevHlpIoPortSetUpContextEx
6657	*/
6658	DECLINLINE(int) PDMDevHlpIoPortSetUpContext(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6659	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser)
6660	{
6661	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, NULL, NULL, pvUser);
6662	}
6663
6664	/**
6665	* @copydoc PDMDEVHLPR0::pfnIoPortSetUpContextEx
6666	*/
6667	DECLINLINE(int) PDMDevHlpIoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
6668	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
6669	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, void *pvUser)
6670	{
6671	return pDevIns->CTX_SUFF(pHlp)->pfnIoPortSetUpContextEx(pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
6672	}
6673
6674	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6675	#ifdef IN_RING3
6676
6677	/**
6678	* @sa PDMDevHlpMmioCreateEx
6679	*/
6680	DECLINLINE(int) PDMDevHlpMmioCreate(PPDMDEVINS pDevIns, RTGCPHYS cbRegion, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6681	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
6682	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6683	{
6684	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6685	pfnWrite, pfnRead, NULL, pvUser, pszDesc, phRegion);
6686	}
6687
6688	/**
6689	* @copydoc PDMDEVHLPR3::pfnMmioCreateEx
6690	*/
6691	DECLINLINE(int) PDMDevHlpMmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
6692	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
6693	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
6694	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
6695	{
6696	return pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6697	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6698	}
6699
6700	/**
6701	* @sa PDMDevHlpMmioCreate and PDMDevHlpMmioMap
6702	*/
6703	DECLINLINE(int) PDMDevHlpMmioCreateAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion,
6704	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
6705	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
6706	{
6707	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6708	pfnWrite, pfnRead, NULL /pfnFill/, NULL /pvUser/, pszDesc, phRegion);
6709	if (RT_SUCCESS(rc))
6710	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6711	return rc;
6712	}
6713
6714	/**
6715	* @sa PDMDevHlpMmioCreateEx and PDMDevHlpMmioMap
6716	*/
6717	DECLINLINE(int) PDMDevHlpMmioCreateExAndMap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cbRegion, uint32_t fFlags,
6718	PPDMPCIDEV pPciDev, uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite,
6719	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser,
6720	const char *pszDesc, PIOMMMIOHANDLE phRegion)
6721	{
6722	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pPciDev, iPciRegion,
6723	pfnWrite, pfnRead, pfnFill, pvUser, pszDesc, phRegion);
6724	if (RT_SUCCESS(rc))
6725	rc = pDevIns->pHlpR3->pfnMmioMap(pDevIns, *phRegion, GCPhys);
6726	return rc;
6727	}
6728
6729	/**
6730	* @copydoc PDMDEVHLPR3::pfnMmioMap
6731	*/
6732	DECLINLINE(int) PDMDevHlpMmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
6733	{
6734	return pDevIns->pHlpR3->pfnMmioMap(pDevIns, hRegion, GCPhys);
6735	}
6736
6737	/**
6738	* @copydoc PDMDEVHLPR3::pfnMmioUnmap
6739	*/
6740	DECLINLINE(int) PDMDevHlpMmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6741	{
6742	return pDevIns->pHlpR3->pfnMmioUnmap(pDevIns, hRegion);
6743	}
6744
6745	/**
6746	* @copydoc PDMDEVHLPR3::pfnMmioReduce
6747	*/
6748	DECLINLINE(int) PDMDevHlpMmioReduce(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
6749	{
6750	return pDevIns->pHlpR3->pfnMmioReduce(pDevIns, hRegion, cbRegion);
6751	}
6752
6753	/**
6754	* @copydoc PDMDEVHLPR3::pfnMmioGetMappingAddress
6755	*/
6756	DECLINLINE(RTGCPHYS) PDMDevHlpMmioGetMappingAddress(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6757	{
6758	return pDevIns->pHlpR3->pfnMmioGetMappingAddress(pDevIns, hRegion);
6759	}
6760
6761	#endif /* IN_RING3 */
6762	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6763
6764	/**
6765	* @sa PDMDevHlpMmioSetUpContextEx
6766	*/
6767	DECLINLINE(int) PDMDevHlpMmioSetUpContext(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion,
6768	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser)
6769	{
6770	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, NULL, pvUser);
6771	}
6772
6773	/**
6774	* @copydoc PDMDEVHLPR0::pfnMmioSetUpContextEx
6775	*/
6776	DECLINLINE(int) PDMDevHlpMmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
6777	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
6778	{
6779	return pDevIns->CTX_SUFF(pHlp)->pfnMmioSetUpContextEx(pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
6780	}
6781
6782	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6783	#ifdef IN_RING3
6784
6785	/**
6786	* @copydoc PDMDEVHLPR3::pfnMmio2Create
6787	*/
6788	DECLINLINE(int) PDMDevHlpMmio2Create(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iPciRegion, RTGCPHYS cbRegion,
6789	uint32_t fFlags, const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
6790	{
6791	return pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pPciDev, iPciRegion, cbRegion, fFlags, pszDesc, ppvMapping, phRegion);
6792	}
6793
6794	/**
6795	* @copydoc PDMDEVHLPR3::pfnMmio2Map
6796	*/
6797	DECLINLINE(int) PDMDevHlpMmio2Map(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS GCPhys)
6798	{
6799	return pDevIns->pHlpR3->pfnMmio2Map(pDevIns, hRegion, GCPhys);
6800	}
6801
6802	/**
6803	* @copydoc PDMDEVHLPR3::pfnMmio2Unmap
6804	*/
6805	DECLINLINE(int) PDMDevHlpMmio2Unmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6806	{
6807	return pDevIns->pHlpR3->pfnMmio2Unmap(pDevIns, hRegion);
6808	}
6809
6810	/**
6811	* @copydoc PDMDEVHLPR3::pfnMmio2Reduce
6812	*/
6813	DECLINLINE(int) PDMDevHlpMmio2Reduce(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, RTGCPHYS cbRegion)
6814	{
6815	return pDevIns->pHlpR3->pfnMmio2Reduce(pDevIns, hRegion, cbRegion);
6816	}
6817
6818	/**
6819	* @copydoc PDMDEVHLPR3::pfnMmio2GetMappingAddress
6820	*/
6821	DECLINLINE(RTGCPHYS) PDMDevHlpMmio2GetMappingAddress(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6822	{
6823	return pDevIns->pHlpR3->pfnMmio2GetMappingAddress(pDevIns, hRegion);
6824	}
6825
6826	/**
6827	* @copydoc PDMDEVHLPR3::pfnMmio2QueryAndResetDirtyBitmap
6828	*/
6829	DECLINLINE(int) PDMDevHlpMmio2QueryAndResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6830	void *pvBitmap, size_t cbBitmap)
6831	{
6832	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, pvBitmap, cbBitmap);
6833	}
6834
6835	/**
6836	* Reset the dirty bitmap tracking for an MMIO2 region.
6837	*
6838	* The MMIO2 region must have been created with the
6839	* PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES flag for this to work.
6840	*
6841	* @returns VBox status code.
6842	* @param pDevIns The device instance.
6843	* @param hRegion The MMIO2 region handle.
6844	*/
6845	DECLINLINE(int) PDMDevHlpMmio2ResetDirtyBitmap(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion)
6846	{
6847	return pDevIns->pHlpR3->pfnMmio2QueryAndResetDirtyBitmap(pDevIns, hRegion, NULL, 0);
6848	}
6849
6850	/**
6851	* @copydoc PDMDEVHLPR3::pfnMmio2ControlDirtyPageTracking
6852	*/
6853	DECLINLINE(int) PDMDevHlpMmio2ControlDirtyPageTracking(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion, bool fEnabled)
6854	{
6855	return pDevIns->pHlpR3->pfnMmio2ControlDirtyPageTracking(pDevIns, hRegion, fEnabled);
6856	}
6857
6858	#endif /* IN_RING3 */
6859
6860	/**
6861	* @copydoc PDMDEVHLPR3::pfnMmioMapMmio2Page
6862	*/
6863	DECLINLINE(int) PDMDevHlpMmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
6864	uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
6865	{
6866	return pDevIns->CTX_SUFF(pHlp)->pfnMmioMapMmio2Page(pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
6867	}
6868
6869	/**
6870	* @copydoc PDMDEVHLPR3::pfnMmioResetRegion
6871	*/
6872	DECLINLINE(int) PDMDevHlpMmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
6873	{
6874	return pDevIns->CTX_SUFF(pHlp)->pfnMmioResetRegion(pDevIns, hRegion);
6875	}
6876
6877	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
6878
6879	/**
6880	* @copydoc PDMDEVHLPR0::pfnMmio2SetUpContext
6881	*/
6882	DECLINLINE(int) PDMDevHlpMmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
6883	size_t offSub, size_t cbSub, void **ppvMapping)
6884	{
6885	return pDevIns->CTX_SUFF(pHlp)->pfnMmio2SetUpContext(pDevIns, hRegion, offSub, cbSub, ppvMapping);
6886	}
6887
6888	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
6889	#ifdef IN_RING3
6890
6891	/**
6892	* @copydoc PDMDEVHLPR3::pfnROMRegister
6893	*/
6894	DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
6895	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
6896	{
6897	return pDevIns->pHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
6898	}
6899
6900	/**
6901	* @copydoc PDMDEVHLPR3::pfnROMProtectShadow
6902	*/
6903	DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
6904	{
6905	return pDevIns->pHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange, enmProt);
6906	}
6907
6908	/**
6909	* Register a save state data unit.
6910	*
6911	* @returns VBox status.
6912	* @param pDevIns The device instance.
6913	* @param uVersion Data layout version number.
6914	* @param cbGuess The approximate amount of data in the unit.
6915	* Only for progress indicators.
6916	* @param pfnSaveExec Execute save callback, optional.
6917	* @param pfnLoadExec Execute load callback, optional.
6918	*/
6919	DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6920	PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6921	{
6922	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6923	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveDone/,
6924	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6925	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6926	}
6927
6928	/**
6929	* Register a save state data unit with a live save callback as well.
6930	*
6931	* @returns VBox status.
6932	* @param pDevIns The device instance.
6933	* @param uVersion Data layout version number.
6934	* @param cbGuess The approximate amount of data in the unit.
6935	* Only for progress indicators.
6936	* @param pfnLiveExec Execute live callback, optional.
6937	* @param pfnSaveExec Execute save callback, optional.
6938	* @param pfnLoadExec Execute load callback, optional.
6939	*/
6940	DECLINLINE(int) PDMDevHlpSSMRegister3(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess,
6941	PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVLOADEXEC pfnLoadExec)
6942	{
6943	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, NULL /pszBefore/,
6944	NULL /pfnLivePrep/, pfnLiveExec, NULL /pfnLiveDone/,
6945	NULL /pfnSavePrep/, pfnSaveExec, NULL /pfnSaveDone/,
6946	NULL /pfnLoadPrep/, pfnLoadExec, NULL /pfnLoadDone/);
6947	}
6948
6949	/**
6950	* @copydoc PDMDEVHLPR3::pfnSSMRegister
6951	*/
6952	DECLINLINE(int) PDMDevHlpSSMRegisterEx(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
6953	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
6954	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
6955	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6956	{
6957	return pDevIns->pHlpR3->pfnSSMRegister(pDevIns, uVersion, cbGuess, pszBefore,
6958	pfnLivePrep, pfnLiveExec, pfnLiveVote,
6959	pfnSavePrep, pfnSaveExec, pfnSaveDone,
6960	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6961	}
6962
6963	/**
6964	* @copydoc PDMDEVHLPR3::pfnSSMRegisterLegacy
6965	*/
6966	DECLINLINE(int) PDMDevHlpSSMRegisterLegacy(PPDMDEVINS pDevIns, const char *pszOldName, PFNSSMDEVLOADPREP pfnLoadPrep,
6967	PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
6968	{
6969	return pDevIns->pHlpR3->pfnSSMRegisterLegacy(pDevIns, pszOldName, pfnLoadPrep, pfnLoadExec, pfnLoadDone);
6970	}
6971
6972	/**
6973	* @copydoc PDMDEVHLPR3::pfnTimerCreate
6974	*/
6975	DECLINLINE(int) PDMDevHlpTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser,
6976	uint32_t fFlags, const char *pszDesc, PTMTIMERHANDLE phTimer)
6977	{
6978	return pDevIns->pHlpR3->pfnTimerCreate(pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, phTimer);
6979	}
6980
6981	#endif /* IN_RING3 */
6982
6983	/**
6984	* @copydoc PDMDEVHLPR3::pfnTimerFromMicro
6985	*/
6986	DECLINLINE(uint64_t) PDMDevHlpTimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
6987	{
6988	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMicro(pDevIns, hTimer, cMicroSecs);
6989	}
6990
6991	/**
6992	* @copydoc PDMDEVHLPR3::pfnTimerFromMilli
6993	*/
6994	DECLINLINE(uint64_t) PDMDevHlpTimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
6995	{
6996	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromMilli(pDevIns, hTimer, cMilliSecs);
6997	}
6998
6999	/**
7000	* @copydoc PDMDEVHLPR3::pfnTimerFromNano
7001	*/
7002	DECLINLINE(uint64_t) PDMDevHlpTimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
7003	{
7004	return pDevIns->CTX_SUFF(pHlp)->pfnTimerFromNano(pDevIns, hTimer, cNanoSecs);
7005	}
7006
7007	/**
7008	* @copydoc PDMDEVHLPR3::pfnTimerGet
7009	*/
7010	DECLINLINE(uint64_t) PDMDevHlpTimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7011	{
7012	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGet(pDevIns, hTimer);
7013	}
7014
7015	/**
7016	* @copydoc PDMDEVHLPR3::pfnTimerGetFreq
7017	*/
7018	DECLINLINE(uint64_t) PDMDevHlpTimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7019	{
7020	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetFreq(pDevIns, hTimer);
7021	}
7022
7023	/**
7024	* @copydoc PDMDEVHLPR3::pfnTimerGetNano
7025	*/
7026	DECLINLINE(uint64_t) PDMDevHlpTimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7027	{
7028	return pDevIns->CTX_SUFF(pHlp)->pfnTimerGetNano(pDevIns, hTimer);
7029	}
7030
7031	/**
7032	* @copydoc PDMDEVHLPR3::pfnTimerIsActive
7033	*/
7034	DECLINLINE(bool) PDMDevHlpTimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7035	{
7036	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsActive(pDevIns, hTimer);
7037	}
7038
7039	/**
7040	* @copydoc PDMDEVHLPR3::pfnTimerIsLockOwner
7041	*/
7042	DECLINLINE(bool) PDMDevHlpTimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7043	{
7044	return pDevIns->CTX_SUFF(pHlp)->pfnTimerIsLockOwner(pDevIns, hTimer);
7045	}
7046
7047	/**
7048	* @copydoc PDMDEVHLPR3::pfnTimerLockClock
7049	*/
7050	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
7051	{
7052	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock(pDevIns, hTimer, rcBusy);
7053	}
7054
7055	/**
7056	* @copydoc PDMDEVHLPR3::pfnTimerLockClock2
7057	*/
7058	DECLINLINE(VBOXSTRICTRC) PDMDevHlpTimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect, int rcBusy)
7059	{
7060	return pDevIns->CTX_SUFF(pHlp)->pfnTimerLockClock2(pDevIns, hTimer, pCritSect, rcBusy);
7061	}
7062
7063	/**
7064	* @copydoc PDMDEVHLPR3::pfnTimerSet
7065	*/
7066	DECLINLINE(int) PDMDevHlpTimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
7067	{
7068	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSet(pDevIns, hTimer, uExpire);
7069	}
7070
7071	/**
7072	* @copydoc PDMDEVHLPR3::pfnTimerSetFrequencyHint
7073	*/
7074	DECLINLINE(int) PDMDevHlpTimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
7075	{
7076	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetFrequencyHint(pDevIns, hTimer, uHz);
7077	}
7078
7079	/**
7080	* @copydoc PDMDEVHLPR3::pfnTimerSetMicro
7081	*/
7082	DECLINLINE(int) PDMDevHlpTimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
7083	{
7084	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMicro(pDevIns, hTimer, cMicrosToNext);
7085	}
7086
7087	/**
7088	* @copydoc PDMDEVHLPR3::pfnTimerSetMillies
7089	*/
7090	DECLINLINE(int) PDMDevHlpTimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
7091	{
7092	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetMillies(pDevIns, hTimer, cMilliesToNext);
7093	}
7094
7095	/**
7096	* @copydoc PDMDEVHLPR3::pfnTimerSetNano
7097	*/
7098	DECLINLINE(int) PDMDevHlpTimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
7099	{
7100	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetNano(pDevIns, hTimer, cNanosToNext);
7101	}
7102
7103	/**
7104	* @copydoc PDMDEVHLPR3::pfnTimerSetRelative
7105	*/
7106	DECLINLINE(int) PDMDevHlpTimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
7107	{
7108	return pDevIns->CTX_SUFF(pHlp)->pfnTimerSetRelative(pDevIns, hTimer, cTicksToNext, pu64Now);
7109	}
7110
7111	/**
7112	* @copydoc PDMDEVHLPR3::pfnTimerStop
7113	*/
7114	DECLINLINE(int) PDMDevHlpTimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7115	{
7116	return pDevIns->CTX_SUFF(pHlp)->pfnTimerStop(pDevIns, hTimer);
7117	}
7118
7119	/**
7120	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock
7121	*/
7122	DECLINLINE(void) PDMDevHlpTimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7123	{
7124	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock(pDevIns, hTimer);
7125	}
7126
7127	/**
7128	* @copydoc PDMDEVHLPR3::pfnTimerUnlockClock2
7129	*/
7130	DECLINLINE(void) PDMDevHlpTimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7131	{
7132	pDevIns->CTX_SUFF(pHlp)->pfnTimerUnlockClock2(pDevIns, hTimer, pCritSect);
7133	}
7134
7135	#ifdef IN_RING3
7136
7137	/**
7138	* @copydoc PDMDEVHLPR3::pfnTimerSetCritSect
7139	*/
7140	DECLINLINE(int) PDMDevHlpTimerSetCritSect(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
7141	{
7142	return pDevIns->pHlpR3->pfnTimerSetCritSect(pDevIns, hTimer, pCritSect);
7143	}
7144
7145	/**
7146	* @copydoc PDMDEVHLPR3::pfnTimerSave
7147	*/
7148	DECLINLINE(int) PDMDevHlpTimerSave(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7149	{
7150	return pDevIns->pHlpR3->pfnTimerSave(pDevIns, hTimer, pSSM);
7151	}
7152
7153	/**
7154	* @copydoc PDMDEVHLPR3::pfnTimerLoad
7155	*/
7156	DECLINLINE(int) PDMDevHlpTimerLoad(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PSSMHANDLE pSSM)
7157	{
7158	return pDevIns->pHlpR3->pfnTimerLoad(pDevIns, hTimer, pSSM);
7159	}
7160
7161	/**
7162	* @copydoc PDMDEVHLPR3::pfnTimerDestroy
7163	*/
7164	DECLINLINE(int) PDMDevHlpTimerDestroy(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
7165	{
7166	return pDevIns->pHlpR3->pfnTimerDestroy(pDevIns, hTimer);
7167	}
7168
7169	/**
7170	* @copydoc PDMDEVHLPR3::pfnTMUtcNow
7171	*/
7172	DECLINLINE(PRTTIMESPEC) PDMDevHlpTMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
7173	{
7174	return pDevIns->pHlpR3->pfnTMUtcNow(pDevIns, pTime);
7175	}
7176
7177	#endif
7178
7179	/**
7180	* Read physical memory - unknown data usage.
7181	*
7182	* @returns VINF_SUCCESS (for now).
7183	* @param pDevIns The device instance.
7184	* @param GCPhys Physical address start reading from.
7185	* @param pvBuf Where to put the read bits.
7186	* @param cbRead How many bytes to read.
7187	* @thread Any thread, but the call may involve the emulation thread.
7188	*/
7189	DECLINLINE(int) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7190	{
7191	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7192	}
7193
7194	/**
7195	* Write to physical memory - unknown data usage.
7196	*
7197	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7198	* @param pDevIns The device instance.
7199	* @param GCPhys Physical address to write to.
7200	* @param pvBuf What to write.
7201	* @param cbWrite How many bytes to write.
7202	* @thread Any thread, but the call may involve the emulation thread.
7203	*/
7204	DECLINLINE(int) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7205	{
7206	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
7207	}
7208
7209	/**
7210	* Read physical memory - reads meta data processed by the device.
7211	*
7212	* @returns VINF_SUCCESS (for now).
7213	* @param pDevIns The device instance.
7214	* @param GCPhys Physical address start reading from.
7215	* @param pvBuf Where to put the read bits.
7216	* @param cbRead How many bytes to read.
7217	* @thread Any thread, but the call may involve the emulation thread.
7218	*/
7219	DECLINLINE(int) PDMDevHlpPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7220	{
7221	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7222	}
7223
7224	/**
7225	* Write to physical memory - written data was created/altered by the device.
7226	*
7227	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7228	* @param pDevIns The device instance.
7229	* @param GCPhys Physical address to write to.
7230	* @param pvBuf What to write.
7231	* @param cbWrite How many bytes to write.
7232	* @thread Any thread, but the call may involve the emulation thread.
7233	*/
7234	DECLINLINE(int) PDMDevHlpPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7235	{
7236	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
7237	}
7238
7239	/**
7240	* Read physical memory - read data will not be touched by the device.
7241	*
7242	* @returns VINF_SUCCESS (for now).
7243	* @param pDevIns The device instance.
7244	* @param GCPhys Physical address start reading from.
7245	* @param pvBuf Where to put the read bits.
7246	* @param cbRead How many bytes to read.
7247	* @thread Any thread, but the call may involve the emulation thread.
7248	*/
7249	DECLINLINE(int) PDMDevHlpPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
7250	{
7251	return pDevIns->CTX_SUFF(pHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7252	}
7253
7254	/**
7255	* Write to physical memory - written data was not touched/created by the device.
7256	*
7257	* @returns VINF_SUCCESS for now, and later maybe VERR_EM_MEMORY.
7258	* @param pDevIns The device instance.
7259	* @param GCPhys Physical address to write to.
7260	* @param pvBuf What to write.
7261	* @param cbWrite How many bytes to write.
7262	* @thread Any thread, but the call may involve the emulation thread.
7263	*/
7264	DECLINLINE(int) PDMDevHlpPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
7265	{
7266	return pDevIns->CTX_SUFF(pHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
7267	}
7268
7269	#ifdef IN_RING3
7270
7271	/**
7272	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr
7273	*/
7274	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
7275	{
7276	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtr(pDevIns, GCPhys, fFlags, ppv, pLock);
7277	}
7278
7279	/**
7280	* @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly
7281	*/
7282	DECLINLINE(int) PDMDevHlpPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv,
7283	PPGMPAGEMAPLOCK pLock)
7284	{
7285	return pDevIns->CTX_SUFF(pHlp)->pfnPhysGCPhys2CCPtrReadOnly(pDevIns, GCPhys, fFlags, ppv, pLock);
7286	}
7287
7288	/**
7289	* @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock
7290	*/
7291	DECLINLINE(void) PDMDevHlpPhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
7292	{
7293	pDevIns->CTX_SUFF(pHlp)->pfnPhysReleasePageMappingLock(pDevIns, pLock);
7294	}
7295
7296	/**
7297	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtr
7298	*/
7299	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7300	uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks)
7301	{
7302	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtr(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7303	}
7304
7305	/**
7306	* @copydoc PDMDEVHLPR3::pfnPhysBulkGCPhys2CCPtrReadOnly
7307	*/
7308	DECLINLINE(int) PDMDevHlpPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
7309	uint32_t fFlags, void const **papvPages, PPGMPAGEMAPLOCK paLocks)
7310	{
7311	return pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkGCPhys2CCPtrReadOnly(pDevIns, cPages, paGCPhysPages, fFlags, papvPages, paLocks);
7312	}
7313
7314	/**
7315	* @copydoc PDMDEVHLPR3::pfnPhysBulkReleasePageMappingLocks
7316	*/
7317	DECLINLINE(void) PDMDevHlpPhysBulkReleasePageMappingLocks(PPDMDEVINS pDevIns, uint32_t cPages, PPGMPAGEMAPLOCK paLocks)
7318	{
7319	pDevIns->CTX_SUFF(pHlp)->pfnPhysBulkReleasePageMappingLocks(pDevIns, cPages, paLocks);
7320	}
7321
7322	/**
7323	* @copydoc PDMDEVHLPR3::pfnPhysIsGCPhysNormal
7324	*/
7325	DECLINLINE(bool) PDMDevHlpPhysIsGCPhysNormal(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
7326	{
7327	return pDevIns->CTX_SUFF(pHlp)->pfnPhysIsGCPhysNormal(pDevIns, GCPhys);
7328	}
7329
7330	/**
7331	* @copydoc PDMDEVHLPR3::pfnPhysChangeMemBalloon
7332	*/
7333	DECLINLINE(int) PDMDevHlpPhysChangeMemBalloon(PPDMDEVINS pDevIns, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage)
7334	{
7335	return pDevIns->CTX_SUFF(pHlp)->pfnPhysChangeMemBalloon(pDevIns, fInflate, cPages, paPhysPage);
7336	}
7337
7338	/**
7339	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestArch
7340	*/
7341	DECLINLINE(CPUMARCH) PDMDevHlpCpuGetGuestArch(PPDMDEVINS pDevIns)
7342	{
7343	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestArch(pDevIns);
7344	}
7345
7346	/**
7347	* Returns a flag whether the current guest CPU architecture is x86.
7348	*
7349	* @returns Flag whether the current guest architecture is x86.
7350	* @param pDevIns The device instance.
7351	*/
7352	DECLINLINE(bool) PDMDevHlpCpuIsGuestArchX86(PPDMDEVINS pDevIns)
7353	{
7354	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestArch(pDevIns) == kCpumArch_X86;
7355	}
7356
7357	/**
7358	* Returns a flag whether the current guest CPU architecture is ARM.
7359	*
7360	* @returns Flag whether the current guest architecture is ARM.
7361	* @param pDevIns The device instance.
7362	*/
7363	DECLINLINE(bool) PDMDevHlpCpuIsGuestArchArm(PPDMDEVINS pDevIns)
7364	{
7365	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestArch(pDevIns) == kCpumArch_Arm;
7366	}
7367
7368	/**
7369	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestMicroarch
7370	*/
7371	DECLINLINE(CPUMMICROARCH) PDMDevHlpCpuGetGuestMicroarch(PPDMDEVINS pDevIns)
7372	{
7373	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestMicroarch(pDevIns);
7374	}
7375
7376	/**
7377	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestScalableBusFrequency
7378	*/
7379	DECLINLINE(uint64_t) PDMDevHlpCpuGetGuestScalableBusFrequency(PPDMDEVINS pDevIns)
7380	{
7381	return pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestScalableBusFrequency(pDevIns);
7382	}
7383
7384	/**
7385	* @copydoc PDMDEVHLPR3::pfnCpuGetGuestAddrWidths
7386	*/
7387	DECLINLINE(void) PDMDevHlpCpuGetGuestAddrWidths(PPDMDEVINS pDevIns, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth)
7388	{
7389	pDevIns->CTX_SUFF(pHlp)->pfnCpuGetGuestAddrWidths(pDevIns, pcPhysAddrWidth, pcLinearAddrWidth);
7390	}
7391
7392	/**
7393	* @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt
7394	*/
7395	DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
7396	{
7397	return pDevIns->pHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);
7398	}
7399
7400	/**
7401	* @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt
7402	*/
7403	DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
7404	{
7405	return pDevIns->pHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);
7406	}
7407
7408	/**
7409	* @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys
7410	*/
7411	DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
7412	{
7413	return pDevIns->pHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);
7414	}
7415
7416	/**
7417	* @copydoc PDMDEVHLPR3::pfnMMHeapAlloc
7418	*/
7419	DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
7420	{
7421	return pDevIns->pHlpR3->pfnMMHeapAlloc(pDevIns, cb);
7422	}
7423
7424	/**
7425	* @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ
7426	*/
7427	DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
7428	{
7429	return pDevIns->pHlpR3->pfnMMHeapAllocZ(pDevIns, cb);
7430	}
7431
7432	/**
7433	* Allocating string printf.
7434	*
7435	* @returns Pointer to the string.
7436	* @param pDevIns The device instance.
7437	* @param enmTag The statistics tag.
7438	* @param pszFormat The format string.
7439	* @param ... Format arguments.
7440	*/
7441	DECLINLINE(char ) RT_IPRT_FORMAT_ATTR(2, 3) PDMDevHlpMMHeapAPrintf(PPDMDEVINS pDevIns, MMTAG enmTag, const char pszFormat, ...)
7442	{
7443	va_list va;
7444	va_start(va, pszFormat);
7445	char *psz = pDevIns->pHlpR3->pfnMMHeapAPrintfV(pDevIns, enmTag, pszFormat, va);
7446	va_end(va);
7447
7448	return psz;
7449	}
7450
7451	/**
7452	* @copydoc PDMDEVHLPR3::pfnMMHeapFree
7453	*/
7454	DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv)
7455	{
7456	pDevIns->pHlpR3->pfnMMHeapFree(pDevIns, pv);
7457	}
7458
7459	/**
7460	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSize
7461	*/
7462	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSize(PPDMDEVINS pDevIns)
7463	{
7464	return pDevIns->pHlpR3->pfnMMPhysGetRamSize(pDevIns);
7465	}
7466
7467	/**
7468	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeBelow4GB
7469	*/
7470	DECLINLINE(uint32_t) PDMDevHlpMMPhysGetRamSizeBelow4GB(PPDMDEVINS pDevIns)
7471	{
7472	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeBelow4GB(pDevIns);
7473	}
7474
7475	/**
7476	* @copydoc PDMDEVHLPR3::pfnMMPhysGetRamSizeAbove4GB
7477	*/
7478	DECLINLINE(uint64_t) PDMDevHlpMMPhysGetRamSizeAbove4GB(PPDMDEVINS pDevIns)
7479	{
7480	return pDevIns->pHlpR3->pfnMMPhysGetRamSizeAbove4GB(pDevIns);
7481	}
7482	#endif /* IN_RING3 */
7483
7484	/**
7485	* @copydoc PDMDEVHLPR3::pfnVMState
7486	*/
7487	DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns)
7488	{
7489	return pDevIns->CTX_SUFF(pHlp)->pfnVMState(pDevIns);
7490	}
7491
7492	#ifdef IN_RING3
7493
7494	/**
7495	* @copydoc PDMDEVHLPR3::pfnVMTeleportedAndNotFullyResumedYet
7496	*/
7497	DECLINLINE(bool) PDMDevHlpVMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
7498	{
7499	return pDevIns->pHlpR3->pfnVMTeleportedAndNotFullyResumedYet(pDevIns);
7500	}
7501
7502	/**
7503	* Set the VM error message
7504	*
7505	* @returns rc.
7506	* @param pDevIns The device instance.
7507	* @param rc VBox status code.
7508	* @param SRC_POS Use RT_SRC_POS.
7509	* @param pszFormat Error message format string.
7510	* @param ... Error message arguments.
7511	* @sa VMSetError
7512	*/
7513	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL,
7514	const char *pszFormat, ...)
7515	{
7516	va_list va;
7517	va_start(va, pszFormat);
7518	pDevIns->CTX_SUFF(pHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va);
7519	va_end(va);
7520	return rc;
7521	}
7522
7523	/**
7524	* Set the VM runtime error message
7525	*
7526	* @returns VBox status code.
7527	* @param pDevIns The device instance.
7528	* @param fFlags The action flags. See VMSETRTERR_FLAGS_*.
7529	* @param pszErrorId Error ID string.
7530	* @param pszFormat Error message format string.
7531	* @param ... Error message arguments.
7532	* @sa VMSetRuntimeError
7533	*/
7534	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId,
7535	const char *pszFormat, ...)
7536	{
7537	va_list va;
7538	int rc;
7539	va_start(va, pszFormat);
7540	rc = pDevIns->CTX_SUFF(pHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFlags, pszErrorId, pszFormat, va);
7541	va_end(va);
7542	return rc;
7543	}
7544
7545	/**
7546	* @copydoc PDMDEVHLPR3::pfnVMWaitForDeviceReady
7547	*/
7548	DECLINLINE(int) PDMDevHlpVMWaitForDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7549	{
7550	return pDevIns->CTX_SUFF(pHlp)->pfnVMWaitForDeviceReady(pDevIns, idCpu);
7551	}
7552
7553	/**
7554	* @copydoc PDMDEVHLPR3::pfnVMNotifyCpuDeviceReady
7555	*/
7556	DECLINLINE(int) PDMDevHlpVMNotifyCpuDeviceReady(PPDMDEVINS pDevIns, VMCPUID idCpu)
7557	{
7558	return pDevIns->CTX_SUFF(pHlp)->pfnVMNotifyCpuDeviceReady(pDevIns, idCpu);
7559	}
7560
7561	/**
7562	* Convenience wrapper for VMR3ReqCallU.
7563	*
7564	* This assumes (1) you're calling a function that returns an VBox status code
7565	* and that you do not wish to wait for it to complete.
7566	*
7567	* @returns VBox status code returned by VMR3ReqCallVU.
7568	*
7569	* @param pDevIns The device instance.
7570	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7571	* one of the following special values:
7572	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7573	* @param pfnFunction Pointer to the function to call.
7574	* @param cArgs Number of arguments following in the ellipsis.
7575	* @param ... Argument list.
7576	*
7577	* @remarks See remarks on VMR3ReqCallVU.
7578	*/
7579	DECLINLINE(int) RT_IPRT_CALLREQ_ATTR(3, 4, 5)
7580	PDMDevHlpVMReqCallNoWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7581	{
7582	va_list Args;
7583	va_start(Args, cArgs);
7584	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqCallNoWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7585	va_end(Args);
7586	return rc;
7587	}
7588
7589	/**
7590	* Convenience wrapper for VMR3ReqCallU.
7591	*
7592	* This assumes (1) you're calling a function that returns void, (2) that you
7593	* wish to wait for ever for it to return, and (3) that it's priority request
7594	* that can be safely be handled during async suspend and power off.
7595	*
7596	* @returns VBox status code of VMR3ReqCallVU.
7597	*
7598	* @param pDevIns The device instance.
7599	* @param idDstCpu The destination CPU(s). Either a specific CPU ID or
7600	* one of the following special values:
7601	* VMCPUID_ANY, VMCPUID_ANY_QUEUE, VMCPUID_ALL or VMCPUID_ALL_REVERSE.
7602	* @param pfnFunction Pointer to the function to call.
7603	* @param cArgs Number of arguments following in the ellipsis.
7604	* @param ... Argument list.
7605	*
7606	* @remarks See remarks on VMR3ReqCallVU.
7607	*/
7608	DECLINLINE(int) RT_IPRT_CALLREQ_ATTR(3, 4, 5)
7609	PDMDevHlpVMReqPriorityCallWait(PPDMDEVINS pDevIns, VMCPUID idDstCpu, PFNRT pfnFunction, unsigned cArgs, ...)
7610	{
7611	va_list Args;
7612	va_start(Args, cArgs);
7613	int rc = pDevIns->CTX_SUFF(pHlp)->pfnVMReqPriorityCallWaitV(pDevIns, idDstCpu, pfnFunction, cArgs, Args);
7614	va_end(Args);
7615	return rc;
7616	}
7617
7618	#endif /* IN_RING3 */
7619
7620	/**
7621	* VBOX_STRICT wrapper for pHlp->pfnDBGFStopV.
7622	*
7623	* @returns VBox status code which must be passed up to the VMM. This will be
7624	* VINF_SUCCESS in non-strict builds.
7625	* @param pDevIns The device instance.
7626	* @param SRC_POS Use RT_SRC_POS.
7627	* @param pszFormat Message. (optional)
7628	* @param ... Message parameters.
7629	*/
7630	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(5, 6) PDMDevHlpDBGFStop(PPDMDEVINS pDevIns, RT_SRC_POS_DECL, const char *pszFormat, ...)
7631	{
7632	#ifdef VBOX_STRICT
7633	# ifdef IN_RING3
7634	int rc;
7635	va_list args;
7636	va_start(args, pszFormat);
7637	rc = pDevIns->pHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);
7638	va_end(args);
7639	return rc;
7640	# else
7641	NOREF(pDevIns);
7642	NOREF(pszFile);
7643	NOREF(iLine);
7644	NOREF(pszFunction);
7645	NOREF(pszFormat);
7646	return VINF_EM_DBG_STOP;
7647	# endif
7648	#else
7649	NOREF(pDevIns);
7650	NOREF(pszFile);
7651	NOREF(iLine);
7652	NOREF(pszFunction);
7653	NOREF(pszFormat);
7654	return VINF_SUCCESS;
7655	#endif
7656	}
7657
7658	#ifdef IN_RING3
7659
7660	/**
7661	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister
7662	*/
7663	DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
7664	{
7665	return pDevIns->pHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);
7666	}
7667
7668	/**
7669	* @copydoc PDMDEVHLPR3::pfnDBGFInfoRegisterArgv
7670	*/
7671	DECLINLINE(int) PDMDevHlpDBGFInfoRegisterArgv(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFINFOARGVDEV pfnHandler)
7672	{
7673	return pDevIns->pHlpR3->pfnDBGFInfoRegisterArgv(pDevIns, pszName, pszDesc, pfnHandler);
7674	}
7675
7676	/**
7677	* @copydoc PDMDEVHLPR3::pfnDBGFRegRegister
7678	*/
7679	DECLINLINE(int) PDMDevHlpDBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
7680	{
7681	return pDevIns->pHlpR3->pfnDBGFRegRegister(pDevIns, paRegisters);
7682	}
7683
7684	/**
7685	* @copydoc PDMDEVHLPR3::pfnDBGFReportBugCheck
7686	*/
7687	DECLINLINE(VBOXSTRICTRC) PDMDevHlpDBGFReportBugCheck(PPDMDEVINS pDevIns, DBGFEVENTTYPE enmEvent, uint64_t uBugCheck,
7688	uint64_t uP1, uint64_t uP2, uint64_t uP3, uint64_t uP4)
7689	{
7690	return pDevIns->pHlpR3->pfnDBGFReportBugCheck(pDevIns, enmEvent, uBugCheck, uP1, uP2, uP3, uP4);
7691	}
7692
7693	/**
7694	* @copydoc PDMDEVHLPR3::pfnDBGFCoreWrite
7695	*/
7696	DECLINLINE(int) PDMDevHlpDBGFCoreWrite(PPDMDEVINS pDevIns, const char *pszFilename, bool fReplaceFile)
7697	{
7698	return pDevIns->pHlpR3->pfnDBGFCoreWrite(pDevIns, pszFilename, fReplaceFile);
7699	}
7700
7701	/**
7702	* @copydoc PDMDEVHLPR3::pfnDBGFInfoLogHlp
7703	*/
7704	DECLINLINE(PCDBGFINFOHLP) PDMDevHlpDBGFInfoLogHlp(PPDMDEVINS pDevIns)
7705	{
7706	return pDevIns->pHlpR3->pfnDBGFInfoLogHlp(pDevIns);
7707	}
7708
7709	/**
7710	* @copydoc PDMDEVHLPR3::pfnDBGFRegNmQueryU64
7711	*/
7712	DECLINLINE(int) PDMDevHlpDBGFRegNmQueryU64(PPDMDEVINS pDevIns, VMCPUID idDefCpu, const char pszReg, uint64_t pu64)
7713	{
7714	return pDevIns->pHlpR3->pfnDBGFRegNmQueryU64(pDevIns, idDefCpu, pszReg, pu64);
7715	}
7716
7717	/**
7718	* Format a set of registers.
7719	*
7720	* This is restricted to registers from one CPU, that specified by @a idCpu.
7721	*
7722	* @returns VBox status code.
7723	* @param pDevIns The device instance.
7724	* @param idCpu The CPU ID of any CPU registers that may be
7725	* printed, pass VMCPUID_ANY if not applicable.
7726	* @param pszBuf The output buffer.
7727	* @param cbBuf The size of the output buffer.
7728	* @param pszFormat The format string. Register names are given by
7729	* %VR{name}, they take no arguments.
7730	* @param ... Argument list.
7731	*/
7732	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(4, 5) PDMDevHlpDBGFRegPrintf(PPDMDEVINS pDevIns, VMCPUID idCpu, char *pszBuf, size_t cbBuf,
7733	const char *pszFormat, ...)
7734	{
7735	va_list Args;
7736	va_start(Args, pszFormat);
7737	int rc = pDevIns->pHlpR3->pfnDBGFRegPrintfV(pDevIns, idCpu, pszBuf, cbBuf, pszFormat, Args);
7738	va_end(Args);
7739	return rc;
7740	}
7741
7742	/**
7743	* @copydoc PDMDEVHLPR3::pfnSTAMRegister
7744	*/
7745	DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
7746	{
7747	pDevIns->pHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
7748	}
7749
7750	/**
7751	* Same as pfnSTAMRegister except that the name is specified in a
7752	* RTStrPrintf like fashion.
7753	*
7754	* @param pDevIns Device instance of the DMA.
7755	* @param pvSample Pointer to the sample.
7756	* @param enmType Sample type. This indicates what pvSample is
7757	* pointing at.
7758	* @param enmVisibility Visibility type specifying whether unused
7759	* statistics should be visible or not.
7760	* @param enmUnit Sample unit.
7761	* @param pszDesc Sample description.
7762	* @param pszName Sample name format string, unix path style. If
7763	* this does not start with a '/', the default
7764	* prefix will be prepended, otherwise it will be
7765	* used as-is.
7766	* @param ... Arguments to the format string.
7767	*/
7768	DECLINLINE(void) RT_IPRT_FORMAT_ATTR(7, 8) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType,
7769	STAMVISIBILITY enmVisibility, STAMUNIT enmUnit,
7770	const char pszDesc, const char pszName, ...)
7771	{
7772	va_list va;
7773	va_start(va, pszName);
7774	pDevIns->pHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);
7775	va_end(va);
7776	}
7777
7778	/**
7779	* @copydoc PDMDEVHLPR3::pfnSTAMDeregisterByPrefix
7780	*/
7781	DECLINLINE(int) PDMDevHlpSTAMDeregisterByPrefix(PPDMDEVINS pDevIns, const char *pszPrefix)
7782	{
7783	return pDevIns->pHlpR3->pfnSTAMDeregisterByPrefix(pDevIns, pszPrefix);
7784	}
7785
7786	/**
7787	* Registers the device with the default PCI bus.
7788	*
7789	* @returns VBox status code.
7790	* @param pDevIns The device instance.
7791	* @param pPciDev The PCI device structure.
7792	* This must be kept in the instance data.
7793	* The PCI configuration must be initialized before registration.
7794	*/
7795	DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev)
7796	{
7797	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, 0 /fFlags/,
7798	PDMPCIDEVREG_DEV_NO_FIRST_UNUSED, PDMPCIDEVREG_FUN_NO_FIRST_UNUSED, NULL);
7799	}
7800
7801	/**
7802	* @copydoc PDMDEVHLPR3::pfnPCIRegister
7803	*/
7804	DECLINLINE(int) PDMDevHlpPCIRegisterEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
7805	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
7806	{
7807	return pDevIns->pHlpR3->pfnPCIRegister(pDevIns, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
7808	}
7809
7810	/**
7811	* Initialize MSI emulation support for the first PCI device.
7812	*
7813	* @returns VBox status code.
7814	* @param pDevIns The device instance.
7815	* @param pMsiReg MSI emulation registration structure.
7816	*/
7817	DECLINLINE(int) PDMDevHlpPCIRegisterMsi(PPDMDEVINS pDevIns, PPDMMSIREG pMsiReg)
7818	{
7819	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, NULL, pMsiReg);
7820	}
7821
7822	/**
7823	* @copydoc PDMDEVHLPR3::pfnPCIRegisterMsi
7824	*/
7825	DECLINLINE(int) PDMDevHlpPCIRegisterMsiEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
7826	{
7827	return pDevIns->pHlpR3->pfnPCIRegisterMsi(pDevIns, pPciDev, pMsiReg);
7828	}
7829
7830	/**
7831	* Registers a I/O port region for the default PCI device.
7832	*
7833	* @returns VBox status code.
7834	* @param pDevIns The device instance.
7835	* @param iRegion The region number.
7836	* @param cbRegion Size of the region.
7837	* @param hIoPorts Handle to the I/O port region.
7838	*/
7839	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIo(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, IOMIOPORTHANDLE hIoPorts)
7840	{
7841	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7842	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE, hIoPorts, NULL);
7843	}
7844
7845	/**
7846	* Registers a I/O port region for the default PCI device, custom map/unmap.
7847	*
7848	* @returns VBox status code.
7849	* @param pDevIns The device instance.
7850	* @param iRegion The region number.
7851	* @param cbRegion Size of the region.
7852	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7853	* callback will be invoked holding only the PDM lock.
7854	* The device lock will _not_ be taken (due to lock
7855	* order).
7856	*/
7857	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterIoCustom(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7858	PFNPCIIOREGIONMAP pfnMapUnmap)
7859	{
7860	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, PCI_ADDRESS_SPACE_IO,
7861	PDMPCIDEV_IORGN_F_NO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7862	UINT64_MAX, pfnMapUnmap);
7863	}
7864
7865	/**
7866	* Combines PDMDevHlpIoPortCreate and PDMDevHlpPCIIORegionRegisterIo, creating
7867	* and registering an I/O port region for the default PCI device.
7868	*
7869	* @returns VBox status code.
7870	* @param pDevIns The device instance to register the ports with.
7871	* @param cPorts The count of I/O ports in the region (the size).
7872	* @param iPciRegion The PCI device region.
7873	* @param pfnOut Pointer to function which is gonna handle OUT
7874	* operations. Optional.
7875	* @param pfnIn Pointer to function which is gonna handle IN operations.
7876	* Optional.
7877	* @param pvUser User argument to pass to the callbacks.
7878	* @param pszDesc Pointer to description string. This must not be freed.
7879	* @param paExtDescs Extended per-port descriptions, optional. Partial range
7880	* coverage is allowed. This must not be freed.
7881	* @param phIoPorts Where to return the I/O port range handle.
7882	*
7883	*/
7884	DECLINLINE(int) PDMDevHlpPCIIORegionCreateIo(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTIOPORT cPorts,
7885	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn, void *pvUser,
7886	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
7887
7888	{
7889	int rc = pDevIns->pHlpR3->pfnIoPortCreateEx(pDevIns, cPorts, 0 /fFlags/, pDevIns->apPciDevs[0], iPciRegion << 16,
7890	pfnOut, pfnIn, NULL, NULL, pvUser, pszDesc, paExtDescs, phIoPorts);
7891	if (RT_SUCCESS(rc))
7892	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cPorts, PCI_ADDRESS_SPACE_IO,
7893	PDMPCIDEV_IORGN_F_IOPORT_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7894	phIoPorts, NULL /pfnMapUnmap*/);
7895	return rc;
7896	}
7897
7898	/**
7899	* Registers an MMIO region for the default PCI device.
7900	*
7901	* @returns VBox status code.
7902	* @param pDevIns The device instance.
7903	* @param iRegion The region number.
7904	* @param cbRegion Size of the region.
7905	* @param enmType PCI_ADDRESS_SPACE_MEM or
7906	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7907	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7908	* @param hMmioRegion Handle to the MMIO region.
7909	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7910	* callback will be invoked holding only the PDM lock.
7911	* The device lock will _not_ be taken (due to lock
7912	* order).
7913	*/
7914	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7915	IOMMMIOHANDLE hMmioRegion, PFNPCIIOREGIONMAP pfnMapUnmap)
7916	{
7917	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
7918	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7919	hMmioRegion, pfnMapUnmap);
7920	}
7921
7922	/**
7923	* Registers an MMIO region for the default PCI device, extended version.
7924	*
7925	* @returns VBox status code.
7926	* @param pDevIns The device instance.
7927	* @param pPciDev The PCI device structure.
7928	* @param iRegion The region number.
7929	* @param cbRegion Size of the region.
7930	* @param enmType PCI_ADDRESS_SPACE_MEM or
7931	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7932	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7933	* @param hMmioRegion Handle to the MMIO region.
7934	* @param pfnMapUnmap Callback for doing the mapping, optional. The
7935	* callback will be invoked holding only the PDM lock.
7936	* The device lock will _not_ be taken (due to lock
7937	* order).
7938	*/
7939	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmioEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
7940	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, IOMMMIOHANDLE hMmioRegion,
7941	PFNPCIIOREGIONMAP pfnMapUnmap)
7942	{
7943	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pPciDev, iRegion, cbRegion, enmType,
7944	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7945	hMmioRegion, pfnMapUnmap);
7946	}
7947
7948	/**
7949	* Combines PDMDevHlpMmioCreate and PDMDevHlpPCIIORegionRegisterMmio, creating
7950	* and registering an MMIO region for the default PCI device.
7951	*
7952	* @returns VBox status code.
7953	* @param pDevIns The device instance to register the ports with.
7954	* @param cbRegion The size of the region in bytes.
7955	* @param iPciRegion The PCI device region.
7956	* @param enmType PCI_ADDRESS_SPACE_MEM or
7957	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7958	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7959	* @param fFlags Flags, IOMMMIO_FLAGS_XXX.
7960	* @param pfnWrite Pointer to function which is gonna handle Write
7961	* operations.
7962	* @param pfnRead Pointer to function which is gonna handle Read
7963	* operations.
7964	* @param pvUser User argument to pass to the callbacks.
7965	* @param pszDesc Pointer to description string. This must not be freed.
7966	* @param phRegion Where to return the MMIO region handle.
7967	*
7968	*/
7969	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion, PCIADDRESSSPACE enmType,
7970	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, void *pvUser,
7971	uint32_t fFlags, const char *pszDesc, PIOMMMIOHANDLE phRegion)
7972
7973	{
7974	int rc = pDevIns->pHlpR3->pfnMmioCreateEx(pDevIns, cbRegion, fFlags, pDevIns->apPciDevs[0], iPciRegion << 16,
7975	pfnWrite, pfnRead, NULL /pfnFill/, pvUser, pszDesc, phRegion);
7976	if (RT_SUCCESS(rc))
7977	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
7978	PDMPCIDEV_IORGN_F_MMIO_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
7979	phRegion, NULL /pfnMapUnmap*/);
7980	return rc;
7981	}
7982
7983
7984	/**
7985	* Registers an MMIO2 region for the default PCI device.
7986	*
7987	* @returns VBox status code.
7988	* @param pDevIns The device instance.
7989	* @param iRegion The region number.
7990	* @param cbRegion Size of the region.
7991	* @param enmType PCI_ADDRESS_SPACE_MEM or
7992	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
7993	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
7994	* @param hMmio2Region Handle to the MMIO2 region.
7995	*/
7996	DECLINLINE(int) PDMDevHlpPCIIORegionRegisterMmio2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cbRegion,
7997	PCIADDRESSSPACE enmType, PGMMMIO2HANDLE hMmio2Region)
7998	{
7999	return pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, NULL, iRegion, cbRegion, enmType,
8000	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8001	hMmio2Region, NULL);
8002	}
8003
8004	/**
8005	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
8006	* and registering an MMIO2 region for the default PCI device, extended edition.
8007	*
8008	* @returns VBox status code.
8009	* @param pDevIns The device instance to register the ports with.
8010	* @param cbRegion The size of the region in bytes.
8011	* @param iPciRegion The PCI device region.
8012	* @param enmType PCI_ADDRESS_SPACE_MEM or
8013	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
8014	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
8015	* @param pszDesc Pointer to description string. This must not be freed.
8016	* @param ppvMapping Where to store the address of the ring-3 mapping of
8017	* the memory.
8018	* @param phRegion Where to return the MMIO2 region handle.
8019	*
8020	*/
8021	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
8022	PCIADDRESSSPACE enmType, const char *pszDesc,
8023	void **ppvMapping, PPGMMMIO2HANDLE phRegion)
8024
8025	{
8026	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, 0 /fFlags/,
8027	pszDesc, ppvMapping, phRegion);
8028	if (RT_SUCCESS(rc))
8029	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
8030	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8031	phRegion, NULL /pfnCallback*/);
8032	return rc;
8033	}
8034
8035	/**
8036	* Combines PDMDevHlpMmio2Create and PDMDevHlpPCIIORegionRegisterMmio2, creating
8037	* and registering an MMIO2 region for the default PCI device.
8038	*
8039	* @returns VBox status code.
8040	* @param pDevIns The device instance to register the ports with.
8041	* @param cbRegion The size of the region in bytes.
8042	* @param iPciRegion The PCI device region.
8043	* @param enmType PCI_ADDRESS_SPACE_MEM or
8044	* PCI_ADDRESS_SPACE_MEM_PREFETCH, optionally or-ing in
8045	* PCI_ADDRESS_SPACE_BAR64 or PCI_ADDRESS_SPACE_BAR32.
8046	* @param fMmio2Flags PGMPHYS_MMIO2_FLAGS_XXX (see pgm.h).
8047	* @param pfnMapUnmap Callback for doing the mapping, optional. The
8048	* callback will be invoked holding only the PDM lock.
8049	* The device lock will _not_ be taken (due to lock
8050	* order).
8051	* @param pszDesc Pointer to description string. This must not be freed.
8052	* @param ppvMapping Where to store the address of the ring-3 mapping of
8053	* the memory.
8054	* @param phRegion Where to return the MMIO2 region handle.
8055	*
8056	*/
8057	DECLINLINE(int) PDMDevHlpPCIIORegionCreateMmio2Ex(PPDMDEVINS pDevIns, uint32_t iPciRegion, RTGCPHYS cbRegion,
8058	PCIADDRESSSPACE enmType, uint32_t fMmio2Flags, PFNPCIIOREGIONMAP pfnMapUnmap,
8059	const char pszDesc, void *ppvMapping, PPGMMMIO2HANDLE phRegion)
8060
8061	{
8062	int rc = pDevIns->pHlpR3->pfnMmio2Create(pDevIns, pDevIns->apPciDevs[0], iPciRegion << 16, cbRegion, fMmio2Flags,
8063	pszDesc, ppvMapping, phRegion);
8064	if (RT_SUCCESS(rc))
8065	rc = pDevIns->pHlpR3->pfnPCIIORegionRegister(pDevIns, pDevIns->apPciDevs[0], iPciRegion, cbRegion, enmType,
8066	PDMPCIDEV_IORGN_F_MMIO2_HANDLE \| PDMPCIDEV_IORGN_F_NEW_STYLE,
8067	*phRegion, pfnMapUnmap);
8068	return rc;
8069	}
8070
8071	/**
8072	* @copydoc PDMDEVHLPR3::pfnPCIInterceptConfigAccesses
8073	*/
8074	DECLINLINE(int) PDMDevHlpPCIInterceptConfigAccesses(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
8075	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite)
8076	{
8077	return pDevIns->pHlpR3->pfnPCIInterceptConfigAccesses(pDevIns, pPciDev, pfnRead, pfnWrite);
8078	}
8079
8080	/**
8081	* @copydoc PDMDEVHLPR3::pfnPCIConfigRead
8082	*/
8083	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8084	unsigned cb, uint32_t *pu32Value)
8085	{
8086	return pDevIns->pHlpR3->pfnPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
8087	}
8088
8089	/**
8090	* @copydoc PDMDEVHLPR3::pfnPCIConfigWrite
8091	*/
8092	DECLINLINE(VBOXSTRICTRC) PDMDevHlpPCIConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
8093	unsigned cb, uint32_t u32Value)
8094	{
8095	return pDevIns->pHlpR3->pfnPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
8096	}
8097
8098	#endif /* IN_RING3 */
8099
8100	/**
8101	* Bus master physical memory read from the default PCI device.
8102	*
8103	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8104	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8105	* @param pDevIns The device instance.
8106	* @param GCPhys Physical address start reading from.
8107	* @param pvBuf Where to put the read bits.
8108	* @param cbRead How many bytes to read.
8109	* @thread Any thread, but the call may involve the emulation thread.
8110	*/
8111	DECLINLINE(int) PDMDevHlpPCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8112	{
8113	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8114	}
8115
8116	/**
8117	* Bus master physical memory read - unknown data usage.
8118	*
8119	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8120	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8121	* @param pDevIns The device instance.
8122	* @param pPciDev The PCI device structure. If NULL the default
8123	* PCI device for this device instance is used.
8124	* @param GCPhys Physical address start reading from.
8125	* @param pvBuf Where to put the read bits.
8126	* @param cbRead How many bytes to read.
8127	* @thread Any thread, but the call may involve the emulation thread.
8128	*/
8129	DECLINLINE(int) PDMDevHlpPCIPhysReadEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8130	{
8131	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8132	}
8133
8134	/**
8135	* Bus master physical memory read from the default PCI device.
8136	*
8137	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8138	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8139	* @param pDevIns The device instance.
8140	* @param GCPhys Physical address start reading from.
8141	* @param pvBuf Where to put the read bits.
8142	* @param cbRead How many bytes to read.
8143	* @thread Any thread, but the call may involve the emulation thread.
8144	*/
8145	DECLINLINE(int) PDMDevHlpPCIPhysReadMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8146	{
8147	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8148	}
8149
8150	/**
8151	* Bus master physical memory read - reads meta data processed by the device.
8152	*
8153	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8154	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8155	* @param pDevIns The device instance.
8156	* @param pPciDev The PCI device structure. If NULL the default
8157	* PCI device for this device instance is used.
8158	* @param GCPhys Physical address start reading from.
8159	* @param pvBuf Where to put the read bits.
8160	* @param cbRead How many bytes to read.
8161	* @thread Any thread, but the call may involve the emulation thread.
8162	*/
8163	DECLINLINE(int) PDMDevHlpPCIPhysReadMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8164	{
8165	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8166	}
8167
8168	/**
8169	* Bus master physical memory read from the default PCI device - read data will not be touched by the device.
8170	*
8171	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8172	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8173	* @param pDevIns The device instance.
8174	* @param GCPhys Physical address start reading from.
8175	* @param pvBuf Where to put the read bits.
8176	* @param cbRead How many bytes to read.
8177	* @thread Any thread, but the call may involve the emulation thread.
8178	*/
8179	DECLINLINE(int) PDMDevHlpPCIPhysReadUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8180	{
8181	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, NULL, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8182	}
8183
8184	/**
8185	* Bus master physical memory read - read data will not be touched by the device.
8186	*
8187	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_READ_BM_DISABLED, later maybe
8188	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8189	* @param pDevIns The device instance.
8190	* @param pPciDev The PCI device structure. If NULL the default
8191	* PCI device for this device instance is used.
8192	* @param GCPhys Physical address start reading from.
8193	* @param pvBuf Where to put the read bits.
8194	* @param cbRead How many bytes to read.
8195	* @thread Any thread, but the call may involve the emulation thread.
8196	*/
8197	DECLINLINE(int) PDMDevHlpPCIPhysReadUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
8198	{
8199	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8200	}
8201
8202	/**
8203	* Bus master physical memory write from the default PCI device - unknown data usage.
8204	*
8205	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8206	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8207	* @param pDevIns The device instance.
8208	* @param GCPhys Physical address to write to.
8209	* @param pvBuf What to write.
8210	* @param cbWrite How many bytes to write.
8211	* @thread Any thread, but the call may involve the emulation thread.
8212	*/
8213	DECLINLINE(int) PDMDevHlpPCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8214	{
8215	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8216	}
8217
8218	/**
8219	* Bus master physical memory write - unknown data usage.
8220	*
8221	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8222	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8223	* @param pDevIns The device instance.
8224	* @param pPciDev The PCI device structure. If NULL the default
8225	* PCI device for this device instance is used.
8226	* @param GCPhys Physical address to write to.
8227	* @param pvBuf What to write.
8228	* @param cbWrite How many bytes to write.
8229	* @thread Any thread, but the call may involve the emulation thread.
8230	*/
8231	DECLINLINE(int) PDMDevHlpPCIPhysWriteEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8232	{
8233	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DEFAULT);
8234	}
8235
8236	/**
8237	* Bus master physical memory write from the default PCI device.
8238	*
8239	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8240	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8241	* @param pDevIns The device instance.
8242	* @param GCPhys Physical address to write to.
8243	* @param pvBuf What to write.
8244	* @param cbWrite How many bytes to write.
8245	* @thread Any thread, but the call may involve the emulation thread.
8246	*/
8247	DECLINLINE(int) PDMDevHlpPCIPhysWriteMeta(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8248	{
8249	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8250	}
8251
8252	/**
8253	* Bus master physical memory write - written data was created/altered by the device.
8254	*
8255	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8256	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8257	* @param pDevIns The device instance.
8258	* @param pPciDev The PCI device structure. If NULL the default
8259	* PCI device for this device instance is used.
8260	* @param GCPhys Physical address to write to.
8261	* @param pvBuf What to write.
8262	* @param cbWrite How many bytes to write.
8263	* @thread Any thread, but the call may involve the emulation thread.
8264	*/
8265	DECLINLINE(int) PDMDevHlpPCIPhysWriteMetaEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8266	{
8267	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_META);
8268	}
8269
8270	/**
8271	* Bus master physical memory write from the default PCI device.
8272	*
8273	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8274	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8275	* @param pDevIns The device instance.
8276	* @param GCPhys Physical address to write to.
8277	* @param pvBuf What to write.
8278	* @param cbWrite How many bytes to write.
8279	* @thread Any thread, but the call may involve the emulation thread.
8280	*/
8281	DECLINLINE(int) PDMDevHlpPCIPhysWriteUser(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8282	{
8283	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, NULL, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8284	}
8285
8286	/**
8287	* Bus master physical memory write - written data was not touched/created by the device.
8288	*
8289	* @returns VINF_SUCCESS or VERR_PGM_PCI_PHYS_WRITE_BM_DISABLED, later maybe
8290	* VERR_EM_MEMORY. The informational status shall NOT be propagated!
8291	* @param pDevIns The device instance.
8292	* @param pPciDev The PCI device structure. If NULL the default
8293	* PCI device for this device instance is used.
8294	* @param GCPhys Physical address to write to.
8295	* @param pvBuf What to write.
8296	* @param cbWrite How many bytes to write.
8297	* @thread Any thread, but the call may involve the emulation thread.
8298	*/
8299	DECLINLINE(int) PDMDevHlpPCIPhysWriteUserEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
8300	{
8301	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, PDM_DEVHLP_PHYS_RW_F_DATA_USER);
8302	}
8303
8304	#ifdef IN_RING3
8305	/**
8306	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtr
8307	*/
8308	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8309	void **ppv, PPGMPAGEMAPLOCK pLock)
8310	{
8311	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtr(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8312	}
8313
8314	/**
8315	* @copydoc PDMDEVHLPR3::pfnPCIPhysGCPhys2CCPtrReadOnly
8316	*/
8317	DECLINLINE(int) PDMDevHlpPCIPhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags,
8318	void const **ppv, PPGMPAGEMAPLOCK pLock)
8319	{
8320	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysGCPhys2CCPtrReadOnly(pDevIns, pPciDev, GCPhys, fFlags, ppv, pLock);
8321	}
8322
8323	/**
8324	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtr
8325	*/
8326	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8327	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages,
8328	PPGMPAGEMAPLOCK paLocks)
8329	{
8330	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtr(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags, papvPages,
8331	paLocks);
8332	}
8333
8334	/**
8335	* @copydoc PDMDEVHLPR3::pfnPCIPhysBulkGCPhys2CCPtrReadOnly
8336	*/
8337	DECLINLINE(int) PDMDevHlpPCIPhysBulkGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages,
8338	PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void const **papvPages,
8339	PPGMPAGEMAPLOCK paLocks)
8340	{
8341	return pDevIns->CTX_SUFF(pHlp)->pfnPCIPhysBulkGCPhys2CCPtrReadOnly(pDevIns, pPciDev, cPages, paGCPhysPages, fFlags,
8342	papvPages, paLocks);
8343	}
8344	#endif /* IN_RING3 */
8345
8346	/**
8347	* Sets the IRQ for the default PCI device.
8348	*
8349	* @param pDevIns The device instance.
8350	* @param iIrq IRQ number to set.
8351	* @param iLevel IRQ level. See the PDM_IRQ_LEVEL_* \#defines.
8352	* @thread Any thread, but will involve the emulation thread.
8353	*/
8354	DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8355	{
8356	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8357	}
8358
8359	/**
8360	* @copydoc PDMDEVHLPR3::pfnPCISetIrq
8361	*/
8362	DECLINLINE(void) PDMDevHlpPCISetIrqEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8363	{
8364	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8365	}
8366
8367	/**
8368	* Sets the IRQ for the given PCI device, but doesn't wait for EMT to process
8369	* the request when not called from EMT.
8370	*
8371	* @param pDevIns The device instance.
8372	* @param iIrq IRQ number to set.
8373	* @param iLevel IRQ level.
8374	* @thread Any thread, but will involve the emulation thread.
8375	*/
8376	DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8377	{
8378	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, NULL, iIrq, iLevel);
8379	}
8380
8381	/**
8382	* @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait
8383	*/
8384	DECLINLINE(void) PDMDevHlpPCISetIrqNoWaitEx(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
8385	{
8386	pDevIns->CTX_SUFF(pHlp)->pfnPCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
8387	}
8388
8389	/**
8390	* @copydoc PDMDEVHLPR3::pfnISASetIrq
8391	*/
8392	DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8393	{
8394	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8395	}
8396
8397	/**
8398	* @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait
8399	*/
8400	DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
8401	{
8402	pDevIns->CTX_SUFF(pHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel);
8403	}
8404
8405	#ifdef IN_RING3
8406
8407	/**
8408	* @copydoc PDMDEVHLPR3::pfnDriverAttach
8409	*/
8410	DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
8411	{
8412	return pDevIns->pHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);
8413	}
8414
8415	/**
8416	* @copydoc PDMDEVHLPR3::pfnDriverDetach
8417	*/
8418	DECLINLINE(int) PDMDevHlpDriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
8419	{
8420	return pDevIns->pHlpR3->pfnDriverDetach(pDevIns, pDrvIns, fFlags);
8421	}
8422
8423	/**
8424	* @copydoc PDMDEVHLPR3::pfnDriverReconfigure
8425	*/
8426	DECLINLINE(int) PDMDevHlpDriverReconfigure(PPDMDEVINS pDevIns, uint32_t iLun, uint32_t cDepth,
8427	const char * const papszDrivers, PCFGMNODE papConfigs, uint32_t fFlags)
8428	{
8429	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, cDepth, papszDrivers, papConfigs, fFlags);
8430	}
8431
8432	/**
8433	* Reconfigures with a single driver reattachement, no config, noflags.
8434	* @sa PDMDevHlpDriverReconfigure
8435	*/
8436	DECLINLINE(int) PDMDevHlpDriverReconfigure1(PPDMDEVINS pDevIns, uint32_t iLun, const char *pszDriver0)
8437	{
8438	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 1, &pszDriver0, NULL, 0);
8439	}
8440
8441	/**
8442	* Reconfigures with a two drivers reattachement, no config, noflags.
8443	* @sa PDMDevHlpDriverReconfigure
8444	*/
8445	DECLINLINE(int) PDMDevHlpDriverReconfigure2(PPDMDEVINS pDevIns, uint32_t iLun, const char pszDriver0, const char pszDriver1)
8446	{
8447	char const * apszDrivers[2];
8448	apszDrivers[0] = pszDriver0;
8449	apszDrivers[1] = pszDriver1;
8450	return pDevIns->pHlpR3->pfnDriverReconfigure(pDevIns, iLun, 2, apszDrivers, NULL, 0);
8451	}
8452
8453	/**
8454	* @copydoc PDMDEVHLPR3::pfnQueueCreate
8455	*/
8456	DECLINLINE(int) PDMDevHlpQueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
8457	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PDMQUEUEHANDLE phQueue)
8458	{
8459	return pDevIns->pHlpR3->pfnQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, phQueue);
8460	}
8461
8462	#endif /* IN_RING3 */
8463
8464	/**
8465	* @copydoc PDMDEVHLPR3::pfnQueueAlloc
8466	*/
8467	DECLINLINE(PPDMQUEUEITEMCORE) PDMDevHlpQueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8468	{
8469	return pDevIns->CTX_SUFF(pHlp)->pfnQueueAlloc(pDevIns, hQueue);
8470	}
8471
8472	/**
8473	* @copydoc PDMDEVHLPR3::pfnQueueInsert
8474	*/
8475	DECLINLINE(int) PDMDevHlpQueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
8476	{
8477	return pDevIns->CTX_SUFF(pHlp)->pfnQueueInsert(pDevIns, hQueue, pItem);
8478	}
8479
8480	/**
8481	* @copydoc PDMDEVHLPR3::pfnQueueFlushIfNecessary
8482	*/
8483	DECLINLINE(bool) PDMDevHlpQueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
8484	{
8485	return pDevIns->CTX_SUFF(pHlp)->pfnQueueFlushIfNecessary(pDevIns, hQueue);
8486	}
8487
8488	#ifdef IN_RING3
8489	/**
8490	* @copydoc PDMDEVHLPR3::pfnTaskCreate
8491	*/
8492	DECLINLINE(int) PDMDevHlpTaskCreate(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszName,
8493	PFNPDMTASKDEV pfnCallback, void pvUser, PDMTASKHANDLE phTask)
8494	{
8495	return pDevIns->pHlpR3->pfnTaskCreate(pDevIns, fFlags, pszName, pfnCallback, pvUser, phTask);
8496	}
8497	#endif
8498
8499	/**
8500	* @copydoc PDMDEVHLPR3::pfnTaskTrigger
8501	*/
8502	DECLINLINE(int) PDMDevHlpTaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
8503	{
8504	return pDevIns->CTX_SUFF(pHlp)->pfnTaskTrigger(pDevIns, hTask);
8505	}
8506
8507	#ifdef IN_RING3
8508
8509	/**
8510	* @copydoc PDMDEVHLPR3::pfnSUPSemEventCreate
8511	*/
8512	DECLINLINE(int) PDMDevHlpSUPSemEventCreate(PPDMDEVINS pDevIns, PSUPSEMEVENT phEvent)
8513	{
8514	return pDevIns->pHlpR3->pfnSUPSemEventCreate(pDevIns, phEvent);
8515	}
8516
8517	/**
8518	* @copydoc PDMDEVHLPR3::pfnSUPSemEventClose
8519	*/
8520	DECLINLINE(int) PDMDevHlpSUPSemEventClose(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8521	{
8522	return pDevIns->pHlpR3->pfnSUPSemEventClose(pDevIns, hEvent);
8523	}
8524
8525	#endif /* IN_RING3 */
8526
8527	/**
8528	* @copydoc PDMDEVHLPR3::pfnSUPSemEventSignal
8529	*/
8530	DECLINLINE(int) PDMDevHlpSUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
8531	{
8532	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventSignal(pDevIns, hEvent);
8533	}
8534
8535	/**
8536	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNoResume
8537	*/
8538	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
8539	{
8540	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNoResume(pDevIns, hEvent, cMillies);
8541	}
8542
8543	/**
8544	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsAbsIntr
8545	*/
8546	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
8547	{
8548	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsAbsIntr(pDevIns, hEvent, uNsTimeout);
8549	}
8550
8551	/**
8552	* @copydoc PDMDEVHLPR3::pfnSUPSemEventWaitNsRelIntr
8553	*/
8554	DECLINLINE(int) PDMDevHlpSUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
8555	{
8556	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventWaitNsRelIntr(pDevIns, hEvent, cNsTimeout);
8557	}
8558
8559	/**
8560	* @copydoc PDMDEVHLPR3::pfnSUPSemEventGetResolution
8561	*/
8562	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventGetResolution(PPDMDEVINS pDevIns)
8563	{
8564	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventGetResolution(pDevIns);
8565	}
8566
8567	#ifdef IN_RING3
8568
8569	/**
8570	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiCreate
8571	*/
8572	DECLINLINE(int) PDMDevHlpSUPSemEventMultiCreate(PPDMDEVINS pDevIns, PSUPSEMEVENTMULTI phEventMulti)
8573	{
8574	return pDevIns->pHlpR3->pfnSUPSemEventMultiCreate(pDevIns, phEventMulti);
8575	}
8576
8577	/**
8578	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiClose
8579	*/
8580	DECLINLINE(int) PDMDevHlpSUPSemEventMultiClose(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8581	{
8582	return pDevIns->pHlpR3->pfnSUPSemEventMultiClose(pDevIns, hEventMulti);
8583	}
8584
8585	#endif /* IN_RING3 */
8586
8587	/**
8588	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiSignal
8589	*/
8590	DECLINLINE(int) PDMDevHlpSUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8591	{
8592	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiSignal(pDevIns, hEventMulti);
8593	}
8594
8595	/**
8596	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiReset
8597	*/
8598	DECLINLINE(int) PDMDevHlpSUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
8599	{
8600	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiReset(pDevIns, hEventMulti);
8601	}
8602
8603	/**
8604	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNoResume
8605	*/
8606	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint32_t cMillies)
8607	{
8608	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cMillies);
8609	}
8610
8611	/**
8612	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsAbsIntr
8613	*/
8614	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t uNsTimeout)
8615	{
8616	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsAbsIntr(pDevIns, hEventMulti, uNsTimeout);
8617	}
8618
8619	/**
8620	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiWaitNsRelIntr
8621	*/
8622	DECLINLINE(int) PDMDevHlpSUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti, uint64_t cNsTimeout)
8623	{
8624	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiWaitNsRelIntr(pDevIns, hEventMulti, cNsTimeout);
8625	}
8626
8627	/**
8628	* @copydoc PDMDEVHLPR3::pfnSUPSemEventMultiGetResolution
8629	*/
8630	DECLINLINE(uint32_t) PDMDevHlpSUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
8631	{
8632	return pDevIns->CTX_SUFF(pHlp)->pfnSUPSemEventMultiGetResolution(pDevIns);
8633	}
8634
8635	#ifdef IN_RING3
8636
8637	/**
8638	* Initializes a PDM critical section.
8639	*
8640	* The PDM critical sections are derived from the IPRT critical sections, but
8641	* works in RC and R0 as well.
8642	*
8643	* @returns VBox status code.
8644	* @param pDevIns The device instance.
8645	* @param pCritSect Pointer to the critical section.
8646	* @param SRC_POS Use RT_SRC_POS.
8647	* @param pszNameFmt Format string for naming the critical section.
8648	* For statistics and lock validation.
8649	* @param ... Arguments for the format string.
8650	*/
8651	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
8652	const char *pszNameFmt, ...)
8653	{
8654	int rc;
8655	va_list va;
8656	va_start(va, pszNameFmt);
8657	rc = pDevIns->pHlpR3->pfnCritSectInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8658	va_end(va);
8659	return rc;
8660	}
8661
8662	#endif /* IN_RING3 */
8663
8664	/**
8665	* @copydoc PDMDEVHLPR3::pfnCritSectGetNop
8666	*/
8667	DECLINLINE(PPDMCRITSECT) PDMDevHlpCritSectGetNop(PPDMDEVINS pDevIns)
8668	{
8669	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetNop(pDevIns);
8670	}
8671
8672	/**
8673	* @copydoc PDMDEVHLPR3::pfnSetDeviceCritSect
8674	*/
8675	DECLINLINE(int) PDMDevHlpSetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8676	{
8677	return pDevIns->CTX_SUFF(pHlp)->pfnSetDeviceCritSect(pDevIns, pCritSect);
8678	}
8679
8680	/**
8681	* Enters a PDM critical section.
8682	*
8683	* @returns VINF_SUCCESS if entered successfully.
8684	* @returns rcBusy when encountering a busy critical section in RC/R0.
8685	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8686	* during the operation.
8687	*
8688	* @param pDevIns The device instance.
8689	* @param pCritSect The PDM critical section to enter.
8690	* @param rcBusy The status code to return when we're in RC or R0
8691	* and the section is busy. Pass VINF_SUCCESS to
8692	* acquired the critical section thru a ring-3
8693	* call if necessary.
8694	*
8695	* @note Even callers setting @a rcBusy to VINF_SUCCESS must either handle
8696	* possible failures in ring-0 or at least apply
8697	* PDM_CRITSECT_RELEASE_ASSERT_RC_DEV() to the return value of this
8698	* function.
8699	*
8700	* @sa PDMCritSectEnter
8701	*/
8702	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
8703	{
8704	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnter(pDevIns, pCritSect, rcBusy);
8705	}
8706
8707	/**
8708	* Enters a PDM critical section, with location information for debugging.
8709	*
8710	* @returns VINF_SUCCESS if entered successfully.
8711	* @returns rcBusy when encountering a busy critical section in RC/R0.
8712	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8713	* during the operation.
8714	*
8715	* @param pDevIns The device instance.
8716	* @param pCritSect The PDM critical section to enter.
8717	* @param rcBusy The status code to return when we're in RC or R0
8718	* and the section is busy. Pass VINF_SUCCESS to
8719	* acquired the critical section thru a ring-3
8720	* call if necessary.
8721	* @param uId Some kind of locking location ID. Typically a
8722	* return address up the stack. Optional (0).
8723	* @param SRC_POS The source position where to lock is being
8724	* acquired from. Optional.
8725	* @sa PDMCritSectEnterDebug
8726	*/
8727	DECLINLINE(DECL_CHECK_RETURN(int))
8728	PDMDevHlpCritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8729	{
8730	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectEnterDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8731	}
8732
8733	/**
8734	* Try enter a critical section.
8735	*
8736	* @retval VINF_SUCCESS on success.
8737	* @retval VERR_SEM_BUSY if the critsect was owned.
8738	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8739	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8740	* during the operation.
8741	*
8742	* @param pDevIns The device instance.
8743	* @param pCritSect The critical section.
8744	* @sa PDMCritSectTryEnter
8745	*/
8746	DECLINLINE(DECL_CHECK_RETURN(int))
8747	PDMDevHlpCritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8748	{
8749	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnter(pDevIns, pCritSect);
8750	}
8751
8752	/**
8753	* Try enter a critical section, with location information for debugging.
8754	*
8755	* @retval VINF_SUCCESS on success.
8756	* @retval VERR_SEM_BUSY if the critsect was owned.
8757	* @retval VERR_SEM_NESTED if nested enter on a no nesting section. (Asserted.)
8758	* @retval VERR_SEM_DESTROYED if the critical section is delete before or
8759	* during the operation.
8760	*
8761	* @param pDevIns The device instance.
8762	* @param pCritSect The critical section.
8763	* @param uId Some kind of locking location ID. Typically a
8764	* return address up the stack. Optional (0).
8765	* @param SRC_POS The source position where to lock is being
8766	* acquired from. Optional.
8767	* @sa PDMCritSectTryEnterDebug
8768	*/
8769	DECLINLINE(DECL_CHECK_RETURN(int))
8770	PDMDevHlpCritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8771	{
8772	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectTryEnterDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8773	}
8774
8775	/**
8776	* Leaves a critical section entered with PDMCritSectEnter().
8777	*
8778	* @returns Indication whether we really exited the critical section.
8779	* @retval VINF_SUCCESS if we really exited.
8780	* @retval VINF_SEM_NESTED if we only reduced the nesting count.
8781	* @retval VERR_NOT_OWNER if you somehow ignore release assertions.
8782	*
8783	* @param pDevIns The device instance.
8784	* @param pCritSect The PDM critical section to leave.
8785	* @sa PDMCritSectLeave
8786	*/
8787	DECLINLINE(int) PDMDevHlpCritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8788	{
8789	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectLeave(pDevIns, pCritSect);
8790	}
8791
8792	/**
8793	* @see PDMCritSectIsOwner
8794	*/
8795	DECLINLINE(bool) PDMDevHlpCritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8796	{
8797	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsOwner(pDevIns, pCritSect);
8798	}
8799
8800	/**
8801	* @see PDMCritSectIsInitialized
8802	*/
8803	DECLINLINE(bool) PDMDevHlpCritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8804	{
8805	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectIsInitialized(pDevIns, pCritSect);
8806	}
8807
8808	/**
8809	* @see PDMCritSectHasWaiters
8810	*/
8811	DECLINLINE(bool) PDMDevHlpCritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8812	{
8813	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectHasWaiters(pDevIns, pCritSect);
8814	}
8815
8816	/**
8817	* @see PDMCritSectGetRecursion
8818	*/
8819	DECLINLINE(uint32_t) PDMDevHlpCritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
8820	{
8821	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectGetRecursion(pDevIns, pCritSect);
8822	}
8823
8824	#if defined(IN_RING3) \|\| defined(IN_RING0)
8825	/**
8826	* @see PDMHCCritSectScheduleExitEvent
8827	*/
8828	DECLINLINE(int) PDMDevHlpCritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, SUPSEMEVENT hEventToSignal)
8829	{
8830	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectScheduleExitEvent(pDevIns, pCritSect, hEventToSignal);
8831	}
8832	#endif
8833
8834	/* Strict build: Remap the two enter calls to the debug versions. */
8835	#ifdef VBOX_STRICT
8836	# ifdef IPRT_INCLUDED_asm_h
8837	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8838	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
8839	# else
8840	# define PDMDevHlpCritSectEnter(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectEnterDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
8841	# define PDMDevHlpCritSectTryEnter(pDevIns, pCritSect) PDMDevHlpCritSectTryEnterDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
8842	# endif
8843	#endif
8844
8845	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
8846
8847	/**
8848	* Deletes the critical section.
8849	*
8850	* @returns VBox status code.
8851	* @param pDevIns The device instance.
8852	* @param pCritSect The PDM critical section to destroy.
8853	* @sa PDMR3CritSectDelete
8854	*/
8855	DECLINLINE(int) PDMDevHlpCritSectDelete(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
8856	{
8857	return pDevIns->pHlpR3->pfnCritSectDelete(pDevIns, pCritSect);
8858	}
8859
8860	/**
8861	* Initializes a PDM read/write critical section.
8862	*
8863	* The PDM read/write critical sections are derived from the IPRT critical
8864	* sections, but works in RC and R0 as well.
8865	*
8866	* @returns VBox status code.
8867	* @param pDevIns The device instance.
8868	* @param pCritSect Pointer to the read/write critical section.
8869	* @param SRC_POS Use RT_SRC_POS.
8870	* @param pszNameFmt Format string for naming the critical section.
8871	* For statistics and lock validation.
8872	* @param ... Arguments for the format string.
8873	*/
8874	DECLINLINE(int) RT_IPRT_FORMAT_ATTR(6, 7) PDMDevHlpCritSectRwInit(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
8875	const char *pszNameFmt, ...)
8876	{
8877	int rc;
8878	va_list va;
8879	va_start(va, pszNameFmt);
8880	rc = pDevIns->pHlpR3->pfnCritSectRwInit(pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
8881	va_end(va);
8882	return rc;
8883	}
8884
8885	/**
8886	* Deletes the read/write critical section.
8887	*
8888	* @returns VBox status code.
8889	* @param pDevIns The device instance.
8890	* @param pCritSect The PDM read/write critical section to destroy.
8891	* @sa PDMR3CritSectRwDelete
8892	*/
8893	DECLINLINE(int) PDMDevHlpCritSectRwDelete(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8894	{
8895	return pDevIns->pHlpR3->pfnCritSectRwDelete(pDevIns, pCritSect);
8896	}
8897
8898	#endif /* IN_RING3 */
8899
8900	/**
8901	* @sa PDMCritSectRwEnterShared, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8902	*/
8903	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8904	{
8905	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterShared(pDevIns, pCritSect, rcBusy);
8906	}
8907
8908	/**
8909	* @sa PDMCritSectRwEnterSharedDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8910	*/
8911	DECLINLINE(DECL_CHECK_RETURN(int))
8912	PDMDevHlpCritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8913	{
8914	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterSharedDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8915	}
8916
8917	/**
8918	* @sa PDMCritSectRwTryEnterShared
8919	*/
8920	DECLINLINE(DECL_CHECK_RETURN(int))
8921	PDMDevHlpCritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8922	{
8923	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterShared(pDevIns, pCritSect);
8924	}
8925
8926	/**
8927	* @sa PDMCritSectRwTryEnterSharedDebug
8928	*/
8929	DECLINLINE(DECL_CHECK_RETURN(int))
8930	PDMDevHlpCritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8931	{
8932	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterSharedDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8933	}
8934
8935	/**
8936	* @sa PDMCritSectRwLeaveShared
8937	*/
8938	DECLINLINE(int) PDMDevHlpCritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8939	{
8940	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveShared(pDevIns, pCritSect);
8941	}
8942
8943	/**
8944	* @sa PDMCritSectRwEnterExcl, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8945	*/
8946	DECLINLINE(DECL_CHECK_RETURN(int)) PDMDevHlpCritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
8947	{
8948	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy);
8949	}
8950
8951	/**
8952	* @sa PDMCritSectRwEnterExclDebug, PDM_CRITSECT_RELEASE_ASSERT_RC_DEV
8953	*/
8954	DECLINLINE(DECL_CHECK_RETURN(int))
8955	PDMDevHlpCritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8956	{
8957	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwEnterExclDebug(pDevIns, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
8958	}
8959
8960	/**
8961	* @sa PDMCritSectRwTryEnterExcl
8962	*/
8963	DECLINLINE(DECL_CHECK_RETURN(int))
8964	PDMDevHlpCritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8965	{
8966	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExcl(pDevIns, pCritSect);
8967	}
8968
8969	/**
8970	* @sa PDMCritSectRwTryEnterExclDebug
8971	*/
8972	DECLINLINE(DECL_CHECK_RETURN(int))
8973	PDMDevHlpCritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
8974	{
8975	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwTryEnterExclDebug(pDevIns, pCritSect, uId, RT_SRC_POS_ARGS);
8976	}
8977
8978	/**
8979	* @sa PDMCritSectRwLeaveExcl
8980	*/
8981	DECLINLINE(int) PDMDevHlpCritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8982	{
8983	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwLeaveExcl(pDevIns, pCritSect);
8984	}
8985
8986	/**
8987	* @see PDMCritSectRwIsWriteOwner
8988	*/
8989	DECLINLINE(bool) PDMDevHlpCritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
8990	{
8991	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsWriteOwner(pDevIns, pCritSect);
8992	}
8993
8994	/**
8995	* @see PDMCritSectRwIsReadOwner
8996	*/
8997	DECLINLINE(bool) PDMDevHlpCritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
8998	{
8999	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsReadOwner(pDevIns, pCritSect, fWannaHear);
9000	}
9001
9002	/**
9003	* @see PDMCritSectRwGetWriteRecursion
9004	*/
9005	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9006	{
9007	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriteRecursion(pDevIns, pCritSect);
9008	}
9009
9010	/**
9011	* @see PDMCritSectRwGetWriterReadRecursion
9012	*/
9013	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9014	{
9015	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetWriterReadRecursion(pDevIns, pCritSect);
9016	}
9017
9018	/**
9019	* @see PDMCritSectRwGetReadCount
9020	*/
9021	DECLINLINE(uint32_t) PDMDevHlpCritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9022	{
9023	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwGetReadCount(pDevIns, pCritSect);
9024	}
9025
9026	/**
9027	* @see PDMCritSectRwIsInitialized
9028	*/
9029	DECLINLINE(bool) PDMDevHlpCritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
9030	{
9031	return pDevIns->CTX_SUFF(pHlp)->pfnCritSectRwIsInitialized(pDevIns, pCritSect);
9032	}
9033
9034	/* Strict build: Remap the two enter calls to the debug versions. */
9035	#ifdef VBOX_STRICT
9036	# ifdef IPRT_INCLUDED_asm_h
9037	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9038	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9039	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9040	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), (uintptr_t)ASMReturnAddress(), RT_SRC_POS)
9041	# else
9042	# define PDMDevHlpCritSectRwEnterShared(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterSharedDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
9043	# define PDMDevHlpCritSectRwTryEnterShared(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterSharedDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
9044	# define PDMDevHlpCritSectRwEnterExcl(pDevIns, pCritSect, rcBusy) PDMDevHlpCritSectRwEnterExclDebug((pDevIns), (pCritSect), (rcBusy), 0, RT_SRC_POS)
9045	# define PDMDevHlpCritSectRwTryEnterExcl(pDevIns, pCritSect) PDMDevHlpCritSectRwTryEnterExclDebug((pDevIns), (pCritSect), 0, RT_SRC_POS)
9046	# endif
9047	#endif
9048
9049	#if defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9050
9051	/**
9052	* @copydoc PDMDEVHLPR3::pfnThreadCreate
9053	*/
9054	DECLINLINE(int) PDMDevHlpThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
9055	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
9056	{
9057	return pDevIns->pHlpR3->pfnThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
9058	}
9059
9060	/**
9061	* @copydoc PDMR3ThreadDestroy
9062	* @param pDevIns The device instance.
9063	*/
9064	DECLINLINE(int) PDMDevHlpThreadDestroy(PPDMDEVINS pDevIns, PPDMTHREAD pThread, int *pRcThread)
9065	{
9066	return pDevIns->pHlpR3->pfnThreadDestroy(pThread, pRcThread);
9067	}
9068
9069	/**
9070	* @copydoc PDMR3ThreadIAmSuspending
9071	* @param pDevIns The device instance.
9072	*/
9073	DECLINLINE(int) PDMDevHlpThreadIAmSuspending(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9074	{
9075	return pDevIns->pHlpR3->pfnThreadIAmSuspending(pThread);
9076	}
9077
9078	/**
9079	* @copydoc PDMR3ThreadIAmRunning
9080	* @param pDevIns The device instance.
9081	*/
9082	DECLINLINE(int) PDMDevHlpThreadIAmRunning(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9083	{
9084	return pDevIns->pHlpR3->pfnThreadIAmRunning(pThread);
9085	}
9086
9087	/**
9088	* @copydoc PDMR3ThreadSleep
9089	* @param pDevIns The device instance.
9090	*/
9091	DECLINLINE(int) PDMDevHlpThreadSleep(PPDMDEVINS pDevIns, PPDMTHREAD pThread, RTMSINTERVAL cMillies)
9092	{
9093	return pDevIns->pHlpR3->pfnThreadSleep(pThread, cMillies);
9094	}
9095
9096	/**
9097	* @copydoc PDMR3ThreadSuspend
9098	* @param pDevIns The device instance.
9099	*/
9100	DECLINLINE(int) PDMDevHlpThreadSuspend(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9101	{
9102	return pDevIns->pHlpR3->pfnThreadSuspend(pThread);
9103	}
9104
9105	/**
9106	* @copydoc PDMR3ThreadResume
9107	* @param pDevIns The device instance.
9108	*/
9109	DECLINLINE(int) PDMDevHlpThreadResume(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
9110	{
9111	return pDevIns->pHlpR3->pfnThreadResume(pThread);
9112	}
9113
9114	/**
9115	* @copydoc PDMDEVHLPR3::pfnSetAsyncNotification
9116	*/
9117	DECLINLINE(int) PDMDevHlpSetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
9118	{
9119	return pDevIns->pHlpR3->pfnSetAsyncNotification(pDevIns, pfnAsyncNotify);
9120	}
9121
9122	/**
9123	* @copydoc PDMDEVHLPR3::pfnAsyncNotificationCompleted
9124	*/
9125	DECLINLINE(void) PDMDevHlpAsyncNotificationCompleted(PPDMDEVINS pDevIns)
9126	{
9127	pDevIns->pHlpR3->pfnAsyncNotificationCompleted(pDevIns);
9128	}
9129
9130	/**
9131	* @copydoc PDMDEVHLPR3::pfnA20Set
9132	*/
9133	DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable)
9134	{
9135	pDevIns->pHlpR3->pfnA20Set(pDevIns, fEnable);
9136	}
9137
9138	/**
9139	* @copydoc PDMDEVHLPR3::pfnRTCRegister
9140	*/
9141	DECLINLINE(int) PDMDevHlpRTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
9142	{
9143	return pDevIns->pHlpR3->pfnRTCRegister(pDevIns, pRtcReg, ppRtcHlp);
9144	}
9145
9146	/**
9147	* @copydoc PDMDEVHLPR3::pfnPCIBusRegister
9148	*/
9149	DECLINLINE(int) PDMDevHlpPCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREGR3 pPciBusReg, PCPDMPCIHLPR3 ppPciHlp, uint32_t piBus)
9150	{
9151	return pDevIns->pHlpR3->pfnPCIBusRegister(pDevIns, pPciBusReg, ppPciHlp, piBus);
9152	}
9153
9154	/**
9155	* @copydoc PDMDEVHLPR3::pfnIommuRegister
9156	*/
9157	DECLINLINE(int) PDMDevHlpIommuRegister(PPDMDEVINS pDevIns, PPDMIOMMUREGR3 pIommuReg, PCPDMIOMMUHLPR3 ppIommuHlp, uint32_t pidxIommu)
9158	{
9159	return pDevIns->pHlpR3->pfnIommuRegister(pDevIns, pIommuReg, ppIommuHlp, pidxIommu);
9160	}
9161
9162	/**
9163	* @copydoc PDMDEVHLPR3::pfnPICRegister
9164	*/
9165	DECLINLINE(int) PDMDevHlpPICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9166	{
9167	return pDevIns->pHlpR3->pfnPICRegister(pDevIns, pPicReg, ppPicHlp);
9168	}
9169
9170	/**
9171	* @copydoc PDMDEVHLPR3::pfnApicRegister
9172	*/
9173	DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
9174	{
9175	return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
9176	}
9177
9178	/**
9179	* @copydoc PDMDEVHLPR3::pfnIoApicRegister
9180	*/
9181	DECLINLINE(int) PDMDevHlpIoApicRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9182	{
9183	return pDevIns->pHlpR3->pfnIoApicRegister(pDevIns, pIoApicReg, ppIoApicHlp);
9184	}
9185
9186	/**
9187	* @copydoc PDMDEVHLPR3::pfnHpetRegister
9188	*/
9189	DECLINLINE(int) PDMDevHlpHpetRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
9190	{
9191	return pDevIns->pHlpR3->pfnHpetRegister(pDevIns, pHpetReg, ppHpetHlpR3);
9192	}
9193
9194	/**
9195	* @copydoc PDMDEVHLPR3::pfnPciRawRegister
9196	*/
9197	DECLINLINE(int) PDMDevHlpPciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
9198	{
9199	return pDevIns->pHlpR3->pfnPciRawRegister(pDevIns, pPciRawReg, ppPciRawHlpR3);
9200	}
9201
9202	/**
9203	* @copydoc PDMDEVHLPR3::pfnDMACRegister
9204	*/
9205	DECLINLINE(int) PDMDevHlpDMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
9206	{
9207	return pDevIns->pHlpR3->pfnDMACRegister(pDevIns, pDmacReg, ppDmacHlp);
9208	}
9209
9210	/**
9211	* @copydoc PDMDEVHLPR3::pfnDMARegister
9212	*/
9213	DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
9214	{
9215	return pDevIns->pHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);
9216	}
9217
9218	/**
9219	* @copydoc PDMDEVHLPR3::pfnDMAReadMemory
9220	*/
9221	DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
9222	{
9223	return pDevIns->pHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);
9224	}
9225
9226	/**
9227	* @copydoc PDMDEVHLPR3::pfnDMAWriteMemory
9228	*/
9229	DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
9230	{
9231	return pDevIns->pHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);
9232	}
9233
9234	/**
9235	* @copydoc PDMDEVHLPR3::pfnDMASetDREQ
9236	*/
9237	DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
9238	{
9239	return pDevIns->pHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel);
9240	}
9241
9242	/**
9243	* @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode
9244	*/
9245	DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
9246	{
9247	return pDevIns->pHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel);
9248	}
9249
9250	/**
9251	* @copydoc PDMDEVHLPR3::pfnDMASchedule
9252	*/
9253	DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns)
9254	{
9255	pDevIns->pHlpR3->pfnDMASchedule(pDevIns);
9256	}
9257
9258	/**
9259	* @copydoc PDMDEVHLPR3::pfnCMOSWrite
9260	*/
9261	DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
9262	{
9263	return pDevIns->pHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value);
9264	}
9265
9266	/**
9267	* @copydoc PDMDEVHLPR3::pfnCMOSRead
9268	*/
9269	DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
9270	{
9271	return pDevIns->pHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value);
9272	}
9273
9274	/**
9275	* @copydoc PDMDEVHLPR3::pfnCallR0
9276	*/
9277	DECLINLINE(int) PDMDevHlpCallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
9278	{
9279	return pDevIns->pHlpR3->pfnCallR0(pDevIns, uOperation, u64Arg);
9280	}
9281
9282	/**
9283	* @copydoc PDMDEVHLPR3::pfnVMGetSuspendReason
9284	*/
9285	DECLINLINE(VMSUSPENDREASON) PDMDevHlpVMGetSuspendReason(PPDMDEVINS pDevIns)
9286	{
9287	return pDevIns->pHlpR3->pfnVMGetSuspendReason(pDevIns);
9288	}
9289
9290	/**
9291	* @copydoc PDMDEVHLPR3::pfnVMGetResumeReason
9292	*/
9293	DECLINLINE(VMRESUMEREASON) PDMDevHlpVMGetResumeReason(PPDMDEVINS pDevIns)
9294	{
9295	return pDevIns->pHlpR3->pfnVMGetResumeReason(pDevIns);
9296	}
9297
9298	/**
9299	* @copydoc PDMDEVHLPR3::pfnGetUVM
9300	*/
9301	DECLINLINE(PUVM) PDMDevHlpGetUVM(PPDMDEVINS pDevIns)
9302	{
9303	return pDevIns->CTX_SUFF(pHlp)->pfnGetUVM(pDevIns);
9304	}
9305
9306	#endif /* IN_RING3 \|\| DOXYGEN_RUNNING */
9307
9308	#if !defined(IN_RING3) \|\| defined(DOXYGEN_RUNNING)
9309
9310	/**
9311	* @copydoc PDMDEVHLPR0::pfnPCIBusSetUpContext
9312	*/
9313	DECLINLINE(int) PDMDevHlpPCIBusSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMPCIBUSREG) pPciBusReg, CTX_SUFF(PCPDMPCIHLP) *ppPciHlp)
9314	{
9315	return pDevIns->CTX_SUFF(pHlp)->pfnPCIBusSetUpContext(pDevIns, pPciBusReg, ppPciHlp);
9316	}
9317
9318	/**
9319	* @copydoc PDMDEVHLPR0::pfnIommuSetUpContext
9320	*/
9321	DECLINLINE(int) PDMDevHlpIommuSetUpContext(PPDMDEVINS pDevIns, CTX_SUFF(PPDMIOMMUREG) pIommuReg, CTX_SUFF(PCPDMIOMMUHLP) *ppIommuHlp)
9322	{
9323	return pDevIns->CTX_SUFF(pHlp)->pfnIommuSetUpContext(pDevIns, pIommuReg, ppIommuHlp);
9324	}
9325
9326	/**
9327	* @copydoc PDMDEVHLPR0::pfnPICSetUpContext
9328	*/
9329	DECLINLINE(int) PDMDevHlpPICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
9330	{
9331	return pDevIns->CTX_SUFF(pHlp)->pfnPICSetUpContext(pDevIns, pPicReg, ppPicHlp);
9332	}
9333
9334	/**
9335	* @copydoc PDMDEVHLPR0::pfnApicSetUpContext
9336	*/
9337	DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
9338	{
9339	return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
9340	}
9341
9342	/**
9343	* @copydoc PDMDEVHLPR0::pfnIoApicSetUpContext
9344	*/
9345	DECLINLINE(int) PDMDevHlpIoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
9346	{
9347	return pDevIns->CTX_SUFF(pHlp)->pfnIoApicSetUpContext(pDevIns, pIoApicReg, ppIoApicHlp);
9348	}
9349
9350	/**
9351	* @copydoc PDMDEVHLPR0::pfnHpetSetUpContext
9352	*/
9353	DECLINLINE(int) PDMDevHlpHpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, CTX_SUFF(PCPDMHPETHLP) *ppHpetHlp)
9354	{
9355	return pDevIns->CTX_SUFF(pHlp)->pfnHpetSetUpContext(pDevIns, pHpetReg, ppHpetHlp);
9356	}
9357
9358	#endif /* !IN_RING3 \|\| DOXYGEN_RUNNING */
9359
9360	/**
9361	* @copydoc PDMDEVHLPR3::pfnGetVM
9362	*/
9363	DECLINLINE(PVMCC) PDMDevHlpGetVM(PPDMDEVINS pDevIns)
9364	{
9365	return pDevIns->CTX_SUFF(pHlp)->pfnGetVM(pDevIns);
9366	}
9367
9368	/**
9369	* @copydoc PDMDEVHLPR3::pfnGetVMCPU
9370	*/
9371	DECLINLINE(PVMCPUCC) PDMDevHlpGetVMCPU(PPDMDEVINS pDevIns)
9372	{
9373	return pDevIns->CTX_SUFF(pHlp)->pfnGetVMCPU(pDevIns);
9374	}
9375
9376	/**
9377	* @copydoc PDMDEVHLPR3::pfnGetCurrentCpuId
9378	*/
9379	DECLINLINE(VMCPUID) PDMDevHlpGetCurrentCpuId(PPDMDEVINS pDevIns)
9380	{
9381	return pDevIns->CTX_SUFF(pHlp)->pfnGetCurrentCpuId(pDevIns);
9382	}
9383
9384	/**
9385	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGet
9386	*/
9387	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGet(PPDMDEVINS pDevIns)
9388	{
9389	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGet(pDevIns);
9390	}
9391
9392	/**
9393	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9394	*/
9395	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetFreq(PPDMDEVINS pDevIns)
9396	{
9397	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetFreq(pDevIns);
9398	}
9399
9400	/**
9401	* @copydoc PDMDEVHLPR3::pfnTMTimeVirtGetFreq
9402	*/
9403	DECLINLINE(uint64_t) PDMDevHlpTMTimeVirtGetNano(PPDMDEVINS pDevIns)
9404	{
9405	return pDevIns->CTX_SUFF(pHlp)->pfnTMTimeVirtGetNano(pDevIns);
9406	}
9407
9408	#ifdef IN_RING3
9409	/**
9410	* @copydoc PDMDEVHLPR3::pfnTMCpuTicksPerSecond
9411	*/
9412	DECLINLINE(uint64_t) PDMDevHlpTMCpuTicksPerSecond(PPDMDEVINS pDevIns)
9413	{
9414	return pDevIns->CTX_SUFF(pHlp)->pfnTMCpuTicksPerSecond(pDevIns);
9415	}
9416
9417	/**
9418	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
9419	*/
9420	DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
9421	{
9422	return pDevIns->pHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbHeap);
9423	}
9424
9425	/**
9426	* @copydoc PDMDEVHLPR3::pfnFirmwareRegister
9427	*/
9428	DECLINLINE(int) PDMDevHlpFirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
9429	{
9430	return pDevIns->pHlpR3->pfnFirmwareRegister(pDevIns, pFwReg, ppFwHlp);
9431	}
9432
9433	/**
9434	* @copydoc PDMDEVHLPR3::pfnVMReset
9435	*/
9436	DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
9437	{
9438	return pDevIns->pHlpR3->pfnVMReset(pDevIns, fFlags);
9439	}
9440
9441	/**
9442	* @copydoc PDMDEVHLPR3::pfnVMSuspend
9443	*/
9444	DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns)
9445	{
9446	return pDevIns->pHlpR3->pfnVMSuspend(pDevIns);
9447	}
9448
9449	/**
9450	* @copydoc PDMDEVHLPR3::pfnVMSuspendSaveAndPowerOff
9451	*/
9452	DECLINLINE(int) PDMDevHlpVMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
9453	{
9454	return pDevIns->pHlpR3->pfnVMSuspendSaveAndPowerOff(pDevIns);
9455	}
9456
9457	/**
9458	* @copydoc PDMDEVHLPR3::pfnVMPowerOff
9459	*/
9460	DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns)
9461	{
9462	return pDevIns->pHlpR3->pfnVMPowerOff(pDevIns);
9463	}
9464
9465	#endif /* IN_RING3 */
9466
9467	/**
9468	* @copydoc PDMDEVHLPR3::pfnA20IsEnabled
9469	*/
9470	DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns)
9471	{
9472	return pDevIns->CTX_SUFF(pHlp)->pfnA20IsEnabled(pDevIns);
9473	}
9474
9475	#ifdef IN_RING3
9476	/**
9477	* @copydoc PDMDEVHLPR3::pfnGetCpuId
9478	*/
9479	DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
9480	{
9481	pDevIns->pHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);
9482	}
9483	#endif
9484
9485	/**
9486	* @copydoc PDMDEVHLPR3::pfnGetMainExecutionEngine
9487	*/
9488	DECLINLINE(uint8_t) PDMDevHlpGetMainExecutionEngine(PPDMDEVINS pDevIns)
9489	{
9490	return pDevIns->CTX_SUFF(pHlp)->pfnGetMainExecutionEngine(pDevIns);
9491	}
9492
9493	#ifdef IN_RING3
9494
9495	/**
9496	* @copydoc PDMDEVHLPR3::pfnGetSupDrvSession
9497	*/
9498	DECLINLINE(PSUPDRVSESSION) PDMDevHlpGetSupDrvSession(PPDMDEVINS pDevIns)
9499	{
9500	return pDevIns->pHlpR3->pfnGetSupDrvSession(pDevIns);
9501	}
9502
9503	/**
9504	* @copydoc PDMDEVHLPR3::pfnQueryGenericUserObject
9505	*/
9506	DECLINLINE(void *) PDMDevHlpQueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
9507	{
9508	return pDevIns->pHlpR3->pfnQueryGenericUserObject(pDevIns, pUuid);
9509	}
9510
9511	/**
9512	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalTypeRegister
9513	*/
9514	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeRegister(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9515	PFNPGMPHYSHANDLER pfnHandler, const char *pszDesc,
9516	PPGMPHYSHANDLERTYPE phType)
9517	{
9518	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalTypeRegister(pDevIns, enmKind, pfnHandler, pszDesc, phType);
9519	}
9520
9521	#elif defined(IN_RING0)
9522
9523	/**
9524	* @copydoc PDMDEVHLPR0::pfnPGMHandlerPhysicalTypeSetUpContext
9525	*/
9526	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalTypeSetUpContext(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
9527	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
9528	const char *pszDesc, PGMPHYSHANDLERTYPE hType)
9529	{
9530	return pDevIns->pHlpR0->pfnPGMHandlerPhysicalTypeSetUpContext(pDevIns, enmKind, pfnHandler, pfnPfHandler, pszDesc, hType);
9531	}
9532
9533	#endif
9534	#ifdef IN_RING3
9535
9536	/**
9537	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalRegister
9538	*/
9539	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
9540	PGMPHYSHANDLERTYPE hType, R3PTRTYPE(const char *) pszDesc)
9541	{
9542	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalRegister(pDevIns, GCPhys, GCPhysLast, hType, pszDesc);
9543	}
9544
9545	/**
9546	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalDeregister
9547	*/
9548	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalDeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9549	{
9550	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalDeregister(pDevIns, GCPhys);
9551	}
9552
9553	#endif /* IN_RING3 */
9554
9555	/**
9556	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalPageTempOff
9557	*/
9558	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
9559	{
9560	return pDevIns->CTX_SUFF(pHlp)->pfnPGMHandlerPhysicalPageTempOff(pDevIns, GCPhys, GCPhysPage);
9561	}
9562
9563	#ifdef IN_RING3
9564
9565	/**
9566	* @copydoc PDMDEVHLPR3::pfnPGMHandlerPhysicalReset
9567	*/
9568	DECLINLINE(int) PDMDevHlpPGMHandlerPhysicalReset(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
9569	{
9570	return pDevIns->pHlpR3->pfnPGMHandlerPhysicalReset(pDevIns, GCPhys);
9571	}
9572
9573	/**
9574	* @copydoc PDMDEVHLPR3::pfnVMMRegisterPatchMemory
9575	*/
9576	DECLINLINE(int) PDMDevHlpVMMRegisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9577	{
9578	return pDevIns->pHlpR3->pfnVMMRegisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9579	}
9580
9581	/**
9582	* @copydoc PDMDEVHLPR3::pfnVMMDeregisterPatchMemory
9583	*/
9584	DECLINLINE(int) PDMDevHlpVMMDeregisterPatchMemory(PPDMDEVINS pDevIns, RTGCPTR GCPtrPatchMem, uint32_t cbPatchMem)
9585	{
9586	return pDevIns->pHlpR3->pfnVMMDeregisterPatchMemory(pDevIns, GCPtrPatchMem, cbPatchMem);
9587	}
9588
9589	/**
9590	* @copydoc PDMDEVHLPR3::pfnSharedModuleRegister
9591	*/
9592	DECLINLINE(int) PDMDevHlpSharedModuleRegister(PPDMDEVINS pDevIns, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
9593	RTGCPTR GCBaseAddr, uint32_t cbModule,
9594	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions)
9595	{
9596	return pDevIns->pHlpR3->pfnSharedModuleRegister(pDevIns, enmGuestOS, pszModuleName, pszVersion,
9597	GCBaseAddr, cbModule, cRegions, paRegions);
9598	}
9599
9600	/**
9601	* @copydoc PDMDEVHLPR3::pfnSharedModuleUnregister
9602	*/
9603	DECLINLINE(int) PDMDevHlpSharedModuleUnregister(PPDMDEVINS pDevIns, char pszModuleName, char pszVersion,
9604	RTGCPTR GCBaseAddr, uint32_t cbModule)
9605	{
9606	return pDevIns->pHlpR3->pfnSharedModuleUnregister(pDevIns, pszModuleName, pszVersion, GCBaseAddr, cbModule);
9607	}
9608
9609	/**
9610	* @copydoc PDMDEVHLPR3::pfnSharedModuleGetPageState
9611	*/
9612	DECLINLINE(int) PDMDevHlpSharedModuleGetPageState(PPDMDEVINS pDevIns, RTGCPTR GCPtrPage, bool *pfShared,
9613	uint64_t *pfPageFlags)
9614	{
9615	return pDevIns->pHlpR3->pfnSharedModuleGetPageState(pDevIns, GCPtrPage, pfShared, pfPageFlags);
9616	}
9617
9618	/**
9619	* @copydoc PDMDEVHLPR3::pfnSharedModuleCheckAll
9620	*/
9621	DECLINLINE(int) PDMDevHlpSharedModuleCheckAll(PPDMDEVINS pDevIns)
9622	{
9623	return pDevIns->pHlpR3->pfnSharedModuleCheckAll(pDevIns);
9624	}
9625
9626	/**
9627	* @copydoc PDMDEVHLPR3::pfnQueryLun
9628	*/
9629	DECLINLINE(int) PDMDevHlpQueryLun(PPDMDEVINS pDevIns, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMIBASE ppBase)
9630	{
9631	return pDevIns->pHlpR3->pfnQueryLun(pDevIns, pszDevice, iInstance, iLun, ppBase);
9632	}
9633
9634	/**
9635	* @copydoc PDMDEVHLPR3::pfnGIMDeviceRegister
9636	*/
9637	DECLINLINE(void) PDMDevHlpGIMDeviceRegister(PPDMDEVINS pDevIns, PGIMDEBUG pDbg)
9638	{
9639	pDevIns->pHlpR3->pfnGIMDeviceRegister(pDevIns, pDbg);
9640	}
9641
9642	/**
9643	* @copydoc PDMDEVHLPR3::pfnGIMGetDebugSetup
9644	*/
9645	DECLINLINE(int) PDMDevHlpGIMGetDebugSetup(PPDMDEVINS pDevIns, PGIMDEBUGSETUP pDbgSetup)
9646	{
9647	return pDevIns->pHlpR3->pfnGIMGetDebugSetup(pDevIns, pDbgSetup);
9648	}
9649
9650	#endif /* IN_RING3 */
9651
9652	/**
9653	* @copydoc PDMDEVHLPR3::pfnGIMGetMmio2Regions
9654	*/
9655	DECLINLINE(PGIMMMIO2REGION) PDMDevHlpGIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
9656	{
9657	return pDevIns->CTX_SUFF(pHlp)->pfnGIMGetMmio2Regions(pDevIns, pcRegions);
9658	}
9659
9660	#ifdef IN_RING3
9661
9662	/** Wrapper around SSMR3GetU32 for simplifying getting enum values saved as uint32_t. */
9663	# define PDMDEVHLP_SSM_GET_ENUM32_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9664	do { \
9665	uint32_t u32GetEnumTmp = 0; \
9666	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU32((a_pSSM), &u32GetEnumTmp); \
9667	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9668	(a_enmDst) = (a_EnumType)u32GetEnumTmp; \
9669	AssertCompile(sizeof(a_EnumType) == sizeof(u32GetEnumTmp)); \
9670	} while (0)
9671
9672	/** Wrapper around SSMR3GetU8 for simplifying getting enum values saved as uint8_t. */
9673	# define PDMDEVHLP_SSM_GET_ENUM8_RET(a_pHlp, a_pSSM, a_enmDst, a_EnumType) \
9674	do { \
9675	uint8_t bGetEnumTmp = 0; \
9676	int rcGetEnum32Tmp = (a_pHlp)->pfnSSMGetU8((a_pSSM), &bGetEnumTmp); \
9677	AssertRCReturn(rcGetEnum32Tmp, rcGetEnum32Tmp); \
9678	(a_enmDst) = (a_EnumType)bGetEnumTmp; \
9679	} while (0)
9680
9681	#endif /* IN_RING3 */
9682
9683	/** Pointer to callbacks provided to the VBoxDeviceRegister() call. */
9684	typedef struct PDMDEVREGCB *PPDMDEVREGCB;
9685
9686	/**
9687	* Callbacks for VBoxDeviceRegister().
9688	*/
9689	typedef struct PDMDEVREGCB
9690	{
9691	/** Interface version.
9692	* This is set to PDM_DEVREG_CB_VERSION. */
9693	uint32_t u32Version;
9694
9695	/**
9696	* Registers a device with the current VM instance.
9697	*
9698	* @returns VBox status code.
9699	* @param pCallbacks Pointer to the callback table.
9700	* @param pReg Pointer to the device registration record.
9701	* This data must be permanent and readonly.
9702	*/
9703	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVREGCB pCallbacks, PCPDMDEVREG pReg));
9704	} PDMDEVREGCB;
9705
9706	/** Current version of the PDMDEVREGCB structure. */
9707	#define PDM_DEVREG_CB_VERSION PDM_VERSION_MAKE(0xffe3, 1, 0)
9708
9709
9710	/**
9711	* The VBoxDevicesRegister callback function.
9712	*
9713	* PDM will invoke this function after loading a device module and letting
9714	* the module decide which devices to register and how to handle conflicts.
9715	*
9716	* @returns VBox status code.
9717	* @param pCallbacks Pointer to the callback table.
9718	* @param u32Version VBox version number.
9719	*/
9720	typedef DECLCALLBACKTYPE(int, FNPDMVBOXDEVICESREGISTER,(PPDMDEVREGCB pCallbacks, uint32_t u32Version));
9721
9722	/** @} */
9723
9724	RT_C_DECLS_END
9725
9726	#endif /* !VBOX_INCLUDED_vmm_pdmdev_h */

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source: vbox/trunk/include/VBox/vmm/pdmdev.h@ 107113

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