VirtualBox

source: vbox/trunk/include/VBox/vmm/iem-x86-amd64.h

Last change on this file was 100052, checked in by vboxsync, 12 months ago

VMM/IEM: Refactored the enmCpuMode, uCpl, fBypassHandlers, fDisregardLock and fPendingInstruction* IEMCPU members into a single fExec member and associated IEM_F_XXX flag defines. Added more flags needed for recompiled execution. The fExec value is maintained as code is executed, so it does not need to be recalculated in the instruction loops. bugref:10369
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1/** @file
2 * IEM - Interpreted Execution Manager.
3 */
4
5/*
6 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_iem_x86_amd64_h
37#define VBOX_INCLUDED_vmm_iem_x86_amd64_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
43# include <VBox/vmm/hm_vmx.h>
44#endif
45
46
47RT_C_DECLS_BEGIN
48
49/** @addtogroup grp_iem
50 * @{ */
51
52/** @name Operand or addressing mode.
53 * @{ */
54typedef uint8_t IEMMODE;
55#define IEMMODE_16BIT 0
56#define IEMMODE_32BIT 1
57#define IEMMODE_64BIT 2
58/** @} */
59
60
61/** @name IEMTARGETCPU_XXX - IEM target CPU specification.
62 *
63 * This is a gross simpliciation of CPUMMICROARCH for dealing with really old
64 * CPUs which didn't have much in the way of hinting at supported instructions
65 * and features. This slowly changes with the introduction of CPUID with the
66 * Intel Pentium.
67 *
68 * @{
69 */
70/** The dynamic target CPU mode is for getting thru the BIOS and then use
71 * the debugger or modifying instruction behaviour (e.g. HLT) to switch to a
72 * different target CPU. */
73#define IEMTARGETCPU_DYNAMIC UINT32_C(0)
74/** Intel 8086/8088. */
75#define IEMTARGETCPU_8086 UINT32_C(1)
76/** NEC V20/V30.
77 * @remarks must be between 8086 and 80186. */
78#define IEMTARGETCPU_V20 UINT32_C(2)
79/** Intel 80186/80188. */
80#define IEMTARGETCPU_186 UINT32_C(3)
81/** Intel 80286. */
82#define IEMTARGETCPU_286 UINT32_C(4)
83/** Intel 80386. */
84#define IEMTARGETCPU_386 UINT32_C(5)
85/** Intel 80486. */
86#define IEMTARGETCPU_486 UINT32_C(6)
87/** Intel Pentium . */
88#define IEMTARGETCPU_PENTIUM UINT32_C(7)
89/** Intel PentiumPro. */
90#define IEMTARGETCPU_PPRO UINT32_C(8)
91/** A reasonably current CPU, probably newer than the pentium pro when it comes
92 * to the feature set and behaviour. Generally the CPUID info and CPU vendor
93 * dicates the behaviour here. */
94#define IEMTARGETCPU_CURRENT UINT32_C(9)
95/** @} */
96
97
98/** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
99 * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
100#define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \
101 | CPUMCTX_EXTRN_RIP \
102 | CPUMCTX_EXTRN_RFLAGS \
103 | CPUMCTX_EXTRN_SS \
104 | CPUMCTX_EXTRN_CS \
105 | CPUMCTX_EXTRN_CR0 \
106 | CPUMCTX_EXTRN_CR3 \
107 | CPUMCTX_EXTRN_CR4 \
108 | CPUMCTX_EXTRN_APIC_TPR \
109 | CPUMCTX_EXTRN_EFER \
110 | CPUMCTX_EXTRN_DR7 )
111/** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
112 * IEM will import missing bits, callers are encouraged to make these registers
113 * available prior to injection calls if fetching state anyway. */
114#define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \
115 | CPUMCTX_EXTRN_CR2 \
116 | CPUMCTX_EXTRN_SREG_MASK \
117 | CPUMCTX_EXTRN_TABLE_MASK )
118/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
119 * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM
120 * APIs has ensured these are already present.
121 * @note ASSUMES execution engine has checked for instruction breakpoints
122 * during decoding. */
123#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \
124 | CPUMCTX_EXTRN_RFLAGS \
125 | CPUMCTX_EXTRN_SS /* for CPL */ \
126 | CPUMCTX_EXTRN_CS /* for mode */ \
127 | CPUMCTX_EXTRN_CR0 /* for mode */ \
128 | CPUMCTX_EXTRN_EFER /* for mode */ \
129 | CPUMCTX_EXTRN_DR7 /* for debugging - compulsory */ \
130 | CPUMCTX_EXTRN_CR4 /* for hwvirt mode - compulsory atm */ )
131/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
132 * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM
133 * APIs has ensured these are already present.
134 * @note ASSUMES execution engine has checked for instruction breakpoints
135 * during decoding. */
136#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
137 | CPUMCTX_EXTRN_CR3 /* for page tables */ \
138 | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
139 | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )
140
141#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
142/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmlaunchVmresume().
143 * IEM will ASSUME the caller has ensured these are already present. */
144# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
145 | CPUMCTX_EXTRN_CR2 \
146 | CPUMCTX_EXTRN_HWVIRT )
147
148/** The CPUMCTX_EXTRN_XXX mask that the IEM VM-exit code will import on-demand when
149 * needed, primarily because there are several IEM VM-exit interface functions and
150 * some of which may not cause a VM-exit at all.
151 *
152 * This is currently unused, but keeping it here in case we can get away a bit more
153 * fine-grained state handling.
154 *
155 * @note Update HM_CHANGED_VMX_VMEXIT_MASK if something here changes. */
156# define IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK ( CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 \
157 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 \
158 | CPUMCTX_EXTRN_EFER \
159 | CPUMCTX_EXTRN_SYSENTER_MSRS \
160 | CPUMCTX_EXTRN_OTHER_MSRS /* for PAT MSR */ \
161 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS \
162 | CPUMCTX_EXTRN_SREG_MASK \
163 | CPUMCTX_EXTRN_TR \
164 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR \
165 | CPUMCTX_EXTRN_HWVIRT )
166#endif
167
168#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
169/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().
170 * IEM will ASSUME the caller has ensured these are already present. */
171# define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \
172 | CPUMCTX_EXTRN_RAX \
173 | CPUMCTX_EXTRN_RIP \
174 | CPUMCTX_EXTRN_RFLAGS \
175 | CPUMCTX_EXTRN_CS \
176 | CPUMCTX_EXTRN_SS \
177 | CPUMCTX_EXTRN_DS \
178 | CPUMCTX_EXTRN_ES \
179 | CPUMCTX_EXTRN_GDTR \
180 | CPUMCTX_EXTRN_IDTR \
181 | CPUMCTX_EXTRN_CR_MASK \
182 | CPUMCTX_EXTRN_EFER \
183 | CPUMCTX_EXTRN_DR6 \
184 | CPUMCTX_EXTRN_DR7 \
185 | CPUMCTX_EXTRN_OTHER_MSRS \
186 | CPUMCTX_EXTRN_HWVIRT \
187 | CPUMCTX_EXTRN_APIC_TPR \
188 | CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
189
190/** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().
191 * IEM will ASSUME the caller has ensured these are already present. */
192# define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK
193#endif
194
195/** @name Given Instruction Interpreters
196 * @{ */
197VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
198 bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);
199VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
200 bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);
201VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
202VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);
203VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
204VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
205VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iDrReg, uint8_t iGReg);
206VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iDrReg);
207VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPUCC pVCpu, uint8_t cbInstr);
208VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);
209VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPUCC pVCpu, uint8_t cbInstr);
210VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWbinvd(PVMCPUCC pVCpu, uint8_t cbInstr);
211VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvd(PVMCPUCC pVCpu, uint8_t cbInstr);
212VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPUCC pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);
213VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvpcid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDesc,
214 uint64_t uType);
215VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedCpuid(PVMCPUCC pVCpu, uint8_t cbInstr);
216VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdpmc(PVMCPUCC pVCpu, uint8_t cbInstr);
217VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPUCC pVCpu, uint8_t cbInstr);
218VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPUCC pVCpu, uint8_t cbInstr);
219VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPUCC pVCpu, uint8_t cbInstr);
220VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPUCC pVCpu, uint8_t cbInstr);
221VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMonitor(PVMCPUCC pVCpu, uint8_t cbInstr);
222VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMwait(PVMCPUCC pVCpu, uint8_t cbInstr);
223VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedHlt(PVMCPUCC pVCpu, uint8_t cbInstr);
224
225#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
226VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPUCC pVCpu, uint8_t cbInstr);
227VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPUCC pVCpu, uint8_t cbInstr);
228VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPUCC pVCpu, uint8_t cbInstr);
229VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPUCC pVCpu, uint8_t cbInstr);
230VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPUCC pVCpu, uint8_t cbInstr);
231VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPUCC pVCpu, uint8_t cbInstr);
232VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
233#endif
234
235#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
236VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst);
237VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val);
238VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);
239VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu);
240VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu);
241VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending);
242VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
243VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu);
244VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu);
245VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector);
246VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
247VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr);
248VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
249VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
250VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
251VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t uExitQual);
252VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
253VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
254VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
255VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
256VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
257VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId);
258VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
259VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr);
260VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
261# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
262VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);
263VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);
264VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo);
265# endif
266#endif
267/** @} */
268
269/** @defgroup grp_iem_r0 The IEM Host Context Ring-0 API.
270 * @{
271 */
272VMMR0_INT_DECL(int) IEMR0InitVM(PGVM pGVM);
273/** @} */
274
275/** @} */
276
277RT_C_DECLS_END
278
279#endif /* !VBOX_INCLUDED_vmm_iem_x86_amd64_h */
280
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