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hm_vmx.h

Last change on this file was 102023, checked in by vboxsync, 6 months ago
hm_vmx.h: Added new VMCS field encodings.
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File size: 243.9 KB

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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
37	#define VBOX_INCLUDED_vmm_hm_vmx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <iprt/x86.h>
44	#include <iprt/assertcompile.h>
45
46
47	/** @defgroup grp_hm_vmx VMX Types and Definitions
48	* @ingroup grp_hm
49	* @{
50	*/
51
52	/** @name Host-state MSR lazy-restoration flags.
53	* @{
54	*/
55	/** The host MSRs have been saved. */
56	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
57	/** The guest MSRs are loaded and in effect. */
58	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
59	/** @} */
60
61	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
62	* UFC = Unsupported Feature Combination.
63	* @{
64	*/
65	/** Unsupported pin-based VM-execution controls combo. */
66	#define VMX_UFC_CTRL_PIN_EXEC 1
67	/** Unsupported processor-based VM-execution controls combo. */
68	#define VMX_UFC_CTRL_PROC_EXEC 2
69	/** Unsupported move debug register VM-exit combo. */
70	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
71	/** Unsupported VM-entry controls combo. */
72	#define VMX_UFC_CTRL_ENTRY 4
73	/** Unsupported VM-exit controls combo. */
74	#define VMX_UFC_CTRL_EXIT 5
75	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
76	* for storing host MSRs. */
77	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
78	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
79	* for storing guest MSRs. */
80	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
81	/** Invalid VMCS size. */
82	#define VMX_UFC_INVALID_VMCS_SIZE 8
83	/** Unsupported secondary processor-based VM-execution controls combo. */
84	#define VMX_UFC_CTRL_PROC_EXEC2 9
85	/** Invalid unrestricted-guest execution controls combo. */
86	#define VMX_UFC_INVALID_UX_COMBO 10
87	/** EPT flush type not supported. */
88	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
89	/** EPT paging structure memory type is not write-back. */
90	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
91	/** EPT requires INVEPT instr. support but it's not available. */
92	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
93	/** EPT requires page-walk length of 4. */
94	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
95	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
96	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
97	/** LBR stack size cannot be determined for the current CPU. */
98	#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
99	/** LBR stack size of the CPU exceeds our buffer size. */
100	#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
101	/** @} */
102
103	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
104	* VCI = VMCS-field Cache Invalid.
105	* @{
106	*/
107	/** Cache of VM-entry controls invalid. */
108	#define VMX_VCI_CTRL_ENTRY 300
109	/** Cache of VM-exit controls invalid. */
110	#define VMX_VCI_CTRL_EXIT 301
111	/** Cache of pin-based VM-execution controls invalid. */
112	#define VMX_VCI_CTRL_PIN_EXEC 302
113	/** Cache of processor-based VM-execution controls invalid. */
114	#define VMX_VCI_CTRL_PROC_EXEC 303
115	/** Cache of secondary processor-based VM-execution controls invalid. */
116	#define VMX_VCI_CTRL_PROC_EXEC2 304
117	/** Cache of exception bitmap invalid. */
118	#define VMX_VCI_CTRL_XCPT_BITMAP 305
119	/** Cache of TSC offset invalid. */
120	#define VMX_VCI_CTRL_TSC_OFFSET 306
121	/** Cache of tertiary processor-based VM-execution controls invalid. */
122	#define VMX_VCI_CTRL_PROC_EXEC3 307
123	/** @} */
124
125	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
126	* IGS = Invalid Guest State.
127	* @{
128	*/
129	/** An error occurred while checking invalid-guest-state. */
130	#define VMX_IGS_ERROR 500
131	/** The invalid guest-state checks did not find any reason why. */
132	#define VMX_IGS_REASON_NOT_FOUND 501
133	/** CR0 fixed1 bits invalid. */
134	#define VMX_IGS_CR0_FIXED1 502
135	/** CR0 fixed0 bits invalid. */
136	#define VMX_IGS_CR0_FIXED0 503
137	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
138	#define VMX_IGS_CR0_PG_PE_COMBO 504
139	/** CR4 fixed1 bits invalid. */
140	#define VMX_IGS_CR4_FIXED1 505
141	/** CR4 fixed0 bits invalid. */
142	#define VMX_IGS_CR4_FIXED0 506
143	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
144	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
145	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
146	/** CR0.PG not set for long-mode when not using unrestricted guest. */
147	#define VMX_IGS_CR0_PG_LONGMODE 508
148	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
149	#define VMX_IGS_CR4_PAE_LONGMODE 509
150	/** CR4.PCIDE set for 32-bit guest. */
151	#define VMX_IGS_CR4_PCIDE 510
152	/** VMCS' DR7 reserved bits not set to 0. */
153	#define VMX_IGS_DR7_RESERVED 511
154	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
155	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
156	/** VMCS' EFER MSR reserved bits not set to 0. */
157	#define VMX_IGS_EFER_MSR_RESERVED 513
158	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
159	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
160	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
161	* without unrestricted guest. */
162	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
163	/** CS.Attr.P bit invalid. */
164	#define VMX_IGS_CS_ATTR_P_INVALID 516
165	/** CS.Attr reserved bits not set to 0. */
166	#define VMX_IGS_CS_ATTR_RESERVED 517
167	/** CS.Attr.G bit invalid. */
168	#define VMX_IGS_CS_ATTR_G_INVALID 518
169	/** CS is unusable. */
170	#define VMX_IGS_CS_ATTR_UNUSABLE 519
171	/** CS and SS DPL unequal. */
172	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
173	/** CS and SS DPL mismatch. */
174	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
175	/** CS Attr.Type invalid. */
176	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
177	/** CS and SS RPL unequal. */
178	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
179	/** SS.Attr.DPL and SS RPL unequal. */
180	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
181	/** SS.Attr.DPL invalid for segment type. */
182	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
183	/** SS.Attr.Type invalid. */
184	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
185	/** SS.Attr.P bit invalid. */
186	#define VMX_IGS_SS_ATTR_P_INVALID 527
187	/** SS.Attr reserved bits not set to 0. */
188	#define VMX_IGS_SS_ATTR_RESERVED 528
189	/** SS.Attr.G bit invalid. */
190	#define VMX_IGS_SS_ATTR_G_INVALID 529
191	/** DS.Attr.A bit invalid. */
192	#define VMX_IGS_DS_ATTR_A_INVALID 530
193	/** DS.Attr.P bit invalid. */
194	#define VMX_IGS_DS_ATTR_P_INVALID 531
195	/** DS.Attr.DPL and DS RPL unequal. */
196	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
197	/** DS.Attr reserved bits not set to 0. */
198	#define VMX_IGS_DS_ATTR_RESERVED 533
199	/** DS.Attr.G bit invalid. */
200	#define VMX_IGS_DS_ATTR_G_INVALID 534
201	/** DS.Attr.Type invalid. */
202	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
203	/** ES.Attr.A bit invalid. */
204	#define VMX_IGS_ES_ATTR_A_INVALID 536
205	/** ES.Attr.P bit invalid. */
206	#define VMX_IGS_ES_ATTR_P_INVALID 537
207	/** ES.Attr.DPL and DS RPL unequal. */
208	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
209	/** ES.Attr reserved bits not set to 0. */
210	#define VMX_IGS_ES_ATTR_RESERVED 539
211	/** ES.Attr.G bit invalid. */
212	#define VMX_IGS_ES_ATTR_G_INVALID 540
213	/** ES.Attr.Type invalid. */
214	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
215	/** FS.Attr.A bit invalid. */
216	#define VMX_IGS_FS_ATTR_A_INVALID 542
217	/** FS.Attr.P bit invalid. */
218	#define VMX_IGS_FS_ATTR_P_INVALID 543
219	/** FS.Attr.DPL and DS RPL unequal. */
220	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
221	/** FS.Attr reserved bits not set to 0. */
222	#define VMX_IGS_FS_ATTR_RESERVED 545
223	/** FS.Attr.G bit invalid. */
224	#define VMX_IGS_FS_ATTR_G_INVALID 546
225	/** FS.Attr.Type invalid. */
226	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
227	/** GS.Attr.A bit invalid. */
228	#define VMX_IGS_GS_ATTR_A_INVALID 548
229	/** GS.Attr.P bit invalid. */
230	#define VMX_IGS_GS_ATTR_P_INVALID 549
231	/** GS.Attr.DPL and DS RPL unequal. */
232	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
233	/** GS.Attr reserved bits not set to 0. */
234	#define VMX_IGS_GS_ATTR_RESERVED 551
235	/** GS.Attr.G bit invalid. */
236	#define VMX_IGS_GS_ATTR_G_INVALID 552
237	/** GS.Attr.Type invalid. */
238	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
239	/** V86 mode CS.Base invalid. */
240	#define VMX_IGS_V86_CS_BASE_INVALID 554
241	/** V86 mode CS.Limit invalid. */
242	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
243	/** V86 mode CS.Attr invalid. */
244	#define VMX_IGS_V86_CS_ATTR_INVALID 556
245	/** V86 mode SS.Base invalid. */
246	#define VMX_IGS_V86_SS_BASE_INVALID 557
247	/** V86 mode SS.Limit invalid. */
248	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
249	/** V86 mode SS.Attr invalid. */
250	#define VMX_IGS_V86_SS_ATTR_INVALID 559
251	/** V86 mode DS.Base invalid. */
252	#define VMX_IGS_V86_DS_BASE_INVALID 560
253	/** V86 mode DS.Limit invalid. */
254	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
255	/** V86 mode DS.Attr invalid. */
256	#define VMX_IGS_V86_DS_ATTR_INVALID 562
257	/** V86 mode ES.Base invalid. */
258	#define VMX_IGS_V86_ES_BASE_INVALID 563
259	/** V86 mode ES.Limit invalid. */
260	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
261	/** V86 mode ES.Attr invalid. */
262	#define VMX_IGS_V86_ES_ATTR_INVALID 565
263	/** V86 mode FS.Base invalid. */
264	#define VMX_IGS_V86_FS_BASE_INVALID 566
265	/** V86 mode FS.Limit invalid. */
266	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
267	/** V86 mode FS.Attr invalid. */
268	#define VMX_IGS_V86_FS_ATTR_INVALID 568
269	/** V86 mode GS.Base invalid. */
270	#define VMX_IGS_V86_GS_BASE_INVALID 569
271	/** V86 mode GS.Limit invalid. */
272	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
273	/** V86 mode GS.Attr invalid. */
274	#define VMX_IGS_V86_GS_ATTR_INVALID 571
275	/** Longmode CS.Base invalid. */
276	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
277	/** Longmode SS.Base invalid. */
278	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
279	/** Longmode DS.Base invalid. */
280	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
281	/** Longmode ES.Base invalid. */
282	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
283	/** SYSENTER ESP is not canonical. */
284	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
285	/** SYSENTER EIP is not canonical. */
286	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
287	/** PAT MSR invalid. */
288	#define VMX_IGS_PAT_MSR_INVALID 578
289	/** PAT MSR reserved bits not set to 0. */
290	#define VMX_IGS_PAT_MSR_RESERVED 579
291	/** GDTR.Base is not canonical. */
292	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
293	/** IDTR.Base is not canonical. */
294	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
295	/** GDTR.Limit invalid. */
296	#define VMX_IGS_GDTR_LIMIT_INVALID 582
297	/** IDTR.Limit invalid. */
298	#define VMX_IGS_IDTR_LIMIT_INVALID 583
299	/** Longmode RIP is invalid. */
300	#define VMX_IGS_LONGMODE_RIP_INVALID 584
301	/** RFLAGS reserved bits not set to 0. */
302	#define VMX_IGS_RFLAGS_RESERVED 585
303	/** RFLAGS RA1 reserved bits not set to 1. */
304	#define VMX_IGS_RFLAGS_RESERVED1 586
305	/** RFLAGS.VM (V86 mode) invalid. */
306	#define VMX_IGS_RFLAGS_VM_INVALID 587
307	/** RFLAGS.IF invalid. */
308	#define VMX_IGS_RFLAGS_IF_INVALID 588
309	/** Activity state invalid. */
310	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
311	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
312	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
313	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
314	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
315	/** Activity state SIPI WAIT invalid. */
316	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
317	/** Interruptibility state reserved bits not set to 0. */
318	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
319	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
320	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
321	/** Interruptibility state block-by-STI invalid for EFLAGS. */
322	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
323	/** Interruptibility state invalid while trying to deliver external
324	* interrupt. */
325	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
326	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
327	* NMI. */
328	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
329	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
330	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
331	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
332	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
333	/** Interruptibility state block-by-STI (maybe) invalid when trying to
334	* deliver an NMI. */
335	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
336	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
337	* active. */
338	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
339	/** Pending debug exceptions reserved bits not set to 0. */
340	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
341	/** Longmode pending debug exceptions reserved bits not set to 0. */
342	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
343	/** Pending debug exceptions.BS bit is not set when it should be. */
344	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
345	/** Pending debug exceptions.BS bit is not clear when it should be. */
346	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
347	/** VMCS link pointer reserved bits not set to 0. */
348	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
349	/** TR cannot index into LDT, TI bit MBZ. */
350	#define VMX_IGS_TR_TI_INVALID 607
351	/** LDTR cannot index into LDT. TI bit MBZ. */
352	#define VMX_IGS_LDTR_TI_INVALID 608
353	/** TR.Base is not canonical. */
354	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
355	/** FS.Base is not canonical. */
356	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
357	/** GS.Base is not canonical. */
358	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
359	/** LDTR.Base is not canonical. */
360	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
361	/** TR is unusable. */
362	#define VMX_IGS_TR_ATTR_UNUSABLE 613
363	/** TR.Attr.S bit invalid. */
364	#define VMX_IGS_TR_ATTR_S_INVALID 614
365	/** TR is not present. */
366	#define VMX_IGS_TR_ATTR_P_INVALID 615
367	/** TR.Attr reserved bits not set to 0. */
368	#define VMX_IGS_TR_ATTR_RESERVED 616
369	/** TR.Attr.G bit invalid. */
370	#define VMX_IGS_TR_ATTR_G_INVALID 617
371	/** Longmode TR.Attr.Type invalid. */
372	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
373	/** TR.Attr.Type invalid. */
374	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
375	/** CS.Attr.S invalid. */
376	#define VMX_IGS_CS_ATTR_S_INVALID 620
377	/** CS.Attr.DPL invalid. */
378	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
379	/** PAE PDPTE reserved bits not set to 0. */
380	#define VMX_IGS_PAE_PDPTE_RESERVED 623
381	/** VMCS link pointer does not point to a shadow VMCS. */
382	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
383	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
384	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
385	/** @} */
386
387	/** @name VMX VMCS-Read cache indices.
388	* @{
389	*/
390	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
391	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
392	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
393	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
394	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
395	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
396	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
397	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
398	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
399	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
400	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
401	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
402	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
403	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
404	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
405	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
406	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
407	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
408	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
409	/** @} */
410
411
412	/** @name VMX EPT memory type encodings.
413	* @{ */
414	#define VMX_EPT_MT_UC UINT64_C(0)
415	#define VMX_EPT_MT_WC UINT64_C(1)
416	#define VMX_EPT_MT_RSVD_2 UINT64_C(2)
417	#define VMX_EPT_MT_RSVD_3 UINT64_C(3)
418	#define VMX_EPT_MT_WT UINT64_C(4)
419	#define VMX_EPT_MT_WP UINT64_C(5)
420	#define VMX_EPT_MT_WB UINT64_C(6)
421	#define VMX_EPT_MT_RSVD_7 UINT64_C(7)
422	/** @} */
423
424
425	/** @name VMX Extended Page Tables (EPT) Common Bits.
426	* @{ */
427	/** Bit 0 - Readable (we often think of it as present). */
428	#define EPT_E_BIT_READ 0
429	#define EPT_E_READ RT_BIT_64(EPT_E_BIT_READ) /*< @see EPT_E_BIT_READ /
430	/** Bit 1 - Writable. */
431	#define EPT_E_BIT_WRITE 1
432	#define EPT_E_WRITE RT_BIT_64(EPT_E_BIT_WRITE) /*< @see EPT_E_BIT_WRITE /
433	/** Bit 2 - Executable.
434	* @note This controls supervisor instruction fetching if mode-based
435	* execution control is enabled. */
436	#define EPT_E_BIT_EXECUTE 2
437	#define EPT_E_EXECUTE RT_BIT_64(EPT_E_BIT_EXECUTE) /*< @see EPT_E_BIT_EXECUTE /
438	/** Bits 3-5 - Memory type mask (leaf only, MBZ).
439	* The memory type is only applicable for leaf entries and MBZ for
440	* non-leaf (causes miconfiguration exit). */
441	#define EPT_E_MEMTYPE_MASK UINT64_C(0x0038)
442	/** Bits 3-5 - Memory type shifted mask. */
443	#define EPT_E_MEMTYPE_SMASK UINT64_C(0x0007)
444	/** Bits 3-5 - Memory type shift count. */
445	#define EPT_E_MEMTYPE_SHIFT 3
446	/** Bits 3-5 - Memory type: UC (Uncacheable). */
447	#define EPT_E_MEMTYPE_UC (VMX_EPT_MT_UC << EPT_E_MEMTYPE_SHIFT)
448	/** Bits 3-5 - Memory type: WC (Write Combining). */
449	#define EPT_E_MEMTYPE_WC (VMX_EPT_MT_WC << EPT_E_MEMTYPE_SHIFT)
450	/** Bits 3-5 - Memory type: Invalid (2). */
451	#define EPT_E_MEMTYPE_INVALID_2 (VMX_EPT_MT_RSVD_2 << EPT_E_MEMTYPE_SHIFT)
452	/** Bits 3-5 - Memory type: Invalid (3). */
453	#define EPT_E_MEMTYPE_INVALID_3 (VMX_EPT_MT_RSVD_3 << EPT_E_MEMTYPE_SHIFT)
454	/** Bits 3-5 - Memory type: WT (Write Through). */
455	#define EPT_E_MEMTYPE_WT (VMX_EPT_MT_WT << EPT_E_MEMTYPE_SHIFT)
456	/** Bits 3-5 - Memory type: WP (Write Protected). */
457	#define EPT_E_MEMTYPE_WP (VMX_EPT_MT_WP << EPT_E_MEMTYPE_SHIFT)
458	/** Bits 3-5 - Memory type: WB (Write Back). */
459	#define EPT_E_MEMTYPE_WB (VMX_EPT_MT_WB << EPT_E_MEMTYPE_SHIFT)
460	/** Bits 3-5 - Memory type: Invalid (7). */
461	#define EPT_E_MEMTYPE_INVALID_7 (VMX_EPT_MT_RSVD_7 << EPT_E_MEMTYPE_SHIFT)
462	/** Bit 6 - Ignore page attribute table (leaf, MBZ). */
463	#define EPT_E_BIT_IGNORE_PAT 6
464	#define EPT_E_IGNORE_PAT RT_BIT_64(EPT_E_BIT_IGNORE_PAT) /*< @see EPT_E_BIT_IGNORE_PAT /
465	/** Bit 7 - Leaf entry (MBZ in PML4, ignored in PT). */
466	#define EPT_E_BIT_LEAF 7
467	#define EPT_E_LEAF RT_BIT_64(EPT_E_BIT_LEAF) /*< @see EPT_E_BIT_LEAF /
468	/** Bit 8 - Accessed (all levels).
469	* @note Ignored and not written when EPTP bit 6 is 0. */
470	#define EPT_E_BIT_ACCESSED 8
471	#define EPT_E_ACCESSED RT_BIT_64(EPT_E_BIT_ACCESSED) /*< @see EPT_E_BIT_ACCESSED /
472	/** Bit 9 - Dirty (leaf only).
473	* @note Ignored and not written when EPTP bit 6 is 0. */
474	#define EPT_E_BIT_DIRTY 9
475	#define EPT_E_DIRTY RT_BIT_64(EPT_E_BIT_DIRTY) /*< @see EPT_E_BIT_DIRTY /
476	/** Bit 10 - Executable for usermode.
477	* @note This ignored if mode-based execution control is disabled. */
478	#define EPT_E_BIT_USER_EXECUTE 10
479	#define EPT_E_USER_EXECUTE RT_BIT_64(EPT_E_BIT_USER_EXECUTE) /*< @see EPT_E_BIT_USER_EXECUTE /
480	/* Bit 11 is always ignored. */
481	/** Bits 12-51 - Physical Page number of the next level. */
482	#define EPT_E_PG_MASK UINT64_C(0x000ffffffffff000)
483	/** Bit 58 - Page-write access (leaf only, ignored).
484	* @note Ignored if EPT page-write control is disabled. */
485	#define EPT_E_BIT_PAGING_WRITE 58
486	#define EPT_E_PAGING_WRITE RT_BIT_64(EPT_E_BIT_PAGING_WRITE) /*< @see EPT_E_BIT_PAGING_WRITE/
487	/* Bit 59 is always ignored. */
488	/** Bit 60 - Supervisor shadow stack (leaf only, ignored).
489	* @note Ignored if EPT bit 7 is 0. */
490	#define EPT_E_BIT_SUPER_SHW_STACK 60
491	#define EPT_E_SUPER_SHW_STACK RT_BIT_64(EPT_E_BIT_SUPER_SHW_STACK) /*< @see EPT_E_BIT_SUPER_SHW_STACK /
492	/** Bit 61 - Sub-page write permission (leaf only, ignored).
493	* @note Ignored if sub-page write permission for EPT is disabled. */
494	#define EPT_E_BIT_SUBPAGE_WRITE_PERM 61
495	#define EPT_E_SUBPAGE_WRITE_PERM RT_BIT_64(EPT_E_BIT_SUBPAGE_WRITE_PERM) /*< @see EPT_E_BIT_SUBPAGE_WRITE_PERM/
496	/* Bit 62 is always ignored. */
497	/** Bit 63 - Suppress \#VE (leaf only, ignored).
498	* @note Ignored if EPT violation to \#VE conversion is disabled. */
499	#define EPT_E_BIT_SUPPRESS_VE 63
500	#define EPT_E_SUPPRESS_VE RT_BIT_64(EPT_E_BIT_SUPPRESS_VE) /*< @see EPT_E_BIT_SUPPRESS_VE /
501	/** @} */
502
503
504	/**@name Bit fields for common EPT attributes.
505	@{ */
506	/** Read access. */
507	#define VMX_BF_EPT_PT_READ_SHIFT 0
508	#define VMX_BF_EPT_PT_READ_MASK UINT64_C(0x0000000000000001)
509	/** Write access. */
510	#define VMX_BF_EPT_PT_WRITE_SHIFT 1
511	#define VMX_BF_EPT_PT_WRITE_MASK UINT64_C(0x0000000000000002)
512	/** Execute access or execute access for supervisor-mode linear-addresses. */
513	#define VMX_BF_EPT_PT_EXECUTE_SHIFT 2
514	#define VMX_BF_EPT_PT_EXECUTE_MASK UINT64_C(0x0000000000000004)
515	/** EPT memory type. */
516	#define VMX_BF_EPT_PT_MEMTYPE_SHIFT 3
517	#define VMX_BF_EPT_PT_MEMTYPE_MASK UINT64_C(0x0000000000000038)
518	/** Ignore PAT. */
519	#define VMX_BF_EPT_PT_IGNORE_PAT_SHIFT 6
520	#define VMX_BF_EPT_PT_IGNORE_PAT_MASK UINT64_C(0x0000000000000040)
521	/** Ignored (bit 7). */
522	#define VMX_BF_EPT_PT_IGN_7_SHIFT 7
523	#define VMX_BF_EPT_PT_IGN_7_MASK UINT64_C(0x0000000000000080)
524	/** Accessed flag. */
525	#define VMX_BF_EPT_PT_ACCESSED_SHIFT 8
526	#define VMX_BF_EPT_PT_ACCESSED_MASK UINT64_C(0x0000000000000100)
527	/** Dirty flag. */
528	#define VMX_BF_EPT_PT_DIRTY_SHIFT 9
529	#define VMX_BF_EPT_PT_DIRTY_MASK UINT64_C(0x0000000000000200)
530	/** Execute access for user-mode linear addresses. */
531	#define VMX_BF_EPT_PT_EXECUTE_USER_SHIFT 10
532	#define VMX_BF_EPT_PT_EXECUTE_USER_MASK UINT64_C(0x0000000000000400)
533	/** Ignored (bit 59:11). */
534	#define VMX_BF_EPT_PT_IGN_59_11_SHIFT 11
535	#define VMX_BF_EPT_PT_IGN_59_11_MASK UINT64_C(0x0ffffffffffff800)
536	/** Supervisor shadow stack. */
537	#define VMX_BF_EPT_PT_SUPER_SHW_STACK_SHIFT 60
538	#define VMX_BF_EPT_PT_SUPER_SHW_STACK_MASK UINT64_C(0x1000000000000000)
539	/** Ignored (bits 62:61). */
540	#define VMX_BF_EPT_PT_IGN_62_61_SHIFT 61
541	#define VMX_BF_EPT_PT_IGN_62_61_MASK UINT64_C(0x6000000000000000)
542	/** Suppress \#VE. */
543	#define VMX_BF_EPT_PT_SUPPRESS_VE_SHIFT 63
544	#define VMX_BF_EPT_PT_SUPPRESS_VE_MASK UINT64_C(0x8000000000000000)
545	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_PT_, UINT64_C(0), UINT64_MAX,
546	(READ, WRITE, EXECUTE, MEMTYPE, IGNORE_PAT, IGN_7, ACCESSED, DIRTY, EXECUTE_USER, IGN_59_11,
547	SUPER_SHW_STACK, IGN_62_61, SUPPRESS_VE));
548	/** @} */
549
550
551	/** @name VMX Extended Page Tables (EPT) Structures
552	* @{
553	*/
554
555	/**
556	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
557	*/
558	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
559
560	/**
561	* EPT present mask.
562	* These are ONLY the common bits in all EPT page-table entries which does
563	* not rely on any CPU feature. It isn't necessarily the complete mask (e.g. when
564	* mode-based excute control is active).
565	*/
566	#define EPT_PRESENT_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE)
567
568	/**
569	* EPT Page Directory Pointer Entry. Bit view.
570	* In accordance with the VT-x spec.
571	*
572	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
573	* this did cause trouble with one compiler/version).
574	*/
575	typedef struct EPTPML4EBITS
576	{
577	/** Present bit. */
578	RT_GCC_EXTENSION uint64_t u1Present : 1;
579	/** Writable bit. */
580	RT_GCC_EXTENSION uint64_t u1Write : 1;
581	/** Executable bit. */
582	RT_GCC_EXTENSION uint64_t u1Execute : 1;
583	/** Reserved (must be 0). */
584	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
585	/** Available for software. */
586	RT_GCC_EXTENSION uint64_t u4Available : 4;
587	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
588	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
589	/** Available for software. */
590	RT_GCC_EXTENSION uint64_t u12Available : 12;
591	} EPTPML4EBITS;
592	AssertCompileSize(EPTPML4EBITS, 8);
593
594	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
595	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
596	/** The page shift to get the PML4 index. */
597	#define EPT_PML4_SHIFT X86_PML4_SHIFT
598	/** The PML4 index mask (apply to a shifted page address). */
599	#define EPT_PML4_MASK X86_PML4_MASK
600	/** Bits - - EPT - PML4 MBZ mask. */
601	#define EPT_PML4E_MBZ_MASK UINT64_C(0x00000000000000f8)
602	/** Mask of all possible EPT PML4E attribute bits. */
603	#define EPT_PML4E_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
604
605	/**
606	* EPT PML4E.
607	* In accordance with the VT-x spec.
608	*/
609	typedef union EPTPML4E
610	{
611	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
612	/** Normal view. */
613	EPTPML4EBITS n;
614	#endif
615	/** Unsigned integer view. */
616	X86PGPAEUINT u;
617	/** 64 bit unsigned integer view. */
618	uint64_t au64[1];
619	/** 32 bit unsigned integer view. */
620	uint32_t au32[2];
621	} EPTPML4E;
622	AssertCompileSize(EPTPML4E, 8);
623	/** Pointer to a PML4 table entry. */
624	typedef EPTPML4E *PEPTPML4E;
625	/** Pointer to a const PML4 table entry. */
626	typedef const EPTPML4E *PCEPTPML4E;
627
628	/**
629	* EPT PML4 Table.
630	* In accordance with the VT-x spec.
631	*/
632	typedef struct EPTPML4
633	{
634	EPTPML4E a[EPT_PG_ENTRIES];
635	} EPTPML4;
636	AssertCompileSize(EPTPML4, 0x1000);
637	/** Pointer to an EPT PML4 Table. */
638	typedef EPTPML4 *PEPTPML4;
639	/** Pointer to a const EPT PML4 Table. */
640	typedef const EPTPML4 *PCEPTPML4;
641
642
643	/**
644	* EPT Page Directory Pointer Entry. Bit view.
645	* In accordance with the VT-x spec.
646	*/
647	typedef struct EPTPDPTEBITS
648	{
649	/** Present bit. */
650	RT_GCC_EXTENSION uint64_t u1Present : 1;
651	/** Writable bit. */
652	RT_GCC_EXTENSION uint64_t u1Write : 1;
653	/** Executable bit. */
654	RT_GCC_EXTENSION uint64_t u1Execute : 1;
655	/** Reserved (must be 0). */
656	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
657	/** Available for software. */
658	RT_GCC_EXTENSION uint64_t u4Available : 4;
659	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
660	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
661	/** Available for software. */
662	RT_GCC_EXTENSION uint64_t u12Available : 12;
663	} EPTPDPTEBITS;
664	AssertCompileSize(EPTPDPTEBITS, 8);
665
666	/** Bit 7 - - EPT - PDPTE maps a 1GB page. */
667	#define EPT_PDPTE1G_SIZE_MASK RT_BIT_64(7)
668	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
669	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
670	/** Bits 30-51 - - EPT - Physical Page number of the 1G large page. */
671	#define EPT_PDPTE1G_PG_MASK X86_PDPE1G_PG_MASK
672
673	/** The page shift to get the PDPT index. */
674	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
675	/** The PDPT index mask (apply to a shifted page address). */
676	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
677	/** Bits 3-7 - - EPT - PDPTE MBZ Mask. */
678	#define EPT_PDPTE_MBZ_MASK UINT64_C(0x00000000000000f8)
679	/** Bits 12-29 - - EPT - 1GB PDPTE MBZ Mask. */
680	#define EPT_PDPTE1G_MBZ_MASK UINT64_C(0x000000003ffff000)
681	/** Mask of all possible EPT PDPTE (1GB) attribute bits. */
682	#define EPT_PDPTE1G_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
683	\| EPT_E_ACCESSED \| EPT_E_DIRTY \| EPT_E_USER_EXECUTE)
684	/** Mask of all possible EPT PDPTE attribute bits. */
685	#define EPT_PDPTE_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
686	/** */
687
688	/**
689	* EPT Page Directory Pointer.
690	* In accordance with the VT-x spec.
691	*/
692	typedef union EPTPDPTE
693	{
694	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
695	/** Normal view. */
696	EPTPDPTEBITS n;
697	#endif
698	/** Unsigned integer view. */
699	X86PGPAEUINT u;
700	/** 64 bit unsigned integer view. */
701	uint64_t au64[1];
702	/** 32 bit unsigned integer view. */
703	uint32_t au32[2];
704	} EPTPDPTE;
705	AssertCompileSize(EPTPDPTE, 8);
706	/** Pointer to an EPT Page Directory Pointer Entry. */
707	typedef EPTPDPTE *PEPTPDPTE;
708	/** Pointer to a const EPT Page Directory Pointer Entry. */
709	typedef const EPTPDPTE *PCEPTPDPTE;
710
711	/**
712	* EPT Page Directory Pointer Table.
713	* In accordance with the VT-x spec.
714	*/
715	typedef struct EPTPDPT
716	{
717	EPTPDPTE a[EPT_PG_ENTRIES];
718	} EPTPDPT;
719	AssertCompileSize(EPTPDPT, 0x1000);
720	/** Pointer to an EPT Page Directory Pointer Table. */
721	typedef EPTPDPT *PEPTPDPT;
722	/** Pointer to a const EPT Page Directory Pointer Table. */
723	typedef const EPTPDPT *PCEPTPDPT;
724
725
726	/**
727	* EPT Page Directory Table Entry. Bit view.
728	* In accordance with the VT-x spec.
729	*/
730	typedef struct EPTPDEBITS
731	{
732	/** Present bit. */
733	RT_GCC_EXTENSION uint64_t u1Present : 1;
734	/** Writable bit. */
735	RT_GCC_EXTENSION uint64_t u1Write : 1;
736	/** Executable bit. */
737	RT_GCC_EXTENSION uint64_t u1Execute : 1;
738	/** Reserved (must be 0). */
739	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
740	/** Big page (must be 0 here). */
741	RT_GCC_EXTENSION uint64_t u1Size : 1;
742	/** Available for software. */
743	RT_GCC_EXTENSION uint64_t u4Available : 4;
744	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
745	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
746	/** Available for software. */
747	RT_GCC_EXTENSION uint64_t u12Available : 12;
748	} EPTPDEBITS;
749	AssertCompileSize(EPTPDEBITS, 8);
750
751	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
752	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
753	/** The page shift to get the PD index. */
754	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
755	/** The PD index mask (apply to a shifted page address). */
756	#define EPT_PD_MASK X86_PD_PAE_MASK
757	/** Bits 3-7 - EPT - PDE MBZ Mask. */
758	#define EPT_PDE_MBZ_MASK UINT64_C(0x00000000000000f8)
759	/** Mask of all possible EPT PDE (2M) attribute bits. */
760	#define EPT_PDE2M_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
761	\| EPT_E_ACCESSED \| EPT_E_DIRTY \| EPT_E_USER_EXECUTE)
762	/** Mask of all possible EPT PDE attribute bits. */
763	#define EPT_PDE_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
764
765
766	/**
767	* EPT 2MB Page Directory Table Entry. Bit view.
768	* In accordance with the VT-x spec.
769	*/
770	typedef struct EPTPDE2MBITS
771	{
772	/** Present bit. */
773	RT_GCC_EXTENSION uint64_t u1Present : 1;
774	/** Writable bit. */
775	RT_GCC_EXTENSION uint64_t u1Write : 1;
776	/** Executable bit. */
777	RT_GCC_EXTENSION uint64_t u1Execute : 1;
778	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
779	RT_GCC_EXTENSION uint64_t u3EMT : 3;
780	/** Ignore PAT memory type */
781	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
782	/** Big page (must be 1 here). */
783	RT_GCC_EXTENSION uint64_t u1Size : 1;
784	/** Available for software. */
785	RT_GCC_EXTENSION uint64_t u4Available : 4;
786	/** Reserved (must be 0). */
787	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
788	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
789	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
790	/** Available for software. */
791	RT_GCC_EXTENSION uint64_t u12Available : 12;
792	} EPTPDE2MBITS;
793	AssertCompileSize(EPTPDE2MBITS, 8);
794
795	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
796	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
797	/** Bits 20-12 - - EPT - PDE 2M MBZ Mask. */
798	#define EPT_PDE2M_MBZ_MASK UINT64_C(0x00000000001ff000)
799
800
801	/**
802	* EPT Page Directory Table Entry.
803	* In accordance with the VT-x spec.
804	*/
805	typedef union EPTPDE
806	{
807	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
808	/** Normal view. */
809	EPTPDEBITS n;
810	/** 2MB view (big). */
811	EPTPDE2MBITS b;
812	#endif
813	/** Unsigned integer view. */
814	X86PGPAEUINT u;
815	/** 64 bit unsigned integer view. */
816	uint64_t au64[1];
817	/** 32 bit unsigned integer view. */
818	uint32_t au32[2];
819	} EPTPDE;
820	AssertCompileSize(EPTPDE, 8);
821	/** Pointer to an EPT Page Directory Table Entry. */
822	typedef EPTPDE *PEPTPDE;
823	/** Pointer to a const EPT Page Directory Table Entry. */
824	typedef const EPTPDE *PCEPTPDE;
825
826	/**
827	* EPT Page Directory Table.
828	* In accordance with the VT-x spec.
829	*/
830	typedef struct EPTPD
831	{
832	EPTPDE a[EPT_PG_ENTRIES];
833	} EPTPD;
834	AssertCompileSize(EPTPD, 0x1000);
835	/** Pointer to an EPT Page Directory Table. */
836	typedef EPTPD *PEPTPD;
837	/** Pointer to a const EPT Page Directory Table. */
838	typedef const EPTPD *PCEPTPD;
839
840	/**
841	* EPT Page Table Entry. Bit view.
842	* In accordance with the VT-x spec.
843	*/
844	typedef struct EPTPTEBITS
845	{
846	/** 0 - Present bit.
847	* @remarks This is a convenience "misnomer". The bit actually indicates read access
848	* and the CPU will consider an entry with any of the first three bits set
849	* as present. Since all our valid entries will have this bit set, it can
850	* be used as a present indicator and allow some code sharing. */
851	RT_GCC_EXTENSION uint64_t u1Present : 1;
852	/** 1 - Writable bit. */
853	RT_GCC_EXTENSION uint64_t u1Write : 1;
854	/** 2 - Executable bit. */
855	RT_GCC_EXTENSION uint64_t u1Execute : 1;
856	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
857	RT_GCC_EXTENSION uint64_t u3EMT : 3;
858	/** 6 - Ignore PAT memory type */
859	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
860	/** 11:7 - Available for software. */
861	RT_GCC_EXTENSION uint64_t u5Available : 5;
862	/** 51:12 - Physical address of page. Restricted by maximum physical
863	* address width of the cpu. */
864	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
865	/** 63:52 - Available for software. */
866	RT_GCC_EXTENSION uint64_t u12Available : 12;
867	} EPTPTEBITS;
868	AssertCompileSize(EPTPTEBITS, 8);
869
870	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
871	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
872	/** The page shift to get the EPT PTE index. */
873	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
874	/** The EPT PT index mask (apply to a shifted page address). */
875	#define EPT_PT_MASK X86_PT_PAE_MASK
876	/** No bits - - EPT - PTE MBZ bits. */
877	#define EPT_PTE_MBZ_MASK UINT64_C(0x0000000000000000)
878	/** Mask of all possible EPT PTE attribute bits. */
879	#define EPT_PTE_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
880	\| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
881
882
883	/**
884	* EPT Page Table Entry.
885	* In accordance with the VT-x spec.
886	*/
887	typedef union EPTPTE
888	{
889	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
890	/** Normal view. */
891	EPTPTEBITS n;
892	#endif
893	/** Unsigned integer view. */
894	X86PGPAEUINT u;
895	/** 64 bit unsigned integer view. */
896	uint64_t au64[1];
897	/** 32 bit unsigned integer view. */
898	uint32_t au32[2];
899	} EPTPTE;
900	AssertCompileSize(EPTPTE, 8);
901	/** Pointer to an EPT Page Directory Table Entry. */
902	typedef EPTPTE *PEPTPTE;
903	/** Pointer to a const EPT Page Directory Table Entry. */
904	typedef const EPTPTE *PCEPTPTE;
905
906	/**
907	* EPT Page Table.
908	* In accordance with the VT-x spec.
909	*/
910	typedef struct EPTPT
911	{
912	EPTPTE a[EPT_PG_ENTRIES];
913	} EPTPT;
914	AssertCompileSize(EPTPT, 0x1000);
915	/** Pointer to an extended page table. */
916	typedef EPTPT *PEPTPT;
917	/** Pointer to a const extended table. */
918	typedef const EPTPT *PCEPTPT;
919
920	/** EPTP page mask for the EPT PML4 table. */
921	#define EPT_EPTP_PG_MASK X86_CR3_AMD64_PAGE_MASK
922	/** @} */
923
924	/**
925	* VMX VPID flush types.
926	* Valid enum members are in accordance with the VT-x spec.
927	*/
928	typedef enum
929	{
930	/** Invalidate a specific page. */
931	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
932	/** Invalidate one context (specific VPID). */
933	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
934	/** Invalidate all contexts (all VPIDs). */
935	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
936	/** Invalidate a single VPID context retaining global mappings. */
937	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
938	/** Unsupported by VirtualBox. */
939	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
940	/** Unsupported by CPU. */
941	VMXTLBFLUSHVPID_NONE = 0xbad1
942	} VMXTLBFLUSHVPID;
943	AssertCompileSize(VMXTLBFLUSHVPID, 4);
944	/** Mask of all valid INVVPID flush types. */
945	#define VMX_INVVPID_VALID_MASK ( VMXTLBFLUSHVPID_INDIV_ADDR \
946	\| VMXTLBFLUSHVPID_SINGLE_CONTEXT \
947	\| VMXTLBFLUSHVPID_ALL_CONTEXTS \
948	\| VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
949
950	/**
951	* VMX EPT flush types.
952	* @note Valid enums values are in accordance with the VT-x spec.
953	*/
954	typedef enum
955	{
956	/** Invalidate one context (specific EPT). */
957	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
958	/* Invalidate all contexts (all EPTs) */
959	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
960	/** Unsupported by VirtualBox. */
961	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
962	/** Unsupported by CPU. */
963	VMXTLBFLUSHEPT_NONE = 0xbad1
964	} VMXTLBFLUSHEPT;
965	AssertCompileSize(VMXTLBFLUSHEPT, 4);
966	/** Mask of all valid INVEPT flush types. */
967	#define VMX_INVEPT_VALID_MASK ( VMXTLBFLUSHEPT_SINGLE_CONTEXT \
968	\| VMXTLBFLUSHEPT_ALL_CONTEXTS)
969
970	/**
971	* VMX Posted Interrupt Descriptor.
972	* In accordance with the VT-x spec.
973	*/
974	typedef struct VMXPOSTEDINTRDESC
975	{
976	uint32_t aVectorBitmap[8];
977	uint32_t fOutstandingNotification : 1;
978	uint32_t uReserved0 : 31;
979	uint8_t au8Reserved0[28];
980	} VMXPOSTEDINTRDESC;
981	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
982	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
983	/** Pointer to a posted interrupt descriptor. */
984	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
985	/** Pointer to a const posted interrupt descriptor. */
986	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
987
988	/**
989	* VMX VMCS revision identifier.
990	* In accordance with the VT-x spec.
991	*/
992	typedef union
993	{
994	struct
995	{
996	/** Revision identifier. */
997	uint32_t u31RevisionId : 31;
998	/** Whether this is a shadow VMCS. */
999	uint32_t fIsShadowVmcs : 1;
1000	} n;
1001	/* The unsigned integer view. */
1002	uint32_t u;
1003	} VMXVMCSREVID;
1004	AssertCompileSize(VMXVMCSREVID, 4);
1005	/** Pointer to the VMXVMCSREVID union. */
1006	typedef VMXVMCSREVID *PVMXVMCSREVID;
1007	/** Pointer to a const VMXVMCSREVID union. */
1008	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
1009
1010	/**
1011	* VMX VM-exit instruction information.
1012	* In accordance with the VT-x spec.
1013	*/
1014	typedef union
1015	{
1016	/** Plain unsigned int representation. */
1017	uint32_t u;
1018
1019	/** INS and OUTS information. */
1020	struct
1021	{
1022	uint32_t u7Reserved0 : 7;
1023	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1024	uint32_t u3AddrSize : 3;
1025	uint32_t u5Reserved1 : 5;
1026	/** The segment register (X86_SREG_XXX). */
1027	uint32_t iSegReg : 3;
1028	uint32_t uReserved2 : 14;
1029	} StrIo;
1030
1031	/** INVEPT, INVPCID, INVVPID information. */
1032	struct
1033	{
1034	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1035	uint32_t u2Scaling : 2;
1036	uint32_t u5Undef0 : 5;
1037	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1038	uint32_t u3AddrSize : 3;
1039	/** Cleared to 0. */
1040	uint32_t u1Cleared0 : 1;
1041	uint32_t u4Undef0 : 4;
1042	/** The segment register (X86_SREG_XXX). */
1043	uint32_t iSegReg : 3;
1044	/** The index register (X86_GREG_XXX). */
1045	uint32_t iIdxReg : 4;
1046	/** Set if index register is invalid. */
1047	uint32_t fIdxRegInvalid : 1;
1048	/** The base register (X86_GREG_XXX). */
1049	uint32_t iBaseReg : 4;
1050	/** Set if base register is invalid. */
1051	uint32_t fBaseRegInvalid : 1;
1052	/** Register 2 (X86_GREG_XXX). */
1053	uint32_t iReg2 : 4;
1054	} Inv;
1055
1056	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
1057	struct
1058	{
1059	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1060	uint32_t u2Scaling : 2;
1061	uint32_t u5Reserved0 : 5;
1062	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1063	uint32_t u3AddrSize : 3;
1064	/** Cleared to 0. */
1065	uint32_t u1Cleared0 : 1;
1066	uint32_t u4Reserved0 : 4;
1067	/** The segment register (X86_SREG_XXX). */
1068	uint32_t iSegReg : 3;
1069	/** The index register (X86_GREG_XXX). */
1070	uint32_t iIdxReg : 4;
1071	/** Set if index register is invalid. */
1072	uint32_t fIdxRegInvalid : 1;
1073	/** The base register (X86_GREG_XXX). */
1074	uint32_t iBaseReg : 4;
1075	/** Set if base register is invalid. */
1076	uint32_t fBaseRegInvalid : 1;
1077	/** Register 2 (X86_GREG_XXX). */
1078	uint32_t iReg2 : 4;
1079	} VmxXsave;
1080
1081	/** LIDT, LGDT, SIDT, SGDT information. */
1082	struct
1083	{
1084	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1085	uint32_t u2Scaling : 2;
1086	uint32_t u5Undef0 : 5;
1087	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1088	uint32_t u3AddrSize : 3;
1089	/** Always cleared to 0. */
1090	uint32_t u1Cleared0 : 1;
1091	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
1092	uint32_t uOperandSize : 1;
1093	uint32_t u3Undef0 : 3;
1094	/** The segment register (X86_SREG_XXX). */
1095	uint32_t iSegReg : 3;
1096	/** The index register (X86_GREG_XXX). */
1097	uint32_t iIdxReg : 4;
1098	/** Set if index register is invalid. */
1099	uint32_t fIdxRegInvalid : 1;
1100	/** The base register (X86_GREG_XXX). */
1101	uint32_t iBaseReg : 4;
1102	/** Set if base register is invalid. */
1103	uint32_t fBaseRegInvalid : 1;
1104	/** Instruction identity (VMX_INSTR_ID_XXX). */
1105	uint32_t u2InstrId : 2;
1106	uint32_t u2Undef0 : 2;
1107	} GdtIdt;
1108
1109	/** LLDT, LTR, SLDT, STR information. */
1110	struct
1111	{
1112	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1113	uint32_t u2Scaling : 2;
1114	uint32_t u1Undef0 : 1;
1115	/** Register 1 (X86_GREG_XXX). */
1116	uint32_t iReg1 : 4;
1117	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1118	uint32_t u3AddrSize : 3;
1119	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1120	uint32_t fIsRegOperand : 1;
1121	uint32_t u4Undef0 : 4;
1122	/** The segment register (X86_SREG_XXX). */
1123	uint32_t iSegReg : 3;
1124	/** The index register (X86_GREG_XXX). */
1125	uint32_t iIdxReg : 4;
1126	/** Set if index register is invalid. */
1127	uint32_t fIdxRegInvalid : 1;
1128	/** The base register (X86_GREG_XXX). */
1129	uint32_t iBaseReg : 4;
1130	/** Set if base register is invalid. */
1131	uint32_t fBaseRegInvalid : 1;
1132	/** Instruction identity (VMX_INSTR_ID_XXX). */
1133	uint32_t u2InstrId : 2;
1134	uint32_t u2Undef0 : 2;
1135	} LdtTr;
1136
1137	/** RDRAND, RDSEED information. */
1138	struct
1139	{
1140	uint32_t u3Undef0 : 3;
1141	/** Destination register (X86_GREG_XXX). */
1142	uint32_t iReg1 : 4;
1143	uint32_t u4Undef0 : 4;
1144	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1145	uint32_t u2OperandSize : 2;
1146	uint32_t u19Undef0 : 19;
1147	} RdrandRdseed;
1148
1149	/** VMREAD, VMWRITE information. */
1150	struct
1151	{
1152	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1153	uint32_t u2Scaling : 2;
1154	uint32_t u1Undef0 : 1;
1155	/** Register 1 (X86_GREG_XXX). */
1156	uint32_t iReg1 : 4;
1157	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1158	uint32_t u3AddrSize : 3;
1159	/** Memory or register operand. */
1160	uint32_t fIsRegOperand : 1;
1161	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1162	uint32_t u4Undef0 : 4;
1163	/** The segment register (X86_SREG_XXX). */
1164	uint32_t iSegReg : 3;
1165	/** The index register (X86_GREG_XXX). */
1166	uint32_t iIdxReg : 4;
1167	/** Set if index register is invalid. */
1168	uint32_t fIdxRegInvalid : 1;
1169	/** The base register (X86_GREG_XXX). */
1170	uint32_t iBaseReg : 4;
1171	/** Set if base register is invalid. */
1172	uint32_t fBaseRegInvalid : 1;
1173	/** Register 2 (X86_GREG_XXX). */
1174	uint32_t iReg2 : 4;
1175	} VmreadVmwrite;
1176
1177	/** LOADIWKEY information. */
1178	struct
1179	{
1180	uint32_t u2Undef0 : 3;
1181	/** First XMM register operand. */
1182	uint32_t u4XmmReg1 : 4;
1183	uint32_t u23Undef1 : 21;
1184	/** Second XMM register operand. */
1185	uint32_t u4XmmReg2 : 4;
1186	} LoadIwkey;
1187
1188	/** This is a combination field of all instruction information. Note! Not all field
1189	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1190	* specialized fields are overwritten by their generic counterparts (e.g. no
1191	* instruction identity field). */
1192	struct
1193	{
1194	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1195	uint32_t u2Scaling : 2;
1196	uint32_t u1Undef0 : 1;
1197	/** Register 1 (X86_GREG_XXX). */
1198	uint32_t iReg1 : 4;
1199	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1200	uint32_t u3AddrSize : 3;
1201	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1202	uint32_t fIsRegOperand : 1;
1203	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1204	uint32_t uOperandSize : 2;
1205	uint32_t u2Undef0 : 2;
1206	/** The segment register (X86_SREG_XXX). */
1207	uint32_t iSegReg : 3;
1208	/** The index register (X86_GREG_XXX). */
1209	uint32_t iIdxReg : 4;
1210	/** Set if index register is invalid. */
1211	uint32_t fIdxRegInvalid : 1;
1212	/** The base register (X86_GREG_XXX). */
1213	uint32_t iBaseReg : 4;
1214	/** Set if base register is invalid. */
1215	uint32_t fBaseRegInvalid : 1;
1216	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1217	uint32_t iReg2 : 4;
1218	} All;
1219	} VMXEXITINSTRINFO;
1220	AssertCompileSize(VMXEXITINSTRINFO, 4);
1221	/** Pointer to a VMX VM-exit instruction info. struct. */
1222	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1223	/** Pointer to a const VMX VM-exit instruction info. struct. */
1224	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1225
1226
1227	/** @name VM-entry failure reported in Exit qualification.
1228	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1229	* @{
1230	*/
1231	/** No errors during VM-entry. */
1232	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1233	/** Not used. */
1234	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1235	/** Error while loading PDPTEs. */
1236	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1237	/** NMI injection when blocking-by-STI is set. */
1238	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1239	/** Invalid VMCS link pointer. */
1240	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1241	/** @} */
1242
1243
1244	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1245	* These are -not- specified by Intel but used internally by VirtualBox.
1246	* @{ */
1247	/** Guest software reads of this MSR must not cause a VM-exit. */
1248	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1249	/** Guest software reads of this MSR must cause a VM-exit. */
1250	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1251	/** Guest software writes to this MSR must not cause a VM-exit. */
1252	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1253	/** Guest software writes to this MSR must cause a VM-exit. */
1254	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1255	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1256	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1257	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1258	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1259	/** Mask of valid MSR read permissions. */
1260	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1261	/** Mask of valid MSR write permissions. */
1262	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1263	/** Mask of valid MSR permissions. */
1264	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1265	/** */
1266	/** Gets whether the MSR permission is valid or not. */
1267	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1268	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1269	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1270	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1271	/** @} */
1272
1273	/**
1274	* VMX MSR autoload/store slot.
1275	* In accordance with the VT-x spec.
1276	*/
1277	typedef struct VMXAUTOMSR
1278	{
1279	/** The MSR Id. */
1280	uint32_t u32Msr;
1281	/** Reserved (MBZ). */
1282	uint32_t u32Reserved;
1283	/** The MSR value. */
1284	uint64_t u64Value;
1285	} VMXAUTOMSR;
1286	AssertCompileSize(VMXAUTOMSR, 16);
1287	/** Pointer to an MSR load/store element. */
1288	typedef VMXAUTOMSR *PVMXAUTOMSR;
1289	/** Pointer to a const MSR load/store element. */
1290	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1291
1292	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1293	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1294
1295	/**
1296	* VMX tagged-TLB flush types.
1297	*/
1298	typedef enum
1299	{
1300	VMXTLBFLUSHTYPE_EPT,
1301	VMXTLBFLUSHTYPE_VPID,
1302	VMXTLBFLUSHTYPE_EPT_VPID,
1303	VMXTLBFLUSHTYPE_NONE
1304	} VMXTLBFLUSHTYPE;
1305	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1306	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1307	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1308	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1309
1310	/**
1311	* VMX controls MSR.
1312	* In accordance with the VT-x spec.
1313	*/
1314	typedef union
1315	{
1316	struct
1317	{
1318	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1319	uint32_t allowed0;
1320	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1321	* controls. */
1322	uint32_t allowed1;
1323	} n;
1324	uint64_t u;
1325	} VMXCTLSMSR;
1326	AssertCompileSize(VMXCTLSMSR, 8);
1327	/** Pointer to a VMXCTLSMSR union. */
1328	typedef VMXCTLSMSR *PVMXCTLSMSR;
1329	/** Pointer to a const VMXCTLSMSR union. */
1330	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1331
1332	/**
1333	* VMX MSRs.
1334	*/
1335	typedef struct VMXMSRS
1336	{
1337	/** Basic information. */
1338	uint64_t u64Basic;
1339	/** Pin-based VM-execution controls. */
1340	VMXCTLSMSR PinCtls;
1341	/** Processor-based VM-execution controls. */
1342	VMXCTLSMSR ProcCtls;
1343	/** Secondary processor-based VM-execution controls. */
1344	VMXCTLSMSR ProcCtls2;
1345	/** VM-exit controls. */
1346	VMXCTLSMSR ExitCtls;
1347	/** VM-entry controls. */
1348	VMXCTLSMSR EntryCtls;
1349	/** True pin-based VM-execution controls. */
1350	VMXCTLSMSR TruePinCtls;
1351	/** True processor-based VM-execution controls. */
1352	VMXCTLSMSR TrueProcCtls;
1353	/** True VM-entry controls. */
1354	VMXCTLSMSR TrueEntryCtls;
1355	/** True VM-exit controls. */
1356	VMXCTLSMSR TrueExitCtls;
1357	/** Miscellaneous data. */
1358	uint64_t u64Misc;
1359	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1360	uint64_t u64Cr0Fixed0;
1361	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1362	uint64_t u64Cr0Fixed1;
1363	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1364	uint64_t u64Cr4Fixed0;
1365	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1366	uint64_t u64Cr4Fixed1;
1367	/** VMCS enumeration. */
1368	uint64_t u64VmcsEnum;
1369	/** VM Functions. */
1370	uint64_t u64VmFunc;
1371	/** EPT, VPID capabilities. */
1372	uint64_t u64EptVpidCaps;
1373	/** Tertiary processor-based VM-execution controls. */
1374	uint64_t u64ProcCtls3;
1375	/** Secondary VM-exit controls. */
1376	uint64_t u64ExitCtls2;
1377	/** Reserved for future. */
1378	uint64_t a_u64Reserved[8];
1379	} VMXMSRS;
1380	AssertCompileSizeAlignment(VMXMSRS, 8);
1381	AssertCompileSize(VMXMSRS, 224);
1382	/** Pointer to a VMXMSRS struct. */
1383	typedef VMXMSRS *PVMXMSRS;
1384	/** Pointer to a const VMXMSRS struct. */
1385	typedef const VMXMSRS *PCVMXMSRS;
1386
1387
1388	/**
1389	* LBR MSRs.
1390	*/
1391	typedef struct LBRMSRS
1392	{
1393	/** List of LastBranch-From-IP MSRs. */
1394	uint64_t au64BranchFromIpMsr[32];
1395	/** List of LastBranch-To-IP MSRs. */
1396	uint64_t au64BranchToIpMsr[32];
1397	/** The MSR containing the index to the most recent branch record. */
1398	uint64_t uBranchTosMsr;
1399	} LBRMSRS;
1400	AssertCompileSizeAlignment(LBRMSRS, 8);
1401	/** Pointer to a VMXMSRS struct. */
1402	typedef LBRMSRS *PLBRMSRS;
1403	/** Pointer to a const VMXMSRS struct. */
1404	typedef const LBRMSRS *PCLBRMSRS;
1405
1406
1407	/** @name VMX Basic Exit Reasons.
1408	* In accordance with the VT-x spec.
1409	* Update g_aVMExitHandlers if new VM-exit reasons are added.
1410	* @{
1411	*/
1412	/** Invalid exit code */
1413	#define VMX_EXIT_INVALID (-1)
1414	/** Exception or non-maskable interrupt (NMI). */
1415	#define VMX_EXIT_XCPT_OR_NMI 0
1416	/** External interrupt. */
1417	#define VMX_EXIT_EXT_INT 1
1418	/** Triple fault. */
1419	#define VMX_EXIT_TRIPLE_FAULT 2
1420	/** INIT signal. */
1421	#define VMX_EXIT_INIT_SIGNAL 3
1422	/** Start-up IPI (SIPI). */
1423	#define VMX_EXIT_SIPI 4
1424	/** I/O system-management interrupt (SMI). */
1425	#define VMX_EXIT_IO_SMI 5
1426	/** Other SMI. */
1427	#define VMX_EXIT_SMI 6
1428	/** Interrupt window exiting. */
1429	#define VMX_EXIT_INT_WINDOW 7
1430	/** NMI window exiting. */
1431	#define VMX_EXIT_NMI_WINDOW 8
1432	/** Task switch. */
1433	#define VMX_EXIT_TASK_SWITCH 9
1434	/** CPUID. */
1435	#define VMX_EXIT_CPUID 10
1436	/** GETSEC. */
1437	#define VMX_EXIT_GETSEC 11
1438	/** HLT. */
1439	#define VMX_EXIT_HLT 12
1440	/** INVD. */
1441	#define VMX_EXIT_INVD 13
1442	/** INVLPG. */
1443	#define VMX_EXIT_INVLPG 14
1444	/** RDPMC. */
1445	#define VMX_EXIT_RDPMC 15
1446	/** RDTSC. */
1447	#define VMX_EXIT_RDTSC 16
1448	/** RSM in SMM. */
1449	#define VMX_EXIT_RSM 17
1450	/** VMCALL. */
1451	#define VMX_EXIT_VMCALL 18
1452	/** VMCLEAR. */
1453	#define VMX_EXIT_VMCLEAR 19
1454	/** VMLAUNCH. */
1455	#define VMX_EXIT_VMLAUNCH 20
1456	/** VMPTRLD. */
1457	#define VMX_EXIT_VMPTRLD 21
1458	/** VMPTRST. */
1459	#define VMX_EXIT_VMPTRST 22
1460	/** VMREAD. */
1461	#define VMX_EXIT_VMREAD 23
1462	/** VMRESUME. */
1463	#define VMX_EXIT_VMRESUME 24
1464	/** VMWRITE. */
1465	#define VMX_EXIT_VMWRITE 25
1466	/** VMXOFF. */
1467	#define VMX_EXIT_VMXOFF 26
1468	/** VMXON. */
1469	#define VMX_EXIT_VMXON 27
1470	/** Control-register accesses. */
1471	#define VMX_EXIT_MOV_CRX 28
1472	/** Debug-register accesses. */
1473	#define VMX_EXIT_MOV_DRX 29
1474	/** I/O instruction. */
1475	#define VMX_EXIT_IO_INSTR 30
1476	/** RDMSR. */
1477	#define VMX_EXIT_RDMSR 31
1478	/** WRMSR. */
1479	#define VMX_EXIT_WRMSR 32
1480	/** VM-entry failure due to invalid guest state. */
1481	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1482	/** VM-entry failure due to MSR loading. */
1483	#define VMX_EXIT_ERR_MSR_LOAD 34
1484	/** MWAIT. */
1485	#define VMX_EXIT_MWAIT 36
1486	/** VM-exit due to monitor trap flag. */
1487	#define VMX_EXIT_MTF 37
1488	/** MONITOR. */
1489	#define VMX_EXIT_MONITOR 39
1490	/** PAUSE. */
1491	#define VMX_EXIT_PAUSE 40
1492	/** VM-entry failure due to machine-check. */
1493	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1494	/** TPR below threshold. Guest software executed MOV to CR8. */
1495	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1496	/** VM-exit due to guest accessing physical address in the APIC-access page. */
1497	#define VMX_EXIT_APIC_ACCESS 44
1498	/** VM-exit due to EOI virtualization. */
1499	#define VMX_EXIT_VIRTUALIZED_EOI 45
1500	/** Access to GDTR/IDTR using LGDT, LIDT, SGDT or SIDT. */
1501	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1502	/** Access to LDTR/TR due to LLDT, LTR, SLDT, or STR. */
1503	#define VMX_EXIT_LDTR_TR_ACCESS 47
1504	/** EPT violation. */
1505	#define VMX_EXIT_EPT_VIOLATION 48
1506	/** EPT misconfiguration. */
1507	#define VMX_EXIT_EPT_MISCONFIG 49
1508	/** INVEPT. */
1509	#define VMX_EXIT_INVEPT 50
1510	/** RDTSCP. */
1511	#define VMX_EXIT_RDTSCP 51
1512	/** VMX-preemption timer expired. */
1513	#define VMX_EXIT_PREEMPT_TIMER 52
1514	/** INVVPID. */
1515	#define VMX_EXIT_INVVPID 53
1516	/** WBINVD. */
1517	#define VMX_EXIT_WBINVD 54
1518	/** XSETBV. */
1519	#define VMX_EXIT_XSETBV 55
1520	/** Guest completed write to virtual-APIC. */
1521	#define VMX_EXIT_APIC_WRITE 56
1522	/** RDRAND. */
1523	#define VMX_EXIT_RDRAND 57
1524	/** INVPCID. */
1525	#define VMX_EXIT_INVPCID 58
1526	/** VMFUNC. */
1527	#define VMX_EXIT_VMFUNC 59
1528	/** ENCLS. */
1529	#define VMX_EXIT_ENCLS 60
1530	/** RDSEED. */
1531	#define VMX_EXIT_RDSEED 61
1532	/** Page-modification log full. */
1533	#define VMX_EXIT_PML_FULL 62
1534	/** XSAVES. */
1535	#define VMX_EXIT_XSAVES 63
1536	/** XRSTORS. */
1537	#define VMX_EXIT_XRSTORS 64
1538	/** SPP-related event (SPP miss or misconfiguration). */
1539	#define VMX_EXIT_SPP_EVENT 66
1540	/* UMWAIT. */
1541	#define VMX_EXIT_UMWAIT 67
1542	/** TPAUSE. */
1543	#define VMX_EXIT_TPAUSE 68
1544	/** LOADIWKEY. */
1545	#define VMX_EXIT_LOADIWKEY 69
1546	/** The maximum VM-exit value (inclusive). */
1547	#define VMX_EXIT_MAX (VMX_EXIT_LOADIWKEY)
1548	/** @} */
1549
1550
1551	/** @name VM Instruction Errors.
1552	* In accordance with the VT-x spec.
1553	* See Intel spec. "30.4 VM Instruction Error Numbers"
1554	* @{
1555	*/
1556	typedef enum
1557	{
1558	/** VMCALL executed in VMX root operation. */
1559	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1560	/** VMCLEAR with invalid physical address. */
1561	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1562	/** VMCLEAR with VMXON pointer. */
1563	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1564	/** VMLAUNCH with non-clear VMCS. */
1565	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1566	/** VMRESUME with non-launched VMCS. */
1567	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1568	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1569	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1570	/** VM-entry with invalid control field(s). */
1571	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1572	/** VM-entry with invalid host-state field(s). */
1573	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1574	/** VMPTRLD with invalid physical address. */
1575	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1576	/** VMPTRLD with VMXON pointer. */
1577	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1578	/** VMPTRLD with incorrect VMCS revision identifier. */
1579	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1580	/** VMREAD from unsupported VMCS component. */
1581	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1582	/** VMWRITE to unsupported VMCS component. */
1583	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1584	/** VMWRITE to read-only VMCS component. */
1585	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1586	/** VMXON executed in VMX root operation. */
1587	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1588	/** VM-entry with invalid executive-VMCS pointer. */
1589	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1590	/** VM-entry with non-launched executive VMCS. */
1591	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1592	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1593	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1594	/** VMCALL with non-clear VMCS. */
1595	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1596	/** VMCALL with invalid VM-exit control fields. */
1597	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1598	/** VMCALL with incorrect MSEG revision identifier. */
1599	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1600	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1601	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1602	/** VMCALL with invalid SMM-monitor features. */
1603	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1604	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1605	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1606	/** VM-entry with events blocked by MOV SS. */
1607	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1608	/** Invalid operand to INVEPT/INVVPID. */
1609	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1610	} VMXINSTRERR;
1611	/** @} */
1612
1613
1614	/** @name VMX abort reasons.
1615	* In accordance with the VT-x spec.
1616	* See Intel spec. "27.7 VMX Aborts".
1617	* Update HMGetVmxAbortDesc() if new reasons are added.
1618	* @{
1619	*/
1620	typedef enum
1621	{
1622	/** None - don't use this / uninitialized value. */
1623	VMXABORT_NONE = 0,
1624	/** VMX abort caused during saving of guest MSRs. */
1625	VMXABORT_SAVE_GUEST_MSRS = 1,
1626	/** VMX abort caused during host PDPTE checks. */
1627	VMXBOART_HOST_PDPTE = 2,
1628	/** VMX abort caused due to current VMCS being corrupted. */
1629	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1630	/** VMX abort caused during loading of host MSRs. */
1631	VMXABORT_LOAD_HOST_MSR = 4,
1632	/** VMX abort caused due to a machine-check exception during VM-exit. */
1633	VMXABORT_MACHINE_CHECK_XCPT = 5,
1634	/** VMX abort caused due to invalid return from long mode. */
1635	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1636	/* Type size hack. */
1637	VMXABORT_32BIT_HACK = 0x7fffffff
1638	} VMXABORT;
1639	AssertCompileSize(VMXABORT, 4);
1640	/** @} */
1641
1642
1643	/** @name VMX MSR - Basic VMX information.
1644	* @{
1645	*/
1646	/** VMCS (and related regions) memory type - Uncacheable. */
1647	#define VMX_BASIC_MEM_TYPE_UC 0
1648	/** VMCS (and related regions) memory type - Write back. */
1649	#define VMX_BASIC_MEM_TYPE_WB 6
1650	/** Width of physical addresses used for VMCS and associated memory regions
1651	* (1=32-bit, 0=processor's physical address width). */
1652	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1653
1654	/** Bit fields for MSR_IA32_VMX_BASIC. */
1655	/** VMCS revision identifier used by the processor. */
1656	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1657	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1658	/** Bit 31 is reserved and RAZ. */
1659	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1660	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1661	/** VMCS size in bytes. */
1662	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1663	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1664	/** Bits 45:47 are reserved. */
1665	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1666	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1667	/** Width of physical addresses used for the VMCS and associated memory regions
1668	* (always 0 on CPUs that support Intel 64 architecture). */
1669	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1670	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1671	/** Dual-monitor treatment of SMI and SMM supported. */
1672	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1673	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1674	/** Memory type that must be used for the VMCS and associated memory regions. */
1675	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1676	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1677	/** VM-exit instruction information for INS/OUTS. */
1678	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1679	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1680	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1681	* bits in VMX control MSRs. */
1682	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1683	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1684	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1685	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1686	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1687	/** Bits 57:63 are reserved and RAZ. */
1688	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1689	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1690	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1691	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1692	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1693	/** @} */
1694
1695
1696	/** @name VMX MSR - Miscellaneous data.
1697	* @{
1698	*/
1699	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1700	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1701	/** Whether Intel PT is supported in VMX operation. */
1702	#define VMX_MISC_INTEL_PT RT_BIT(14)
1703	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1704	* VMWRITE cannot modify read-only VM-exit information fields. */
1705	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1706	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1707	* instructions. */
1708	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1709	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1710	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1711	/** Maximum CR3-target count supported by the CPU. */
1712	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1713
1714	/** Bit fields for MSR_IA32_VMX_MISC. */
1715	/** Relationship between the preemption timer and tsc. */
1716	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1717	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1718	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1719	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1720	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1721	/** Activity states supported by the implementation. */
1722	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1723	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1724	/** Bits 9:13 is reserved and RAZ. */
1725	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1726	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1727	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1728	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1729	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1730	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1731	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1732	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1733	/** Number of CR3 target values supported by the processor. (0-256) */
1734	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1735	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1736	/** Maximum number of MSRs in the VMCS. */
1737	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1738	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1739	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1740	* SMIs. */
1741	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1742	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1743	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1744	* VMWRITE cannot modify read-only VM-exit information fields. */
1745	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1746	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1747	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1748	* instructions. */
1749	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1750	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1751	/** Bit 31 is reserved and RAZ. */
1752	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1753	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1754	/** 32-bit MSEG revision ID used by the processor. */
1755	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1756	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1757	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1758	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1759	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1760	/** @} */
1761
1762	/** @name VMX MSR - VMCS enumeration.
1763	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1764	* @{
1765	*/
1766	/** Bit 0 is reserved and RAZ. */
1767	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1768	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1769	/** Highest index value used in VMCS field encoding. */
1770	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1771	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1772	/** Bit 10:63 is reserved and RAZ. */
1773	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1774	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1775	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1776	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1777	/** @} */
1778
1779
1780	/** @name VMX MSR - VM Functions.
1781	* Bit fields for MSR_IA32_VMX_VMFUNC.
1782	* @{
1783	*/
1784	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1785	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1786	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1787	/** Bits 1:63 are reserved and RAZ. */
1788	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1789	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1790	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1791	(EPTP_SWITCHING, RSVD_1_63));
1792	/** @} */
1793
1794
1795	/** @name VMX MSR - EPT/VPID capabilities.
1796	* @{
1797	*/
1798	/** Supports execute-only translations by EPT. */
1799	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1800	/** Supports page-walk length of 4. */
1801	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1802	/** Supports page-walk length of 5. */
1803	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1804	/** Supports EPT paging-structure memory type to be uncacheable. */
1805	#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC RT_BIT_64(8)
1806	/** Supports EPT paging structure memory type to be write-back. */
1807	#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB RT_BIT_64(14)
1808	/** Supports EPT PDE to map a 2 MB page. */
1809	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1810	/** Supports EPT PDPTE to map a 1 GB page. */
1811	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1812	/** Supports INVEPT instruction. */
1813	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1814	/** Supports accessed and dirty flags for EPT. */
1815	#define MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY RT_BIT_64(21)
1816	/** Supports advanced VM-exit info. for EPT violations. */
1817	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION RT_BIT_64(22)
1818	/** Supports supervisor shadow-stack control. */
1819	#define MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK RT_BIT_64(23)
1820	/** Supports single-context INVEPT type. */
1821	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1822	/** Supports all-context INVEPT type. */
1823	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1824	/** Supports INVVPID instruction. */
1825	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1826	/** Supports individual-address INVVPID type. */
1827	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1828	/** Supports single-context INVVPID type. */
1829	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1830	/** Supports all-context INVVPID type. */
1831	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1832	/** Supports singe-context-retaining-globals INVVPID type. */
1833	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1834
1835	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1836	#define VMX_BF_EPT_VPID_CAP_EXEC_ONLY_SHIFT 0
1837	#define VMX_BF_EPT_VPID_CAP_EXEC_ONLY_MASK UINT64_C(0x0000000000000001)
1838	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1839	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1840	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1841	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1842	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1843	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1844	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_SHIFT 8
1845	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_MASK UINT64_C(0x0000000000000100)
1846	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1847	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1848	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_SHIFT 14
1849	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_MASK UINT64_C(0x0000000000004000)
1850	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1851	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1852	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1853	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1854	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1855	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1856	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1857	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1858	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1859	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1860	#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_SHIFT 21
1861	#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1862	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_SHIFT 22
1863	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_MASK UINT64_C(0x0000000000400000)
1864	#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_SHIFT 23
1865	#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000800000)
1866	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1867	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1868	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1869	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1870	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1871	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1872	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1873	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1874	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1875	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1876	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1877	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1878	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1879	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1880	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1881	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1882	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1883	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1884	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1885	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1886	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1887	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1888	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1889	(EXEC_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, MEMTYPE_UC, RSVD_9_13, MEMTYPE_WB, RSVD_15, PDE_2M,
1890	PDPTE_1G, RSVD_18_19, INVEPT, ACCESS_DIRTY, ADVEXITINFO_EPT_VIOLATION, SUPER_SHW_STACK, RSVD_24,
1891	INVEPT_SINGLE_CTX, INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR,
1892	INVVPID_SINGLE_CTX, INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1893	/** @} */
1894
1895
1896	/** @name Extended Page Table Pointer (EPTP)
1897	* In accordance with the VT-x spec.
1898	* See Intel spec. 23.6.11 "Extended-Page-Table Pointer (EPTP)".
1899	* @{
1900	*/
1901	/** EPTP memory type: Uncachable. */
1902	#define VMX_EPTP_MEMTYPE_UC 0
1903	/** EPTP memory type: Write Back. */
1904	#define VMX_EPTP_MEMTYPE_WB 6
1905	/** Page-walk length for PML4 (4-level paging). */
1906	#define VMX_EPTP_PAGE_WALK_LENGTH_4 3
1907
1908	/** Bit fields for EPTP. */
1909	#define VMX_BF_EPTP_MEMTYPE_SHIFT 0
1910	#define VMX_BF_EPTP_MEMTYPE_MASK UINT64_C(0x0000000000000007)
1911	#define VMX_BF_EPTP_PAGE_WALK_LENGTH_SHIFT 3
1912	#define VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK UINT64_C(0x0000000000000038)
1913	#define VMX_BF_EPTP_ACCESS_DIRTY_SHIFT 6
1914	#define VMX_BF_EPTP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000000040)
1915	#define VMX_BF_EPTP_SUPER_SHW_STACK_SHIFT 7
1916	#define VMX_BF_EPTP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000000080)
1917	#define VMX_BF_EPTP_RSVD_8_11_SHIFT 8
1918	#define VMX_BF_EPTP_RSVD_8_11_MASK UINT64_C(0x0000000000000f00)
1919	#define VMX_BF_EPTP_PML4_TABLE_ADDR_SHIFT 12
1920	#define VMX_BF_EPTP_PML4_TABLE_ADDR_MASK UINT64_C(0xfffffffffffff000)
1921	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPTP_, UINT64_C(0), UINT64_MAX,
1922	(MEMTYPE, PAGE_WALK_LENGTH, ACCESS_DIRTY, SUPER_SHW_STACK, RSVD_8_11, PML4_TABLE_ADDR));
1923
1924	/* Mask of valid EPTP bits sans physically non-addressable bits. */
1925	#define VMX_EPTP_VALID_MASK ( VMX_BF_EPTP_MEMTYPE_MASK \
1926	\| VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK \
1927	\| VMX_BF_EPTP_ACCESS_DIRTY_MASK \
1928	\| VMX_BF_EPTP_SUPER_SHW_STACK_MASK \
1929	\| VMX_BF_EPTP_PML4_TABLE_ADDR_MASK)
1930	/** @} */
1931
1932
1933	/** @name VMCS fields and encoding.
1934	*
1935	* When adding a new field:
1936	* - Always add it to g_aVmcsFields.
1937	* - Consider if it needs to be added to VMXVVMCS.
1938	* @{
1939	*/
1940	/** 16-bit control fields. */
1941	#define VMX_VMCS16_VPID 0x0000
1942	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1943	#define VMX_VMCS16_EPTP_INDEX 0x0004
1944	#define VMX_VMCS16_HLAT_PREFIX_SIZE 0x0006
1945	#define VMX_VMCS16_LAST_PID_PTR_INDEX 0x0008
1946
1947	/** 16-bit guest-state fields. */
1948	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1949	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1950	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1951	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1952	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1953	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1954	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1955	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1956	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1957	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1958	#define VMX_VMCS16_GUEST_UINV 0x0814
1959
1960	/** 16-bits host-state fields. */
1961	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1962	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1963	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1964	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1965	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1966	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1967	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1968
1969	/** 64-bit control fields. */
1970	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1971	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1972	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1973	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1974	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1975	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1976	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1977	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1978	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1979	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1980	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1981	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1982	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1983	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1984	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1985	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1986	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1987	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1988	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1989	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1990	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1991	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1992	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1993	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1994	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1995	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1996	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1997	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1998	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1999	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
2000	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
2001	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
2002	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
2003	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
2004	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
2005	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
2006	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
2007	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
2008	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
2009	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
2010	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
2011	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
2012	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL 0x202a
2013	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH 0x202b
2014	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
2015	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
2016	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
2017	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
2018	#define VMX_VMCS64_CTRL_SPPTP_FULL 0x2030
2019	#define VMX_VMCS64_CTRL_SPPTP_HIGH 0x2031
2020	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
2021	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
2022	#define VMX_VMCS64_CTRL_PROC_EXEC3_FULL 0x2034
2023	#define VMX_VMCS64_CTRL_PROC_EXEC3_HIGH 0x2035
2024	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_FULL 0x2036
2025	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH 0x2037
2026	#define VMX_VMCS64_CTRL_PCONFIG_EXITING_BITMAP_FULL 0x203e
2027	#define VMX_VMCS64_CTRL_PCONFIG_EXITING_BITMAP_HIGH 0x203f
2028	#define VMX_VMCS64_CTRL_HLAT_PTR_FULL 0x2040
2029	#define VMX_VMCS64_CTRL_HLAT_PTR_HIGH 0x2041
2030	#define VMX_VMCS64_CTRL_EXIT2_FULL 0x2044
2031	#define VMX_VMCS64_CTRL_EXIT2_HIGH 0x2045
2032	#define VMX_VMCS64_CTRL_SPEC_CTRL_MASK_FULL 0x204a
2033	#define VMX_VMCS64_CTRL_SPEC_CTRL_MASK_HIGH 0x204b
2034	#define VMX_VMCS64_CTRL_SPEC_CTRL_SHADOW_FULL 0x204c
2035	#define VMX_VMCS64_CTRL_SPEC_CTRL_SHADOW_HIGH 0x204d
2036
2037	/** 64-bit read-only data fields. */
2038	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
2039	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
2040
2041	/** 64-bit guest-state fields. */
2042	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
2043	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
2044	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
2045	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
2046	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
2047	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
2048	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
2049	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
2050	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
2051	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
2052	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
2053	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
2054	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
2055	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
2056	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
2057	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
2058	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
2059	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
2060	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
2061	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
2062	#define VMX_VMCS64_GUEST_RTIT_CTL_FULL 0x2814
2063	#define VMX_VMCS64_GUEST_RTIT_CTL_HIGH 0x2815
2064	#define VMX_VMCS64_GUEST_PKRS_FULL 0x2818
2065	#define VMX_VMCS64_GUEST_PKRS_HIGH 0x2819
2066
2067	/** 64-bit host-state fields. */
2068	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
2069	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
2070	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
2071	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
2072	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
2073	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
2074	#define VMX_VMCS64_HOST_PKRS_FULL 0x2c06
2075	#define VMX_VMCS64_HOST_PKRS_HIGH 0x2c07
2076
2077	/** 32-bit control fields. */
2078	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
2079	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
2080	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
2081	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
2082	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
2083	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
2084	#define VMX_VMCS32_CTRL_EXIT 0x400c
2085	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
2086	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
2087	#define VMX_VMCS32_CTRL_ENTRY 0x4012
2088	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
2089	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
2090	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
2091	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
2092	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
2093	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
2094	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
2095	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
2096	#define VMX_VMCS32_CTRL_INSTR_TIMEOUT 0x4024
2097
2098	/** 32-bits read-only fields. */
2099	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
2100	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
2101	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
2102	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
2103	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
2104	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
2105	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
2106	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
2107
2108	/** 32-bit guest-state fields. */
2109	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
2110	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
2111	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
2112	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
2113	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
2114	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
2115	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
2116	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
2117	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
2118	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
2119	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
2120	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
2121	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
2122	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
2123	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
2124	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
2125	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
2126	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
2127	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
2128	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
2129	#define VMX_VMCS32_GUEST_SMBASE 0x4828
2130	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
2131	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
2132
2133	/** 32-bit host-state fields. */
2134	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
2135
2136	/** Natural-width control fields. */
2137	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
2138	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
2139	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
2140	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
2141	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
2142	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
2143	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
2144	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
2145
2146	/** Natural-width read-only data fields. */
2147	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
2148	#define VMX_VMCS_RO_IO_RCX 0x6402
2149	#define VMX_VMCS_RO_IO_RSI 0x6404
2150	#define VMX_VMCS_RO_IO_RDI 0x6406
2151	#define VMX_VMCS_RO_IO_RIP 0x6408
2152	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
2153
2154	/** Natural-width guest-state fields. */
2155	#define VMX_VMCS_GUEST_CR0 0x6800
2156	#define VMX_VMCS_GUEST_CR3 0x6802
2157	#define VMX_VMCS_GUEST_CR4 0x6804
2158	#define VMX_VMCS_GUEST_ES_BASE 0x6806
2159	#define VMX_VMCS_GUEST_CS_BASE 0x6808
2160	#define VMX_VMCS_GUEST_SS_BASE 0x680a
2161	#define VMX_VMCS_GUEST_DS_BASE 0x680c
2162	#define VMX_VMCS_GUEST_FS_BASE 0x680e
2163	#define VMX_VMCS_GUEST_GS_BASE 0x6810
2164	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
2165	#define VMX_VMCS_GUEST_TR_BASE 0x6814
2166	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
2167	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
2168	#define VMX_VMCS_GUEST_DR7 0x681a
2169	#define VMX_VMCS_GUEST_RSP 0x681c
2170	#define VMX_VMCS_GUEST_RIP 0x681e
2171	#define VMX_VMCS_GUEST_RFLAGS 0x6820
2172	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
2173	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
2174	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
2175	#define VMX_VMCS_GUEST_S_CET 0x6828
2176	#define VMX_VMCS_GUEST_SSP 0x682a
2177	#define VMX_VMCS_GUEST_INTR_SSP_TABLE_ADDR 0x682c
2178
2179	/** Natural-width host-state fields. */
2180	#define VMX_VMCS_HOST_CR0 0x6c00
2181	#define VMX_VMCS_HOST_CR3 0x6c02
2182	#define VMX_VMCS_HOST_CR4 0x6c04
2183	#define VMX_VMCS_HOST_FS_BASE 0x6c06
2184	#define VMX_VMCS_HOST_GS_BASE 0x6c08
2185	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
2186	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
2187	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
2188	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
2189	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
2190	#define VMX_VMCS_HOST_RSP 0x6c14
2191	#define VMX_VMCS_HOST_RIP 0x6c16
2192	#define VMX_VMCS_HOST_S_CET 0x6c18
2193	#define VMX_VMCS_HOST_SSP 0x6c1a
2194	#define VMX_VMCS_HOST_INTR_SSP_TABLE_ADDR 0x6c1c
2195
2196	#define VMX_VMCS16_GUEST_SEG_SEL(a_iSegReg) (VMX_VMCS16_GUEST_ES_SEL + (a_iSegReg) * 2)
2197	#define VMX_VMCS_GUEST_SEG_BASE(a_iSegReg) (VMX_VMCS_GUEST_ES_BASE + (a_iSegReg) * 2)
2198	#define VMX_VMCS32_GUEST_SEG_LIMIT(a_iSegReg) (VMX_VMCS32_GUEST_ES_LIMIT + (a_iSegReg) * 2)
2199	#define VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(a_iSegReg) (VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS + (a_iSegReg) * 2)
2200
2201	/**
2202	* VMCS field.
2203	* In accordance with the VT-x spec.
2204	*/
2205	typedef union
2206	{
2207	struct
2208	{
2209	/** The access type; 0=full, 1=high of 64-bit fields. */
2210	uint32_t fAccessType : 1;
2211	/** The index. */
2212	uint32_t u8Index : 8;
2213	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2214	uint32_t u2Type : 2;
2215	/** Reserved (MBZ). */
2216	uint32_t u1Reserved0 : 1;
2217	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2218	uint32_t u2Width : 2;
2219	/** Reserved (MBZ). */
2220	uint32_t u18Reserved0 : 18;
2221	} n;
2222
2223	/* The unsigned integer view. */
2224	uint32_t u;
2225	} VMXVMCSFIELD;
2226	AssertCompileSize(VMXVMCSFIELD, 4);
2227	/** Pointer to a VMCS field. */
2228	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
2229	/** Pointer to a const VMCS field. */
2230	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2231
2232	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2233	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2234
2235	/** Bits fields for a VMCS field. */
2236	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2237	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2238	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2239	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2240	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2241	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2242	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2243	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2244	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2245	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2246	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2247	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2248	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2249	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2250
2251	/**
2252	* VMCS field encoding: Access type.
2253	* In accordance with the VT-x spec.
2254	*/
2255	typedef enum
2256	{
2257	VMXVMCSFIELDACCESS_FULL = 0,
2258	VMXVMCSFIELDACCESS_HIGH
2259	} VMXVMCSFIELDACCESS;
2260	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2261	/** VMCS field encoding type: Full. */
2262	#define VMX_VMCSFIELD_ACCESS_FULL 0
2263	/** VMCS field encoding type: High. */
2264	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2265
2266	/**
2267	* VMCS field encoding: Type.
2268	* In accordance with the VT-x spec.
2269	*/
2270	typedef enum
2271	{
2272	VMXVMCSFIELDTYPE_CONTROL = 0,
2273	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2274	VMXVMCSFIELDTYPE_GUEST_STATE,
2275	VMXVMCSFIELDTYPE_HOST_STATE
2276	} VMXVMCSFIELDTYPE;
2277	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2278	/** VMCS field encoding type: Control. */
2279	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2280	/** VMCS field encoding type: VM-exit information / read-only fields. */
2281	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2282	/** VMCS field encoding type: Guest-state. */
2283	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2284	/** VMCS field encoding type: Host-state. */
2285	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2286
2287	/**
2288	* VMCS field encoding: Width.
2289	* In accordance with the VT-x spec.
2290	*/
2291	typedef enum
2292	{
2293	VMXVMCSFIELDWIDTH_16BIT = 0,
2294	VMXVMCSFIELDWIDTH_64BIT,
2295	VMXVMCSFIELDWIDTH_32BIT,
2296	VMXVMCSFIELDWIDTH_NATURAL
2297	} VMXVMCSFIELDWIDTH;
2298	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2299	/** VMCS field encoding width: 16-bit. */
2300	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2301	/** VMCS field encoding width: 64-bit. */
2302	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2303	/** VMCS field encoding width: 32-bit. */
2304	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2305	/** VMCS field encoding width: Natural width. */
2306	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2307	/** @} */
2308
2309
2310	/** @name VM-entry instruction length.
2311	* @{ */
2312	/** The maximum valid value for VM-entry instruction length while injecting a
2313	* software interrupt, software exception or privileged software exception. */
2314	#define VMX_ENTRY_INSTR_LEN_MAX 15
2315	/** @} */
2316
2317
2318	/** @name VM-entry register masks.
2319	* @{ */
2320	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2321	* bit 17 and bits 19:28).
2322	*
2323	* I don't know the Intel spec. excludes the high bits here while includes them in
2324	* the corresponding VM-exit mask. Nonetheless, I'm including the high bits here
2325	* (by making it identical to the VM-exit CR0 mask) since they are reserved anyway
2326	* and to prevent omission of the high bits with hardware-assisted VMX execution.
2327	*/
2328	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK VMX_EXIT_HOST_CR0_IGNORE_MASK
2329	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2330	* 12, bits 14:15). */
2331	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2332	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2333	* 10). */
2334	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2335	/** @} */
2336
2337
2338	/** @name VM-exit register masks.
2339	* @{ */
2340	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2341	* bit 17, bits 19:28 and bits 32:63). */
2342	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2343	/** @} */
2344
2345
2346	/** @name Pin-based VM-execution controls.
2347	* @{
2348	*/
2349	/** External interrupt exiting. */
2350	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2351	/** NMI exiting. */
2352	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2353	/** Virtual NMIs. */
2354	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2355	/** Activate VMX preemption timer. */
2356	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2357	/** Process interrupts with the posted-interrupt notification vector. */
2358	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2359	/** Default1 class when true capability MSRs are not supported. */
2360	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2361
2362	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2363	* controls field in the VMCS. */
2364	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2365	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2366	#define VMX_BF_PIN_CTLS_RSVD_1_2_SHIFT 1
2367	#define VMX_BF_PIN_CTLS_RSVD_1_2_MASK UINT32_C(0x00000006)
2368	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2369	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2370	#define VMX_BF_PIN_CTLS_RSVD_4_SHIFT 4
2371	#define VMX_BF_PIN_CTLS_RSVD_4_MASK UINT32_C(0x00000010)
2372	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2373	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2374	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2375	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2376	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2377	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2378	#define VMX_BF_PIN_CTLS_RSVD_8_31_SHIFT 8
2379	#define VMX_BF_PIN_CTLS_RSVD_8_31_MASK UINT32_C(0xffffff00)
2380	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2381	(EXT_INT_EXIT, RSVD_1_2, NMI_EXIT, RSVD_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, RSVD_8_31));
2382	/** @} */
2383
2384
2385	/** @name Processor-based VM-execution controls.
2386	* @{
2387	*/
2388	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2389	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2390	/** Use timestamp counter offset. */
2391	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2392	/** VM-exit when executing the HLT instruction. */
2393	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2394	/** VM-exit when executing the INVLPG instruction. */
2395	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2396	/** VM-exit when executing the MWAIT instruction. */
2397	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2398	/** VM-exit when executing the RDPMC instruction. */
2399	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2400	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2401	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2402	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2403	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2404	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2405	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2406	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2407	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2408	/** Whether the secondary processor based VM-execution controls are used. */
2409	#define VMX_PROC_CTLS_USE_TERTIARY_CTLS RT_BIT(17)
2410	/** VM-exit on CR8 loads. */
2411	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2412	/** VM-exit on CR8 stores. */
2413	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2414	/** Use TPR shadow. */
2415	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2416	/** VM-exit when virtual NMI blocking is disabled. */
2417	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2418	/** VM-exit when executing a MOV DRx instruction. */
2419	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2420	/** VM-exit when executing IO instructions. */
2421	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2422	/** Use IO bitmaps. */
2423	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2424	/** Monitor trap flag. */
2425	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2426	/** Use MSR bitmaps. */
2427	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2428	/** VM-exit when executing the MONITOR instruction. */
2429	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2430	/** VM-exit when executing the PAUSE instruction. */
2431	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2432	/** Whether the secondary processor based VM-execution controls are used. */
2433	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2434	/** Default1 class when true-capability MSRs are not supported. */
2435	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2436
2437	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2438	* controls field in the VMCS. */
2439	#define VMX_BF_PROC_CTLS_RSVD_0_1_SHIFT 0
2440	#define VMX_BF_PROC_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2441	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2442	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2443	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2444	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2445	#define VMX_BF_PROC_CTLS_RSVD_4_6_SHIFT 4
2446	#define VMX_BF_PROC_CTLS_RSVD_4_6_MASK UINT32_C(0x00000070)
2447	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2448	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2449	#define VMX_BF_PROC_CTLS_RSVD_8_SHIFT 8
2450	#define VMX_BF_PROC_CTLS_RSVD_8_MASK UINT32_C(0x00000100)
2451	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2452	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2453	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2454	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2455	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2456	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2457	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2458	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2459	#define VMX_BF_PROC_CTLS_RSVD_13_14_SHIFT 13
2460	#define VMX_BF_PROC_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2461	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2462	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2463	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2464	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2465	#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT 17
2466	#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_MASK UINT32_C(0x00020000)
2467	#define VMX_BF_PROC_CTLS_RSVD_18_SHIFT 18
2468	#define VMX_BF_PROC_CTLS_RSVD_18_MASK UINT32_C(0x00040000)
2469	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2470	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2471	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2472	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2473	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2474	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2475	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2476	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2477	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2478	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2479	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2480	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2481	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2482	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2483	#define VMX_BF_PROC_CTLS_RSVD_26_SHIFT 26
2484	#define VMX_BF_PROC_CTLS_RSVD_26_MASK UINT32_C(0x4000000)
2485	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2486	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2487	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2488	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2489	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2490	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2491	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2492	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2493	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2494	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2495	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2496	(RSVD_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, RSVD_4_6, HLT_EXIT, RSVD_8, INVLPG_EXIT,
2497	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, RSVD_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, USE_TERTIARY_CTLS,
2498	RSVD_18, CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2499	USE_IO_BITMAPS, RSVD_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2500	USE_SECONDARY_CTLS));
2501	/** @} */
2502
2503
2504	/** @name Secondary Processor-based VM-execution controls.
2505	* @{
2506	*/
2507	/** Virtualize APIC accesses. */
2508	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2509	/** EPT supported/enabled. */
2510	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2511	/** Descriptor table instructions cause VM-exits. */
2512	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2513	/** RDTSCP supported/enabled. */
2514	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2515	/** Virtualize x2APIC mode. */
2516	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2517	/** VPID supported/enabled. */
2518	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2519	/** VM-exit when executing the WBINVD instruction. */
2520	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2521	/** Unrestricted guest execution. */
2522	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2523	/** APIC register virtualization. */
2524	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2525	/** Virtual-interrupt delivery. */
2526	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2527	/** A specified number of pause loops cause a VM-exit. */
2528	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2529	/** VM-exit when executing RDRAND instructions. */
2530	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2531	/** Enables INVPCID instructions. */
2532	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2533	/** Enables VMFUNC instructions. */
2534	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2535	/** Enables VMCS shadowing. */
2536	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2537	/** Enables ENCLS VM-exits. */
2538	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2539	/** VM-exit when executing RDSEED. */
2540	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2541	/** Enables page-modification logging. */
2542	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2543	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2544	#define VMX_PROC_CTLS2_EPT_XCPT_VE RT_BIT(18)
2545	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2546	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2547	/** Enables XSAVES/XRSTORS instructions. */
2548	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2549	/** Enables PASID translation. */
2550	#define VMX_PROC_CTLS2_PASID_TRANSLATE RT_BIT(21)
2551	/** Enables supervisor/user mode based EPT execute permission for linear
2552	* addresses. */
2553	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2554	/** Enables EPT write permissions to be specified at granularity of 128 bytes. */
2555	#define VMX_PROC_CTLS2_SPP_EPT RT_BIT(23)
2556	/** Intel PT output addresses are treated as guest-physical addresses and
2557	* translated using EPT. */
2558	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2559	/** Use TSC scaling. */
2560	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2561	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2562	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2563	/** Enables PCONFIG instruction. */
2564	#define VMX_PROC_CTLS2_PCONFIG RT_BIT(27)
2565	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2566	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2567	/** Enables VMM Bus-lock detection. */
2568	#define VMX_PROC_CTLS2_BUS_LOCK_DETECT RT_BIT(30)
2569	/** Enables instruction timeout VM-exits. */
2570	#define VMX_PROC_CTLS2_INSTR_TIMEOUT RT_BIT(31)
2571
2572
2573	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2574	* VM-execution controls field in the VMCS. */
2575	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2576	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2577	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2578	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2579	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2580	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2581	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2582	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2583	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2584	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2585	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2586	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2587	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2588	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2589	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2590	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2591	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2592	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2593	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2594	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2595	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2596	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2597	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2598	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2599	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2600	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2601	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2602	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2603	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2604	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2605	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2606	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2607	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2608	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2609	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2610	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2611	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2612	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2613	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2614	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2615	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2616	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2617	#define VMX_BF_PROC_CTLS2_PASID_TRANSLATE_SHIFT 21
2618	#define VMX_BF_PROC_CTLS2_PASID_TRANSLATE_MASK UINT32_C(0x00200000)
2619	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2620	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2621	#define VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT 23
2622	#define VMX_BF_PROC_CTLS2_SPP_EPT_MASK UINT32_C(0x00800000)
2623	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2624	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2625	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2626	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2627	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2628	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2629	#define VMX_BF_PROC_CTLS2_PCONFIG_SHIFT 27
2630	#define VMX_BF_PROC_CTLS2_PCONFIG_MASK UINT32_C(0x08000000)
2631	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2632	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2633	#define VMX_BF_PROC_CTLS2_RSVD_29_SHIFT 29
2634	#define VMX_BF_PROC_CTLS2_RSVD_29_MASK UINT32_C(0x20000000)
2635	#define VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_SHIFT 30
2636	#define VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_MASK UINT32_C(0x40000000)
2637	#define VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_SHIFT 31
2638	#define VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_MASK UINT32_C(0x80000000)
2639
2640	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2641	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2642	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2643	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS,
2644	PASID_TRANSLATE, MODE_BASED_EPT_PERM, SPP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, PCONFIG,
2645	ENCLV_EXIT, RSVD_29, BUSLOCK_DETECT, INSTR_TIMEOUT));
2646	/** @} */
2647
2648
2649	/** @name Tertiary Processor-based VM-execution controls.
2650	* @{
2651	*/
2652	/** VM-exit when executing LOADIWKEY. */
2653	#define VMX_PROC_CTLS3_LOADIWKEY_EXIT RT_BIT_64(0)
2654	/** Enables hypervisor-managed linear-address translation (HLAT). */
2655	#define VMX_PROC_CTLS3_HLAT RT_BIT_64(1)
2656	/** Enables EPT paging-write control. */
2657	#define VMX_PROC_CTLS3_EPT_PAGING_WRITE RT_BIT_64(2)
2658	/** Enables Guest-paging verification. */
2659	#define VMX_PROC_CTLS3_GST_PAGING_VERIFY RT_BIT_64(3)
2660	/** Enables IPI virtualization. */
2661	#define VMX_PROC_CTLS3_IPI_VIRT RT_BIT_64(4)
2662	/** Virtualize IA32_SPEC_CTRL. */
2663	#define VMX_PROC_CTLS3_VIRT_SPEC_CTRL RT_BIT_64(7)
2664
2665	/** Bit fields for Tertiary processor-based VM-execution controls field in the VMCS. */
2666	#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT 0
2667	#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_MASK UINT64_C(0x0000000000000001)
2668	#define VMX_BF_PROC_CTLS3_HLAT_SHIFT 1
2669	#define VMX_BF_PROC_CTLS3_HLAT_MASK UINT64_C(0x0000000000000002)
2670	#define VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_SHIFT 2
2671	#define VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_MASK UINT64_C(0x0000000000000004)
2672	#define VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_SHIFT 3
2673	#define VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_MASK UINT64_C(0x0000000000000008)
2674	#define VMX_BF_PROC_CTLS3_IPI_VIRT_SHIFT 4
2675	#define VMX_BF_PROC_CTLS3_IPI_VIRT_MASK UINT64_C(0x0000000000000010)
2676	#define VMX_BF_PROC_CTLS3_RSVD_5_6_SHIFT 5
2677	#define VMX_BF_PROC_CTLS3_RSVD_5_6_MASK UINT64_C(0x0000000000000060)
2678	#define VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_SHIFT 7
2679	#define VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_MASK UINT64_C(0x0000000000000080)
2680	#define VMX_BF_PROC_CTLS3_RSVD_8_63_SHIFT 8
2681	#define VMX_BF_PROC_CTLS3_RSVD_8_63_MASK UINT64_C(0xffffffffffffff00)
2682
2683	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS3_, UINT64_C(0), UINT64_MAX,
2684	(LOADIWKEY_EXIT, HLAT, EPT_PAGING_WRITE, GST_PAGING_VERIFY, IPI_VIRT, RSVD_5_6, VIRT_SPEC_CTRL,
2685	RSVD_8_63));
2686	/** @} */
2687
2688
2689	/** @name VM-entry controls.
2690	* @{
2691	*/
2692	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2693	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2694	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2695	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2696	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2697	/** In SMM mode after VM-entry. */
2698	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2699	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2700	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2701	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2702	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2703	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2704	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2705	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2706	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2707	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2708	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2709	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2710	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2711	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2712	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2713	/** Whether the guest UINV is loaded on VM-entry. */
2714	#define VMX_ENTRY_CTLS_LOAD_UINV RT_BIT(19)
2715	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2716	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2717	/** Whether the guest IA32_LBR_CTL MSR is loaded on VM-entry. */
2718	#define VMX_ENTRY_CTLS_LOAD_LBR_CTL_MSR RT_BIT(21)
2719	/** Whether the guest IA32_PKRS MSR is loaded on VM-entry. */
2720	#define VMX_ENTRY_CTLS_LOAD_PKRS_MSR RT_BIT(22)
2721	/** Default1 class when true-capability MSRs are not supported. */
2722	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2723
2724	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2725	* VMCS. */
2726	#define VMX_BF_ENTRY_CTLS_RSVD_0_1_SHIFT 0
2727	#define VMX_BF_ENTRY_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2728	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2729	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2730	#define VMX_BF_ENTRY_CTLS_RSVD_3_8_SHIFT 3
2731	#define VMX_BF_ENTRY_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2732	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2733	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2734	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2735	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2736	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2737	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2738	#define VMX_BF_ENTRY_CTLS_RSVD_12_SHIFT 12
2739	#define VMX_BF_ENTRY_CTLS_RSVD_12_MASK UINT32_C(0x00001000)
2740	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2741	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2742	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2743	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2744	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2745	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2746	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2747	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2748	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2749	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2750	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2751	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2752	#define VMX_BF_ENTRY_CTLS_LOAD_UINV_SHIFT 19
2753	#define VMX_BF_ENTRY_CTLS_LOAD_UINV_MASK UINT32_C(0x00080000)
2754	#define VMX_BF_ENTRY_CTLS_LOAD_CET_SHIFT 20
2755	#define VMX_BF_ENTRY_CTLS_LOAD_CET_MASK UINT32_C(0x00100000)
2756	#define VMX_BF_ENTRY_CTLS_LOAD_LBR_CTL_MSR_SHIFT 21
2757	#define VMX_BF_ENTRY_CTLS_LOAD_LBR_CTL_MSR_MASK UINT32_C(0x00200000)
2758	#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_SHIFT 22
2759	#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x00400000)
2760	#define VMX_BF_ENTRY_CTLS_RSVD_23_31_SHIFT 23
2761	#define VMX_BF_ENTRY_CTLS_RSVD_23_31_MASK UINT32_C(0xff800000)
2762
2763	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2764	(RSVD_0_1, LOAD_DEBUG, RSVD_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, RSVD_12,
2765	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2766	LOAD_RTIT_CTL_MSR, LOAD_UINV, LOAD_CET, LOAD_LBR_CTL_MSR, LOAD_PKRS_MSR, RSVD_23_31));
2767	/** @} */
2768
2769
2770	/** @name VM-exit controls.
2771	* @{
2772	*/
2773	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2774	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2775	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2776	/** Return to long mode after a VM-exit. */
2777	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2778	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2779	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2780	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2781	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2782	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2783	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2784	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2785	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2786	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2787	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2788	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2789	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2790	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2791	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2792	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2793	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2794	/** Whether to conceal VMX from Intel PT. */
2795	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2796	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2797	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2798	/** Whether IA32_LBR_CTL MSR is cleared on VM-exit. */
2799	#define VMX_EXIT_CTLS_CLEAR_LBR_CTL_MSR RT_BIT(26)
2800	/** Whether UINV is cleared on VM-exit. */
2801	#define VMX_EXIT_CTLS_CLEAR_UINV RT_BIT(27)
2802	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2803	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2804	/** Whether the host IA32_PKRS MSR is loaded on VM-exit. */
2805	#define VMX_EXIT_CTLS_LOAD_PKRS_MSR RT_BIT(29)
2806	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is saved on VM-exit. */
2807	#define VMX_EXIT_CTLS_SAVE_PERF_MSR RT_BIT(30)
2808	/** Whether secondary VM-exit controls are used. */
2809	#define VMX_EXIT_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2810	/** Default1 class when true-capability MSRs are not supported. */
2811	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2812
2813	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2814	* VMCS. */
2815	#define VMX_BF_EXIT_CTLS_RSVD_0_1_SHIFT 0
2816	#define VMX_BF_EXIT_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2817	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2818	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2819	#define VMX_BF_EXIT_CTLS_RSVD_3_8_SHIFT 3
2820	#define VMX_BF_EXIT_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2821	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2822	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2823	#define VMX_BF_EXIT_CTLS_RSVD_10_11_SHIFT 10
2824	#define VMX_BF_EXIT_CTLS_RSVD_10_11_MASK UINT32_C(0x00000c00)
2825	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2826	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2827	#define VMX_BF_EXIT_CTLS_RSVD_13_14_SHIFT 13
2828	#define VMX_BF_EXIT_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2829	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2830	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2831	#define VMX_BF_EXIT_CTLS_RSVD_16_17_SHIFT 16
2832	#define VMX_BF_EXIT_CTLS_RSVD_16_17_MASK UINT32_C(0x00030000)
2833	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2834	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2835	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2836	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2837	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2838	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2839	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2840	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2841	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2842	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2843	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2844	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2845	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2846	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2847	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2848	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2849	#define VMX_BF_EXIT_CTLS_CLEAR_LBR_CTL_MSR_SHIFT 26
2850	#define VMX_BF_EXIT_CTLS_CLEAR_LBR_CTL_MSR_MASK UINT32_C(0x04000000)
2851	#define VMX_BF_EXIT_CTLS_CLEAR_UINV_SHIFT 27
2852	#define VMX_BF_EXIT_CTLS_CLEAR_UINV_MASK UINT32_C(0x08000000)
2853	#define VMX_BF_EXIT_CTLS_LOAD_CET_SHIFT 28
2854	#define VMX_BF_EXIT_CTLS_LOAD_CET_MASK UINT32_C(0x10000000)
2855	#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_SHIFT 29
2856	#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x20000000)
2857	#define VMX_BF_EXIT_CTLS_SAVE_PERF_MSR_SHIFT 30
2858	#define VMX_BF_EXIT_CTLS_SAVE_PERF_MSR_MASK UINT32_C(0x40000000)
2859	#define VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2860	#define VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2861	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2862	(RSVD_0_1, SAVE_DEBUG, RSVD_3_8, HOST_ADDR_SPACE_SIZE, RSVD_10_11, LOAD_PERF_MSR, RSVD_13_14,
2863	ACK_EXT_INT, RSVD_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2864	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, CLEAR_LBR_CTL_MSR,
2865	CLEAR_UINV, LOAD_CET, LOAD_PKRS_MSR, SAVE_PERF_MSR, USE_SECONDARY_CTLS));
2866	/** @} */
2867
2868
2869	/** @name VM-exit reason.
2870	* @{
2871	*/
2872	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2873	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2874	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2875
2876	/** Bit fields for VM-exit reason. */
2877	/** The exit reason. */
2878	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2879	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2880	/** Bits 16:26 are reseved and MBZ. */
2881	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2882	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2883	/** Whether the VM-exit was incident to enclave mode. */
2884	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2885	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2886	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2887	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2888	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2889	/** VM-exit from VMX root operation (only possible with SMM). */
2890	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2891	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2892	/** Bit 30 is reserved and MBZ. */
2893	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2894	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2895	/** Whether VM-entry failed (currently only happens during loading guest-state
2896	* or MSRs or machine check exceptions). */
2897	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2898	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2899	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2900	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2901	/** @} */
2902
2903
2904	/** @name VM-entry interruption information.
2905	* @{
2906	*/
2907	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2908	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2909	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2910	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2911	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2912	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2913	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2914	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2915	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2916	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2917	/** Construct an VM-entry interruption information field from a VM-exit interruption
2918	* info value (same except that bit 12 is reserved). */
2919	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2920	/** Construct a VM-entry interruption information field from an IDT-vectoring
2921	* information field (same except that bit 12 is reserved). */
2922	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2923	/** If the VM-entry interruption information field indicates a page-fault. */
2924	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2925	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2926	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2927	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2928	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2929	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2930	/** If the VM-entry interruption information field indicates an external
2931	* interrupt. */
2932	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2933	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2934	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2935	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2936	/** If the VM-entry interruption information field indicates an NMI. */
2937	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2938	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2939	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2940	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2941	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2942	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2943
2944	/** Bit fields for VM-entry interruption information. */
2945	/** The VM-entry interruption vector. */
2946	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2947	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2948	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2949	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2950	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2951	/** Whether this event has an error code. */
2952	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2953	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2954	/** Bits 12:30 are reserved and MBZ. */
2955	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2956	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2957	/** Whether this VM-entry interruption info is valid. */
2958	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2959	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2960	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2961	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2962	/** @} */
2963
2964
2965	/** @name VM-entry exception error code.
2966	* @{ */
2967	/** Error code valid mask. */
2968	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2969	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2970	* stack aligned for doubleword pushes, the upper half of the error code is
2971	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2972	* use below. */
2973	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2974	/** @} */
2975
2976	/** @name VM-entry interruption information types.
2977	* @{
2978	*/
2979	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2980	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2981	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2982	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2983	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2984	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2985	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2986	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2987	/** @} */
2988
2989
2990	/** @name VM-entry interruption information vector types for
2991	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2992	* @{ */
2993	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2994	/** @} */
2995
2996
2997	/** @name VM-exit interruption information.
2998	* @{
2999	*/
3000	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
3001	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
3002	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
3003	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
3004	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
3005	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
3006	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3007	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
3008	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
3009
3010	/** If the VM-exit interruption information field indicates an page-fault. */
3011	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
3012	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
3013	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
3014	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
3015	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
3016	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
3017	/** If the VM-exit interruption information field indicates an double-fault. */
3018	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
3019	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
3020	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
3021	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
3022	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
3023	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
3024	/** If the VM-exit interruption information field indicates an NMI. */
3025	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
3026	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
3027	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
3028	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
3029	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
3030	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
3031
3032
3033	/** Bit fields for VM-exit interruption infomration. */
3034	/** The VM-exit interruption vector. */
3035	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
3036	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
3037	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
3038	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
3039	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
3040	/** Whether this event has an error code. */
3041	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
3042	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
3043	/** Whether NMI-unblocking due to IRET is active. */
3044	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
3045	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
3046	/** Bits 13:30 is reserved (MBZ). */
3047	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
3048	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
3049	/** Whether this VM-exit interruption info is valid. */
3050	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
3051	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
3052	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
3053	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
3054	/** @} */
3055
3056
3057	/** @name VM-exit interruption information types.
3058	* @{
3059	*/
3060	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
3061	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
3062	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
3063	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
3064	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
3065	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
3066	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
3067	/** @} */
3068
3069
3070	/** @name VM-exit instruction identity.
3071	*
3072	* These are found in VM-exit instruction information fields for certain
3073	* instructions.
3074	* @{ */
3075	typedef uint32_t VMXINSTRID;
3076	/** Whether the instruction ID field is valid. */
3077	#define VMXINSTRID_VALID RT_BIT_32(31)
3078	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
3079	* read or write. */
3080	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
3081	/** Gets whether the instruction ID is valid or not. */
3082	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
3083	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
3084	/** Gets the instruction ID. */
3085	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
3086	/** No instruction ID info. */
3087	#define VMXINSTRID_NONE 0
3088
3089	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
3090	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3091	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3092	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
3093	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
3094
3095	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3096	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3097	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
3098	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
3099
3100	/** The following IDs are used internally (some for logging, others for conveying
3101	* the ModR/M primary operand write bit): */
3102	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
3103	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
3104	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
3105	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3106	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
3107	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
3108	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
3109	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
3110	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
3111	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
3112	#define VMXINSTRID_RDSEED (0x20 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3113	#define VMXINSTRID_RDRAND (0x21 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3114	/** @} */
3115
3116
3117	/** @name IDT-vectoring information.
3118	* @{
3119	*/
3120	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
3121	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
3122	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
3123	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
3124	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
3125	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
3126	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
3127
3128	/** Construct an IDT-vectoring information field from an VM-entry interruption
3129	* information field (same except that bit 12 is reserved). */
3130	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
3131	/** If the IDT-vectoring information field indicates a page-fault. */
3132	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
3133	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
3134	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
3135	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
3136	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
3137	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
3138	/** If the IDT-vectoring information field indicates an NMI. */
3139	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
3140	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
3141	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
3142	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
3143	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
3144	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
3145
3146
3147	/** Bit fields for IDT-vectoring information. */
3148	/** The IDT-vectoring info vector. */
3149	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
3150	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
3151	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
3152	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
3153	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
3154	/** Whether the event has an error code. */
3155	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
3156	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
3157	/** Bit 12 is undefined. */
3158	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
3159	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
3160	/** Bits 13:30 is reserved (MBZ). */
3161	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
3162	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
3163	/** Whether this IDT-vectoring info is valid. */
3164	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
3165	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
3166	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
3167	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
3168	/** @} */
3169
3170
3171	/** @name IDT-vectoring information vector types.
3172	* @{
3173	*/
3174	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
3175	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
3176	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
3177	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
3178	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
3179	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
3180	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
3181	/** @} */
3182
3183
3184	/** @name TPR threshold.
3185	* @{ */
3186	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
3187	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
3188
3189	/** Bit fields for TPR threshold. */
3190	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
3191	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
3192	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
3193	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
3194	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
3195	(TPR, RSVD_4_31));
3196	/** @} */
3197
3198
3199	/** @name Guest-activity states.
3200	* @{
3201	*/
3202	/** The logical processor is active. */
3203	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
3204	/** The logical processor is inactive, because it executed a HLT instruction. */
3205	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
3206	/** The logical processor is inactive, because of a triple fault or other serious error. */
3207	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
3208	/** The logical processor is inactive, because it's waiting for a startup-IPI */
3209	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
3210	/** @} */
3211
3212
3213	/** @name Guest-interruptibility states.
3214	* @{
3215	*/
3216	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
3217	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
3218	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
3219	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
3220	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
3221
3222	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
3223	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
3224	/** @} */
3225
3226
3227	/** @name Exit qualification for debug exceptions.
3228	* @{
3229	*/
3230	/** Hardware breakpoint 0 was met. */
3231	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
3232	/** Hardware breakpoint 1 was met. */
3233	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
3234	/** Hardware breakpoint 2 was met. */
3235	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
3236	/** Hardware breakpoint 3 was met. */
3237	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
3238	/** Debug register access detected. */
3239	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
3240	/** A debug exception would have been triggered by single-step execution mode. */
3241	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
3242	/** Mask of all valid bits. */
3243	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
3244	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
3245	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
3246	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
3247	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
3248	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
3249
3250	/** Bit fields for Exit qualifications due to debug exceptions. */
3251	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
3252	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3253	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
3254	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3255	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
3256	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3257	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
3258	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3259	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
3260	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
3261	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
3262	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
3263	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
3264	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3265	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
3266	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
3267	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
3268	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
3269	/** @} */
3270
3271	/** @name Exit qualification for Mov DRx.
3272	* @{
3273	*/
3274	/** 0-2: Debug register number */
3275	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
3276	/** 3: Reserved; cleared to 0. */
3277	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
3278	/** 4: Direction of move (0 = write, 1 = read) */
3279	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
3280	/** 5-7: Reserved; cleared to 0. */
3281	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
3282	/** 8-11: General purpose register number. */
3283	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
3284
3285	/** Bit fields for Exit qualification due to Mov DRx. */
3286	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
3287	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
3288	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
3289	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
3290	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
3291	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
3292	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
3293	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
3294	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
3295	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3296	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
3297	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
3298	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
3299	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
3300	/** @} */
3301
3302
3303	/** @name Exit qualification for debug exceptions types.
3304	* @{
3305	*/
3306	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
3307	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
3308	/** @} */
3309
3310
3311	/** @name Exit qualification for control-register accesses.
3312	* @{
3313	*/
3314	/** 0-3: Control register number (0 for CLTS & LMSW) */
3315	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
3316	/** 4-5: Access type. */
3317	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
3318	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
3319	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
3320	/** 7: Reserved; cleared to 0. */
3321	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
3322	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
3323	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
3324	/** 12-15: Reserved; cleared to 0. */
3325	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
3326	/** 16-31: LMSW source data (else 0). */
3327	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
3328
3329	/** Bit fields for Exit qualification for control-register accesses. */
3330	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3331	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3332	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3333	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3334	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3335	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3336	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3337	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3338	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3339	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3340	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3341	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3342	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3343	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3344	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3345	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3346	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3347	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3348	/** @} */
3349
3350
3351	/** @name Exit qualification for control-register access types.
3352	* @{
3353	*/
3354	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3355	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3356	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3357	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3358	/** @} */
3359
3360
3361	/** @name Exit qualification for task switch.
3362	* @{
3363	*/
3364	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3365	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3366	/** Task switch caused by a call instruction. */
3367	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3368	/** Task switch caused by an iret instruction. */
3369	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3370	/** Task switch caused by a jmp instruction. */
3371	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3372	/** Task switch caused by an interrupt gate. */
3373	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3374
3375	/** Bit fields for Exit qualification for task switches. */
3376	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3377	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3378	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3379	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3380	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3381	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3382	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3383	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3384	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3385	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3386	/** @} */
3387
3388
3389	/** @name Exit qualification for EPT violations.
3390	* @{
3391	*/
3392	/** Set if acess causing the violation was a data read. */
3393	#define VMX_EXIT_QUAL_EPT_ACCESS_READ RT_BIT_64(0)
3394	/** Set if acess causing the violation was a data write. */
3395	#define VMX_EXIT_QUAL_EPT_ACCESS_WRITE RT_BIT_64(1)
3396	/** Set if the violation was caused by an instruction fetch. */
3397	#define VMX_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH RT_BIT_64(2)
3398	/** AND of the read bit of all EPT structures. */
3399	#define VMX_EXIT_QUAL_EPT_ENTRY_READ RT_BIT_64(3)
3400	/** AND of the write bit of all EPT structures. */
3401	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT_64(4)
3402	/** AND of the execute bit of all EPT structures. */
3403	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT_64(5)
3404	/** And of the execute bit of all EPT structures for user-mode addresses
3405	* (requires mode-based execute control). */
3406	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER RT_BIT_64(6)
3407	/** Set if the guest linear address field is valid. */
3408	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID RT_BIT_64(7)
3409	/** If bit 7 is one: (reserved otherwise)
3410	* 1 - violation due to physical address access.
3411	* 0 - violation caused by page walk or access/dirty bit updates.
3412	*/
3413	#define VMX_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR RT_BIT_64(8)
3414	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3415	* 1 - linear address is user-mode address.
3416	* 0 - linear address is supervisor-mode address.
3417	*/
3418	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_USER RT_BIT_64(9)
3419	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3420	* 1 - linear address translates to read-only page.
3421	* 0 - linear address translates to read-write page.
3422	*/
3423	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_RO RT_BIT_64(10)
3424	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3425	* 1 - linear address translates to executable-disabled page.
3426	* 0 - linear address translates to executable page.
3427	*/
3428	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_XD RT_BIT_64(11)
3429	/** NMI unblocking due to IRET. */
3430	#define VMX_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET RT_BIT_64(12)
3431	/** Set if acess causing the violation was a shadow-stack access. */
3432	#define VMX_EXIT_QUAL_EPT_ACCESS_SHW_STACK RT_BIT_64(13)
3433	/** If supervisor-shadow stack is enabled: (reserved otherwise)
3434	* 1 - supervisor shadow-stack access allowed.
3435	* 0 - supervisor shadow-stack access disallowed.
3436	*/
3437	#define VMX_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER RT_BIT_64(14)
3438	/** Set if access is related to trace output by Intel PT (reserved otherwise). */
3439	#define VMX_EXIT_QUAL_EPT_ACCESS_PT_TRACE RT_BIT_64(16)
3440
3441	/** Checks whether NMI unblocking due to IRET. */
3442	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3443
3444	/** Bit fields for Exit qualification for EPT violations. */
3445	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_SHIFT 0
3446	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_MASK UINT64_C(0x0000000000000001)
3447	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_SHIFT 1
3448	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_MASK UINT64_C(0x0000000000000002)
3449	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_SHIFT 2
3450	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_MASK UINT64_C(0x0000000000000004)
3451	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_SHIFT 3
3452	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_MASK UINT64_C(0x0000000000000008)
3453	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_SHIFT 4
3454	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_MASK UINT64_C(0x0000000000000010)
3455	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_SHIFT 5
3456	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_MASK UINT64_C(0x0000000000000020)
3457	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_SHIFT 6
3458	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_MASK UINT64_C(0x0000000000000040)
3459	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_SHIFT 7
3460	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK UINT64_C(0x0000000000000080)
3461	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR_SHIFT 8
3462	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR_MASK UINT64_C(0x0000000000000100)
3463	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_SHIFT 9
3464	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_MASK UINT64_C(0x0000000000000200)
3465	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_SHIFT 10
3466	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_MASK UINT64_C(0x0000000000000400)
3467	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_SHIFT 11
3468	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_MASK UINT64_C(0x0000000000000800)
3469	#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_SHIFT 12
3470	#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_MASK UINT64_C(0x0000000000001000)
3471	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_SHIFT 13
3472	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_MASK UINT64_C(0x0000000000002000)
3473	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_SHIFT 14
3474	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_MASK UINT64_C(0x0000000000004000)
3475	#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_SHIFT 15
3476	#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3477	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_SHIFT 16
3478	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_MASK UINT64_C(0x0000000000010000)
3479	#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_SHIFT 17
3480	#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3481	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_EPT_, UINT64_C(0), UINT64_MAX,
3482	(ACCESS_READ, ACCESS_WRITE, ACCESS_INSTR_FETCH, ENTRY_READ, ENTRY_WRITE, ENTRY_EXECUTE,
3483	ENTRY_EXECUTE_USER, LINEAR_ADDR_VALID, LINEAR_TO_PHYS_ADDR, LINEAR_ADDR_USER, LINEAR_ADDR_RO,
3484	LINEAR_ADDR_XD, NMI_UNBLOCK_IRET, ACCESS_SHW_STACK, ENTRY_SHW_STACK_SUPER, RSVD_15,
3485	ACCESS_PT_TRACE, RSVD_17_63));
3486	/** @} */
3487
3488
3489	/** @name Exit qualification for I/O instructions.
3490	* @{
3491	*/
3492	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3493	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3494	/** 3: IO operation direction. */
3495	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3496	/** 4: String IO operation (INS / OUTS). */
3497	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3498	/** 5: Repeated IO operation. */
3499	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3500	/** 6: Operand encoding. */
3501	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3502	/** 16-31: IO Port (0-0xffff). */
3503	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3504
3505	/** Bit fields for Exit qualification for I/O instructions. */
3506	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3507	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3508	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3509	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3510	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3511	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3512	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3513	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3514	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3515	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3516	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3517	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3518	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3519	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3520	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3521	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3522	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3523	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3524	/** @} */
3525
3526
3527	/** @name Exit qualification for I/O instruction types.
3528	* @{
3529	*/
3530	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3531	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3532	/** @} */
3533
3534
3535	/** @name Exit qualification for I/O instruction encoding.
3536	* @{
3537	*/
3538	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3539	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3540	/** @} */
3541
3542
3543	/** @name Exit qualification for APIC-access VM-exits from linear and
3544	* guest-physical accesses.
3545	* @{
3546	*/
3547	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3548	* access within the APIC page. */
3549	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3550	/** 12-15: Access type. */
3551	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3552	/* Rest reserved. */
3553
3554	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3555	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3556	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3557	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3558	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3559	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3560	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3561	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3562	(OFFSET, TYPE, RSVD_16_63));
3563	/** @} */
3564
3565
3566	/** @name Exit qualification for linear address APIC-access types.
3567	* @{
3568	*/
3569	/** Linear access for a data read during instruction execution. */
3570	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3571	/** Linear access for a data write during instruction execution. */
3572	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3573	/** Linear access for an instruction fetch. */
3574	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3575	/** Linear read/write access during event delivery. */
3576	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3577	/** Physical read/write access during event delivery. */
3578	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3579	/** Physical access for an instruction fetch or during instruction execution. */
3580	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3581
3582	/**
3583	* APIC-access type.
3584	* In accordance with the VT-x spec.
3585	*/
3586	typedef enum
3587	{
3588	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3589	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3590	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3591	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3592	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3593	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3594	} VMXAPICACCESS;
3595	AssertCompileSize(VMXAPICACCESS, 4);
3596	/** @} */
3597
3598
3599	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3600	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3601	* @{
3602	*/
3603	/** Address calculation scaling field (powers of two). */
3604	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3605	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3606	/** Bits 2 thru 6 are undefined. */
3607	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3608	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3609	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3610	* @remarks anyone's guess why this is a 3 bit field... */
3611	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3612	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3613	/** Bit 10 is defined as zero. */
3614	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3615	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3616	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3617	* for exits from 64-bit code as the operand size there is fixed. */
3618	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3619	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3620	/** Bits 12 thru 14 are undefined. */
3621	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3622	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3623	/** Applicable segment register (X86_SREG_XXX values). */
3624	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3625	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3626	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3627	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3628	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3629	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3630	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3631	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3632	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3633	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3634	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3635	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3636	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3637	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3638	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3639	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3640	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3641	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3642	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3643	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3644	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3645	/** Bits 30 & 31 are undefined. */
3646	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3647	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3648	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3649	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3650	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3651	/** @} */
3652
3653
3654	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3655	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3656	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3657	* @{
3658	*/
3659	/** Address calculation scaling field (powers of two). */
3660	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3661	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3662	/** Bit 2 is undefined. */
3663	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3664	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3665	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3666	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3667	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3668	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3669	* @remarks anyone's guess why this is a 3 bit field... */
3670	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3671	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3672	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3673	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3674	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3675	/** Bits 11 thru 14 are undefined. */
3676	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3677	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3678	/** Applicable segment register (X86_SREG_XXX values). */
3679	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3680	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3681	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3682	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3683	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3684	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3685	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3686	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3687	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3688	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3689	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3690	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3691	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3692	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3693	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3694	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3695	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3696	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3697	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3698	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3699	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3700	/** Bits 30 & 31 are undefined. */
3701	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3702	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3703	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3704	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3705	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3706	/** @} */
3707
3708
3709	/** @name Format of Pending-Debug-Exceptions.
3710	* Bits 4-11, 13, 15 and 17-63 are reserved.
3711	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3712	* possibly valid here but not in DR6.
3713	* @{
3714	*/
3715	/** Hardware breakpoint 0 was met. */
3716	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3717	/** Hardware breakpoint 1 was met. */
3718	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3719	/** Hardware breakpoint 2 was met. */
3720	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3721	/** Hardware breakpoint 3 was met. */
3722	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3723	/** At least one data or IO breakpoint was hit. */
3724	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3725	/** A debug exception would have been triggered by single-step execution mode. */
3726	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3727	/** A debug exception occurred inside an RTM region. */
3728	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3729	/** Mask of valid bits. */
3730	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3731	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3732	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3733	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3734	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3735	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3736	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3737	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3738	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3739	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3740	/** Bit fields for Pending debug exceptions. */
3741	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3742	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3743	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3744	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3745	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3746	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3747	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3748	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3749	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3750	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3751	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3752	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3753	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3754	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3755	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3756	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3757	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3758	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3759	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3760	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3761	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3762	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3763	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3764	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3765	/** @} */
3766
3767
3768	/**
3769	* VM-exit auxiliary information.
3770	*
3771	* This includes information that isn't necessarily stored in the guest-CPU
3772	* context but provided as part of VM-exits.
3773	*/
3774	typedef struct
3775	{
3776	/** The VM-exit reason. */
3777	uint32_t uReason;
3778	/** The Exit qualification field. */
3779	uint64_t u64Qual;
3780	/** The Guest-linear address field. */
3781	uint64_t u64GuestLinearAddr;
3782	/** The Guest-physical address field. */
3783	uint64_t u64GuestPhysAddr;
3784	/** The guest pending-debug exceptions. */
3785	uint64_t u64GuestPendingDbgXcpts;
3786	/** The VM-exit instruction length. */
3787	uint32_t cbInstr;
3788	/** The VM-exit instruction information. */
3789	VMXEXITINSTRINFO InstrInfo;
3790	/** VM-exit interruption information. */
3791	uint32_t uExitIntInfo;
3792	/** VM-exit interruption error code. */
3793	uint32_t uExitIntErrCode;
3794	/** IDT-vectoring information. */
3795	uint32_t uIdtVectoringInfo;
3796	/** IDT-vectoring error code. */
3797	uint32_t uIdtVectoringErrCode;
3798	} VMXEXITAUX;
3799	/** Pointer to a VMXEXITAUX struct. */
3800	typedef VMXEXITAUX *PVMXEXITAUX;
3801	/** Pointer to a const VMXEXITAUX struct. */
3802	typedef const VMXEXITAUX *PCVMXEXITAUX;
3803
3804
3805	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3806	* @{
3807	*/
3808
3809	/** @name Virtual VMX MSR - Miscellaneous data.
3810	* @{ */
3811	/** Number of CR3-target values supported. */
3812	#define VMX_V_CR3_TARGET_COUNT 4
3813	/** Activity states supported. */
3814	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3815	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3816	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3817	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3818	#define VMX_V_AUTOMSR_COUNT_MAX 0
3819	/** SMM MSEG revision ID. */
3820	#define VMX_V_MSEG_REV_ID 0
3821	/** @} */
3822
3823	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3824	* @{ */
3825	/** VMCS launch state clear legacy value -- deprecated!!!. */
3826	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR_LEGACY RT_BIT(0)
3827	/** VMCS launch state clear. */
3828	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR (0)
3829	/* Bit 1 used to be "active", no longer used. */
3830	/* Bit 2 used to be "current", no longer used. */
3831	/** VMCS launch state launched. */
3832	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3833	/** @} */
3834
3835	/** CR0 bits set here must always be set when in VMX operation. */
3836	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3837	/** CR0 bits set here must always be set when in VMX non-root operation with
3838	* unrestricted-guest control enabled. */
3839	#define VMX_V_CR0_FIXED0_UX (X86_CR0_NE)
3840	/** CR0 bits cleared here must always be cleared when in VMX operation. */
3841	#define VMX_V_CR0_FIXED1 UINT32_C(0xffffffff)
3842	/** CR4 bits set here must always be set when in VMX operation. */
3843	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3844
3845	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3846	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3847	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3848	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3849
3850	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3851	* complications when teleporation may be implemented). */
3852	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3853	/** The size of the virtual VMCS region (in pages). */
3854	#define VMX_V_VMCS_PAGES 1
3855
3856	/** The size of the virtual shadow VMCS region. */
3857	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3858	/** The size of the virtual shadow VMCS region (in pages). */
3859	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3860
3861	/** The size of the Virtual-APIC page (in bytes). */
3862	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3863	/** The size of the Virtual-APIC page (in pages). */
3864	#define VMX_V_VIRT_APIC_PAGES 1
3865
3866	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3867	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3868	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3869	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3870
3871	/** The size of the MSR bitmap (in bytes). */
3872	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3873	/** The size of the MSR bitmap (in pages). */
3874	#define VMX_V_MSR_BITMAP_PAGES 1
3875
3876	/** The size of I/O bitmap A (in bytes). */
3877	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3878	/** The size of I/O bitmap A (in pages). */
3879	#define VMX_V_IO_BITMAP_A_PAGES 1
3880
3881	/** The size of I/O bitmap B (in bytes). */
3882	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3883	/** The size of I/O bitmap B (in pages). */
3884	#define VMX_V_IO_BITMAP_B_PAGES 1
3885
3886	/** The size of the auto-load/store MSR area (in bytes). */
3887	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3888	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3889	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3890	/** The size of the auto-load/store MSR area (in pages). */
3891	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3892
3893	/** The highest index value used for supported virtual VMCS field encoding. */
3894	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_EXIT2_HIGH, VMX_BF_VMCSFIELD_INDEX)
3895
3896	/**
3897	* Virtual VM-exit information.
3898	*
3899	* This is a convenience structure that bundles some VM-exit information related
3900	* fields together.
3901	*/
3902	typedef struct
3903	{
3904	/** The VM-exit reason. */
3905	uint32_t uReason;
3906	/** The VM-exit instruction length. */
3907	uint32_t cbInstr;
3908	/** The VM-exit instruction information. */
3909	VMXEXITINSTRINFO InstrInfo;
3910	/** The VM-exit instruction ID. */
3911	VMXINSTRID uInstrId;
3912
3913	/** The Exit qualification field. */
3914	uint64_t u64Qual;
3915	/** The Guest-linear address field. */
3916	uint64_t u64GuestLinearAddr;
3917	/** The Guest-physical address field. */
3918	uint64_t u64GuestPhysAddr;
3919	/** The guest pending-debug exceptions. */
3920	uint64_t u64GuestPendingDbgXcpts;
3921	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3922	* instruction VM-exit. */
3923	RTGCPTR GCPtrEffAddr;
3924	} VMXVEXITINFO;
3925	/** Pointer to the VMXVEXITINFO struct. */
3926	typedef VMXVEXITINFO *PVMXVEXITINFO;
3927	/** Pointer to a const VMXVEXITINFO struct. */
3928	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3929	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3930
3931	/** Initialize a VMXVEXITINFO structure from only an exit reason. */
3932	#define VMXVEXITINFO_INIT_ONLY_REASON(a_uReason) \
3933	{ (a_uReason), 0, { 0 }, VMXINSTRID_NONE, 0, 0, 0, 0, 0 }
3934
3935	/** Initialize a VMXVEXITINFO structure from exit reason and instruction length (no info). */
3936	#define VMXVEXITINFO_INIT_WITH_INSTR_LEN(a_uReason, a_cbInstr) \
3937	{ (a_uReason), (a_cbInstr), { 0 }, VMXINSTRID_NONE, 0, 0, 0, 0, 0 }
3938
3939	/** Initialize a VMXVEXITINFO structure from exit reason and exit qualification. */
3940	#define VMXVEXITINFO_INIT_WITH_QUAL(a_uReason, a_uQual) \
3941	{ (a_uReason), 0, { 0 }, VMXINSTRID_NONE, (a_uQual), 0, 0, 0, 0 }
3942
3943	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification,
3944	* instruction info and length. */
3945	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO(a_uReason, a_uQual, a_uInstrInfo, a_cbInstr) \
3946	{ (a_uReason), (a_cbInstr), { a_uInstrInfo }, VMXINSTRID_NONE, (a_uQual), 0, 0, 0, 0 }
3947
3948	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification,
3949	* instruction info and length all copied from a VMXTRANSIENT structure. */
3950	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_FROM_TRANSIENT(a_pVmxTransient) \
3951	VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO((a_pVmxTransient)->uExitReason, \
3952	(a_pVmxTransient)->uExitQual, \
3953	(a_pVmxTransient)->ExitInstrInfo.u, \
3954	(a_pVmxTransient)->cbExitInstr)
3955
3956	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification,
3957	* instruction length (no info). */
3958	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN(a_uReason, a_uQual, a_cbInstr) \
3959	{ (a_uReason), (a_cbInstr), { 0 }, VMXINSTRID_NONE, (a_uQual), 0, 0, 0, 0 }
3960
3961	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification and
3962	* instruction length (no info) all copied from a VMXTRANSIENT structure. */
3963	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN_FROM_TRANSIENT(a_pVmxTransient) \
3964	VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN((a_pVmxTransient)->uExitReason, \
3965	(a_pVmxTransient)->uExitQual, \
3966	(a_pVmxTransient)->cbExitInstr)
3967
3968	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification,
3969	* instruction info, instruction length and guest linear address. */
3970	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR(a_uReason, a_uQual, a_uInstrInfo, \
3971	a_cbInstr, a_uGstLinAddr) \
3972	{ (a_uReason), (a_cbInstr), { (a_uInstrInfo) }, VMXINSTRID_NONE, (a_uQual), (a_uGstLinAddr), 0, 0, 0 }
3973
3974	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification,
3975	* instruction info, instruction length and guest linear address all copied
3976	* from a VMXTRANSIENT structure. */
3977	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR_FROM_TRANSIENT(a_pVmxTransient) \
3978	VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_INFO_AND_LIN_ADDR((a_pVmxTransient)->uExitReason, \
3979	(a_pVmxTransient)->uExitQual, \
3980	(a_pVmxTransient)->ExitInstrInfo.u, \
3981	(a_pVmxTransient)->cbExitInstr, \
3982	(a_pVmxTransient)->uGuestLinearAddr)
3983
3984	/** Initialize a VMXVEXITINFO structure from exit reason and pending debug
3985	* exceptions. */
3986	#define VMXVEXITINFO_INIT_WITH_DBG_XCPTS(a_uReason, a_uPendingDbgXcpts) \
3987	{ (a_uReason), 0, { 0 }, VMXINSTRID_NONE, 0, 0, 0, (a_uPendingDbgXcpts), 0 }
3988
3989	/** Initialize a VMXVEXITINFO structure from exit reason and pending debug
3990	* exceptions both copied from a VMXTRANSIENT structure. */
3991	#define VMXVEXITINFO_INIT_WITH_DBG_XCPTS_FROM_TRANSIENT(a_pVmxTransient) \
3992	VMXVEXITINFO_INIT_WITH_DBG_XCPTS((a_pVmxTransient)->uExitReason, (a_pVmxTransient)->uGuestPendingDbgXcpts)
3993
3994
3995	/** Initialize a VMXVEXITINFO structure from exit reason, exit qualification,
3996	* instruction length, guest linear address and guest physical address. */
3997	#define VMXVEXITINFO_INIT_WITH_QUAL_AND_INSTR_LEN_AND_GST_ADDRESSES(a_uReason, a_uQual, a_cbInstr, \
3998	a_uGstLinAddr, a_uGstPhysAddr) \
3999	{ (a_uReason), (a_cbInstr), { 0 }, VMXINSTRID_NONE, (a_uQual), (a_uGstLinAddr), (a_uGstPhysAddr), 0, 0 }
4000
4001
4002	/**
4003	* Virtual VM-exit information for events.
4004	*
4005	* This is a convenience structure that bundles some event-based VM-exit information
4006	* related fields together that are not included in VMXVEXITINFO.
4007	*
4008	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
4009	* easier to distinguish that IEM VM-exit handlers will set one or more of the
4010	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
4011	* make it ovbious which fields may get set (or cleared).
4012	*/
4013	typedef struct
4014	{
4015	/** VM-exit interruption information. */
4016	uint32_t uExitIntInfo;
4017	/** VM-exit interruption error code. */
4018	uint32_t uExitIntErrCode;
4019	/** IDT-vectoring information. */
4020	uint32_t uIdtVectoringInfo;
4021	/** IDT-vectoring error code. */
4022	uint32_t uIdtVectoringErrCode;
4023	} VMXVEXITEVENTINFO;
4024	/** Pointer to the VMXVEXITEVENTINFO struct. */
4025	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
4026	/** Pointer to a const VMXVEXITEVENTINFO struct. */
4027	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
4028
4029	/** Initialize a VMXVEXITEVENTINFO. */
4030	#define VMXVEXITEVENTINFO_INIT(a_uExitIntInfo, a_uExitIntErrCode, a_uIdtVectoringInfo, a_uIdtVectoringErrCode) \
4031	{ (a_uExitIntInfo), (a_uExitIntErrCode), (a_uIdtVectoringInfo), (a_uIdtVectoringErrCode) }
4032
4033	/** Initialize a VMXVEXITEVENTINFO with VM-exit interruption info and VM-exit
4034	* interruption error code. */
4035	#define VMXVEXITEVENTINFO_INIT_ONLY_INT(a_uExitIntInfo, a_uExitIntErrCode) \
4036	VMXVEXITEVENTINFO_INIT(a_uExitIntInfo, a_uExitIntErrCode, 0, 0)
4037
4038	/** Initialize a VMXVEXITEVENTINFO with IDT vectoring info and IDT
4039	* vectoring error code. */
4040	#define VMXVEXITEVENTINFO_INIT_ONLY_IDT(a_uIdtVectoringInfo, a_uIdtVectoringErrCode) \
4041	VMXVEXITEVENTINFO_INIT(0, 0, a_uIdtVectoringInfo, a_uIdtVectoringErrCode)
4042
4043	/**
4044	* Virtual VMCS.
4045	*
4046	* This is our custom format. Relevant fields from this VMCS will be merged into the
4047	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
4048	* VMX.
4049	*
4050	* The first 8 bytes must be in accordance with the Intel VT-x spec.
4051	* See Intel spec. 24.2 "Format of the VMCS Region".
4052	*
4053	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
4054	* the Intel spec. but for our own requirements) as we use it to offset into guest
4055	* memory.
4056	*
4057	* Although the guest is supposed to access the VMCS only through the execution of
4058	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
4059	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
4060	* for teleportation purposes, any newly added fields should be added to the
4061	* appropriate reserved sections or at the end of the structure.
4062	*
4063	* We always treat natural-width fields as 64-bit in our implementation since
4064	* it's easier, allows for teleporation in the future and does not affect guest
4065	* software.
4066	*
4067	* @note Any fields that are added or modified here, make sure to update the
4068	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
4069	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
4070	* Also consider updating CPUMIsGuestVmxVmcsFieldValid and cpumR3InfoVmxVmcs.
4071	*/
4072	#pragma pack(1)
4073	typedef struct
4074	{
4075	/** @name Header.
4076	* @{
4077	*/
4078	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
4079	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
4080	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
4081	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
4082	uint32_t u32RestoreProcCtls2; /*< 0x00c - Secondary VM-execution controls to restore, see iemVmxVmentryCheckCtls(). /
4083	uint32_t au32Reserved0[11]; /*< 0x010 - Reserved for future. /
4084	/** @} */
4085
4086	/** @name Read-only fields.
4087	* @{ */
4088	/** 16-bit fields. */
4089	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
4090
4091	/** 32-bit fields. */
4092	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
4093	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
4094	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
4095	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
4096	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
4097	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
4098	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
4099	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
4100	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
4101
4102	/** 64-bit fields. */
4103	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
4104	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
4105
4106	/** Natural-width fields. */
4107	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
4108	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
4109	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
4110	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
4111	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
4112	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
4113	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
4114	/** @} */
4115
4116	/** @name Control fields.
4117	* @{ */
4118	/** 16-bit fields. */
4119	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
4120	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
4121	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
4122	uint16_t u16HlatPrefixSize; /*< 0x1b6 - HLAT prefix size. /
4123	uint16_t au16Reserved0[12]; /*< 0x1b8 - Reserved for future. /
4124
4125	/** 32-bit fields. */
4126	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
4127	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
4128	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
4129	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
4130	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
4131	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
4132	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
4133	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
4134	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
4135	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
4136	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
4137	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
4138	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
4139	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
4140	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
4141	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
4142	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
4143	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
4144	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
4145
4146	/** 64-bit fields. */
4147	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
4148	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
4149	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
4150	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
4151	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
4152	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
4153	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
4154	RTUINT64U u64AddrPml; /*< 0x290 - Page-modification log address (PML). /
4155	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
4156	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
4157	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
4158	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
4159	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
4160	RTUINT64U u64EptPtr; /*< 0x2c0 - EPT pointer. /
4161	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
4162	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
4163	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
4164	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
4165	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
4166	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
4167	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
4168	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
4169	RTUINT64U u64XssExitBitmap; /*< 0x308 - XSS-exiting bitmap. /
4170	RTUINT64U u64EnclsExitBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
4171	RTUINT64U u64SppTablePtr; /*< 0x318 - Sub-page-permission-table pointer (SPPTP). /
4172	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
4173	RTUINT64U u64ProcCtls3; /*< 0x328 - Tertiary-Processor based VM-execution controls. /
4174	RTUINT64U u64EnclvExitBitmap; /*< 0x330 - ENCLV-exiting bitmap. /
4175	RTUINT64U u64PconfigExitBitmap; /*< 0x338 - PCONFIG-exiting bitmap. /
4176	RTUINT64U u64HlatPtr; /*< 0x340 - HLAT pointer. /
4177	RTUINT64U u64ExitCtls2; /*< 0x348 - Secondary VM-exit controls. /
4178	RTUINT64U au64Reserved0[10]; /*< 0x350 - Reserved for future. /
4179
4180	/** Natural-width fields. */
4181	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
4182	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
4183	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
4184	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
4185	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
4186	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
4187	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
4188	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
4189	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
4190	/** @} */
4191
4192	/** @name Host-state fields.
4193	* @{ */
4194	/** 16-bit fields. */
4195	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4196	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
4197	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
4198	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
4199	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
4200	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
4201	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
4202	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
4203	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
4204
4205	/** 32-bit fields. */
4206	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
4207	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
4208
4209	/** 64-bit fields. */
4210	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
4211	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
4212	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
4213	RTUINT64U u64HostPkrsMsr; /*< 0x550 - Host PKRS MSR. /
4214	RTUINT64U au64Reserved3[15]; /*< 0x558 - Reserved for future. /
4215
4216	/** Natural-width fields. */
4217	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
4218	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
4219	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
4220	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
4221	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
4222	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
4223	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
4224	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
4225	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
4226	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
4227	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
4228	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
4229	RTUINT64U u64HostSCetMsr; /*< 0x630 - Host S_CET MSR. /
4230	RTUINT64U u64HostSsp; /*< 0x638 - Host SSP. /
4231	RTUINT64U u64HostIntrSspTableAddrMsr; /*< 0x640 - Host Interrupt SSP table address MSR. /
4232	RTUINT64U au64Reserved7[29]; /*< 0x648 - Reserved for future. /
4233	/** @} */
4234
4235	/** @name Guest-state fields.
4236	* @{ */
4237	/** 16-bit fields. */
4238	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4239	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
4240	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
4241	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
4242	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
4243	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
4244	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
4245	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
4246	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
4247	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
4248	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
4249	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
4250
4251	/** 32-bit fields. */
4252	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4253	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
4254	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
4255	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
4256	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
4257	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
4258	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
4259	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
4260	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
4261	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
4262	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
4263	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
4264	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
4265	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
4266	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
4267	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
4268	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
4269	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
4270	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
4271	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
4272	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
4273	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
4274	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
4275	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
4276	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
4277
4278	/** 64-bit fields. */
4279	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
4280	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
4281	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
4282	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
4283	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
4284	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
4285	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
4286	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
4287	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
4288	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
4289	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
4290	RTUINT64U u64GuestPkrsMsr; /*< 0x840 - Guest PKRS MSR. /
4291	RTUINT64U au64Reserved2[31]; /*< 0x848 - Reserved for future. /
4292
4293	/** Natural-width fields. */
4294	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
4295	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
4296	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
4297	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
4298	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
4299	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
4300	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
4301	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
4302	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
4303	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
4304	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
4305	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
4306	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
4307	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
4308	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
4309	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
4310	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
4311	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
4312	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
4313	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
4314	RTUINT64U u64GuestSCetMsr; /*< 0x9e0 - Guest S_CET MSR. /
4315	RTUINT64U u64GuestSsp; /*< 0x9e8 - Guest SSP. /
4316	RTUINT64U u64GuestIntrSspTableAddrMsr; /*< 0x9f0 - Guest Interrupt SSP table address MSR. /
4317	RTUINT64U au64Reserved6[29]; /*< 0x9f8 - Reserved for future. /
4318	/** @} */
4319
4320	/** 0xae0 - Padding / reserved for future use. */
4321	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
4322	} VMXVVMCS;
4323	#pragma pack()
4324	/** Pointer to the VMXVVMCS struct. */
4325	typedef VMXVVMCS *PVMXVVMCS;
4326	/** Pointer to a const VMXVVMCS struct. */
4327	typedef const VMXVVMCS *PCVMXVVMCS;
4328	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
4329	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
4330	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
4331	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
4332	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
4333	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
4334	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
4335	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
4336	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
4337	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
4338	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
4339	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
4340	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
4341	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
4342	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
4343	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
4344	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
4345	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
4346	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
4347
4348	/**
4349	* Virtual VMX-instruction and VM-exit diagnostics.
4350	*
4351	* These are not the same as VM instruction errors that are enumerated in the Intel
4352	* spec. These are purely internal, fine-grained definitions used for diagnostic
4353	* purposes and are not reported to guest software under the VM-instruction error
4354	* field in its VMCS.
4355	*
4356	* @note Members of this enum are used as array indices, so no gaps are allowed.
4357	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
4358	*/
4359	typedef enum
4360	{
4361	/* Internal processing errors. */
4362	kVmxVDiag_None = 0,
4363	kVmxVDiag_Ipe_1,
4364	kVmxVDiag_Ipe_2,
4365	kVmxVDiag_Ipe_3,
4366	kVmxVDiag_Ipe_4,
4367	kVmxVDiag_Ipe_5,
4368	kVmxVDiag_Ipe_6,
4369	kVmxVDiag_Ipe_7,
4370	kVmxVDiag_Ipe_8,
4371	kVmxVDiag_Ipe_9,
4372	kVmxVDiag_Ipe_10,
4373	kVmxVDiag_Ipe_11,
4374	kVmxVDiag_Ipe_12,
4375	kVmxVDiag_Ipe_13,
4376	kVmxVDiag_Ipe_14,
4377	kVmxVDiag_Ipe_15,
4378	kVmxVDiag_Ipe_16,
4379	/* VMXON. */
4380	kVmxVDiag_Vmxon_A20M,
4381	kVmxVDiag_Vmxon_Cpl,
4382	kVmxVDiag_Vmxon_Cr0Fixed0,
4383	kVmxVDiag_Vmxon_Cr0Fixed1,
4384	kVmxVDiag_Vmxon_Cr4Fixed0,
4385	kVmxVDiag_Vmxon_Cr4Fixed1,
4386	kVmxVDiag_Vmxon_Intercept,
4387	kVmxVDiag_Vmxon_LongModeCS,
4388	kVmxVDiag_Vmxon_MsrFeatCtl,
4389	kVmxVDiag_Vmxon_PtrAbnormal,
4390	kVmxVDiag_Vmxon_PtrAlign,
4391	kVmxVDiag_Vmxon_PtrMap,
4392	kVmxVDiag_Vmxon_PtrReadPhys,
4393	kVmxVDiag_Vmxon_PtrWidth,
4394	kVmxVDiag_Vmxon_RealOrV86Mode,
4395	kVmxVDiag_Vmxon_ShadowVmcs,
4396	kVmxVDiag_Vmxon_VmxAlreadyRoot,
4397	kVmxVDiag_Vmxon_Vmxe,
4398	kVmxVDiag_Vmxon_VmcsRevId,
4399	kVmxVDiag_Vmxon_VmxRootCpl,
4400	/* VMXOFF. */
4401	kVmxVDiag_Vmxoff_Cpl,
4402	kVmxVDiag_Vmxoff_Intercept,
4403	kVmxVDiag_Vmxoff_LongModeCS,
4404	kVmxVDiag_Vmxoff_RealOrV86Mode,
4405	kVmxVDiag_Vmxoff_Vmxe,
4406	kVmxVDiag_Vmxoff_VmxRoot,
4407	/* VMPTRLD. */
4408	kVmxVDiag_Vmptrld_Cpl,
4409	kVmxVDiag_Vmptrld_LongModeCS,
4410	kVmxVDiag_Vmptrld_PtrAbnormal,
4411	kVmxVDiag_Vmptrld_PtrAlign,
4412	kVmxVDiag_Vmptrld_PtrMap,
4413	kVmxVDiag_Vmptrld_PtrReadPhys,
4414	kVmxVDiag_Vmptrld_PtrVmxon,
4415	kVmxVDiag_Vmptrld_PtrWidth,
4416	kVmxVDiag_Vmptrld_RealOrV86Mode,
4417	kVmxVDiag_Vmptrld_RevPtrReadPhys,
4418	kVmxVDiag_Vmptrld_ShadowVmcs,
4419	kVmxVDiag_Vmptrld_VmcsRevId,
4420	kVmxVDiag_Vmptrld_VmxRoot,
4421	/* VMPTRST. */
4422	kVmxVDiag_Vmptrst_Cpl,
4423	kVmxVDiag_Vmptrst_LongModeCS,
4424	kVmxVDiag_Vmptrst_PtrMap,
4425	kVmxVDiag_Vmptrst_RealOrV86Mode,
4426	kVmxVDiag_Vmptrst_VmxRoot,
4427	/* VMCLEAR. */
4428	kVmxVDiag_Vmclear_Cpl,
4429	kVmxVDiag_Vmclear_LongModeCS,
4430	kVmxVDiag_Vmclear_PtrAbnormal,
4431	kVmxVDiag_Vmclear_PtrAlign,
4432	kVmxVDiag_Vmclear_PtrMap,
4433	kVmxVDiag_Vmclear_PtrReadPhys,
4434	kVmxVDiag_Vmclear_PtrVmxon,
4435	kVmxVDiag_Vmclear_PtrWidth,
4436	kVmxVDiag_Vmclear_RealOrV86Mode,
4437	kVmxVDiag_Vmclear_VmxRoot,
4438	/* VMWRITE. */
4439	kVmxVDiag_Vmwrite_Cpl,
4440	kVmxVDiag_Vmwrite_FieldInvalid,
4441	kVmxVDiag_Vmwrite_FieldRo,
4442	kVmxVDiag_Vmwrite_LinkPtrInvalid,
4443	kVmxVDiag_Vmwrite_LongModeCS,
4444	kVmxVDiag_Vmwrite_PtrInvalid,
4445	kVmxVDiag_Vmwrite_PtrMap,
4446	kVmxVDiag_Vmwrite_RealOrV86Mode,
4447	kVmxVDiag_Vmwrite_VmxRoot,
4448	/* VMREAD. */
4449	kVmxVDiag_Vmread_Cpl,
4450	kVmxVDiag_Vmread_FieldInvalid,
4451	kVmxVDiag_Vmread_LinkPtrInvalid,
4452	kVmxVDiag_Vmread_LongModeCS,
4453	kVmxVDiag_Vmread_PtrInvalid,
4454	kVmxVDiag_Vmread_PtrMap,
4455	kVmxVDiag_Vmread_RealOrV86Mode,
4456	kVmxVDiag_Vmread_VmxRoot,
4457	/* INVVPID. */
4458	kVmxVDiag_Invvpid_Cpl,
4459	kVmxVDiag_Invvpid_DescRsvd,
4460	kVmxVDiag_Invvpid_LongModeCS,
4461	kVmxVDiag_Invvpid_RealOrV86Mode,
4462	kVmxVDiag_Invvpid_TypeInvalid,
4463	kVmxVDiag_Invvpid_Type0InvalidAddr,
4464	kVmxVDiag_Invvpid_Type0InvalidVpid,
4465	kVmxVDiag_Invvpid_Type1InvalidVpid,
4466	kVmxVDiag_Invvpid_Type3InvalidVpid,
4467	kVmxVDiag_Invvpid_VmxRoot,
4468	/* INVEPT. */
4469	kVmxVDiag_Invept_Cpl,
4470	kVmxVDiag_Invept_DescRsvd,
4471	kVmxVDiag_Invept_EptpInvalid,
4472	kVmxVDiag_Invept_LongModeCS,
4473	kVmxVDiag_Invept_RealOrV86Mode,
4474	kVmxVDiag_Invept_TypeInvalid,
4475	kVmxVDiag_Invept_VmxRoot,
4476	/* VMLAUNCH/VMRESUME. */
4477	kVmxVDiag_Vmentry_AddrApicAccess,
4478	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4479	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4480	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4481	kVmxVDiag_Vmentry_AddrExitMsrLoad,
4482	kVmxVDiag_Vmentry_AddrExitMsrStore,
4483	kVmxVDiag_Vmentry_AddrIoBitmapA,
4484	kVmxVDiag_Vmentry_AddrIoBitmapB,
4485	kVmxVDiag_Vmentry_AddrMsrBitmap,
4486	kVmxVDiag_Vmentry_AddrVirtApicPage,
4487	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4488	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4489	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4490	kVmxVDiag_Vmentry_ApicRegVirt,
4491	kVmxVDiag_Vmentry_BlocKMovSS,
4492	kVmxVDiag_Vmentry_Cpl,
4493	kVmxVDiag_Vmentry_Cr3TargetCount,
4494	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4495	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4496	kVmxVDiag_Vmentry_EntryInstrLen,
4497	kVmxVDiag_Vmentry_EntryInstrLenZero,
4498	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4499	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4500	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4501	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4502	kVmxVDiag_Vmentry_EptpAccessDirty,
4503	kVmxVDiag_Vmentry_EptpPageWalkLength,
4504	kVmxVDiag_Vmentry_EptpMemType,
4505	kVmxVDiag_Vmentry_EptpRsvd,
4506	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4507	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4508	kVmxVDiag_Vmentry_GuestActStateHlt,
4509	kVmxVDiag_Vmentry_GuestActStateRsvd,
4510	kVmxVDiag_Vmentry_GuestActStateShutdown,
4511	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4512	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4513	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4514	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4515	kVmxVDiag_Vmentry_GuestCr0PgPe,
4516	kVmxVDiag_Vmentry_GuestCr3,
4517	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4518	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4519	kVmxVDiag_Vmentry_GuestDebugCtl,
4520	kVmxVDiag_Vmentry_GuestDr7,
4521	kVmxVDiag_Vmentry_GuestEferMsr,
4522	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4523	kVmxVDiag_Vmentry_GuestGdtrBase,
4524	kVmxVDiag_Vmentry_GuestGdtrLimit,
4525	kVmxVDiag_Vmentry_GuestIdtrBase,
4526	kVmxVDiag_Vmentry_GuestIdtrLimit,
4527	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4528	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4529	kVmxVDiag_Vmentry_GuestIntStateNmi,
4530	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4531	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4532	kVmxVDiag_Vmentry_GuestIntStateSmi,
4533	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4534	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4535	kVmxVDiag_Vmentry_GuestPae,
4536	kVmxVDiag_Vmentry_GuestPatMsr,
4537	kVmxVDiag_Vmentry_GuestPcide,
4538	kVmxVDiag_Vmentry_GuestPdpte,
4539	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4540	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4541	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4542	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4543	kVmxVDiag_Vmentry_GuestRip,
4544	kVmxVDiag_Vmentry_GuestRipRsvd,
4545	kVmxVDiag_Vmentry_GuestRFlagsIf,
4546	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4547	kVmxVDiag_Vmentry_GuestRFlagsVm,
4548	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4549	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4550	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4551	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4552	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4553	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4554	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4555	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4556	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4557	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4558	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4559	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4560	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4561	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4562	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4563	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4564	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4565	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4566	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4567	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4568	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4569	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4570	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4571	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4572	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4573	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4574	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4575	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4576	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4577	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4578	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4579	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4580	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4581	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4582	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4583	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4584	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4585	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4586	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4587	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4588	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4589	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4590	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4591	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4592	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4593	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4594	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4595	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4596	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4597	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4598	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4599	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4600	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4601	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4602	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4603	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4604	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4605	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4606	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4607	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4608	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4609	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4610	kVmxVDiag_Vmentry_GuestSegBaseCs,
4611	kVmxVDiag_Vmentry_GuestSegBaseDs,
4612	kVmxVDiag_Vmentry_GuestSegBaseEs,
4613	kVmxVDiag_Vmentry_GuestSegBaseFs,
4614	kVmxVDiag_Vmentry_GuestSegBaseGs,
4615	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4616	kVmxVDiag_Vmentry_GuestSegBaseSs,
4617	kVmxVDiag_Vmentry_GuestSegBaseTr,
4618	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4619	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4620	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4621	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4622	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4623	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4624	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4625	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4626	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4627	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4628	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4629	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4630	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4631	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4632	kVmxVDiag_Vmentry_GuestSegSelTr,
4633	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4634	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4635	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4636	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4637	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4638	kVmxVDiag_Vmentry_HostCr0Fixed0,
4639	kVmxVDiag_Vmentry_HostCr0Fixed1,
4640	kVmxVDiag_Vmentry_HostCr3,
4641	kVmxVDiag_Vmentry_HostCr4Fixed0,
4642	kVmxVDiag_Vmentry_HostCr4Fixed1,
4643	kVmxVDiag_Vmentry_HostCr4Pae,
4644	kVmxVDiag_Vmentry_HostCr4Pcide,
4645	kVmxVDiag_Vmentry_HostCsTr,
4646	kVmxVDiag_Vmentry_HostEferMsr,
4647	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4648	kVmxVDiag_Vmentry_HostGuestLongMode,
4649	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4650	kVmxVDiag_Vmentry_HostLongMode,
4651	kVmxVDiag_Vmentry_HostPatMsr,
4652	kVmxVDiag_Vmentry_HostRip,
4653	kVmxVDiag_Vmentry_HostRipRsvd,
4654	kVmxVDiag_Vmentry_HostSel,
4655	kVmxVDiag_Vmentry_HostSegBase,
4656	kVmxVDiag_Vmentry_HostSs,
4657	kVmxVDiag_Vmentry_HostSysenterEspEip,
4658	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4659	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4660	kVmxVDiag_Vmentry_LongModeCS,
4661	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4662	kVmxVDiag_Vmentry_MsrLoad,
4663	kVmxVDiag_Vmentry_MsrLoadCount,
4664	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4665	kVmxVDiag_Vmentry_MsrLoadRing3,
4666	kVmxVDiag_Vmentry_MsrLoadRsvd,
4667	kVmxVDiag_Vmentry_NmiWindowExit,
4668	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4669	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4670	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4671	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4672	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4673	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4674	kVmxVDiag_Vmentry_PtrInvalid,
4675	kVmxVDiag_Vmentry_PtrShadowVmcs,
4676	kVmxVDiag_Vmentry_RealOrV86Mode,
4677	kVmxVDiag_Vmentry_SavePreemptTimer,
4678	kVmxVDiag_Vmentry_TprThresholdRsvd,
4679	kVmxVDiag_Vmentry_TprThresholdVTpr,
4680	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4681	kVmxVDiag_Vmentry_VirtIntDelivery,
4682	kVmxVDiag_Vmentry_VirtNmi,
4683	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4684	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4685	kVmxVDiag_Vmentry_VmcsClear,
4686	kVmxVDiag_Vmentry_VmcsLaunch,
4687	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4688	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4689	kVmxVDiag_Vmentry_VmxRoot,
4690	kVmxVDiag_Vmentry_Vpid,
4691	kVmxVDiag_Vmexit_HostPdpte,
4692	kVmxVDiag_Vmexit_MsrLoad,
4693	kVmxVDiag_Vmexit_MsrLoadCount,
4694	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4695	kVmxVDiag_Vmexit_MsrLoadRing3,
4696	kVmxVDiag_Vmexit_MsrLoadRsvd,
4697	kVmxVDiag_Vmexit_MsrStore,
4698	kVmxVDiag_Vmexit_MsrStoreCount,
4699	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4700	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4701	kVmxVDiag_Vmexit_MsrStoreRing3,
4702	kVmxVDiag_Vmexit_MsrStoreRsvd,
4703	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4704	/* Last member for determining array index limit. */
4705	kVmxVDiag_End
4706	} VMXVDIAG;
4707	AssertCompileSize(VMXVDIAG, 4);
4708
4709	/** @} */
4710
4711	/** @} */
4712
4713	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4714

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h

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