cpumctx-x86-amd64.h

Last change on this file was 108968, checked in by vboxsync, 3 weeks ago
VMM,Main,Devices: Respect VBOX_VMM_TARGET_ARMV8 correctly on amd64 hosts (for IEM debugging purposes). jiraref:VBP-1598
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures for the x86/amd64 emulation/virtualization.
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_x86_amd64_h
37	#define VBOX_INCLUDED_vmm_cpumctx_x86_amd64_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/** A general register (union). */
110	typedef union CPUMCTXGREG
111	{
112	/** Natural unsigned integer view. */
113	uint64_t u;
114	/** 64-bit view. */
115	uint64_t u64;
116	/** 32-bit view. */
117	uint32_t u32;
118	/** 16-bit view. */
119	uint16_t u16;
120	/** 8-bit view. */
121	uint8_t u8;
122	/** 8-bit low/high view. */
123	RT_GCC_EXTENSION struct
124	{
125	/** Low byte (al, cl, dl, bl, ++). */
126	uint8_t bLo;
127	/** High byte in the first word - ah, ch, dh, bh. */
128	uint8_t bHi;
129	} CPUM_STRUCT_NM(s);
130	} CPUMCTXGREG;
131	#ifndef VBOX_FOR_DTRACE_LIB
132	AssertCompileSize(CPUMCTXGREG, 8);
133	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
134	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
135	#endif
136
137
138
139	/**
140	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
141	*
142	* @warning Exercise caution while modifying the layout of this struct. It's
143	* part of VM saved states.
144	*/
145	#pragma pack(1)
146	typedef struct SVMHOSTSTATE
147	{
148	uint64_t uEferMsr;
149	uint64_t uCr0;
150	uint64_t uCr4;
151	uint64_t uCr3;
152	uint64_t uRip;
153	uint64_t uRsp;
154	uint64_t uRax;
155	X86RFLAGS rflags;
156	CPUMSELREG es;
157	CPUMSELREG cs;
158	CPUMSELREG ss;
159	CPUMSELREG ds;
160	VBOXGDTR gdtr;
161	VBOXIDTR idtr;
162	uint8_t abPadding[4];
163	} SVMHOSTSTATE;
164	#pragma pack()
165	/** Pointer to the SVMHOSTSTATE structure. */
166	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
167	/** Pointer to a const SVMHOSTSTATE structure. */
168	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
169	#ifndef VBOX_FOR_DTRACE_LIB
170	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
171	AssertCompileSize(SVMHOSTSTATE, 184);
172	#endif
173
174
175	/**
176	* CPU hardware virtualization types.
177	*/
178	typedef enum
179	{
180	CPUMHWVIRT_NONE = 0,
181	CPUMHWVIRT_VMX,
182	CPUMHWVIRT_SVM,
183	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
184	} CPUMHWVIRT;
185	#ifndef VBOX_FOR_DTRACE_LIB
186	AssertCompileSize(CPUMHWVIRT, 4);
187	#endif
188
189	/** Number of EFLAGS bits we put aside for the hardware EFLAGS, with the bits
190	* above this we use for storing internal state not visible to the guest.
191	*
192	* Using a value less than 32 here means some code bloat when loading and
193	* fetching the hardware EFLAGS value. Comparing VMMR0.r0 text size when
194	* compiling release build using gcc 11.3.1 on linux:
195	* - 32 bits: 2475709 bytes
196	* - 24 bits: 2482069 bytes; +6360 bytes.
197	* - 22 bits: 2482261 bytes; +6552 bytes.
198	* Same for windows (virtual size of .text):
199	* - 32 bits: 1498502 bytes
200	* - 24 bits: 1502278 bytes; +3776 bytes.
201	* - 22 bits: 1502198 bytes; +3696 bytes.
202	*
203	* In addition we pass pointer the 32-bit EFLAGS to a number of IEM assembly
204	* functions, so it would be safer to not store anything in the lower 32 bits.
205	* OTOH, we'd sooner discover buggy assembly code by doing so, as we've had one
206	* example of accidental EFLAGS trashing by these functions already.
207	*
208	* It would be more efficient for IEM to store the interrupt shadow bit (and
209	* anything else that needs to be cleared at the same time) in the 30:22 bit
210	* range, because that would allow using a simple AND imm32 instruction on x86
211	* and a MOVN imm16,16 instruction to load the constant on ARM64 (assuming the
212	* other flag needing clearing is RF (bit 16)). Putting it in the 63:32 range
213	* means we that on x86 we'll either use a memory variant of AND or require a
214	* separate load instruction for the immediate, whereas on ARM we'll need more
215	* instructions to construct the immediate value.
216	*
217	* Comparing the instruction exit thruput via the bs2-test-1 testcase, there
218	* seems to be little difference between 32 and 24 here (best results out of 9
219	* runs on Linux/VT-x). So, unless the results are really wrong and there is
220	* clear drop in thruput, it would on the whole make the most sense to use 24
221	* here.
222	*
223	* Update: We need more than 8 bits because of DBGF, so using 22 now.
224	*/
225	#define CPUMX86EFLAGS_HW_BITS 22
226	/** Mask for the hardware EFLAGS bits, 64-bit version. */
227	#define CPUMX86EFLAGS_HW_MASK_64 (RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - UINT64_C(1))
228	/** Mask for the hardware EFLAGS bits, 32-bit version. */
229	#if CPUMX86EFLAGS_HW_BITS == 32
230	# define CPUMX86EFLAGS_HW_MASK_32 UINT32_MAX
231	#elif CPUMX86EFLAGS_HW_BITS < 32 && CPUMX86EFLAGS_HW_BITS >= 22
232	# define CPUMX86EFLAGS_HW_MASK_32 (RT_BIT_32(CPUMX86EFLAGS_HW_BITS) - UINT32_C(1))
233	#else
234	# error "Misconfigured CPUMX86EFLAGS_HW_BITS value!"
235	#endif
236
237	/** Mask of internal flags kept with EFLAGS, 64-bit version.
238	* Bits 22-24 are taken by CPUMCTX_INHIBIT_SHADOW_SS, CPUMCTX_INHIBIT_SHADOW_STI
239	* and CPUMCTX_INHIBIT_NMI, bits 25-28 are for CPUMCTX_DBG_HIT_DRX_MASK, and
240	* bits 29-30 are for DBGF events and breakpoints.
241	*
242	* @todo The two DBGF bits could be merged. The NMI inhibiting could move to
243	* bit 32 or higher as it isn't automatically cleared on instruction
244	* completion (except for iret).
245	*/
246	#define CPUMX86EFLAGS_INT_MASK_64 UINT64_C(0x00000000ffc00000)
247	/** Mask of internal flags kept with EFLAGS, 32-bit version. */
248	#define CPUMX86EFLAGS_INT_MASK_32 UINT32_C(0xffc00000)
249
250
251	/**
252	* CPUM EFLAGS.
253	*
254	* This differs from X86EFLAGS in that we could use bits 31:22 for internal
255	* purposes, see CPUMX86EFLAGS_HW_BITS.
256	*/
257	typedef union CPUMX86EFLAGS
258	{
259	/** The full unsigned view, both hardware and VBox bits. */
260	uint32_t uBoth;
261	/** The plain unsigned view of the hardware bits. */
262	#if CPUMX86EFLAGS_HW_BITS == 32
263	uint32_t u;
264	#else
265	uint32_t u : CPUMX86EFLAGS_HW_BITS;
266	#endif
267	#ifndef VBOX_FOR_DTRACE_LIB
268	/** The bitfield view. */
269	X86EFLAGSBITS Bits;
270	#endif
271	} CPUMX86EFLAGS;
272	/** Pointer to CPUM EFLAGS. */
273	typedef CPUMX86EFLAGS *PCPUMX86EFLAGS;
274	/** Pointer to const CPUM EFLAGS. */
275	typedef const CPUMX86EFLAGS *PCCPUMX86EFLAGS;
276
277	/**
278	* CPUM RFLAGS.
279	*
280	* This differs from X86EFLAGS in that we use could be using bits 63:22 for
281	* internal purposes, see CPUMX86EFLAGS_HW_BITS.
282	*/
283	typedef union CPUMX86RFLAGS
284	{
285	/** The full unsigned view, both hardware and VBox bits. */
286	uint64_t uBoth;
287	/** The plain unsigned view of the hardware bits. */
288	#if CPUMX86EFLAGS_HW_BITS == 32
289	uint32_t u;
290	#else
291	uint32_t u : CPUMX86EFLAGS_HW_BITS;
292	#endif
293	#ifndef VBOX_FOR_DTRACE_LIB
294	/** The bitfield view. */
295	X86EFLAGSBITS Bits;
296	#endif
297	} CPUMX86RFLAGS;
298	/** Pointer to CPUM RFLAGS. */
299	typedef CPUMX86RFLAGS *PCPUMX86RFLAGS;
300	/** Pointer to const CPUM RFLAGS. */
301	typedef const CPUMX86RFLAGS *PCCPUMX86RFLAGS;
302
303
304	/**
305	* CPU context.
306	*/
307	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
308	typedef struct CPUMCTX
309	{
310	/** 0x0000 - General purpose registers. */
311	union /* no tag! */
312	{
313	/** The general purpose register array view, indexed by X86_GREG_XXX. */
314	CPUMCTXGREG aGRegs[16];
315
316	/** 64-bit general purpose register view. */
317	RT_GCC_EXTENSION struct /* no tag! */
318	{
319	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
320	} CPUM_STRUCT_NM(qw);
321	/** 64-bit general purpose register view. */
322	RT_GCC_EXTENSION struct /* no tag! */
323	{
324	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
325	} CPUM_STRUCT_NM(qw2);
326	/** 32-bit general purpose register view. */
327	RT_GCC_EXTENSION struct /* no tag! */
328	{
329	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
330	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
331	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
332	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
333	} CPUM_STRUCT_NM(dw);
334	/** 16-bit general purpose register view. */
335	RT_GCC_EXTENSION struct /* no tag! */
336	{
337	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
338	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
339	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
340	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
341	} CPUM_STRUCT_NM(w);
342	RT_GCC_EXTENSION struct /* no tag! */
343	{
344	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
345	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
346	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
347	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
348	} CPUM_STRUCT_NM(b);
349	} CPUM_UNION_NM(g);
350
351	/** 0x0080 - Segment registers. */
352	union /* no tag! */
353	{
354	/** The segment register array view, indexed by X86_SREG_XXX. */
355	CPUMSELREG aSRegs[6];
356	/** The named segment register view. */
357	RT_GCC_EXTENSION struct /* no tag! */
358	{
359	CPUMSELREG es, cs, ss, ds, fs, gs;
360	} CPUM_STRUCT_NM(n);
361	} CPUM_UNION_NM(s);
362
363	/** 0x0110 - The task register.
364	* Only the guest context uses all the members. */
365	CPUMSELREG ldtr;
366	/** 0x0128 - The task register.
367	* Only the guest context uses all the members. */
368	CPUMSELREG tr;
369
370	/** 0x0140 - The program counter. */
371	union
372	{
373	uint16_t ip;
374	uint32_t eip;
375	uint64_t rip;
376	} CPUM_UNION_NM(rip);
377
378	/** 0x0148 - The flags register. */
379	union
380	{
381	CPUMX86EFLAGS eflags;
382	CPUMX86RFLAGS rflags;
383	} CPUM_UNION_NM(rflags);
384
385	/** 0x0150 - Externalized state tracker, CPUMCTX_EXTRN_XXX. */
386	uint64_t fExtrn;
387
388	/** 0x0158 The RIP value an interrupt shadow is/was valid for. */
389	uint64_t uRipInhibitInt;
390
391	/** @name Control registers.
392	* @{ */
393	uint64_t cr0; /*< 0x0160 /
394	uint64_t cr2; /*< 0x0168 /
395	uint64_t cr3; /*< 0x0170 /
396	uint64_t cr4; /*< 0x0178 /
397	/** @} */
398
399	/** 0x0180 - Debug registers.
400	* @remarks DR4 and DR5 should not be used since they are aliases for
401	* DR6 and DR7 respectively on both AMD and Intel CPUs.
402	* @remarks DR8-15 are currently not supported by AMD or Intel, so
403	* neither do we.
404	*/
405	uint64_t dr[8];
406
407	/** 0x01c0 - Padding before the structure so the 64-bit member is correctly aligned.
408	* @todo fix this structure! */
409	uint16_t gdtrPadding[3];
410	/** Global Descriptor Table register. */
411	VBOXGDTR gdtr;
412
413	/** 0x01d0 - Padding before the structure so the 64-bit member is correctly aligned.
414	* @todo fix this structure! */
415	uint16_t idtrPadding[3];
416	/** Interrupt Descriptor Table register. */
417	VBOXIDTR idtr;
418
419	/** 0x01e0 - The sysenter msr registers.
420	* This member is not used by the hypervisor context. */
421	CPUMSYSENTER SysEnter;
422
423	/** @name System MSRs.
424	* @{ */
425	uint64_t msrEFER; /*< 0x01f8 - @todo move EFER up to the crX registers for better cacheline mojo /
426	uint64_t msrSTAR; /*< 0x0200 - Legacy syscall eip, cs & ss. /
427	uint64_t msrPAT; /*< 0x0208 - Page attribute table. /
428	uint64_t msrLSTAR; /*< 0x0210 - 64 bits mode syscall rip. /
429	uint64_t msrCSTAR; /*< 0x0218 - Compatibility mode syscall rip. /
430	uint64_t msrSFMASK; /*< 0x0220 - syscall flag mask. /
431	uint64_t msrKERNELGSBASE; /*< 0x0228 - swapgs exchange value. /
432	/** @} */
433
434	uint64_t au64Unused[2]; /*< 0x0230 /
435
436	/** 0x240 - PAE PDPTEs. */
437	X86PDPE aPaePdpes[4];
438
439	/** 0x260 - The XCR0..XCR1 registers. */
440	uint64_t aXcr[2];
441	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
442	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
443	uint64_t fXStateMask;
444	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
445	bool fUsedFpuGuest;
446	uint8_t afUnused[7];
447
448	/* ---- Start of members not zeroed at reset. ---- */
449
450	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
451	* @note Everything before this member will be memset to zero during reset. */
452	uint16_t aoffXState[64];
453	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
454	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
455	union /* no tag */
456	{
457	X86XSAVEAREA XState;
458	/** Byte view for simple indexing and space allocation. */
459	uint8_t abXState[0x4000 - 0x300];
460	} CPUM_UNION_NM(u);
461
462	/** 0x4000 - Hardware virtualization state.
463	* @note This is page aligned, so an full page member comes first in the
464	* substructures. */
465	struct
466	{
467	union /* no tag! */
468	{
469	struct
470	{
471	/** 0x4000 - Cache of the nested-guest VMCB. */
472	SVMVMCB Vmcb;
473	/** 0x5000 - The MSRPM (MSR Permission bitmap).
474	*
475	* This need not be physically contiguous pages because we use the one from
476	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
477	* This one is just used for caching the bitmap from guest physical memory.
478	*
479	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
480	* really need to even be page aligned.
481	*
482	* Also, couldn't we just access the guest page directly when we need to,
483	* or do we have to use a cached copy of it? */
484	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
485	/** 0x7000 - The IOPM (IO Permission bitmap).
486	*
487	* This need not be physically contiguous pages because we re-use the ring-0
488	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
489	* because it's identical (we trap all IO accesses).
490	*
491	* This one is just used for caching the IOPM from guest physical memory in
492	* case the guest hypervisor allows direct access to some IO ports.
493	*
494	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
495	* really need to even be page aligned.
496	*
497	* Also, couldn't we just access the guest page directly when we need to,
498	* or do we have to use a cached copy of it? */
499	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
500
501	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
502	uint64_t uMsrHSavePa;
503	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
504	RTGCPHYS GCPhysVmcb;
505	/** 0xa010 - Guest's host-state save area. */
506	SVMHOSTSTATE HostState;
507	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
508	* executed. */
509	uint64_t uPrevPauseTick;
510	/** 0xa0d0 - Pause filter count. */
511	uint16_t cPauseFilter;
512	/** 0xa0d2 - Pause filter threshold. */
513	uint16_t cPauseFilterThreshold;
514	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
515	bool fInterceptEvents;
516	/** 0xa0d5 - Padding. */
517	bool afPadding[3];
518	} svm;
519
520	struct
521	{
522	/** 0x4000 - The current VMCS. */
523	VMXVVMCS Vmcs;
524	/** 0X5000 - The shadow VMCS. */
525	VMXVVMCS ShadowVmcs;
526	/** 0x6000 - The VMREAD bitmap.
527	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
528	* access the guest memory directly as needed? */
529	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
530	/** 0x7000 - The VMWRITE bitmap.
531	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
532	* access the guest memory directly as needed? */
533	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
534	/** 0x8000 - The VM-entry MSR-load area. */
535	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
536	/** 0xa000 - The VM-exit MSR-store area. */
537	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
538	/** 0xc000 - The VM-exit MSR-load area. */
539	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
540	/** 0xe000 - The MSR permission bitmap.
541	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
542	* access the guest memory directly as needed? */
543	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
544	/** 0xf000 - The I/O permission bitmap.
545	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
546	* access the guest memory directly as needed? */
547	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
548
549	/** 0x11000 - Guest physical address of the VMXON region. */
550	RTGCPHYS GCPhysVmxon;
551	/** 0x11008 - Guest physical address of the current VMCS pointer. */
552	RTGCPHYS GCPhysVmcs;
553	/** 0x11010 - Guest physical address of the shadow VMCS pointer. */
554	RTGCPHYS GCPhysShadowVmcs;
555	/** 0x11018 - Last emulated VMX instruction/VM-exit diagnostic. */
556	VMXVDIAG enmDiag;
557	/** 0x1101c - VMX abort reason. */
558	VMXABORT enmAbort;
559	/** 0x11020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
560	* (mainly used for info. that's not part of the VMCS). */
561	uint64_t uDiagAux;
562	/** 0x11028 - VMX abort auxiliary info. */
563	uint32_t uAbortAux;
564	/** 0x1102c - Whether the guest is in VMX root mode. */
565	bool fInVmxRootMode;
566	/** 0x1102d - Whether the guest is in VMX non-root mode. */
567	bool fInVmxNonRootMode;
568	/** 0x1102e - Whether the injected events are subjected to event intercepts. */
569	bool fInterceptEvents;
570	/** 0x1102f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
571	* non-root mode before execution of IRET. */
572	bool fNmiUnblockingIret;
573	/** 0x11030 - Guest TSC timestamp of the first PAUSE instruction that is
574	* considered to be the first in a loop. */
575	uint64_t uFirstPauseLoopTick;
576	/** 0x11038 - Guest TSC timestamp of the previous PAUSE instruction. */
577	uint64_t uPrevPauseTick;
578	/** 0x11040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
579	* timer). */
580	uint64_t uEntryTick;
581	/** 0x11048 - Virtual-APIC write offset (until trap-like VM-exit). */
582	uint16_t offVirtApicWrite;
583	/** 0x1104a - Whether virtual-NMI blocking is in effect. */
584	bool fVirtNmiBlocking;
585	/** 0x1104b - Padding. */
586	uint8_t abPadding0[5];
587	/** 0x11050 - Guest VMX MSRs. */
588	VMXMSRS Msrs;
589	} vmx;
590	} CPUM_UNION_NM(s);
591
592	/** 0x11130 - Hardware virtualization type currently in use. */
593	CPUMHWVIRT enmHwvirt;
594	/** 0x11134 - Global interrupt flag - AMD only (always true on Intel). */
595	bool fGif;
596	/** 0x11135 - Padding. */
597	bool afPadding0[3];
598	/** 0x11138 - A subset of guest inhibit flags (CPUMCTX_INHIBIT_XXX) that are
599	* saved while running the nested-guest. */
600	uint32_t fSavedInhibit;
601	/** 0x1113c - Pad to 64 byte boundary. */
602	uint8_t abPadding1[4];
603	} hwvirt;
604	} CPUMCTX;
605	#pragma pack()
606
607	#ifndef VBOX_FOR_DTRACE_LIB
608	AssertCompileSizeAlignment(CPUMCTX, 64);
609	AssertCompileSizeAlignment(CPUMCTX, 32);
610	AssertCompileSizeAlignment(CPUMCTX, 16);
611	AssertCompileSizeAlignment(CPUMCTX, 8);
612	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0x0000);
613	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 0x0008);
614	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 0x0010);
615	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 0x0018);
616	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 0x0020);
617	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 0x0028);
618	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 0x0030);
619	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 0x0038);
620	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 0x0040);
621	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 0x0048);
622	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 0x0050);
623	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 0x0058);
624	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 0x0060);
625	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 0x0068);
626	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 0x0070);
627	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 0x0078);
628	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 0x0080);
629	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 0x0098);
630	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 0x00b0);
631	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 0x00c8);
632	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 0x00e0);
633	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 0x00f8);
634	AssertCompileMemberOffset(CPUMCTX, ldtr, 0x0110);
635	AssertCompileMemberOffset(CPUMCTX, tr, 0x0128);
636	AssertCompileMemberOffset(CPUMCTX, rip, 0x0140);
637	AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148);
638	AssertCompileMemberOffset(CPUMCTX, fExtrn, 0x0150);
639	AssertCompileMemberOffset(CPUMCTX, uRipInhibitInt, 0x0158);
640	AssertCompileMemberOffset(CPUMCTX, cr0, 0x0160);
641	AssertCompileMemberOffset(CPUMCTX, cr2, 0x0168);
642	AssertCompileMemberOffset(CPUMCTX, cr3, 0x0170);
643	AssertCompileMemberOffset(CPUMCTX, cr4, 0x0178);
644	AssertCompileMemberOffset(CPUMCTX, dr, 0x0180);
645	AssertCompileMemberOffset(CPUMCTX, gdtr, 0x01c0+6);
646	AssertCompileMemberOffset(CPUMCTX, idtr, 0x01d0+6);
647	AssertCompileMemberOffset(CPUMCTX, SysEnter, 0x01e0);
648	AssertCompileMemberOffset(CPUMCTX, msrEFER, 0x01f8);
649	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 0x0200);
650	AssertCompileMemberOffset(CPUMCTX, msrPAT, 0x0208);
651	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 0x0210);
652	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 0x0218);
653	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 0x0220);
654	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 0x0228);
655	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x0240);
656	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x0260);
657	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x0270);
658	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x0278);
659	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0300);
660	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x0300);
661	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0100);
662	/* Only do spot checks for hwvirt */
663	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
664	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
665	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
666	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
667	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
668	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
669	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
670	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
671	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
672	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
673	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
674	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
675	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
676	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
677	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
678	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
679	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
680	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1104a);
681	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x11130);
682	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x11134);
683	AssertCompileMemberOffset(CPUMCTX, hwvirt.fSavedInhibit, 0x11138);
684	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
685	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
686	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
687	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
688	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
689	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
690	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
691	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
692	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
693	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
694	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
695	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
696	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
697	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
698	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
699	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
700	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
701	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
702	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
703	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
704	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
705	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
706	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
707	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
708	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
709	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
710	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
711	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
712	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
713	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
714	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
715	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
716	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
717	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
718	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
719	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
720	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
721	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
722	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
723	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
724	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
725	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
726	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
727	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
728	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
729	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
730	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
731	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
732	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
733	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
734	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
735	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
736	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
737	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
738	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
739	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
740	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
741	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
742	# ifndef _MSC_VER
743	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
744	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
745	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
746	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
747	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
748	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
749	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
750	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
751	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
752	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
753	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
754	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
755	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
756	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
757	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
758	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
759	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
760	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
761	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
762	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
763	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
764	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
765	# endif
766
767
768	/**
769	* Calculates the pointer to the given extended state component.
770	*
771	* @returns Pointer of type @a a_PtrType
772	* @param a_pCtx Pointer to the context.
773	* @param a_iCompBit The extended state component bit number. This bit
774	* must be set in CPUMCTX::fXStateMask.
775	* @param a_PtrType The pointer type of the extended state component.
776	*
777	*/
778	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
779	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
780	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
781	{ \
782	AssertCompile((a_iCompBit) < 64U); \
783	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
784	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
785	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
786	}(a_pCtx))
787	#elif defined(VBOX_STRICT) && defined(__GNUC__)
788	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
789	__extension__ (\
790	{ \
791	AssertCompile((a_iCompBit) < 64U); \
792	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
793	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
794	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
795	})
796	#else
797	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
798	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
799	#endif
800
801	/**
802	* Gets the first selector register of a CPUMCTX.
803	*
804	* Use this with X86_SREG_COUNT to loop thru the selector registers.
805	*/
806	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
807
808	#endif /* !VBOX_FOR_DTRACE_LIB */
809
810
811	/** @name CPUMCTX_EXTRN_XXX
812	* Used for parts of the CPUM state that is externalized and needs fetching
813	* before use.
814	*
815	* @{ */
816	/** External state keeper: Invalid. */
817	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
818	/** External state keeper: HM. */
819	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
820	/** External state keeper: NEM. */
821	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
822	/** External state keeper: REM. */
823	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
824	/** External state keeper mask. */
825	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
826
827	/** The RIP register value is kept externally. */
828	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
829	/** The RFLAGS register values are kept externally. */
830	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
831
832	/** The RAX register value is kept externally. */
833	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
834	/** The RCX register value is kept externally. */
835	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
836	/** The RDX register value is kept externally. */
837	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
838	/** The RBX register value is kept externally. */
839	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
840	/** The RSP register value is kept externally. */
841	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
842	/** The RBP register value is kept externally. */
843	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
844	/** The RSI register value is kept externally. */
845	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
846	/** The RDI register value is kept externally. */
847	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
848	/** The R8 thru R15 register values are kept externally. */
849	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
850	/** General purpose registers mask. */
851	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
852
853	/** The ES register values are kept externally. */
854	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
855	/** The CS register values are kept externally. */
856	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
857	/** The SS register values are kept externally. */
858	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
859	/** The DS register values are kept externally. */
860	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
861	/** The FS register values are kept externally. */
862	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
863	/** The GS register values are kept externally. */
864	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
865	/** Segment registers (includes CS). */
866	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
867	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
868	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
869	#ifndef VBOX_FOR_DTRACE_LIB
870	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
871	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
872	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
873	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
874	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
875	#endif
876
877	/** The GDTR register values are kept externally. */
878	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
879	/** The IDTR register values are kept externally. */
880	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
881	/** The LDTR register values are kept externally. */
882	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
883	/** The TR register values are kept externally. */
884	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
885	/** Table register mask. */
886	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
887
888	/** The CR0 register value is kept externally. */
889	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
890	/** The CR2 register value is kept externally. */
891	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
892	/** The CR3 register value is kept externally. */
893	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
894	/** The CR4 register value is kept externally. */
895	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
896	/** Control register mask. */
897	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
898	/** The TPR/CR8 register value is kept externally. */
899	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
900	/** The EFER register value is kept externally. */
901	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
902
903	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
904	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
905	/** The DR6 register value is kept externally. */
906	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
907	/** The DR7 register value is kept externally. */
908	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
909	/** Debug register mask. */
910	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
911
912	/** The XSAVE_C_X87 state is kept externally. */
913	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
914	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
915	* XSAVE_C_OPMASK state is kept externally. */
916	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
917	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
918	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
919	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
920	/** The state of XCR0 and XCR1 register values are kept externally. */
921	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
922
923
924	/** The KERNEL GS BASE MSR value is kept externally. */
925	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
926	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
927	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
928	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
929	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
930	/** The TSC_AUX MSR is kept externally. */
931	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
932	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
933	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
934	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
935	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
936
937	/** Mask of all the MSRs. */
938	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
939	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
940
941	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
942	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
943
944	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
945	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
946	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
947	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
948
949	/** Mask of bits the keepers can use for state tracking. */
950	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
951
952	/** NEM/Win: Event injection (known was interruption) pending state. */
953	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
954	/** NEM/Win: Mask. */
955	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
956
957	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
958	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
959	/** HM/SVM: Mask. */
960	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
961
962	/** All CPUM state bits, not including keeper specific ones. */
963	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
964	/** All CPUM state bits, including keeper specific ones. */
965	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
966	/** @} */
967
968
969	/** @name CPUMCTX_INHIBIT_XXX - Interrupt inhibiting flags.
970	* @{ */
971	/** Interrupt shadow following MOV SS or POP SS.
972	*
973	* When this in effect, both maskable and non-maskable interrupts are blocked
974	* from delivery for one instruction. Same for certain debug exceptions too,
975	* unlike the STI variant.
976	*
977	* It is implementation specific whether a sequence of two or more of these
978	* instructions will have any effect on the instruction following the last one
979	* of them. */
980	#define CPUMCTX_INHIBIT_SHADOW_SS RT_BIT_32(0 + CPUMX86EFLAGS_HW_BITS)
981	/** Interrupt shadow following STI.
982	* Same as CPUMCTX_INHIBIT_SHADOW_SS but without blocking any debug exceptions. */
983	#define CPUMCTX_INHIBIT_SHADOW_STI RT_BIT_32(1 + CPUMX86EFLAGS_HW_BITS)
984	/** Mask combining STI and SS shadowing. */
985	#define CPUMCTX_INHIBIT_SHADOW (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI)
986
987	/** Interrupts blocked by NMI delivery. This condition is cleared by IRET.
988	*
989	* Section "6.7 NONMASKABLE INTERRUPT (NMI)" in Intel SDM Vol 3A states that
990	* "The processor also invokes certain hardware conditions to ensure that no
991	* other interrupts, including NMI interrupts, are received until the NMI
992	* handler has completed executing." This flag indicates that these
993	* conditions are currently active.
994	*
995	* @todo this does not really need to be in the lower 32-bits of EFLAGS.
996	*/
997	#define CPUMCTX_INHIBIT_NMI RT_BIT_32(2 + CPUMX86EFLAGS_HW_BITS)
998
999	/** Mask containing all the interrupt inhibit bits. */
1000	#define CPUMCTX_INHIBIT_ALL_MASK (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI \| CPUMCTX_INHIBIT_NMI)
1001	AssertCompile(CPUMCTX_INHIBIT_ALL_MASK < UINT32_MAX);
1002	/** @} */
1003
1004	/** @name CPUMCTX_DBG_XXX - Pending debug events.
1005	* @{ */
1006	/** Hit guest DR0 breakpoint. */
1007	#define CPUMCTX_DBG_HIT_DR0 RT_BIT_32(CPUMCTX_DBG_HIT_DR0_BIT)
1008	#define CPUMCTX_DBG_HIT_DR0_BIT (3 + CPUMX86EFLAGS_HW_BITS)
1009	/** Hit guest DR1 breakpoint. */
1010	#define CPUMCTX_DBG_HIT_DR1 RT_BIT_32(CPUMCTX_DBG_HIT_DR1_BIT)
1011	#define CPUMCTX_DBG_HIT_DR1_BIT (4 + CPUMX86EFLAGS_HW_BITS)
1012	/** Hit guest DR2 breakpoint. */
1013	#define CPUMCTX_DBG_HIT_DR2 RT_BIT_32(CPUMCTX_DBG_HIT_DR2_BIT)
1014	#define CPUMCTX_DBG_HIT_DR2_BIT (5 + CPUMX86EFLAGS_HW_BITS)
1015	/** Hit guest DR3 breakpoint. */
1016	#define CPUMCTX_DBG_HIT_DR3 RT_BIT_32(CPUMCTX_DBG_HIT_DR3_BIT)
1017	#define CPUMCTX_DBG_HIT_DR3_BIT (6 + CPUMX86EFLAGS_HW_BITS)
1018	/** Silent guest DRx breakpoint (presistent Intel errata fun). */
1019	#define CPUMCTX_DBG_HIT_DRX_SILENT RT_BIT_32(CPUMCTX_DBG_HIT_DRX_SILENT_BIT)
1020	#define CPUMCTX_DBG_HIT_DRX_SILENT_BIT (7 + CPUMX86EFLAGS_HW_BITS)
1021	/** Shift for the CPUMCTX_DBG_HIT_DRx bits. */
1022	#define CPUMCTX_DBG_HIT_DRX_SHIFT CPUMCTX_DBG_HIT_DR0_BIT
1023	/** Mask of all guest pending DR0-DR3 indicators (excluding the silent). */
1024	#define CPUMCTX_DBG_HIT_DRX_MASK_NONSILENT (CPUMCTX_DBG_HIT_DR0 \| CPUMCTX_DBG_HIT_DR1 \| CPUMCTX_DBG_HIT_DR2 \| CPUMCTX_DBG_HIT_DR3)
1025	/** Mask of all guest pending DR0-DR3 + silent breakpoint indicators. */
1026	#define CPUMCTX_DBG_HIT_DRX_MASK (CPUMCTX_DBG_HIT_DRX_MASK_NONSILENT \| CPUMCTX_DBG_HIT_DRX_SILENT)
1027	/** DBGF event/breakpoint pending. */
1028	#define CPUMCTX_DBG_DBGF_EVENT RT_BIT_32(CPUMCTX_DBG_DBGF_EVENT_BIT)
1029	#define CPUMCTX_DBG_DBGF_EVENT_BIT (8 + CPUMX86EFLAGS_HW_BITS)
1030	/** DBGF event/breakpoint pending. */
1031	#define CPUMCTX_DBG_DBGF_BP RT_BIT_32(CPUMCTX_DBG_DBGF_BP_BIT)
1032	#define CPUMCTX_DBG_DBGF_BP_BIT (9 + CPUMX86EFLAGS_HW_BITS)
1033	/** Mask of all DBGF indicators. */
1034	#define CPUMCTX_DBG_DBGF_MASK (CPUMCTX_DBG_DBGF_EVENT \| CPUMCTX_DBG_DBGF_BP)
1035	AssertCompile((CPUMCTX_DBG_HIT_DRX_MASK \| CPUMCTX_DBG_DBGF_MASK) < UINT32_MAX);
1036	/** @} */
1037
1038	/** Maximum number of variable-range MTRR pairs supported.
1039	*
1040	* Intel documents upto 10, see IA32_MTRR_PHYS[BASE\|MASK](0..9).
1041	* AMD documents upto 8, see MTRR_phys[Base\|Mask](0..7)
1042	* Hyper-V documents upto 16, see WHvX64RegisterMsrMtrrPhys[Base\|Mask](0..F).
1043	*
1044	* CPUs can in theory accomodate upto 39 pairs ([0x200,0x201]..[0x24e,0x24f])
1045	* unless AMD/Intel decides to put something else in this range.
1046	*/
1047	#define CPUMCTX_MAX_MTRRVAR_COUNT 16
1048
1049
1050	/**
1051	* Additional guest MSRs (i.e. not part of the CPU context structure).
1052	*
1053	* @remarks Never change the order here because of the saved stated! The size
1054	* can in theory be changed, but keep older VBox versions in mind.
1055	*/
1056	typedef union CPUMCTXMSRS
1057	{
1058	struct
1059	{
1060	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
1061	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
1062	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
1063	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
1064	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
1065	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
1066	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
1067	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
1068	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
1069	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
1070	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
1071	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
1072	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
1073	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
1074	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
1075	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
1076	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
1077	uint64_t MtrrCap; /*< IA32_MTRR_CAP /
1078	X86MTRRVAR aMtrrVarMsrs[CPUMCTX_MAX_MTRRVAR_COUNT]; /*< IA32_MTRR_PHYSBASE, IA32_MTRR_PHYSMASK /
1079	} msr;
1080	uint64_t au64[64];
1081	} CPUMCTXMSRS;
1082	/** Pointer to the guest MSR state. */
1083	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1084	/** Pointer to the const guest MSR state. */
1085	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1086
1087	/** @} */
1088
1089	RT_C_DECLS_END
1090
1091	#endif /* !VBOX_INCLUDED_vmm_cpumctx_x86_amd64_h */
1092

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source: vbox/trunk/include/VBox/vmm/cpumctx-x86-amd64.h

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