VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h

Last change on this file was 109031, checked in by vboxsync, 2 weeks ago

VBoxCpuReport,VMM/CPUM,iprt/armv8.h: Deal with core variations on arm CPUs when generating reports for them. Fixes. [build fix] jiraref:VBP-1598
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 76.4 KB
Line 
1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_cpum_h
37#define VBOX_INCLUDED_vmm_cpum_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <VBox/types.h>
43#include <VBox/vmm/cpumctx.h>
44#include <VBox/vmm/stam.h>
45#include <VBox/vmm/vmapi.h>
46#include <VBox/vmm/cpum-common.h>
47
48
49/** @defgroup grp_cpum The CPU Monitor / Manager API
50 * @ingroup grp_vmm
51 * @{
52 */
53
54/**
55 * CPU Vendor.
56 */
57typedef enum CPUMCPUVENDOR
58{
59 CPUMCPUVENDOR_INVALID = 0,
60 CPUMCPUVENDOR_INTEL,
61 CPUMCPUVENDOR_AMD,
62 CPUMCPUVENDOR_VIA,
63 CPUMCPUVENDOR_CYRIX,
64 CPUMCPUVENDOR_SHANGHAI,
65 CPUMCPUVENDOR_HYGON,
66
67 /* ARM: */
68 CPUMCPUVENDOR_ARM,
69 CPUMCPUVENDOR_BROADCOM,
70 CPUMCPUVENDOR_QUALCOMM,
71 CPUMCPUVENDOR_APPLE,
72 CPUMCPUVENDOR_AMPERE,
73
74 CPUMCPUVENDOR_UNKNOWN,
75 /** 32bit hackishness. */
76 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
77} CPUMCPUVENDOR;
78
79
80/**
81 * CPU architecture.
82 */
83typedef enum CPUMARCH
84{
85 /** Invalid zero value. */
86 kCpumArch_Invalid = 0,
87 /** x86 based architecture (includes 64-bit). */
88 kCpumArch_X86,
89 /** ARM based architecture (includs both AArch32 and AArch64). */
90 kCpumArch_Arm,
91
92 /** @todo RiscV, Mips, ... ;). */
93
94 /*
95 * Unknown.
96 */
97 kCpumArch_Unknown,
98
99 kCpumArch_32BitHack = 0x7fffffff
100} CPUMARCH;
101
102
103/**
104 * CPU microarchitectures and in processor generations.
105 *
106 * @remarks The separation here is sometimes a little bit too finely grained,
107 * and the differences is more like processor generation than micro
108 * arch. This can be useful, so we'll provide functions for getting at
109 * more coarse grained info.
110 */
111typedef enum CPUMMICROARCH
112{
113 kCpumMicroarch_Invalid = 0,
114
115 /*
116 * x86 and AMD64 CPUs.
117 */
118
119 kCpumMicroarch_Intel_First,
120
121 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
122 kCpumMicroarch_Intel_80186,
123 kCpumMicroarch_Intel_80286,
124 kCpumMicroarch_Intel_80386,
125 kCpumMicroarch_Intel_80486,
126 kCpumMicroarch_Intel_P5,
127
128 kCpumMicroarch_Intel_P6_Core_Atom_First,
129 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
130 kCpumMicroarch_Intel_P6_II,
131 kCpumMicroarch_Intel_P6_III,
132
133 kCpumMicroarch_Intel_P6_M_Banias,
134 kCpumMicroarch_Intel_P6_M_Dothan,
135 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
136
137 kCpumMicroarch_Intel_Core2_First,
138 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /**< 65nm, Merom/Conroe/Kentsfield/Tigerton */
139 kCpumMicroarch_Intel_Core2_Penryn, /**< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown */
140 kCpumMicroarch_Intel_Core2_End,
141
142 kCpumMicroarch_Intel_Core7_First,
143 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
144 kCpumMicroarch_Intel_Core7_Westmere,
145 kCpumMicroarch_Intel_Core7_SandyBridge,
146 kCpumMicroarch_Intel_Core7_IvyBridge,
147 kCpumMicroarch_Intel_Core7_Haswell,
148 kCpumMicroarch_Intel_Core7_Broadwell,
149 kCpumMicroarch_Intel_Core7_Skylake,
150 kCpumMicroarch_Intel_Core7_KabyLake,
151 kCpumMicroarch_Intel_Core7_CoffeeLake,
152 kCpumMicroarch_Intel_Core7_WhiskeyLake,
153 kCpumMicroarch_Intel_Core7_CascadeLake,
154 kCpumMicroarch_Intel_Core7_CannonLake, /**< Limited 10nm. */
155 kCpumMicroarch_Intel_Core7_CometLake, /**< 10th gen, 14nm desktop + high power mobile. */
156 kCpumMicroarch_Intel_Core7_IceLake, /**< 10th gen, 10nm mobile and some Xeons. Actually 'Sunny Cove' march. */
157 kCpumMicroarch_Intel_Core7_SunnyCove = kCpumMicroarch_Intel_Core7_IceLake,
158 kCpumMicroarch_Intel_Core7_RocketLake, /**< 11th gen, 14nm desktop + high power mobile. Aka 'Cypress Cove', backport of 'Willow Cove' to 14nm. */
159 kCpumMicroarch_Intel_Core7_CypressCove = kCpumMicroarch_Intel_Core7_RocketLake,
160 kCpumMicroarch_Intel_Core7_TigerLake, /**< 11th gen, 10nm mobile. Actually 'Willow Cove' march. */
161 kCpumMicroarch_Intel_Core7_WillowCove = kCpumMicroarch_Intel_Core7_TigerLake,
162 kCpumMicroarch_Intel_Core7_AlderLake, /**< 12th gen, 10nm all platforms(?). */
163 kCpumMicroarch_Intel_Core7_SapphireRapids, /**< 12th? gen, 10nm server? */
164 kCpumMicroarch_Intel_Core7_End,
165
166 kCpumMicroarch_Intel_Atom_First,
167 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
168 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
169 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
170 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
171 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
172 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
173 kCpumMicroarch_Intel_Atom_GoldmontPlus, /**< 14nm */
174 kCpumMicroarch_Intel_Atom_Unknown,
175 kCpumMicroarch_Intel_Atom_End,
176
177
178 kCpumMicroarch_Intel_Phi_First,
179 kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
180 kCpumMicroarch_Intel_Phi_KnightsCorner,
181 kCpumMicroarch_Intel_Phi_KnightsLanding,
182 kCpumMicroarch_Intel_Phi_KnightsHill,
183 kCpumMicroarch_Intel_Phi_KnightsMill,
184 kCpumMicroarch_Intel_Phi_End,
185
186 kCpumMicroarch_Intel_P6_Core_Atom_End,
187
188 kCpumMicroarch_Intel_NB_First,
189 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
190 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
191 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
192 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
193 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
194 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
195 kCpumMicroarch_Intel_NB_Unknown,
196 kCpumMicroarch_Intel_NB_End,
197
198 kCpumMicroarch_Intel_Unknown,
199 kCpumMicroarch_Intel_End,
200
201 kCpumMicroarch_AMD_First,
202 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
203 kCpumMicroarch_AMD_Am386,
204 kCpumMicroarch_AMD_Am486,
205 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
206 kCpumMicroarch_AMD_K5,
207 kCpumMicroarch_AMD_K6,
208
209 kCpumMicroarch_AMD_K7_First,
210 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
211 kCpumMicroarch_AMD_K7_Spitfire,
212 kCpumMicroarch_AMD_K7_Thunderbird,
213 kCpumMicroarch_AMD_K7_Morgan,
214 kCpumMicroarch_AMD_K7_Thoroughbred,
215 kCpumMicroarch_AMD_K7_Barton,
216 kCpumMicroarch_AMD_K7_Unknown,
217 kCpumMicroarch_AMD_K7_End,
218
219 kCpumMicroarch_AMD_K8_First,
220 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
221 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
222 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
223 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
224 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
225 kCpumMicroarch_AMD_K8_End,
226
227 kCpumMicroarch_AMD_K10,
228 kCpumMicroarch_AMD_K10_Lion,
229 kCpumMicroarch_AMD_K10_Llano,
230 kCpumMicroarch_AMD_Bobcat,
231 kCpumMicroarch_AMD_Jaguar,
232
233 kCpumMicroarch_AMD_15h_First,
234 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
235 kCpumMicroarch_AMD_15h_Piledriver,
236 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
237 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
238 kCpumMicroarch_AMD_15h_Unknown,
239 kCpumMicroarch_AMD_15h_End,
240
241 kCpumMicroarch_AMD_16h_First,
242 kCpumMicroarch_AMD_16h_End,
243
244 kCpumMicroarch_AMD_Zen_First,
245 kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
246 kCpumMicroarch_AMD_Zen_End,
247
248 kCpumMicroarch_AMD_Unknown,
249 kCpumMicroarch_AMD_End,
250
251 kCpumMicroarch_Hygon_First,
252 kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
253 kCpumMicroarch_Hygon_Unknown,
254 kCpumMicroarch_Hygon_End,
255
256 kCpumMicroarch_VIA_First,
257 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
258 kCpumMicroarch_Centaur_C2,
259 kCpumMicroarch_Centaur_C3,
260 kCpumMicroarch_VIA_C3_M2,
261 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
262 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
263 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
264 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
265 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
266 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
267 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
268 kCpumMicroarch_VIA_Isaiah,
269 kCpumMicroarch_VIA_Unknown,
270 kCpumMicroarch_VIA_End,
271
272 kCpumMicroarch_Shanghai_First,
273 kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
274 kCpumMicroarch_Shanghai_Unknown,
275 kCpumMicroarch_Shanghai_End,
276
277 kCpumMicroarch_Cyrix_First,
278 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
279 kCpumMicroarch_Cyrix_M1,
280 kCpumMicroarch_Cyrix_MediaGX,
281 kCpumMicroarch_Cyrix_MediaGXm,
282 kCpumMicroarch_Cyrix_M2,
283 kCpumMicroarch_Cyrix_Unknown,
284 kCpumMicroarch_Cyrix_End,
285
286 kCpumMicroarch_NEC_First,
287 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
288 kCpumMicroarch_NEC_V30,
289 kCpumMicroarch_NEC_End,
290
291 /*
292 * ARM CPUs.
293 */
294 kCpumMicroarch_Apple_First,
295 kCpumMicroarch_Apple_M1 = kCpumMicroarch_Apple_First,
296 kCpumMicroarch_Apple_M2,
297 kCpumMicroarch_Apple_M3,
298 kCpumMicroarch_Apple_M4,
299 kCpumMicroarch_Apple_End,
300
301 kCpumMicroarch_Qualcomm_First,
302 kCpumMicroarch_Qualcomm_Kyro = kCpumMicroarch_Qualcomm_First,
303 kCpumMicroarch_Qualcomm_Oryon,
304 kCpumMicroarch_Qualcomm_End,
305
306 /*
307 * Unknown.
308 */
309 kCpumMicroarch_Unknown,
310
311 kCpumMicroarch_32BitHack = 0x7fffffff
312} CPUMMICROARCH;
313
314
315/** Predicate macro for catching netburst CPUs. */
316#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
317 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
318
319/** Predicate macro for catching Core7 CPUs. */
320#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
321 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
322
323/** Predicate macro for catching Core 2 CPUs. */
324#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
325 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
326
327/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
328#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
329 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
330
331/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
332#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
333 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
334
335/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
336#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
337
338/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
339#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
340
341/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
342#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
343
344/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
345#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
346
347/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
348 * decendants). */
349#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
350 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
351
352/** Predicate macro for catching AMD Family 16H CPUs. */
353#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
354 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
355
356/** Predicate macro for catching AMD Zen Family CPUs. */
357#define CPUMMICROARCH_IS_AMD_FAM_ZEN(a_enmMicroarch) \
358 ((a_enmMicroarch) >= kCpumMicroarch_AMD_Zen_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_Zen_End)
359
360/** Predicate macro for catching Apple (ARM) CPUs. */
361#define CPUMMICROARCH_IS_APPLE(a_enmMicroarch) \
362 ((a_enmMicroarch) >= kCpumMicroarch_Apple_First && (a_enmMicroarch) <= kCpumMicroarch_Apple_End)
363
364
365/**
366 * Common portion of the CPU feature structures.
367 */
368typedef struct CPUMFEATURESCOMMON
369{
370 /** The microarchitecture. */
371#ifndef VBOX_FOR_DTRACE_LIB
372 CPUMMICROARCH enmMicroarch;
373#else
374 uint32_t enmMicroarch;
375#endif
376 /** The CPU vendor (CPUMCPUVENDOR). */
377 uint8_t enmCpuVendor;
378 /** The maximum physical address width of the CPU. */
379 uint8_t cMaxPhysAddrWidth;
380 /** The maximum linear address width of the CPU. */
381 uint8_t cMaxLinearAddrWidth;
382} CPUMFEATURESCOMMON;
383
384/**
385 * CPU features and quirks for X86.
386 *
387 * This is mostly exploded CPUID info.
388 */
389typedef struct CPUMFEATURESX86
390{
391 /** The microarchitecture. */
392#ifndef VBOX_FOR_DTRACE_LIB
393 CPUMMICROARCH enmMicroarch;
394#else
395 uint32_t enmMicroarch;
396#endif
397 /** The CPU vendor (CPUMCPUVENDOR). */
398 uint8_t enmCpuVendor;
399 /** The maximum physical address width of the CPU. */
400 uint8_t cMaxPhysAddrWidth;
401 /** The maximum linear address width of the CPU. */
402 uint8_t cMaxLinearAddrWidth;
403
404 /** The CPU family. */
405 uint8_t uFamily;
406 /** The CPU model. */
407 uint8_t uModel;
408 /** The CPU stepping. */
409 uint8_t uStepping;
410 /** Max size of the extended state (or FPU state if no XSAVE). */
411 uint16_t cbMaxExtendedState;
412
413 /** Supports MSRs. */
414 uint32_t fMsr : 1;
415 /** Supports the page size extension (4/2 MB pages). */
416 uint32_t fPse : 1;
417 /** Supports 36-bit page size extension (4 MB pages can map memory above
418 * 4GB). */
419 uint32_t fPse36 : 1;
420 /** Supports physical address extension (PAE). */
421 uint32_t fPae : 1;
422 /** Supports page-global extension (PGE). */
423 uint32_t fPge : 1;
424 /** Page attribute table (PAT) support (page level cache control). */
425 uint32_t fPat : 1;
426 /** Supports the FXSAVE and FXRSTOR instructions. */
427 uint32_t fFxSaveRstor : 1;
428 /** Supports the XSAVE and XRSTOR instructions. */
429 uint32_t fXSaveRstor : 1;
430 /** Supports the XSAVEOPT instruction. */
431 uint32_t fXSaveOpt : 1;
432 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
433 uint32_t fOpSysXSaveRstor : 1;
434 /** Supports MMX. */
435 uint32_t fMmx : 1;
436 /** Supports AMD extensions to MMX instructions. */
437 uint32_t fAmdMmxExts : 1;
438 /** Supports SSE. */
439 uint32_t fSse : 1;
440 /** Supports SSE2. */
441 uint32_t fSse2 : 1;
442 /** Supports SSE3. */
443 uint32_t fSse3 : 1;
444 /** Supports SSSE3. */
445 uint32_t fSsse3 : 1;
446 /** Supports SSE4.1. */
447 uint32_t fSse41 : 1;
448 /** Supports SSE4.2. */
449 uint32_t fSse42 : 1;
450 /** Supports AVX. */
451 uint32_t fAvx : 1;
452 /** Supports AVX2. */
453 uint32_t fAvx2 : 1;
454 /** Supports AVX512 foundation. */
455 uint32_t fAvx512Foundation : 1;
456 /** Supports RDTSC. */
457 uint32_t fTsc : 1;
458 /** Intel SYSENTER/SYSEXIT support */
459 uint32_t fSysEnter : 1;
460 /** Supports MTRR. */
461 uint32_t fMtrr : 1;
462 /** First generation APIC. */
463 uint32_t fApic : 1;
464 /** Second generation APIC. */
465 uint32_t fX2Apic : 1;
466 /** Hypervisor present. */
467 uint32_t fHypervisorPresent : 1;
468 /** MWAIT & MONITOR instructions supported. */
469 uint32_t fMonitorMWait : 1;
470 /** MWAIT Extensions present. */
471 uint32_t fMWaitExtensions : 1;
472 /** Supports CMPXCHG8B. */
473 uint32_t fCmpXchg8b : 1;
474 /** Supports CMPXCHG16B in 64-bit mode. */
475 uint32_t fCmpXchg16b : 1;
476 /** Supports CLFLUSH. */
477 uint32_t fClFlush : 1;
478 /** Supports CLFLUSHOPT. */
479 uint32_t fClFlushOpt : 1;
480 /** Supports IA32_PRED_CMD.IBPB. */
481 uint32_t fIbpb : 1;
482 /** Supports the IA32_SPEC_CTRL MSR (summary of the next). */
483 uint32_t fSpecCtrlMsr : 1;
484 /** Supports IA32_SPEC_CTRL.IBRS. */
485 uint32_t fIbrs : 1;
486 /** Supports IA32_SPEC_CTRL.STIBP. */
487 uint32_t fStibp : 1;
488 /** Supports IA32_SPEC_CTRL.SSBD. */
489 uint32_t fSsbd : 1;
490 /** Supports IA32_SPEC_CTRL.PSFD. */
491 uint32_t fPsfd : 1;
492 /** Supports IA32_SPEC_CTRL.IPRED_DIS_U/S. */
493 uint32_t fIpredCtrl : 1;
494 /** Supports IA32_SPEC_CTRL.RRSBA_DIS_U/S. */
495 uint32_t fRrsbaCtrl : 1;
496 /** Supports IA32_SPEC_CTRL.DDPD_DIS_U. */
497 uint32_t fDdpdU : 1;
498 /** Supports IA32_SPEC_CTRL.BHI_S. */
499 uint32_t fBhiCtrl : 1;
500 /** Supports IA32_FLUSH_CMD. */
501 uint32_t fFlushCmd : 1;
502 /** Supports IA32_ARCH_CAP. */
503 uint32_t fArchCap : 1;
504 /** Supports IA32_CORE_CAP. */
505 uint32_t fCoreCap : 1;
506 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
507 uint32_t fMdsClear : 1;
508 /** Whether susceptible to MXCSR configuration dependent timing (MCDT) behaviour. */
509 uint32_t fMcdtNo : 1;
510 /** Whether susceptible MONITOR/UMONITOR internal table capacity issues. */
511 uint32_t fMonitorMitgNo : 1;
512 /** Supports the UC-lock disable feature. */
513 uint32_t fUcLockDis : 1;
514 /** Supports PCID. */
515 uint32_t fPcid : 1;
516 /** Supports INVPCID. */
517 uint32_t fInvpcid : 1;
518 /** Supports read/write FSGSBASE instructions. */
519 uint32_t fFsGsBase : 1;
520 /** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
521 uint32_t fBmi1 : 1;
522 /** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
523 * and SHLX). */
524 uint32_t fBmi2 : 1;
525 /** Supports POPCNT instruction. */
526 uint32_t fPopCnt : 1;
527 /** Supports RDRAND instruction. */
528 uint32_t fRdRand : 1;
529 /** Supports RDSEED instruction. */
530 uint32_t fRdSeed : 1;
531 /** Supports Hardware Lock Elision (HLE). */
532 uint32_t fHle : 1;
533 /** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */
534 uint32_t fRtm : 1;
535 /** Supports PCLMULQDQ instruction. */
536 uint32_t fPclMul : 1;
537 /** Supports AES-NI (six AESxxx instructions). */
538 uint32_t fAesNi : 1;
539 /** Support MOVBE instruction. */
540 uint32_t fMovBe : 1;
541 /** Support SHA instructions. */
542 uint32_t fSha : 1;
543 /** Support ADX instructions. */
544 uint32_t fAdx : 1;
545 /** Supports FMA. */
546 uint32_t fFma : 1;
547 /** Supports F16C. */
548 uint32_t fF16c : 1;
549
550 /** Supports AMD 3DNow instructions. */
551 uint32_t f3DNow : 1;
552 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
553 uint32_t f3DNowPrefetch : 1;
554
555 /** AMD64: Supports long mode. */
556 uint32_t fLongMode : 1;
557 /** AMD64: SYSCALL/SYSRET support. */
558 uint32_t fSysCall : 1;
559 /** AMD64: No-execute page table bit. */
560 uint32_t fNoExecute : 1;
561 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
562 uint32_t fLahfSahf : 1;
563 /** AMD64: Supports RDTSCP. */
564 uint32_t fRdTscP : 1;
565 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
566 uint32_t fMovCr8In32Bit : 1;
567 /** AMD64: Supports XOP (similar to VEX3/AVX). */
568 uint32_t fXop : 1;
569 /** AMD64: Supports ABM, i.e. the LZCNT instruction. */
570 uint32_t fAbm : 1;
571 /** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
572 * BLSFILL, BLSIC, T1MSKC, and TZMSK). */
573 uint32_t fTbm : 1;
574
575 /** Indicates that FPU instruction and data pointers may leak.
576 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
577 * is only saved and restored if an exception is pending. */
578 uint32_t fLeakyFxSR : 1;
579
580 /** Supports VEX instruction encoding (AVX, BMI, etc.). */
581 uint32_t fVex : 1;
582
583 /** AMD64: Supports AMD SVM. */
584 uint32_t fSvm : 1;
585
586 /** Support for Intel VMX. */
587 uint32_t fVmx : 1;
588
589 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
590 * The details are different for Intel and AMD but both have similar
591 * functionality. */
592 uint32_t fSpeculationControl : 1;
593
594 /** @name MSR_IA32_ARCH_CAPABILITIES
595 * @remarks Only safe use after CPUM ring-0 init!
596 * @{ */
597 /** MSR_IA32_ARCH_CAPABILITIES[0]: RDCL_NO */
598 uint32_t fArchRdclNo : 1;
599 /** MSR_IA32_ARCH_CAPABILITIES[1]: IBRS_ALL */
600 uint32_t fArchIbrsAll : 1;
601 /** MSR_IA32_ARCH_CAPABILITIES[2]: RSB Alternate */
602 uint32_t fArchRsbOverride : 1;
603 /** MSR_IA32_ARCH_CAPABILITIES[3]: SKIP_L1DFL_VMENTRY */
604 uint32_t fArchVmmNeedNotFlushL1d : 1;
605 /** MSR_IA32_ARCH_CAPABILITIES[4]: SSB_NO - No Speculative Store Bypass */
606 uint32_t fArchSsbNo : 1;
607 /** MSR_IA32_ARCH_CAPABILITIES[5]: MDS_NO - No Microarchitecural Data Sampling */
608 uint32_t fArchMdsNo : 1;
609 /** MSR_IA32_ARCH_CAPABILITIES[6]: IF_PSCHANGE_MC_NO */
610 uint32_t fArchIfPschangeMscNo : 1;
611 /** MSR_IA32_ARCH_CAPABILITIES[7]: TSX_CTRL (MSR: IA32_TSX_CTRL_MSR[1:0]) */
612 uint32_t fArchTsxCtrl : 1;
613 /** MSR_IA32_ARCH_CAPABILITIES[8]: TAA_NO - No Transactional Synchronization
614 * Extensions Asynchronous Abort. */
615 uint32_t fArchTaaNo : 1;
616 /** MSR_IA32_ARCH_CAPABILITIES[10]: MISC_PACKAGE_CTRLS (MSR: IA32_UARCH_MISC_CTL) */
617 uint32_t fArchMiscPackageCtrls : 1;
618 /** MSR_IA32_ARCH_CAPABILITIES[11]: ENERGY_FILTERING_CTL (MSR: IA32_MISC_PACKAGE_CTLS[0]) */
619 uint32_t fArchEnergyFilteringCtl : 1;
620 /** MSR_IA32_ARCH_CAPABILITIES[12]: DOITM (MSR: IA32_UARCH_MISC_CTL[0]) */
621 uint32_t fArchDoitm : 1;
622 /** MSR_IA32_ARCH_CAPABILITIES[13]: SBDR_SSDP_NO - No Shared Buffers Data Read
623 * nor Sideband Stale Data Propagator issues. */
624 uint32_t fArchSbdrSsdpNo : 1;
625 /** MSR_IA32_ARCH_CAPABILITIES[14]: FBSDP_NO - Fill Buffer Stale Data Propagator */
626 uint32_t fArchFbsdpNo : 1;
627 /** MSR_IA32_ARCH_CAPABILITIES[15]: PSDP_NO - Primary Stale Data Propagator */
628 uint32_t fArchPsdpNo : 1;
629 /** MSR_IA32_ARCH_CAPABILITIES[17]: FB_CLEAR (VERW) */
630 uint32_t fArchFbClear : 1;
631 /** MSR_IA32_ARCH_CAPABILITIES[18]: FB_CLEAR_CTRL (MSR: IA32_MCU_OPT_CTRL[3]) */
632 uint32_t fArchFbClearCtrl : 1;
633 /** MSR_IA32_ARCH_CAPABILITIES[19]: RRSBA */
634 uint32_t fArchRrsba : 1;
635 /** MSR_IA32_ARCH_CAPABILITIES[20]: BHI_NO */
636 uint32_t fArchBhiNo : 1;
637 /** MSR_IA32_ARCH_CAPABILITIES[21]: XAPIC_DISABLE_STATUS (MSR: IA32_XAPIC_DISABLE_STATUS ) */
638 uint32_t fArchXapicDisableStatus : 1;
639 /** MSR_IA32_ARCH_CAPABILITIES[23]: OVERCLOCKING_STATUS (MSR: IA32_OVERCLOCKING STATUS) */
640 uint32_t fArchOverclockingStatus : 1;
641 /** MSR_IA32_ARCH_CAPABILITIES[24]: PBRSB_NO - No post-barrier Return Stack Buffer predictions */
642 uint32_t fArchPbrsbNo : 1;
643 /** MSR_IA32_ARCH_CAPABILITIES[25]: GDS_CTRL (MSR: IA32_MCU_OPT_CTRL[5:4]) */
644 uint32_t fArchGdsCtrl : 1;
645 /** MSR_IA32_ARCH_CAPABILITIES[26]: GDS_NO - No Gather Data Sampling */
646 uint32_t fArchGdsNo : 1;
647 /** MSR_IA32_ARCH_CAPABILITIES[27]: RFDS_NO - No Register File Data Sampling */
648 uint32_t fArchRfdsNo : 1;
649 /** MSR_IA32_ARCH_CAPABILITIES[28]: RFDS_CLEAR (VERW++) */
650 uint32_t fArchRfdsClear : 1;
651 /** MSR_IA32_ARCH_CAPABILITIES[29]: IGN_UMONITOR_SUPPORT (MSR: IA32_MCU_OPT_CTRL[6]) */
652 uint32_t fArchIgnUmonitorSupport : 1;
653 /** MSR_IA32_ARCH_CAPABILITIES[30]: MON_UMON_MITG_SUPPORT (MSR: IA32_MCU_OPT_CTRL[7]) */
654 uint32_t fArchMonUmonMitigSupport : 1;
655 /** @} */
656
657 /** Alignment padding / reserved for future use. */
658 uint32_t fPadding0 : 17;
659 uint32_t auPadding[3];
660
661 /** @name SVM
662 * @{ */
663 /** SVM: Supports Nested-paging. */
664 uint32_t fSvmNestedPaging : 1;
665 /** SVM: Support LBR (Last Branch Record) virtualization. */
666 uint32_t fSvmLbrVirt : 1;
667 /** SVM: Supports SVM lock. */
668 uint32_t fSvmSvmLock : 1;
669 /** SVM: Supports Next RIP save. */
670 uint32_t fSvmNextRipSave : 1;
671 /** SVM: Supports TSC rate MSR. */
672 uint32_t fSvmTscRateMsr : 1;
673 /** SVM: Supports VMCB clean bits. */
674 uint32_t fSvmVmcbClean : 1;
675 /** SVM: Supports Flush-by-ASID. */
676 uint32_t fSvmFlusbByAsid : 1;
677 /** SVM: Supports decode assist. */
678 uint32_t fSvmDecodeAssists : 1;
679 /** SVM: Supports Pause filter. */
680 uint32_t fSvmPauseFilter : 1;
681 /** SVM: Supports Pause filter threshold. */
682 uint32_t fSvmPauseFilterThreshold : 1;
683 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
684 uint32_t fSvmAvic : 1;
685 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
686 uint32_t fSvmVirtVmsaveVmload : 1;
687 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
688 uint32_t fSvmVGif : 1;
689 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
690 uint32_t fSvmGmet : 1;
691 /** SVM: Supports AVIC in x2APIC mode. */
692 uint32_t fSvmX2Avic : 1;
693 /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
694 uint32_t fSvmSSSCheck : 1;
695 /** SVM: Supports SPEC_CTRL virtualization. */
696 uint32_t fSvmSpecCtrl : 1;
697 /** SVM: Supports Read-Only Guest Page Table feature. */
698 uint32_t fSvmRoGpt : 1;
699 /** SVM: Supports HOST_MCE_OVERRIDE. */
700 uint32_t fSvmHostMceOverride : 1;
701 /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
702 uint32_t fSvmTlbiCtl : 1;
703 /** SVM: Supports NMI virtualization. */
704 uint32_t fSvmVNmi : 1;
705 /** SVM: Supports IBS virtualizaiton. */
706 uint32_t fSvmIbsVirt : 1;
707 /** SVM: Supports Extended LVT AVIC access changes. */
708 uint32_t fSvmExtLvtAvicAccessChg : 1;
709 /** SVM: Supports Guest VMCB address check. */
710 uint32_t fSvmNstVirtVmcbAddrChk : 1;
711 /** SVM: Supports Bus Lock Threshold. */
712 uint32_t fSvmBusLockThreshold : 1;
713 /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
714 uint32_t fSvmPadding0 : 7;
715 /** SVM: Maximum supported ASID. */
716 uint32_t uSvmMaxAsid;
717 /** @} */
718
719
720 /** VMX: Maximum physical address width. */
721 uint32_t cVmxMaxPhysAddrWidth : 8;
722
723 /** @name VMX basic controls.
724 * @{ */
725 /** VMX: Supports INS/OUTS VM-exit instruction info. */
726 uint32_t fVmxInsOutInfo : 1;
727 /** @} */
728
729 /** @name VMX Pin-based controls.
730 * @{ */
731 /** VMX: Supports external interrupt VM-exit. */
732 uint32_t fVmxExtIntExit : 1;
733 /** VMX: Supports NMI VM-exit. */
734 uint32_t fVmxNmiExit : 1;
735 /** VMX: Supports Virtual NMIs. */
736 uint32_t fVmxVirtNmi : 1;
737 /** VMX: Supports preemption timer. */
738 uint32_t fVmxPreemptTimer : 1;
739 /** VMX: Supports posted interrupts. */
740 uint32_t fVmxPostedInt : 1;
741 /** @} */
742
743 /** @name VMX Processor-based controls.
744 * @{ */
745 /** VMX: Supports Interrupt-window exiting. */
746 uint32_t fVmxIntWindowExit : 1;
747 /** VMX: Supports TSC offsetting. */
748 uint32_t fVmxTscOffsetting : 1;
749 /** VMX: Supports HLT exiting. */
750 uint32_t fVmxHltExit : 1;
751 /** VMX: Supports INVLPG exiting. */
752 uint32_t fVmxInvlpgExit : 1;
753 /** VMX: Supports MWAIT exiting. */
754 uint32_t fVmxMwaitExit : 1;
755 /** VMX: Supports RDPMC exiting. */
756 uint32_t fVmxRdpmcExit : 1;
757 /** VMX: Supports RDTSC exiting. */
758 uint32_t fVmxRdtscExit : 1;
759 /** VMX: Supports CR3-load exiting. */
760 uint32_t fVmxCr3LoadExit : 1;
761 /** VMX: Supports CR3-store exiting. */
762 uint32_t fVmxCr3StoreExit : 1;
763 /** VMX: Supports tertiary processor-based VM-execution controls. */
764 uint32_t fVmxTertiaryExecCtls : 1;
765 /** VMX: Supports CR8-load exiting. */
766 uint32_t fVmxCr8LoadExit : 1;
767 /** VMX: Supports CR8-store exiting. */
768 uint32_t fVmxCr8StoreExit : 1;
769 /** VMX: Supports TPR shadow. */
770 uint32_t fVmxUseTprShadow : 1;
771 /** VMX: Supports NMI-window exiting. */
772 uint32_t fVmxNmiWindowExit : 1;
773 /** VMX: Supports Mov-DRx exiting. */
774 uint32_t fVmxMovDRxExit : 1;
775 /** VMX: Supports Unconditional I/O exiting. */
776 uint32_t fVmxUncondIoExit : 1;
777 /** VMX: Supportgs I/O bitmaps. */
778 uint32_t fVmxUseIoBitmaps : 1;
779 /** VMX: Supports Monitor Trap Flag. */
780 uint32_t fVmxMonitorTrapFlag : 1;
781 /** VMX: Supports MSR bitmap. */
782 uint32_t fVmxUseMsrBitmaps : 1;
783 /** VMX: Supports MONITOR exiting. */
784 uint32_t fVmxMonitorExit : 1;
785 /** VMX: Supports PAUSE exiting. */
786 uint32_t fVmxPauseExit : 1;
787 /** VMX: Supports secondary processor-based VM-execution controls. */
788 uint32_t fVmxSecondaryExecCtls : 1;
789 /** @} */
790
791 /** @name VMX Secondary processor-based controls.
792 * @{ */
793 /** VMX: Supports virtualize-APIC access. */
794 uint32_t fVmxVirtApicAccess : 1;
795 /** VMX: Supports EPT (Extended Page Tables). */
796 uint32_t fVmxEpt : 1;
797 /** VMX: Supports descriptor-table exiting. */
798 uint32_t fVmxDescTableExit : 1;
799 /** VMX: Supports RDTSCP. */
800 uint32_t fVmxRdtscp : 1;
801 /** VMX: Supports virtualize-x2APIC mode. */
802 uint32_t fVmxVirtX2ApicMode : 1;
803 /** VMX: Supports VPID. */
804 uint32_t fVmxVpid : 1;
805 /** VMX: Supports WBIND exiting. */
806 uint32_t fVmxWbinvdExit : 1;
807 /** VMX: Supports Unrestricted guest. */
808 uint32_t fVmxUnrestrictedGuest : 1;
809 /** VMX: Supports APIC-register virtualization. */
810 uint32_t fVmxApicRegVirt : 1;
811 /** VMX: Supports virtual-interrupt delivery. */
812 uint32_t fVmxVirtIntDelivery : 1;
813 /** VMX: Supports Pause-loop exiting. */
814 uint32_t fVmxPauseLoopExit : 1;
815 /** VMX: Supports RDRAND exiting. */
816 uint32_t fVmxRdrandExit : 1;
817 /** VMX: Supports INVPCID. */
818 uint32_t fVmxInvpcid : 1;
819 /** VMX: Supports VM functions. */
820 uint32_t fVmxVmFunc : 1;
821 /** VMX: Supports VMCS shadowing. */
822 uint32_t fVmxVmcsShadowing : 1;
823 /** VMX: Supports RDSEED exiting. */
824 uint32_t fVmxRdseedExit : 1;
825 /** VMX: Supports PML. */
826 uint32_t fVmxPml : 1;
827 /** VMX: Supports EPT-violations \#VE. */
828 uint32_t fVmxEptXcptVe : 1;
829 /** VMX: Supports conceal VMX from PT. */
830 uint32_t fVmxConcealVmxFromPt : 1;
831 /** VMX: Supports XSAVES/XRSTORS. */
832 uint32_t fVmxXsavesXrstors : 1;
833 /** VMX: Supports PASID translation. */
834 uint32_t fVmxPasidTranslate : 1;
835 /** VMX: Supports mode-based execute control for EPT. */
836 uint32_t fVmxModeBasedExecuteEpt : 1;
837 /** VMX: Supports sub-page write permissions for EPT. */
838 uint32_t fVmxSppEpt : 1;
839 /** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
840 uint32_t fVmxPtEpt : 1;
841 /** VMX: Supports TSC scaling. */
842 uint32_t fVmxUseTscScaling : 1;
843 /** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
844 uint32_t fVmxUserWaitPause : 1;
845 /** VMX: Supports PCONFIG. */
846 uint32_t fVmxPconfig : 1;
847 /** VMX: Supports enclave (ENCLV) exiting. */
848 uint32_t fVmxEnclvExit : 1;
849 /** VMX: Supports VMM bus-lock detection. */
850 uint32_t fVmxBusLockDetect : 1;
851 /** VMX: Supports instruction timeout. */
852 uint32_t fVmxInstrTimeout : 1;
853 /** @} */
854
855 /** @name VMX Tertiary processor-based controls.
856 * @{ */
857 /** VMX: Supports LOADIWKEY exiting. */
858 uint32_t fVmxLoadIwKeyExit : 1;
859 /** VMX: Supports hypervisor-managed linear address translation (HLAT). */
860 uint32_t fVmxHlat : 1;
861 /** VMX: Supports EPT paging-write control. */
862 uint32_t fVmxEptPagingWrite : 1;
863 /** VMX: Supports Guest-paging verification. */
864 uint32_t fVmxGstPagingVerify : 1;
865 /** VMX: Supports IPI virtualization. */
866 uint32_t fVmxIpiVirt : 1;
867 /** VMX: Supports virtualize IA32_SPEC_CTRL. */
868 uint32_t fVmxVirtSpecCtrl : 1;
869 /** @} */
870
871 /** @name VMX VM-entry controls.
872 * @{ */
873 /** VMX: Supports load-debug controls on VM-entry. */
874 uint32_t fVmxEntryLoadDebugCtls : 1;
875 /** VMX: Supports IA32e mode guest. */
876 uint32_t fVmxIa32eModeGuest : 1;
877 /** VMX: Supports load guest EFER MSR on VM-entry. */
878 uint32_t fVmxEntryLoadEferMsr : 1;
879 /** VMX: Supports load guest PAT MSR on VM-entry. */
880 uint32_t fVmxEntryLoadPatMsr : 1;
881 /** @} */
882
883 /** @name VMX VM-exit controls.
884 * @{ */
885 /** VMX: Supports save debug controls on VM-exit. */
886 uint32_t fVmxExitSaveDebugCtls : 1;
887 /** VMX: Supports host-address space size. */
888 uint32_t fVmxHostAddrSpaceSize : 1;
889 /** VMX: Supports acknowledge external interrupt on VM-exit. */
890 uint32_t fVmxExitAckExtInt : 1;
891 /** VMX: Supports save guest PAT MSR on VM-exit. */
892 uint32_t fVmxExitSavePatMsr : 1;
893 /** VMX: Supports load hsot PAT MSR on VM-exit. */
894 uint32_t fVmxExitLoadPatMsr : 1;
895 /** VMX: Supports save guest EFER MSR on VM-exit. */
896 uint32_t fVmxExitSaveEferMsr : 1;
897 /** VMX: Supports load host EFER MSR on VM-exit. */
898 uint32_t fVmxExitLoadEferMsr : 1;
899 /** VMX: Supports save VMX preemption timer on VM-exit. */
900 uint32_t fVmxSavePreemptTimer : 1;
901 /** VMX: Supports secondary VM-exit controls. */
902 uint32_t fVmxSecondaryExitCtls : 1;
903 /** @} */
904
905 /** @name VMX Miscellaneous data.
906 * @{ */
907 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
908 uint32_t fVmxExitSaveEferLma : 1;
909 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
910 uint32_t fVmxPt : 1;
911 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
912 * VMWRITE cannot modify read-only VM-exit information fields. */
913 uint32_t fVmxVmwriteAll : 1;
914 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
915 * length instructions. */
916 uint32_t fVmxEntryInjectSoftInt : 1;
917 /** @} */
918
919 /** VMX: Padding / reserved for future features. */
920 uint32_t fVmxPadding0 : 7;
921 /** VMX: Padding / reserved for future, making it a total of 128 bits. */
922 uint32_t fVmxPadding1;
923} CPUMFEATURESX86;
924#ifndef VBOX_FOR_DTRACE_LIB
925AssertCompileSize(CPUMFEATURESX86, 64);
926AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor, CPUMFEATURESX86, enmCpuVendor);
927AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch, CPUMFEATURESX86, enmMicroarch);
928AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth, CPUMFEATURESX86, cMaxPhysAddrWidth);
929AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth, CPUMFEATURESX86, cMaxLinearAddrWidth);
930#endif
931
932/**
933 * CPU features and quirks for ARMv8.
934 *
935 * This is mostly exploded CPU feature register info.
936 */
937typedef struct CPUMFEATURESARMV8
938{
939 /** The microarchitecture. */
940#ifndef VBOX_FOR_DTRACE_LIB
941 CPUMMICROARCH enmMicroarch;
942#else
943 uint32_t enmMicroarch;
944#endif
945 /** The CPU vendor (CPUMCPUVENDOR). */
946 uint8_t enmCpuVendor;
947 /** The maximum physical address width of the CPU. */
948 uint8_t cMaxPhysAddrWidth;
949 /** The maximum linear address width of the CPU. */
950 uint8_t cMaxLinearAddrWidth;
951
952 /** The CPU implementer value (from MIDR_EL1). */
953 uint8_t uImplementeter;
954 /** The CPU part number (from MIDR_EL1). */
955 uint16_t uPartNum;
956 /** The CPU variant (from MIDR_EL1). */
957 uint8_t uVariant;
958 /** The CPU revision (from MIDR_EL1). */
959 uint8_t uRevision;
960
961 /** @name Granule sizes supported.
962 * @{ */
963 /** 4KiB translation granule size supported. */
964 uint32_t fTGran4K : 1;
965 /** 16KiB translation granule size supported. */
966 uint32_t fTGran16K : 1;
967 /** 64KiB translation granule size supported. */
968 uint32_t fTGran64K : 1;
969 /** @} */
970
971 /** @name pre-2020 Architecture Extensions.
972 * @{ */
973 /** Supports Advanced SIMD Extension (FEAT_AdvSIMD). */
974 uint32_t fAdvSimd : 1;
975 /** Supports Advanced SIMD AES instructions (FEAT_AES). */
976 uint32_t fAes : 1;
977 /** Supports Advanced SIMD PMULL instructions (FEAT_PMULL). */
978 uint32_t fPmull : 1;
979 /** Supports CP15Disable2 (FEAT_CP15DISABLE2). */
980 uint32_t fCp15Disable2 : 1;
981 /** Supports Cache Speculation Variant 2 (FEAT_CSV2). */
982 uint32_t fCsv2 : 1;
983 /** Supports Cache Speculation Variant 2, version 1.1 (FEAT_CSV2_1p1). */
984 uint32_t fCsv21p1 : 1;
985 /** Supports Cache Speculation Variant 2, version 1.2 (FEAT_CSV2_1p2). */
986 uint32_t fCsv21p2 : 1;
987 /** Supports Cache Speculation Variant 3 (FEAT_CSV3). */
988 uint32_t fCsv3 : 1;
989 /** Supports Data Gahtering Hint (FEAT_DGH). */
990 uint32_t fDgh : 1;
991 /** Supports Double Lock (FEAT_DoubleLock). */
992 uint32_t fDoubleLock : 1;
993 /** Supports Enhanced Translation Synchronization (FEAT_ETS2). */
994 uint32_t fEts2 : 1;
995 /** Supports Floating Point Extensions (FEAT_FP). */
996 uint32_t fFp : 1;
997 /** Supports IVIPT Extensions (FEAT_IVIPT). */
998 uint32_t fIvipt : 1;
999 /** Supports PC Sample-based Profiling Extension (FEAT_PCSRv8). */
1000 uint32_t fPcsrV8 : 1;
1001 /** Supports Speculation Restrictions instructions (FEAT_SPECRES). */
1002 uint32_t fSpecres : 1;
1003 /** Supports Reliability, Availability, and Serviceability (RAS) Extension (FEAT_RAS). */
1004 uint32_t fRas : 1;
1005 /** Supports Speculation Barrier (FEAT_SB). */
1006 uint32_t fSb : 1;
1007 /** Supports Advanced SIMD SHA1 instructions (FEAT_SHA1). */
1008 uint32_t fSha1 : 1;
1009 /** Supports Advanced SIMD SHA256 instructions (FEAT_SHA256). */
1010 uint32_t fSha256 : 1;
1011 /** Supports Speculation Store Bypass Safe (FEAT_SSBS). */
1012 uint32_t fSsbs : 1;
1013 /** Supports MRS and MSR instructions for Speculation Store Bypass Safe version 2 (FEAT_SSBS2). */
1014 uint32_t fSsbs2 : 1;
1015 /** Supports CRC32 instructions (FEAT_CRC32). */
1016 uint32_t fCrc32 : 1;
1017 /** Supports Intermediate chacing of trnslation table walks (FEAT_nTLBPA). */
1018 uint32_t fNTlbpa : 1;
1019 /** Supports debug with VHE (FEAT_Debugv8p1). */
1020 uint32_t fDebugV8p1 : 1;
1021 /** Supports Hierarchical permission disables in translation tables (FEAT_HPDS). */
1022 uint32_t fHpds : 1;
1023 /** Supports Limited ordering regions (FEAT_LOR). */
1024 uint32_t fLor : 1;
1025 /** Supports Lare Systems Extensons (FEAT_LSE). */
1026 uint32_t fLse : 1;
1027 /** Supports Privileged access never (FEAT_PAN). */
1028 uint32_t fPan : 1;
1029 /** Supports Armv8.1 PMU extensions (FEAT_PMUv3p1). */
1030 uint32_t fPmuV3p1 : 1;
1031 /** Supports Advanced SIMD rouding double multiply accumulate instructions (FEAT_RDM). */
1032 uint32_t fRdm : 1;
1033 /** Supports hardware management of the Access flag and dirty state (FEAT_HAFDBS). */
1034 uint32_t fHafdbs : 1;
1035 /** Supports Virtualization Host Extensions (FEAT_VHE). */
1036 uint32_t fVhe : 1;
1037 /** Supports 16-bit VMID (FEAT_VMID16). */
1038 uint32_t fVmid16 : 1;
1039 /** Supports AArch32 BFloat16 instructions (FEAT_AA32BF16). */
1040 uint32_t fAa32Bf16 : 1;
1041 /** Supports AArch32 Hierarchical permission disables (FEAT_AA32HPD). */
1042 uint32_t fAa32Hpd : 1;
1043 /** Supports AArch32 Int8 matrix multiplication instructions (FEAT_AA32I8MM). */
1044 uint32_t fAa32I8mm : 1;
1045 /** Supports AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN (FEAT_PAN2). */
1046 uint32_t fPan2 : 1;
1047 /** Supports AArch64 BFloat16 instructions (FEAT_BF16). */
1048 uint32_t fBf16 : 1;
1049 /** Supports DC CVADP instruction (FEAT_DPB2). */
1050 uint32_t fDpb2 : 1;
1051 /** Supports DC VAP instruction (FEAT_DPB). */
1052 uint32_t fDpb : 1;
1053 /** Supports Debug v8.2 (FEAT_Debugv8p2). */
1054 uint32_t fDebugV8p2 : 1;
1055 /** Supports Advanced SIMD dot product instructions (FEAT_DotProd). */
1056 uint32_t fDotProd : 1;
1057 /** Supports Enhanced Virtualization Traps (FEAT_EVT). */
1058 uint32_t fEvt : 1;
1059 /** Supports Single precision Matrix Multiplication (FEAT_F32MM). */
1060 uint32_t fF32mm : 1;
1061 /** Supports Double precision Matrix Multiplication (FEAT_F64MM). */
1062 uint32_t fF64mm : 1;
1063 /** Supports Floating-point half precision multiplication instructions (FEAT_FHM). */
1064 uint32_t fFhm : 1;
1065 /** Supports Half-precision floating point data processing (FEAT_FP16). */
1066 uint32_t fFp16 : 1;
1067 /** Supports AArch64 Int8 matrix multiplication instructions (FEAT_I8MM). */
1068 uint32_t fI8mm : 1;
1069 /** Supports Implicit Error Synchronization event (FEAT_IESB). */
1070 uint32_t fIesb : 1;
1071 /** Supports Large PA and IPA support (FEAT_LPA). */
1072 uint32_t fLpa : 1;
1073 /** Supports AArch32 Load/Store Multiple instructions atomicity and ordering controls (FEAT_LSMAOC). */
1074 uint32_t fLsmaoc : 1;
1075 /** Supports Large VA support (FEAT_LVA). */
1076 uint32_t fLva : 1;
1077 /** Supports Memory Partitioning and Monitoring Extension (FEAT_MPAM). */
1078 uint32_t fMpam : 1;
1079 /** Supports PC Sample-based Profiling Extension, version 8.2 (FEAT_PCSRv8p2). */
1080 uint32_t fPcsrV8p2 : 1;
1081 /** Supports Advanced SIMD SHA3 instructions (FEAT_SHA3). */
1082 uint32_t fSha3 : 1;
1083 /** Supports Advanced SIMD SHA512 instructions (FEAT_SHA512). */
1084 uint32_t fSha512 : 1;
1085 /** Supports Advanced SIMD SM3 instructions (FEAT_SM3). */
1086 uint32_t fSm3 : 1;
1087 /** Supports Advanced SIMD SM4 instructions (FEAT_SM4). */
1088 uint32_t fSm4 : 1;
1089 /** Supports Statistical Profiling Extension (FEAT_SPE). */
1090 uint32_t fSpe : 1;
1091 /** Supports Scalable Vector Extension (FEAT_SVE). */
1092 uint32_t fSve : 1;
1093 /** Supports Translation Table Common not private translations (FEAT_TTCNP). */
1094 uint32_t fTtcnp : 1;
1095 /** Supports Hierarchical permission disables, version 2 (FEAT_HPDS2). */
1096 uint32_t fHpds2 : 1;
1097 /** Supports Translation table stage 2 Unprivileged Execute-never (FEAT_XNX). */
1098 uint32_t fXnx : 1;
1099 /** Supports Unprivileged Access Override control (FEAT_UAO). */
1100 uint32_t fUao : 1;
1101 /** Supports VMID-aware PIPT instruction cache (FEAT_VPIPT). */
1102 uint32_t fVpipt : 1;
1103 /** Supports Extended cache index (FEAT_CCIDX). */
1104 uint32_t fCcidx : 1;
1105 /** Supports Floating-point complex number instructions (FEAT_FCMA). */
1106 uint32_t fFcma : 1;
1107 /** Supports Debug over Powerdown (FEAT_DoPD). */
1108 uint32_t fDopd : 1;
1109 /** Supports Enhanced pointer authentication (FEAT_EPAC). */
1110 uint32_t fEpac : 1;
1111 /** Supports Faulting on AUT* instructions (FEAT_FPAC). */
1112 uint32_t fFpac : 1;
1113 /** Supports Faulting on combined pointer euthentication instructions (FEAT_FPACCOMBINE). */
1114 uint32_t fFpacCombine : 1;
1115 /** Supports JavaScript conversion instructions (FEAT_JSCVT). */
1116 uint32_t fJscvt : 1;
1117 /** Supports Load-Acquire RCpc instructions (FEAT_LRCPC). */
1118 uint32_t fLrcpc : 1;
1119 /** Supports Nexted Virtualization (FEAT_NV). */
1120 uint32_t fNv : 1;
1121 /** Supports QARMA5 pointer authentication algorithm (FEAT_PACQARMA5). */
1122 uint32_t fPacQarma5 : 1;
1123 /** Supports implementation defined pointer authentication algorithm (FEAT_PACIMP). */
1124 uint32_t fPacImp : 1;
1125 /** Supports Pointer authentication (FEAT_PAuth). */
1126 uint32_t fPAuth : 1;
1127 /** Supports Enhancements to pointer authentication (FEAT_PAuth2). */
1128 uint32_t fPAuth2 : 1;
1129 /** Supports Statistical Profiling Extensions version 1.1 (FEAT_SPEv1p1). */
1130 uint32_t fSpeV1p1 : 1;
1131 /** Supports Activity Monitor Extension, version 1 (FEAT_AMUv1). */
1132 uint32_t fAmuV1 : 1;
1133 /** Supports Generic Counter Scaling (FEAT_CNTSC). */
1134 uint32_t fCntsc : 1;
1135 /** Supports Debug v8.4 (FEAT_Debugv8p4). */
1136 uint32_t fDebugV8p4 : 1;
1137 /** Supports Double Fault Extension (FEAT_DoubleFault). */
1138 uint32_t fDoubleFault : 1;
1139 /** Supports Data Independent Timing instructions (FEAT_DIT). */
1140 uint32_t fDit : 1;
1141 /** Supports Condition flag manipulation isntructions (FEAT_FlagM). */
1142 uint32_t fFlagM : 1;
1143 /** Supports ID space trap handling (FEAT_IDST). */
1144 uint32_t fIdst : 1;
1145 /** Supports Load-Acquire RCpc instructions version 2 (FEAT_LRCPC2). */
1146 uint32_t fLrcpc2 : 1;
1147 /** Supports Large Sytem Extensions version 2 (FEAT_LSE2). */
1148 uint32_t fLse2 : 1;
1149 /** Supports Enhanced nested virtualization support (FEAT_NV2). */
1150 uint32_t fNv2 : 1;
1151 /** Supports Armv8.4 PMU Extensions (FEAT_PMUv3p4). */
1152 uint32_t fPmuV3p4 : 1;
1153 /** Supports RAS Extension v1.1 (FEAT_RASv1p1). */
1154 uint32_t fRasV1p1 : 1;
1155 /** Supports RAS Extension v1.1 System Architecture (FEAT_RASSAv1p1). */
1156 uint32_t fRassaV1p1 : 1;
1157 /** Supports Stage 2 forced Write-Back (FEAT_S2FWB). */
1158 uint32_t fS2Fwb : 1;
1159 /** Supports Secure El2 (FEAT_SEL2). */
1160 uint32_t fSecEl2 : 1;
1161 /** Supports TLB invalidate instructions on Outer Shareable domain (FEAT_TLBIOS). */
1162 uint32_t fTlbios : 1;
1163 /** Supports TLB invalidate range instructions (FEAT_TLBIRANGE). */
1164 uint32_t fTlbirange : 1;
1165 /** Supports Self-hosted Trace Extensions (FEAT_TRF). */
1166 uint32_t fTrf : 1;
1167 /** Supports Translation Table Level (FEAT_TTL). */
1168 uint32_t fTtl : 1;
1169 /** Supports Translation table break-before-make levels (FEAT_BBM). */
1170 uint32_t fBbm : 1;
1171 /** Supports Small translation tables (FEAT_TTST). */
1172 uint32_t fTtst : 1;
1173 /** Supports Branch Target Identification (FEAT_BTI). */
1174 uint32_t fBti : 1;
1175 /** Supports Enhancements to flag manipulation instructions (FEAT_FlagM2). */
1176 uint32_t fFlagM2 : 1;
1177 /** Supports Context synchronization and exception handling (FEAT_ExS). */
1178 uint32_t fExs : 1;
1179 /** Supports Preenting EL0 access to halves of address maps (FEAT_E0PD). */
1180 uint32_t fE0Pd : 1;
1181 /** Supports Floating-point to integer instructions (FEAT_FRINTTS). */
1182 uint32_t fFrintts : 1;
1183 /** Supports Guest translation granule size (FEAT_GTG). */
1184 uint32_t fGtg : 1;
1185 /** Supports Instruction-only Memory Tagging Extension (FEAT_MTE). */
1186 uint32_t fMte : 1;
1187 /** Supports memory Tagging Extension version 2 (FEAT_MTE2). */
1188 uint32_t fMte2 : 1;
1189 /** Supports Armv8.5 PMU Extensions (FEAT_PMUv3p5). */
1190 uint32_t fPmuV3p5 : 1;
1191 /** Supports Random number generator (FEAT_RNG). */
1192 uint32_t fRng : 1;
1193 /** Supports AMU Extensions version 1.1 (FEAT_AMUv1p1). */
1194 uint32_t fAmuV1p1 : 1;
1195 /** Supports Enhanced Counter Virtualization (FEAT_ECV). */
1196 uint32_t fEcv : 1;
1197 /** Supports Fine Grain Traps (FEAT_FGT). */
1198 uint32_t fFgt : 1;
1199 /** Supports Memory Partitioning and Monitoring version 0.1 (FEAT_MPAMv0p1). */
1200 uint32_t fMpamV0p1 : 1;
1201 /** Supports Memory Partitioning and Monitoring version 1.1 (FEAT_MPAMv1p1). */
1202 uint32_t fMpamV1p1 : 1;
1203 /** Supports Multi-threaded PMU Extensions (FEAT_MTPMU). */
1204 uint32_t fMtPmu : 1;
1205 /** Supports Delayed Trapping of WFE (FEAT_TWED). */
1206 uint32_t fTwed : 1;
1207 /** Supports Embbedded Trace Macrocell version 4 (FEAT_ETMv4). */
1208 uint32_t fEtmV4 : 1;
1209 /** Supports Embbedded Trace Macrocell version 4.1 (FEAT_ETMv4p1). */
1210 uint32_t fEtmV4p1 : 1;
1211 /** Supports Embbedded Trace Macrocell version 4.2 (FEAT_ETMv4p2). */
1212 uint32_t fEtmV4p2 : 1;
1213 /** Supports Embbedded Trace Macrocell version 4.3 (FEAT_ETMv4p3). */
1214 uint32_t fEtmV4p3 : 1;
1215 /** Supports Embbedded Trace Macrocell version 4.4 (FEAT_ETMv4p4). */
1216 uint32_t fEtmV4p4 : 1;
1217 /** Supports Embbedded Trace Macrocell version 4.5 (FEAT_ETMv4p5). */
1218 uint32_t fEtmV4p5 : 1;
1219 /** Supports Embbedded Trace Macrocell version 4.6 (FEAT_ETMv4p6). */
1220 uint32_t fEtmV4p6 : 1;
1221 /** Supports Generic Interrupt Controller version 3 (FEAT_GICv3). */
1222 uint32_t fGicV3 : 1;
1223 /** Supports Generic Interrupt Controller version 3.1 (FEAT_GICv3p1). */
1224 uint32_t fGicV3p1 : 1;
1225 /** Supports Trapping Non-secure EL1 writes to ICV_DIR (FEAT_GICv3_TDIR). */
1226 uint32_t fGicV3Tdir : 1;
1227 /** Supports Generic Interrupt Controller version 4 (FEAT_GICv4). */
1228 uint32_t fGicV4 : 1;
1229 /** Supports Generic Interrupt Controller version 4.1 (FEAT_GICv4p1). */
1230 uint32_t fGicV4p1 : 1;
1231 /** Supports PMU extension, version 3 (FEAT_PMUv3). */
1232 uint32_t fPmuV3 : 1;
1233 /** Supports Embedded Trace Extension (FEAT_ETE). */
1234 uint32_t fEte : 1;
1235 /** Supports Embedded Trace Extension, version 1.1 (FEAT_ETEv1p1). */
1236 uint32_t fEteV1p1 : 1;
1237 /** Supports Embedded Trace Extension, version 1.2 (FEAT_ETEv1p2). */
1238 uint32_t fEteV1p2 : 1;
1239 /** Supports Scalable Vector Extension version 2 (FEAT_SVE2). */
1240 uint32_t fSve2 : 1;
1241 /** Supports Scalable Vector AES instructions (FEAT_SVE_AES). */
1242 uint32_t fSveAes : 1;
1243 /** Supports Scalable Vector PMULL instructions (FEAT_SVE_PMULL128). */
1244 uint32_t fSvePmull128 : 1;
1245 /** Supports Scalable Vector Bit Permutes instructions (FEAT_SVE_BitPerm). */
1246 uint32_t fSveBitPerm : 1;
1247 /** Supports Scalable Vector SHA3 instructions (FEAT_SVE_SHA3). */
1248 uint32_t fSveSha3 : 1;
1249 /** Supports Scalable Vector SM4 instructions (FEAT_SVE_SM4). */
1250 uint32_t fSveSm4 : 1;
1251 /** Supports Transactional Memory Extension (FEAT_TME). */
1252 uint32_t fTme : 1;
1253 /** Supports Trace Buffer Extension (FEAT_TRBE). */
1254 uint32_t fTrbe : 1;
1255 /** Supports Scalable Matrix Extension (FEAT_SME). */
1256 uint32_t fSme : 1;
1257 /** @} */
1258
1259 /** @name 2020 Architecture Extensions.
1260 * @{ */
1261 /** Supports Alternate floating-point behavior (FEAT_AFP). */
1262 uint32_t fAfp : 1;
1263 /** Supports HCRX_EL2 register (FEAT_HCX). */
1264 uint32_t fHcx : 1;
1265 /** Supports Larger phsical address for 4KiB and 16KiB translation granules (FEAT_LPA2). */
1266 uint32_t fLpa2 : 1;
1267 /** Supports 64 byte loads and stores without return (FEAT_LS64). */
1268 uint32_t fLs64 : 1;
1269 /** Supports 64 byte stores with return (FEAT_LS64_V). */
1270 uint32_t fLs64V : 1;
1271 /** Supports 64 byte EL0 stores with return (FEAT_LS64_ACCDATA). */
1272 uint32_t fLs64Accdata : 1;
1273 /** Supports MTE Asymmetric Fault Handling (FEAT_MTE3). */
1274 uint32_t fMte3 : 1;
1275 /** Supports SCTLR_ELx.EPAN (FEAT_PAN3). */
1276 uint32_t fPan3 : 1;
1277 /** Supports Armv8.7 PMU extensions (FEAT_PMUv3p7). */
1278 uint32_t fPmuV3p7 : 1;
1279 /** Supports Increased precision of Reciprocal Extimate and Reciprocal Square Root Estimate (FEAT_RPRES). */
1280 uint32_t fRpres : 1;
1281 /** Supports Realm Management Extension (FEAT_RME). */
1282 uint32_t fRme : 1;
1283 /** Supports Full A64 instruction set support in Streaming SVE mode (FEAT_SME_FA64). */
1284 uint32_t fSmeFA64 : 1;
1285 /** Supports Double-precision floating-point outer product instructions (FEAT_SME_F64F64). */
1286 uint32_t fSmeF64F64 : 1;
1287 /** Supports 16-bit to 64-bit integer widening outer product instructions (FEAT_SME_I16I64). */
1288 uint32_t fSmeI16I64 : 1;
1289 /** Supports Statistical Profiling Extensions version 1.2 (FEAT_SPEv1p2). */
1290 uint32_t fSpeV1p2 : 1;
1291 /** Supports AArch64 Extended BFloat16 instructions (FEAT_EBF16). */
1292 uint32_t fEbf16 : 1;
1293 /** Supports WFE and WFI instructions with timeout (FEAT_WFxT). */
1294 uint32_t fWfxt : 1;
1295 /** Supports XS attribute (FEAT_XS). */
1296 uint32_t fXs : 1;
1297 /** Supports branch Record Buffer Extension (FEAT_BRBE). */
1298 uint32_t fBrbe : 1;
1299 /** @} */
1300
1301 /** @name 2021 Architecture Extensions.
1302 * @{ */
1303 /** Supports Control for cache maintenance permission (FEAT_CMOW). */
1304 uint32_t fCmow : 1;
1305 /** Supports PAC algorithm enhancement (FEAT_CONSTPACFIELD). */
1306 uint32_t fConstPacField : 1;
1307 /** Supports Debug v8.8 (FEAT_Debugv8p8). */
1308 uint32_t fDebugV8p8 : 1;
1309 /** Supports Hinted conditional branches (FEAT_HBC). */
1310 uint32_t fHbc : 1;
1311 /** Supports Setting of MDCR_EL2.HPMN to zero (FEAT_HPMN0). */
1312 uint32_t fHpmn0 : 1;
1313 /** Supports Non-Maskable Interrupts (FEAT_NMI). */
1314 uint32_t fNmi : 1;
1315 /** Supports GIC Non-Maskable Interrupts (FEAT_GICv3_NMI). */
1316 uint32_t fGicV3Nmi : 1;
1317 /** Supports Standardization of memory operations (FEAT_MOPS). */
1318 uint32_t fMops : 1;
1319 /** Supports Pointer authentication - QARMA3 algorithm (FEAT_PACQARMA3). */
1320 uint32_t fPacQarma3 : 1;
1321 /** Supports Event counting threshold (FEAT_PMUv3_TH). */
1322 uint32_t fPmuV3Th : 1;
1323 /** Supports Armv8.8 PMU extensions (FEAT_PMUv3p8). */
1324 uint32_t fPmuV3p8 : 1;
1325 /** Supports 64-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT64). */
1326 uint32_t fPmuV3Ext64 : 1;
1327 /** Supports 32-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT32). */
1328 uint32_t fPmuV3Ext32 : 1;
1329 /** Supports External interface to the Performance Monitors (FEAT_PMUv3_EXT). */
1330 uint32_t fPmuV3Ext : 1;
1331 /** Supports Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP). */
1332 uint32_t fRngTrap : 1;
1333 /** Supports Statistical Profiling Extension version 1.3 (FEAT_SPEv1p3). */
1334 uint32_t fSpeV1p3 : 1;
1335 /** Supports EL0 use of IMPLEMENTATION DEFINEd functionality (FEAT_TIDCP1). */
1336 uint32_t fTidcp1 : 1;
1337 /** Supports Branch Record Buffer Extension version 1.1 (FEAT_BRBEv1p1). */
1338 uint32_t fBrbeV1p1 : 1;
1339 /** @} */
1340
1341 /** @name 2022 Architecture Extensions.
1342 * @{ */
1343 /** Supports Address Breakpoint Linking Extenions (FEAT_ABLE). */
1344 uint32_t fAble : 1;
1345 /** Supports Asynchronous Device error exceptions (FEAT_ADERR). */
1346 uint32_t fAderr : 1;
1347 /** Supports Memory Attribute Index Enhancement (FEAT_AIE). */
1348 uint32_t fAie : 1;
1349 /** Supports Asynchronous Normal error exception (FEAT_ANERR). */
1350 uint32_t fAnerr : 1;
1351 /** Supports Breakpoint Mismatch and Range Extension (FEAT_BWE). */
1352 uint32_t fBwe : 1;
1353 /** Supports Clear Branch History instruction (FEAT_CLRBHB). */
1354 uint32_t fClrBhb : 1;
1355 /** Supports Check Feature Status (FEAT_CHK). */
1356 uint32_t fChk : 1;
1357 /** Supports Common Short Sequence Compression instructions (FEAT_CSSC). */
1358 uint32_t fCssc : 1;
1359 /** Supports Cache Speculation Variant 2 version 3 (FEAT_CSV2_3). */
1360 uint32_t fCsv2v3 : 1;
1361 /** Supports 128-bit Translation Tables, 56 bit PA (FEAT_D128). */
1362 uint32_t fD128 : 1;
1363 /** Supports Debug v8.9 (FEAT_Debugv8p9). */
1364 uint32_t fDebugV8p9 : 1;
1365 /** Supports Enhancements to the Double Fault Extension (FEAT_DoubleFault2). */
1366 uint32_t fDoubleFault2 : 1;
1367 /** Supports Exception based Event Profiling (FEAT_EBEP). */
1368 uint32_t fEbep : 1;
1369 /** Supports Exploitative control using branch history information (FEAT_ECBHB). */
1370 uint32_t fEcBhb : 1;
1371 /** Supports for EDHSR (FEAT_EDHSR). */
1372 uint32_t fEdhsr : 1;
1373 /** Supports Embedded Trace Extension version 1.3 (FEAT_ETEv1p3). */
1374 uint32_t fEteV1p3 : 1;
1375 /** Supports Fine-grained traps 2 (FEAT_FGT2). */
1376 uint32_t fFgt2 : 1;
1377 /** Supports Guarded Control Stack Extension (FEAT_GCS). */
1378 uint32_t fGcs : 1;
1379 /** Supports Hardware managed Access Flag for Table descriptors (FEAT_HAFT). */
1380 uint32_t fHaft : 1;
1381 /** Supports Instrumentation Extension (FEAT_ITE). */
1382 uint32_t fIte : 1;
1383 /** Supports Load-Acquire RCpc instructions version 3 (FEAT_LRCPC3). */
1384 uint32_t fLrcpc3 : 1;
1385 /** Supports 128-bit atomics (FEAT_LSE128). */
1386 uint32_t fLse128 : 1;
1387 /** Supports 56-bit VA (FEAT_LVA3). */
1388 uint32_t fLva3 : 1;
1389 /** Supports Memory Encryption Contexts (FEAT_MEC). */
1390 uint32_t fMec : 1;
1391 /** Supports Enhanced Memory Tagging Extension (FEAT_MTE4). */
1392 uint32_t fMte4 : 1;
1393 /** Supports Canoncial Tag checking for untagged memory (FEAT_MTE_CANONCIAL_TAGS). */
1394 uint32_t fMteCanonicalTags : 1;
1395 /** Supports FAR_ELx on a Tag Check Fault (FEAT_MTE_TAGGED_FAR). */
1396 uint32_t fMteTaggedFar : 1;
1397 /** Supports Store only Tag checking (FEAT_MTE_STORE_ONLY). */
1398 uint32_t fMteStoreOnly : 1;
1399 /** Supports Memory tagging with Address tagging disabled (FEAT_MTE_NO_ADDRESS_TAGS). */
1400 uint32_t fMteNoAddressTags : 1;
1401 /** Supports Memory tagging asymmetric faults (FEAT_MTE_ASYM_FAULT). */
1402 uint32_t fMteAsymFault : 1;
1403 /** Supports Memory Tagging asynchronous faulting (FEAT_MTE_ASYNC). */
1404 uint32_t fMteAsync : 1;
1405 /** Supports Allocation tag access permission (FEAT_MTE_PERM_S1). */
1406 uint32_t fMtePermS1 : 1;
1407 /** Supports Armv8.9 PC Sample-based Profiling Extension (FEAT_PCSRv8p9). */
1408 uint32_t fPcsrV8p9 : 1;
1409 /** Supports Permission model enhancements (FEAT_S1PIE). */
1410 uint32_t fS1Pie : 1;
1411 /** Supports Permission model enhancements (FEAT_S2PIE). */
1412 uint32_t fS2Pie : 1;
1413 /** Supports Permission model enhancements (FEAT_S1POE). */
1414 uint32_t fS1Poe : 1;
1415 /** Supports Permission model enhancements (FEAT_S2POE). */
1416 uint32_t fS2Poe : 1;
1417 /** Supports Physical Fault Address Registers (FEAT_PFAR). */
1418 uint32_t fPfar : 1;
1419 /** Supports Armv8.9 PMU extensions (FEAT_PMUv3p9). */
1420 uint32_t fPmuV3p9 : 1;
1421 /** Supports PMU event edge detection (FEAT_PMUv3_EDGE). */
1422 uint32_t fPmuV3Edge : 1;
1423 /** Supports Fixed-function instruction counter (FEAT_PMUv3_ICNTR). */
1424 uint32_t fPmuV3Icntr : 1;
1425 /** Supports PMU Snapshot Extension (FEAT_PMUv3_SS). */
1426 uint32_t fPmuV3Ss : 1;
1427 /** Supports SLC traget for PRFM instructions (FEAT_PRFMSLC). */
1428 uint32_t fPrfmSlc : 1;
1429 /** Supports RAS version 2 (FEAT_RASv2). */
1430 uint32_t fRasV2 : 1;
1431 /** Supports RAS version 2 System Architecture (FEAT_RASSAv2). */
1432 uint32_t fRasSaV2 : 1;
1433 /** Supports for Range Prefetch Memory instruction (FEAT_RPRFM). */
1434 uint32_t fRprfm : 1;
1435 /** Supports extensions to SCTLR_ELx (FEAT_SCTLR2). */
1436 uint32_t fSctlr2 : 1;
1437 /** Supports Synchronous Exception-based Event Profiling (FEAT_SEBEP). */
1438 uint32_t fSebep : 1;
1439 /** Supports non-widening half-precision FP16 to FP16 arithmetic for SME2.1 (FEAT_SME_F16F16). */
1440 uint32_t fSmeF16F16 : 1;
1441 /** Supports Scalable Matrix Extension version 2 (FEAT_SME2). */
1442 uint32_t fSme2 : 1;
1443 /** Supports Scalable Matrix Extension version 2.1 (FEAT_SME2p1). */
1444 uint32_t fSme2p1 : 1;
1445 /** Supports Enhanced speculation restriction instructions (FEAT_SPECRES2). */
1446 uint32_t fSpecres2 : 1;
1447 /** Supports System Performance Monitors Extension (FEAT_SPMU). */
1448 uint32_t fSpmu : 1;
1449 /** Supports Statistical profiling Extension version 1.4 (FEAT_SPEv1p4). */
1450 uint32_t fSpeV1p4 : 1;
1451 /** Supports Call Return Branch Records (FEAT_SPE_CRR). */
1452 uint32_t fSpeCrr : 1;
1453 /** Supports Data Source Filtering (FEAT_SPE_FDS). */
1454 uint32_t fSpeFds : 1;
1455 /** Supports Scalable Vector Extension version SVE2.1 (FEAT_SVE2p1). */
1456 uint32_t fSve2p1 : 1;
1457 /** Supports Non-widening BFloat16 to BFloat16 arithmetic for SVE (FEAT_SVE_B16B16). */
1458 uint32_t fSveB16B16 : 1;
1459 /** Supports 128-bit System instructions (FEAT_SYSINSTR128). */
1460 uint32_t fSysInstr128 : 1;
1461 /** Supports 128-bit System registers (FEAT_SYSREG128). */
1462 uint32_t fSysReg128 : 1;
1463 /** Supports Extension to TCR_ELx (FEAT_TCR2). */
1464 uint32_t fTcr2 : 1;
1465 /** Supports Translation Hardening Extension (FEAT_THE). */
1466 uint32_t fThe : 1;
1467 /** Supports Trace Buffer external mode (FEAT_TRBE_EXT). */
1468 uint32_t fTrbeExt : 1;
1469 /** Supports Trace Buffer MPAM extension (FEAT_TRBE_MPAM). */
1470 uint32_t fTrbeMpam : 1;
1471 /** @} */
1472
1473 /** Padding to the required size to match CPUMFEATURESX86. */
1474 uint32_t auPadding[5];
1475} CPUMFEATURESARMV8;
1476#ifndef VBOX_FOR_DTRACE_LIB
1477AssertCompileSize(CPUMFEATURESARMV8, 64);
1478AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch, CPUMFEATURESARMV8, enmMicroarch);
1479AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor, CPUMFEATURESARMV8, enmCpuVendor);
1480AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth, CPUMFEATURESARMV8, cMaxPhysAddrWidth);
1481AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth, CPUMFEATURESARMV8, cMaxLinearAddrWidth);
1482#endif
1483
1484
1485/**
1486 * Chameleon wrapper structure for the host CPU features.
1487 *
1488 * This is used for the globally readable g_CpumHostFeatures variable, which is
1489 * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
1490 * ring-3. To reflect this immutability after load/init, we use this wrapper
1491 * structure to switch it between const and non-const depending on the context.
1492 * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
1493 */
1494typedef union CPUHOSTFEATURES
1495{
1496 /** Fields common to all CPU types. */
1497 CPUMFEATURESCOMMON Common;
1498 /** The host specific structure. */
1499#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
1500 CPUMFEATURESX86
1501#elif defined(RT_ARCH_ARM64)
1502 CPUMFEATURESARMV8
1503#else
1504# error "port me"
1505#endif
1506#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
1507 const
1508#endif
1509 s;
1510} CPUHOSTFEATURES;
1511#ifndef VBOX_FOR_DTRACE_LIB
1512AssertCompileSize(CPUHOSTFEATURES, 64);
1513#endif
1514/** Pointer to a const host CPU feature structure. */
1515typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
1516
1517/** Host CPU features.
1518 * @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
1519 * module init. */
1520extern CPUHOSTFEATURES g_CpumHostFeatures;
1521
1522
1523/** The target CPU feature structure.
1524 * @todo this should have a chameleon wrapper as well (ring-0). */
1525#ifndef VBOX_VMM_TARGET_ARMV8
1526typedef CPUMFEATURESX86 CPUMFEATURES;
1527#else
1528typedef CPUMFEATURESARMV8 CPUMFEATURES;
1529#endif
1530/** Pointer to a CPU feature structure. */
1531typedef CPUMFEATURES *PCPUMFEATURES;
1532/** Pointer to a const CPU feature structure. */
1533typedef CPUMFEATURES const *PCCPUMFEATURES;
1534
1535
1536/**
1537 * CPUID leaf on x86.
1538 * @note Used by both x86 hosts and guest.
1539 * @todo s/CPUMCPUIDLEAF/CPUMX86CPUIDLEAF/
1540 */
1541typedef struct CPUMCPUIDLEAF
1542{
1543 /** The leaf number. */
1544 uint32_t uLeaf;
1545 /** The sub-leaf number. */
1546 uint32_t uSubLeaf;
1547 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
1548 uint32_t fSubLeafMask;
1549
1550 /** The EAX value. */
1551 uint32_t uEax;
1552 /** The EBX value. */
1553 uint32_t uEbx;
1554 /** The ECX value. */
1555 uint32_t uEcx;
1556 /** The EDX value. */
1557 uint32_t uEdx;
1558
1559 /** Flags. */
1560 uint32_t fFlags;
1561} CPUMCPUIDLEAF;
1562#ifndef VBOX_FOR_DTRACE_LIB
1563AssertCompileSize(CPUMCPUIDLEAF, 32);
1564#endif
1565/** Pointer to a CPUID leaf. */
1566typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
1567/** Pointer to a const CPUID leaf. */
1568typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
1569
1570/** @name CPUMCPUIDLEAF::fFlags
1571 * @{ */
1572/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
1573 * and EDX containing the extended APIC ID. */
1574#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
1575/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
1576#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
1577/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
1578#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
1579/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
1580#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
1581/** Mask of the valid flags. */
1582#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
1583/** @} */
1584
1585
1586/**
1587 * Method used to deal with unknown CPUID leaves on x86.
1588 */
1589typedef enum CPUMUNKNOWNCPUID
1590{
1591 /** Invalid zero value. */
1592 CPUMUNKNOWNCPUID_INVALID = 0,
1593 /** Use given default values (DefCpuId). */
1594 CPUMUNKNOWNCPUID_DEFAULTS,
1595 /** Return the last standard leaf.
1596 * Intel Sandy Bridge has been observed doing this. */
1597 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
1598 /** Return the last standard leaf, with ecx observed.
1599 * Intel Sandy Bridge has been observed doing this. */
1600 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
1601 /** The register values are passed thru unmodified. */
1602 CPUMUNKNOWNCPUID_PASSTHRU,
1603 /** End of valid value. */
1604 CPUMUNKNOWNCPUID_END,
1605 /** Ensure 32-bit type. */
1606 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
1607} CPUMUNKNOWNCPUID;
1608/** Pointer to unknown CPUID leaf method. */
1609typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
1610
1611
1612/**
1613 * The register set returned by an x86 CPUID operation.
1614 */
1615typedef struct CPUMCPUID
1616{
1617 uint32_t uEax;
1618 uint32_t uEbx;
1619 uint32_t uEcx;
1620 uint32_t uEdx;
1621} CPUMCPUID;
1622/** Pointer to a CPUID leaf. */
1623typedef CPUMCPUID *PCPUMCPUID;
1624/** Pointer to a const CPUID leaf. */
1625typedef const CPUMCPUID *PCCPUMCPUID;
1626
1627
1628/**
1629 * ARMv8 CPU ID registers.
1630 */
1631typedef struct CPUMARMV8IDREGS
1632{
1633 /** Content of the ID_AA64PFR0_EL1 register. */
1634 uint64_t u64RegIdAa64Pfr0El1;
1635 /** Content of the ID_AA64PFR1_EL1 register. */
1636 uint64_t u64RegIdAa64Pfr1El1;
1637 /** Content of the ID_AA64DFR0_EL1 register. */
1638 uint64_t u64RegIdAa64Dfr0El1;
1639 /** Content of the ID_AA64DFR1_EL1 register. */
1640 uint64_t u64RegIdAa64Dfr1El1;
1641 /** Content of the ID_AA64AFR0_EL1 register. */
1642 uint64_t u64RegIdAa64Afr0El1;
1643 /** Content of the ID_AA64AFR1_EL1 register. */
1644 uint64_t u64RegIdAa64Afr1El1;
1645 /** Content of the ID_AA64ISAR0_EL1 register. */
1646 uint64_t u64RegIdAa64Isar0El1;
1647 /** Content of the ID_AA64ISAR1_EL1 register. */
1648 uint64_t u64RegIdAa64Isar1El1;
1649 /** Content of the ID_AA64ISAR2_EL1 register. */
1650 uint64_t u64RegIdAa64Isar2El1;
1651 /** Content of the ID_AA64MMFR0_EL1 register. */
1652 uint64_t u64RegIdAa64Mmfr0El1;
1653 /** Content of the ID_AA64MMFR1_EL1 register. */
1654 uint64_t u64RegIdAa64Mmfr1El1;
1655 /** Content of the ID_AA64MMFR2_EL1 register. */
1656 uint64_t u64RegIdAa64Mmfr2El1;
1657 /** Content of the CLIDR_EL1 register. */
1658 uint64_t u64RegClidrEl1;
1659 /** Content of the CTR_EL0 register. */
1660 uint64_t u64RegCtrEl0;
1661 /** Content of the DCZID_EL0 register. */
1662 uint64_t u64RegDczidEl0;
1663 /** @todo we need MIDR_EL1 here, possibly also MPIDR_EL1 and REVIDR_EL1. */
1664} CPUMARMV8IDREGS;
1665/** Pointer to CPU ID registers. */
1666typedef CPUMARMV8IDREGS *PCPUMARMV8IDREGS;
1667/** Pointer to a const CPU ID registers structure. */
1668typedef CPUMARMV8IDREGS const *PCCPUMARMV8IDREGS;
1669
1670
1671/** For identifying the extended database entry type. */
1672typedef enum CPUMDBENTRYTYPE
1673{
1674 CPUMDBENTRYTYPE_INVALID = 0,
1675 CPUMDBENTRYTYPE_X86,
1676 CPUMDBENTRYTYPE_ARM,
1677 CPUMDBENTRYTYPE_END,
1678 CPUMDBENTRYTYPE_32BIT_HACK = 0x7fffffff
1679} CPUMDBENTRYTYPE;
1680
1681/**
1682 * CPU database entry, common parts.
1683 */
1684typedef struct CPUMDBENTRY
1685{
1686 /** The CPU name. */
1687 const char *pszName;
1688 /** The full CPU name. */
1689 const char *pszFullName;
1690 /** The CPU vendor. */
1691 CPUMCPUVENDOR enmVendor;
1692 /** The microarchitecture. */
1693 CPUMMICROARCH enmMicroarch;
1694 /** Flags - CPUMDB_F_XXX. */
1695 uint32_t fFlags;
1696 /** The database entry type. */
1697 CPUMDBENTRYTYPE enmEntryType;
1698} CPUMDBENTRY;
1699/** Pointer to a const CPU database entry. */
1700typedef CPUMDBENTRY const *PCCPUMDBENTRY;
1701
1702/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
1703 * @{ */
1704/** Should execute all in IEM.
1705 * @todo Implement this - currently done in Main... */
1706#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
1707/** @} */
1708
1709
1710/** CPU core type. */
1711typedef enum CPUMCORETYPE
1712{
1713 kCpumCoreType_Invalid = 0,
1714 kCpumCoreType_Efficiency,
1715 kCpumCoreType_Performance,
1716 kCpumCoreType_Unknown,
1717 kCpumCoreType_End,
1718 kCpumCoreType_32BitHack = 0x7fffffff
1719} CPUMCORETYPE;
1720
1721
1722/**
1723 * CPU database entry for x86.
1724 */
1725typedef struct CPUMDBENTRYX86
1726{
1727 CPUMDBENTRY Core;
1728 /** The CPU family. */
1729 uint8_t uFamily;
1730 /** The CPU model. */
1731 uint8_t uModel;
1732 /** The CPU stepping. */
1733 uint8_t uStepping;
1734 /** Scalable bus frequency used for reporting other frequencies. */
1735 uint64_t uScalableBusFreq;
1736 /** The maximum physical address with of the CPU. This should correspond to
1737 * the value in CPUID leaf 0x80000008 when present. */
1738 uint8_t cMaxPhysAddrWidth;
1739 /** The MXCSR mask. */
1740 uint32_t fMxCsrMask;
1741 /** Pointer to an array of CPUID leaves. */
1742 PCCPUMCPUIDLEAF paCpuIdLeaves;
1743 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
1744 uint32_t cCpuIdLeaves;
1745 /** The method used to deal with unknown CPUID leaves. */
1746 CPUMUNKNOWNCPUID enmUnknownCpuId;
1747 /** The default unknown CPUID value. */
1748 CPUMCPUID DefUnknownCpuId;
1749
1750 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
1751 * the RDMSR and WRMSR instructions. */
1752 uint32_t fMsrMask;
1753
1754 /** The number of ranges in the table pointed to b paMsrRanges. */
1755 uint32_t cMsrRanges;
1756 /** MSR ranges for this CPU. */
1757 struct CPUMMSRRANGE const *paMsrRanges;
1758} CPUMDBENTRYX86;
1759/** Pointer to a const X86 CPU database entry. */
1760typedef CPUMDBENTRYX86 const *PCCPUMDBENTRYX86;
1761
1762
1763/**
1764 * CPU database entry for ARM.
1765 */
1766typedef struct CPUMDBENTRYARM
1767{
1768 /** The common parts. */
1769 CPUMDBENTRY Core;
1770
1771 /** System register values common to all the core variations. */
1772 struct SUPARMSYSREGVAL const *paSysRegCmnVals;
1773 /** Number of entries in the table paSysRegCmnVals points to. */
1774 uint32_t cSysRegCmnVals;
1775 /** Number of core variants in aVariants below. */
1776 uint32_t cVariants;
1777
1778 /** CPU core variation details. */
1779 struct
1780 {
1781 /** The name of this CPU core variation. */
1782 const char *pszName;
1783 /** MIDR_EL1 for this CPU core variation. */
1784 union
1785 {
1786 struct
1787 {
1788 /** CPU revision. */
1789 uint32_t u4Revision : 4;
1790 /** Part number. */
1791 uint32_t u12PartNum : 12;
1792 /** ARM architecture indicator. */
1793 uint32_t u4Arch : 4;
1794 /** Implementer specific variant. */
1795 uint32_t u4Variant : 4;
1796 /** The implementer. */
1797 uint32_t u8Implementer : 8;
1798 } s;
1799 uint64_t u64;
1800 } Midr;
1801 /** The CPU core type. */
1802 CPUMCORETYPE enmCoreType;
1803 /** Number of entries in the table paSysRegVals points to. */
1804 uint32_t cSysRegVals;
1805 /** System register values specific to this CPU core variant. */
1806 struct SUPARMSYSREGVAL const *paSysRegVals;
1807 } aVariants[2];
1808} CPUMDBENTRYARM;
1809/** Pointer to a const ARM CPU database entry. */
1810typedef CPUMDBENTRYARM const *PCCPUMDBENTRYARM;
1811
1812
1813/*
1814 * Include the target specific header.
1815 * This uses several of the above types, so it must be postponed till here.
1816 */
1817#ifndef VBOX_VMM_TARGET_ARMV8
1818# include <VBox/vmm/cpum-x86-amd64.h>
1819#else
1820# include <VBox/vmm/cpum-armv8.h>
1821#endif
1822
1823
1824
1825RT_C_DECLS_BEGIN
1826
1827#ifndef VBOX_FOR_DTRACE_LIB
1828
1829VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
1830VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1831VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1832VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1833VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1834
1835/** @name Guest Register Getters.
1836 * @{ */
1837VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1838VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1839VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1840VMMDECL(CPUMARCH) CPUMGetGuestArch(PCVM pVM);
1841VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
1842VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth);
1843/** @} */
1844
1845/** @name Misc Guest Predicate Functions.
1846 * @{ */
1847VMMDECL(bool) CPUMIsGuestIn64BitCode(PCVMCPU pVCpu);
1848/** @} */
1849
1850VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1851VMMDECL(CPUMARCH) CPUMGetHostArch(PCVM pVM);
1852VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
1853
1854VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
1855VMMDECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
1856
1857VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1858#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
1859VMMDECL(int) CPUMCpuIdCollectLeavesFromX86Host(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
1860VMM_INT_DECL(void) CPUMCpuIdApplyX86HostArchCapabilities(PVMCC pVM, bool fHasArchCap, uint64_t fHostArchVal);
1861#endif
1862#if defined(RT_ARCH_ARM64)
1863VMMDECL(int) CPUMCpuIdCollectIdRegistersFromArmV8Host(PCPUMARMV8IDREGS pIdRegs);
1864#endif
1865
1866#ifdef IN_RING3
1867/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1868 * @{
1869 */
1870
1871VMMR3DECL(int) CPUMR3Init(PVM pVM);
1872VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1873VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
1874VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1875VMMR3DECL(int) CPUMR3Term(PVM pVM);
1876VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1877VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1878VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1879
1880VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void);
1881/** Pointer to CPUMR3DbGetEntries. */
1882typedef DECLCALLBACKPTR(uint32_t, PFNCPUMDBGETENTRIES, (void));
1883VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb);
1884/** Pointer to CPUMR3DbGetEntryByIndex. */
1885typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYINDEX, (uint32_t idxCpuDb));
1886VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName);
1887/** Pointer to CPUMR3DbGetEntryByName. */
1888typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYNAME, (const char *pszName));
1889
1890VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
1891VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
1892/** @} */
1893#endif /* IN_RING3 */
1894
1895#endif /* !VBOX_FOR_DTRACE_LIB */
1896/** @} */
1897RT_C_DECLS_END
1898
1899
1900#endif /* !VBOX_INCLUDED_vmm_cpum_h */
1901
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette