VirtualBox

source: vbox/trunk/include/VBox/pgm.h@ 28800

Last change on this file since 28800 was 28800, checked in by vboxsync, 15 years ago

Automated rebranding to Oracle copyright/license strings via filemuncher
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 29.0 KB
Line 
1/** @file
2 * PGM - Page Monitor / Monitor. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pgm_h
27#define ___VBox_pgm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/sup.h>
32#include <VBox/vmapi.h>
33#include <VBox/x86.h>
34#include <VBox/hwacc_vmx.h>
35#include <VBox/VMMDev.h> /* for VMMDEVSHAREDREGIONDESC */
36
37RT_C_DECLS_BEGIN
38
39/** @defgroup grp_pgm The Page Monitor / Manager API
40 * @{
41 */
42
43/** Chunk size for dynamically allocated physical memory. */
44#define PGM_DYNAMIC_CHUNK_SIZE (1*1024*1024)
45/** Shift GC physical address by 20 bits to get the offset into the pvHCChunkHC array. */
46#define PGM_DYNAMIC_CHUNK_SHIFT 20
47/** Dynamic chunk offset mask. */
48#define PGM_DYNAMIC_CHUNK_OFFSET_MASK 0xfffff
49/** Dynamic chunk base mask. */
50#define PGM_DYNAMIC_CHUNK_BASE_MASK (~(RTGCPHYS)PGM_DYNAMIC_CHUNK_OFFSET_MASK)
51
52
53/**
54 * FNPGMRELOCATE callback mode.
55 */
56typedef enum PGMRELOCATECALL
57{
58 /** The callback is for checking if the suggested address is suitable. */
59 PGMRELOCATECALL_SUGGEST = 1,
60 /** The callback is for executing the relocation. */
61 PGMRELOCATECALL_RELOCATE
62} PGMRELOCATECALL;
63
64
65/**
66 * Callback function which will be called when PGM is trying to find
67 * a new location for the mapping.
68 *
69 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
70 * In 1) the callback should say if it objects to a suggested new location. If it
71 * accepts the new location, it is called again for doing it's relocation.
72 *
73 *
74 * @returns true if the location is ok.
75 * @returns false if another location should be found.
76 * @param GCPtrOld The old virtual address.
77 * @param GCPtrNew The new virtual address.
78 * @param enmMode Used to indicate the callback mode.
79 * @param pvUser User argument.
80 * @remark The return value is no a failure indicator, it's an acceptance
81 * indicator. Relocation can not fail!
82 */
83typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
84/** Pointer to a relocation callback function. */
85typedef FNPGMRELOCATE *PFNPGMRELOCATE;
86
87
88/**
89 * Physical page access handler type.
90 */
91typedef enum PGMPHYSHANDLERTYPE
92{
93 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
94 PGMPHYSHANDLERTYPE_MMIO = 1,
95 /** Handler all write access to a physical page range. */
96 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
97 /** Handler all access to a physical page range. */
98 PGMPHYSHANDLERTYPE_PHYSICAL_ALL
99
100} PGMPHYSHANDLERTYPE;
101
102/**
103 * \#PF Handler callback for physical access handler ranges in RC.
104 *
105 * @returns VBox status code (appropriate for RC return).
106 * @param pVM VM Handle.
107 * @param uErrorCode CPU Error code.
108 * @param pRegFrame Trap register frame.
109 * NULL on DMA and other non CPU access.
110 * @param pvFault The fault address (cr2).
111 * @param GCPhysFault The GC physical address corresponding to pvFault.
112 * @param pvUser User argument.
113 */
114typedef DECLCALLBACK(int) FNPGMRCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
115/** Pointer to PGM access callback. */
116typedef FNPGMRCPHYSHANDLER *PFNPGMRCPHYSHANDLER;
117
118/**
119 * \#PF Handler callback for physical access handler ranges in R0.
120 *
121 * @returns VBox status code (appropriate for R0 return).
122 * @param pVM VM Handle.
123 * @param uErrorCode CPU Error code.
124 * @param pRegFrame Trap register frame.
125 * NULL on DMA and other non CPU access.
126 * @param pvFault The fault address (cr2).
127 * @param GCPhysFault The GC physical address corresponding to pvFault.
128 * @param pvUser User argument.
129 */
130typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
131/** Pointer to PGM access callback. */
132typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
133
134/**
135 * Guest Access type
136 */
137typedef enum PGMACCESSTYPE
138{
139 /** Read access. */
140 PGMACCESSTYPE_READ = 1,
141 /** Write access. */
142 PGMACCESSTYPE_WRITE
143} PGMACCESSTYPE;
144
145/**
146 * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
147 *
148 * The handler can not raise any faults, it's mainly for monitoring write access
149 * to certain pages.
150 *
151 * @returns VINF_SUCCESS if the handler have carried out the operation.
152 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
153 * @param pVM VM Handle.
154 * @param GCPhys The physical address the guest is writing to.
155 * @param pvPhys The HC mapping of that address.
156 * @param pvBuf What the guest is reading/writing.
157 * @param cbBuf How much it's reading/writing.
158 * @param enmAccessType The access type.
159 * @param pvUser User argument.
160 */
161typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
162/** Pointer to PGM access callback. */
163typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
164
165
166/**
167 * Virtual access handler type.
168 */
169typedef enum PGMVIRTHANDLERTYPE
170{
171 /** Write access handled. */
172 PGMVIRTHANDLERTYPE_WRITE = 1,
173 /** All access handled. */
174 PGMVIRTHANDLERTYPE_ALL,
175 /** Hypervisor write access handled.
176 * This is used to catch the guest trying to write to LDT, TSS and any other
177 * system structure which the brain dead intel guys let unprivilegde code find. */
178 PGMVIRTHANDLERTYPE_HYPERVISOR
179} PGMVIRTHANDLERTYPE;
180
181/**
182 * \#PF Handler callback for virtual access handler ranges, RC.
183 *
184 * Important to realize that a physical page in a range can have aliases, and
185 * for ALL and WRITE handlers these will also trigger.
186 *
187 * @returns VBox status code (appropriate for GC return).
188 * @param pVM VM Handle.
189 * @param uErrorCode CPU Error code.
190 * @param pRegFrame Trap register frame.
191 * @param pvFault The fault address (cr2).
192 * @param pvRange The base address of the handled virtual range.
193 * @param offRange The offset of the access into this range.
194 * (If it's a EIP range this's the EIP, if not it's pvFault.)
195 */
196typedef DECLCALLBACK(int) FNPGMRCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
197/** Pointer to PGM access callback. */
198typedef FNPGMRCVIRTHANDLER *PFNPGMRCVIRTHANDLER;
199
200/**
201 * \#PF Handler callback for virtual access handler ranges, R3.
202 *
203 * Important to realize that a physical page in a range can have aliases, and
204 * for ALL and WRITE handlers these will also trigger.
205 *
206 * @returns VINF_SUCCESS if the handler have carried out the operation.
207 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
208 * @param pVM VM Handle.
209 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
210 * @param pvPtr The HC mapping of that address.
211 * @param pvBuf What the guest is reading/writing.
212 * @param cbBuf How much it's reading/writing.
213 * @param enmAccessType The access type.
214 * @param pvUser User argument.
215 */
216typedef DECLCALLBACK(int) FNPGMR3VIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
217/** Pointer to PGM access callback. */
218typedef FNPGMR3VIRTHANDLER *PFNPGMR3VIRTHANDLER;
219
220
221/**
222 * \#PF Handler callback for invalidation of virtual access handler ranges.
223 *
224 * @param pVM VM Handle.
225 * @param GCPtr The virtual address the guest has changed.
226 */
227typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
228/** Pointer to PGM invalidation callback. */
229typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
230
231/**
232 * Paging mode.
233 */
234typedef enum PGMMODE
235{
236 /** The usual invalid value. */
237 PGMMODE_INVALID = 0,
238 /** Real mode. */
239 PGMMODE_REAL,
240 /** Protected mode, no paging. */
241 PGMMODE_PROTECTED,
242 /** 32-bit paging. */
243 PGMMODE_32_BIT,
244 /** PAE paging. */
245 PGMMODE_PAE,
246 /** PAE paging with NX enabled. */
247 PGMMODE_PAE_NX,
248 /** 64-bit AMD paging (long mode). */
249 PGMMODE_AMD64,
250 /** 64-bit AMD paging (long mode) with NX enabled. */
251 PGMMODE_AMD64_NX,
252 /** Nested paging mode (shadow only; guest physical to host physical). */
253 PGMMODE_NESTED,
254 /** Extended paging (Intel) mode. */
255 PGMMODE_EPT,
256 /** The max number of modes */
257 PGMMODE_MAX,
258 /** 32bit hackishness. */
259 PGMMODE_32BIT_HACK = 0x7fffffff
260} PGMMODE;
261
262/** Macro for checking if the guest is using paging.
263 * @param enmMode PGMMODE_*.
264 * @remark ASSUMES certain order of the PGMMODE_* values.
265 */
266#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
267
268/** Macro for checking if it's one of the long mode modes.
269 * @param enmMode PGMMODE_*.
270 */
271#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX || (enmMode) == PGMMODE_AMD64)
272
273/**
274 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
275 *
276 * @returns boolean.
277 * @param enmProt The PGMROMPROT value, must be valid.
278 */
279#define PGMROMPROT_IS_ROM(enmProt) \
280 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
281 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
282
283
284
285VMMDECL(bool) PGMIsLocked(PVM pVM);
286VMMDECL(bool) PGMIsLockOwner(PVM pVM);
287
288VMMDECL(int) PGMRegisterStringFormatTypes(void);
289VMMDECL(void) PGMDeregisterStringFormatTypes(void);
290VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
291VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
292VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
293VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
294VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
295VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
296VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
297VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
298VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
299VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
300VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
301VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
302VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
303VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
304VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
305#ifndef IN_RING0
306VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
307#endif
308#ifdef VBOX_STRICT
309VMMDECL(void) PGMMapCheck(PVM pVM);
310#endif
311VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
312VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
313VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
314VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
315VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
316VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
317VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
318VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdPt);
319
320VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
321VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
322VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
323VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
324VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
325VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
326VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
327VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
328VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
329VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
330VMMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
331 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
332 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
333 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
334 R3PTRTYPE(const char *) pszDesc);
335VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
336VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
337VMMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
338 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
339 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
340 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
341 R3PTRTYPE(const char *) pszDesc);
342VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
343VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
344VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
345VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
346VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
347VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
348VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
349VMMDECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
350VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
351VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
352VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
353VMMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
354VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
355VMMDECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
356VMMDECL(void) PGMPhysInvalidatePageMapTLB(PVM pVM);
357VMMDECL(void) PGMPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
358VMMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
359VMMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
360VMMDECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
361VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
362VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
363VMMDECL(int) PGMPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTR3PTR pR3Ptr);
364#ifdef VBOX_STRICT
365VMMDECL(RTR3PTR) PGMPhysGCPhys2R3PtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
366#endif
367VMMDECL(int) PGMPhysGCPtr2R3Ptr(PVMCPU pVCpu, RTGCPTR GCPtr, PRTR3PTR pR3Ptr);
368VMMDECL(int) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
369VMMDECL(int) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
370VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
371VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
372VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
373VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
374VMMDECL(int) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
375VMMDECL(int) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
376VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
377VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
378VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
379VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
380#ifdef VBOX_STRICT
381VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
382VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
383VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
384#endif /* VBOX_STRICT */
385
386#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
387VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
388VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv);
389# ifdef IN_RC
390VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
391VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage);
392VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage);
393# ifdef VBOX_STRICT
394VMMDECL(void) PGMDynCheckLocks(PVM pVM);
395# endif
396# endif
397VMMDECL(void) PGMDynMapStartAutoSet(PVMCPU pVCpu);
398VMMDECL(bool) PGMDynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
399VMMDECL(void) PGMDynMapReleaseAutoSet(PVMCPU pVCpu);
400VMMDECL(void) PGMDynMapFlushAutoSet(PVMCPU pVCpu);
401VMMDECL(void) PGMDynMapMigrateAutoSet(PVMCPU pVCpu);
402VMMDECL(uint32_t) PGMDynMapPushAutoSubset(PVMCPU pVCpu);
403VMMDECL(void) PGMDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
404#endif
405
406
407VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
408
409/**
410 * Query large page usage state
411 *
412 * @returns 0 - disabled, 1 - enabled
413 * @param pVM The VM to operate on.
414 */
415#define PGMIsUsingLargePages(pVM) (pVM->fUseLargePages)
416
417
418#ifdef IN_RC
419/** @defgroup grp_pgm_gc The PGM Guest Context API
420 * @ingroup grp_pgm
421 * @{
422 */
423/** @} */
424#endif /* IN_RC */
425
426
427#ifdef IN_RING0
428/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
429 * @ingroup grp_pgm
430 * @{
431 */
432VMMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
433VMMR0DECL(int) PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu);
434VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
435# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
436VMMR0DECL(int) PGMR0DynMapInit(void);
437VMMR0DECL(void) PGMR0DynMapTerm(void);
438VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
439VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
440VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
441# endif
442/** @} */
443#endif /* IN_RING0 */
444
445
446
447#ifdef IN_RING3
448/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
449 * @ingroup grp_pgm
450 * @{
451 */
452VMMR3DECL(int) PGMR3Init(PVM pVM);
453VMMR3DECL(int) PGMR3InitCPU(PVM pVM);
454VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
455VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
456VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
457VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
458VMMR3DECL(void) PGMR3Reset(PVM pVM);
459VMMR3DECL(int) PGMR3Term(PVM pVM);
460VMMR3DECL(int) PGMR3TermCPU(PVM pVM);
461VMMR3DECL(int) PGMR3LockCall(PVM pVM);
462VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
463
464VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
465VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
466VMMR3DECL(int) PGMR3QueryVMMMemoryStats(PVM pVM, uint64_t *puTotalAllocSize, uint64_t *puTotalFreeSize, uint64_t *puTotalBalloonSize);
467VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
468 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
469 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
470 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
471 R3PTRTYPE(const char *) pszDesc);
472VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
473VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
474VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
475VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
476VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
477VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
478VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
479VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
480
481/** @name PGMR3PhysRegisterRom flags.
482 * @{ */
483/** Inidicates that ROM shadowing should be enabled. */
484#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
485/** Indicates that what pvBinary points to won't go away
486 * and can be used for strictness checks. */
487#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
488/** @} */
489
490VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
491 const void *pvBinary, uint32_t fFlags, const char *pszDesc);
492VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
493VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
494VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
495/** @name PGMR3MapPT flags.
496 * @{ */
497/** The mapping may be unmapped later. The default is permanent mappings. */
498#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
499/** @} */
500VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
501VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
502VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
503VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM);
504VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
505VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
506VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
507VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
508VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
509VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
510
511VMMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
512 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
513 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
514 const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
515VMMDECL(int) PGMR3HandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
516 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
517 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
518 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
519 R3PTRTYPE(const char *) pszDesc);
520VMMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
521 PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
522 PFNPGMR3VIRTHANDLER pfnHandlerR3,
523 const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
524VMMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
525VMMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
526VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
527#ifdef ___VBox_dbgf_h /** @todo fix this! */
528VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
529#endif
530VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
531
532VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
533VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
534VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
535VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
536VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
537VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
538VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
539VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
540VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
541VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
542VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, const char *pszWho);
543VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
544VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
545VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
546VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
547VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
548VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
549
550VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM);
551
552VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
553
554VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
555VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
556VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
557VMMR3DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
558VMMR3DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
559VMMR3DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
560VMMR3DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
561VMMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
562VMMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
563
564
565/** @name Page sharing
566 * @{ */
567VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, char *pszModuleName, char *pszVersion, RTGCPTR GCBaseAddr, uint32_t cbModule, unsigned cRegions, VMMDEVSHAREDREGIONDESC *pRegions);
568VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char *pszModuleName, char *pszVersion, RTGCPTR GCBaseAddr, uint32_t cbModule);
569VMMR3DECL(int) PGMR3SharedModuleCheck(PVM pVM);
570/** @} */
571
572/** @} */
573#endif /* IN_RING3 */
574
575RT_C_DECLS_END
576
577/** @} */
578#endif
579
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette