[88153] | 1 | /** @file
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| 2 | * IOMMU - Input/Output Memory Management Unit (Intel).
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| 3 | */
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| 4 |
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| 5 | /*
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[98103] | 6 | * Copyright (C) 2021-2023 Oracle and/or its affiliates.
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[88153] | 7 | *
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[96407] | 8 | * This file is part of VirtualBox base platform packages, as
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| 9 | * available from https://www.virtualbox.org.
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[88153] | 10 | *
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[96407] | 11 | * This program is free software; you can redistribute it and/or
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| 12 | * modify it under the terms of the GNU General Public License
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| 13 | * as published by the Free Software Foundation, in version 3 of the
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| 14 | * License.
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| 15 | *
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| 16 | * This program is distributed in the hope that it will be useful, but
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 19 | * General Public License for more details.
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| 20 | *
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| 21 | * You should have received a copy of the GNU General Public License
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| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 23 | *
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[88153] | 24 | * The contents of this file may alternatively be used under the terms
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| 25 | * of the Common Development and Distribution License Version 1.0
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[96407] | 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 27 | * in the VirtualBox distribution, in which case the provisions of the
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[88153] | 28 | * CDDL are applicable instead of those of the GPL.
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| 29 | *
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| 30 | * You may elect to license modified versions of this file under the
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| 31 | * terms and conditions of either the GPL or the CDDL or both.
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[96407] | 32 | *
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| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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[88153] | 34 | */
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| 35 |
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| 36 | #ifndef VBOX_INCLUDED_iommu_intel_h
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| 37 | #define VBOX_INCLUDED_iommu_intel_h
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| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 39 | # pragma once
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| 40 | #endif
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| 41 |
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[88202] | 42 | #include <iprt/assertcompile.h>
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[88153] | 43 | #include <iprt/types.h>
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| 44 |
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| 45 |
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| 46 | /**
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| 47 | * @name MMIO register offsets.
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[88265] | 48 | * In accordance with the Intel spec.
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[88153] | 49 | * @{
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| 50 | */
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[88257] | 51 | #define VTD_MMIO_OFF_VER_REG 0x000 /**< Version. */
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[88192] | 52 | #define VTD_MMIO_OFF_CAP_REG 0x008 /**< Capability. */
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| 53 | #define VTD_MMIO_OFF_ECAP_REG 0x010 /**< Extended Capability. */
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| 54 | #define VTD_MMIO_OFF_GCMD_REG 0x018 /**< Global Command. */
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| 55 | #define VTD_MMIO_OFF_GSTS_REG 0x01c /**< Global Status. */
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| 56 | #define VTD_MMIO_OFF_RTADDR_REG 0x020 /**< Root Table Address. */
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| 57 | #define VTD_MMIO_OFF_CCMD_REG 0x028 /**< Context Command. */
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[88153] | 58 |
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[88192] | 59 | #define VTD_MMIO_OFF_FSTS_REG 0x034 /**< Fault Status.*/
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| 60 | #define VTD_MMIO_OFF_FECTL_REG 0x038 /**< Fault Event Control.*/
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| 61 | #define VTD_MMIO_OFF_FEDATA_REG 0x03c /**< Fault Event Data. */
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| 62 | #define VTD_MMIO_OFF_FEADDR_REG 0x040 /**< Fault Event Address. */
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| 63 | #define VTD_MMIO_OFF_FEUADDR_REG 0x044 /**< Fault Event Upper Address. */
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[88153] | 64 |
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[88192] | 65 | #define VTD_MMIO_OFF_AFLOG_REG 0x058 /**< Advance Fault Log. */
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[88153] | 66 |
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[88192] | 67 | #define VTD_MMIO_OFF_PMEN_REG 0x064 /**< Protected Memory Enable (PMEN). */
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| 68 | #define VTD_MMIO_OFF_PLMBASE_REG 0x068 /**< Protected Low Memory Base. */
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| 69 | #define VTD_MMIO_OFF_PLMLIMIT_REG 0x06c /**< Protected Low Memory Limit. */
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| 70 | #define VTD_MMIO_OFF_PHMBASE_REG 0x070 /**< Protected High Memory Base. */
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| 71 | #define VTD_MMIO_OFF_PHMLIMIT_REG 0x078 /**< Protected High Memory Limit. */
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[88153] | 72 |
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[88192] | 73 | #define VTD_MMIO_OFF_IQH_REG 0x080 /**< Invalidation Queue Head. */
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| 74 | #define VTD_MMIO_OFF_IQT_REG 0x088 /**< Invalidation Queue Tail. */
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| 75 | #define VTD_MMIO_OFF_IQA_REG 0x090 /**< Invalidation Queue Address. */
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| 76 | #define VTD_MMIO_OFF_ICS_REG 0x09c /**< Invalidation Completion Status. */
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| 77 | #define VTD_MMIO_OFF_IECTL_REG 0x0a0 /**< Invalidation Completion Event Control. */
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| 78 | #define VTD_MMIO_OFF_IEDATA_REG 0x0a4 /**< Invalidation Completion Event Data. */
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| 79 | #define VTD_MMIO_OFF_IEADDR_REG 0x0a8 /**< Invalidation Completion Event Address. */
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| 80 | #define VTD_MMIO_OFF_IEUADDR_REG 0x0ac /**< Invalidation Completion Event Upper Address. */
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| 81 | #define VTD_MMIO_OFF_IQERCD_REG 0x0b0 /**< Invalidation Queue Error Record. */
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[88153] | 82 |
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[88192] | 83 | #define VTD_MMIO_OFF_IRTA_REG 0x0b8 /**< Interrupt Remapping Table Address. */
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[88153] | 84 |
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[88192] | 85 | #define VTD_MMIO_OFF_PQH_REG 0x0c0 /**< Page Request Queue Head. */
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| 86 | #define VTD_MMIO_OFF_PQT_REG 0x0c8 /**< Page Request Queue Tail. */
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| 87 | #define VTD_MMIO_OFF_PQA_REG 0x0d0 /**< Page Request Queue Address. */
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| 88 | #define VTD_MMIO_OFF_PRS_REG 0x0dc /**< Page Request Status. */
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| 89 | #define VTD_MMIO_OFF_PECTL_REG 0x0e0 /**< Page Request Event Control. */
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| 90 | #define VTD_MMIO_OFF_PEDATA_REG 0x0e4 /**< Page Request Event Data. */
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| 91 | #define VTD_MMIO_OFF_PEADDR_REG 0x0e8 /**< Page Request Event Address. */
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| 92 | #define VTD_MMIO_OFF_PEUADDR_REG 0x0ec /**< Page Request Event Upper Address. */
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[88153] | 93 |
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[88192] | 94 | #define VTD_MMIO_OFF_MTRRCAP_REG 0x100 /**< MTRR Capabliity. */
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| 95 | #define VTD_MMIO_OFF_MTRRDEF_REG 0x108 /**< MTRR Default Type. */
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[88153] | 96 |
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[88192] | 97 | #define VTD_MMIO_OFF_MTRR_FIX64_00000_REG 0x120 /**< Fixed-range MTRR Register for 64K at 00000. */
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| 98 | #define VTD_MMIO_OFF_MTRR_FIX16K_80000_REG 0x128 /**< Fixed-range MTRR Register for 16K at 80000. */
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| 99 | #define VTD_MMIO_OFF_MTRR_FIX16K_A0000_REG 0x130 /**< Fixed-range MTRR Register for 16K at a0000. */
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| 100 | #define VTD_MMIO_OFF_MTRR_FIX4K_C0000_REG 0x138 /**< Fixed-range MTRR Register for 4K at c0000. */
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| 101 | #define VTD_MMIO_OFF_MTRR_FIX4K_C8000_REG 0x140 /**< Fixed-range MTRR Register for 4K at c8000. */
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| 102 | #define VTD_MMIO_OFF_MTRR_FIX4K_D0000_REG 0x148 /**< Fixed-range MTRR Register for 4K at d0000. */
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| 103 | #define VTD_MMIO_OFF_MTRR_FIX4K_D8000_REG 0x150 /**< Fixed-range MTRR Register for 4K at d8000. */
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| 104 | #define VTD_MMIO_OFF_MTRR_FIX4K_E0000_REG 0x158 /**< Fixed-range MTRR Register for 4K at e0000. */
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| 105 | #define VTD_MMIO_OFF_MTRR_FIX4K_E8000_REG 0x160 /**< Fixed-range MTRR Register for 4K at e8000. */
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| 106 | #define VTD_MMIO_OFF_MTRR_FIX4K_F0000_REG 0x168 /**< Fixed-range MTRR Register for 4K at f0000. */
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| 107 | #define VTD_MMIO_OFF_MTRR_FIX4K_F8000_REG 0x170 /**< Fixed-range MTRR Register for 4K at f8000. */
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[88153] | 108 |
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[88192] | 109 | #define VTD_MMIO_OFF_MTRR_PHYSBASE0_REG 0x180 /**< Variable-range MTRR Base 0. */
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| 110 | #define VTD_MMIO_OFF_MTRR_PHYSMASK0_REG 0x188 /**< Variable-range MTRR Mask 0. */
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| 111 | #define VTD_MMIO_OFF_MTRR_PHYSBASE1_REG 0x190 /**< Variable-range MTRR Base 1. */
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| 112 | #define VTD_MMIO_OFF_MTRR_PHYSMASK1_REG 0x198 /**< Variable-range MTRR Mask 1. */
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| 113 | #define VTD_MMIO_OFF_MTRR_PHYSBASE2_REG 0x1a0 /**< Variable-range MTRR Base 2. */
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| 114 | #define VTD_MMIO_OFF_MTRR_PHYSMASK2_REG 0x1a8 /**< Variable-range MTRR Mask 2. */
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| 115 | #define VTD_MMIO_OFF_MTRR_PHYSBASE3_REG 0x1b0 /**< Variable-range MTRR Base 3. */
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| 116 | #define VTD_MMIO_OFF_MTRR_PHYSMASK3_REG 0x1b8 /**< Variable-range MTRR Mask 3. */
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| 117 | #define VTD_MMIO_OFF_MTRR_PHYSBASE4_REG 0x1c0 /**< Variable-range MTRR Base 4. */
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| 118 | #define VTD_MMIO_OFF_MTRR_PHYSMASK4_REG 0x1c8 /**< Variable-range MTRR Mask 4. */
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| 119 | #define VTD_MMIO_OFF_MTRR_PHYSBASE5_REG 0x1d0 /**< Variable-range MTRR Base 5. */
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| 120 | #define VTD_MMIO_OFF_MTRR_PHYSMASK5_REG 0x1d8 /**< Variable-range MTRR Mask 5. */
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| 121 | #define VTD_MMIO_OFF_MTRR_PHYSBASE6_REG 0x1e0 /**< Variable-range MTRR Base 6. */
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| 122 | #define VTD_MMIO_OFF_MTRR_PHYSMASK6_REG 0x1e8 /**< Variable-range MTRR Mask 6. */
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| 123 | #define VTD_MMIO_OFF_MTRR_PHYSBASE7_REG 0x1f0 /**< Variable-range MTRR Base 7. */
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| 124 | #define VTD_MMIO_OFF_MTRR_PHYSMASK7_REG 0x1f8 /**< Variable-range MTRR Mask 7. */
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| 125 | #define VTD_MMIO_OFF_MTRR_PHYSBASE8_REG 0x200 /**< Variable-range MTRR Base 8. */
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| 126 | #define VTD_MMIO_OFF_MTRR_PHYSMASK8_REG 0x208 /**< Variable-range MTRR Mask 8. */
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| 127 | #define VTD_MMIO_OFF_MTRR_PHYSBASE9_REG 0x210 /**< Variable-range MTRR Base 9. */
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| 128 | #define VTD_MMIO_OFF_MTRR_PHYSMASK9_REG 0x218 /**< Variable-range MTRR Mask 9. */
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[88153] | 129 |
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[88257] | 130 | #define VTD_MMIO_OFF_VCCAP_REG 0xe00 /**< Virtual Command Capability. */
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[88192] | 131 | #define VTD_MMIO_OFF_VCMD_REG 0xe10 /**< Virtual Command. */
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[88257] | 132 | #define VTD_MMIO_OFF_VCMDRSVD_REG 0xe18 /**< Reserved for future for Virtual Command. */
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[88192] | 133 | #define VTD_MMIO_OFF_VCRSP_REG 0xe20 /**< Virtual Command Response. */
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[88257] | 134 | #define VTD_MMIO_OFF_VCRSPRSVD_REG 0xe28 /**< Reserved for future for Virtual Command Response. */
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[88153] | 135 | /** @} */
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| 136 |
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| 137 |
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| 138 | /** @name Root Entry.
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| 139 | * In accordance with the Intel spec.
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| 140 | * @{ */
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| 141 | /** P: Present. */
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| 142 | #define VTD_BF_0_ROOT_ENTRY_P_SHIFT 0
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| 143 | #define VTD_BF_0_ROOT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
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| 144 | /** R: Reserved (bits 11:1). */
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| 145 | #define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_SHIFT 1
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| 146 | #define VTD_BF_0_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
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| 147 | /** CTP: Context-Table Pointer. */
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| 148 | #define VTD_BF_0_ROOT_ENTRY_CTP_SHIFT 12
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| 149 | #define VTD_BF_0_ROOT_ENTRY_CTP_MASK UINT64_C(0xfffffffffffff000)
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| 150 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
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| 151 | (P, RSVD_11_1, CTP));
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| 152 |
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| 153 | /** Root Entry. */
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| 154 | typedef struct VTD_ROOT_ENTRY_T
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| 155 | {
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| 156 | /** The qwords in the root entry. */
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| 157 | uint64_t au64[2];
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| 158 | } VTD_ROOT_ENTRY_T;
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| 159 | /** Pointer to a root entry. */
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| 160 | typedef VTD_ROOT_ENTRY_T *PVTD_ROOT_ENTRY_T;
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| 161 | /** Pointer to a const root entry. */
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| 162 | typedef VTD_ROOT_ENTRY_T const *PCVTD_ROOT_ENTRY_T;
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[89245] | 163 |
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| 164 | /* Root Entry: Qword 0 valid mask. */
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| 165 | #define VTD_ROOT_ENTRY_0_VALID_MASK (VTD_BF_0_ROOT_ENTRY_P_MASK | VTD_BF_0_ROOT_ENTRY_CTP_MASK)
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| 166 | /* Root Entry: Qword 1 valid mask. */
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| 167 | #define VTD_ROOT_ENTRY_1_VALID_MASK UINT64_C(0)
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[88153] | 168 | /** @} */
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| 169 |
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| 170 |
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| 171 | /** @name Scalable-mode Root Entry.
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| 172 | * In accordance with the Intel spec.
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| 173 | * @{ */
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| 174 | /** LP: Lower Present. */
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| 175 | #define VTD_BF_0_SM_ROOT_ENTRY_LP_SHIFT 0
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| 176 | #define VTD_BF_0_SM_ROOT_ENTRY_LP_MASK UINT64_C(0x0000000000000001)
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| 177 | /** R: Reserved (bits 11:1). */
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| 178 | #define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
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| 179 | #define VTD_BF_0_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
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| 180 | /** LCTP: Lower Context-Table Pointer */
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| 181 | #define VTD_BF_0_SM_ROOT_ENTRY_LCTP_SHIFT 12
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| 182 | #define VTD_BF_0_SM_ROOT_ENTRY_LCTP_MASK UINT64_C(0xfffffffffffff000)
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| 183 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
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| 184 | (LP, RSVD_11_1, LCTP));
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| 185 |
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| 186 | /** UP: Upper Present. */
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| 187 | #define VTD_BF_1_SM_ROOT_ENTRY_UP_SHIFT 0
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| 188 | #define VTD_BF_1_SM_ROOT_ENTRY_UP_MASK UINT64_C(0x0000000000000001)
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| 189 | /** R: Reserved (bits 11:1). */
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| 190 | #define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_SHIFT 1
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| 191 | #define VTD_BF_1_SM_ROOT_ENTRY_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
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| 192 | /** UCTP: Upper Context-Table Pointer. */
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| 193 | #define VTD_BF_1_SM_ROOT_ENTRY_UCTP_SHIFT 12
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| 194 | #define VTD_BF_1_SM_ROOT_ENTRY_UCTP_MASK UINT64_C(0xfffffffffffff000)
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| 195 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_ROOT_ENTRY_, UINT64_C(0), UINT64_MAX,
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| 196 | (UP, RSVD_11_1, UCTP));
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| 197 |
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| 198 | /** Scalable-mode root entry. */
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| 199 | typedef struct VTD_SM_ROOT_ENTRY_T
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| 200 | {
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| 201 | /** The lower scalable-mode root entry. */
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| 202 | uint64_t uLower;
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| 203 | /** The upper scalable-mode root entry. */
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| 204 | uint64_t uUpper;
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| 205 | } VTD_SM_ROOT_ENTRY_T;
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| 206 | /** Pointer to a scalable-mode root entry. */
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| 207 | typedef VTD_SM_ROOT_ENTRY_T *PVTD_SM_ROOT_ENTRY_T;
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| 208 | /** Pointer to a const scalable-mode root entry. */
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| 209 | typedef VTD_SM_ROOT_ENTRY_T const *PCVTD_SM_ROOT_ENTRY_T;
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| 210 | /** @} */
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| 211 |
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| 212 |
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| 213 | /** @name Context Entry.
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| 214 | * In accordance with the Intel spec.
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| 215 | * @{ */
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| 216 | /** P: Present. */
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| 217 | #define VTD_BF_0_CONTEXT_ENTRY_P_SHIFT 0
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| 218 | #define VTD_BF_0_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
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| 219 | /** FPD: Fault Processing Disable. */
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| 220 | #define VTD_BF_0_CONTEXT_ENTRY_FPD_SHIFT 1
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| 221 | #define VTD_BF_0_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
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| 222 | /** TT: Translation Type. */
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| 223 | #define VTD_BF_0_CONTEXT_ENTRY_TT_SHIFT 2
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| 224 | #define VTD_BF_0_CONTEXT_ENTRY_TT_MASK UINT64_C(0x000000000000000c)
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| 225 | /** R: Reserved (bits 11:4). */
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| 226 | #define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_SHIFT 4
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| 227 | #define VTD_BF_0_CONTEXT_ENTRY_RSVD_11_4_MASK UINT64_C(0x0000000000000ff0)
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| 228 | /** SLPTPTR: Second Level Page Translation Pointer. */
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| 229 | #define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_SHIFT 12
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| 230 | #define VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
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| 231 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
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| 232 | (P, FPD, TT, RSVD_11_4, SLPTPTR));
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| 233 |
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| 234 | /** AW: Address Width. */
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| 235 | #define VTD_BF_1_CONTEXT_ENTRY_AW_SHIFT 0
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| 236 | #define VTD_BF_1_CONTEXT_ENTRY_AW_MASK UINT64_C(0x0000000000000007)
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| 237 | /** IGN: Ignored (bits 6:3). */
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| 238 | #define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_SHIFT 3
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| 239 | #define VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK UINT64_C(0x0000000000000078)
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| 240 | /** R: Reserved (bit 7). */
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| 241 | #define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_SHIFT 7
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| 242 | #define VTD_BF_1_CONTEXT_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
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| 243 | /** DID: Domain Identifier. */
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| 244 | #define VTD_BF_1_CONTEXT_ENTRY_DID_SHIFT 8
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| 245 | #define VTD_BF_1_CONTEXT_ENTRY_DID_MASK UINT64_C(0x0000000000ffff00)
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| 246 | /** R: Reserved (bits 63:24). */
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| 247 | #define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_SHIFT 24
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| 248 | #define VTD_BF_1_CONTEXT_ENTRY_RSVD_63_24_MASK UINT64_C(0xffffffffff000000)
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| 249 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
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| 250 | (AW, IGN_6_3, RSVD_7, DID, RSVD_63_24));
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| 251 |
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| 252 | /** Context Entry. */
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| 253 | typedef struct VTD_CONTEXT_ENTRY_T
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| 254 | {
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| 255 | /** The qwords in the context entry. */
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| 256 | uint64_t au64[2];
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| 257 | } VTD_CONTEXT_ENTRY_T;
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| 258 | /** Pointer to a context entry. */
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| 259 | typedef VTD_CONTEXT_ENTRY_T *PVTD_CONTEXT_ENTRY_T;
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| 260 | /** Pointer to a const context entry. */
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| 261 | typedef VTD_CONTEXT_ENTRY_T const *PCVTD_CONTEXT_ENTRY_T;
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[89552] | 262 | AssertCompileSize(VTD_CONTEXT_ENTRY_T, 16);
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[89256] | 263 |
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[89365] | 264 | /** Context Entry: Qword 0 valid mask. */
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[89256] | 265 | #define VTD_CONTEXT_ENTRY_0_VALID_MASK ( VTD_BF_0_CONTEXT_ENTRY_P_MASK \
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| 266 | | VTD_BF_0_CONTEXT_ENTRY_FPD_MASK \
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| 267 | | VTD_BF_0_CONTEXT_ENTRY_TT_MASK \
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| 268 | | VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK)
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[89365] | 269 | /** Context Entry: Qword 1 valid mask. */
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[89256] | 270 | #define VTD_CONTEXT_ENTRY_1_VALID_MASK ( VTD_BF_1_CONTEXT_ENTRY_AW_MASK \
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| 271 | | VTD_BF_1_CONTEXT_ENTRY_IGN_6_3_MASK \
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| 272 | | VTD_BF_1_CONTEXT_ENTRY_DID_MASK)
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[89365] | 273 |
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| 274 | /** Translation Type: Untranslated requests uses second-level paging. */
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| 275 | #define VTD_TT_UNTRANSLATED_SLP 0
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| 276 | /** Translation Type: Untranslated requests requires device-TLB support. */
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| 277 | #define VTD_TT_UNTRANSLATED_DEV_TLB 1
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| 278 | /** Translation Type: Untranslated requests are pass-through. */
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| 279 | #define VTD_TT_UNTRANSLATED_PT 2
|
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| 280 | /** Translation Type: Reserved. */
|
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| 281 | #define VTD_TT_RSVD 3
|
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[88153] | 282 | /** @} */
|
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| 283 |
|
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| 284 |
|
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| 285 | /** @name Scalable-mode Context Entry.
|
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| 286 | * In accordance with the Intel spec.
|
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| 287 | * @{ */
|
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| 288 | /** P: Present. */
|
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| 289 | #define VTD_BF_0_SM_CONTEXT_ENTRY_P_SHIFT 0
|
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| 290 | #define VTD_BF_0_SM_CONTEXT_ENTRY_P_MASK UINT64_C(0x0000000000000001)
|
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| 291 | /** FPD: Fault Processing Disable. */
|
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| 292 | #define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_SHIFT 1
|
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| 293 | #define VTD_BF_0_SM_CONTEXT_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
|
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| 294 | /** DTE: Device-TLB Enable. */
|
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| 295 | #define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_SHIFT 2
|
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| 296 | #define VTD_BF_0_SM_CONTEXT_ENTRY_DTE_MASK UINT64_C(0x0000000000000004)
|
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| 297 | /** PASIDE: PASID Enable. */
|
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| 298 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_SHIFT 3
|
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| 299 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDE_MASK UINT64_C(0x0000000000000008)
|
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| 300 | /** PRE: Page Request Enable. */
|
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| 301 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_SHIFT 4
|
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| 302 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PRE_MASK UINT64_C(0x0000000000000010)
|
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| 303 | /** R: Reserved (bits 8:5). */
|
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| 304 | #define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_SHIFT 5
|
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| 305 | #define VTD_BF_0_SM_CONTEXT_ENTRY_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
|
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| 306 | /** PDTS: PASID Directory Size. */
|
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| 307 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_SHIFT 9
|
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| 308 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PDTS_MASK UINT64_C(0x0000000000000e00)
|
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| 309 | /** PASIDDIRPTR: PASID Directory Pointer. */
|
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| 310 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_SHIFT 12
|
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| 311 | #define VTD_BF_0_SM_CONTEXT_ENTRY_PASIDDIRPTR_MASK UINT64_C(0xfffffffffffff000)
|
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| 312 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
|
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| 313 | (P, FPD, DTE, PASIDE, PRE, RSVD_8_5, PDTS, PASIDDIRPTR));
|
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| 314 |
|
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| 315 | /** RID_PASID: Requested Id to PASID assignment. */
|
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| 316 | #define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_SHIFT 0
|
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| 317 | #define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PASID_MASK UINT64_C(0x00000000000fffff)
|
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| 318 | /** RID_PRIV: Requested Id to PrivilegeModeRequested assignment. */
|
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| 319 | #define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_SHIFT 20
|
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| 320 | #define VTD_BF_1_SM_CONTEXT_ENTRY_RID_PRIV_MASK UINT64_C(0x0000000000100000)
|
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| 321 | /** R: Reserved (bits 63:21). */
|
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| 322 | #define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_SHIFT 21
|
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| 323 | #define VTD_BF_1_SM_CONTEXT_ENTRY_RSVD_63_21_MASK UINT64_C(0xffffffffffe00000)
|
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| 324 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_CONTEXT_ENTRY_, UINT64_C(0), UINT64_MAX,
|
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| 325 | (RID_PASID, RID_PRIV, RSVD_63_21));
|
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| 326 |
|
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[89256] | 327 | /** Scalable-mode Context Entry. */
|
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[88153] | 328 | typedef struct VTD_SM_CONTEXT_ENTRY_T
|
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| 329 | {
|
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| 330 | /** The qwords in the scalable-mode context entry. */
|
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| 331 | uint64_t au64[4];
|
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| 332 | } VTD_SM_CONTEXT_ENTRY_T;
|
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| 333 | /** Pointer to a scalable-mode context entry. */
|
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| 334 | typedef VTD_SM_CONTEXT_ENTRY_T *PVTD_SM_CONTEXT_ENTRY_T;
|
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| 335 | /** Pointer to a const scalable-mode context entry. */
|
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| 336 | typedef VTD_SM_CONTEXT_ENTRY_T const *PCVTD_SM_CONTEXT_ENTRY_T;
|
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| 337 | /** @} */
|
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| 338 |
|
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| 339 |
|
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| 340 | /** @name Scalable-mode PASID Directory Entry.
|
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| 341 | * In accordance with the Intel spec.
|
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| 342 | * @{ */
|
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| 343 | /** P: Present. */
|
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| 344 | #define VTD_BF_SM_PASID_DIR_ENTRY_P_SHIFT 0
|
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| 345 | #define VTD_BF_SM_PASID_DIR_ENTRY_P_MASK UINT64_C(0x0000000000000001)
|
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| 346 | /** FPD: Fault Processing Disable. */
|
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| 347 | #define VTD_BF_SM_PASID_DIR_ENTRY_FPD_SHIFT 1
|
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| 348 | #define VTD_BF_SM_PASID_DIR_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
|
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| 349 | /** R: Reserved (bits 11:2). */
|
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| 350 | #define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_SHIFT 2
|
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| 351 | #define VTD_BF_SM_PASID_DIR_ENTRY_RSVD_11_2_MASK UINT64_C(0x0000000000000ffc)
|
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| 352 | /** SMPTBLPTR: Scalable Mode PASID Table Pointer. */
|
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| 353 | #define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_SHIFT 12
|
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| 354 | #define VTD_BF_SM_PASID_DIR_ENTRY_SMPTBLPTR_MASK UINT64_C(0xfffffffffffff000)
|
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| 355 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SM_PASID_DIR_ENTRY_, UINT64_C(0), UINT64_MAX,
|
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| 356 | (P, FPD, RSVD_11_2, SMPTBLPTR));
|
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| 357 |
|
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| 358 | /** Scalable-mode PASID Directory Entry. */
|
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| 359 | typedef struct VTD_SM_PASID_DIR_ENTRY_T
|
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| 360 | {
|
---|
| 361 | /** The scalable-mode PASID directory entry. */
|
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| 362 | uint64_t u;
|
---|
| 363 | } VTD_SM_PASID_DIR_ENTRY_T;
|
---|
| 364 | /** Pointer to a scalable-mode PASID directory entry. */
|
---|
| 365 | typedef VTD_SM_PASID_DIR_ENTRY_T *PVTD_SM_PASID_DIR_ENTRY_T;
|
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| 366 | /** Pointer to a const scalable-mode PASID directory entry. */
|
---|
| 367 | typedef VTD_SM_PASID_DIR_ENTRY_T const *PCVTD_SM_PASID_DIR_ENTRY_T;
|
---|
| 368 | /** @} */
|
---|
| 369 |
|
---|
| 370 |
|
---|
| 371 | /** @name Scalable-mode PASID Table Entry.
|
---|
| 372 | * In accordance with the Intel spec.
|
---|
| 373 | * @{ */
|
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| 374 | /** P: Present. */
|
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| 375 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_P_SHIFT 0
|
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| 376 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_P_MASK UINT64_C(0x0000000000000001)
|
---|
| 377 | /** FPD: Fault Processing Disable. */
|
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| 378 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_SHIFT 1
|
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| 379 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_FPD_MASK UINT64_C(0x0000000000000002)
|
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| 380 | /** AW: Address Width. */
|
---|
| 381 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_SHIFT 2
|
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| 382 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_AW_MASK UINT64_C(0x000000000000001c)
|
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| 383 | /** SLEE: Second-Level Execute Enable. */
|
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| 384 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_SHIFT 5
|
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| 385 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_SLEE_MASK UINT64_C(0x0000000000000020)
|
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| 386 | /** PGTT: PASID Granular Translation Type. */
|
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| 387 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_SHIFT 6
|
---|
| 388 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_PGTT_MASK UINT64_C(0x00000000000001c0)
|
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| 389 | /** SLADE: Second-Level Address/Dirty Enable. */
|
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| 390 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_SHIFT 9
|
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| 391 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_SLADE_MASK UINT64_C(0x0000000000000200)
|
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| 392 | /** R: Reserved (bits 11:10). */
|
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| 393 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_SHIFT 10
|
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| 394 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_RSVD_11_10_MASK UINT64_C(0x0000000000000c00)
|
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| 395 | /** SLPTPTR: Second-Level Page Table Pointer. */
|
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| 396 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_SHIFT 12
|
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| 397 | #define VTD_BF_0_SM_PASID_TBL_ENTRY_SLPTPTR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 398 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
|
---|
| 399 | (P, FPD, AW, SLEE, PGTT, SLADE, RSVD_11_10, SLPTPTR));
|
---|
| 400 |
|
---|
| 401 | /** DID: Domain Identifer. */
|
---|
| 402 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_SHIFT 0
|
---|
| 403 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_DID_MASK UINT64_C(0x000000000000ffff)
|
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| 404 | /** R: Reserved (bits 22:16). */
|
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| 405 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_SHIFT 16
|
---|
| 406 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_RSVD_22_16_MASK UINT64_C(0x00000000007f0000)
|
---|
| 407 | /** PWSNP: Page-Walk Snoop. */
|
---|
| 408 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_SHIFT 23
|
---|
| 409 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PWSNP_MASK UINT64_C(0x0000000000800000)
|
---|
| 410 | /** PGSNP: Page Snoop. */
|
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| 411 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_SHIFT 24
|
---|
| 412 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PGSNP_MASK UINT64_C(0x0000000001000000)
|
---|
| 413 | /** CD: Cache Disable. */
|
---|
| 414 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_SHIFT 25
|
---|
| 415 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_CD_MASK UINT64_C(0x0000000002000000)
|
---|
| 416 | /** EMTE: Extended Memory Type Enable. */
|
---|
| 417 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_SHIFT 26
|
---|
| 418 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_EMTE_MASK UINT64_C(0x0000000004000000)
|
---|
| 419 | /** EMT: Extended Memory Type. */
|
---|
| 420 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_SHIFT 27
|
---|
| 421 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_EMT_MASK UINT64_C(0x0000000038000000)
|
---|
| 422 | /** PWT: Page-Level Write Through. */
|
---|
| 423 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_SHIFT 30
|
---|
| 424 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PWT_MASK UINT64_C(0x0000000040000000)
|
---|
| 425 | /** PCD: Page-Level Cache Disable. */
|
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| 426 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_SHIFT 31
|
---|
| 427 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PCD_MASK UINT64_C(0x0000000080000000)
|
---|
| 428 | /** PAT: Page Attribute Table. */
|
---|
| 429 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_SHIFT 32
|
---|
| 430 | #define VTD_BF_1_SM_PASID_TBL_ENTRY_PAT_MASK UINT64_C(0xffffffff00000000)
|
---|
| 431 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
|
---|
| 432 | (DID, RSVD_22_16, PWSNP, PGSNP, CD, EMTE, EMT, PWT, PCD, PAT));
|
---|
| 433 |
|
---|
| 434 | /** SRE: Supervisor Request Enable. */
|
---|
| 435 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_SHIFT 0
|
---|
| 436 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_SRE_MASK UINT64_C(0x0000000000000001)
|
---|
| 437 | /** ERE: Execute Request Enable. */
|
---|
| 438 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_SHIFT 1
|
---|
| 439 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_ERE_MASK UINT64_C(0x0000000000000002)
|
---|
| 440 | /** FLPM: First Level Paging Mode. */
|
---|
| 441 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_SHIFT 2
|
---|
| 442 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPM_MASK UINT64_C(0x000000000000000c)
|
---|
| 443 | /** WPE: Write Protect Enable. */
|
---|
| 444 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_SHIFT 4
|
---|
| 445 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_WPE_MASK UINT64_C(0x0000000000000010)
|
---|
| 446 | /** NXE: No-Execute Enable. */
|
---|
| 447 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_SHIFT 5
|
---|
| 448 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_NXE_MASK UINT64_C(0x0000000000000020)
|
---|
| 449 | /** SMEP: Supervisor Mode Execute Prevent. */
|
---|
| 450 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_SHIFT 6
|
---|
| 451 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_SMPE_MASK UINT64_C(0x0000000000000040)
|
---|
| 452 | /** EAFE: Extended Accessed Flag Enable. */
|
---|
| 453 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_SHIFT 7
|
---|
| 454 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_EAFE_MASK UINT64_C(0x0000000000000080)
|
---|
| 455 | /** R: Reserved (bits 11:8). */
|
---|
| 456 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_SHIFT 8
|
---|
| 457 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_RSVD_11_8_MASK UINT64_C(0x0000000000000f00)
|
---|
| 458 | /** FLPTPTR: First Level Page Table Pointer. */
|
---|
| 459 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_SHIFT 12
|
---|
| 460 | #define VTD_BF_2_SM_PASID_TBL_ENTRY_FLPTPTR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 461 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_2_SM_PASID_TBL_ENTRY_, UINT64_C(0), UINT64_MAX,
|
---|
| 462 | (SRE, ERE, FLPM, WPE, NXE, SMPE, EAFE, RSVD_11_8, FLPTPTR));
|
---|
| 463 |
|
---|
| 464 | /** Scalable-mode PASID Table Entry. */
|
---|
| 465 | typedef struct VTD_SM_PASID_TBL_ENTRY_T
|
---|
| 466 | {
|
---|
| 467 | /** The qwords in the scalable-mode PASID table entry. */
|
---|
| 468 | uint64_t au64[8];
|
---|
| 469 | } VTD_SM_PASID_TBL_ENTRY_T;
|
---|
| 470 | /** Pointer to a scalable-mode PASID table entry. */
|
---|
| 471 | typedef VTD_SM_PASID_TBL_ENTRY_T *PVTD_SM_PASID_TBL_ENTRY_T;
|
---|
| 472 | /** Pointer to a const scalable-mode PASID table entry. */
|
---|
| 473 | typedef VTD_SM_PASID_TBL_ENTRY_T const *PCVTD_SM_PASID_TBL_ENTRY_T;
|
---|
| 474 | /** @} */
|
---|
| 475 |
|
---|
| 476 |
|
---|
| 477 | /** @name First-Level Paging Entry.
|
---|
| 478 | * In accordance with the Intel spec.
|
---|
| 479 | * @{ */
|
---|
| 480 | /** P: Present. */
|
---|
| 481 | #define VTD_BF_FLP_ENTRY_P_SHIFT 0
|
---|
| 482 | #define VTD_BF_FLP_ENTRY_P_MASK UINT64_C(0x0000000000000001)
|
---|
| 483 | /** R/W: Read/Write. */
|
---|
| 484 | #define VTD_BF_FLP_ENTRY_RW_SHIFT 1
|
---|
| 485 | #define VTD_BF_FLP_ENTRY_RW_MASK UINT64_C(0x0000000000000002)
|
---|
| 486 | /** U/S: User/Supervisor. */
|
---|
| 487 | #define VTD_BF_FLP_ENTRY_US_SHIFT 2
|
---|
| 488 | #define VTD_BF_FLP_ENTRY_US_MASK UINT64_C(0x0000000000000004)
|
---|
| 489 | /** PWT: Page-Level Write Through. */
|
---|
| 490 | #define VTD_BF_FLP_ENTRY_PWT_SHIFT 3
|
---|
| 491 | #define VTD_BF_FLP_ENTRY_PWT_MASK UINT64_C(0x0000000000000008)
|
---|
| 492 | /** PC: Page-Level Cache Disable. */
|
---|
| 493 | #define VTD_BF_FLP_ENTRY_PCD_SHIFT 4
|
---|
| 494 | #define VTD_BF_FLP_ENTRY_PCD_MASK UINT64_C(0x0000000000000010)
|
---|
| 495 | /** A: Accessed. */
|
---|
| 496 | #define VTD_BF_FLP_ENTRY_A_SHIFT 5
|
---|
| 497 | #define VTD_BF_FLP_ENTRY_A_MASK UINT64_C(0x0000000000000020)
|
---|
| 498 | /** IGN: Ignored (bit 6). */
|
---|
| 499 | #define VTD_BF_FLP_ENTRY_IGN_6_SHIFT 6
|
---|
| 500 | #define VTD_BF_FLP_ENTRY_IGN_6_MASK UINT64_C(0x0000000000000040)
|
---|
| 501 | /** R: Reserved (bit 7). */
|
---|
| 502 | #define VTD_BF_FLP_ENTRY_RSVD_7_SHIFT 7
|
---|
| 503 | #define VTD_BF_FLP_ENTRY_RSVD_7_MASK UINT64_C(0x0000000000000080)
|
---|
| 504 | /** IGN: Ignored (bits 9:8). */
|
---|
| 505 | #define VTD_BF_FLP_ENTRY_IGN_9_8_SHIFT 8
|
---|
| 506 | #define VTD_BF_FLP_ENTRY_IGN_9_8_MASK UINT64_C(0x0000000000000300)
|
---|
| 507 | /** EA: Extended Accessed. */
|
---|
| 508 | #define VTD_BF_FLP_ENTRY_EA_SHIFT 10
|
---|
| 509 | #define VTD_BF_FLP_ENTRY_EA_MASK UINT64_C(0x0000000000000400)
|
---|
| 510 | /** IGN: Ignored (bit 11). */
|
---|
| 511 | #define VTD_BF_FLP_ENTRY_IGN_11_SHIFT 11
|
---|
| 512 | #define VTD_BF_FLP_ENTRY_IGN_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 513 | /** ADDR: Address. */
|
---|
| 514 | #define VTD_BF_FLP_ENTRY_ADDR_SHIFT 12
|
---|
| 515 | #define VTD_BF_FLP_ENTRY_ADDR_MASK UINT64_C(0x000ffffffffff000)
|
---|
| 516 | /** IGN: Ignored (bits 62:52). */
|
---|
| 517 | #define VTD_BF_FLP_ENTRY_IGN_62_52_SHIFT 52
|
---|
| 518 | #define VTD_BF_FLP_ENTRY_IGN_62_52_MASK UINT64_C(0x7ff0000000000000)
|
---|
| 519 | /** XD: Execute Disabled. */
|
---|
| 520 | #define VTD_BF_FLP_ENTRY_XD_SHIFT 63
|
---|
| 521 | #define VTD_BF_FLP_ENTRY_XD_MASK UINT64_C(0x8000000000000000)
|
---|
| 522 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FLP_ENTRY_, UINT64_C(0), UINT64_MAX,
|
---|
| 523 | (P, RW, US, PWT, PCD, A, IGN_6, RSVD_7, IGN_9_8, EA, IGN_11, ADDR, IGN_62_52, XD));
|
---|
| 524 | /** @} */
|
---|
| 525 |
|
---|
| 526 |
|
---|
[89407] | 527 | /** @name Second-Level PML5E.
|
---|
[88153] | 528 | * In accordance with the Intel spec.
|
---|
| 529 | * @{ */
|
---|
| 530 | /** R: Read. */
|
---|
[89407] | 531 | #define VTD_BF_SL_PML5E_R_SHIFT 0
|
---|
| 532 | #define VTD_BF_SL_PML5E_R_MASK UINT64_C(0x0000000000000001)
|
---|
[88153] | 533 | /** W: Write. */
|
---|
[89407] | 534 | #define VTD_BF_SL_PML5E_W_SHIFT 1
|
---|
| 535 | #define VTD_BF_SL_PML5E_W_MASK UINT64_C(0x0000000000000002)
|
---|
[88153] | 536 | /** X: Execute. */
|
---|
[89407] | 537 | #define VTD_BF_SL_PML5E_X_SHIFT 2
|
---|
| 538 | #define VTD_BF_SL_PML5E_X_MASK UINT64_C(0x0000000000000004)
|
---|
[88153] | 539 | /** IGN: Ignored (bits 6:3). */
|
---|
[89407] | 540 | #define VTD_BF_SL_PML5E_IGN_6_3_SHIFT 3
|
---|
| 541 | #define VTD_BF_SL_PML5E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
|
---|
[88153] | 542 | /** R: Reserved (bit 7). */
|
---|
[89407] | 543 | #define VTD_BF_SL_PML5E_RSVD_7_SHIFT 7
|
---|
| 544 | #define VTD_BF_SL_PML5E_RSVD_7_MASK UINT64_C(0x0000000000000080)
|
---|
[88153] | 545 | /** A: Accessed. */
|
---|
[89407] | 546 | #define VTD_BF_SL_PML5E_A_SHIFT 8
|
---|
| 547 | #define VTD_BF_SL_PML5E_A_MASK UINT64_C(0x0000000000000100)
|
---|
[88153] | 548 | /** IGN: Ignored (bits 10:9). */
|
---|
[89407] | 549 | #define VTD_BF_SL_PML5E_IGN_10_9_SHIFT 9
|
---|
| 550 | #define VTD_BF_SL_PML5E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
|
---|
[88153] | 551 | /** R: Reserved (bit 11). */
|
---|
[89407] | 552 | #define VTD_BF_SL_PML5E_RSVD_11_SHIFT 11
|
---|
| 553 | #define VTD_BF_SL_PML5E_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
[88153] | 554 | /** ADDR: Address. */
|
---|
[89407] | 555 | #define VTD_BF_SL_PML5E_ADDR_SHIFT 12
|
---|
| 556 | #define VTD_BF_SL_PML5E_ADDR_MASK UINT64_C(0x000ffffffffff000)
|
---|
[88153] | 557 | /** IGN: Ignored (bits 61:52). */
|
---|
[89407] | 558 | #define VTD_BF_SL_PML5E_IGN_61_52_SHIFT 52
|
---|
| 559 | #define VTD_BF_SL_PML5E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
[88153] | 560 | /** R: Reserved (bit 62). */
|
---|
[89407] | 561 | #define VTD_BF_SL_PML5E_RSVD_62_SHIFT 62
|
---|
| 562 | #define VTD_BF_SL_PML5E_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
[88153] | 563 | /** IGN: Ignored (bit 63). */
|
---|
[89407] | 564 | #define VTD_BF_SL_PML5E_IGN_63_SHIFT 63
|
---|
| 565 | #define VTD_BF_SL_PML5E_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 566 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML5E_, UINT64_C(0), UINT64_MAX,
|
---|
[88153] | 567 | (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 568 |
|
---|
[89407] | 569 | /** Second-level PML5E valid mask. */
|
---|
| 570 | #define VTD_SL_PML5E_VALID_MASK ( VTD_BF_SL_PML5E_R_MASK | VTD_BF_SL_PML5E_W_MASK \
|
---|
| 571 | | VTD_BF_SL_PML5E_X_MASK | VTD_BF_SL_PML5E_IGN_6_3_MASK \
|
---|
| 572 | | VTD_BF_SL_PML5E_A_MASK | VTD_BF_SL_PML5E_IGN_10_9_MASK \
|
---|
| 573 | | VTD_BF_SL_PML5E_ADDR_MASK | VTD_BF_SL_PML5E_IGN_61_52_MASK \
|
---|
| 574 | | VTD_BF_SL_PML5E_IGN_63_MASK)
|
---|
| 575 | /** @} */
|
---|
[89312] | 576 |
|
---|
[89407] | 577 |
|
---|
| 578 | /** @name Second-Level PML4E.
|
---|
| 579 | * In accordance with the Intel spec.
|
---|
| 580 | * @{ */
|
---|
| 581 | /** R: Read. */
|
---|
| 582 | #define VTD_BF_SL_PML4E_R_SHIFT 0
|
---|
| 583 | #define VTD_BF_SL_PML4E_R_MASK UINT64_C(0x0000000000000001)
|
---|
| 584 | /** W: Write. */
|
---|
| 585 | #define VTD_BF_SL_PML4E_W_SHIFT 1
|
---|
| 586 | #define VTD_BF_SL_PML4E_W_MASK UINT64_C(0x0000000000000002)
|
---|
| 587 | /** X: Execute. */
|
---|
| 588 | #define VTD_BF_SL_PML4E_X_SHIFT 2
|
---|
| 589 | #define VTD_BF_SL_PML4E_X_MASK UINT64_C(0x0000000000000004)
|
---|
| 590 | /** IGN: Ignored (bits 6:3). */
|
---|
| 591 | #define VTD_BF_SL_PML4E_IGN_6_3_SHIFT 3
|
---|
| 592 | #define VTD_BF_SL_PML4E_IGN_6_3_MASK UINT64_C(0x0000000000000078)
|
---|
| 593 | /** R: Reserved (bit 7). */
|
---|
| 594 | #define VTD_BF_SL_PML4E_RSVD_7_SHIFT 7
|
---|
| 595 | #define VTD_BF_SL_PML4E_RSVD_7_MASK UINT64_C(0x0000000000000080)
|
---|
| 596 | /** A: Accessed. */
|
---|
| 597 | #define VTD_BF_SL_PML4E_A_SHIFT 8
|
---|
| 598 | #define VTD_BF_SL_PML4E_A_MASK UINT64_C(0x0000000000000100)
|
---|
| 599 | /** IGN: Ignored (bits 10:9). */
|
---|
| 600 | #define VTD_BF_SL_PML4E_IGN_10_9_SHIFT 9
|
---|
| 601 | #define VTD_BF_SL_PML4E_IGN_10_9_MASK UINT64_C(0x0000000000000600)
|
---|
| 602 | /** R: Reserved (bit 11). */
|
---|
| 603 | #define VTD_BF_SL_PML4E_RSVD_11_SHIFT 11
|
---|
| 604 | #define VTD_BF_SL_PML4E_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 605 | /** ADDR: Address. */
|
---|
| 606 | #define VTD_BF_SL_PML4E_ADDR_SHIFT 12
|
---|
| 607 | #define VTD_BF_SL_PML4E_ADDR_MASK UINT64_C(0x000ffffffffff000)
|
---|
| 608 | /** IGN: Ignored (bits 61:52). */
|
---|
| 609 | #define VTD_BF_SL_PML4E_IGN_61_52_SHIFT 52
|
---|
| 610 | #define VTD_BF_SL_PML4E_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
| 611 | /** R: Reserved (bit 62). */
|
---|
| 612 | #define VTD_BF_SL_PML4E_RSVD_62_SHIFT 62
|
---|
| 613 | #define VTD_BF_SL_PML4E_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 614 | /** IGN: Ignored (bit 63). */
|
---|
| 615 | #define VTD_BF_SL_PML4E_IGN_63_SHIFT 63
|
---|
| 616 | #define VTD_BF_SL_PML4E_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 617 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PML4E_, UINT64_C(0), UINT64_MAX,
|
---|
| 618 | (R, W, X, IGN_6_3, RSVD_7, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 619 |
|
---|
| 620 | /** Second-level PML4E valid mask. */
|
---|
| 621 | #define VTD_SL_PML4E_VALID_MASK VTD_SL_PML5E_VALID_MASK
|
---|
| 622 | /** @} */
|
---|
| 623 |
|
---|
| 624 |
|
---|
| 625 | /** @name Second-Level PDPE (1GB Page).
|
---|
| 626 | * In accordance with the Intel spec.
|
---|
| 627 | * @{ */
|
---|
| 628 | /** R: Read. */
|
---|
| 629 | #define VTD_BF_SL_PDPE1G_R_SHIFT 0
|
---|
| 630 | #define VTD_BF_SL_PDPE1G_R_MASK UINT64_C(0x0000000000000001)
|
---|
| 631 | /** W: Write. */
|
---|
| 632 | #define VTD_BF_SL_PDPE1G_W_SHIFT 1
|
---|
| 633 | #define VTD_BF_SL_PDPE1G_W_MASK UINT64_C(0x0000000000000002)
|
---|
| 634 | /** X: Execute. */
|
---|
| 635 | #define VTD_BF_SL_PDPE1G_X_SHIFT 2
|
---|
| 636 | #define VTD_BF_SL_PDPE1G_X_MASK UINT64_C(0x0000000000000004)
|
---|
| 637 | /** EMT: Extended Memory Type. */
|
---|
| 638 | #define VTD_BF_SL_PDPE1G_EMT_SHIFT 3
|
---|
| 639 | #define VTD_BF_SL_PDPE1G_EMT_MASK UINT64_C(0x0000000000000038)
|
---|
| 640 | /** IPAT: Ignore PAT (Page Attribute Table). */
|
---|
| 641 | #define VTD_BF_SL_PDPE1G_IPAT_SHIFT 6
|
---|
| 642 | #define VTD_BF_SL_PDPE1G_IPAT_MASK UINT64_C(0x0000000000000040)
|
---|
| 643 | /** PS: Page Size (MB1). */
|
---|
| 644 | #define VTD_BF_SL_PDPE1G_PS_SHIFT 7
|
---|
| 645 | #define VTD_BF_SL_PDPE1G_PS_MASK UINT64_C(0x0000000000000080)
|
---|
| 646 | /** A: Accessed. */
|
---|
| 647 | #define VTD_BF_SL_PDPE1G_A_SHIFT 8
|
---|
| 648 | #define VTD_BF_SL_PDPE1G_A_MASK UINT64_C(0x0000000000000100)
|
---|
| 649 | /** D: Dirty. */
|
---|
| 650 | #define VTD_BF_SL_PDPE1G_D_SHIFT 9
|
---|
| 651 | #define VTD_BF_SL_PDPE1G_D_MASK UINT64_C(0x0000000000000200)
|
---|
| 652 | /** IGN: Ignored (bit 10). */
|
---|
| 653 | #define VTD_BF_SL_PDPE1G_IGN_10_SHIFT 10
|
---|
| 654 | #define VTD_BF_SL_PDPE1G_IGN_10_MASK UINT64_C(0x0000000000000400)
|
---|
| 655 | /** R: Reserved (bit 11). */
|
---|
| 656 | #define VTD_BF_SL_PDPE1G_RSVD_11_SHIFT 11
|
---|
| 657 | #define VTD_BF_SL_PDPE1G_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 658 | /** R: Reserved (bits 29:12). */
|
---|
| 659 | #define VTD_BF_SL_PDPE1G_RSVD_29_12_SHIFT 12
|
---|
| 660 | #define VTD_BF_SL_PDPE1G_RSVD_29_12_MASK UINT64_C(0x000000003ffff000)
|
---|
| 661 | /** ADDR: Address of 1GB page. */
|
---|
| 662 | #define VTD_BF_SL_PDPE1G_ADDR_SHIFT 30
|
---|
| 663 | #define VTD_BF_SL_PDPE1G_ADDR_MASK UINT64_C(0x000fffffc0000000)
|
---|
| 664 | /** IGN: Ignored (bits 61:52). */
|
---|
| 665 | #define VTD_BF_SL_PDPE1G_IGN_61_52_SHIFT 52
|
---|
| 666 | #define VTD_BF_SL_PDPE1G_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
| 667 | /** R: Reserved (bit 62). */
|
---|
| 668 | #define VTD_BF_SL_PDPE1G_RSVD_62_SHIFT 62
|
---|
| 669 | #define VTD_BF_SL_PDPE1G_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 670 | /** IGN: Ignored (bit 63). */
|
---|
| 671 | #define VTD_BF_SL_PDPE1G_IGN_63_SHIFT 63
|
---|
| 672 | #define VTD_BF_SL_PDPE1G_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 673 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE1G_, UINT64_C(0), UINT64_MAX,
|
---|
| 674 | (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_29_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 675 |
|
---|
| 676 | /** Second-level PDPE (1GB Page) valid mask. */
|
---|
| 677 | #define VTD_SL_PDPE1G_VALID_MASK ( VTD_BF_SL_PDPE1G_R_MASK | VTD_BF_SL_PDPE1G_W_MASK \
|
---|
| 678 | | VTD_BF_SL_PDPE1G_X_MASK | VTD_BF_SL_PDPE1G_EMT_MASK \
|
---|
| 679 | | VTD_BF_SL_PDPE1G_IPAT_MASK | VTD_BF_SL_PDPE1G_PS_MASK \
|
---|
| 680 | | VTD_BF_SL_PDPE1G_A_MASK | VTD_BF_SL_PDPE1G_D_MASK \
|
---|
| 681 | | VTD_BF_SL_PDPE1G_IGN_10_MASK | VTD_BF_SL_PDPE1G_ADDR_MASK \
|
---|
| 682 | | VTD_BF_SL_PDPE1G_IGN_61_52_MASK | VTD_BF_SL_PDPE1G_IGN_63_MASK)
|
---|
| 683 | /** @} */
|
---|
| 684 |
|
---|
| 685 |
|
---|
| 686 | /** @name Second-Level PDPE.
|
---|
| 687 | * In accordance with the Intel spec.
|
---|
| 688 | * @{ */
|
---|
| 689 | /** R: Read. */
|
---|
| 690 | #define VTD_BF_SL_PDPE_R_SHIFT 0
|
---|
| 691 | #define VTD_BF_SL_PDPE_R_MASK UINT64_C(0x0000000000000001)
|
---|
| 692 | /** W: Write. */
|
---|
| 693 | #define VTD_BF_SL_PDPE_W_SHIFT 1
|
---|
| 694 | #define VTD_BF_SL_PDPE_W_MASK UINT64_C(0x0000000000000002)
|
---|
| 695 | /** X: Execute. */
|
---|
| 696 | #define VTD_BF_SL_PDPE_X_SHIFT 2
|
---|
| 697 | #define VTD_BF_SL_PDPE_X_MASK UINT64_C(0x0000000000000004)
|
---|
| 698 | /** IGN: Ignored (bits 6:3). */
|
---|
| 699 | #define VTD_BF_SL_PDPE_IGN_6_3_SHIFT 3
|
---|
| 700 | #define VTD_BF_SL_PDPE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
|
---|
| 701 | /** PS: Page Size (MBZ). */
|
---|
| 702 | #define VTD_BF_SL_PDPE_PS_SHIFT 7
|
---|
| 703 | #define VTD_BF_SL_PDPE_PS_MASK UINT64_C(0x0000000000000080)
|
---|
| 704 | /** A: Accessed. */
|
---|
| 705 | #define VTD_BF_SL_PDPE_A_SHIFT 8
|
---|
| 706 | #define VTD_BF_SL_PDPE_A_MASK UINT64_C(0x0000000000000100)
|
---|
| 707 | /** IGN: Ignored (bits 10:9). */
|
---|
| 708 | #define VTD_BF_SL_PDPE_IGN_10_9_SHIFT 9
|
---|
| 709 | #define VTD_BF_SL_PDPE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
|
---|
| 710 | /** R: Reserved (bit 11). */
|
---|
| 711 | #define VTD_BF_SL_PDPE_RSVD_11_SHIFT 11
|
---|
| 712 | #define VTD_BF_SL_PDPE_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 713 | /** ADDR: Address of second-level PDT. */
|
---|
| 714 | #define VTD_BF_SL_PDPE_ADDR_SHIFT 12
|
---|
| 715 | #define VTD_BF_SL_PDPE_ADDR_MASK UINT64_C(0x000ffffffffff000)
|
---|
| 716 | /** IGN: Ignored (bits 61:52). */
|
---|
| 717 | #define VTD_BF_SL_PDPE_IGN_61_52_SHIFT 52
|
---|
| 718 | #define VTD_BF_SL_PDPE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
| 719 | /** R: Reserved (bit 62). */
|
---|
| 720 | #define VTD_BF_SL_PDPE_RSVD_62_SHIFT 62
|
---|
| 721 | #define VTD_BF_SL_PDPE_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 722 | /** IGN: Ignored (bit 63). */
|
---|
| 723 | #define VTD_BF_SL_PDPE_IGN_63_SHIFT 63
|
---|
| 724 | #define VTD_BF_SL_PDPE_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 725 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDPE_, UINT64_C(0), UINT64_MAX,
|
---|
| 726 | (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 727 |
|
---|
| 728 | /** Second-level PDPE valid mask. */
|
---|
| 729 | #define VTD_SL_PDPE_VALID_MASK ( VTD_BF_SL_PDPE_R_MASK | VTD_BF_SL_PDPE_W_MASK \
|
---|
| 730 | | VTD_BF_SL_PDPE_X_MASK | VTD_BF_SL_PDPE_IGN_6_3_MASK \
|
---|
| 731 | | VTD_BF_SL_PDPE_PS_MASK | VTD_BF_SL_PDPE_A_MASK \
|
---|
| 732 | | VTD_BF_SL_PDPE_IGN_10_9_MASK | VTD_BF_SL_PDPE_ADDR_MASK \
|
---|
| 733 | | VTD_BF_SL_PDPE_IGN_61_52_MASK | VTD_BF_SL_PDPE_IGN_63_MASK)
|
---|
| 734 | /** @} */
|
---|
| 735 |
|
---|
| 736 |
|
---|
| 737 | /** @name Second-Level PDE (2MB Page).
|
---|
| 738 | * In accordance with the Intel spec.
|
---|
| 739 | * @{ */
|
---|
| 740 | /** R: Read. */
|
---|
| 741 | #define VTD_BF_SL_PDE2M_R_SHIFT 0
|
---|
| 742 | #define VTD_BF_SL_PDE2M_R_MASK UINT64_C(0x0000000000000001)
|
---|
| 743 | /** W: Write. */
|
---|
| 744 | #define VTD_BF_SL_PDE2M_W_SHIFT 1
|
---|
| 745 | #define VTD_BF_SL_PDE2M_W_MASK UINT64_C(0x0000000000000002)
|
---|
| 746 | /** X: Execute. */
|
---|
| 747 | #define VTD_BF_SL_PDE2M_X_SHIFT 2
|
---|
| 748 | #define VTD_BF_SL_PDE2M_X_MASK UINT64_C(0x0000000000000004)
|
---|
| 749 | /** EMT: Extended Memory Type. */
|
---|
| 750 | #define VTD_BF_SL_PDE2M_EMT_SHIFT 3
|
---|
| 751 | #define VTD_BF_SL_PDE2M_EMT_MASK UINT64_C(0x0000000000000038)
|
---|
| 752 | /** IPAT: Ignore PAT (Page Attribute Table). */
|
---|
| 753 | #define VTD_BF_SL_PDE2M_IPAT_SHIFT 6
|
---|
| 754 | #define VTD_BF_SL_PDE2M_IPAT_MASK UINT64_C(0x0000000000000040)
|
---|
| 755 | /** PS: Page Size (MB1). */
|
---|
| 756 | #define VTD_BF_SL_PDE2M_PS_SHIFT 7
|
---|
| 757 | #define VTD_BF_SL_PDE2M_PS_MASK UINT64_C(0x0000000000000080)
|
---|
| 758 | /** A: Accessed. */
|
---|
| 759 | #define VTD_BF_SL_PDE2M_A_SHIFT 8
|
---|
| 760 | #define VTD_BF_SL_PDE2M_A_MASK UINT64_C(0x0000000000000100)
|
---|
| 761 | /** D: Dirty. */
|
---|
| 762 | #define VTD_BF_SL_PDE2M_D_SHIFT 9
|
---|
| 763 | #define VTD_BF_SL_PDE2M_D_MASK UINT64_C(0x0000000000000200)
|
---|
| 764 | /** IGN: Ignored (bit 10). */
|
---|
| 765 | #define VTD_BF_SL_PDE2M_IGN_10_SHIFT 10
|
---|
| 766 | #define VTD_BF_SL_PDE2M_IGN_10_MASK UINT64_C(0x0000000000000400)
|
---|
| 767 | /** R: Reserved (bit 11). */
|
---|
| 768 | #define VTD_BF_SL_PDE2M_RSVD_11_SHIFT 11
|
---|
| 769 | #define VTD_BF_SL_PDE2M_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 770 | /** R: Reserved (bits 20:12). */
|
---|
| 771 | #define VTD_BF_SL_PDE2M_RSVD_20_12_SHIFT 12
|
---|
| 772 | #define VTD_BF_SL_PDE2M_RSVD_20_12_MASK UINT64_C(0x00000000001ff000)
|
---|
| 773 | /** ADDR: Address of 2MB page. */
|
---|
| 774 | #define VTD_BF_SL_PDE2M_ADDR_SHIFT 21
|
---|
| 775 | #define VTD_BF_SL_PDE2M_ADDR_MASK UINT64_C(0x000fffffffe00000)
|
---|
| 776 | /** IGN: Ignored (bits 61:52). */
|
---|
| 777 | #define VTD_BF_SL_PDE2M_IGN_61_52_SHIFT 52
|
---|
| 778 | #define VTD_BF_SL_PDE2M_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
| 779 | /** R: Reserved (bit 62). */
|
---|
| 780 | #define VTD_BF_SL_PDE2M_RSVD_62_SHIFT 62
|
---|
| 781 | #define VTD_BF_SL_PDE2M_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 782 | /** IGN: Ignored (bit 63). */
|
---|
| 783 | #define VTD_BF_SL_PDE2M_IGN_63_SHIFT 63
|
---|
| 784 | #define VTD_BF_SL_PDE2M_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 785 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE2M_, UINT64_C(0), UINT64_MAX,
|
---|
| 786 | (R, W, X, EMT, IPAT, PS, A, D, IGN_10, RSVD_11, RSVD_20_12, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 787 |
|
---|
| 788 | /** Second-level PDE (2MB page) valid mask. */
|
---|
| 789 | #define VTD_SL_PDE2M_VALID_MASK ( VTD_BF_SL_PDE2M_R_MASK | VTD_BF_SL_PDE2M_W_MASK \
|
---|
| 790 | | VTD_BF_SL_PDE2M_X_MASK | VTD_BF_SL_PDE2M_EMT_MASK \
|
---|
| 791 | | VTD_BF_SL_PDE2M_IPAT_MASK | VTD_BF_SL_PDE2M_PS_MASK \
|
---|
| 792 | | VTD_BF_SL_PDE2M_A_MASK | VTD_BF_SL_PDE2M_D_MASK \
|
---|
| 793 | | VTD_BF_SL_PDE2M_IGN_10_MASK | VTD_BF_SL_PDE2M_ADDR_MASK \
|
---|
| 794 | | VTD_BF_SL_PDE2M_IGN_61_52_MASK | VTD_BF_SL_PDE2M_IGN_63_MASK)
|
---|
| 795 | /** @} */
|
---|
| 796 |
|
---|
| 797 |
|
---|
| 798 | /** @name Second-Level PDE.
|
---|
| 799 | * In accordance with the Intel spec.
|
---|
| 800 | * @{ */
|
---|
| 801 | /** R: Read. */
|
---|
| 802 | #define VTD_BF_SL_PDE_R_SHIFT 0
|
---|
| 803 | #define VTD_BF_SL_PDE_R_MASK UINT64_C(0x0000000000000001)
|
---|
| 804 | /** W: Write. */
|
---|
| 805 | #define VTD_BF_SL_PDE_W_SHIFT 1
|
---|
| 806 | #define VTD_BF_SL_PDE_W_MASK UINT64_C(0x0000000000000002)
|
---|
| 807 | /** X: Execute. */
|
---|
| 808 | #define VTD_BF_SL_PDE_X_SHIFT 2
|
---|
| 809 | #define VTD_BF_SL_PDE_X_MASK UINT64_C(0x0000000000000004)
|
---|
| 810 | /** IGN: Ignored (bits 6:3). */
|
---|
| 811 | #define VTD_BF_SL_PDE_IGN_6_3_SHIFT 3
|
---|
| 812 | #define VTD_BF_SL_PDE_IGN_6_3_MASK UINT64_C(0x0000000000000078)
|
---|
| 813 | /** PS: Page Size (MBZ). */
|
---|
| 814 | #define VTD_BF_SL_PDE_PS_SHIFT 7
|
---|
| 815 | #define VTD_BF_SL_PDE_PS_MASK UINT64_C(0x0000000000000080)
|
---|
| 816 | /** A: Accessed. */
|
---|
| 817 | #define VTD_BF_SL_PDE_A_SHIFT 8
|
---|
| 818 | #define VTD_BF_SL_PDE_A_MASK UINT64_C(0x0000000000000100)
|
---|
| 819 | /** IGN: Ignored (bits 10:9). */
|
---|
| 820 | #define VTD_BF_SL_PDE_IGN_10_9_SHIFT 9
|
---|
| 821 | #define VTD_BF_SL_PDE_IGN_10_9_MASK UINT64_C(0x0000000000000600)
|
---|
| 822 | /** R: Reserved (bit 11). */
|
---|
| 823 | #define VTD_BF_SL_PDE_RSVD_11_SHIFT 11
|
---|
| 824 | #define VTD_BF_SL_PDE_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 825 | /** ADDR: Address of second-level PT. */
|
---|
| 826 | #define VTD_BF_SL_PDE_ADDR_SHIFT 12
|
---|
| 827 | #define VTD_BF_SL_PDE_ADDR_MASK UINT64_C(0x000ffffffffff000)
|
---|
| 828 | /** IGN: Ignored (bits 61:52). */
|
---|
| 829 | #define VTD_BF_SL_PDE_IGN_61_52_SHIFT 52
|
---|
| 830 | #define VTD_BF_SL_PDE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
| 831 | /** R: Reserved (bit 62). */
|
---|
| 832 | #define VTD_BF_SL_PDE_RSVD_62_SHIFT 62
|
---|
| 833 | #define VTD_BF_SL_PDE_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 834 | /** IGN: Ignored (bit 63). */
|
---|
| 835 | #define VTD_BF_SL_PDE_IGN_63_SHIFT 63
|
---|
| 836 | #define VTD_BF_SL_PDE_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 837 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PDE_, UINT64_C(0), UINT64_MAX,
|
---|
| 838 | (R, W, X, IGN_6_3, PS, A, IGN_10_9, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 839 |
|
---|
| 840 | /** Second-level PDE valid mask. */
|
---|
| 841 | #define VTD_SL_PDE_VALID_MASK ( VTD_BF_SL_PDE_R_MASK | VTD_BF_SL_PDE_W_MASK \
|
---|
| 842 | | VTD_BF_SL_PDE_X_MASK | VTD_BF_SL_PDE_IGN_6_3_MASK \
|
---|
| 843 | | VTD_BF_SL_PDE_PS_MASK | VTD_BF_SL_PDE_A_MASK \
|
---|
| 844 | | VTD_BF_SL_PDE_IGN_10_9_MASK | VTD_BF_SL_PDE_ADDR_MASK \
|
---|
| 845 | | VTD_BF_SL_PDE_IGN_61_52_MASK | VTD_BF_SL_PDE_IGN_63_MASK)
|
---|
| 846 | /** @} */
|
---|
| 847 |
|
---|
| 848 |
|
---|
| 849 | /** @name Second-Level PTE.
|
---|
| 850 | * In accordance with the Intel spec.
|
---|
| 851 | * @{ */
|
---|
| 852 | /** R: Read. */
|
---|
| 853 | #define VTD_BF_SL_PTE_R_SHIFT 0
|
---|
| 854 | #define VTD_BF_SL_PTE_R_MASK UINT64_C(0x0000000000000001)
|
---|
| 855 | /** W: Write. */
|
---|
| 856 | #define VTD_BF_SL_PTE_W_SHIFT 1
|
---|
| 857 | #define VTD_BF_SL_PTE_W_MASK UINT64_C(0x0000000000000002)
|
---|
| 858 | /** X: Execute. */
|
---|
| 859 | #define VTD_BF_SL_PTE_X_SHIFT 2
|
---|
| 860 | #define VTD_BF_SL_PTE_X_MASK UINT64_C(0x0000000000000004)
|
---|
| 861 | /** EMT: Extended Memory Type. */
|
---|
| 862 | #define VTD_BF_SL_PTE_EMT_SHIFT 3
|
---|
| 863 | #define VTD_BF_SL_PTE_EMT_MASK UINT64_C(0x0000000000000038)
|
---|
| 864 | /** IPAT: Ignore PAT (Page Attribute Table). */
|
---|
| 865 | #define VTD_BF_SL_PTE_IPAT_SHIFT 6
|
---|
| 866 | #define VTD_BF_SL_PTE_IPAT_MASK UINT64_C(0x0000000000000040)
|
---|
| 867 | /** IGN: Ignored (bit 7). */
|
---|
| 868 | #define VTD_BF_SL_PTE_IGN_7_SHIFT 7
|
---|
| 869 | #define VTD_BF_SL_PTE_IGN_7_MASK UINT64_C(0x0000000000000080)
|
---|
| 870 | /** A: Accessed. */
|
---|
| 871 | #define VTD_BF_SL_PTE_A_SHIFT 8
|
---|
| 872 | #define VTD_BF_SL_PTE_A_MASK UINT64_C(0x0000000000000100)
|
---|
| 873 | /** D: Dirty. */
|
---|
| 874 | #define VTD_BF_SL_PTE_D_SHIFT 9
|
---|
| 875 | #define VTD_BF_SL_PTE_D_MASK UINT64_C(0x0000000000000200)
|
---|
| 876 | /** IGN: Ignored (bit 10). */
|
---|
| 877 | #define VTD_BF_SL_PTE_IGN_10_SHIFT 10
|
---|
| 878 | #define VTD_BF_SL_PTE_IGN_10_MASK UINT64_C(0x0000000000000400)
|
---|
| 879 | /** R: Reserved (bit 11). */
|
---|
| 880 | #define VTD_BF_SL_PTE_RSVD_11_SHIFT 11
|
---|
| 881 | #define VTD_BF_SL_PTE_RSVD_11_MASK UINT64_C(0x0000000000000800)
|
---|
| 882 | /** ADDR: Address of 4K page. */
|
---|
| 883 | #define VTD_BF_SL_PTE_ADDR_SHIFT 12
|
---|
| 884 | #define VTD_BF_SL_PTE_ADDR_MASK UINT64_C(0x000ffffffffff000)
|
---|
| 885 | /** IGN: Ignored (bits 61:52). */
|
---|
| 886 | #define VTD_BF_SL_PTE_IGN_61_52_SHIFT 52
|
---|
| 887 | #define VTD_BF_SL_PTE_IGN_61_52_MASK UINT64_C(0x3ff0000000000000)
|
---|
| 888 | /** R: Reserved (bit 62). */
|
---|
| 889 | #define VTD_BF_SL_PTE_RSVD_62_SHIFT 62
|
---|
| 890 | #define VTD_BF_SL_PTE_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 891 | /** IGN: Ignored (bit 63). */
|
---|
| 892 | #define VTD_BF_SL_PTE_IGN_63_SHIFT 63
|
---|
| 893 | #define VTD_BF_SL_PTE_IGN_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 894 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_SL_PTE_, UINT64_C(0), UINT64_MAX,
|
---|
| 895 | (R, W, X, EMT, IPAT, IGN_7, A, D, IGN_10, RSVD_11, ADDR, IGN_61_52, RSVD_62, IGN_63));
|
---|
| 896 |
|
---|
| 897 | /** Second-level PTE valid mask. */
|
---|
| 898 | #define VTD_SL_PTE_VALID_MASK ( VTD_BF_SL_PTE_R_MASK | VTD_BF_SL_PTE_W_MASK \
|
---|
| 899 | | VTD_BF_SL_PTE_X_MASK | VTD_BF_SL_PTE_EMT_MASK \
|
---|
| 900 | | VTD_BF_SL_PTE_IPAT_MASK | VTD_BF_SL_PTE_IGN_7_MASK \
|
---|
| 901 | | VTD_BF_SL_PTE_A_MASK | VTD_BF_SL_PTE_D_MASK \
|
---|
[89429] | 902 | | VTD_BF_SL_PTE_IGN_10_MASK | VTD_BF_SL_PTE_ADDR_MASK \
|
---|
[89430] | 903 | | VTD_BF_SL_PTE_IGN_61_52_MASK | VTD_BF_SL_PTE_IGN_63_MASK)
|
---|
[89407] | 904 | /** @} */
|
---|
| 905 |
|
---|
| 906 |
|
---|
[88153] | 907 | /** @name Fault Record.
|
---|
| 908 | * In accordance with the Intel spec.
|
---|
| 909 | * @{ */
|
---|
| 910 | /** R: Reserved (bits 11:0). */
|
---|
| 911 | #define VTD_BF_0_FAULT_RECORD_RSVD_11_0_SHIFT 0
|
---|
| 912 | #define VTD_BF_0_FAULT_RECORD_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
|
---|
| 913 | /** FI: Fault Information. */
|
---|
| 914 | #define VTD_BF_0_FAULT_RECORD_FI_SHIFT 12
|
---|
| 915 | #define VTD_BF_0_FAULT_RECORD_FI_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 916 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
|
---|
| 917 | (RSVD_11_0, FI));
|
---|
| 918 |
|
---|
| 919 | /** SID: Source identifier. */
|
---|
| 920 | #define VTD_BF_1_FAULT_RECORD_SID_SHIFT 0
|
---|
| 921 | #define VTD_BF_1_FAULT_RECORD_SID_MASK UINT64_C(0x000000000000ffff)
|
---|
| 922 | /** R: Reserved (bits 28:16). */
|
---|
| 923 | #define VTD_BF_1_FAULT_RECORD_RSVD_28_16_SHIFT 16
|
---|
| 924 | #define VTD_BF_1_FAULT_RECORD_RSVD_28_16_MASK UINT64_C(0x000000001fff0000)
|
---|
| 925 | /** PRIV: Privilege Mode Requested. */
|
---|
| 926 | #define VTD_BF_1_FAULT_RECORD_PRIV_SHIFT 29
|
---|
| 927 | #define VTD_BF_1_FAULT_RECORD_PRIV_MASK UINT64_C(0x0000000020000000)
|
---|
| 928 | /** EXE: Execute Permission Requested. */
|
---|
| 929 | #define VTD_BF_1_FAULT_RECORD_EXE_SHIFT 30
|
---|
| 930 | #define VTD_BF_1_FAULT_RECORD_EXE_MASK UINT64_C(0x0000000040000000)
|
---|
| 931 | /** PP: PASID Present. */
|
---|
| 932 | #define VTD_BF_1_FAULT_RECORD_PP_SHIFT 31
|
---|
| 933 | #define VTD_BF_1_FAULT_RECORD_PP_MASK UINT64_C(0x0000000080000000)
|
---|
| 934 | /** FR: Fault Reason. */
|
---|
| 935 | #define VTD_BF_1_FAULT_RECORD_FR_SHIFT 32
|
---|
| 936 | #define VTD_BF_1_FAULT_RECORD_FR_MASK UINT64_C(0x000000ff00000000)
|
---|
| 937 | /** PV: PASID Value. */
|
---|
| 938 | #define VTD_BF_1_FAULT_RECORD_PV_SHIFT 40
|
---|
| 939 | #define VTD_BF_1_FAULT_RECORD_PV_MASK UINT64_C(0x0fffff0000000000)
|
---|
| 940 | /** AT: Address Type. */
|
---|
| 941 | #define VTD_BF_1_FAULT_RECORD_AT_SHIFT 60
|
---|
| 942 | #define VTD_BF_1_FAULT_RECORD_AT_MASK UINT64_C(0x3000000000000000)
|
---|
| 943 | /** T: Type. */
|
---|
| 944 | #define VTD_BF_1_FAULT_RECORD_T_SHIFT 62
|
---|
| 945 | #define VTD_BF_1_FAULT_RECORD_T_MASK UINT64_C(0x4000000000000000)
|
---|
| 946 | /** R: Reserved (bit 127). */
|
---|
| 947 | #define VTD_BF_1_FAULT_RECORD_RSVD_63_SHIFT 63
|
---|
| 948 | #define VTD_BF_1_FAULT_RECORD_RSVD_63_MASK UINT64_C(0x8000000000000000)
|
---|
| 949 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FAULT_RECORD_, UINT64_C(0), UINT64_MAX,
|
---|
| 950 | (SID, RSVD_28_16, PRIV, EXE, PP, FR, PV, AT, T, RSVD_63));
|
---|
| 951 |
|
---|
| 952 | /** Fault record. */
|
---|
| 953 | typedef struct VTD_FAULT_RECORD_T
|
---|
| 954 | {
|
---|
| 955 | /** The qwords in the fault record. */
|
---|
| 956 | uint64_t au64[2];
|
---|
| 957 | } VTD_FAULT_RECORD_T;
|
---|
| 958 | /** Pointer to a fault record. */
|
---|
| 959 | typedef VTD_FAULT_RECORD_T *PVTD_FAULT_RECORD_T;
|
---|
| 960 | /** Pointer to a const fault record. */
|
---|
| 961 | typedef VTD_FAULT_RECORD_T const *PCVTD_FAULT_RECORD_T;
|
---|
| 962 | /** @} */
|
---|
| 963 |
|
---|
| 964 |
|
---|
| 965 | /** @name Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts.
|
---|
| 966 | * In accordance with the Intel spec.
|
---|
| 967 | * @{ */
|
---|
| 968 | /** P: Present. */
|
---|
| 969 | #define VTD_BF_0_IRTE_P_SHIFT 0
|
---|
| 970 | #define VTD_BF_0_IRTE_P_MASK UINT64_C(0x0000000000000001)
|
---|
| 971 | /** FPD: Fault Processing Disable. */
|
---|
| 972 | #define VTD_BF_0_IRTE_FPD_SHIFT 1
|
---|
| 973 | #define VTD_BF_0_IRTE_FPD_MASK UINT64_C(0x0000000000000002)
|
---|
| 974 | /** DM: Destination Mode (0=physical, 1=logical). */
|
---|
| 975 | #define VTD_BF_0_IRTE_DM_SHIFT 2
|
---|
| 976 | #define VTD_BF_0_IRTE_DM_MASK UINT64_C(0x0000000000000004)
|
---|
| 977 | /** RH: Redirection Hint. */
|
---|
| 978 | #define VTD_BF_0_IRTE_RH_SHIFT 3
|
---|
| 979 | #define VTD_BF_0_IRTE_RH_MASK UINT64_C(0x0000000000000008)
|
---|
| 980 | /** TM: Trigger Mode. */
|
---|
| 981 | #define VTD_BF_0_IRTE_TM_SHIFT 4
|
---|
| 982 | #define VTD_BF_0_IRTE_TM_MASK UINT64_C(0x0000000000000010)
|
---|
| 983 | /** DLM: Delivery Mode. */
|
---|
| 984 | #define VTD_BF_0_IRTE_DLM_SHIFT 5
|
---|
| 985 | #define VTD_BF_0_IRTE_DLM_MASK UINT64_C(0x00000000000000e0)
|
---|
| 986 | /** AVL: Available. */
|
---|
| 987 | #define VTD_BF_0_IRTE_AVAIL_SHIFT 8
|
---|
| 988 | #define VTD_BF_0_IRTE_AVAIL_MASK UINT64_C(0x0000000000000f00)
|
---|
| 989 | /** R: Reserved (bits 14:12). */
|
---|
| 990 | #define VTD_BF_0_IRTE_RSVD_14_12_SHIFT 12
|
---|
| 991 | #define VTD_BF_0_IRTE_RSVD_14_12_MASK UINT64_C(0x0000000000007000)
|
---|
| 992 | /** IM: IRTE Mode. */
|
---|
| 993 | #define VTD_BF_0_IRTE_IM_SHIFT 15
|
---|
| 994 | #define VTD_BF_0_IRTE_IM_MASK UINT64_C(0x0000000000008000)
|
---|
| 995 | /** V: Vector. */
|
---|
| 996 | #define VTD_BF_0_IRTE_V_SHIFT 16
|
---|
| 997 | #define VTD_BF_0_IRTE_V_MASK UINT64_C(0x0000000000ff0000)
|
---|
| 998 | /** R: Reserved (bits 31:24). */
|
---|
| 999 | #define VTD_BF_0_IRTE_RSVD_31_24_SHIFT 24
|
---|
| 1000 | #define VTD_BF_0_IRTE_RSVD_31_24_MASK UINT64_C(0x00000000ff000000)
|
---|
| 1001 | /** DST: Desination Id. */
|
---|
| 1002 | #define VTD_BF_0_IRTE_DST_SHIFT 32
|
---|
| 1003 | #define VTD_BF_0_IRTE_DST_MASK UINT64_C(0xffffffff00000000)
|
---|
[88893] | 1004 | /** R: Reserved (bits 39:32) when EIME=0. */
|
---|
| 1005 | #define VTD_BF_0_IRTE_RSVD_39_32_SHIFT 32
|
---|
| 1006 | #define VTD_BF_0_IRTE_RSVD_39_32_MASK UINT64_C(0x000000ff00000000)
|
---|
| 1007 | /** DST_XAPIC: Destination Id when EIME=0. */
|
---|
| 1008 | #define VTD_BF_0_IRTE_DST_XAPIC_SHIFT 40
|
---|
| 1009 | #define VTD_BF_0_IRTE_DST_XAPIC_MASK UINT64_C(0x0000ff0000000000)
|
---|
| 1010 | /** R: Reserved (bits 63:48) when EIME=0. */
|
---|
| 1011 | #define VTD_BF_0_IRTE_RSVD_63_48_SHIFT 48
|
---|
| 1012 | #define VTD_BF_0_IRTE_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
|
---|
[88153] | 1013 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
|
---|
| 1014 | (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, DST));
|
---|
[88893] | 1015 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IRTE_, UINT64_C(0), UINT64_MAX,
|
---|
| 1016 | (P, FPD, DM, RH, TM, DLM, AVAIL, RSVD_14_12, IM, V, RSVD_31_24, RSVD_39_32, DST_XAPIC, RSVD_63_48));
|
---|
[88153] | 1017 |
|
---|
| 1018 | /** SID: Source Identifier. */
|
---|
| 1019 | #define VTD_BF_1_IRTE_SID_SHIFT 0
|
---|
| 1020 | #define VTD_BF_1_IRTE_SID_MASK UINT64_C(0x000000000000ffff)
|
---|
| 1021 | /** SQ: Source-Id Qualifier. */
|
---|
| 1022 | #define VTD_BF_1_IRTE_SQ_SHIFT 16
|
---|
| 1023 | #define VTD_BF_1_IRTE_SQ_MASK UINT64_C(0x0000000000030000)
|
---|
| 1024 | /** SVT: Source Validation Type. */
|
---|
| 1025 | #define VTD_BF_1_IRTE_SVT_SHIFT 18
|
---|
| 1026 | #define VTD_BF_1_IRTE_SVT_MASK UINT64_C(0x00000000000c0000)
|
---|
| 1027 | /** R: Reserved (bits 127:84). */
|
---|
| 1028 | #define VTD_BF_1_IRTE_RSVD_63_20_SHIFT 20
|
---|
| 1029 | #define VTD_BF_1_IRTE_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
|
---|
| 1030 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IRTE_, UINT64_C(0), UINT64_MAX,
|
---|
| 1031 | (SID, SQ, SVT, RSVD_63_20));
|
---|
| 1032 |
|
---|
[88893] | 1033 | /** IRTE: Qword 0 valid mask when EIME=1. */
|
---|
| 1034 | #define VTD_IRTE_0_X2APIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
|
---|
[88858] | 1035 | | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
|
---|
| 1036 | | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
|
---|
| 1037 | | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
|
---|
| 1038 | | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_MASK)
|
---|
[88893] | 1039 | /** IRTE: Qword 0 valid mask when EIME=0. */
|
---|
| 1040 | #define VTD_IRTE_0_XAPIC_VALID_MASK ( VTD_BF_0_IRTE_P_MASK | VTD_BF_0_IRTE_FPD_MASK \
|
---|
| 1041 | | VTD_BF_0_IRTE_DM_MASK | VTD_BF_0_IRTE_RH_MASK \
|
---|
| 1042 | | VTD_BF_0_IRTE_TM_MASK | VTD_BF_0_IRTE_DLM_MASK \
|
---|
| 1043 | | VTD_BF_0_IRTE_AVAIL_MASK | VTD_BF_0_IRTE_IM_MASK \
|
---|
| 1044 | | VTD_BF_0_IRTE_V_MASK | VTD_BF_0_IRTE_DST_XAPIC_MASK)
|
---|
[88858] | 1045 | /** IRTE: Qword 1 valid mask. */
|
---|
| 1046 | #define VTD_IRTE_1_VALID_MASK ( VTD_BF_1_IRTE_SID_MASK | VTD_BF_1_IRTE_SQ_MASK \
|
---|
| 1047 | | VTD_BF_1_IRTE_SVT_MASK)
|
---|
| 1048 |
|
---|
[88153] | 1049 | /** Interrupt Remapping Table Entry (IRTE) for remapped interrupts. */
|
---|
| 1050 | typedef struct VTD_IRTE_T
|
---|
| 1051 | {
|
---|
| 1052 | /** The qwords in the IRTE. */
|
---|
| 1053 | uint64_t au64[2];
|
---|
| 1054 | } VTD_IRTE_T;
|
---|
| 1055 | /** Pointer to an IRTE. */
|
---|
| 1056 | typedef VTD_IRTE_T *PVTD_IRTE_T;
|
---|
| 1057 | /** Pointer to a const IRTE. */
|
---|
| 1058 | typedef VTD_IRTE_T const *PCVTD_IRTE_T;
|
---|
[88858] | 1059 |
|
---|
| 1060 | /** IRTE SVT: No validation required. */
|
---|
| 1061 | #define VTD_IRTE_SVT_NONE 0
|
---|
| 1062 | /** IRTE SVT: Validate using a mask derived from SID and SQT. */
|
---|
| 1063 | #define VTD_IRTE_SVT_VALIDATE_MASK 1
|
---|
| 1064 | /** IRTE SVT: Validate using Bus range in the SID. */
|
---|
| 1065 | #define VTD_IRTE_SVT_VALIDATE_BUS_RANGE 2
|
---|
| 1066 | /** IRTE SVT: Reserved. */
|
---|
| 1067 | #define VTD_IRTE_SVT_VALIDATE_RSVD 3
|
---|
[88153] | 1068 | /** @} */
|
---|
| 1069 |
|
---|
| 1070 |
|
---|
| 1071 | /** @name Version Register (VER_REG).
|
---|
[88265] | 1072 | * In accordance with the Intel spec.
|
---|
[88153] | 1073 | * @{ */
|
---|
| 1074 | /** Min: Minor Version Number. */
|
---|
[88403] | 1075 | #define VTD_BF_VER_REG_MIN_SHIFT 0
|
---|
| 1076 | #define VTD_BF_VER_REG_MIN_MASK UINT32_C(0x0000000f)
|
---|
[88153] | 1077 | /** Max: Major Version Number. */
|
---|
[88403] | 1078 | #define VTD_BF_VER_REG_MAX_SHIFT 4
|
---|
| 1079 | #define VTD_BF_VER_REG_MAX_MASK UINT32_C(0x000000f0)
|
---|
[88153] | 1080 | /** R: Reserved (bits 31:8). */
|
---|
[88403] | 1081 | #define VTD_BF_VER_REG_RSVD_31_8_SHIFT 8
|
---|
| 1082 | #define VTD_BF_VER_REG_RSVD_31_8_MASK UINT32_C(0xffffff00)
|
---|
| 1083 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VER_REG_, UINT32_C(0), UINT32_MAX,
|
---|
[88153] | 1084 | (MIN, MAX, RSVD_31_8));
|
---|
[88201] | 1085 | /** RW: Read/write mask. */
|
---|
| 1086 | #define VTD_VER_REG_RW_MASK UINT32_C(0)
|
---|
[88153] | 1087 | /** @} */
|
---|
| 1088 |
|
---|
| 1089 |
|
---|
| 1090 | /** @name Capability Register (CAP_REG).
|
---|
[88265] | 1091 | * In accordance with the Intel spec.
|
---|
[88153] | 1092 | * @{ */
|
---|
| 1093 | /** ND: Number of domains supported. */
|
---|
| 1094 | #define VTD_BF_CAP_REG_ND_SHIFT 0
|
---|
| 1095 | #define VTD_BF_CAP_REG_ND_MASK UINT64_C(0x0000000000000007)
|
---|
| 1096 | /** AFL: Advanced Fault Logging. */
|
---|
| 1097 | #define VTD_BF_CAP_REG_AFL_SHIFT 3
|
---|
| 1098 | #define VTD_BF_CAP_REG_AFL_MASK UINT64_C(0x0000000000000008)
|
---|
| 1099 | /** RWBF: Required Write-Buffer Flushing. */
|
---|
| 1100 | #define VTD_BF_CAP_REG_RWBF_SHIFT 4
|
---|
| 1101 | #define VTD_BF_CAP_REG_RWBF_MASK UINT64_C(0x0000000000000010)
|
---|
| 1102 | /** PLMR: Protected Low-Memory Region. */
|
---|
| 1103 | #define VTD_BF_CAP_REG_PLMR_SHIFT 5
|
---|
| 1104 | #define VTD_BF_CAP_REG_PLMR_MASK UINT64_C(0x0000000000000020)
|
---|
| 1105 | /** PHMR: Protected High-Memory Region. */
|
---|
| 1106 | #define VTD_BF_CAP_REG_PHMR_SHIFT 6
|
---|
| 1107 | #define VTD_BF_CAP_REG_PHMR_MASK UINT64_C(0x0000000000000040)
|
---|
| 1108 | /** CM: Caching Mode. */
|
---|
| 1109 | #define VTD_BF_CAP_REG_CM_SHIFT 7
|
---|
| 1110 | #define VTD_BF_CAP_REG_CM_MASK UINT64_C(0x0000000000000080)
|
---|
| 1111 | /** SAGAW: Supported Adjusted Guest Address Widths. */
|
---|
| 1112 | #define VTD_BF_CAP_REG_SAGAW_SHIFT 8
|
---|
| 1113 | #define VTD_BF_CAP_REG_SAGAW_MASK UINT64_C(0x0000000000001f00)
|
---|
| 1114 | /** R: Reserved (bits 15:13). */
|
---|
| 1115 | #define VTD_BF_CAP_REG_RSVD_15_13_SHIFT 13
|
---|
| 1116 | #define VTD_BF_CAP_REG_RSVD_15_13_MASK UINT64_C(0x000000000000e000)
|
---|
| 1117 | /** MGAW: Maximum Guest Address Width. */
|
---|
| 1118 | #define VTD_BF_CAP_REG_MGAW_SHIFT 16
|
---|
| 1119 | #define VTD_BF_CAP_REG_MGAW_MASK UINT64_C(0x00000000003f0000)
|
---|
| 1120 | /** ZLR: Zero Length Read. */
|
---|
| 1121 | #define VTD_BF_CAP_REG_ZLR_SHIFT 22
|
---|
| 1122 | #define VTD_BF_CAP_REG_ZLR_MASK UINT64_C(0x0000000000400000)
|
---|
| 1123 | /** DEP: Deprecated MBZ. Reserved (bit 23). */
|
---|
| 1124 | #define VTD_BF_CAP_REG_RSVD_23_SHIFT 23
|
---|
| 1125 | #define VTD_BF_CAP_REG_RSVD_23_MASK UINT64_C(0x0000000000800000)
|
---|
| 1126 | /** FRO: Fault-recording Register Offset. */
|
---|
| 1127 | #define VTD_BF_CAP_REG_FRO_SHIFT 24
|
---|
| 1128 | #define VTD_BF_CAP_REG_FRO_MASK UINT64_C(0x00000003ff000000)
|
---|
| 1129 | /** SLLPS: Second Level Large Page Support. */
|
---|
| 1130 | #define VTD_BF_CAP_REG_SLLPS_SHIFT 34
|
---|
| 1131 | #define VTD_BF_CAP_REG_SLLPS_MASK UINT64_C(0x0000003c00000000)
|
---|
| 1132 | /** R: Reserved (bit 38). */
|
---|
| 1133 | #define VTD_BF_CAP_REG_RSVD_38_SHIFT 38
|
---|
| 1134 | #define VTD_BF_CAP_REG_RSVD_38_MASK UINT64_C(0x0000004000000000)
|
---|
| 1135 | /** PSI: Page Selective Invalidation. */
|
---|
| 1136 | #define VTD_BF_CAP_REG_PSI_SHIFT 39
|
---|
| 1137 | #define VTD_BF_CAP_REG_PSI_MASK UINT64_C(0x0000008000000000)
|
---|
| 1138 | /** NFR: Number of Fault-recording Registers. */
|
---|
| 1139 | #define VTD_BF_CAP_REG_NFR_SHIFT 40
|
---|
| 1140 | #define VTD_BF_CAP_REG_NFR_MASK UINT64_C(0x0000ff0000000000)
|
---|
| 1141 | /** MAMV: Maximum Address Mask Value. */
|
---|
| 1142 | #define VTD_BF_CAP_REG_MAMV_SHIFT 48
|
---|
| 1143 | #define VTD_BF_CAP_REG_MAMV_MASK UINT64_C(0x003f000000000000)
|
---|
| 1144 | /** DWD: Write Draining. */
|
---|
| 1145 | #define VTD_BF_CAP_REG_DWD_SHIFT 54
|
---|
| 1146 | #define VTD_BF_CAP_REG_DWD_MASK UINT64_C(0x0040000000000000)
|
---|
| 1147 | /** DRD: Read Draining. */
|
---|
| 1148 | #define VTD_BF_CAP_REG_DRD_SHIFT 55
|
---|
| 1149 | #define VTD_BF_CAP_REG_DRD_MASK UINT64_C(0x0080000000000000)
|
---|
| 1150 | /** FL1GP: First Level 1 GB Page Support. */
|
---|
| 1151 | #define VTD_BF_CAP_REG_FL1GP_SHIFT 56
|
---|
| 1152 | #define VTD_BF_CAP_REG_FL1GP_MASK UINT64_C(0x0100000000000000)
|
---|
| 1153 | /** R: Reserved (bits 58:57). */
|
---|
| 1154 | #define VTD_BF_CAP_REG_RSVD_58_57_SHIFT 57
|
---|
| 1155 | #define VTD_BF_CAP_REG_RSVD_58_57_MASK UINT64_C(0x0600000000000000)
|
---|
| 1156 | /** PI: Posted Interrupt Support. */
|
---|
| 1157 | #define VTD_BF_CAP_REG_PI_SHIFT 59
|
---|
| 1158 | #define VTD_BF_CAP_REG_PI_MASK UINT64_C(0x0800000000000000)
|
---|
| 1159 | /** FL5LP: First Level 5-level Paging Support. */
|
---|
| 1160 | #define VTD_BF_CAP_REG_FL5LP_SHIFT 60
|
---|
| 1161 | #define VTD_BF_CAP_REG_FL5LP_MASK UINT64_C(0x1000000000000000)
|
---|
[88521] | 1162 | /** R: Reserved (bit 61). */
|
---|
| 1163 | #define VTD_BF_CAP_REG_RSVD_61_SHIFT 61
|
---|
| 1164 | #define VTD_BF_CAP_REG_RSVD_61_MASK UINT64_C(0x2000000000000000)
|
---|
| 1165 | /** ESIRTPS: Enhanced Set Interrupt Root Table Pointer Support. */
|
---|
| 1166 | #define VTD_BF_CAP_REG_ESIRTPS_SHIFT 62
|
---|
| 1167 | #define VTD_BF_CAP_REG_ESIRTPS_MASK UINT64_C(0x4000000000000000)
|
---|
| 1168 | /** : Enhanced Set Root Table Pointer Support. */
|
---|
| 1169 | #define VTD_BF_CAP_REG_ESRTPS_SHIFT 63
|
---|
| 1170 | #define VTD_BF_CAP_REG_ESRTPS_MASK UINT64_C(0x8000000000000000)
|
---|
[88153] | 1171 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CAP_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1172 | (ND, AFL, RWBF, PLMR, PHMR, CM, SAGAW, RSVD_15_13, MGAW, ZLR, RSVD_23, FRO, SLLPS, RSVD_38, PSI, NFR,
|
---|
[88521] | 1173 | MAMV, DWD, DRD, FL1GP, RSVD_58_57, PI, FL5LP, RSVD_61, ESIRTPS, ESRTPS));
|
---|
[88201] | 1174 |
|
---|
| 1175 | /** RW: Read/write mask. */
|
---|
[88257] | 1176 | #define VTD_CAP_REG_RW_MASK UINT64_C(0)
|
---|
[88153] | 1177 | /** @} */
|
---|
| 1178 |
|
---|
| 1179 |
|
---|
| 1180 | /** @name Extended Capability Register (ECAP_REG).
|
---|
[88265] | 1181 | * In accordance with the Intel spec.
|
---|
[88153] | 1182 | * @{ */
|
---|
| 1183 | /** C: Page-walk Coherence. */
|
---|
| 1184 | #define VTD_BF_ECAP_REG_C_SHIFT 0
|
---|
| 1185 | #define VTD_BF_ECAP_REG_C_MASK UINT64_C(0x0000000000000001)
|
---|
| 1186 | /** QI: Queued Invalidation Support. */
|
---|
| 1187 | #define VTD_BF_ECAP_REG_QI_SHIFT 1
|
---|
| 1188 | #define VTD_BF_ECAP_REG_QI_MASK UINT64_C(0x0000000000000002)
|
---|
| 1189 | /** DT: Device-TLB Support. */
|
---|
| 1190 | #define VTD_BF_ECAP_REG_DT_SHIFT 2
|
---|
| 1191 | #define VTD_BF_ECAP_REG_DT_MASK UINT64_C(0x0000000000000004)
|
---|
| 1192 | /** IR: Interrupt Remapping Support. */
|
---|
| 1193 | #define VTD_BF_ECAP_REG_IR_SHIFT 3
|
---|
| 1194 | #define VTD_BF_ECAP_REG_IR_MASK UINT64_C(0x0000000000000008)
|
---|
| 1195 | /** EIM: Extended Interrupt Mode. */
|
---|
| 1196 | #define VTD_BF_ECAP_REG_EIM_SHIFT 4
|
---|
| 1197 | #define VTD_BF_ECAP_REG_EIM_MASK UINT64_C(0x0000000000000010)
|
---|
| 1198 | /** DEP: Deprecated MBZ. Reserved (bit 5). */
|
---|
| 1199 | #define VTD_BF_ECAP_REG_RSVD_5_SHIFT 5
|
---|
| 1200 | #define VTD_BF_ECAP_REG_RSVD_5_MASK UINT64_C(0x0000000000000020)
|
---|
| 1201 | /** PT: Pass Through. */
|
---|
| 1202 | #define VTD_BF_ECAP_REG_PT_SHIFT 6
|
---|
| 1203 | #define VTD_BF_ECAP_REG_PT_MASK UINT64_C(0x0000000000000040)
|
---|
| 1204 | /** SC: Snoop Control. */
|
---|
| 1205 | #define VTD_BF_ECAP_REG_SC_SHIFT 7
|
---|
| 1206 | #define VTD_BF_ECAP_REG_SC_MASK UINT64_C(0x0000000000000080)
|
---|
| 1207 | /** IRO: IOTLB Register Offset. */
|
---|
| 1208 | #define VTD_BF_ECAP_REG_IRO_SHIFT 8
|
---|
| 1209 | #define VTD_BF_ECAP_REG_IRO_MASK UINT64_C(0x000000000003ff00)
|
---|
| 1210 | /** R: Reserved (bits 19:18). */
|
---|
| 1211 | #define VTD_BF_ECAP_REG_RSVD_19_18_SHIFT 18
|
---|
| 1212 | #define VTD_BF_ECAP_REG_RSVD_19_18_MASK UINT64_C(0x00000000000c0000)
|
---|
| 1213 | /** MHMV: Maximum Handle Mask Value. */
|
---|
| 1214 | #define VTD_BF_ECAP_REG_MHMV_SHIFT 20
|
---|
| 1215 | #define VTD_BF_ECAP_REG_MHMV_MASK UINT64_C(0x0000000000f00000)
|
---|
| 1216 | /** DEP: Deprecated MBZ. Reserved (bit 24). */
|
---|
| 1217 | #define VTD_BF_ECAP_REG_RSVD_24_SHIFT 24
|
---|
| 1218 | #define VTD_BF_ECAP_REG_RSVD_24_MASK UINT64_C(0x0000000001000000)
|
---|
| 1219 | /** MTS: Memory Type Support. */
|
---|
| 1220 | #define VTD_BF_ECAP_REG_MTS_SHIFT 25
|
---|
| 1221 | #define VTD_BF_ECAP_REG_MTS_MASK UINT64_C(0x0000000002000000)
|
---|
| 1222 | /** NEST: Nested Translation Support. */
|
---|
| 1223 | #define VTD_BF_ECAP_REG_NEST_SHIFT 26
|
---|
| 1224 | #define VTD_BF_ECAP_REG_NEST_MASK UINT64_C(0x0000000004000000)
|
---|
| 1225 | /** R: Reserved (bit 27). */
|
---|
| 1226 | #define VTD_BF_ECAP_REG_RSVD_27_SHIFT 27
|
---|
| 1227 | #define VTD_BF_ECAP_REG_RSVD_27_MASK UINT64_C(0x0000000008000000)
|
---|
| 1228 | /** DEP: Deprecated MBZ. Reserved (bit 28). */
|
---|
| 1229 | #define VTD_BF_ECAP_REG_RSVD_28_SHIFT 28
|
---|
| 1230 | #define VTD_BF_ECAP_REG_RSVD_28_MASK UINT64_C(0x0000000010000000)
|
---|
| 1231 | /** PRS: Page Request Support. */
|
---|
| 1232 | #define VTD_BF_ECAP_REG_PRS_SHIFT 29
|
---|
| 1233 | #define VTD_BF_ECAP_REG_PRS_MASK UINT64_C(0x0000000020000000)
|
---|
| 1234 | /** ERS: Execute Request Support. */
|
---|
| 1235 | #define VTD_BF_ECAP_REG_ERS_SHIFT 30
|
---|
| 1236 | #define VTD_BF_ECAP_REG_ERS_MASK UINT64_C(0x0000000040000000)
|
---|
| 1237 | /** SRS: Supervisor Request Support. */
|
---|
| 1238 | #define VTD_BF_ECAP_REG_SRS_SHIFT 31
|
---|
| 1239 | #define VTD_BF_ECAP_REG_SRS_MASK UINT64_C(0x0000000080000000)
|
---|
| 1240 | /** R: Reserved (bit 32). */
|
---|
| 1241 | #define VTD_BF_ECAP_REG_RSVD_32_SHIFT 32
|
---|
| 1242 | #define VTD_BF_ECAP_REG_RSVD_32_MASK UINT64_C(0x0000000100000000)
|
---|
| 1243 | /** NWFS: No Write Flag Support. */
|
---|
| 1244 | #define VTD_BF_ECAP_REG_NWFS_SHIFT 33
|
---|
| 1245 | #define VTD_BF_ECAP_REG_NWFS_MASK UINT64_C(0x0000000200000000)
|
---|
| 1246 | /** EAFS: Extended Accessed Flags Support. */
|
---|
| 1247 | #define VTD_BF_ECAP_REG_EAFS_SHIFT 34
|
---|
| 1248 | #define VTD_BF_ECAP_REG_EAFS_MASK UINT64_C(0x0000000400000000)
|
---|
| 1249 | /** PSS: PASID Size Supported. */
|
---|
| 1250 | #define VTD_BF_ECAP_REG_PSS_SHIFT 35
|
---|
| 1251 | #define VTD_BF_ECAP_REG_PSS_MASK UINT64_C(0x000000f800000000)
|
---|
| 1252 | /** PASID: Process Address Space ID Support. */
|
---|
| 1253 | #define VTD_BF_ECAP_REG_PASID_SHIFT 40
|
---|
| 1254 | #define VTD_BF_ECAP_REG_PASID_MASK UINT64_C(0x0000010000000000)
|
---|
| 1255 | /** DIT: Device-TLB Invalidation Throttle. */
|
---|
| 1256 | #define VTD_BF_ECAP_REG_DIT_SHIFT 41
|
---|
| 1257 | #define VTD_BF_ECAP_REG_DIT_MASK UINT64_C(0x0000020000000000)
|
---|
| 1258 | /** PDS: Page-request Drain Support. */
|
---|
| 1259 | #define VTD_BF_ECAP_REG_PDS_SHIFT 42
|
---|
| 1260 | #define VTD_BF_ECAP_REG_PDS_MASK UINT64_C(0x0000040000000000)
|
---|
| 1261 | /** SMTS: Scalable-Mode Translation Support. */
|
---|
| 1262 | #define VTD_BF_ECAP_REG_SMTS_SHIFT 43
|
---|
| 1263 | #define VTD_BF_ECAP_REG_SMTS_MASK UINT64_C(0x0000080000000000)
|
---|
| 1264 | /** VCS: Virtual Command Support. */
|
---|
| 1265 | #define VTD_BF_ECAP_REG_VCS_SHIFT 44
|
---|
| 1266 | #define VTD_BF_ECAP_REG_VCS_MASK UINT64_C(0x0000100000000000)
|
---|
| 1267 | /** SLADS: Second-Level Accessed/Dirty Support. */
|
---|
| 1268 | #define VTD_BF_ECAP_REG_SLADS_SHIFT 45
|
---|
| 1269 | #define VTD_BF_ECAP_REG_SLADS_MASK UINT64_C(0x0000200000000000)
|
---|
| 1270 | /** SLTS: Second-Level Translation Support. */
|
---|
| 1271 | #define VTD_BF_ECAP_REG_SLTS_SHIFT 46
|
---|
| 1272 | #define VTD_BF_ECAP_REG_SLTS_MASK UINT64_C(0x0000400000000000)
|
---|
| 1273 | /** FLTS: First-Level Translation Support. */
|
---|
| 1274 | #define VTD_BF_ECAP_REG_FLTS_SHIFT 47
|
---|
| 1275 | #define VTD_BF_ECAP_REG_FLTS_MASK UINT64_C(0x0000800000000000)
|
---|
| 1276 | /** SMPWCS: Scalable-Mode Page-Walk Coherency Support. */
|
---|
| 1277 | #define VTD_BF_ECAP_REG_SMPWCS_SHIFT 48
|
---|
| 1278 | #define VTD_BF_ECAP_REG_SMPWCS_MASK UINT64_C(0x0001000000000000)
|
---|
| 1279 | /** RPS: RID-PASID Support. */
|
---|
| 1280 | #define VTD_BF_ECAP_REG_RPS_SHIFT 49
|
---|
| 1281 | #define VTD_BF_ECAP_REG_RPS_MASK UINT64_C(0x0002000000000000)
|
---|
[88521] | 1282 | /** R: Reserved (bits 51:50). */
|
---|
| 1283 | #define VTD_BF_ECAP_REG_RSVD_51_50_SHIFT 50
|
---|
| 1284 | #define VTD_BF_ECAP_REG_RSVD_51_50_MASK UINT64_C(0x000c000000000000)
|
---|
| 1285 | /** ADMS: Abort DMA Mode Support. */
|
---|
| 1286 | #define VTD_BF_ECAP_REG_ADMS_SHIFT 52
|
---|
| 1287 | #define VTD_BF_ECAP_REG_ADMS_MASK UINT64_C(0x0010000000000000)
|
---|
| 1288 | /** RPRIVS: RID_PRIV Support. */
|
---|
| 1289 | #define VTD_BF_ECAP_REG_RPRIVS_SHIFT 53
|
---|
| 1290 | #define VTD_BF_ECAP_REG_RPRIVS_MASK UINT64_C(0x0020000000000000)
|
---|
| 1291 | /** R: Reserved (bits 63:54). */
|
---|
| 1292 | #define VTD_BF_ECAP_REG_RSVD_63_54_SHIFT 54
|
---|
| 1293 | #define VTD_BF_ECAP_REG_RSVD_63_54_MASK UINT64_C(0xffc0000000000000)
|
---|
[88153] | 1294 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ECAP_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1295 | (C, QI, DT, IR, EIM, RSVD_5, PT, SC, IRO, RSVD_19_18, MHMV, RSVD_24, MTS, NEST, RSVD_27, RSVD_28,
|
---|
| 1296 | PRS, ERS, SRS, RSVD_32, NWFS, EAFS, PSS, PASID, DIT, PDS, SMTS, VCS, SLADS, SLTS, FLTS, SMPWCS, RPS,
|
---|
[88521] | 1297 | RSVD_51_50, ADMS, RPRIVS, RSVD_63_54));
|
---|
[88201] | 1298 |
|
---|
| 1299 | /** RW: Read/write mask. */
|
---|
[88257] | 1300 | #define VTD_ECAP_REG_RW_MASK UINT64_C(0)
|
---|
[88153] | 1301 | /** @} */
|
---|
| 1302 |
|
---|
| 1303 |
|
---|
| 1304 | /** @name Global Command Register (GCMD_REG).
|
---|
[88265] | 1305 | * In accordance with the Intel spec.
|
---|
[88153] | 1306 | * @{ */
|
---|
| 1307 | /** R: Reserved (bits 22:0). */
|
---|
| 1308 | #define VTD_BF_GCMD_REG_RSVD_22_0_SHIFT 0
|
---|
| 1309 | #define VTD_BF_GCMD_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
|
---|
| 1310 | /** CFI: Compatibility Format Interrupt. */
|
---|
| 1311 | #define VTD_BF_GCMD_REG_CFI_SHIFT 23
|
---|
| 1312 | #define VTD_BF_GCMD_REG_CFI_MASK UINT32_C(0x00800000)
|
---|
| 1313 | /** SIRTP: Set Interrupt Table Remap Pointer. */
|
---|
| 1314 | #define VTD_BF_GCMD_REG_SIRTP_SHIFT 24
|
---|
| 1315 | #define VTD_BF_GCMD_REG_SIRTP_MASK UINT32_C(0x01000000)
|
---|
| 1316 | /** IRE: Interrupt Remap Enable. */
|
---|
| 1317 | #define VTD_BF_GCMD_REG_IRE_SHIFT 25
|
---|
| 1318 | #define VTD_BF_GCMD_REG_IRE_MASK UINT32_C(0x02000000)
|
---|
| 1319 | /** QIE: Queued Invalidation Enable. */
|
---|
| 1320 | #define VTD_BF_GCMD_REG_QIE_SHIFT 26
|
---|
| 1321 | #define VTD_BF_GCMD_REG_QIE_MASK UINT32_C(0x04000000)
|
---|
| 1322 | /** WBF: Write Buffer Flush. */
|
---|
| 1323 | #define VTD_BF_GCMD_REG_WBF_SHIFT 27
|
---|
| 1324 | #define VTD_BF_GCMD_REG_WBF_MASK UINT32_C(0x08000000)
|
---|
| 1325 | /** EAFL: Enable Advance Fault Logging. */
|
---|
| 1326 | #define VTD_BF_GCMD_REG_EAFL_SHIFT 28
|
---|
| 1327 | #define VTD_BF_GCMD_REG_EAFL_MASK UINT32_C(0x10000000)
|
---|
| 1328 | /** SFL: Set Fault Log. */
|
---|
| 1329 | #define VTD_BF_GCMD_REG_SFL_SHIFT 29
|
---|
| 1330 | #define VTD_BF_GCMD_REG_SFL_MASK UINT32_C(0x20000000)
|
---|
| 1331 | /** SRTP: Set Root Table Pointer. */
|
---|
| 1332 | #define VTD_BF_GCMD_REG_SRTP_SHIFT 30
|
---|
| 1333 | #define VTD_BF_GCMD_REG_SRTP_MASK UINT32_C(0x40000000)
|
---|
| 1334 | /** TE: Translation Enable. */
|
---|
| 1335 | #define VTD_BF_GCMD_REG_TE_SHIFT 31
|
---|
| 1336 | #define VTD_BF_GCMD_REG_TE_MASK UINT32_C(0x80000000)
|
---|
| 1337 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GCMD_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1338 | (RSVD_22_0, CFI, SIRTP, IRE, QIE, WBF, EAFL, SFL, SRTP, TE));
|
---|
[88201] | 1339 |
|
---|
| 1340 | /** RW: Read/write mask. */
|
---|
[88894] | 1341 | #define VTD_GCMD_REG_RW_MASK ( VTD_BF_GCMD_REG_TE_MASK | VTD_BF_GCMD_REG_SRTP_MASK \
|
---|
| 1342 | | VTD_BF_GCMD_REG_SFL_MASK | VTD_BF_GCMD_REG_EAFL_MASK \
|
---|
| 1343 | | VTD_BF_GCMD_REG_WBF_MASK | VTD_BF_GCMD_REG_QIE_MASK \
|
---|
| 1344 | | VTD_BF_GCMD_REG_IRE_MASK | VTD_BF_GCMD_REG_SIRTP_MASK \
|
---|
| 1345 | | VTD_BF_GCMD_REG_CFI_MASK)
|
---|
[88153] | 1346 | /** @} */
|
---|
| 1347 |
|
---|
| 1348 |
|
---|
| 1349 | /** @name Global Status Register (GSTS_REG).
|
---|
[88265] | 1350 | * In accordance with the Intel spec.
|
---|
[88153] | 1351 | * @{ */
|
---|
| 1352 | /** R: Reserved (bits 22:0). */
|
---|
| 1353 | #define VTD_BF_GSTS_REG_RSVD_22_0_SHIFT 0
|
---|
| 1354 | #define VTD_BF_GSTS_REG_RSVD_22_0_MASK UINT32_C(0x007fffff)
|
---|
| 1355 | /** CFIS: Compatibility Format Interrupt Status. */
|
---|
| 1356 | #define VTD_BF_GSTS_REG_CFIS_SHIFT 23
|
---|
| 1357 | #define VTD_BF_GSTS_REG_CFIS_MASK UINT32_C(0x00800000)
|
---|
| 1358 | /** IRTPS: Interrupt Remapping Table Pointer Status. */
|
---|
| 1359 | #define VTD_BF_GSTS_REG_IRTPS_SHIFT 24
|
---|
| 1360 | #define VTD_BF_GSTS_REG_IRTPS_MASK UINT32_C(0x01000000)
|
---|
| 1361 | /** IRES: Interrupt Remapping Enable Status. */
|
---|
| 1362 | #define VTD_BF_GSTS_REG_IRES_SHIFT 25
|
---|
| 1363 | #define VTD_BF_GSTS_REG_IRES_MASK UINT32_C(0x02000000)
|
---|
| 1364 | /** QIES: Queued Invalidation Enable Status. */
|
---|
| 1365 | #define VTD_BF_GSTS_REG_QIES_SHIFT 26
|
---|
| 1366 | #define VTD_BF_GSTS_REG_QIES_MASK UINT32_C(0x04000000)
|
---|
| 1367 | /** WBFS: Write Buffer Flush Status. */
|
---|
| 1368 | #define VTD_BF_GSTS_REG_WBFS_SHIFT 27
|
---|
| 1369 | #define VTD_BF_GSTS_REG_WBFS_MASK UINT32_C(0x08000000)
|
---|
| 1370 | /** AFLS: Advanced Fault Logging Status. */
|
---|
| 1371 | #define VTD_BF_GSTS_REG_AFLS_SHIFT 28
|
---|
| 1372 | #define VTD_BF_GSTS_REG_AFLS_MASK UINT32_C(0x10000000)
|
---|
| 1373 | /** FLS: Fault Log Status. */
|
---|
| 1374 | #define VTD_BF_GSTS_REG_FLS_SHIFT 29
|
---|
| 1375 | #define VTD_BF_GSTS_REG_FLS_MASK UINT32_C(0x20000000)
|
---|
| 1376 | /** RTPS: Root Table Pointer Status. */
|
---|
| 1377 | #define VTD_BF_GSTS_REG_RTPS_SHIFT 30
|
---|
| 1378 | #define VTD_BF_GSTS_REG_RTPS_MASK UINT32_C(0x40000000)
|
---|
| 1379 | /** TES: Translation Enable Status. */
|
---|
| 1380 | #define VTD_BF_GSTS_REG_TES_SHIFT 31
|
---|
| 1381 | #define VTD_BF_GSTS_REG_TES_MASK UINT32_C(0x80000000)
|
---|
| 1382 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_GSTS_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1383 | (RSVD_22_0, CFIS, IRTPS, IRES, QIES, WBFS, AFLS, FLS, RTPS, TES));
|
---|
[88201] | 1384 |
|
---|
| 1385 | /** RW: Read/write mask. */
|
---|
| 1386 | #define VTD_GSTS_REG_RW_MASK UINT32_C(0)
|
---|
[88153] | 1387 | /** @} */
|
---|
| 1388 |
|
---|
| 1389 |
|
---|
| 1390 | /** @name Root Table Address Register (RTADDR_REG).
|
---|
[88265] | 1391 | * In accordance with the Intel spec.
|
---|
[88153] | 1392 | * @{ */
|
---|
| 1393 | /** R: Reserved (bits 9:0). */
|
---|
| 1394 | #define VTD_BF_RTADDR_REG_RSVD_9_0_SHIFT 0
|
---|
| 1395 | #define VTD_BF_RTADDR_REG_RSVD_9_0_MASK UINT64_C(0x00000000000003ff)
|
---|
| 1396 | /** TTM: Translation Table Mode. */
|
---|
| 1397 | #define VTD_BF_RTADDR_REG_TTM_SHIFT 10
|
---|
| 1398 | #define VTD_BF_RTADDR_REG_TTM_MASK UINT64_C(0x0000000000000c00)
|
---|
| 1399 | /** RTA: Root Table Address. */
|
---|
| 1400 | #define VTD_BF_RTADDR_REG_RTA_SHIFT 12
|
---|
| 1401 | #define VTD_BF_RTADDR_REG_RTA_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 1402 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_RTADDR_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1403 | (RSVD_9_0, TTM, RTA));
|
---|
[88201] | 1404 |
|
---|
| 1405 | /** RW: Read/write mask. */
|
---|
| 1406 | #define VTD_RTADDR_REG_RW_MASK UINT64_C(0xfffffffffffffc00)
|
---|
[88558] | 1407 |
|
---|
| 1408 | /** RTADDR_REG.TTM: Legacy mode. */
|
---|
| 1409 | #define VTD_TTM_LEGACY_MODE 0
|
---|
| 1410 | /** RTADDR_REG.TTM: Scalable mode. */
|
---|
| 1411 | #define VTD_TTM_SCALABLE_MODE 1
|
---|
| 1412 | /** RTADDR_REG.TTM: Reserved. */
|
---|
| 1413 | #define VTD_TTM_RSVD 2
|
---|
| 1414 | /** RTADDR_REG.TTM: Abort DMA mode. */
|
---|
| 1415 | #define VTD_TTM_ABORT_DMA_MODE 3
|
---|
[88153] | 1416 | /** @} */
|
---|
| 1417 |
|
---|
| 1418 |
|
---|
| 1419 | /** @name Context Command Register (CCMD_REG).
|
---|
[88265] | 1420 | * In accordance with the Intel spec.
|
---|
[88153] | 1421 | * @{ */
|
---|
| 1422 | /** DID: Domain-ID. */
|
---|
| 1423 | #define VTD_BF_CCMD_REG_DID_SHIFT 0
|
---|
| 1424 | #define VTD_BF_CCMD_REG_DID_MASK UINT64_C(0x000000000000ffff)
|
---|
| 1425 | /** SID: Source-ID. */
|
---|
| 1426 | #define VTD_BF_CCMD_REG_SID_SHIFT 16
|
---|
| 1427 | #define VTD_BF_CCMD_REG_SID_MASK UINT64_C(0x00000000ffff0000)
|
---|
| 1428 | /** FM: Function Mask. */
|
---|
| 1429 | #define VTD_BF_CCMD_REG_FM_SHIFT 32
|
---|
| 1430 | #define VTD_BF_CCMD_REG_FM_MASK UINT64_C(0x0000000300000000)
|
---|
| 1431 | /** R: Reserved (bits 58:34). */
|
---|
| 1432 | #define VTD_BF_CCMD_REG_RSVD_58_34_SHIFT 34
|
---|
| 1433 | #define VTD_BF_CCMD_REG_RSVD_58_34_MASK UINT64_C(0x07fffffc00000000)
|
---|
| 1434 | /** CAIG: Context Actual Invalidation Granularity. */
|
---|
| 1435 | #define VTD_BF_CCMD_REG_CAIG_SHIFT 59
|
---|
| 1436 | #define VTD_BF_CCMD_REG_CAIG_MASK UINT64_C(0x1800000000000000)
|
---|
| 1437 | /** CIRG: Context Invalidation Request Granularity. */
|
---|
| 1438 | #define VTD_BF_CCMD_REG_CIRG_SHIFT 61
|
---|
| 1439 | #define VTD_BF_CCMD_REG_CIRG_MASK UINT64_C(0x6000000000000000)
|
---|
| 1440 | /** ICC: Invalidation Context Cache. */
|
---|
| 1441 | #define VTD_BF_CCMD_REG_ICC_SHIFT 63
|
---|
| 1442 | #define VTD_BF_CCMD_REG_ICC_MASK UINT64_C(0x8000000000000000)
|
---|
| 1443 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_CCMD_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1444 | (DID, SID, FM, RSVD_58_34, CAIG, CIRG, ICC));
|
---|
[88201] | 1445 |
|
---|
| 1446 | /** RW: Read/write mask. */
|
---|
| 1447 | #define VTD_CCMD_REG_RW_MASK ( VTD_BF_CCMD_REG_DID_MASK | VTD_BF_CCMD_REG_SID_MASK \
|
---|
| 1448 | | VTD_BF_CCMD_REG_FM_MASK | VTD_BF_CCMD_REG_CIRG_MASK \
|
---|
| 1449 | | VTD_BF_CCMD_REG_ICC_MASK)
|
---|
[88153] | 1450 | /** @} */
|
---|
| 1451 |
|
---|
| 1452 |
|
---|
| 1453 | /** @name IOTLB Invalidation Register (IOTLB_REG).
|
---|
[88265] | 1454 | * In accordance with the Intel spec.
|
---|
[88153] | 1455 | * @{ */
|
---|
| 1456 | /** R: Reserved (bits 31:0). */
|
---|
| 1457 | #define VTD_BF_IOTLB_REG_RSVD_31_0_SHIFT 0
|
---|
| 1458 | #define VTD_BF_IOTLB_REG_RSVD_31_0_MASK UINT64_C(0x00000000ffffffff)
|
---|
| 1459 | /** DID: Domain-ID. */
|
---|
| 1460 | #define VTD_BF_IOTLB_REG_DID_SHIFT 32
|
---|
| 1461 | #define VTD_BF_IOTLB_REG_DID_MASK UINT64_C(0x0000ffff00000000)
|
---|
| 1462 | /** DW: Draining Writes. */
|
---|
| 1463 | #define VTD_BF_IOTLB_REG_DW_SHIFT 48
|
---|
| 1464 | #define VTD_BF_IOTLB_REG_DW_MASK UINT64_C(0x0001000000000000)
|
---|
| 1465 | /** DR: Draining Reads. */
|
---|
| 1466 | #define VTD_BF_IOTLB_REG_DR_SHIFT 49
|
---|
| 1467 | #define VTD_BF_IOTLB_REG_DR_MASK UINT64_C(0x0002000000000000)
|
---|
| 1468 | /** R: Reserved (bits 56:50). */
|
---|
| 1469 | #define VTD_BF_IOTLB_REG_RSVD_56_50_SHIFT 50
|
---|
| 1470 | #define VTD_BF_IOTLB_REG_RSVD_56_50_MASK UINT64_C(0x01fc000000000000)
|
---|
| 1471 | /** IAIG: IOTLB Actual Invalidation Granularity. */
|
---|
| 1472 | #define VTD_BF_IOTLB_REG_IAIG_SHIFT 57
|
---|
| 1473 | #define VTD_BF_IOTLB_REG_IAIG_MASK UINT64_C(0x0600000000000000)
|
---|
| 1474 | /** R: Reserved (bit 59). */
|
---|
| 1475 | #define VTD_BF_IOTLB_REG_RSVD_59_SHIFT 59
|
---|
| 1476 | #define VTD_BF_IOTLB_REG_RSVD_59_MASK UINT64_C(0x0800000000000000)
|
---|
| 1477 | /** IIRG: IOTLB Invalidation Request Granularity. */
|
---|
| 1478 | #define VTD_BF_IOTLB_REG_IIRG_SHIFT 60
|
---|
| 1479 | #define VTD_BF_IOTLB_REG_IIRG_MASK UINT64_C(0x3000000000000000)
|
---|
| 1480 | /** R: Reserved (bit 62). */
|
---|
| 1481 | #define VTD_BF_IOTLB_REG_RSVD_62_SHIFT 62
|
---|
| 1482 | #define VTD_BF_IOTLB_REG_RSVD_62_MASK UINT64_C(0x4000000000000000)
|
---|
| 1483 | /** IVT: Invalidate IOTLB. */
|
---|
| 1484 | #define VTD_BF_IOTLB_REG_IVT_SHIFT 63
|
---|
| 1485 | #define VTD_BF_IOTLB_REG_IVT_MASK UINT64_C(0x8000000000000000)
|
---|
| 1486 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IOTLB_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1487 | (RSVD_31_0, DID, DW, DR, RSVD_56_50, IAIG, RSVD_59, IIRG, RSVD_62, IVT));
|
---|
[88257] | 1488 |
|
---|
| 1489 | /** RW: Read/write mask. */
|
---|
| 1490 | #define VTD_IOTLB_REG_RW_MASK ( VTD_BF_IOTLB_REG_DID_MASK | VTD_BF_IOTLB_REG_DW_MASK \
|
---|
| 1491 | | VTD_BF_IOTLB_REG_DR_MASK | VTD_BF_IOTLB_REG_IIRG_MASK \
|
---|
| 1492 | | VTD_BF_IOTLB_REG_IVT_MASK)
|
---|
[88153] | 1493 | /** @} */
|
---|
| 1494 |
|
---|
| 1495 |
|
---|
| 1496 | /** @name Invalidate Address Register (IVA_REG).
|
---|
[88265] | 1497 | * In accordance with the Intel spec.
|
---|
[88153] | 1498 | * @{ */
|
---|
| 1499 | /** AM: Address Mask. */
|
---|
| 1500 | #define VTD_BF_IVA_REG_AM_SHIFT 0
|
---|
| 1501 | #define VTD_BF_IVA_REG_AM_MASK UINT64_C(0x000000000000003f)
|
---|
| 1502 | /** IH: Invalidation Hint. */
|
---|
| 1503 | #define VTD_BF_IVA_REG_IH_SHIFT 6
|
---|
| 1504 | #define VTD_BF_IVA_REG_IH_MASK UINT64_C(0x0000000000000040)
|
---|
| 1505 | /** R: Reserved (bits 11:7). */
|
---|
| 1506 | #define VTD_BF_IVA_REG_RSVD_11_7_SHIFT 7
|
---|
| 1507 | #define VTD_BF_IVA_REG_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
|
---|
| 1508 | /** ADDR: Address. */
|
---|
| 1509 | #define VTD_BF_IVA_REG_ADDR_SHIFT 12
|
---|
| 1510 | #define VTD_BF_IVA_REG_ADDR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 1511 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IVA_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1512 | (AM, IH, RSVD_11_7, ADDR));
|
---|
[88257] | 1513 |
|
---|
| 1514 | /** RW: Read/write mask. */
|
---|
| 1515 | #define VTD_IVA_REG_RW_MASK ( VTD_BF_IVA_REG_AM_MASK | VTD_BF_IVA_REG_IH_MASK \
|
---|
| 1516 | | VTD_BF_IVA_REG_ADDR_MASK)
|
---|
[88153] | 1517 | /** @} */
|
---|
| 1518 |
|
---|
| 1519 |
|
---|
| 1520 | /** @name Fault Status Register (FSTS_REG).
|
---|
[88265] | 1521 | * In accordance with the Intel spec.
|
---|
[88153] | 1522 | * @{ */
|
---|
| 1523 | /** PFO: Primary Fault Overflow. */
|
---|
| 1524 | #define VTD_BF_FSTS_REG_PFO_SHIFT 0
|
---|
| 1525 | #define VTD_BF_FSTS_REG_PFO_MASK UINT32_C(0x00000001)
|
---|
| 1526 | /** PPF: Primary Pending Fault. */
|
---|
| 1527 | #define VTD_BF_FSTS_REG_PPF_SHIFT 1
|
---|
| 1528 | #define VTD_BF_FSTS_REG_PPF_MASK UINT32_C(0x00000002)
|
---|
| 1529 | /** AFO: Advanced Fault Overflow. */
|
---|
| 1530 | #define VTD_BF_FSTS_REG_AFO_SHIFT 2
|
---|
| 1531 | #define VTD_BF_FSTS_REG_AFO_MASK UINT32_C(0x00000004)
|
---|
| 1532 | /** APF: Advanced Pending Fault. */
|
---|
| 1533 | #define VTD_BF_FSTS_REG_APF_SHIFT 3
|
---|
| 1534 | #define VTD_BF_FSTS_REG_APF_MASK UINT32_C(0x00000008)
|
---|
| 1535 | /** IQE: Invalidation Queue Error. */
|
---|
| 1536 | #define VTD_BF_FSTS_REG_IQE_SHIFT 4
|
---|
| 1537 | #define VTD_BF_FSTS_REG_IQE_MASK UINT32_C(0x00000010)
|
---|
| 1538 | /** ICE: Invalidation Completion Error. */
|
---|
| 1539 | #define VTD_BF_FSTS_REG_ICE_SHIFT 5
|
---|
| 1540 | #define VTD_BF_FSTS_REG_ICE_MASK UINT32_C(0x00000020)
|
---|
| 1541 | /** ITE: Invalidation Timeout Error. */
|
---|
| 1542 | #define VTD_BF_FSTS_REG_ITE_SHIFT 6
|
---|
| 1543 | #define VTD_BF_FSTS_REG_ITE_MASK UINT32_C(0x00000040)
|
---|
| 1544 | /** DEP: Deprecated MBZ. Reserved (bit 7). */
|
---|
| 1545 | #define VTD_BF_FSTS_REG_RSVD_7_SHIFT 7
|
---|
| 1546 | #define VTD_BF_FSTS_REG_RSVD_7_MASK UINT32_C(0x00000080)
|
---|
| 1547 | /** FRI: Fault Record Index. */
|
---|
| 1548 | #define VTD_BF_FSTS_REG_FRI_SHIFT 8
|
---|
| 1549 | #define VTD_BF_FSTS_REG_FRI_MASK UINT32_C(0x0000ff00)
|
---|
| 1550 | /** R: Reserved (bits 31:16). */
|
---|
| 1551 | #define VTD_BF_FSTS_REG_RSVD_31_16_SHIFT 16
|
---|
| 1552 | #define VTD_BF_FSTS_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
|
---|
| 1553 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FSTS_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1554 | (PFO, PPF, AFO, APF, IQE, ICE, ITE, RSVD_7, FRI, RSVD_31_16));
|
---|
[88201] | 1555 |
|
---|
| 1556 | /** RW: Read/write mask. */
|
---|
| 1557 | #define VTD_FSTS_REG_RW_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
|
---|
| 1558 | | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
|
---|
| 1559 | | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
|
---|
[88203] | 1560 | /** RW1C: Read-only-status, Write-1-to-clear status mask. */
|
---|
| 1561 | #define VTD_FSTS_REG_RW1C_MASK ( VTD_BF_FSTS_REG_PFO_MASK | VTD_BF_FSTS_REG_AFO_MASK \
|
---|
| 1562 | | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_IQE_MASK \
|
---|
| 1563 | | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK)
|
---|
[88153] | 1564 | /** @} */
|
---|
| 1565 |
|
---|
| 1566 |
|
---|
| 1567 | /** @name Fault Event Control Register (FECTL_REG).
|
---|
[88265] | 1568 | * In accordance with the Intel spec.
|
---|
[88153] | 1569 | * @{ */
|
---|
| 1570 | /** R: Reserved (bits 29:0). */
|
---|
| 1571 | #define VTD_BF_FECTL_REG_RSVD_29_0_SHIFT 0
|
---|
| 1572 | #define VTD_BF_FECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
|
---|
| 1573 | /** IP: Interrupt Pending. */
|
---|
| 1574 | #define VTD_BF_FECTL_REG_IP_SHIFT 30
|
---|
| 1575 | #define VTD_BF_FECTL_REG_IP_MASK UINT32_C(0x40000000)
|
---|
| 1576 | /** IM: Interrupt Mask. */
|
---|
| 1577 | #define VTD_BF_FECTL_REG_IM_SHIFT 31
|
---|
| 1578 | #define VTD_BF_FECTL_REG_IM_MASK UINT32_C(0x80000000)
|
---|
| 1579 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FECTL_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1580 | (RSVD_29_0, IP, IM));
|
---|
[88201] | 1581 |
|
---|
| 1582 | /** RW: Read/write mask. */
|
---|
| 1583 | #define VTD_FECTL_REG_RW_MASK VTD_BF_FECTL_REG_IM_MASK
|
---|
[88153] | 1584 | /** @} */
|
---|
| 1585 |
|
---|
| 1586 |
|
---|
| 1587 | /** @name Fault Event Data Register (FEDATA_REG).
|
---|
[88265] | 1588 | * In accordance with the Intel spec.
|
---|
[88153] | 1589 | * @{ */
|
---|
| 1590 | /** IMD: Interrupt Message Data. */
|
---|
| 1591 | #define VTD_BF_FEDATA_REG_IMD_SHIFT 0
|
---|
| 1592 | #define VTD_BF_FEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
|
---|
[88518] | 1593 | /** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
|
---|
| 1594 | #define VTD_BF_FEDATA_REG_RSVD_31_16_SHIFT 16
|
---|
| 1595 | #define VTD_BF_FEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
|
---|
[88153] | 1596 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEDATA_REG_, UINT32_C(0), UINT32_MAX,
|
---|
[88518] | 1597 | (IMD, RSVD_31_16));
|
---|
[88201] | 1598 |
|
---|
[89001] | 1599 | /** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
|
---|
| 1600 | * Programming". */
|
---|
| 1601 | #define VTD_FEDATA_REG_RW_MASK UINT32_C(0x000001ff)
|
---|
[88153] | 1602 | /** @} */
|
---|
| 1603 |
|
---|
| 1604 |
|
---|
| 1605 | /** @name Fault Event Address Register (FEADDR_REG).
|
---|
[88265] | 1606 | * In accordance with the Intel spec.
|
---|
[88153] | 1607 | * @{ */
|
---|
| 1608 | /** R: Reserved (bits 1:0). */
|
---|
| 1609 | #define VTD_BF_FEADDR_REG_RSVD_1_0_SHIFT 0
|
---|
| 1610 | #define VTD_BF_FEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
|
---|
| 1611 | /** MA: Message Address. */
|
---|
| 1612 | #define VTD_BF_FEADDR_REG_MA_SHIFT 2
|
---|
| 1613 | #define VTD_BF_FEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
|
---|
| 1614 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_FEADDR_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1615 | (RSVD_1_0, MA));
|
---|
[88201] | 1616 |
|
---|
| 1617 | /** RW: Read/write mask. */
|
---|
| 1618 | #define VTD_FEADDR_REG_RW_MASK VTD_BF_FEADDR_REG_MA_MASK
|
---|
[88153] | 1619 | /** @} */
|
---|
| 1620 |
|
---|
| 1621 |
|
---|
[88201] | 1622 | /** @name Fault Event Upper Address Register (FEUADDR_REG).
|
---|
[88265] | 1623 | * In accordance with the Intel spec.
|
---|
[88201] | 1624 | * @{ */
|
---|
| 1625 | /** MUA: Message Upper Address. */
|
---|
| 1626 | #define VTD_BF_FEUADDR_REG_MA_SHIFT 0
|
---|
| 1627 | #define VTD_BF_FEUADDR_REG_MA_MASK UINT32_C(0xffffffff)
|
---|
| 1628 |
|
---|
| 1629 | /** RW: Read/write mask. */
|
---|
| 1630 | #define VTD_FEUADDR_REG_RW_MASK VTD_BF_FEUADDR_REG_MA_MASK
|
---|
| 1631 | /** @} */
|
---|
| 1632 |
|
---|
| 1633 |
|
---|
[88153] | 1634 | /** @name Fault Recording Register (FRCD_REG).
|
---|
[88265] | 1635 | * In accordance with the Intel spec.
|
---|
[88153] | 1636 | * @{ */
|
---|
| 1637 | /** R: Reserved (bits 11:0). */
|
---|
| 1638 | #define VTD_BF_0_FRCD_REG_RSVD_11_0_SHIFT 0
|
---|
| 1639 | #define VTD_BF_0_FRCD_REG_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
|
---|
| 1640 | /** FI: Fault Info. */
|
---|
| 1641 | #define VTD_BF_0_FRCD_REG_FI_SHIFT 12
|
---|
| 1642 | #define VTD_BF_0_FRCD_REG_FI_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 1643 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_FRCD_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1644 | (RSVD_11_0, FI));
|
---|
| 1645 |
|
---|
| 1646 | /** SID: Source Identifier. */
|
---|
| 1647 | #define VTD_BF_1_FRCD_REG_SID_SHIFT 0
|
---|
| 1648 | #define VTD_BF_1_FRCD_REG_SID_MASK UINT64_C(0x000000000000ffff)
|
---|
| 1649 | /** R: Reserved (bits 27:16). */
|
---|
| 1650 | #define VTD_BF_1_FRCD_REG_RSVD_27_16_SHIFT 16
|
---|
| 1651 | #define VTD_BF_1_FRCD_REG_RSVD_27_16_MASK UINT64_C(0x000000000fff0000)
|
---|
| 1652 | /** T2: Type bit 2. */
|
---|
| 1653 | #define VTD_BF_1_FRCD_REG_T2_SHIFT 28
|
---|
| 1654 | #define VTD_BF_1_FRCD_REG_T2_MASK UINT64_C(0x0000000010000000)
|
---|
| 1655 | /** PRIV: Privilege Mode. */
|
---|
| 1656 | #define VTD_BF_1_FRCD_REG_PRIV_SHIFT 29
|
---|
| 1657 | #define VTD_BF_1_FRCD_REG_PRIV_MASK UINT64_C(0x0000000020000000)
|
---|
| 1658 | /** EXE: Execute Permission Requested. */
|
---|
| 1659 | #define VTD_BF_1_FRCD_REG_EXE_SHIFT 30
|
---|
| 1660 | #define VTD_BF_1_FRCD_REG_EXE_MASK UINT64_C(0x0000000040000000)
|
---|
| 1661 | /** PP: PASID Present. */
|
---|
| 1662 | #define VTD_BF_1_FRCD_REG_PP_SHIFT 31
|
---|
| 1663 | #define VTD_BF_1_FRCD_REG_PP_MASK UINT64_C(0x0000000080000000)
|
---|
| 1664 | /** FR: Fault Reason. */
|
---|
| 1665 | #define VTD_BF_1_FRCD_REG_FR_SHIFT 32
|
---|
| 1666 | #define VTD_BF_1_FRCD_REG_FR_MASK UINT64_C(0x000000ff00000000)
|
---|
| 1667 | /** PV: PASID Value. */
|
---|
| 1668 | #define VTD_BF_1_FRCD_REG_PV_SHIFT 40
|
---|
| 1669 | #define VTD_BF_1_FRCD_REG_PV_MASK UINT64_C(0x0fffff0000000000)
|
---|
| 1670 | /** AT: Address Type. */
|
---|
| 1671 | #define VTD_BF_1_FRCD_REG_AT_SHIFT 60
|
---|
| 1672 | #define VTD_BF_1_FRCD_REG_AT_MASK UINT64_C(0x3000000000000000)
|
---|
| 1673 | /** T1: Type bit 1. */
|
---|
| 1674 | #define VTD_BF_1_FRCD_REG_T1_SHIFT 62
|
---|
| 1675 | #define VTD_BF_1_FRCD_REG_T1_MASK UINT64_C(0x4000000000000000)
|
---|
| 1676 | /** F: Fault. */
|
---|
| 1677 | #define VTD_BF_1_FRCD_REG_F_SHIFT 63
|
---|
| 1678 | #define VTD_BF_1_FRCD_REG_F_MASK UINT64_C(0x8000000000000000)
|
---|
| 1679 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_FRCD_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1680 | (SID, RSVD_27_16, T2, PRIV, EXE, PP, FR, PV, AT, T1, F));
|
---|
[88257] | 1681 |
|
---|
| 1682 | /** RW: Read/write mask. */
|
---|
| 1683 | #define VTD_FRCD_REG_LO_RW_MASK UINT64_C(0)
|
---|
| 1684 | #define VTD_FRCD_REG_HI_RW_MASK VTD_BF_1_FRCD_REG_F_MASK
|
---|
| 1685 | /** RW1C: Read-only-status, Write-1-to-clear status mask. */
|
---|
| 1686 | #define VTD_FRCD_REG_LO_RW1C_MASK UINT64_C(0)
|
---|
| 1687 | #define VTD_FRCD_REG_HI_RW1C_MASK VTD_BF_1_FRCD_REG_F_MASK
|
---|
[88153] | 1688 | /** @} */
|
---|
| 1689 |
|
---|
| 1690 |
|
---|
[89216] | 1691 | /**
|
---|
[89238] | 1692 | * VT-d faulted address translation request types (FRCD_REG::T2).
|
---|
[89216] | 1693 | * In accordance with the Intel spec.
|
---|
| 1694 | */
|
---|
| 1695 | typedef enum VTDREQTYPE
|
---|
| 1696 | {
|
---|
[89235] | 1697 | VTDREQTYPE_WRITE = 0, /**< Memory access write request. */
|
---|
| 1698 | VTDREQTYPE_PAGE, /**< Page translation request. */
|
---|
| 1699 | VTDREQTYPE_READ, /**< Memory access read request. */
|
---|
| 1700 | VTDREQTYPE_ATOMIC_OP /**< Memory access atomic operation. */
|
---|
[89216] | 1701 | } VTDREQTYPE;
|
---|
[89578] | 1702 | /** Pointer to a VTDREQTYPE. */
|
---|
| 1703 | typedef VTDREQTYPE *PVTDREQTYPE;
|
---|
[89216] | 1704 |
|
---|
| 1705 |
|
---|
[88153] | 1706 | /** @name Advanced Fault Log Register (AFLOG_REG).
|
---|
[88265] | 1707 | * In accordance with the Intel spec.
|
---|
[88153] | 1708 | * @{ */
|
---|
| 1709 | /** R: Reserved (bits 8:0). */
|
---|
| 1710 | #define VTD_BF_0_AFLOG_REG_RSVD_8_0_SHIFT 0
|
---|
| 1711 | #define VTD_BF_0_AFLOG_REG_RSVD_8_0_MASK UINT64_C(0x00000000000001ff)
|
---|
| 1712 | /** FLS: Fault Log Size. */
|
---|
| 1713 | #define VTD_BF_0_AFLOG_REG_FLS_SHIFT 9
|
---|
| 1714 | #define VTD_BF_0_AFLOG_REG_FLS_MASK UINT64_C(0x0000000000000e00)
|
---|
| 1715 | /** FLA: Fault Log Address. */
|
---|
| 1716 | #define VTD_BF_0_AFLOG_REG_FLA_SHIFT 12
|
---|
| 1717 | #define VTD_BF_0_AFLOG_REG_FLA_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 1718 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_AFLOG_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1719 | (RSVD_8_0, FLS, FLA));
|
---|
[88201] | 1720 |
|
---|
| 1721 | /** RW: Read/write mask. */
|
---|
| 1722 | #define VTD_AFLOG_REG_RW_MASK (VTD_BF_0_AFLOG_REG_FLS_MASK | VTD_BF_0_AFLOG_REG_FLA_MASK)
|
---|
[88153] | 1723 | /** @} */
|
---|
| 1724 |
|
---|
| 1725 |
|
---|
| 1726 | /** @name Protected Memory Enable Register (PMEN_REG).
|
---|
[88265] | 1727 | * In accordance with the Intel spec.
|
---|
[88153] | 1728 | * @{ */
|
---|
| 1729 | /** PRS: Protected Region Status. */
|
---|
| 1730 | #define VTD_BF_PMEN_REG_PRS_SHIFT 0
|
---|
| 1731 | #define VTD_BF_PMEN_REG_PRS_MASK UINT32_C(0x00000001)
|
---|
| 1732 | /** R: Reserved (bits 30:1). */
|
---|
| 1733 | #define VTD_BF_PMEN_REG_RSVD_30_1_SHIFT 1
|
---|
| 1734 | #define VTD_BF_PMEN_REG_RSVD_30_1_MASK UINT32_C(0x7ffffffe)
|
---|
| 1735 | /** EPM: Enable Protected Memory. */
|
---|
| 1736 | #define VTD_BF_PMEN_REG_EPM_SHIFT 31
|
---|
| 1737 | #define VTD_BF_PMEN_REG_EPM_MASK UINT32_C(0x80000000)
|
---|
| 1738 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PMEN_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1739 | (PRS, RSVD_30_1, EPM));
|
---|
[88201] | 1740 |
|
---|
| 1741 | /** RW: Read/write mask. */
|
---|
| 1742 | #define VTD_PMEN_REG_RW_MASK VTD_BF_PMEN_REG_EPM_MASK
|
---|
[88153] | 1743 | /** @} */
|
---|
| 1744 |
|
---|
| 1745 |
|
---|
| 1746 | /** @name Invalidation Queue Head Register (IQH_REG).
|
---|
[88265] | 1747 | * In accordance with the Intel spec.
|
---|
[88153] | 1748 | * @{ */
|
---|
| 1749 | /** R: Reserved (bits 3:0). */
|
---|
| 1750 | #define VTD_BF_IQH_REG_RSVD_3_0_SHIFT 0
|
---|
| 1751 | #define VTD_BF_IQH_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
|
---|
| 1752 | /** QH: Queue Head. */
|
---|
| 1753 | #define VTD_BF_IQH_REG_QH_SHIFT 4
|
---|
| 1754 | #define VTD_BF_IQH_REG_QH_MASK UINT64_C(0x000000000007fff0)
|
---|
| 1755 | /** R: Reserved (bits 63:19). */
|
---|
| 1756 | #define VTD_BF_IQH_REG_RSVD_63_19_SHIFT 19
|
---|
| 1757 | #define VTD_BF_IQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
|
---|
| 1758 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQH_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1759 | (RSVD_3_0, QH, RSVD_63_19));
|
---|
[88201] | 1760 |
|
---|
| 1761 | /** RW: Read/write mask. */
|
---|
| 1762 | #define VTD_IQH_REG_RW_MASK UINT64_C(0x0)
|
---|
[88153] | 1763 | /** @} */
|
---|
| 1764 |
|
---|
| 1765 |
|
---|
| 1766 | /** @name Invalidation Queue Tail Register (IQT_REG).
|
---|
[88265] | 1767 | * In accordance with the Intel spec.
|
---|
[88153] | 1768 | * @{ */
|
---|
| 1769 | /** R: Reserved (bits 3:0). */
|
---|
| 1770 | #define VTD_BF_IQT_REG_RSVD_3_0_SHIFT 0
|
---|
| 1771 | #define VTD_BF_IQT_REG_RSVD_3_0_MASK UINT64_C(0x000000000000000f)
|
---|
| 1772 | /** QH: Queue Tail. */
|
---|
| 1773 | #define VTD_BF_IQT_REG_QT_SHIFT 4
|
---|
| 1774 | #define VTD_BF_IQT_REG_QT_MASK UINT64_C(0x000000000007fff0)
|
---|
| 1775 | /** R: Reserved (bits 63:19). */
|
---|
| 1776 | #define VTD_BF_IQT_REG_RSVD_63_19_SHIFT 19
|
---|
| 1777 | #define VTD_BF_IQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
|
---|
| 1778 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQT_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1779 | (RSVD_3_0, QT, RSVD_63_19));
|
---|
[88201] | 1780 |
|
---|
| 1781 | /** RW: Read/write mask. */
|
---|
| 1782 | #define VTD_IQT_REG_RW_MASK VTD_BF_IQT_REG_QT_MASK
|
---|
[88153] | 1783 | /** @} */
|
---|
| 1784 |
|
---|
[88201] | 1785 |
|
---|
[88153] | 1786 | /** @name Invalidation Queue Address Register (IQA_REG).
|
---|
[88265] | 1787 | * In accordance with the Intel spec.
|
---|
[88153] | 1788 | * @{ */
|
---|
| 1789 | /** QS: Queue Size. */
|
---|
| 1790 | #define VTD_BF_IQA_REG_QS_SHIFT 0
|
---|
| 1791 | #define VTD_BF_IQA_REG_QS_MASK UINT64_C(0x0000000000000007)
|
---|
| 1792 | /** R: Reserved (bits 10:3). */
|
---|
| 1793 | #define VTD_BF_IQA_REG_RSVD_10_3_SHIFT 3
|
---|
| 1794 | #define VTD_BF_IQA_REG_RSVD_10_3_MASK UINT64_C(0x00000000000007f8)
|
---|
| 1795 | /** DW: Descriptor Width. */
|
---|
| 1796 | #define VTD_BF_IQA_REG_DW_SHIFT 11
|
---|
| 1797 | #define VTD_BF_IQA_REG_DW_MASK UINT64_C(0x0000000000000800)
|
---|
| 1798 | /** IQA: Invalidation Queue Base Address. */
|
---|
| 1799 | #define VTD_BF_IQA_REG_IQA_SHIFT 12
|
---|
| 1800 | #define VTD_BF_IQA_REG_IQA_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 1801 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQA_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1802 | (QS, RSVD_10_3, DW, IQA));
|
---|
[88201] | 1803 |
|
---|
| 1804 | /** RW: Read/write mask. */
|
---|
| 1805 | #define VTD_IQA_REG_RW_MASK ( VTD_BF_IQA_REG_QS_MASK | VTD_BF_IQA_REG_DW_MASK \
|
---|
| 1806 | | VTD_BF_IQA_REG_IQA_MASK)
|
---|
[88494] | 1807 | /** DW: 128-bit descriptor. */
|
---|
| 1808 | #define VTD_IQA_REG_DW_128_BIT 0
|
---|
| 1809 | /** DW: 256-bit descriptor. */
|
---|
| 1810 | #define VTD_IQA_REG_DW_256_BIT 1
|
---|
[88153] | 1811 | /** @} */
|
---|
| 1812 |
|
---|
| 1813 |
|
---|
| 1814 | /** @name Invalidation Completion Status Register (ICS_REG).
|
---|
[88265] | 1815 | * In accordance with the Intel spec.
|
---|
[88153] | 1816 | * @{ */
|
---|
| 1817 | /** IWC: Invalidation Wait Descriptor Complete. */
|
---|
| 1818 | #define VTD_BF_ICS_REG_IWC_SHIFT 0
|
---|
| 1819 | #define VTD_BF_ICS_REG_IWC_MASK UINT32_C(0x00000001)
|
---|
| 1820 | /** R: Reserved (bits 31:1). */
|
---|
| 1821 | #define VTD_BF_ICS_REG_RSVD_31_1_SHIFT 1
|
---|
| 1822 | #define VTD_BF_ICS_REG_RSVD_31_1_MASK UINT32_C(0xfffffffe)
|
---|
| 1823 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_ICS_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1824 | (IWC, RSVD_31_1));
|
---|
[88201] | 1825 |
|
---|
| 1826 | /** RW: Read/write mask. */
|
---|
| 1827 | #define VTD_ICS_REG_RW_MASK VTD_BF_ICS_REG_IWC_MASK
|
---|
[88203] | 1828 | /** RW1C: Read-only-status, Write-1-to-clear status mask. */
|
---|
| 1829 | #define VTD_ICS_REG_RW1C_MASK VTD_BF_ICS_REG_IWC_MASK
|
---|
[88153] | 1830 | /** @} */
|
---|
| 1831 |
|
---|
| 1832 |
|
---|
| 1833 | /** @name Invalidation Event Control Register (IECTL_REG).
|
---|
[88265] | 1834 | * In accordance with the Intel spec.
|
---|
[88153] | 1835 | * @{ */
|
---|
| 1836 | /** R: Reserved (bits 29:0). */
|
---|
| 1837 | #define VTD_BF_IECTL_REG_RSVD_29_0_SHIFT 0
|
---|
| 1838 | #define VTD_BF_IECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
|
---|
| 1839 | /** IP: Interrupt Pending. */
|
---|
| 1840 | #define VTD_BF_IECTL_REG_IP_SHIFT 30
|
---|
| 1841 | #define VTD_BF_IECTL_REG_IP_MASK UINT32_C(0x40000000)
|
---|
| 1842 | /** IM: Interrupt Mask. */
|
---|
| 1843 | #define VTD_BF_IECTL_REG_IM_SHIFT 31
|
---|
| 1844 | #define VTD_BF_IECTL_REG_IM_MASK UINT32_C(0x80000000)
|
---|
| 1845 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IECTL_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1846 | (RSVD_29_0, IP, IM));
|
---|
[88201] | 1847 |
|
---|
| 1848 | /** RW: Read/write mask. */
|
---|
| 1849 | #define VTD_IECTL_REG_RW_MASK VTD_BF_IECTL_REG_IM_MASK
|
---|
[88153] | 1850 | /** @} */
|
---|
| 1851 |
|
---|
| 1852 |
|
---|
| 1853 | /** @name Invalidation Event Data Register (IEDATA_REG).
|
---|
[88265] | 1854 | * In accordance with the Intel spec.
|
---|
[88153] | 1855 | * @{ */
|
---|
| 1856 | /** IMD: Interrupt Message Data. */
|
---|
| 1857 | #define VTD_BF_IEDATA_REG_IMD_SHIFT 0
|
---|
| 1858 | #define VTD_BF_IEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
|
---|
[88518] | 1859 | /** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
|
---|
| 1860 | #define VTD_BF_IEDATA_REG_RSVD_31_16_SHIFT 16
|
---|
| 1861 | #define VTD_BF_IEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
|
---|
[88153] | 1862 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEDATA_REG_, UINT32_C(0), UINT32_MAX,
|
---|
[88518] | 1863 | (IMD, RSVD_31_16));
|
---|
[88201] | 1864 |
|
---|
[89001] | 1865 | /** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
|
---|
| 1866 | * Programming". */
|
---|
| 1867 | #define VTD_IEDATA_REG_RW_MASK UINT32_C(0x000001ff)
|
---|
[88153] | 1868 | /** @} */
|
---|
| 1869 |
|
---|
| 1870 |
|
---|
| 1871 | /** @name Invalidation Event Address Register (IEADDR_REG).
|
---|
[88265] | 1872 | * In accordance with the Intel spec.
|
---|
[88153] | 1873 | * @{ */
|
---|
| 1874 | /** R: Reserved (bits 1:0). */
|
---|
| 1875 | #define VTD_BF_IEADDR_REG_RSVD_1_0_SHIFT 0
|
---|
| 1876 | #define VTD_BF_IEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
|
---|
| 1877 | /** MA: Message Address. */
|
---|
| 1878 | #define VTD_BF_IEADDR_REG_MA_SHIFT 2
|
---|
| 1879 | #define VTD_BF_IEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
|
---|
| 1880 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IEADDR_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 1881 | (RSVD_1_0, MA));
|
---|
[88201] | 1882 |
|
---|
| 1883 | /** RW: Read/write mask. */
|
---|
| 1884 | #define VTD_IEADDR_REG_RW_MASK VTD_BF_IEADDR_REG_MA_MASK
|
---|
[88153] | 1885 | /** @} */
|
---|
| 1886 |
|
---|
| 1887 |
|
---|
[88201] | 1888 | /** @name Invalidation Event Upper Address Register (IEUADDR_REG).
|
---|
| 1889 | * @{ */
|
---|
| 1890 | /** MUA: Message Upper Address. */
|
---|
| 1891 | #define VTD_BF_IEUADDR_REG_MUA_SHIFT 0
|
---|
| 1892 | #define VTD_BF_IEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
|
---|
| 1893 |
|
---|
| 1894 | /** RW: Read/write mask. */
|
---|
| 1895 | #define VTD_IEUADDR_REG_RW_MASK VTD_BF_IEUADDR_REG_MUA_MASK
|
---|
| 1896 | /** @} */
|
---|
| 1897 |
|
---|
| 1898 |
|
---|
[88153] | 1899 | /** @name Invalidation Queue Error Record Register (IQERCD_REG).
|
---|
[88265] | 1900 | * In accordance with the Intel spec.
|
---|
[88153] | 1901 | * @{ */
|
---|
| 1902 | /** IQEI: Invalidation Queue Error Info. */
|
---|
| 1903 | #define VTD_BF_IQERCD_REG_IQEI_SHIFT 0
|
---|
| 1904 | #define VTD_BF_IQERCD_REG_IQEI_MASK UINT64_C(0x000000000000000f)
|
---|
| 1905 | /** R: Reserved (bits 31:4). */
|
---|
| 1906 | #define VTD_BF_IQERCD_REG_RSVD_31_4_SHIFT 4
|
---|
| 1907 | #define VTD_BF_IQERCD_REG_RSVD_31_4_MASK UINT64_C(0x00000000fffffff0)
|
---|
| 1908 | /** ITESID: Invalidation Timeout Error Source Identifier. */
|
---|
| 1909 | #define VTD_BF_IQERCD_REG_ITESID_SHIFT 32
|
---|
| 1910 | #define VTD_BF_IQERCD_REG_ITESID_MASK UINT64_C(0x0000ffff00000000)
|
---|
| 1911 | /** ICESID: Invalidation Completion Error Source Identifier. */
|
---|
| 1912 | #define VTD_BF_IQERCD_REG_ICESID_SHIFT 48
|
---|
| 1913 | #define VTD_BF_IQERCD_REG_ICESID_MASK UINT64_C(0xffff000000000000)
|
---|
| 1914 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IQERCD_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1915 | (IQEI, RSVD_31_4, ITESID, ICESID));
|
---|
[88201] | 1916 |
|
---|
| 1917 | /** RW: Read/write mask. */
|
---|
| 1918 | #define VTD_IQERCD_REG_RW_MASK UINT64_C(0)
|
---|
[88574] | 1919 |
|
---|
| 1920 | /** Invalidation Queue Error Information. */
|
---|
[89201] | 1921 | typedef enum VTDIQEI
|
---|
[88574] | 1922 | {
|
---|
[89201] | 1923 | VTDIQEI_INFO_NOT_AVAILABLE,
|
---|
| 1924 | VTDIQEI_INVALID_TAIL_PTR,
|
---|
| 1925 | VTDIQEI_FETCH_DESCRIPTOR_ERR,
|
---|
| 1926 | VTDIQEI_INVALID_DESCRIPTOR_TYPE,
|
---|
| 1927 | VTDIQEI_RSVD_FIELD_VIOLATION,
|
---|
| 1928 | VTDIQEI_INVALID_DESCRIPTOR_WIDTH,
|
---|
| 1929 | VTDIQEI_QUEUE_TAIL_MISALIGNED,
|
---|
| 1930 | VTDIQEI_INVALID_TTM
|
---|
| 1931 | } VTDIQEI;
|
---|
[88153] | 1932 | /** @} */
|
---|
| 1933 |
|
---|
| 1934 |
|
---|
| 1935 | /** @name Interrupt Remapping Table Address Register (IRTA_REG).
|
---|
[88265] | 1936 | * In accordance with the Intel spec.
|
---|
[88153] | 1937 | * @{ */
|
---|
| 1938 | /** S: Size. */
|
---|
| 1939 | #define VTD_BF_IRTA_REG_S_SHIFT 0
|
---|
| 1940 | #define VTD_BF_IRTA_REG_S_MASK UINT64_C(0x000000000000000f)
|
---|
| 1941 | /** R: Reserved (bits 10:4). */
|
---|
| 1942 | #define VTD_BF_IRTA_REG_RSVD_10_4_SHIFT 4
|
---|
| 1943 | #define VTD_BF_IRTA_REG_RSVD_10_4_MASK UINT64_C(0x00000000000007f0)
|
---|
| 1944 | /** EIME: Extended Interrupt Mode Enable. */
|
---|
| 1945 | #define VTD_BF_IRTA_REG_EIME_SHIFT 11
|
---|
| 1946 | #define VTD_BF_IRTA_REG_EIME_MASK UINT64_C(0x0000000000000800)
|
---|
| 1947 | /** IRTA: Interrupt Remapping Table Address. */
|
---|
| 1948 | #define VTD_BF_IRTA_REG_IRTA_SHIFT 12
|
---|
| 1949 | #define VTD_BF_IRTA_REG_IRTA_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 1950 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_IRTA_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1951 | (S, RSVD_10_4, EIME, IRTA));
|
---|
[88201] | 1952 |
|
---|
| 1953 | /** RW: Read/write mask. */
|
---|
| 1954 | #define VTD_IRTA_REG_RW_MASK ( VTD_BF_IRTA_REG_S_MASK | VTD_BF_IRTA_REG_EIME_MASK \
|
---|
| 1955 | | VTD_BF_IRTA_REG_IRTA_MASK)
|
---|
[88858] | 1956 | /** IRTA_REG: Get number of interrupt entries. */
|
---|
[88894] | 1957 | #define VTD_IRTA_REG_GET_ENTRY_COUNT(a) (UINT32_C(1) << (1 + ((a) & VTD_BF_IRTA_REG_S_MASK)))
|
---|
[88153] | 1958 | /** @} */
|
---|
| 1959 |
|
---|
| 1960 |
|
---|
| 1961 | /** @name Page Request Queue Head Register (PQH_REG).
|
---|
[88265] | 1962 | * In accordance with the Intel spec.
|
---|
[88153] | 1963 | * @{ */
|
---|
| 1964 | /** R: Reserved (bits 4:0). */
|
---|
| 1965 | #define VTD_BF_PQH_REG_RSVD_4_0_SHIFT 0
|
---|
| 1966 | #define VTD_BF_PQH_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
|
---|
| 1967 | /** PQH: Page Queue Head. */
|
---|
| 1968 | #define VTD_BF_PQH_REG_PQH_SHIFT 5
|
---|
| 1969 | #define VTD_BF_PQH_REG_PQH_MASK UINT64_C(0x000000000007ffe0)
|
---|
| 1970 | /** R: Reserved (bits 63:19). */
|
---|
| 1971 | #define VTD_BF_PQH_REG_RSVD_63_19_SHIFT 19
|
---|
| 1972 | #define VTD_BF_PQH_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
|
---|
| 1973 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQH_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1974 | (RSVD_4_0, PQH, RSVD_63_19));
|
---|
[88201] | 1975 |
|
---|
| 1976 | /** RW: Read/write mask. */
|
---|
| 1977 | #define VTD_PQH_REG_RW_MASK VTD_BF_PQH_REG_PQH_MASK
|
---|
[88153] | 1978 | /** @} */
|
---|
| 1979 |
|
---|
| 1980 |
|
---|
| 1981 | /** @name Page Request Queue Tail Register (PQT_REG).
|
---|
[88265] | 1982 | * In accordance with the Intel spec.
|
---|
[88153] | 1983 | * @{ */
|
---|
| 1984 | /** R: Reserved (bits 4:0). */
|
---|
| 1985 | #define VTD_BF_PQT_REG_RSVD_4_0_SHIFT 0
|
---|
| 1986 | #define VTD_BF_PQT_REG_RSVD_4_0_MASK UINT64_C(0x000000000000001f)
|
---|
| 1987 | /** PQT: Page Queue Tail. */
|
---|
| 1988 | #define VTD_BF_PQT_REG_PQT_SHIFT 5
|
---|
| 1989 | #define VTD_BF_PQT_REG_PQT_MASK UINT64_C(0x000000000007ffe0)
|
---|
| 1990 | /** R: Reserved (bits 63:19). */
|
---|
| 1991 | #define VTD_BF_PQT_REG_RSVD_63_19_SHIFT 19
|
---|
| 1992 | #define VTD_BF_PQT_REG_RSVD_63_19_MASK UINT64_C(0xfffffffffff80000)
|
---|
| 1993 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQT_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 1994 | (RSVD_4_0, PQT, RSVD_63_19));
|
---|
[88201] | 1995 |
|
---|
| 1996 | /** RW: Read/write mask. */
|
---|
| 1997 | #define VTD_PQT_REG_RW_MASK VTD_BF_PQT_REG_PQT_MASK
|
---|
[88153] | 1998 | /** @} */
|
---|
| 1999 |
|
---|
| 2000 |
|
---|
| 2001 | /** @name Page Request Queue Address Register (PQA_REG).
|
---|
[88265] | 2002 | * In accordance with the Intel spec.
|
---|
[88153] | 2003 | * @{ */
|
---|
| 2004 | /** PQS: Page Queue Size. */
|
---|
| 2005 | #define VTD_BF_PQA_REG_PQS_SHIFT 0
|
---|
| 2006 | #define VTD_BF_PQA_REG_PQS_MASK UINT64_C(0x0000000000000007)
|
---|
| 2007 | /** R: Reserved bits (11:3). */
|
---|
| 2008 | #define VTD_BF_PQA_REG_RSVD_11_3_SHIFT 3
|
---|
| 2009 | #define VTD_BF_PQA_REG_RSVD_11_3_MASK UINT64_C(0x0000000000000ff8)
|
---|
| 2010 | /** PQA: Page Request Queue Base Address. */
|
---|
| 2011 | #define VTD_BF_PQA_REG_PQA_SHIFT 12
|
---|
| 2012 | #define VTD_BF_PQA_REG_PQA_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2013 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PQA_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 2014 | (PQS, RSVD_11_3, PQA));
|
---|
[88201] | 2015 |
|
---|
| 2016 | /** RW: Read/write mask. */
|
---|
| 2017 | #define VTD_PQA_REG_RW_MASK (VTD_BF_PQA_REG_PQS_MASK | VTD_BF_PQA_REG_PQA_MASK)
|
---|
[88153] | 2018 | /** @} */
|
---|
| 2019 |
|
---|
| 2020 |
|
---|
| 2021 | /** @name Page Request Status Register (PRS_REG).
|
---|
[88265] | 2022 | * In accordance with the Intel spec.
|
---|
[88153] | 2023 | * @{ */
|
---|
| 2024 | /** PPR: Pending Page Request. */
|
---|
| 2025 | #define VTD_BF_PRS_REG_PPR_SHIFT 0
|
---|
| 2026 | #define VTD_BF_PRS_REG_PPR_MASK UINT64_C(0x00000001)
|
---|
| 2027 | /** PRO: Page Request Overflow. */
|
---|
| 2028 | #define VTD_BF_PRS_REG_PRO_SHIFT 1
|
---|
| 2029 | #define VTD_BF_PRS_REG_PRO_MASK UINT64_C(0x00000002)
|
---|
| 2030 | /** R: Reserved (bits 31:2). */
|
---|
| 2031 | #define VTD_BF_PRS_REG_RSVD_31_2_SHIFT 2
|
---|
| 2032 | #define VTD_BF_PRS_REG_RSVD_31_2_MASK UINT64_C(0xfffffffc)
|
---|
| 2033 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PRS_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 2034 | (PPR, PRO, RSVD_31_2));
|
---|
[88201] | 2035 |
|
---|
| 2036 | /** RW: Read/write mask. */
|
---|
| 2037 | #define VTD_PRS_REG_RW_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
|
---|
[88203] | 2038 | /** RW1C: Read-only-status, Write-1-to-clear status mask. */
|
---|
| 2039 | #define VTD_PRS_REG_RW1C_MASK (VTD_BF_PRS_REG_PPR_MASK | VTD_BF_PRS_REG_PRO_MASK)
|
---|
[88153] | 2040 | /** @} */
|
---|
| 2041 |
|
---|
| 2042 |
|
---|
| 2043 | /** @name Page Request Event Control Register (PECTL_REG).
|
---|
[88265] | 2044 | * In accordance with the Intel spec.
|
---|
[88153] | 2045 | * @{ */
|
---|
| 2046 | /** R: Reserved (bits 29:0). */
|
---|
| 2047 | #define VTD_BF_PECTL_REG_RSVD_29_0_SHIFT 0
|
---|
| 2048 | #define VTD_BF_PECTL_REG_RSVD_29_0_MASK UINT32_C(0x3fffffff)
|
---|
| 2049 | /** IP: Interrupt Pending. */
|
---|
| 2050 | #define VTD_BF_PECTL_REG_IP_SHIFT 30
|
---|
| 2051 | #define VTD_BF_PECTL_REG_IP_MASK UINT32_C(0x40000000)
|
---|
| 2052 | /** IM: Interrupt Mask. */
|
---|
| 2053 | #define VTD_BF_PECTL_REG_IM_SHIFT 31
|
---|
| 2054 | #define VTD_BF_PECTL_REG_IM_MASK UINT32_C(0x80000000)
|
---|
| 2055 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PECTL_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 2056 | (RSVD_29_0, IP, IM));
|
---|
[88201] | 2057 |
|
---|
| 2058 | /** RW: Read/write mask. */
|
---|
| 2059 | #define VTD_PECTL_REG_RW_MASK VTD_BF_PECTL_REG_IM_MASK
|
---|
[88153] | 2060 | /** @} */
|
---|
| 2061 |
|
---|
| 2062 |
|
---|
| 2063 | /** @name Page Request Event Data Register (PEDATA_REG).
|
---|
[88265] | 2064 | * In accordance with the Intel spec.
|
---|
[88153] | 2065 | * @{ */
|
---|
| 2066 | /** IMD: Interrupt Message Data. */
|
---|
| 2067 | #define VTD_BF_PEDATA_REG_IMD_SHIFT 0
|
---|
| 2068 | #define VTD_BF_PEDATA_REG_IMD_MASK UINT32_C(0x0000ffff)
|
---|
[88518] | 2069 | /** R: Reserved (bits 31:16). VT-d specs. prior to 2021 had EIMD here. */
|
---|
| 2070 | #define VTD_BF_PEDATA_REG_RSVD_31_16_SHIFT 16
|
---|
| 2071 | #define VTD_BF_PEDATA_REG_RSVD_31_16_MASK UINT32_C(0xffff0000)
|
---|
[88153] | 2072 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEDATA_REG_, UINT32_C(0), UINT32_MAX,
|
---|
[88518] | 2073 | (IMD, RSVD_31_16));
|
---|
[88201] | 2074 |
|
---|
[89001] | 2075 | /** RW: Read/write mask, see 5.1.6 "Remapping Hardware Event Interrupt
|
---|
| 2076 | * Programming". */
|
---|
| 2077 | #define VTD_PEDATA_REG_RW_MASK UINT32_C(0x000001ff)
|
---|
[88153] | 2078 | /** @} */
|
---|
| 2079 |
|
---|
| 2080 |
|
---|
| 2081 | /** @name Page Request Event Address Register (PEADDR_REG).
|
---|
[88265] | 2082 | * In accordance with the Intel spec.
|
---|
[88153] | 2083 | * @{ */
|
---|
| 2084 | /** R: Reserved (bits 1:0). */
|
---|
| 2085 | #define VTD_BF_PEADDR_REG_RSVD_1_0_SHIFT 0
|
---|
| 2086 | #define VTD_BF_PEADDR_REG_RSVD_1_0_MASK UINT32_C(0x00000003)
|
---|
| 2087 | /** MA: Message Address. */
|
---|
| 2088 | #define VTD_BF_PEADDR_REG_MA_SHIFT 2
|
---|
| 2089 | #define VTD_BF_PEADDR_REG_MA_MASK UINT32_C(0xfffffffc)
|
---|
| 2090 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_PEADDR_REG_, UINT32_C(0), UINT32_MAX,
|
---|
| 2091 | (RSVD_1_0, MA));
|
---|
[88201] | 2092 |
|
---|
| 2093 | /** RW: Read/write mask. */
|
---|
| 2094 | #define VTD_PEADDR_REG_RW_MASK VTD_BF_PEADDR_REG_MA_MASK
|
---|
[88153] | 2095 | /** @} */
|
---|
| 2096 |
|
---|
| 2097 |
|
---|
[88201] | 2098 |
|
---|
| 2099 | /** @name Page Request Event Upper Address Register (PEUADDR_REG).
|
---|
[88265] | 2100 | * In accordance with the Intel spec.
|
---|
[88201] | 2101 | * @{ */
|
---|
| 2102 | /** MA: Message Address. */
|
---|
| 2103 | #define VTD_BF_PEUADDR_REG_MUA_SHIFT 0
|
---|
| 2104 | #define VTD_BF_PEUADDR_REG_MUA_MASK UINT32_C(0xffffffff)
|
---|
| 2105 |
|
---|
| 2106 | /** RW: Read/write mask. */
|
---|
| 2107 | #define VTD_PEUADDR_REG_RW_MASK VTD_BF_PEUADDR_REG_MUA_MASK
|
---|
| 2108 | /** @} */
|
---|
| 2109 |
|
---|
| 2110 |
|
---|
| 2111 | /** @name MTRR Capability Register (MTRRCAP_REG).
|
---|
[88265] | 2112 | * In accordance with the Intel spec.
|
---|
[88201] | 2113 | * @{ */
|
---|
| 2114 | /** VCNT: Variable MTRR Count. */
|
---|
| 2115 | #define VTD_BF_MTRRCAP_REG_VCNT_SHIFT 0
|
---|
| 2116 | #define VTD_BF_MTRRCAP_REG_VCNT_MASK UINT64_C(0x00000000000000ff)
|
---|
| 2117 | /** FIX: Fixed range MTRRs Supported. */
|
---|
| 2118 | #define VTD_BF_MTRRCAP_REG_FIX_SHIFT 8
|
---|
| 2119 | #define VTD_BF_MTRRCAP_REG_FIX_MASK UINT64_C(0x0000000000000100)
|
---|
| 2120 | /** R: Reserved (bit 9). */
|
---|
| 2121 | #define VTD_BF_MTRRCAP_REG_RSVD_9_SHIFT 9
|
---|
| 2122 | #define VTD_BF_MTRRCAP_REG_RSVD_9_MASK UINT64_C(0x0000000000000200)
|
---|
| 2123 | /** WC: Write Combining. */
|
---|
| 2124 | #define VTD_BF_MTRRCAP_REG_WC_SHIFT 10
|
---|
| 2125 | #define VTD_BF_MTRRCAP_REG_WC_MASK UINT64_C(0x0000000000000400)
|
---|
| 2126 | /** R: Reserved (bits 63:11). */
|
---|
| 2127 | #define VTD_BF_MTRRCAP_REG_RSVD_63_11_SHIFT 11
|
---|
| 2128 | #define VTD_BF_MTRRCAP_REG_RSVD_63_11_MASK UINT64_C(0xfffffffffffff800)
|
---|
| 2129 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRCAP_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 2130 | (VCNT, FIX, RSVD_9, WC, RSVD_63_11));
|
---|
| 2131 |
|
---|
| 2132 | /** RW: Read/write mask. */
|
---|
| 2133 | #define VTD_MTRRCAP_REG_RW_MASK UINT64_C(0)
|
---|
| 2134 | /** @} */
|
---|
| 2135 |
|
---|
| 2136 |
|
---|
[88153] | 2137 | /** @name MTRR Default Type Register (MTRRDEF_REG).
|
---|
[88265] | 2138 | * In accordance with the Intel spec.
|
---|
[88153] | 2139 | * @{ */
|
---|
| 2140 | /** TYPE: Default Memory Type. */
|
---|
| 2141 | #define VTD_BF_MTRRDEF_REG_TYPE_SHIFT 0
|
---|
| 2142 | #define VTD_BF_MTRRDEF_REG_TYPE_MASK UINT64_C(0x00000000000000ff)
|
---|
| 2143 | /** R: Reserved (bits 9:8). */
|
---|
| 2144 | #define VTD_BF_MTRRDEF_REG_RSVD_9_8_SHIFT 8
|
---|
| 2145 | #define VTD_BF_MTRRDEF_REG_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
|
---|
| 2146 | /** FE: Fixed Range MTRR Enable. */
|
---|
| 2147 | #define VTD_BF_MTRRDEF_REG_FE_SHIFT 10
|
---|
| 2148 | #define VTD_BF_MTRRDEF_REG_FE_MASK UINT64_C(0x0000000000000400)
|
---|
| 2149 | /** E: MTRR Enable. */
|
---|
| 2150 | #define VTD_BF_MTRRDEF_REG_E_SHIFT 11
|
---|
| 2151 | #define VTD_BF_MTRRDEF_REG_E_MASK UINT64_C(0x0000000000000800)
|
---|
| 2152 | /** R: Reserved (bits 63:12). */
|
---|
| 2153 | #define VTD_BF_MTRRDEF_REG_RSVD_63_12_SHIFT 12
|
---|
| 2154 | #define VTD_BF_MTRRDEF_REG_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2155 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_MTRRDEF_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 2156 | (TYPE, RSVD_9_8, FE, E, RSVD_63_12));
|
---|
[88201] | 2157 |
|
---|
| 2158 | /** RW: Read/write mask. */
|
---|
| 2159 | #define VTD_MTRRDEF_REG_RW_MASK ( VTD_BF_MTRRDEF_REG_TYPE_MASK | VTD_BF_MTRRDEF_REG_FE_MASK \
|
---|
| 2160 | | VTD_BF_MTRRDEF_REG_E_MASK)
|
---|
[88153] | 2161 | /** @} */
|
---|
| 2162 |
|
---|
| 2163 |
|
---|
| 2164 | /** @name Virtual Command Capability Register (VCCAP_REG).
|
---|
[88265] | 2165 | * In accordance with the Intel spec.
|
---|
[88153] | 2166 | * @{ */
|
---|
| 2167 | /** PAS: PASID Support. */
|
---|
| 2168 | #define VTD_BF_VCCAP_REG_PAS_SHIFT 0
|
---|
| 2169 | #define VTD_BF_VCCAP_REG_PAS_MASK UINT64_C(0x0000000000000001)
|
---|
| 2170 | /** R: Reserved (bits 63:1). */
|
---|
| 2171 | #define VTD_BF_VCCAP_REG_RSVD_63_1_SHIFT 1
|
---|
| 2172 | #define VTD_BF_VCCAP_REG_RSVD_63_1_MASK UINT64_C(0xfffffffffffffffe)
|
---|
| 2173 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCCAP_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 2174 | (PAS, RSVD_63_1));
|
---|
[88201] | 2175 |
|
---|
| 2176 | /** RW: Read/write mask. */
|
---|
| 2177 | #define VTD_VCCAP_REG_RW_MASK UINT64_C(0)
|
---|
[88153] | 2178 | /** @} */
|
---|
| 2179 |
|
---|
| 2180 |
|
---|
[88515] | 2181 | /** @name Virtual Command Extended Operand Register (VCMD_EO_REG).
|
---|
| 2182 | * In accordance with the Intel spec.
|
---|
| 2183 | * @{ */
|
---|
| 2184 | /** OB: Operand B. */
|
---|
| 2185 | #define VTD_BF_VCMD_EO_REG_OB_SHIFT 0
|
---|
| 2186 | #define VTD_BF_VCMD_EO_REG_OB_MASK UINT32_C(0xffffffffffffffff)
|
---|
| 2187 |
|
---|
| 2188 | /** RW: Read/write mask. */
|
---|
| 2189 | #define VTD_VCMD_EO_REG_RW_MASK VTD_BF_VCMD_EO_REG_OB_MASK
|
---|
| 2190 | /** @} */
|
---|
| 2191 |
|
---|
| 2192 |
|
---|
[88153] | 2193 | /** @name Virtual Command Register (VCMD_REG).
|
---|
[88265] | 2194 | * In accordance with the Intel spec.
|
---|
[88153] | 2195 | * @{ */
|
---|
| 2196 | /** CMD: Command. */
|
---|
| 2197 | #define VTD_BF_VCMD_REG_CMD_SHIFT 0
|
---|
| 2198 | #define VTD_BF_VCMD_REG_CMD_MASK UINT64_C(0x00000000000000ff)
|
---|
| 2199 | /** OP: Operand. */
|
---|
| 2200 | #define VTD_BF_VCMD_REG_OP_SHIFT 8
|
---|
[88174] | 2201 | #define VTD_BF_VCMD_REG_OP_MASK UINT64_C(0xffffffffffffff00)
|
---|
[88153] | 2202 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCMD_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 2203 | (CMD, OP));
|
---|
[88201] | 2204 |
|
---|
| 2205 | /** RW: Read/write mask. */
|
---|
| 2206 | #define VTD_VCMD_REG_RW_MASK (VTD_BF_VCMD_REG_CMD_MASK | VTD_BF_VCMD_REG_OP_MASK)
|
---|
[88153] | 2207 | /** @} */
|
---|
| 2208 |
|
---|
| 2209 |
|
---|
[88201] | 2210 | /** @name Virtual Command Response Register (VCRSP_REG).
|
---|
[88265] | 2211 | * In accordance with the Intel spec.
|
---|
[88153] | 2212 | * @{ */
|
---|
| 2213 | /** IP: In Progress. */
|
---|
| 2214 | #define VTD_BF_VCRSP_REG_IP_SHIFT 0
|
---|
| 2215 | #define VTD_BF_VCRSP_REG_IP_MASK UINT64_C(0x0000000000000001)
|
---|
| 2216 | /** SC: Status Code. */
|
---|
| 2217 | #define VTD_BF_VCRSP_REG_SC_SHIFT 1
|
---|
| 2218 | #define VTD_BF_VCRSP_REG_SC_MASK UINT64_C(0x0000000000000006)
|
---|
| 2219 | /** R: Reserved (bits 7:3). */
|
---|
| 2220 | #define VTD_BF_VCRSP_REG_RSVD_7_3_SHIFT 3
|
---|
| 2221 | #define VTD_BF_VCRSP_REG_RSVD_7_3_MASK UINT64_C(0x00000000000000f8)
|
---|
| 2222 | /** RSLT: Result. */
|
---|
| 2223 | #define VTD_BF_VCRSP_REG_RSLT_SHIFT 8
|
---|
| 2224 | #define VTD_BF_VCRSP_REG_RSLT_MASK UINT64_C(0xffffffffffffff00)
|
---|
| 2225 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_VCRSP_REG_, UINT64_C(0), UINT64_MAX,
|
---|
| 2226 | (IP, SC, RSVD_7_3, RSLT));
|
---|
[88201] | 2227 |
|
---|
| 2228 | /** RW: Read/write mask. */
|
---|
| 2229 | #define VTD_VCRSP_REG_RW_MASK UINT64_C(0)
|
---|
[88153] | 2230 | /** @} */
|
---|
| 2231 |
|
---|
| 2232 |
|
---|
[88744] | 2233 | /** @name Generic Invalidation Descriptor.
|
---|
[88764] | 2234 | * In accordance with the Intel spec.
|
---|
| 2235 | * Non-reserved fields here are common to all invalidation descriptors.
|
---|
[88744] | 2236 | * @{ */
|
---|
| 2237 | /** Type (Lo). */
|
---|
| 2238 | #define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2239 | #define VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2240 | /** R: Reserved (bits 8:4). */
|
---|
| 2241 | #define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_SHIFT 4
|
---|
| 2242 | #define VTD_BF_0_GENERIC_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
|
---|
| 2243 | /** Type (Hi). */
|
---|
| 2244 | #define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2245 | #define VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2246 | /** R: Reserved (bits 63:12). */
|
---|
| 2247 | #define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_SHIFT 12
|
---|
| 2248 | #define VTD_BF_0_GENERIC_INV_DSC_RSVD_63_12_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2249 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_GENERIC_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2250 | (TYPE_LO, RSVD_8_4, TYPE_HI, RSVD_63_12));
|
---|
| 2251 |
|
---|
| 2252 | /** GENERIC_INV_DSC: Type. */
|
---|
| 2253 | #define VTD_GENERIC_INV_DSC_GET_TYPE(a) ((((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_HI_MASK) >> 5) \
|
---|
| 2254 | | ((a) & VTD_BF_0_GENERIC_INV_DSC_TYPE_LO_MASK))
|
---|
| 2255 | /** @} */
|
---|
| 2256 |
|
---|
| 2257 |
|
---|
[88696] | 2258 | /** @name Context-Cache Invalidation Descriptor (cc_inv_dsc).
|
---|
| 2259 | * In accordance with the Intel spec.
|
---|
| 2260 | * @{ */
|
---|
| 2261 | /** Type (Lo). */
|
---|
| 2262 | #define VTD_BF_0_CC_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2263 | #define VTD_BF_0_CC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2264 | /** G: Granularity. */
|
---|
| 2265 | #define VTD_BF_0_CC_INV_DSC_G_SHIFT 4
|
---|
| 2266 | #define VTD_BF_0_CC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
|
---|
| 2267 | /** R: Reserved (bits 8:6). */
|
---|
| 2268 | #define VTD_BF_0_CC_INV_DSC_RSVD_8_6_SHIFT 6
|
---|
| 2269 | #define VTD_BF_0_CC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
|
---|
| 2270 | /** Type (Hi). */
|
---|
| 2271 | #define VTD_BF_0_CC_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2272 | #define VTD_BF_0_CC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2273 | /** R: Reserved (bits 15:12). */
|
---|
| 2274 | #define VTD_BF_0_CC_INV_DSC_RSVD_15_12_SHIFT 12
|
---|
| 2275 | #define VTD_BF_0_CC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
|
---|
| 2276 | /** DID: Domain Id. */
|
---|
| 2277 | #define VTD_BF_0_CC_INV_DSC_DID_SHIFT 16
|
---|
| 2278 | #define VTD_BF_0_CC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
|
---|
| 2279 | /** SID: Source Id. */
|
---|
| 2280 | #define VTD_BF_0_CC_INV_DSC_SID_SHIFT 32
|
---|
| 2281 | #define VTD_BF_0_CC_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
|
---|
| 2282 | /** FM: Function Mask. */
|
---|
| 2283 | #define VTD_BF_0_CC_INV_DSC_FM_SHIFT 48
|
---|
| 2284 | #define VTD_BF_0_CC_INV_DSC_FM_MASK UINT64_C(0x0003000000000000)
|
---|
| 2285 | /** R: Reserved (bits 63:50). */
|
---|
| 2286 | #define VTD_BF_0_CC_INV_DSC_RSVD_63_50_SHIFT 50
|
---|
| 2287 | #define VTD_BF_0_CC_INV_DSC_RSVD_63_50_MASK UINT64_C(0xfffc000000000000)
|
---|
| 2288 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_CC_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2289 | (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, SID, FM, RSVD_63_50));
|
---|
| 2290 | /** @} */
|
---|
| 2291 |
|
---|
| 2292 |
|
---|
| 2293 | /** @name PASID-Cache Invalidation Descriptor (pc_inv_dsc).
|
---|
| 2294 | * In accordance with the Intel spec.
|
---|
| 2295 | * @{ */
|
---|
| 2296 | /** Type (Lo). */
|
---|
| 2297 | #define VTD_BF_0_PC_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2298 | #define VTD_BF_0_PC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2299 | /** G: Granularity. */
|
---|
| 2300 | #define VTD_BF_0_PC_INV_DSC_G_SHIFT 4
|
---|
| 2301 | #define VTD_BF_0_PC_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
|
---|
| 2302 | /** R: Reserved (bits 8:6). */
|
---|
| 2303 | #define VTD_BF_0_PC_INV_DSC_RSVD_8_6_SHIFT 6
|
---|
| 2304 | #define VTD_BF_0_PC_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
|
---|
| 2305 | /** Type (Hi). */
|
---|
| 2306 | #define VTD_BF_0_PC_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2307 | #define VTD_BF_0_PC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2308 | /** R: Reserved (bits 15:12). */
|
---|
| 2309 | #define VTD_BF_0_PC_INV_DSC_RSVD_15_12_SHIFT 12
|
---|
| 2310 | #define VTD_BF_0_PC_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
|
---|
| 2311 | /** DID: Domain Id. */
|
---|
| 2312 | #define VTD_BF_0_PC_INV_DSC_DID_SHIFT 16
|
---|
| 2313 | #define VTD_BF_0_PC_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
|
---|
| 2314 | /** PASID: Process Address-Space Id. */
|
---|
| 2315 | #define VTD_BF_0_PC_INV_DSC_PASID_SHIFT 32
|
---|
| 2316 | #define VTD_BF_0_PC_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
|
---|
| 2317 | /** R: Reserved (bits 63:52). */
|
---|
| 2318 | #define VTD_BF_0_PC_INV_DSC_RSVD_63_52_SHIFT 52
|
---|
| 2319 | #define VTD_BF_0_PC_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
|
---|
| 2320 |
|
---|
| 2321 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_PC_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2322 | (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
|
---|
| 2323 | /** @} */
|
---|
| 2324 |
|
---|
| 2325 |
|
---|
| 2326 | /** @name IOTLB Invalidate Descriptor (iotlb_inv_dsc).
|
---|
| 2327 | * In accordance with the Intel spec.
|
---|
| 2328 | * @{ */
|
---|
| 2329 | /** Type (Lo). */
|
---|
| 2330 | #define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2331 | #define VTD_BF_0_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2332 | /** G: Granularity. */
|
---|
| 2333 | #define VTD_BF_0_IOTLB_INV_DSC_G_SHIFT 4
|
---|
| 2334 | #define VTD_BF_0_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
|
---|
| 2335 | /** DW: Drain Writes. */
|
---|
| 2336 | #define VTD_BF_0_IOTLB_INV_DSC_DW_SHIFT 6
|
---|
| 2337 | #define VTD_BF_0_IOTLB_INV_DSC_DW_MASK UINT64_C(0x0000000000000040)
|
---|
| 2338 | /** DR: Drain Reads. */
|
---|
| 2339 | #define VTD_BF_0_IOTLB_INV_DSC_DR_SHIFT 7
|
---|
| 2340 | #define VTD_BF_0_IOTLB_INV_DSC_DR_MASK UINT64_C(0x0000000000000080)
|
---|
| 2341 | /** R: Reserved (bit 8). */
|
---|
| 2342 | #define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_SHIFT 8
|
---|
| 2343 | #define VTD_BF_0_IOTLB_INV_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
|
---|
| 2344 | /** Type (Hi). */
|
---|
| 2345 | #define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2346 | #define VTD_BF_0_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2347 | /** R: Reserved (bits 15:12). */
|
---|
| 2348 | #define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
|
---|
| 2349 | #define VTD_BF_0_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
|
---|
| 2350 | /** DID: Domain Id. */
|
---|
| 2351 | #define VTD_BF_0_IOTLB_INV_DSC_DID_SHIFT 16
|
---|
| 2352 | #define VTD_BF_0_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
|
---|
[88698] | 2353 | /** R: Reserved (bits 63:32). */
|
---|
[88696] | 2354 | #define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_SHIFT 32
|
---|
| 2355 | #define VTD_BF_0_IOTLB_INV_DSC_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
|
---|
| 2356 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2357 | (TYPE_LO, G, DW, DR, RSVD_8, TYPE_HI, RSVD_15_12, DID, RSVD_63_32));
|
---|
| 2358 |
|
---|
| 2359 | /** AM: Address Mask. */
|
---|
| 2360 | #define VTD_BF_1_IOTLB_INV_DSC_AM_SHIFT 0
|
---|
| 2361 | #define VTD_BF_1_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
|
---|
| 2362 | /** IH: Invalidation Hint. */
|
---|
| 2363 | #define VTD_BF_1_IOTLB_INV_DSC_IH_SHIFT 6
|
---|
| 2364 | #define VTD_BF_1_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
|
---|
| 2365 | /** R: Reserved (bits 11:7). */
|
---|
| 2366 | #define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
|
---|
| 2367 | #define VTD_BF_1_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
|
---|
| 2368 | /** ADDR: Address. */
|
---|
| 2369 | #define VTD_BF_1_IOTLB_INV_DSC_ADDR_SHIFT 12
|
---|
| 2370 | #define VTD_BF_1_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2371 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2372 | (AM, IH, RSVD_11_7, ADDR));
|
---|
| 2373 | /** @} */
|
---|
| 2374 |
|
---|
| 2375 |
|
---|
| 2376 | /** @name PASID-based IOTLB Invalidate Descriptor (p_iotlb_inv_dsc).
|
---|
| 2377 | * In accordance with the Intel spec.
|
---|
| 2378 | * @{ */
|
---|
| 2379 | /** Type (Lo). */
|
---|
| 2380 | #define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2381 | #define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2382 | /** G: Granularity. */
|
---|
| 2383 | #define VTD_BF_0_P_IOTLB_INV_DSC_G_SHIFT 4
|
---|
| 2384 | #define VTD_BF_0_P_IOTLB_INV_DSC_G_MASK UINT64_C(0x0000000000000030)
|
---|
| 2385 | /** R: Reserved (bits 8:6). */
|
---|
| 2386 | #define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_SHIFT 6
|
---|
| 2387 | #define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_8_6_MASK UINT64_C(0x00000000000001c0)
|
---|
| 2388 | /** Type (Hi). */
|
---|
| 2389 | #define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2390 | #define VTD_BF_0_P_IOTLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2391 | /** R: Reserved (bits 15:12). */
|
---|
| 2392 | #define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_SHIFT 12
|
---|
| 2393 | #define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
|
---|
| 2394 | /** DID: Domain Id. */
|
---|
| 2395 | #define VTD_BF_0_P_IOTLB_INV_DSC_DID_SHIFT 16
|
---|
| 2396 | #define VTD_BF_0_P_IOTLB_INV_DSC_DID_MASK UINT64_C(0x00000000ffff0000)
|
---|
| 2397 | /** PASID: Process Address-Space Id. */
|
---|
| 2398 | #define VTD_BF_0_P_IOTLB_INV_DSC_PASID_SHIFT 32
|
---|
| 2399 | #define VTD_BF_0_P_IOTLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
|
---|
| 2400 | /** R: Reserved (bits 63:52). */
|
---|
| 2401 | #define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_SHIFT 52
|
---|
| 2402 | #define VTD_BF_0_P_IOTLB_INV_DSC_RSVD_63_52_MASK UINT64_C(0xfff0000000000000)
|
---|
| 2403 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2404 | (TYPE_LO, G, RSVD_8_6, TYPE_HI, RSVD_15_12, DID, PASID, RSVD_63_52));
|
---|
| 2405 |
|
---|
| 2406 |
|
---|
| 2407 | /** AM: Address Mask. */
|
---|
| 2408 | #define VTD_BF_1_P_IOTLB_INV_DSC_AM_SHIFT 0
|
---|
| 2409 | #define VTD_BF_1_P_IOTLB_INV_DSC_AM_MASK UINT64_C(0x000000000000003f)
|
---|
| 2410 | /** IH: Invalidation Hint. */
|
---|
| 2411 | #define VTD_BF_1_P_IOTLB_INV_DSC_IH_SHIFT 6
|
---|
| 2412 | #define VTD_BF_1_P_IOTLB_INV_DSC_IH_MASK UINT64_C(0x0000000000000040)
|
---|
| 2413 | /** R: Reserved (bits 11:7). */
|
---|
| 2414 | #define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_SHIFT 7
|
---|
| 2415 | #define VTD_BF_1_P_IOTLB_INV_DSC_RSVD_11_7_MASK UINT64_C(0x0000000000000f80)
|
---|
| 2416 | /** ADDR: Address. */
|
---|
| 2417 | #define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_SHIFT 12
|
---|
| 2418 | #define VTD_BF_1_P_IOTLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2419 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_IOTLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2420 | (AM, IH, RSVD_11_7, ADDR));
|
---|
| 2421 | /** @} */
|
---|
| 2422 |
|
---|
| 2423 |
|
---|
| 2424 | /** @name Device-TLB Invalidate Descriptor (dev_tlb_inv_dsc).
|
---|
| 2425 | * In accordance with the Intel spec.
|
---|
| 2426 | * @{ */
|
---|
| 2427 | /** Type (Lo). */
|
---|
| 2428 | #define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2429 | #define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2430 | /** R: Reserved (bits 8:4). */
|
---|
| 2431 | #define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_SHIFT 4
|
---|
| 2432 | #define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_8_4_MASK UINT64_C(0x00000000000001f0)
|
---|
| 2433 | /** Type (Hi). */
|
---|
| 2434 | #define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2435 | #define VTD_BF_0_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2436 | /** PFSID: Physical-Function Source Id (Lo). */
|
---|
| 2437 | #define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
|
---|
| 2438 | #define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
|
---|
| 2439 | /** MIP: Max Invalidations Pending. */
|
---|
| 2440 | #define VTD_BF_0_DEV_TLB_INV_DSC_MIP_SHIFT 16
|
---|
| 2441 | #define VTD_BF_0_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000001f0000)
|
---|
| 2442 | /** R: Reserved (bits 31:21). */
|
---|
| 2443 | #define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_SHIFT 21
|
---|
| 2444 | #define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_31_21_MASK UINT64_C(0x00000000ffe00000)
|
---|
| 2445 | /** SID: Source Id. */
|
---|
| 2446 | #define VTD_BF_0_DEV_TLB_INV_DSC_SID_SHIFT 32
|
---|
| 2447 | #define VTD_BF_0_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x0000ffff00000000)
|
---|
| 2448 | /** R: Reserved (bits 51:48). */
|
---|
| 2449 | #define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_SHIFT 48
|
---|
| 2450 | #define VTD_BF_0_DEV_TLB_INV_DSC_RSVD_51_48_MASK UINT64_C(0x000f000000000000)
|
---|
| 2451 | /** PFSID: Physical-Function Source Id (Hi). */
|
---|
| 2452 | #define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
|
---|
| 2453 | #define VTD_BF_0_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
|
---|
| 2454 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2455 | (TYPE_LO, RSVD_8_4, TYPE_HI, PFSID_LO, MIP, RSVD_31_21, SID, RSVD_51_48, PFSID_HI));
|
---|
| 2456 |
|
---|
| 2457 | /** S: Size. */
|
---|
| 2458 | #define VTD_BF_1_DEV_TLB_INV_DSC_S_SHIFT 0
|
---|
| 2459 | #define VTD_BF_1_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000001)
|
---|
| 2460 | /** R: Reserved (bits 11:1). */
|
---|
| 2461 | #define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_SHIFT 1
|
---|
| 2462 | #define VTD_BF_1_DEV_TLB_INV_DSC_RSVD_11_1_MASK UINT64_C(0x0000000000000ffe)
|
---|
| 2463 | /** ADDR: Address. */
|
---|
| 2464 | #define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_SHIFT 12
|
---|
| 2465 | #define VTD_BF_1_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2466 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2467 | (S, RSVD_11_1, ADDR));
|
---|
| 2468 | /** @} */
|
---|
| 2469 |
|
---|
| 2470 |
|
---|
| 2471 | /** @name PASID-based-device-TLB Invalidate Descriptor (p_dev_tlb_inv_dsc).
|
---|
| 2472 | * In accordance with the Intel spec.
|
---|
| 2473 | * @{ */
|
---|
| 2474 | /** Type (Lo). */
|
---|
| 2475 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2476 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2477 | /** MIP: Max Invalidations Pending. */
|
---|
| 2478 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_SHIFT 4
|
---|
| 2479 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_MIP_MASK UINT64_C(0x00000000000001f0)
|
---|
| 2480 | /** Type (Hi). */
|
---|
| 2481 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2482 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2483 | /** PFSID: Physical-Function Source Id (Lo). */
|
---|
| 2484 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_SHIFT 12
|
---|
| 2485 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_LO_MASK UINT64_C(0x000000000000f000)
|
---|
| 2486 | /** SID: Source Id. */
|
---|
| 2487 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_SHIFT 16
|
---|
| 2488 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_SID_MASK UINT64_C(0x00000000ffff0000)
|
---|
| 2489 | /** PASID: Process Address-Space Id. */
|
---|
| 2490 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_SHIFT 32
|
---|
| 2491 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_PASID_MASK UINT64_C(0x000fffff00000000)
|
---|
| 2492 | /** PFSID: Physical-Function Source Id (Hi). */
|
---|
| 2493 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_SHIFT 52
|
---|
| 2494 | #define VTD_BF_0_P_DEV_TLB_INV_DSC_PFSID_HI_MASK UINT64_C(0xfff0000000000000)
|
---|
| 2495 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2496 | (TYPE_LO, MIP, TYPE_HI, PFSID_LO, SID, PASID, PFSID_HI));
|
---|
| 2497 |
|
---|
| 2498 | /** G: Granularity. */
|
---|
| 2499 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_G_SHIFT 0
|
---|
| 2500 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_G_MASK UINT64_C(0x0000000000000001)
|
---|
| 2501 | /** R: Reserved (bits 10:1). */
|
---|
| 2502 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_SHIFT 1
|
---|
| 2503 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_RSVD_10_1_MASK UINT64_C(0x00000000000007fe)
|
---|
| 2504 | /** S: Size. */
|
---|
| 2505 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_S_SHIFT 11
|
---|
| 2506 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_S_MASK UINT64_C(0x0000000000000800)
|
---|
| 2507 | /** ADDR: Address. */
|
---|
| 2508 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_SHIFT 12
|
---|
| 2509 | #define VTD_BF_1_P_DEV_TLB_INV_DSC_ADDR_MASK UINT64_C(0xfffffffffffff000)
|
---|
| 2510 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_P_DEV_TLB_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2511 | (G, RSVD_10_1, S, ADDR));
|
---|
| 2512 | /** @} */
|
---|
| 2513 |
|
---|
| 2514 |
|
---|
| 2515 | /** @name Interrupt Entry Cache Invalidate Descriptor (iec_inv_dsc).
|
---|
| 2516 | * In accordance with the Intel spec.
|
---|
| 2517 | * @{ */
|
---|
| 2518 | /** Type (Lo). */
|
---|
| 2519 | #define VTD_BF_0_IEC_INV_DSC_TYPE_LO_SHIFT 0
|
---|
| 2520 | #define VTD_BF_0_IEC_INV_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2521 | /** G: Granularity. */
|
---|
| 2522 | #define VTD_BF_0_IEC_INV_DSC_G_SHIFT 4
|
---|
| 2523 | #define VTD_BF_0_IEC_INV_DSC_G_MASK UINT64_C(0x0000000000000010)
|
---|
| 2524 | /** R: Reserved (bits 8:5). */
|
---|
| 2525 | #define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_SHIFT 5
|
---|
| 2526 | #define VTD_BF_0_IEC_INV_DSC_RSVD_8_5_MASK UINT64_C(0x00000000000001e0)
|
---|
| 2527 | /** Type (Hi). */
|
---|
| 2528 | #define VTD_BF_0_IEC_INV_DSC_TYPE_HI_SHIFT 9
|
---|
| 2529 | #define VTD_BF_0_IEC_INV_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2530 | /** R: Reserved (bits 26:12). */
|
---|
| 2531 | #define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_SHIFT 12
|
---|
| 2532 | #define VTD_BF_0_IEC_INV_DSC_RSVD_26_12_MASK UINT64_C(0x0000000007fff000)
|
---|
| 2533 | /** IM: Index Mask. */
|
---|
| 2534 | #define VTD_BF_0_IEC_INV_DSC_IM_SHIFT 27
|
---|
| 2535 | #define VTD_BF_0_IEC_INV_DSC_IM_MASK UINT64_C(0x00000000f8000000)
|
---|
| 2536 | /** IIDX: Interrupt Index. */
|
---|
| 2537 | #define VTD_BF_0_IEC_INV_DSC_IIDX_SHIFT 32
|
---|
| 2538 | #define VTD_BF_0_IEC_INV_DSC_IIDX_MASK UINT64_C(0x0000ffff00000000)
|
---|
| 2539 | /** R: Reserved (bits 63:48). */
|
---|
| 2540 | #define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_SHIFT 48
|
---|
| 2541 | #define VTD_BF_0_IEC_INV_DSC_RSVD_63_48_MASK UINT64_C(0xffff000000000000)
|
---|
| 2542 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_IEC_INV_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2543 | (TYPE_LO, G, RSVD_8_5, TYPE_HI, RSVD_26_12, IM, IIDX, RSVD_63_48));
|
---|
| 2544 | /** @} */
|
---|
| 2545 |
|
---|
| 2546 |
|
---|
| 2547 | /** @name Invalidation Wait Descriptor (inv_wait_dsc).
|
---|
| 2548 | * In accordance with the Intel spec.
|
---|
| 2549 | * @{ */
|
---|
| 2550 | /** Type (Lo). */
|
---|
| 2551 | #define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_SHIFT 0
|
---|
| 2552 | #define VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK UINT64_C(0x000000000000000f)
|
---|
| 2553 | /** IF: Interrupt Flag. */
|
---|
| 2554 | #define VTD_BF_0_INV_WAIT_DSC_IF_SHIFT 4
|
---|
| 2555 | #define VTD_BF_0_INV_WAIT_DSC_IF_MASK UINT64_C(0x0000000000000010)
|
---|
| 2556 | /** SW: Status Write. */
|
---|
| 2557 | #define VTD_BF_0_INV_WAIT_DSC_SW_SHIFT 5
|
---|
| 2558 | #define VTD_BF_0_INV_WAIT_DSC_SW_MASK UINT64_C(0x0000000000000020)
|
---|
| 2559 | /** FN: Fence Flag. */
|
---|
| 2560 | #define VTD_BF_0_INV_WAIT_DSC_FN_SHIFT 6
|
---|
| 2561 | #define VTD_BF_0_INV_WAIT_DSC_FN_MASK UINT64_C(0x0000000000000040)
|
---|
| 2562 | /** PD: Page-Request Drain. */
|
---|
| 2563 | #define VTD_BF_0_INV_WAIT_DSC_PD_SHIFT 7
|
---|
| 2564 | #define VTD_BF_0_INV_WAIT_DSC_PD_MASK UINT64_C(0x0000000000000080)
|
---|
| 2565 | /** R: Reserved (bit 8). */
|
---|
| 2566 | #define VTD_BF_0_INV_WAIT_DSC_RSVD_8_SHIFT 8
|
---|
| 2567 | #define VTD_BF_0_INV_WAIT_DSC_RSVD_8_MASK UINT64_C(0x0000000000000100)
|
---|
| 2568 | /** Type (Hi). */
|
---|
| 2569 | #define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_SHIFT 9
|
---|
| 2570 | #define VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK UINT64_C(0x0000000000000e00)
|
---|
| 2571 | /** R: Reserved (bits 31:12). */
|
---|
| 2572 | #define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_SHIFT 12
|
---|
| 2573 | #define VTD_BF_0_INV_WAIT_DSC_RSVD_31_12_MASK UINT64_C(0x00000000fffff000)
|
---|
| 2574 | /** STDATA: Status Data. */
|
---|
| 2575 | #define VTD_BF_0_INV_WAIT_DSC_STDATA_SHIFT 32
|
---|
| 2576 | #define VTD_BF_0_INV_WAIT_DSC_STDATA_MASK UINT64_C(0xffffffff00000000)
|
---|
| 2577 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_0_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2578 | (TYPE_LO, IF, SW, FN, PD, RSVD_8, TYPE_HI, RSVD_31_12, STDATA));
|
---|
| 2579 |
|
---|
| 2580 | /** R: Reserved (bits 1:0). */
|
---|
| 2581 | #define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_SHIFT 0
|
---|
| 2582 | #define VTD_BF_1_INV_WAIT_DSC_RSVD_1_0_MASK UINT64_C(0x0000000000000003)
|
---|
| 2583 | /** STADDR: Status Address. */
|
---|
| 2584 | #define VTD_BF_1_INV_WAIT_DSC_STADDR_SHIFT 2
|
---|
| 2585 | #define VTD_BF_1_INV_WAIT_DSC_STADDR_MASK UINT64_C(0xfffffffffffffffc)
|
---|
| 2586 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_1_INV_WAIT_DSC_, UINT64_C(0), UINT64_MAX,
|
---|
| 2587 | (RSVD_1_0, STADDR));
|
---|
[88781] | 2588 |
|
---|
| 2589 | /* INV_WAIT_DSC: Qword 0 valid mask. */
|
---|
| 2590 | #define VTD_INV_WAIT_DSC_0_VALID_MASK ( VTD_BF_0_INV_WAIT_DSC_TYPE_LO_MASK \
|
---|
| 2591 | | VTD_BF_0_INV_WAIT_DSC_IF_MASK \
|
---|
| 2592 | | VTD_BF_0_INV_WAIT_DSC_SW_MASK \
|
---|
| 2593 | | VTD_BF_0_INV_WAIT_DSC_FN_MASK \
|
---|
| 2594 | | VTD_BF_0_INV_WAIT_DSC_PD_MASK \
|
---|
| 2595 | | VTD_BF_0_INV_WAIT_DSC_TYPE_HI_MASK \
|
---|
| 2596 | | VTD_BF_0_INV_WAIT_DSC_STDATA_MASK)
|
---|
| 2597 | /* INV_WAIT_DSC: Qword 1 valid mask. */
|
---|
| 2598 | #define VTD_INV_WAIT_DSC_1_VALID_MASK VTD_BF_1_INV_WAIT_DSC_STADDR_MASK
|
---|
[88696] | 2599 | /** @} */
|
---|
| 2600 |
|
---|
| 2601 |
|
---|
[88744] | 2602 | /** @name Invalidation descriptor types.
|
---|
| 2603 | * In accordance with the Intel spec.
|
---|
| 2604 | * @{ */
|
---|
| 2605 | #define VTD_CC_INV_DSC_TYPE 1
|
---|
| 2606 | #define VTD_IOTLB_INV_DSC_TYPE 2
|
---|
| 2607 | #define VTD_DEV_TLB_INV_DSC_TYPE 3
|
---|
| 2608 | #define VTD_IEC_INV_DSC_TYPE 4
|
---|
| 2609 | #define VTD_INV_WAIT_DSC_TYPE 5
|
---|
| 2610 | #define VTD_P_IOTLB_INV_DSC_TYPE 6
|
---|
| 2611 | #define VTD_PC_INV_DSC_TYPE 7
|
---|
| 2612 | #define VTD_P_DEV_TLB_INV_DSC_TYPE 8
|
---|
| 2613 | /** @} */
|
---|
| 2614 |
|
---|
| 2615 |
|
---|
[88841] | 2616 | /** @name Remappable Format Interrupt Request.
|
---|
| 2617 | * In accordance with the Intel spec.
|
---|
| 2618 | * @{ */
|
---|
| 2619 | /** IGN: Ignored (bits 1:0). */
|
---|
[88858] | 2620 | #define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_SHIFT 0
|
---|
| 2621 | #define VTD_BF_REMAPPABLE_MSI_ADDR_IGN_1_0_MASK UINT32_C(0x00000003)
|
---|
[88841] | 2622 | /** Handle (Hi). */
|
---|
[88858] | 2623 | #define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_SHIFT 2
|
---|
| 2624 | #define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI_MASK UINT32_C(0x00000004)
|
---|
[88841] | 2625 | /** SHV: Subhandle Valid. */
|
---|
[88858] | 2626 | #define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_SHIFT 3
|
---|
| 2627 | #define VTD_BF_REMAPPABLE_MSI_ADDR_SHV_MASK UINT32_C(0x00000008)
|
---|
[88841] | 2628 | /** Interrupt format. */
|
---|
[88858] | 2629 | #define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_SHIFT 4
|
---|
| 2630 | #define VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT_MASK UINT32_C(0x00000010)
|
---|
[88841] | 2631 | /** Handle (Lo). */
|
---|
[88858] | 2632 | #define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_SHIFT 5
|
---|
| 2633 | #define VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO_MASK UINT32_C(0x000fffe0)
|
---|
[88841] | 2634 | /** Address. */
|
---|
[88858] | 2635 | #define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_SHIFT 20
|
---|
| 2636 | #define VTD_BF_REMAPPABLE_MSI_ADDR_ADDR_MASK UINT32_C(0xfff00000)
|
---|
| 2637 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_ADDR_, UINT32_C(0), UINT32_MAX,
|
---|
[88841] | 2638 | (IGN_1_0, HANDLE_HI, SHV, INTR_FMT, HANDLE_LO, ADDR));
|
---|
| 2639 |
|
---|
| 2640 | /** Subhandle. */
|
---|
[88858] | 2641 | #define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_SHIFT 0
|
---|
| 2642 | #define VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK UINT32_C(0x0000ffff)
|
---|
[88841] | 2643 | /** R: Reserved (bits 31:16). */
|
---|
[88858] | 2644 | #define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_SHIFT 16
|
---|
| 2645 | #define VTD_BF_REMAPPABLE_MSI_DATA_RSVD_31_16_MASK UINT32_C(0xffff0000)
|
---|
| 2646 | RT_BF_ASSERT_COMPILE_CHECKS(VTD_BF_REMAPPABLE_MSI_DATA_, UINT32_C(0), UINT32_MAX,
|
---|
[88841] | 2647 | (SUBHANDLE, RSVD_31_16));
|
---|
[88858] | 2648 |
|
---|
| 2649 | /** Remappable MSI Address: Valid mask. */
|
---|
| 2650 | #define VTD_REMAPPABLE_MSI_ADDR_VALID_MASK UINT32_MAX
|
---|
| 2651 | /** Remappable MSI Data: Valid mask. */
|
---|
| 2652 | #define VTD_REMAPPABLE_MSI_DATA_VALID_MASK VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE_MASK
|
---|
| 2653 |
|
---|
| 2654 | /** Interrupt format: Compatibility. */
|
---|
| 2655 | #define VTD_INTR_FORMAT_COMPAT 0
|
---|
| 2656 | /** Interrupt format: Remappable. */
|
---|
| 2657 | #define VTD_INTR_FORMAT_REMAPPABLE 1
|
---|
[88841] | 2658 | /** @} */
|
---|
| 2659 |
|
---|
| 2660 |
|
---|
[88858] | 2661 | /** @name Interrupt Remapping Fault Conditions.
|
---|
| 2662 | * In accordance with the Intel spec.
|
---|
| 2663 | * @{ */
|
---|
[89236] | 2664 | typedef enum VTDIRFAULT
|
---|
[88858] | 2665 | {
|
---|
| 2666 | /** Reserved bits invalid in remappable interrupt. */
|
---|
[89236] | 2667 | VTDIRFAULT_REMAPPABLE_INTR_RSVD = 0x20,
|
---|
| 2668 |
|
---|
[88858] | 2669 | /** Interrupt index for remappable interrupt exceeds table size or referenced
|
---|
| 2670 | * address above host address width (HAW) */
|
---|
[89236] | 2671 | VTDIRFAULT_INTR_INDEX_INVALID = 0x21,
|
---|
| 2672 |
|
---|
[88858] | 2673 | /** The IRTE is not present. */
|
---|
[89236] | 2674 | VTDIRFAULT_IRTE_NOT_PRESENT = 0x22,
|
---|
[88858] | 2675 | /** Reading IRTE from memory failed. */
|
---|
[89236] | 2676 | VTDIRFAULT_IRTE_READ_FAILED = 0x23,
|
---|
[88858] | 2677 | /** IRTE reserved bits invalid for an IRTE with Present bit set. */
|
---|
[89236] | 2678 | VTDIRFAULT_IRTE_PRESENT_RSVD = 0x24,
|
---|
| 2679 |
|
---|
[89201] | 2680 | /** Compatibility format interrupt (CFI) blocked due to EIME being enabled or CFIs
|
---|
| 2681 | * were disabled. */
|
---|
[89236] | 2682 | VTDIRFAULT_CFI_BLOCKED = 0x25,
|
---|
| 2683 |
|
---|
[88858] | 2684 | /** IRTE SID, SVT, SQ bits invalid for an IRTE with Present bit set. */
|
---|
[89236] | 2685 | VTDIRFAULT_IRTE_PRESENT_INVALID = 0x26,
|
---|
| 2686 |
|
---|
[88858] | 2687 | /** Reading posted interrupt descriptor (PID) failed. */
|
---|
[89236] | 2688 | VTDIRFAULT_PID_READ_FAILED = 0x27,
|
---|
[88858] | 2689 | /** PID reserved bits invalid. */
|
---|
[89236] | 2690 | VTDIRFAULT_PID_RSVD = 0x28,
|
---|
| 2691 |
|
---|
[88858] | 2692 | /** Untranslated interrupt requested (without PASID) is invalid. */
|
---|
[89236] | 2693 | VTDIRFAULT_IR_WITHOUT_PASID_INVALID = 0x29
|
---|
| 2694 | } VTDIRFAULT;
|
---|
| 2695 | AssertCompileSize(VTDIRFAULT, 4);
|
---|
[88858] | 2696 | /** @} */
|
---|
| 2697 |
|
---|
| 2698 |
|
---|
[89201] | 2699 | /** @name Address Translation Fault Conditions.
|
---|
| 2700 | * In accordance with the Intel spec.
|
---|
| 2701 | * @{ */
|
---|
[89236] | 2702 | typedef enum VTDATFAULT
|
---|
[89201] | 2703 | {
|
---|
| 2704 | /* Legacy root table faults (LRT). */
|
---|
[89236] | 2705 | VTDATFAULT_LRT_1 = 0x8,
|
---|
| 2706 | VTDATFAULT_LRT_2 = 0x1,
|
---|
| 2707 | VTDATFAULT_LRT_3 = 0xa,
|
---|
[89201] | 2708 |
|
---|
| 2709 | /* Legacy Context-Table Faults (LCT). */
|
---|
[89236] | 2710 | VTDATFAULT_LCT_1 = 0x9,
|
---|
| 2711 | VTDATFAULT_LCT_2 = 0x2,
|
---|
| 2712 | VTDATFAULT_LCT_3 = 0xb,
|
---|
| 2713 | VTDATFAULT_LCT_4_1 = 0x3,
|
---|
| 2714 | VTDATFAULT_LCT_4_2 = 0x3,
|
---|
| 2715 | VTDATFAULT_LCT_4_3 = 0x3,
|
---|
| 2716 | VTDATFAULT_LCT_5 = 0xd,
|
---|
[89201] | 2717 |
|
---|
| 2718 | /* Legacy Second-Level Table Faults (LSL). */
|
---|
[89236] | 2719 | VTDATFAULT_LSL_1 = 0x7,
|
---|
| 2720 | VTDATFAULT_LSL_2 = 0xc,
|
---|
[89201] | 2721 |
|
---|
| 2722 | /* Legacy General Faults (LGN). */
|
---|
[89236] | 2723 | VTDATFAULT_LGN_1_1 = 0x4,
|
---|
| 2724 | VTDATFAULT_LGN_1_2 = 0x4,
|
---|
| 2725 | VTDATFAULT_LGN_1_3 = 0x4,
|
---|
| 2726 | VTDATFAULT_LGN_2 = 0x5,
|
---|
| 2727 | VTDATFAULT_LGN_3 = 0x6,
|
---|
| 2728 | VTDATFAULT_LGN_4 = 0xe,
|
---|
[89201] | 2729 |
|
---|
| 2730 | /* Root-Table Address Register Faults (RTA). */
|
---|
[89236] | 2731 | VTDATFAULT_RTA_1_1 = 0x30,
|
---|
| 2732 | VTDATFAULT_RTA_1_2 = 0x30,
|
---|
| 2733 | VTDATFAULT_RTA_1_3 = 0x30,
|
---|
| 2734 | VTDATFAULT_RTA_2 = 0x31,
|
---|
| 2735 | VTDATFAULT_RTA_3 = 0x32,
|
---|
| 2736 | VTDATFAULT_RTA_4 = 0x33,
|
---|
[89201] | 2737 |
|
---|
| 2738 | /* Scalable-Mode Root-Table Faults (SRT). */
|
---|
[89236] | 2739 | VTDATFAULT_SRT_1 = 0x38,
|
---|
| 2740 | VTDATFAULT_SRT_2 = 0x39,
|
---|
| 2741 | VTDATFAULT_SRT_3 = 0x3a,
|
---|
[89201] | 2742 |
|
---|
| 2743 | /* Scalable-Mode Context-Table Faults (SCT). */
|
---|
[89236] | 2744 | VTDATFAULT_SCT_1 = 0x40,
|
---|
| 2745 | VTDATFAULT_SCT_2 = 0x41,
|
---|
| 2746 | VTDATFAULT_SCT_3 = 0x42,
|
---|
| 2747 | VTDATFAULT_SCT_4_1 = 0x43,
|
---|
| 2748 | VTDATFAULT_SCT_4_2 = 0x43,
|
---|
| 2749 | VTDATFAULT_SCT_5 = 0x44,
|
---|
| 2750 | VTDATFAULT_SCT_6 = 0x45,
|
---|
| 2751 | VTDATFAULT_SCT_7 = 0x46,
|
---|
| 2752 | VTDATFAULT_SCT_8 = 0x47,
|
---|
| 2753 | VTDATFAULT_SCT_9 = 0x48,
|
---|
[89201] | 2754 |
|
---|
| 2755 | /* Scalable-Mode PASID-Directory Faults (SPD). */
|
---|
[89236] | 2756 | VTDATFAULT_SPD_1 = 0x50,
|
---|
| 2757 | VTDATFAULT_SPD_2 = 0x51,
|
---|
| 2758 | VTDATFAULT_SPD_3 = 0x52,
|
---|
[89201] | 2759 |
|
---|
| 2760 | /* Scalable-Mode PASID-Table Faults (SPT). */
|
---|
[89236] | 2761 | VTDATFAULT_SPT_1 = 0x58,
|
---|
| 2762 | VTDATFAULT_SPT_2 = 0x59,
|
---|
| 2763 | VTDATFAULT_SPT_3 = 0x5a,
|
---|
| 2764 | VTDATFAULT_SPT_4_1 = 0x5b,
|
---|
| 2765 | VTDATFAULT_SPT_4_2 = 0x5b,
|
---|
| 2766 | VTDATFAULT_SPT_4_3 = 0x5b,
|
---|
| 2767 | VTDATFAULT_SPT_4_4 = 0x5b,
|
---|
| 2768 | VTDATFAULT_SPT_5 = 0x5c,
|
---|
| 2769 | VTDATFAULT_SPT_6 = 0x5d,
|
---|
[89201] | 2770 |
|
---|
| 2771 | /* Scalable-Mode First-Level Table Faults (SFL). */
|
---|
[89236] | 2772 | VTDATFAULT_SFL_1 = 0x70,
|
---|
| 2773 | VTDATFAULT_SFL_2 = 0x71,
|
---|
| 2774 | VTDATFAULT_SFL_3 = 0x72,
|
---|
| 2775 | VTDATFAULT_SFL_4 = 0x73,
|
---|
| 2776 | VTDATFAULT_SFL_5 = 0x74,
|
---|
| 2777 | VTDATFAULT_SFL_6 = 0x75,
|
---|
| 2778 | VTDATFAULT_SFL_7 = 0x76,
|
---|
| 2779 | VTDATFAULT_SFL_8 = 0x77,
|
---|
| 2780 | VTDATFAULT_SFL_9 = 0x90,
|
---|
| 2781 | VTDATFAULT_SFL_10 = 0x91,
|
---|
[89201] | 2782 |
|
---|
| 2783 | /* Scalable-Mode Second-Level Table Faults (SSL). */
|
---|
[89236] | 2784 | VTDATFAULT_SSL_1 = 0x78,
|
---|
| 2785 | VTDATFAULT_SSL_2 = 0x79,
|
---|
| 2786 | VTDATFAULT_SSL_3 = 0x7a,
|
---|
| 2787 | VTDATFAULT_SSL_4 = 0x7b,
|
---|
| 2788 | VTDATFAULT_SSL_5 = 0x7c,
|
---|
| 2789 | VTDATFAULT_SSL_6 = 0x7d,
|
---|
[89201] | 2790 |
|
---|
| 2791 | /* Scalable-Mode General Faults (SGN). */
|
---|
[89236] | 2792 | VTDATFAULT_SGN_1 = 0x80,
|
---|
| 2793 | VTDATFAULT_SGN_2 = 0x81,
|
---|
| 2794 | VTDATFAULT_SGN_3 = 0x82,
|
---|
| 2795 | VTDATFAULT_SGN_4_1 = 0x83,
|
---|
| 2796 | VTDATFAULT_SGN_4_2 = 0x83,
|
---|
| 2797 | VTDATFAULT_SGN_5 = 0x84,
|
---|
| 2798 | VTDATFAULT_SGN_6 = 0x85,
|
---|
| 2799 | VTDATFAULT_SGN_7 = 0x86,
|
---|
| 2800 | VTDATFAULT_SGN_8 = 0x87,
|
---|
| 2801 | VTDATFAULT_SGN_9 = 0x88,
|
---|
| 2802 | VTDATFAULT_SGN_10 = 0x89
|
---|
| 2803 | } VTDATFAULT;
|
---|
| 2804 | AssertCompileSize(VTDATFAULT, 4);
|
---|
[89201] | 2805 | /** @} */
|
---|
| 2806 |
|
---|
| 2807 |
|
---|
[88265] | 2808 | /** @name ACPI_DMAR_F_XXX: DMA Remapping Reporting Structure Flags.
|
---|
| 2809 | * In accordance with the Intel spec.
|
---|
| 2810 | * @{ */
|
---|
| 2811 | /** INTR_REMAP: Interrupt remapping supported. */
|
---|
| 2812 | #define ACPI_DMAR_F_INTR_REMAP RT_BIT(0)
|
---|
| 2813 | /** X2APIC_OPT_OUT: Request system software to opt-out of enabling x2APIC. */
|
---|
[88341] | 2814 | #define ACPI_DMAR_F_X2APIC_OPT_OUT RT_BIT(1)
|
---|
[88265] | 2815 | /** DMA_CTRL_PLATFORM_OPT_IN_FLAG: Firmware initiated DMA restricted to reserved
|
---|
| 2816 | * memory regions (RMRR). */
|
---|
| 2817 | #define ACPI_DMAR_F_DMA_CTRL_PLATFORM_OPT_IN RT_BIT(2)
|
---|
| 2818 | /** @} */
|
---|
| 2819 |
|
---|
| 2820 |
|
---|
| 2821 | /** @name ACPI_DRHD_F_XXX: DMA-Remapping Hardware Unit Definition Flags.
|
---|
| 2822 | * In accordance with the Intel spec.
|
---|
| 2823 | * @{ */
|
---|
| 2824 | /** INCLUDE_PCI_ALL: All PCI devices under scope. */
|
---|
| 2825 | #define ACPI_DRHD_F_INCLUDE_PCI_ALL RT_BIT(0)
|
---|
| 2826 | /** @} */
|
---|
| 2827 |
|
---|
| 2828 |
|
---|
| 2829 | /**
|
---|
| 2830 | * DRHD: DMA-Remapping Hardware Unit Definition.
|
---|
| 2831 | * In accordance with the Intel spec.
|
---|
| 2832 | */
|
---|
| 2833 | #pragma pack(1)
|
---|
| 2834 | typedef struct ACPIDRHD
|
---|
| 2835 | {
|
---|
| 2836 | /** Type (must be 0=DRHD). */
|
---|
| 2837 | uint16_t uType;
|
---|
| 2838 | /** Length (must be 16 + size of device scope structure). */
|
---|
| 2839 | uint16_t cbLength;
|
---|
[88301] | 2840 | /** Flags, see ACPI_DRHD_F_XXX. */
|
---|
[88265] | 2841 | uint8_t fFlags;
|
---|
| 2842 | /** Reserved (MBZ). */
|
---|
| 2843 | uint8_t bRsvd;
|
---|
| 2844 | /** PCI segment number. */
|
---|
| 2845 | uint16_t uPciSegment;
|
---|
| 2846 | /** Register Base Address (MMIO). */
|
---|
| 2847 | uint64_t uRegBaseAddr;
|
---|
| 2848 | /* Device Scope[] Structures follow. */
|
---|
| 2849 | } ACPIDRHD;
|
---|
| 2850 | #pragma pack()
|
---|
| 2851 | AssertCompileSize(ACPIDRHD, 16);
|
---|
| 2852 | AssertCompileMemberOffset(ACPIDRHD, cbLength, 2);
|
---|
| 2853 | AssertCompileMemberOffset(ACPIDRHD, fFlags, 4);
|
---|
| 2854 | AssertCompileMemberOffset(ACPIDRHD, uPciSegment, 6);
|
---|
| 2855 | AssertCompileMemberOffset(ACPIDRHD, uRegBaseAddr, 8);
|
---|
| 2856 |
|
---|
| 2857 |
|
---|
| 2858 | /** @name ACPIDMARDEVSCOPE_TYPE_XXX: Device Type.
|
---|
| 2859 | * In accordance with the Intel spec.
|
---|
| 2860 | * @{ */
|
---|
| 2861 | #define ACPIDMARDEVSCOPE_TYPE_PCI_ENDPOINT 1
|
---|
| 2862 | #define ACPIDMARDEVSCOPE_TYPE_PCI_SUB_HIERARCHY 2
|
---|
| 2863 | #define ACPIDMARDEVSCOPE_TYPE_IOAPIC 3
|
---|
| 2864 | #define ACPIDMARDEVSCOPE_TYPE_MSI_CAP_HPET 4
|
---|
| 2865 | #define ACPIDMARDEVSCOPE_TYPE_ACPI_NAMESPACE_DEV 5
|
---|
| 2866 | /** @} */
|
---|
| 2867 |
|
---|
| 2868 |
|
---|
| 2869 | /**
|
---|
[88484] | 2870 | * ACPI Device Scope Structure - PCI device path.
|
---|
| 2871 | * In accordance with the Intel spec.
|
---|
| 2872 | */
|
---|
| 2873 | typedef struct ACPIDEVSCOPEPATH
|
---|
| 2874 | {
|
---|
| 2875 | /** PCI device number. */
|
---|
| 2876 | uint8_t uDevice;
|
---|
| 2877 | /** PCI function number. */
|
---|
| 2878 | uint8_t uFunction;
|
---|
| 2879 | } ACPIDEVSCOPEPATH;
|
---|
| 2880 | AssertCompileSize(ACPIDEVSCOPEPATH, 2);
|
---|
| 2881 |
|
---|
| 2882 |
|
---|
| 2883 | /**
|
---|
[88265] | 2884 | * Device Scope Structure.
|
---|
| 2885 | * In accordance with the Intel spec.
|
---|
| 2886 | */
|
---|
| 2887 | #pragma pack(1)
|
---|
| 2888 | typedef struct ACPIDMARDEVSCOPE
|
---|
| 2889 | {
|
---|
| 2890 | /** Type, see ACPIDMARDEVSCOPE_TYPE_XXX. */
|
---|
[88484] | 2891 | uint8_t uType;
|
---|
[88265] | 2892 | /** Length (must be 6 + size of auPath field). */
|
---|
[88484] | 2893 | uint8_t cbLength;
|
---|
[88265] | 2894 | /** Reserved (MBZ). */
|
---|
[88484] | 2895 | uint8_t abRsvd[2];
|
---|
[88265] | 2896 | /** Enumeration ID (for I/O APIC, HPET and ACPI namespace devices). */
|
---|
[88484] | 2897 | uint8_t idEnum;
|
---|
[88265] | 2898 | /** First bus number for this device. */
|
---|
[88484] | 2899 | uint8_t uStartBusNum;
|
---|
[88265] | 2900 | /** Hierarchical path from the Host Bridge to the device. */
|
---|
[88484] | 2901 | ACPIDEVSCOPEPATH Path;
|
---|
[88265] | 2902 | } ACPIDMARDEVSCOPE;
|
---|
| 2903 | #pragma pack()
|
---|
| 2904 | AssertCompileMemberOffset(ACPIDMARDEVSCOPE, cbLength, 1);
|
---|
| 2905 | AssertCompileMemberOffset(ACPIDMARDEVSCOPE, idEnum, 4);
|
---|
| 2906 | AssertCompileMemberOffset(ACPIDMARDEVSCOPE, uStartBusNum, 5);
|
---|
[88484] | 2907 | AssertCompileMemberOffset(ACPIDMARDEVSCOPE, Path, 6);
|
---|
[88265] | 2908 |
|
---|
[88280] | 2909 | /** ACPI DMAR revision (not the OEM revision field).
|
---|
| 2910 | * In accordance with the Intel spec. */
|
---|
| 2911 | #define ACPI_DMAR_REVISION 1
|
---|
[88265] | 2912 |
|
---|
[88280] | 2913 |
|
---|
[88153] | 2914 | #endif /* !VBOX_INCLUDED_iommu_intel_h */
|
---|
[88696] | 2915 |
|
---|