VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 28800

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1/** @file
2 * HWACCM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmx_h
27#define ___VBox_vmx_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33#include <VBox/x86.h>
34
35/** @defgroup grp_vmx vmx Types and Definitions
36 * @ingroup grp_hwaccm
37 * @{
38 */
39
40/** @name VMX EPT paging structures
41 * @{
42 */
43
44/**
45 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
46 */
47#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
48
49/**
50 * EPT Page Directory Pointer Entry. Bit view.
51 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
52 * this did cause trouble with one compiler/version).
53 */
54#pragma pack(1)
55typedef struct EPTPML4EBITS
56{
57 /** Present bit. */
58 uint64_t u1Present : 1;
59 /** Writable bit. */
60 uint64_t u1Write : 1;
61 /** Executable bit. */
62 uint64_t u1Execute : 1;
63 /** Reserved (must be 0). */
64 uint64_t u5Reserved : 5;
65 /** Available for software. */
66 uint64_t u4Available : 4;
67 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
68 uint64_t u40PhysAddr : 40;
69 /** Availabe for software. */
70 uint64_t u12Available : 12;
71} EPTPML4EBITS;
72#pragma pack()
73AssertCompileSize(EPTPML4EBITS, 8);
74
75/** Bits 12-51 - - EPT - Physical Page number of the next level. */
76#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
77/** The page shift to get the PML4 index. */
78#define EPT_PML4_SHIFT X86_PML4_SHIFT
79/** The PML4 index mask (apply to a shifted page address). */
80#define EPT_PML4_MASK X86_PML4_MASK
81
82/**
83 * EPT PML4E.
84 */
85#pragma pack(1)
86typedef union EPTPML4E
87{
88 /** Normal view. */
89 EPTPML4EBITS n;
90 /** Unsigned integer view. */
91 X86PGPAEUINT u;
92 /** 64 bit unsigned integer view. */
93 uint64_t au64[1];
94 /** 32 bit unsigned integer view. */
95 uint32_t au32[2];
96} EPTPML4E;
97#pragma pack()
98/** Pointer to a PML4 table entry. */
99typedef EPTPML4E *PEPTPML4E;
100/** Pointer to a const PML4 table entry. */
101typedef const EPTPML4E *PCEPTPML4E;
102AssertCompileSize(EPTPML4E, 8);
103
104/**
105 * EPT PML4 Table.
106 */
107#pragma pack(1)
108typedef struct EPTPML4
109{
110 EPTPML4E a[EPT_PG_ENTRIES];
111} EPTPML4;
112#pragma pack()
113/** Pointer to an EPT PML4 Table. */
114typedef EPTPML4 *PEPTPML4;
115/** Pointer to a const EPT PML4 Table. */
116typedef const EPTPML4 *PCEPTPML4;
117
118/**
119 * EPT Page Directory Pointer Entry. Bit view.
120 */
121#pragma pack(1)
122typedef struct EPTPDPTEBITS
123{
124 /** Present bit. */
125 uint64_t u1Present : 1;
126 /** Writable bit. */
127 uint64_t u1Write : 1;
128 /** Executable bit. */
129 uint64_t u1Execute : 1;
130 /** Reserved (must be 0). */
131 uint64_t u5Reserved : 5;
132 /** Available for software. */
133 uint64_t u4Available : 4;
134 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
135 uint64_t u40PhysAddr : 40;
136 /** Availabe for software. */
137 uint64_t u12Available : 12;
138} EPTPDPTEBITS;
139#pragma pack()
140AssertCompileSize(EPTPDPTEBITS, 8);
141
142/** Bits 12-51 - - EPT - Physical Page number of the next level. */
143#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
144/** The page shift to get the PDPT index. */
145#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
146/** The PDPT index mask (apply to a shifted page address). */
147#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
148
149/**
150 * EPT Page Directory Pointer.
151 */
152#pragma pack(1)
153typedef union EPTPDPTE
154{
155 /** Normal view. */
156 EPTPDPTEBITS n;
157 /** Unsigned integer view. */
158 X86PGPAEUINT u;
159 /** 64 bit unsigned integer view. */
160 uint64_t au64[1];
161 /** 32 bit unsigned integer view. */
162 uint32_t au32[2];
163} EPTPDPTE;
164#pragma pack()
165/** Pointer to an EPT Page Directory Pointer Entry. */
166typedef EPTPDPTE *PEPTPDPTE;
167/** Pointer to a const EPT Page Directory Pointer Entry. */
168typedef const EPTPDPTE *PCEPTPDPTE;
169AssertCompileSize(EPTPDPTE, 8);
170
171/**
172 * EPT Page Directory Pointer Table.
173 */
174#pragma pack(1)
175typedef struct EPTPDPT
176{
177 EPTPDPTE a[EPT_PG_ENTRIES];
178} EPTPDPT;
179#pragma pack()
180/** Pointer to an EPT Page Directory Pointer Table. */
181typedef EPTPDPT *PEPTPDPT;
182/** Pointer to a const EPT Page Directory Pointer Table. */
183typedef const EPTPDPT *PCEPTPDPT;
184
185
186/**
187 * EPT Page Directory Table Entry. Bit view.
188 */
189#pragma pack(1)
190typedef struct EPTPDEBITS
191{
192 /** Present bit. */
193 uint64_t u1Present : 1;
194 /** Writable bit. */
195 uint64_t u1Write : 1;
196 /** Executable bit. */
197 uint64_t u1Execute : 1;
198 /** Reserved (must be 0). */
199 uint64_t u4Reserved : 4;
200 /** Big page (must be 0 here). */
201 uint64_t u1Size : 1;
202 /** Available for software. */
203 uint64_t u4Available : 4;
204 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
205 uint64_t u40PhysAddr : 40;
206 /** Availabe for software. */
207 uint64_t u12Available : 12;
208} EPTPDEBITS;
209#pragma pack()
210AssertCompileSize(EPTPDEBITS, 8);
211
212/** Bits 12-51 - - EPT - Physical Page number of the next level. */
213#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
214/** The page shift to get the PD index. */
215#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
216/** The PD index mask (apply to a shifted page address). */
217#define EPT_PD_MASK X86_PD_PAE_MASK
218
219/**
220 * EPT 2MB Page Directory Table Entry. Bit view.
221 */
222#pragma pack(1)
223typedef struct EPTPDE2MBITS
224{
225 /** Present bit. */
226 uint64_t u1Present : 1;
227 /** Writable bit. */
228 uint64_t u1Write : 1;
229 /** Executable bit. */
230 uint64_t u1Execute : 1;
231 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
232 uint64_t u3EMT : 3;
233 /** Ignore PAT memory type */
234 uint64_t u1IgnorePAT : 1;
235 /** Big page (must be 1 here). */
236 uint64_t u1Size : 1;
237 /** Available for software. */
238 uint64_t u4Available : 4;
239 /** Reserved (must be 0). */
240 uint64_t u9Reserved : 9;
241 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
242 uint64_t u31PhysAddr : 31;
243 /** Availabe for software. */
244 uint64_t u12Available : 12;
245} EPTPDE2MBITS;
246#pragma pack()
247AssertCompileSize(EPTPDE2MBITS, 8);
248
249/** Bits 21-51 - - EPT - Physical Page number of the next level. */
250#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
251
252/**
253 * EPT Page Directory Table Entry.
254 */
255#pragma pack(1)
256typedef union EPTPDE
257{
258 /** Normal view. */
259 EPTPDEBITS n;
260 /** 2MB view (big). */
261 EPTPDE2MBITS b;
262 /** Unsigned integer view. */
263 X86PGPAEUINT u;
264 /** 64 bit unsigned integer view. */
265 uint64_t au64[1];
266 /** 32 bit unsigned integer view. */
267 uint32_t au32[2];
268} EPTPDE;
269#pragma pack()
270/** Pointer to an EPT Page Directory Table Entry. */
271typedef EPTPDE *PEPTPDE;
272/** Pointer to a const EPT Page Directory Table Entry. */
273typedef const EPTPDE *PCEPTPDE;
274AssertCompileSize(EPTPDE, 8);
275
276/**
277 * EPT Page Directory Table.
278 */
279#pragma pack(1)
280typedef struct EPTPD
281{
282 EPTPDE a[EPT_PG_ENTRIES];
283} EPTPD;
284#pragma pack()
285/** Pointer to an EPT Page Directory Table. */
286typedef EPTPD *PEPTPD;
287/** Pointer to a const EPT Page Directory Table. */
288typedef const EPTPD *PCEPTPD;
289
290
291/**
292 * EPT Page Table Entry. Bit view.
293 */
294#pragma pack(1)
295typedef struct EPTPTEBITS
296{
297 /** Present bit. */
298 uint64_t u1Present : 1;
299 /** Writable bit. */
300 uint64_t u1Write : 1;
301 /** Executable bit. */
302 uint64_t u1Execute : 1;
303 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
304 uint64_t u3EMT : 3;
305 /** Ignore PAT memory type */
306 uint64_t u1IgnorePAT : 1;
307 /** Available for software. */
308 uint64_t u5Available : 5;
309 /** Physical address of page. Restricted by maximum physical address width of the cpu. */
310 uint64_t u40PhysAddr : 40;
311 /** Availabe for software. */
312 uint64_t u12Available : 12;
313} EPTPTEBITS;
314#pragma pack()
315AssertCompileSize(EPTPTEBITS, 8);
316
317/** Bits 12-51 - - EPT - Physical Page number of the next level. */
318#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
319/** The page shift to get the EPT PTE index. */
320#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
321/** The EPT PT index mask (apply to a shifted page address). */
322#define EPT_PT_MASK X86_PT_PAE_MASK
323
324/**
325 * EPT Page Table Entry.
326 */
327#pragma pack(1)
328typedef union EPTPTE
329{
330 /** Normal view. */
331 EPTPTEBITS n;
332 /** Unsigned integer view. */
333 X86PGPAEUINT u;
334 /** 64 bit unsigned integer view. */
335 uint64_t au64[1];
336 /** 32 bit unsigned integer view. */
337 uint32_t au32[2];
338} EPTPTE;
339#pragma pack()
340/** Pointer to an EPT Page Directory Table Entry. */
341typedef EPTPTE *PEPTPTE;
342/** Pointer to a const EPT Page Directory Table Entry. */
343typedef const EPTPTE *PCEPTPTE;
344AssertCompileSize(EPTPTE, 8);
345
346/**
347 * EPT Page Table.
348 */
349#pragma pack(1)
350typedef struct EPTPT
351{
352 EPTPTE a[EPT_PG_ENTRIES];
353} EPTPT;
354#pragma pack()
355/** Pointer to an extended page table. */
356typedef EPTPT *PEPTPT;
357/** Pointer to a const extended table. */
358typedef const EPTPT *PCEPTPT;
359
360/**
361 * VPID and EPT flush types
362 */
363typedef enum
364{
365 /* Invalidate a specific page. */
366 VMX_FLUSH_PAGE = 0,
367 /* Invalidate one context (VPID or EPT) */
368 VMX_FLUSH_SINGLE_CONTEXT = 1,
369 /* Invalidate all contexts (VPIDs or EPTs) */
370 VMX_FLUSH_ALL_CONTEXTS = 2,
371 /* Invalidate a single VPID context retaining global mappings. */
372 VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
373 /** 32bit hackishness. */
374 VMX_FLUSH_32BIT_HACK = 0x7fffffff
375} VMX_FLUSH;
376/** @} */
377
378/** @name MSR load/store elements
379 * @{
380 */
381#pragma pack(1)
382typedef struct
383{
384 uint32_t u32IndexMSR;
385 uint32_t u32Reserved;
386 uint64_t u64Value;
387} VMXMSR;
388#pragma pack()
389/** Pointer to an MSR load/store element. */
390typedef VMXMSR *PVMXMSR;
391/** Pointer to a const MSR load/store element. */
392typedef const VMXMSR *PCVMXMSR;
393
394/** @} */
395
396
397/** @name VT-x capability qword
398 * @{
399 */
400#pragma pack(1)
401typedef union
402{
403 struct
404 {
405 uint32_t disallowed0;
406 uint32_t allowed1;
407 } n;
408 uint64_t u;
409} VMX_CAPABILITY;
410#pragma pack()
411/** @} */
412
413/** @name VMX Basic Exit Reasons.
414 * @{
415 */
416/** And-mask for setting reserved bits to zero */
417#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
418/** Or-mask for setting reserved bits to 1 */
419#define VMX_EFLAGS_RESERVED_1 0x00000002
420/** @} */
421
422/** @name VMX Basic Exit Reasons.
423 * @{
424 */
425/** -1 Invalid exit code */
426#define VMX_EXIT_INVALID -1
427/** 0 Exception or non-maskable interrupt (NMI). */
428#define VMX_EXIT_EXCEPTION 0
429/** 1 External interrupt. */
430#define VMX_EXIT_EXTERNAL_IRQ 1
431/** 2 Triple fault. */
432#define VMX_EXIT_TRIPLE_FAULT 2
433/** 3 INIT signal. */
434#define VMX_EXIT_INIT_SIGNAL 3
435/** 4 Start-up IPI (SIPI). */
436#define VMX_EXIT_SIPI 4
437/** 5 I/O system-management interrupt (SMI). */
438#define VMX_EXIT_IO_SMI_IRQ 5
439/** 6 Other SMI. */
440#define VMX_EXIT_SMI_IRQ 6
441/** 7 Interrupt window. */
442#define VMX_EXIT_IRQ_WINDOW 7
443/** 9 Task switch. */
444#define VMX_EXIT_TASK_SWITCH 9
445/** 10 Guest software attempted to execute CPUID. */
446#define VMX_EXIT_CPUID 10
447/** 12 Guest software attempted to execute HLT. */
448#define VMX_EXIT_HLT 12
449/** 13 Guest software attempted to execute INVD. */
450#define VMX_EXIT_INVD 13
451/** 14 Guest software attempted to execute INVPG. */
452#define VMX_EXIT_INVPG 14
453/** 15 Guest software attempted to execute RDPMC. */
454#define VMX_EXIT_RDPMC 15
455/** 16 Guest software attempted to execute RDTSC. */
456#define VMX_EXIT_RDTSC 16
457/** 17 Guest software attempted to execute RSM in SMM. */
458#define VMX_EXIT_RSM 17
459/** 18 Guest software executed VMCALL. */
460#define VMX_EXIT_VMCALL 18
461/** 19 Guest software executed VMCLEAR. */
462#define VMX_EXIT_VMCLEAR 19
463/** 20 Guest software executed VMLAUNCH. */
464#define VMX_EXIT_VMLAUNCH 20
465/** 21 Guest software executed VMPTRLD. */
466#define VMX_EXIT_VMPTRLD 21
467/** 22 Guest software executed VMPTRST. */
468#define VMX_EXIT_VMPTRST 22
469/** 23 Guest software executed VMREAD. */
470#define VMX_EXIT_VMREAD 23
471/** 24 Guest software executed VMRESUME. */
472#define VMX_EXIT_VMRESUME 24
473/** 25 Guest software executed VMWRITE. */
474#define VMX_EXIT_VMWRITE 25
475/** 26 Guest software executed VMXOFF. */
476#define VMX_EXIT_VMXOFF 26
477/** 27 Guest software executed VMXON. */
478#define VMX_EXIT_VMXON 27
479/** 28 Control-register accesses. */
480#define VMX_EXIT_CRX_MOVE 28
481/** 29 Debug-register accesses. */
482#define VMX_EXIT_DRX_MOVE 29
483/** 30 I/O instruction. */
484#define VMX_EXIT_PORT_IO 30
485/** 31 RDMSR. Guest software attempted to execute RDMSR. */
486#define VMX_EXIT_RDMSR 31
487/** 32 WRMSR. Guest software attempted to execute WRMSR. */
488#define VMX_EXIT_WRMSR 32
489/** 33 VM-entry failure due to invalid guest state. */
490#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
491/** 34 VM-entry failure due to MSR loading. */
492#define VMX_EXIT_ERR_MSR_LOAD 34
493/** 36 Guest software executed MWAIT. */
494#define VMX_EXIT_MWAIT 36
495/** 39 Guest software attempted to execute MONITOR. */
496#define VMX_EXIT_MONITOR 39
497/** 40 Guest software attempted to execute PAUSE. */
498#define VMX_EXIT_PAUSE 40
499/** 41 VM-entry failure due to machine-check. */
500#define VMX_EXIT_ERR_MACHINE_CHECK 41
501/** 43 TPR below threshold. Guest software executed MOV to CR8. */
502#define VMX_EXIT_TPR 43
503/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
504#define VMX_EXIT_APIC_ACCESS 44
505/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
506#define VMX_EXIT_XDTR_ACCESS 46
507/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
508#define VMX_EXIT_TR_ACCESS 47
509/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
510#define VMX_EXIT_EPT_VIOLATION 48
511/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
512#define VMX_EXIT_EPT_MISCONFIG 49
513/** 50 INVEPT. Guest software attempted to execute INVEPT. */
514#define VMX_EXIT_INVEPT 50
515/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
516#define VMX_EXIT_PREEMPTION_TIMER 52
517/** 53 INVVPID. Guest software attempted to execute INVVPID. */
518#define VMX_EXIT_INVVPID 53
519/** 54 WBINVD. Guest software attempted to execute WBINVD. */
520#define VMX_EXIT_WBINVD 54
521/** 55 XSETBV. Guest software attempted to execute XSETBV. */
522#define VMX_EXIT_XSETBV 55
523/** @} */
524
525
526/** @name VM Instruction Errors
527 * @{
528 */
529/** 1 VMCALL executed in VMX root operation. */
530#define VMX_ERROR_VMCALL 1
531/** 2 VMCLEAR with invalid physical address. */
532#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
533/** 3 VMCLEAR with VMXON pointer. */
534#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
535/** 4 VMLAUNCH with non-clear VMCS. */
536#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
537/** 5 VMRESUME with non-launched VMCS. */
538#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
539/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
540#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
541/** 7 VM entry with invalid control field(s). */
542#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
543/** 8 VM entry with invalid host-state field(s). */
544#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
545/** 9 VMPTRLD with invalid physical address. */
546#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
547/** 10 VMPTRLD with VMXON pointer. */
548#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
549/** 11 VMPTRLD with incorrect VMCS revision identifier. */
550#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
551/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
552#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
553#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
554/** 13 VMWRITE to read-only VMCS component. */
555#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
556/** 15 VMXON executed in VMX root operation. */
557#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
558/** 16 VM entry with invalid executive-VMCS pointer. */
559#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
560/** 17 VM entry with non-launched executive VMCS. */
561#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
562/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
563#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
564/** 19 VMCALL with non-clear VMCS. */
565#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
566/** 20 VMCALL with invalid VM-exit control fields. */
567#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
568/** 22 VMCALL with incorrect MSEG revision identifier. */
569#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
570/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
571#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
572/** 24 VMCALL with invalid SMM-monitor features. */
573#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
574/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
575#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
576/** 26 VM entry with events blocked by MOV SS. */
577#define VMX_ERROR_VMENTRY_MOV_SS 26
578/** 26 Invalid operand to INVEPT/INVVPID. */
579#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
580
581/** @} */
582
583
584/** @name VMX MSRs - Basic VMX information.
585 * @{
586 */
587/** VMCS revision identifier used by the processor. */
588#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
589/** Size of the VMCS. */
590#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
591/** Width of physical address used for the VMCS.
592 * 0 -> limited to the available amount of physical ram
593 * 1 -> within the first 4 GB
594 */
595#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
596/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
597#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
598/** Memory type that must be used for the VMCS. */
599#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
600/** @} */
601
602
603/** @name VMX MSRs - Misc VMX info.
604 * @{
605 */
606/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
607#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) (a & 0x1f)
608/** Activity states supported by the implementation. */
609#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
610/** Number of CR3 target values supported by the processor. (0-256) */
611#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
612/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
613#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
614/** MSEG revision identifier used by the processor. */
615#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
616/** @} */
617
618
619/** @name VMX MSRs - VMCS enumeration field info
620 * @{
621 */
622/** Highest field index. */
623#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
624
625/** @} */
626
627
628/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
629 * @{
630 */
631#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
632#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
633#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
634#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
635#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
636#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
637#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
638#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
639#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
640#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
641#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
642#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
643#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
644#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
645#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
646#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
647#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
648#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
649#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
650#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
651#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
652#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
653#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
654#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
655#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
656#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
657
658/** @} */
659
660/** @name Extended Page Table Pointer (EPTP)
661 * @{
662 */
663/** Uncachable EPT paging structure memory type. */
664#define VMX_EPT_MEMTYPE_UC 0
665/** Write-back EPT paging structure memory type. */
666#define VMX_EPT_MEMTYPE_WB 6
667/** Shift value to get the EPT page walk length (bits 5-3) */
668#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
669/** Mask value to get the EPT page walk length (bits 5-3) */
670#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
671/** Default EPT page walk length */
672#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
673/** @} */
674
675
676/** @name VMCS field encoding - 16 bits guest fields
677 * @{
678 */
679#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
680#define VMX_VMCS16_GUEST_FIELD_ES 0x800
681#define VMX_VMCS16_GUEST_FIELD_CS 0x802
682#define VMX_VMCS16_GUEST_FIELD_SS 0x804
683#define VMX_VMCS16_GUEST_FIELD_DS 0x806
684#define VMX_VMCS16_GUEST_FIELD_FS 0x808
685#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
686#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
687#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
688/** @} */
689
690/** @name VMCS field encoding - 16 bits host fields
691 * @{
692 */
693#define VMX_VMCS16_HOST_FIELD_ES 0xC00
694#define VMX_VMCS16_HOST_FIELD_CS 0xC02
695#define VMX_VMCS16_HOST_FIELD_SS 0xC04
696#define VMX_VMCS16_HOST_FIELD_DS 0xC06
697#define VMX_VMCS16_HOST_FIELD_FS 0xC08
698#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
699#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
700/** @} */
701
702/** @name VMCS field encoding - 64 bits host fields
703 * @{
704 */
705#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
706#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
707#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
708#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
709#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
710#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
711/** @} */
712
713
714/** @name VMCS field encoding - 64 Bits control fields
715 * @{
716 */
717#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
718#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
719#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
720#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
721
722/* Optional */
723#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
724#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
725
726#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
727#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
728#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
729#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
730
731#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
732#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
733
734#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
735#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
736
737#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
738#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
739
740/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
741#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
742#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
743
744/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
745#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
746#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
747
748/** Extended page table pointer. */
749#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
750#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
751
752/** VM-exit phyiscal address. */
753#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
754#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
755/** @} */
756
757
758/** @name VMCS field encoding - 64 Bits guest fields
759 * @{
760 */
761#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
762#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
763#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
764#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
765#define VMX_VMCS_GUEST_PAT_FULL 0x2804
766#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
767#define VMX_VMCS_GUEST_EFER_FULL 0x2806
768#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
769#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
770#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
771#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
772#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
773#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
774#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
775#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
776#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
777#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
778#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
779/** @} */
780
781
782/** @name VMCS field encoding - 32 Bits control fields
783 * @{
784 */
785#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
786#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
787#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
788#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
789#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
790#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
791#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
792#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
793#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
794#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
795#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
796#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
797#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
798#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
799/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
800#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
801/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
802#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
803/** @} */
804
805
806/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
807 * @{
808 */
809/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
810#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
811/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
812#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
813/** Virtual NMIs. */
814#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
815/** Activate VMX preemption timer. */
816#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
817/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
818/** @} */
819
820/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
821 * @{
822 */
823/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
824#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
825/** Use timestamp counter offset. */
826#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
827/** VM Exit when executing the HLT instruction. */
828#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
829/** VM Exit when executing the INVLPG instruction. */
830#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
831/** VM Exit when executing the MWAIT instruction. */
832#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
833/** VM Exit when executing the RDPMC instruction. */
834#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
835/** VM Exit when executing the RDTSC instruction. */
836#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
837/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
838#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
839/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
840#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
841/** VM Exit on CR8 loads. */
842#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
843/** VM Exit on CR8 stores. */
844#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
845/** Use TPR shadow. */
846#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
847/** VM Exit when virtual nmi blocking is disabled. */
848#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
849/** VM Exit when executing a MOV DRx instruction. */
850#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
851/** VM Exit when executing IO instructions. */
852#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
853/** Use IO bitmaps. */
854#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
855/** Monitor trap flag. */
856#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
857/** Use MSR bitmaps. */
858#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
859/** VM Exit when executing the MONITOR instruction. */
860#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
861/** VM Exit when executing the PAUSE instruction. */
862#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
863/** Determines whether the secondary processor based VM-execution controls are used. */
864#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
865/** @} */
866
867/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
868 * @{
869 */
870/** Virtualize APIC access. */
871#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
872/** EPT supported/enabled. */
873#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
874/** Descriptor table instructions cause VM-exits. */
875#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
876/** RDTSCP causes a VM-exit. */
877#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT RT_BIT(3)
878/** Virtualize x2APIC mode. */
879#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
880/** VPID supported/enabled. */
881#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
882/** VM Exit when executing the WBINVD instruction. */
883#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
884/** Unrestricted guest execution. */
885#define VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE RT_BIT(7)
886/** A specified nr of pause loops cause a VM-exit. */
887#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT RT_BIT(10)
888/** @} */
889
890
891/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
892 * @{
893 */
894/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
895#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
896/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
897#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
898/** In SMM mode after VM-entry. */
899#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
900/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
901#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
902/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
903#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
904/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
905#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
906/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
907#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
908/** @} */
909
910
911/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
912 * @{
913 */
914/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
915#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
916/** Return to long mode after a VM-exit. */
917#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
918/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
919#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
920/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
921#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
922/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
923#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
924/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
925#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
926/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
927#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
928/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
929#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
930/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
931#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
932/** @} */
933
934/** @name VMCS field encoding - 32 Bits read-only fields
935 * @{
936 */
937#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
938#define VMX_VMCS32_RO_EXIT_REASON 0x4402
939#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
940#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
941#define VMX_VMCS32_RO_IDT_INFO 0x4408
942#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
943#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
944#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
945/** @} */
946
947/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
948 * @{
949 */
950#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
951#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
952#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
953#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
954#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
955#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
956#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
957#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
958/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
959#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
960/** @} */
961
962/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
963 * @{
964 */
965#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
966#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
967#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
968#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /**< int xx */
969#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /**< Why are we getting this one?? */
970#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
971/** @} */
972
973
974/** @name VMCS field encoding - 32 Bits guest state fields
975 * @{
976 */
977#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
978#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
979#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
980#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
981#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
982#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
983#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
984#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
985#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
986#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
987#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
988#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
989#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
990#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
991#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
992#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
993#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
994#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
995#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
996#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
997#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
998#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
999/** @} */
1000
1001
1002/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
1003 * @{
1004 */
1005/** The logical processor is active. */
1006#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
1007/** The logical processor is inactive, because executed a HLT instruction. */
1008#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
1009/** The logical processor is inactive, because of a triple fault or other serious error. */
1010#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
1011/** The logical processor is inactive, because it's waiting for a startup-IPI */
1012#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
1013/** @} */
1014
1015
1016/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
1017 * @{
1018 */
1019#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
1020#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
1021#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
1022#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
1023/** @} */
1024
1025
1026/** @name VMCS field encoding - 32 Bits host state fields
1027 * @{
1028 */
1029#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
1030/** @} */
1031
1032/** @name Natural width control fields
1033 * @{
1034 */
1035#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1036#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1037#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1038#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1039#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1040#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1041#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1042#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1043/** @} */
1044
1045
1046/** @name Natural width read-only data fields
1047 * @{
1048 */
1049#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1050#define VMX_VMCS_RO_IO_RCX 0x6402
1051#define VMX_VMCS_RO_IO_RSX 0x6404
1052#define VMX_VMCS_RO_IO_RDI 0x6406
1053#define VMX_VMCS_RO_IO_RIP 0x6408
1054#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1055/** @} */
1056
1057
1058/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1059 * @{
1060 */
1061/** 0-2: Debug register number */
1062#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1063/** 3: Reserved; cleared to 0. */
1064#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1065/** 4: Direction of move (0 = write, 1 = read) */
1066#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1067/** 5-7: Reserved; cleared to 0. */
1068#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1069/** 8-11: General purpose register number. */
1070#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1071/** Rest: reserved. */
1072/** @} */
1073
1074/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1075 * @{
1076 */
1077#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1078#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1079/** @} */
1080
1081
1082
1083/** @name CRx accesses
1084 * @{
1085 */
1086/** 0-3: Control register number (0 for CLTS & LMSW) */
1087#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1088/** 4-5: Access type. */
1089#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1090/** 6: LMSW operand type */
1091#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1092/** 7: Reserved; cleared to 0. */
1093#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1094/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1095#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1096/** 12-15: Reserved; cleared to 0. */
1097#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1098/** 16-31: LMSW source data (else 0). */
1099#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1100/** Rest: reserved. */
1101/** @} */
1102
1103/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1104 * @{
1105 */
1106#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1107#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1108#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1109#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1110/** @} */
1111
1112/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
1113 * @{
1114 */
1115#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
1116#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a) ((a >> 30)& 0x3)
1117/** Task switch caused by a call instruction. */
1118#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL 0
1119/** Task switch caused by an iret instruction. */
1120#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET 1
1121/** Task switch caused by a jmp instruction. */
1122#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP 2
1123/** Task switch caused by an interrupt gate. */
1124#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT 3
1125
1126/** @} */
1127
1128
1129/** @name VMX_EXIT_EPT_VIOLATION
1130 * @{
1131 */
1132/** Set if the violation was caused by a data read. */
1133#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1134/** Set if the violation was caused by a data write. */
1135#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1136/** Set if the violation was caused by an insruction fetch. */
1137#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1138/** AND of the present bit of all EPT structures. */
1139#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1140/** AND of the write bit of all EPT structures. */
1141#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1142/** AND of the execute bit of all EPT structures. */
1143#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1144/** Set if the guest linear address field contains the faulting address. */
1145#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1146/** If bit 7 is one: (reserved otherwise)
1147 * 1 - violation due to physical address access.
1148 * 0 - violation caused by page walk or access/dirty bit updates
1149 */
1150#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1151/** @} */
1152
1153
1154/** @name VMX_EXIT_PORT_IO
1155 * @{
1156 */
1157/** 0-2: IO operation width. */
1158#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1159/** 3: IO operation direction. */
1160#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1161/** 4: String IO operation. */
1162#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1163/** 5: Repeated IO operation. */
1164#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1165/** 6: Operand encoding. */
1166#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1167/** 16-31: IO Port (0-0xffff). */
1168#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1169/* Rest reserved. */
1170/** @} */
1171
1172/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1173 * @{
1174 */
1175#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1176#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1177/** @} */
1178
1179
1180/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1181 * @{
1182 */
1183#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1184#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1185/** @} */
1186
1187/** @name VMX_EXIT_APIC_ACCESS
1188 * @{
1189 */
1190/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1191#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1192/** 12-15: Access type. */
1193#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1194/* Rest reserved. */
1195/** @} */
1196
1197
1198/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1199 * @{
1200 */
1201/** Linear read access. */
1202#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1203/** Linear write access. */
1204#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1205/** Linear instruction fetch access. */
1206#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1207/** Linear read/write access during event delivery. */
1208#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1209/** Physical read/write access during event delivery. */
1210#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1211/** Physical access for an instruction fetch or during instruction execution. */
1212#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1213/** @} */
1214
1215/** @} */
1216
1217/** @name VMCS field encoding - Natural width guest state fields
1218 * @{
1219 */
1220#define VMX_VMCS64_GUEST_CR0 0x6800
1221#define VMX_VMCS64_GUEST_CR3 0x6802
1222#define VMX_VMCS64_GUEST_CR4 0x6804
1223#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1224#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1225#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1226#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1227#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1228#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1229#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1230#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1231#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1232#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1233#define VMX_VMCS64_GUEST_DR7 0x681A
1234#define VMX_VMCS64_GUEST_RSP 0x681C
1235#define VMX_VMCS64_GUEST_RIP 0x681E
1236#define VMX_VMCS_GUEST_RFLAGS 0x6820
1237#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1238#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1239#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1240/** @} */
1241
1242
1243/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1244 * @{
1245 */
1246/** Hardware breakpoint 0 was met. */
1247#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1248/** Hardware breakpoint 1 was met. */
1249#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1250/** Hardware breakpoint 2 was met. */
1251#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1252/** Hardware breakpoint 3 was met. */
1253#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1254/** At least one data or IO breakpoint was hit. */
1255#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1256/** A debug exception would have been triggered by single-step execution mode. */
1257#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1258/** Bits 4-11, 13 and 15-63 are reserved. */
1259
1260/** @} */
1261
1262/** @name VMCS field encoding - Natural width host state fields
1263 * @{
1264 */
1265#define VMX_VMCS_HOST_CR0 0x6C00
1266#define VMX_VMCS_HOST_CR3 0x6C02
1267#define VMX_VMCS_HOST_CR4 0x6C04
1268#define VMX_VMCS_HOST_FS_BASE 0x6C06
1269#define VMX_VMCS_HOST_GS_BASE 0x6C08
1270#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1271#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1272#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1273#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1274#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1275#define VMX_VMCS_HOST_RSP 0x6C14
1276#define VMX_VMCS_HOST_RIP 0x6C16
1277/** @} */
1278
1279/** @} */
1280
1281
1282#if RT_INLINE_ASM_GNU_STYLE
1283# define __STR(x) #x
1284# define STR(x) __STR(x)
1285#endif
1286
1287
1288/** @defgroup grp_vmx_asm vmx assembly helpers
1289 * @ingroup grp_vmx
1290 * @{
1291 */
1292
1293/**
1294 * Executes VMXON
1295 *
1296 * @returns VBox status code
1297 * @param pVMXOn Physical address of VMXON structure
1298 */
1299#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1300DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1301#else
1302DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1303{
1304 int rc = VINF_SUCCESS;
1305# if RT_INLINE_ASM_GNU_STYLE
1306 __asm__ __volatile__ (
1307 "push %3 \n\t"
1308 "push %2 \n\t"
1309 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1310 "ja 2f \n\t"
1311 "je 1f \n\t"
1312 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1313 "jmp 2f \n\t"
1314 "1: \n\t"
1315 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1316 "2: \n\t"
1317 "add $8, %%esp \n\t"
1318 :"=rm"(rc)
1319 :"0"(VINF_SUCCESS),
1320 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1321 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1322 :"memory"
1323 );
1324# else
1325 __asm
1326 {
1327 push dword ptr [pVMXOn+4]
1328 push dword ptr [pVMXOn]
1329 _emit 0xF3
1330 _emit 0x0F
1331 _emit 0xC7
1332 _emit 0x34
1333 _emit 0x24 /* VMXON [esp] */
1334 jnc vmxon_good
1335 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1336 jmp the_end
1337
1338vmxon_good:
1339 jnz the_end
1340 mov dword ptr [rc], VERR_VMX_GENERIC
1341the_end:
1342 add esp, 8
1343 }
1344# endif
1345 return rc;
1346}
1347#endif
1348
1349
1350/**
1351 * Executes VMXOFF
1352 */
1353#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1354DECLASM(void) VMXDisable(void);
1355#else
1356DECLINLINE(void) VMXDisable(void)
1357{
1358# if RT_INLINE_ASM_GNU_STYLE
1359 __asm__ __volatile__ (
1360 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1361 );
1362# else
1363 __asm
1364 {
1365 _emit 0x0F
1366 _emit 0x01
1367 _emit 0xC4 /* VMXOFF */
1368 }
1369# endif
1370}
1371#endif
1372
1373
1374/**
1375 * Executes VMCLEAR
1376 *
1377 * @returns VBox status code
1378 * @param pVMCS Physical address of VM control structure
1379 */
1380#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1381DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1382#else
1383DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1384{
1385 int rc = VINF_SUCCESS;
1386# if RT_INLINE_ASM_GNU_STYLE
1387 __asm__ __volatile__ (
1388 "push %3 \n\t"
1389 "push %2 \n\t"
1390 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1391 "jnc 1f \n\t"
1392 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1393 "1: \n\t"
1394 "add $8, %%esp \n\t"
1395 :"=rm"(rc)
1396 :"0"(VINF_SUCCESS),
1397 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1398 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1399 :"memory"
1400 );
1401# else
1402 __asm
1403 {
1404 push dword ptr [pVMCS+4]
1405 push dword ptr [pVMCS]
1406 _emit 0x66
1407 _emit 0x0F
1408 _emit 0xC7
1409 _emit 0x34
1410 _emit 0x24 /* VMCLEAR [esp] */
1411 jnc success
1412 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1413success:
1414 add esp, 8
1415 }
1416# endif
1417 return rc;
1418}
1419#endif
1420
1421
1422/**
1423 * Executes VMPTRLD
1424 *
1425 * @returns VBox status code
1426 * @param pVMCS Physical address of VMCS structure
1427 */
1428#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1429DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1430#else
1431DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1432{
1433 int rc = VINF_SUCCESS;
1434# if RT_INLINE_ASM_GNU_STYLE
1435 __asm__ __volatile__ (
1436 "push %3 \n\t"
1437 "push %2 \n\t"
1438 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1439 "jnc 1f \n\t"
1440 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1441 "1: \n\t"
1442 "add $8, %%esp \n\t"
1443 :"=rm"(rc)
1444 :"0"(VINF_SUCCESS),
1445 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1446 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1447 );
1448# else
1449 __asm
1450 {
1451 push dword ptr [pVMCS+4]
1452 push dword ptr [pVMCS]
1453 _emit 0x0F
1454 _emit 0xC7
1455 _emit 0x34
1456 _emit 0x24 /* VMPTRLD [esp] */
1457 jnc success
1458 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1459
1460success:
1461 add esp, 8
1462 }
1463# endif
1464 return rc;
1465}
1466#endif
1467
1468/**
1469 * Executes VMPTRST
1470 *
1471 * @returns VBox status code
1472 * @param pVMCS Address that will receive the current pointer
1473 */
1474DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1475
1476/**
1477 * Executes VMWRITE
1478 *
1479 * @returns VBox status code
1480 * @param idxField VMCS index
1481 * @param u32Val 32 bits value
1482 */
1483#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1484DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1485#else
1486DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1487{
1488 int rc = VINF_SUCCESS;
1489# if RT_INLINE_ASM_GNU_STYLE
1490 __asm__ __volatile__ (
1491 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1492 "ja 2f \n\t"
1493 "je 1f \n\t"
1494 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1495 "jmp 2f \n\t"
1496 "1: \n\t"
1497 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1498 "2: \n\t"
1499 :"=rm"(rc)
1500 :"0"(VINF_SUCCESS),
1501 "a"(idxField),
1502 "d"(u32Val)
1503 );
1504# else
1505 __asm
1506 {
1507 push dword ptr [u32Val]
1508 mov eax, [idxField]
1509 _emit 0x0F
1510 _emit 0x79
1511 _emit 0x04
1512 _emit 0x24 /* VMWRITE eax, [esp] */
1513 jnc valid_vmcs
1514 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1515 jmp the_end
1516
1517valid_vmcs:
1518 jnz the_end
1519 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1520the_end:
1521 add esp, 4
1522 }
1523# endif
1524 return rc;
1525}
1526#endif
1527
1528/**
1529 * Executes VMWRITE
1530 *
1531 * @returns VBox status code
1532 * @param idxField VMCS index
1533 * @param u64Val 16, 32 or 64 bits value
1534 */
1535#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1536DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1537#else
1538VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1539
1540#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1541#endif
1542
1543#if HC_ARCH_BITS == 64
1544#define VMXWriteVMCS VMXWriteVMCS64
1545#else
1546#define VMXWriteVMCS VMXWriteVMCS32
1547#endif /* HC_ARCH_BITS == 64 */
1548
1549
1550/**
1551 * Invalidate a page using invept
1552 * @returns VBox status code
1553 * @param enmFlush Type of flush
1554 * @param pDescriptor Descriptor
1555 */
1556DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1557
1558/**
1559 * Invalidate a page using invvpid
1560 * @returns VBox status code
1561 * @param enmFlush Type of flush
1562 * @param pDescriptor Descriptor
1563 */
1564DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1565
1566/**
1567 * Executes VMREAD
1568 *
1569 * @returns VBox status code
1570 * @param idxField VMCS index
1571 * @param pData Ptr to store VM field value
1572 */
1573#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1574DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1575#else
1576DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1577{
1578 int rc = VINF_SUCCESS;
1579# if RT_INLINE_ASM_GNU_STYLE
1580 __asm__ __volatile__ (
1581 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1582 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1583 "ja 2f \n\t"
1584 "je 1f \n\t"
1585 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1586 "jmp 2f \n\t"
1587 "1: \n\t"
1588 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1589 "2: \n\t"
1590 :"=&r"(rc),
1591 "=d"(*pData)
1592 :"a"(idxField),
1593 "d"(0)
1594 );
1595# else
1596 __asm
1597 {
1598 sub esp, 4
1599 mov dword ptr [esp], 0
1600 mov eax, [idxField]
1601 _emit 0x0F
1602 _emit 0x78
1603 _emit 0x04
1604 _emit 0x24 /* VMREAD eax, [esp] */
1605 mov edx, pData
1606 pop dword ptr [edx]
1607 jnc valid_vmcs
1608 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1609 jmp the_end
1610
1611valid_vmcs:
1612 jnz the_end
1613 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1614the_end:
1615 }
1616# endif
1617 return rc;
1618}
1619#endif
1620
1621/**
1622 * Executes VMREAD
1623 *
1624 * @returns VBox status code
1625 * @param idxField VMCS index
1626 * @param pData Ptr to store VM field value
1627 */
1628#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1629DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1630#else
1631DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1632{
1633 int rc;
1634
1635 uint32_t val_hi, val;
1636 rc = VMXReadVMCS32(idxField, &val);
1637 rc |= VMXReadVMCS32(idxField + 1, &val_hi);
1638 AssertRC(rc);
1639 *pData = RT_MAKE_U64(val, val_hi);
1640 return rc;
1641}
1642#endif
1643
1644#if HC_ARCH_BITS == 64
1645# define VMXReadVMCS VMXReadVMCS64
1646#else
1647# define VMXReadVMCS VMXReadVMCS32
1648#endif /* HC_ARCH_BITS == 64 */
1649
1650/**
1651 * Gets the last instruction error value from the current VMCS
1652 *
1653 * @returns error value
1654 */
1655DECLINLINE(uint32_t) VMXGetLastError(void)
1656{
1657#if HC_ARCH_BITS == 64
1658 uint64_t uLastError = 0;
1659 int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1660 AssertRC(rc);
1661 return (uint32_t)uLastError;
1662
1663#else /* 32-bit host: */
1664 uint32_t uLastError = 0;
1665 int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1666 AssertRC(rc);
1667 return uLastError;
1668#endif
1669}
1670
1671#ifdef IN_RING0
1672VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1673VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1674#endif /* IN_RING0 */
1675
1676/** @} */
1677
1678#endif
1679
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