VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 21217

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1/** @file
2 * HWACCM - VMX Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_vmx_h
31#define ___VBox_vmx_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37#include <VBox/x86.h>
38
39/** @defgroup grp_vmx vmx Types and Definitions
40 * @ingroup grp_hwaccm
41 * @{
42 */
43
44/** @name VMX EPT paging structures
45 * @{
46 */
47
48/**
49 * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
50 */
51#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
52
53/**
54 * EPT Page Directory Pointer Entry. Bit view.
55 * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
56 * this did cause trouble with one compiler/version).
57 */
58#pragma pack(1)
59typedef struct EPTPML4EBITS
60{
61 /** Present bit. */
62 uint64_t u1Present : 1;
63 /** Writable bit. */
64 uint64_t u1Write : 1;
65 /** Executable bit. */
66 uint64_t u1Execute : 1;
67 /** Reserved (must be 0). */
68 uint64_t u5Reserved : 5;
69 /** Available for software. */
70 uint64_t u4Available : 4;
71 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
72 uint64_t u40PhysAddr : 40;
73 /** Availabe for software. */
74 uint64_t u12Available : 12;
75} EPTPML4EBITS;
76#pragma pack()
77AssertCompileSize(EPTPML4EBITS, 8);
78
79/** Bits 12-51 - - EPT - Physical Page number of the next level. */
80#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK_FULL
81/** The page shift to get the PML4 index. */
82#define EPT_PML4_SHIFT X86_PML4_SHIFT
83/** The PML4 index mask (apply to a shifted page address). */
84#define EPT_PML4_MASK X86_PML4_MASK
85
86/**
87 * EPT PML4E.
88 */
89#pragma pack(1)
90typedef union EPTPML4E
91{
92 /** Normal view. */
93 EPTPML4EBITS n;
94 /** Unsigned integer view. */
95 X86PGPAEUINT u;
96 /** 64 bit unsigned integer view. */
97 uint64_t au64[1];
98 /** 32 bit unsigned integer view. */
99 uint32_t au32[2];
100} EPTPML4E;
101#pragma pack()
102/** Pointer to a PML4 table entry. */
103typedef EPTPML4E *PEPTPML4E;
104/** Pointer to a const PML4 table entry. */
105typedef const EPTPML4E *PCEPTPML4E;
106AssertCompileSize(EPTPML4E, 8);
107
108/**
109 * EPT PML4 Table.
110 */
111#pragma pack(1)
112typedef struct EPTPML4
113{
114 EPTPML4E a[EPT_PG_ENTRIES];
115} EPTPML4;
116#pragma pack()
117/** Pointer to an EPT PML4 Table. */
118typedef EPTPML4 *PEPTPML4;
119/** Pointer to a const EPT PML4 Table. */
120typedef const EPTPML4 *PCEPTPML4;
121
122/**
123 * EPT Page Directory Pointer Entry. Bit view.
124 */
125#pragma pack(1)
126typedef struct EPTPDPTEBITS
127{
128 /** Present bit. */
129 uint64_t u1Present : 1;
130 /** Writable bit. */
131 uint64_t u1Write : 1;
132 /** Executable bit. */
133 uint64_t u1Execute : 1;
134 /** Reserved (must be 0). */
135 uint64_t u5Reserved : 5;
136 /** Available for software. */
137 uint64_t u4Available : 4;
138 /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
139 uint64_t u40PhysAddr : 40;
140 /** Availabe for software. */
141 uint64_t u12Available : 12;
142} EPTPDPTEBITS;
143#pragma pack()
144AssertCompileSize(EPTPDPTEBITS, 8);
145
146/** Bits 12-51 - - EPT - Physical Page number of the next level. */
147#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK_FULL
148/** The page shift to get the PDPT index. */
149#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
150/** The PDPT index mask (apply to a shifted page address). */
151#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
152
153/**
154 * EPT Page Directory Pointer.
155 */
156#pragma pack(1)
157typedef union EPTPDPTE
158{
159 /** Normal view. */
160 EPTPDPTEBITS n;
161 /** Unsigned integer view. */
162 X86PGPAEUINT u;
163 /** 64 bit unsigned integer view. */
164 uint64_t au64[1];
165 /** 32 bit unsigned integer view. */
166 uint32_t au32[2];
167} EPTPDPTE;
168#pragma pack()
169/** Pointer to an EPT Page Directory Pointer Entry. */
170typedef EPTPDPTE *PEPTPDPTE;
171/** Pointer to a const EPT Page Directory Pointer Entry. */
172typedef const EPTPDPTE *PCEPTPDPTE;
173AssertCompileSize(EPTPDPTE, 8);
174
175/**
176 * EPT Page Directory Pointer Table.
177 */
178#pragma pack(1)
179typedef struct EPTPDPT
180{
181 EPTPDPTE a[EPT_PG_ENTRIES];
182} EPTPDPT;
183#pragma pack()
184/** Pointer to an EPT Page Directory Pointer Table. */
185typedef EPTPDPT *PEPTPDPT;
186/** Pointer to a const EPT Page Directory Pointer Table. */
187typedef const EPTPDPT *PCEPTPDPT;
188
189
190/**
191 * EPT Page Directory Table Entry. Bit view.
192 */
193#pragma pack(1)
194typedef struct EPTPDEBITS
195{
196 /** Present bit. */
197 uint64_t u1Present : 1;
198 /** Writable bit. */
199 uint64_t u1Write : 1;
200 /** Executable bit. */
201 uint64_t u1Execute : 1;
202 /** Reserved (must be 0). */
203 uint64_t u4Reserved : 4;
204 /** Big page (must be 0 here). */
205 uint64_t u1Big : 1;
206 /** Available for software. */
207 uint64_t u4Available : 4;
208 /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
209 uint64_t u40PhysAddr : 40;
210 /** Availabe for software. */
211 uint64_t u12Available : 12;
212} EPTPDEBITS;
213#pragma pack()
214AssertCompileSize(EPTPDEBITS, 8);
215
216/** Bits 12-51 - - EPT - Physical Page number of the next level. */
217#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
218/** The page shift to get the PD index. */
219#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
220/** The PD index mask (apply to a shifted page address). */
221#define EPT_PD_MASK X86_PD_PAE_MASK
222
223/**
224 * EPT 2MB Page Directory Table Entry. Bit view.
225 */
226#pragma pack(1)
227typedef struct EPTPDE2MBITS
228{
229 /** Present bit. */
230 uint64_t u1Present : 1;
231 /** Writable bit. */
232 uint64_t u1Write : 1;
233 /** Executable bit. */
234 uint64_t u1Execute : 1;
235 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
236 uint64_t u3EMT : 3;
237 /** Ignore PAT memory type */
238 uint64_t u1IgnorePAT : 1;
239 /** Big page (must be 1 here). */
240 uint64_t u1Size : 1;
241 /** Available for software. */
242 uint64_t u4Available : 4;
243 /** Reserved (must be 0). */
244 uint64_t u9Reserved : 9;
245 /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
246 uint64_t u31PhysAddr : 31;
247 /** Availabe for software. */
248 uint64_t u12Available : 12;
249} EPTPDE2MBITS;
250#pragma pack()
251AssertCompileSize(EPTPDE2MBITS, 8);
252
253/** Bits 21-51 - - EPT - Physical Page number of the next level. */
254#define EPT_PDE2M_PG_MASK ( 0x000fffffffe00000ULL )
255
256/**
257 * EPT Page Directory Table Entry.
258 */
259#pragma pack(1)
260typedef union EPTPDE
261{
262 /** Normal view. */
263 EPTPDEBITS n;
264 /** 2MB view (big). */
265 EPTPDE2MBITS b;
266 /** Unsigned integer view. */
267 X86PGPAEUINT u;
268 /** 64 bit unsigned integer view. */
269 uint64_t au64[1];
270 /** 32 bit unsigned integer view. */
271 uint32_t au32[2];
272} EPTPDE;
273#pragma pack()
274/** Pointer to an EPT Page Directory Table Entry. */
275typedef EPTPDE *PEPTPDE;
276/** Pointer to a const EPT Page Directory Table Entry. */
277typedef const EPTPDE *PCEPTPDE;
278AssertCompileSize(EPTPDE, 8);
279
280/**
281 * EPT Page Directory Table.
282 */
283#pragma pack(1)
284typedef struct EPTPD
285{
286 EPTPDE a[EPT_PG_ENTRIES];
287} EPTPD;
288#pragma pack()
289/** Pointer to an EPT Page Directory Table. */
290typedef EPTPD *PEPTPD;
291/** Pointer to a const EPT Page Directory Table. */
292typedef const EPTPD *PCEPTPD;
293
294
295/**
296 * EPT Page Table Entry. Bit view.
297 */
298#pragma pack(1)
299typedef struct EPTPTEBITS
300{
301 /** Present bit. */
302 uint64_t u1Present : 1;
303 /** Writable bit. */
304 uint64_t u1Write : 1;
305 /** Executable bit. */
306 uint64_t u1Execute : 1;
307 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
308 uint64_t u3EMT : 3;
309 /** Ignore PAT memory type */
310 uint64_t u1IgnorePAT : 1;
311 /** Available for software. */
312 uint64_t u5Available : 5;
313 /** Physical address of page. Restricted by maximum physical address width of the cpu. */
314 uint64_t u40PhysAddr : 40;
315 /** Availabe for software. */
316 uint64_t u12Available : 12;
317} EPTPTEBITS;
318#pragma pack()
319AssertCompileSize(EPTPTEBITS, 8);
320
321/** Bits 12-51 - - EPT - Physical Page number of the next level. */
322#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
323/** The page shift to get the EPT PTE index. */
324#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
325/** The EPT PT index mask (apply to a shifted page address). */
326#define EPT_PT_MASK X86_PT_PAE_MASK
327
328/**
329 * EPT Page Table Entry.
330 */
331#pragma pack(1)
332typedef union EPTPTE
333{
334 /** Normal view. */
335 EPTPTEBITS n;
336 /** Unsigned integer view. */
337 X86PGPAEUINT u;
338 /** 64 bit unsigned integer view. */
339 uint64_t au64[1];
340 /** 32 bit unsigned integer view. */
341 uint32_t au32[2];
342} EPTPTE;
343#pragma pack()
344/** Pointer to an EPT Page Directory Table Entry. */
345typedef EPTPTE *PEPTPTE;
346/** Pointer to a const EPT Page Directory Table Entry. */
347typedef const EPTPTE *PCEPTPTE;
348AssertCompileSize(EPTPTE, 8);
349
350/**
351 * EPT Page Table.
352 */
353#pragma pack(1)
354typedef struct EPTPT
355{
356 EPTPTE a[EPT_PG_ENTRIES];
357} EPTPT;
358#pragma pack()
359/** Pointer to an extended page table. */
360typedef EPTPT *PEPTPT;
361/** Pointer to a const extended table. */
362typedef const EPTPT *PCEPTPT;
363
364/**
365 * VPID and EPT flush types
366 */
367typedef enum
368{
369 /* Invalidate a specific page. */
370 VMX_FLUSH_PAGE = 0,
371 /* Invalidate one context (VPID or EPT) */
372 VMX_FLUSH_SINGLE_CONTEXT = 1,
373 /* Invalidate all contexts (VPIDs or EPTs) */
374 VMX_FLUSH_ALL_CONTEXTS = 2,
375 /* Invalidate a single VPID context retaining global mappings. */
376 VMX_FLUSH_SINGLE_CONTEXT_WITHOUT_GLOBAL = 3,
377 /** 32bit hackishness. */
378 VMX_FLUSH_32BIT_HACK = 0x7fffffff
379} VMX_FLUSH;
380
381/** @} */
382
383
384/** @name VMX Basic Exit Reasons.
385 * @{
386 */
387/** And-mask for setting reserved bits to zero */
388#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
389/** Or-mask for setting reserved bits to 1 */
390#define VMX_EFLAGS_RESERVED_1 0x00000002
391/** @} */
392
393/** @name VMX Basic Exit Reasons.
394 * @{
395 */
396/** -1 Invalid exit code */
397#define VMX_EXIT_INVALID -1
398/** 0 Exception or non-maskable interrupt (NMI). */
399#define VMX_EXIT_EXCEPTION 0
400/** 1 External interrupt. */
401#define VMX_EXIT_EXTERNAL_IRQ 1
402/** 2 Triple fault. */
403#define VMX_EXIT_TRIPLE_FAULT 2
404/** 3 INIT signal. */
405#define VMX_EXIT_INIT_SIGNAL 3
406/** 4 Start-up IPI (SIPI). */
407#define VMX_EXIT_SIPI 4
408/** 5 I/O system-management interrupt (SMI). */
409#define VMX_EXIT_IO_SMI_IRQ 5
410/** 6 Other SMI. */
411#define VMX_EXIT_SMI_IRQ 6
412/** 7 Interrupt window. */
413#define VMX_EXIT_IRQ_WINDOW 7
414/** 9 Task switch. */
415#define VMX_EXIT_TASK_SWITCH 9
416/** 10 Guest software attempted to execute CPUID. */
417#define VMX_EXIT_CPUID 10
418/** 12 Guest software attempted to execute HLT. */
419#define VMX_EXIT_HLT 12
420/** 13 Guest software attempted to execute INVD. */
421#define VMX_EXIT_INVD 13
422/** 14 Guest software attempted to execute INVPG. */
423#define VMX_EXIT_INVPG 14
424/** 15 Guest software attempted to execute RDPMC. */
425#define VMX_EXIT_RDPMC 15
426/** 16 Guest software attempted to execute RDTSC. */
427#define VMX_EXIT_RDTSC 16
428/** 17 Guest software attempted to execute RSM in SMM. */
429#define VMX_EXIT_RSM 17
430/** 18 Guest software executed VMCALL. */
431#define VMX_EXIT_VMCALL 18
432/** 19 Guest software executed VMCLEAR. */
433#define VMX_EXIT_VMCLEAR 19
434/** 20 Guest software executed VMLAUNCH. */
435#define VMX_EXIT_VMLAUNCH 20
436/** 21 Guest software executed VMPTRLD. */
437#define VMX_EXIT_VMPTRLD 21
438/** 22 Guest software executed VMPTRST. */
439#define VMX_EXIT_VMPTRST 22
440/** 23 Guest software executed VMREAD. */
441#define VMX_EXIT_VMREAD 23
442/** 24 Guest software executed VMRESUME. */
443#define VMX_EXIT_VMRESUME 24
444/** 25 Guest software executed VMWRITE. */
445#define VMX_EXIT_VMWRITE 25
446/** 26 Guest software executed VMXOFF. */
447#define VMX_EXIT_VMXOFF 26
448/** 27 Guest software executed VMXON. */
449#define VMX_EXIT_VMXON 27
450/** 28 Control-register accesses. */
451#define VMX_EXIT_CRX_MOVE 28
452/** 29 Debug-register accesses. */
453#define VMX_EXIT_DRX_MOVE 29
454/** 30 I/O instruction. */
455#define VMX_EXIT_PORT_IO 30
456/** 31 RDMSR. Guest software attempted to execute RDMSR. */
457#define VMX_EXIT_RDMSR 31
458/** 32 WRMSR. Guest software attempted to execute WRMSR. */
459#define VMX_EXIT_WRMSR 32
460/** 33 VM-entry failure due to invalid guest state. */
461#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
462/** 34 VM-entry failure due to MSR loading. */
463#define VMX_EXIT_ERR_MSR_LOAD 34
464/** 36 Guest software executed MWAIT. */
465#define VMX_EXIT_MWAIT 36
466/** 39 Guest software attempted to execute MONITOR. */
467#define VMX_EXIT_MONITOR 39
468/** 40 Guest software attempted to execute PAUSE. */
469#define VMX_EXIT_PAUSE 40
470/** 41 VM-entry failure due to machine-check. */
471#define VMX_EXIT_ERR_MACHINE_CHECK 41
472/** 43 TPR below threshold. Guest software executed MOV to CR8. */
473#define VMX_EXIT_TPR 43
474/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
475#define VMX_EXIT_APIC_ACCESS 44
476/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
477#define VMX_EXIT_XDTR_ACCESS 46
478/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
479#define VMX_EXIT_TR_ACCESS 47
480/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
481#define VMX_EXIT_EPT_VIOLATION 48
482/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
483#define VMX_EXIT_EPT_MISCONFIG 49
484/** 50 INVEPT. Guest software attempted to execute INVEPT. */
485#define VMX_EXIT_INVEPT 50
486/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
487#define VMX_EXIT_PREEMPTION_TIMER 52
488/** 53 INVVPID. Guest software attempted to execute INVVPID. */
489#define VMX_EXIT_INVVPID 53
490/** 54 WBINVD. Guest software attempted to execute WBINVD. */
491#define VMX_EXIT_WBINVD 54
492/** 55 XSETBV. Guest software attempted to execute XSETBV. */
493#define VMX_EXIT_XSETBV 55
494/** @} */
495
496
497/** @name VM Instruction Errors
498 * @{
499 */
500/** 1 VMCALL executed in VMX root operation. */
501#define VMX_ERROR_VMCALL 1
502/** 2 VMCLEAR with invalid physical address. */
503#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
504/** 3 VMCLEAR with VMXON pointer. */
505#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
506/** 4 VMLAUNCH with non-clear VMCS. */
507#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
508/** 5 VMRESUME with non-launched VMCS. */
509#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
510/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
511#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
512/** 7 VM entry with invalid control field(s). */
513#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
514/** 8 VM entry with invalid host-state field(s). */
515#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
516/** 9 VMPTRLD with invalid physical address. */
517#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
518/** 10 VMPTRLD with VMXON pointer. */
519#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
520/** 11 VMPTRLD with incorrect VMCS revision identifier. */
521#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
522/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
523#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
524#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
525/** 13 VMWRITE to read-only VMCS component. */
526#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
527/** 15 VMXON executed in VMX root operation. */
528#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
529/** 16 VM entry with invalid executive-VMCS pointer. */
530#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
531/** 17 VM entry with non-launched executive VMCS. */
532#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
533/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
534#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
535/** 19 VMCALL with non-clear VMCS. */
536#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
537/** 20 VMCALL with invalid VM-exit control fields. */
538#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
539/** 22 VMCALL with incorrect MSEG revision identifier. */
540#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
541/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
542#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
543/** 24 VMCALL with invalid SMM-monitor features. */
544#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
545/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
546#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
547/** 26 VM entry with events blocked by MOV SS. */
548#define VMX_ERROR_VMENTRY_MOV_SS 26
549/** 26 Invalid operand to INVEPT/INVVPID. */
550#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
551
552/** @} */
553
554
555/** @name VMX MSRs - Basic VMX information.
556 * @{
557 */
558/** VMCS revision identifier used by the processor. */
559#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
560/** Size of the VMCS. */
561#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
562/** Width of physical address used for the VMCS.
563 * 0 -> limited to the available amount of physical ram
564 * 1 -> within the first 4 GB
565 */
566#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
567/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
568#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
569/** Memory type that must be used for the VMCS. */
570#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
571/** @} */
572
573
574/** @name VMX MSRs - Misc VMX info.
575 * @{
576 */
577/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
578#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) (a & 0x1f)
579/** Activity states supported by the implementation. */
580#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
581/** Number of CR3 target values supported by the processor. (0-256) */
582#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
583/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
584#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
585/** MSEG revision identifier used by the processor. */
586#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
587/** @} */
588
589
590/** @name VMX MSRs - VMCS enumeration field info
591 * @{
592 */
593/** Highest field index. */
594#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
595
596/** @} */
597
598
599/** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
600 * @{
601 */
602#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
603#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
604#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
605#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
606#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
607#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
608#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
609#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
610#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
611#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
612#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
613#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
614#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
615#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
616#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
617#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
618#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
619#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
620#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
621#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
622#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
623#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
624#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
625#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
626#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
627#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
628
629/** @} */
630
631/** @name Extended Page Table Pointer (EPTP)
632 * @{
633 */
634/** Uncachable EPT paging structure memory type. */
635#define VMX_EPT_MEMTYPE_UC 0
636/** Write-back EPT paging structure memory type. */
637#define VMX_EPT_MEMTYPE_WB 6
638/** Shift value to get the EPT page walk length (bits 5-3) */
639#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
640/** Mask value to get the EPT page walk length (bits 5-3) */
641#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
642/** Default EPT page walk length */
643#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
644/** @} */
645
646
647/** @name VMCS field encoding - 16 bits guest fields
648 * @{
649 */
650#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
651#define VMX_VMCS16_GUEST_FIELD_ES 0x800
652#define VMX_VMCS16_GUEST_FIELD_CS 0x802
653#define VMX_VMCS16_GUEST_FIELD_SS 0x804
654#define VMX_VMCS16_GUEST_FIELD_DS 0x806
655#define VMX_VMCS16_GUEST_FIELD_FS 0x808
656#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
657#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
658#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
659/** @} */
660
661/** @name VMCS field encoding - 16 bits host fields
662 * @{
663 */
664#define VMX_VMCS16_HOST_FIELD_ES 0xC00
665#define VMX_VMCS16_HOST_FIELD_CS 0xC02
666#define VMX_VMCS16_HOST_FIELD_SS 0xC04
667#define VMX_VMCS16_HOST_FIELD_DS 0xC06
668#define VMX_VMCS16_HOST_FIELD_FS 0xC08
669#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
670#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
671/** @} */
672
673/** @name VMCS field encoding - 64 bits host fields
674 * @{
675 */
676#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
677#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
678#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
679#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
680#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /**< MSR IA32_PERF_GLOBAL_CTRL */
681#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /**< MSR IA32_PERF_GLOBAL_CTRL */
682/** @} */
683
684
685/** @name VMCS field encoding - 64 Bits control fields
686 * @{
687 */
688#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
689#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
690#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
691#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
692
693/* Optional */
694#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
695#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
696
697#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
698#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
699#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
700#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
701
702#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
703#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
704
705#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
706#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
707
708#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
709#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
710
711/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
712#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
713#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
714
715/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
716#define VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL 0x2014
717#define VMX_VMCS_CTRL_APIC_ACCESSADDR_HIGH 0x2015
718
719/** Extended page table pointer. */
720#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
721#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
722
723/** VM-exit phyiscal address. */
724#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
725#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
726/** @} */
727
728
729/** @name VMCS field encoding - 64 Bits guest fields
730 * @{
731 */
732#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
733#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
734#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /**< MSR IA32_DEBUGCTL */
735#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /**< MSR IA32_DEBUGCTL */
736#define VMX_VMCS_GUEST_PAT_FULL 0x2804
737#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
738#define VMX_VMCS_GUEST_EFER_FULL 0x2806
739#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
740#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /**< MSR IA32_PERF_GLOBAL_CTRL */
741#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /**< MSR IA32_PERF_GLOBAL_CTRL */
742#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
743#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
744#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
745#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
746#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
747#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
748#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
749#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
750/** @} */
751
752
753/** @name VMCS field encoding - 32 Bits control fields
754 * @{
755 */
756#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
757#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
758#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
759#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
760#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
761#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
762#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
763#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
764#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
765#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
766#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
767#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
768#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
769#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
770/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
771#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
772/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
773#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
774/** @} */
775
776
777/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
778 * @{
779 */
780/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
781#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
782/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
783#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
784/** Virtual NMIs. */
785#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI RT_BIT(5)
786/** Activate VMX preemption timer. */
787#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER RT_BIT(6)
788/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
789/** @} */
790
791/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
792 * @{
793 */
794/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
795#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
796/** Use timestamp counter offset. */
797#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
798/** VM Exit when executing the HLT instruction. */
799#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
800/** VM Exit when executing the INVLPG instruction. */
801#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
802/** VM Exit when executing the MWAIT instruction. */
803#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
804/** VM Exit when executing the RDPMC instruction. */
805#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
806/** VM Exit when executing the RDTSC instruction. */
807#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
808/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
809#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT RT_BIT(15)
810/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
811#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT RT_BIT(16)
812/** VM Exit on CR8 loads. */
813#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
814/** VM Exit on CR8 stores. */
815#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
816/** Use TPR shadow. */
817#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
818/** VM Exit when virtual nmi blocking is disabled. */
819#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT RT_BIT(22)
820/** VM Exit when executing a MOV DRx instruction. */
821#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
822/** VM Exit when executing IO instructions. */
823#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
824/** Use IO bitmaps. */
825#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
826/** Monitor trap flag. */
827#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG RT_BIT(27)
828/** Use MSR bitmaps. */
829#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
830/** VM Exit when executing the MONITOR instruction. */
831#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
832/** VM Exit when executing the PAUSE instruction. */
833#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
834/** Determines whether the secondary processor based VM-execution controls are used. */
835#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
836/** @} */
837
838/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
839 * @{
840 */
841/** Virtualize APIC access. */
842#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
843/** EPT supported/enabled. */
844#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
845/** Descriptor table instructions cause VM-exits. */
846#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT RT_BIT(2)
847/** Virtualize x2APIC mode. */
848#define VMX_VMCS_CTRL_PROC_EXEC2_X2APIC RT_BIT(4)
849/** VPID supported/enabled. */
850#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
851/** VM Exit when executing the WBINVD instruction. */
852#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
853/** @} */
854
855
856/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
857 * @{
858 */
859/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
860#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG RT_BIT(2)
861/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
862#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
863/** In SMM mode after VM-entry. */
864#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
865/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
866#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
867/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
868#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR RT_BIT(13)
869/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
870#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR RT_BIT(14)
871/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
872#define VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR RT_BIT(15)
873/** @} */
874
875
876/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
877 * @{
878 */
879/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
880#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG RT_BIT(2)
881/** Return to long mode after a VM-exit. */
882#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
883/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
884#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR RT_BIT(12)
885/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
886#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
887/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
888#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR RT_BIT(18)
889/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
890#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR RT_BIT(19)
891/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
892#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR RT_BIT(20)
893/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
894#define VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR RT_BIT(21)
895/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
896#define VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER RT_BIT(22)
897/** @} */
898
899/** @name VMCS field encoding - 32 Bits read-only fields
900 * @{
901 */
902#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
903#define VMX_VMCS32_RO_EXIT_REASON 0x4402
904#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
905#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
906#define VMX_VMCS32_RO_IDT_INFO 0x4408
907#define VMX_VMCS32_RO_IDT_ERRCODE 0x440A
908#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
909#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
910/** @} */
911
912/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
913 * @{
914 */
915#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
916#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
917#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
918#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
919#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
920#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
921#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
922#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
923/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
924#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
925/** @} */
926
927/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
928 * @{
929 */
930#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
931#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
932#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
933#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /**< int xx */
934#define VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT 5 /**< Why are we getting this one?? */
935#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
936/** @} */
937
938
939/** @name VMCS field encoding - 32 Bits guest state fields
940 * @{
941 */
942#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
943#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
944#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
945#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
946#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
947#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
948#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
949#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
950#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
951#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
952#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
953#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
954#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
955#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
956#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
957#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
958#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
959#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
960#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
961#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
962#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482A /**< MSR IA32_SYSENTER_CS */
963#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
964/** @} */
965
966
967/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
968 * @{
969 */
970/** The logical processor is active. */
971#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
972/** The logical processor is inactive, because executed a HLT instruction. */
973#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
974/** The logical processor is inactive, because of a triple fault or other serious error. */
975#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
976/** The logical processor is inactive, because it's waiting for a startup-IPI */
977#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
978/** @} */
979
980
981/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
982 * @{
983 */
984#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
985#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
986#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
987#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
988/** @} */
989
990
991/** @name VMCS field encoding - 32 Bits host state fields
992 * @{
993 */
994#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
995/** @} */
996
997/** @name Natural width control fields
998 * @{
999 */
1000#define VMX_VMCS_CTRL_CR0_MASK 0x6000
1001#define VMX_VMCS_CTRL_CR4_MASK 0x6002
1002#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
1003#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
1004#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
1005#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
1006#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
1007#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
1008/** @} */
1009
1010
1011/** @name Natural width read-only data fields
1012 * @{
1013 */
1014#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
1015#define VMX_VMCS_RO_IO_RCX 0x6402
1016#define VMX_VMCS_RO_IO_RSX 0x6404
1017#define VMX_VMCS_RO_IO_RDI 0x6406
1018#define VMX_VMCS_RO_IO_RIP 0x6408
1019#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
1020/** @} */
1021
1022
1023/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
1024 * @{
1025 */
1026/** 0-2: Debug register number */
1027#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
1028/** 3: Reserved; cleared to 0. */
1029#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
1030/** 4: Direction of move (0 = write, 1 = read) */
1031#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
1032/** 5-7: Reserved; cleared to 0. */
1033#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
1034/** 8-11: General purpose register number. */
1035#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
1036/** Rest: reserved. */
1037/** @} */
1038
1039/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
1040 * @{
1041 */
1042#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
1043#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
1044/** @} */
1045
1046
1047
1048/** @name CRx accesses
1049 * @{
1050 */
1051/** 0-3: Control register number (0 for CLTS & LMSW) */
1052#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
1053/** 4-5: Access type. */
1054#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
1055/** 6: LMSW operand type */
1056#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
1057/** 7: Reserved; cleared to 0. */
1058#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
1059/** 8-11: General purpose register number (0 for CLTS & LMSW). */
1060#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
1061/** 12-15: Reserved; cleared to 0. */
1062#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
1063/** 16-31: LMSW source data (else 0). */
1064#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
1065/** Rest: reserved. */
1066/** @} */
1067
1068/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
1069 * @{
1070 */
1071#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
1072#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
1073#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
1074#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
1075/** @} */
1076
1077
1078/** @name VMX_EXIT_EPT_VIOLATION
1079 * @{
1080 */
1081/** Set if the violation was caused by a data read. */
1082#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
1083/** Set if the violation was caused by a data write. */
1084#define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE RT_BIT(1)
1085/** Set if the violation was caused by an insruction fetch. */
1086#define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH RT_BIT(2)
1087/** AND of the present bit of all EPT structures. */
1088#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT RT_BIT(3)
1089/** AND of the write bit of all EPT structures. */
1090#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE RT_BIT(4)
1091/** AND of the execute bit of all EPT structures. */
1092#define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE RT_BIT(5)
1093/** Set if the guest linear address field contains the faulting address. */
1094#define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID RT_BIT(7)
1095/** If bit 7 is one: (reserved otherwise)
1096 * 1 - violation due to physical address access.
1097 * 0 - violation caused by page walk or access/dirty bit updates
1098 */
1099#define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS RT_BIT(8)
1100/** @} */
1101
1102
1103/** @name VMX_EXIT_PORT_IO
1104 * @{
1105 */
1106/** 0-2: IO operation width. */
1107#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
1108/** 3: IO operation direction. */
1109#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
1110/** 4: String IO operation. */
1111#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
1112/** 5: Repeated IO operation. */
1113#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
1114/** 6: Operand encoding. */
1115#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
1116/** 16-31: IO Port (0-0xffff). */
1117#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
1118/* Rest reserved. */
1119/** @} */
1120
1121/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
1122 * @{
1123 */
1124#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
1125#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
1126/** @} */
1127
1128
1129/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
1130 * @{
1131 */
1132#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
1133#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
1134/** @} */
1135
1136/** @name VMX_EXIT_APIC_ACCESS
1137 * @{
1138 */
1139/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
1140#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
1141/** 12-15: Access type. */
1142#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a) ((a >> 12) & 0xf)
1143/* Rest reserved. */
1144/** @} */
1145
1146
1147/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
1148 * @{
1149 */
1150/** Linear read access. */
1151#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
1152/** Linear write access. */
1153#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
1154/** Linear instruction fetch access. */
1155#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
1156/** Linear read/write access during event delivery. */
1157#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
1158/** Physical read/write access during event delivery. */
1159#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
1160/** Physical access for an instruction fetch or during instruction execution. */
1161#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
1162/** @} */
1163
1164/** @} */
1165
1166/** @name VMCS field encoding - Natural width guest state fields
1167 * @{
1168 */
1169#define VMX_VMCS64_GUEST_CR0 0x6800
1170#define VMX_VMCS64_GUEST_CR3 0x6802
1171#define VMX_VMCS64_GUEST_CR4 0x6804
1172#define VMX_VMCS64_GUEST_ES_BASE 0x6806
1173#define VMX_VMCS64_GUEST_CS_BASE 0x6808
1174#define VMX_VMCS64_GUEST_SS_BASE 0x680A
1175#define VMX_VMCS64_GUEST_DS_BASE 0x680C
1176#define VMX_VMCS64_GUEST_FS_BASE 0x680E
1177#define VMX_VMCS64_GUEST_GS_BASE 0x6810
1178#define VMX_VMCS64_GUEST_LDTR_BASE 0x6812
1179#define VMX_VMCS64_GUEST_TR_BASE 0x6814
1180#define VMX_VMCS64_GUEST_GDTR_BASE 0x6816
1181#define VMX_VMCS64_GUEST_IDTR_BASE 0x6818
1182#define VMX_VMCS64_GUEST_DR7 0x681A
1183#define VMX_VMCS64_GUEST_RSP 0x681C
1184#define VMX_VMCS64_GUEST_RIP 0x681E
1185#define VMX_VMCS_GUEST_RFLAGS 0x6820
1186#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
1187#define VMX_VMCS64_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */
1188#define VMX_VMCS64_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */
1189/** @} */
1190
1191
1192/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
1193 * @{
1194 */
1195/** Hardware breakpoint 0 was met. */
1196#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
1197/** Hardware breakpoint 1 was met. */
1198#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
1199/** Hardware breakpoint 2 was met. */
1200#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
1201/** Hardware breakpoint 3 was met. */
1202#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
1203/** At least one data or IO breakpoint was hit. */
1204#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
1205/** A debug exception would have been triggered by single-step execution mode. */
1206#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
1207/** Bits 4-11, 13 and 15-63 are reserved. */
1208
1209/** @} */
1210
1211/** @name VMCS field encoding - Natural width host state fields
1212 * @{
1213 */
1214#define VMX_VMCS_HOST_CR0 0x6C00
1215#define VMX_VMCS_HOST_CR3 0x6C02
1216#define VMX_VMCS_HOST_CR4 0x6C04
1217#define VMX_VMCS_HOST_FS_BASE 0x6C06
1218#define VMX_VMCS_HOST_GS_BASE 0x6C08
1219#define VMX_VMCS_HOST_TR_BASE 0x6C0A
1220#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
1221#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
1222#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
1223#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
1224#define VMX_VMCS_HOST_RSP 0x6C14
1225#define VMX_VMCS_HOST_RIP 0x6C16
1226/** @} */
1227
1228/** @} */
1229
1230
1231#if RT_INLINE_ASM_GNU_STYLE
1232# define __STR(x) #x
1233# define STR(x) __STR(x)
1234#endif
1235
1236
1237/** @defgroup grp_vmx_asm vmx assembly helpers
1238 * @ingroup grp_vmx
1239 * @{
1240 */
1241
1242/**
1243 * Executes VMXON
1244 *
1245 * @returns VBox status code
1246 * @param pVMXOn Physical address of VMXON structure
1247 */
1248#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1249DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
1250#else
1251DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
1252{
1253 int rc = VINF_SUCCESS;
1254# if RT_INLINE_ASM_GNU_STYLE
1255 __asm__ __volatile__ (
1256 "push %3 \n\t"
1257 "push %2 \n\t"
1258 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
1259 "ja 2f \n\t"
1260 "je 1f \n\t"
1261 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
1262 "jmp 2f \n\t"
1263 "1: \n\t"
1264 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
1265 "2: \n\t"
1266 "add $8, %%esp \n\t"
1267 :"=rm"(rc)
1268 :"0"(VINF_SUCCESS),
1269 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
1270 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
1271 :"memory"
1272 );
1273# else
1274 __asm
1275 {
1276 push dword ptr [pVMXOn+4]
1277 push dword ptr [pVMXOn]
1278 _emit 0xF3
1279 _emit 0x0F
1280 _emit 0xC7
1281 _emit 0x34
1282 _emit 0x24 /* VMXON [esp] */
1283 jnc vmxon_good
1284 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
1285 jmp the_end
1286
1287vmxon_good:
1288 jnz the_end
1289 mov dword ptr [rc], VERR_VMX_GENERIC
1290the_end:
1291 add esp, 8
1292 }
1293# endif
1294 return rc;
1295}
1296#endif
1297
1298
1299/**
1300 * Executes VMXOFF
1301 */
1302#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1303DECLASM(void) VMXDisable(void);
1304#else
1305DECLINLINE(void) VMXDisable(void)
1306{
1307# if RT_INLINE_ASM_GNU_STYLE
1308 __asm__ __volatile__ (
1309 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
1310 );
1311# else
1312 __asm
1313 {
1314 _emit 0x0F
1315 _emit 0x01
1316 _emit 0xC4 /* VMXOFF */
1317 }
1318# endif
1319}
1320#endif
1321
1322
1323/**
1324 * Executes VMCLEAR
1325 *
1326 * @returns VBox status code
1327 * @param pVMCS Physical address of VM control structure
1328 */
1329#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1330DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
1331#else
1332DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
1333{
1334 int rc = VINF_SUCCESS;
1335# if RT_INLINE_ASM_GNU_STYLE
1336 __asm__ __volatile__ (
1337 "push %3 \n\t"
1338 "push %2 \n\t"
1339 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
1340 "jnc 1f \n\t"
1341 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1342 "1: \n\t"
1343 "add $8, %%esp \n\t"
1344 :"=rm"(rc)
1345 :"0"(VINF_SUCCESS),
1346 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1347 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
1348 :"memory"
1349 );
1350# else
1351 __asm
1352 {
1353 push dword ptr [pVMCS+4]
1354 push dword ptr [pVMCS]
1355 _emit 0x66
1356 _emit 0x0F
1357 _emit 0xC7
1358 _emit 0x34
1359 _emit 0x24 /* VMCLEAR [esp] */
1360 jnc success
1361 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1362success:
1363 add esp, 8
1364 }
1365# endif
1366 return rc;
1367}
1368#endif
1369
1370
1371/**
1372 * Executes VMPTRLD
1373 *
1374 * @returns VBox status code
1375 * @param pVMCS Physical address of VMCS structure
1376 */
1377#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1378DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1379#else
1380DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1381{
1382 int rc = VINF_SUCCESS;
1383# if RT_INLINE_ASM_GNU_STYLE
1384 __asm__ __volatile__ (
1385 "push %3 \n\t"
1386 "push %2 \n\t"
1387 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1388 "jnc 1f \n\t"
1389 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1390 "1: \n\t"
1391 "add $8, %%esp \n\t"
1392 :"=rm"(rc)
1393 :"0"(VINF_SUCCESS),
1394 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1395 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1396 );
1397# else
1398 __asm
1399 {
1400 push dword ptr [pVMCS+4]
1401 push dword ptr [pVMCS]
1402 _emit 0x0F
1403 _emit 0xC7
1404 _emit 0x34
1405 _emit 0x24 /* VMPTRLD [esp] */
1406 jnc success
1407 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1408
1409success:
1410 add esp, 8
1411 }
1412# endif
1413 return rc;
1414}
1415#endif
1416
1417/**
1418 * Executes VMPTRST
1419 *
1420 * @returns VBox status code
1421 * @param pVMCS Address that will receive the current pointer
1422 */
1423DECLASM(int) VMXGetActivateVMCS(RTHCPHYS *pVMCS);
1424
1425/**
1426 * Executes VMWRITE
1427 *
1428 * @returns VBox status code
1429 * @param idxField VMCS index
1430 * @param u32Val 32 bits value
1431 */
1432#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1433DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1434#else
1435DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1436{
1437 int rc = VINF_SUCCESS;
1438# if RT_INLINE_ASM_GNU_STYLE
1439 __asm__ __volatile__ (
1440 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1441 "ja 2f \n\t"
1442 "je 1f \n\t"
1443 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1444 "jmp 2f \n\t"
1445 "1: \n\t"
1446 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1447 "2: \n\t"
1448 :"=rm"(rc)
1449 :"0"(VINF_SUCCESS),
1450 "a"(idxField),
1451 "d"(u32Val)
1452 );
1453# else
1454 __asm
1455 {
1456 push dword ptr [u32Val]
1457 mov eax, [idxField]
1458 _emit 0x0F
1459 _emit 0x79
1460 _emit 0x04
1461 _emit 0x24 /* VMWRITE eax, [esp] */
1462 jnc valid_vmcs
1463 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1464 jmp the_end
1465
1466valid_vmcs:
1467 jnz the_end
1468 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1469the_end:
1470 add esp, 4
1471 }
1472# endif
1473 return rc;
1474}
1475#endif
1476
1477/**
1478 * Executes VMWRITE
1479 *
1480 * @returns VBox status code
1481 * @param idxField VMCS index
1482 * @param u64Val 16, 32 or 64 bits value
1483 */
1484#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1485DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1486#else
1487VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
1488
1489#define VMXWriteVMCS64(idxField, u64Val) VMXWriteVMCS64Ex(pVCpu, idxField, u64Val)
1490#endif
1491
1492#if HC_ARCH_BITS == 64
1493#define VMXWriteVMCS VMXWriteVMCS64
1494#else
1495#define VMXWriteVMCS VMXWriteVMCS32
1496#endif /* HC_ARCH_BITS == 64 */
1497
1498
1499/**
1500 * Invalidate a page using invept
1501 * @returns VBox status code
1502 * @param enmFlush Type of flush
1503 * @param pDescriptor Descriptor
1504 */
1505DECLASM(int) VMXR0InvEPT(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1506
1507/**
1508 * Invalidate a page using invvpid
1509 * @returns VBox status code
1510 * @param enmFlush Type of flush
1511 * @param pDescriptor Descriptor
1512 */
1513DECLASM(int) VMXR0InvVPID(VMX_FLUSH enmFlush, uint64_t *pDescriptor);
1514
1515/**
1516 * Executes VMREAD
1517 *
1518 * @returns VBox status code
1519 * @param idxField VMCS index
1520 * @param pData Ptr to store VM field value
1521 */
1522#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1523DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1524#else
1525DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1526{
1527 int rc = VINF_SUCCESS;
1528# if RT_INLINE_ASM_GNU_STYLE
1529 __asm__ __volatile__ (
1530 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1531 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1532 "ja 2f \n\t"
1533 "je 1f \n\t"
1534 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1535 "jmp 2f \n\t"
1536 "1: \n\t"
1537 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1538 "2: \n\t"
1539 :"=&r"(rc),
1540 "=d"(*pData)
1541 :"a"(idxField),
1542 "d"(0)
1543 );
1544# else
1545 __asm
1546 {
1547 sub esp, 4
1548 mov dword ptr [esp], 0
1549 mov eax, [idxField]
1550 _emit 0x0F
1551 _emit 0x78
1552 _emit 0x04
1553 _emit 0x24 /* VMREAD eax, [esp] */
1554 mov edx, pData
1555 pop dword ptr [edx]
1556 jnc valid_vmcs
1557 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1558 jmp the_end
1559
1560valid_vmcs:
1561 jnz the_end
1562 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1563the_end:
1564 }
1565# endif
1566 return rc;
1567}
1568#endif
1569
1570/**
1571 * Executes VMREAD
1572 *
1573 * @returns VBox status code
1574 * @param idxField VMCS index
1575 * @param pData Ptr to store VM field value
1576 */
1577#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1578DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1579#else
1580DECLINLINE(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData)
1581{
1582 int rc;
1583
1584 uint32_t val_hi, val;
1585 rc = VMXReadVMCS32(idxField, &val);
1586 rc |= VMXReadVMCS32(idxField + 1, &val_hi);
1587 AssertRC(rc);
1588 *pData = RT_MAKE_U64(val, val_hi);
1589 return rc;
1590}
1591#endif
1592
1593#if HC_ARCH_BITS == 64
1594# define VMXReadVMCS VMXReadVMCS64
1595#else
1596# define VMXReadVMCS VMXReadVMCS32
1597#endif /* HC_ARCH_BITS == 64 */
1598
1599/**
1600 * Gets the last instruction error value from the current VMCS
1601 *
1602 * @returns error value
1603 */
1604DECLINLINE(uint32_t) VMXGetLastError(void)
1605{
1606#if HC_ARCH_BITS == 64
1607 uint64_t uLastError = 0;
1608 int rc = VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1609 AssertRC(rc);
1610 return (uint32_t)uLastError;
1611
1612#else /* 32-bit host: */
1613 uint32_t uLastError = 0;
1614 int rc = VMXReadVMCS32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
1615 AssertRC(rc);
1616 return uLastError;
1617#endif
1618}
1619
1620#ifdef IN_RING0
1621VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
1622VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys);
1623#endif /* IN_RING0 */
1624
1625/** @} */
1626
1627#endif
1628
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