VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 10822

Last change on this file since 10822 was 10822, checked in by vboxsync, 17 years ago

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1/** @file
2 * HWACC/VMX - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_vmx_h
31#define ___VBox_vmx_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_vmx vmx Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43/**
44 * Extended Page Directory Pointer. Bit view.
45 */
46#pragma pack(1)
47typedef struct VTXEPTPBITS
48{
49 /** EPT Table Memory Type. */
50 uint64_t u3ETMT : 3;
51 /** Guest Address Width. */
52 uint64_t u3GAW : 3;
53 /** Reserved. */
54 uint64_t u6Reserved : 6;
55 /** Address Space Root; page frame address of the first level EPT page. Actual width depends on the maximum physical address width of the CPU. */
56 uint64_t u52ASR : 52;
57} VTXEPTPBITS;
58#pragma pack()
59/** Pointer to an extended page directory pointer. */
60typedef VTXEPTPBITS *PVTXEPTPBITS;
61/** Pointer to a const extended page directory pointer. */
62typedef const VTXEPTPBITS *PCVTXEPTPBITS;
63
64/**
65 * Extended Page Directory Pointer.
66 */
67#pragma pack(1)
68typedef union VTXEPTP
69{
70 VTXEPTPBITS n;
71 /** 64 bit unsigned integer view. */
72 uint64_t au64[1];
73} VTXEPTP;
74#pragma pack()
75/** Pointer to an extended page directory pointer. */
76typedef VTXEPTP *PVTXEPTP;
77/** Pointer to a const extended page directory pointer. */
78typedef const VTXEPTP *PCVTXEPTP;
79
80
81/**
82 * Extended Page Directory Table Entry. Bit view.
83 */
84#pragma pack(1)
85typedef union VTXEPTEBITS
86{
87 /** Readable bit. */
88 uint64_t u1Readable : 1;
89 /** Writable bit. */
90 uint64_t u1Writable : 1;
91 /** Executable bit. */
92 uint64_t u1Executable : 1;
93 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
94 uint64_t u3EMT : 3;
95 /** IGMT (Ignore Guest Memory Type) (leaf nodes). MBZ for non-leaf nodes. */
96 uint64_t u1IGMT : 1;
97 /** Super page (non-leaf) / available (leaf). */
98 uint64_t u1SP : 1;
99 /** Available for software. */
100 uint64_t u4Available : 4;
101 /** Physical address of next leaf/super page. Restricted by maximum physical address width of the cpu. */
102 uint64_t u45PhysAddr : 45;
103 /** Reserved (MBZ). */
104 uint64_t u5Reserved : 5;
105 /** Availabe for software. */
106 uint64_t u2Available : 2;
107} VTXEPTEBITS;
108#pragma pack()
109/** Pointer to an extended page table entry. */
110typedef VTXEPTEBITS *PVTXEPTEBITS;
111/** Pointer to a const extended table entry. */
112typedef const VTXEPTEBITS *PCVTXEPTEBITS;
113
114/**
115 * Extended Page Directory Table Entry.
116 */
117#pragma pack(1)
118typedef union VTXEPTE
119{
120 VTXEPTEBITS n;
121 /** 64 bit unsigned integer view. */
122 uint64_t au64[1];
123} VTXEPTE;
124#pragma pack()
125/** Pointer to an extended page table entry. */
126typedef VTXEPTE *PVTXEPTE;
127/** Pointer to a const extended table entry. */
128typedef const VTXEPTE *PCVTXEPTE;
129
130/**
131 * Number of page table entries in the EPT.
132 */
133#define VTX_PT_ENTRIES 512
134
135/**
136 * Extended Page Directory Table.
137 */
138#pragma pack(1)
139typedef union VTXEPT
140{
141 VTXEPTE a[VTX_PT_ENTRIES];
142} VTXEPT;
143#pragma pack()
144/** Pointer to an extended page table. */
145typedef VTXEPT *PVTXEPT;
146/** Pointer to a const extended table. */
147typedef const VTXEPT *PCVTXEPT;
148
149/** VMX Basic Exit Reasons.
150 * @{
151 */
152/* And-mask for setting reserved bits to zero */
153#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
154/* Or-mask for setting reserved bits to 1 */
155#define VMX_EFLAGS_RESERVED_1 0x00000002
156/** @} */
157
158/** VMX Basic Exit Reasons.
159 * @{
160 */
161/** 0 Exception or non-maskable interrupt (NMI). */
162#define VMX_EXIT_EXCEPTION 0
163/** 1 External interrupt. */
164#define VMX_EXIT_EXTERNAL_IRQ 1
165/** 2 Triple fault. */
166#define VMX_EXIT_TRIPLE_FAULT 2
167/** 3 INIT signal. */
168#define VMX_EXIT_INIT_SIGNAL 3
169/** 4 Start-up IPI (SIPI). */
170#define VMX_EXIT_SIPI 4
171/** 5 I/O system-management interrupt (SMI). */
172#define VMX_EXIT_IO_SMI_IRQ 5
173/** 6 Other SMI. */
174#define VMX_EXIT_SMI_IRQ 6
175/** 7 Interrupt window. */
176#define VMX_EXIT_IRQ_WINDOW 7
177/** 9 Task switch. */
178#define VMX_EXIT_TASK_SWITCH 9
179/** 10 Guest software attempted to execute CPUID. */
180#define VMX_EXIT_CPUID 10
181/** 12 Guest software attempted to execute HLT. */
182#define VMX_EXIT_HLT 12
183/** 13 Guest software attempted to execute INVD. */
184#define VMX_EXIT_INVD 13
185/** 14 Guest software attempted to execute INVPG. */
186#define VMX_EXIT_INVPG 14
187/** 15 Guest software attempted to execute RDPMC. */
188#define VMX_EXIT_RDPMC 15
189/** 16 Guest software attempted to execute RDTSC. */
190#define VMX_EXIT_RDTSC 16
191/** 17 Guest software attempted to execute RSM in SMM. */
192#define VMX_EXIT_RSM 17
193/** 18 Guest software executed VMCALL. */
194#define VMX_EXIT_VMCALL 18
195/** 19 Guest software executed VMCLEAR. */
196#define VMX_EXIT_VMCLEAR 19
197/** 20 Guest software executed VMLAUNCH. */
198#define VMX_EXIT_VMLAUNCH 20
199/** 21 Guest software executed VMPTRLD. */
200#define VMX_EXIT_VMPTRLD 21
201/** 22 Guest software executed VMPTRST. */
202#define VMX_EXIT_VMPTRST 22
203/** 23 Guest software executed VMREAD. */
204#define VMX_EXIT_VMREAD 23
205/** 24 Guest software executed VMRESUME. */
206#define VMX_EXIT_VMRESUME 24
207/** 25 Guest software executed VMWRITE. */
208#define VMX_EXIT_VMWRITE 25
209/** 26 Guest software executed VMXOFF. */
210#define VMX_EXIT_VMXOFF 26
211/** 27 Guest software executed VMXON. */
212#define VMX_EXIT_VMXON 27
213/** 28 Control-register accesses. */
214#define VMX_EXIT_CRX_MOVE 28
215/** 29 Debug-register accesses. */
216#define VMX_EXIT_DRX_MOVE 29
217/** 30 I/O instruction. */
218#define VMX_EXIT_PORT_IO 30
219/** 31 RDMSR. Guest software attempted to execute RDMSR. */
220#define VMX_EXIT_RDMSR 31
221/** 32 WRMSR. Guest software attempted to execute WRMSR. */
222#define VMX_EXIT_WRMSR 32
223/** 33 VM-entry failure due to invalid guest state. */
224#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
225/** 34 VM-entry failure due to MSR loading. */
226#define VMX_EXIT_ERR_MSR_LOAD 34
227/** 36 Guest software executed MWAIT. */
228#define VMX_EXIT_MWAIT 36
229/** 39 Guest software attempted to execute MONITOR. */
230#define VMX_EXIT_MONITOR 39
231/** 40 Guest software attempted to execute PAUSE. */
232#define VMX_EXIT_PAUSE 40
233/** 41 VM-entry failure due to machine-check. */
234#define VMX_EXIT_ERR_MACHINE_CHECK 41
235/** 43 TPR below threshold. Guest software executed MOV to CR8. */
236#define VMX_EXIT_TPR 43
237
238/** @} */
239
240
241/** VM Instruction Errors
242 * @{
243 */
244/** 1 VMCALL executed in VMX root operation. */
245#define VMX_ERROR_VMCALL 1
246/** 2 VMCLEAR with invalid physical address. */
247#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
248/** 3 VMCLEAR with VMXON pointer. */
249#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
250/** 4 VMLAUNCH with non-clear VMCS. */
251#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
252/** 5 VMRESUME with non-launched VMCS. */
253#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
254/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
255#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
256/** 7 VM entry with invalid control field(s). */
257#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
258/** 8 VM entry with invalid host-state field(s). */
259#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
260/** 9 VMPTRLD with invalid physical address. */
261#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
262/** 10 VMPTRLD with VMXON pointer. */
263#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
264/** 11 VMPTRLD with incorrect VMCS revision identifier. */
265#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
266/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
267#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
268#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
269/** 13 VMWRITE to read-only VMCS component. */
270#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
271/** 15 VMXON executed in VMX root operation. */
272#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
273/** 16 VM entry with invalid executive-VMCS pointer. */
274#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
275/** 17 VM entry with non-launched executive VMCS. */
276#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
277/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
278#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
279/** 19 VMCALL with non-clear VMCS. */
280#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
281/** 20 VMCALL with invalid VM-exit control fields. */
282#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
283/** 22 VMCALL with incorrect MSEG revision identifier. */
284#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
285/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
286#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
287/** 24 VMCALL with invalid SMM-monitor features. */
288#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
289/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
290#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
291/** 26 VM entry with events blocked by MOV SS. */
292#define VMX_ERROR_VMENTRY_MOV_SS 26
293
294/** @} */
295
296
297/** VMX MSR bit definitions
298 * @{
299 */
300
301/** Basic VMX information.
302 * @{
303 */
304/** VMCS revision identifier used by the processor. */
305#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
306/** Size of the VMCS. */
307#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
308/** Width of physical address used for the VMCS.
309 * 0 -> limited to the available amount of physical ram
310 * 1 -> within the first 4 GB
311 */
312#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
313/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
314#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
315/** Memory type that must be used for the VMCS. */
316#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
317/** @} */
318
319
320/** Misc VMX info.
321 * @{
322 */
323/** Activity states supported by the implementation. */
324#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
325/** Number of CR3 target values supported by the processor. (0-256) */
326#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
327/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
328#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
329/** MSEG revision identifier used by the processor. */
330#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
331/** @} */
332
333
334/** VMCS enumeration field info
335 * @{
336 */
337/** Highest field index. */
338#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
339
340/** @} */
341
342
343/** MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
344 * @{
345 */
346#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
347#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
348#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
349#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
350#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
351#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
352#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
353#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
354#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
355#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
356#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
357#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
358#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
359#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
360#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
361#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
362#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
363#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
364#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
365#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
366#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
367#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
368#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
369#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
370#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
371#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
372
373/** @} */
374
375/** @} */
376
377
378/** VMCS field encoding
379 * @{
380 */
381
382/* 16 bits guest fields
383 * @{
384 */
385#define VMX_VMCS_GUEST_FIELD_VPID 0x0
386#define VMX_VMCS_GUEST_FIELD_ES 0x800
387#define VMX_VMCS_GUEST_FIELD_CS 0x802
388#define VMX_VMCS_GUEST_FIELD_SS 0x804
389#define VMX_VMCS_GUEST_FIELD_DS 0x806
390#define VMX_VMCS_GUEST_FIELD_FS 0x808
391#define VMX_VMCS_GUEST_FIELD_GS 0x80A
392#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
393#define VMX_VMCS_GUEST_FIELD_TR 0x80E
394/** @} */
395
396/** 16 bits host fields
397 * @{
398 */
399#define VMX_VMCS_HOST_FIELD_ES 0xC00
400#define VMX_VMCS_HOST_FIELD_CS 0xC02
401#define VMX_VMCS_HOST_FIELD_SS 0xC04
402#define VMX_VMCS_HOST_FIELD_DS 0xC06
403#define VMX_VMCS_HOST_FIELD_FS 0xC08
404#define VMX_VMCS_HOST_FIELD_GS 0xC0A
405#define VMX_VMCS_HOST_FIELD_TR 0xC0C
406/** @} */
407
408/** 64 bits host fields
409 * @{
410 */
411#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
412#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
413#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
414#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
415#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /* MSR IA32_PERF_GLOBAL_CTRL */
416#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /* MSR IA32_PERF_GLOBAL_CTRL */
417/** @} */
418
419
420/** 64 Bits control fields
421 * @{
422 */
423#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
424#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
425#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
426#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
427
428/* Optional */
429#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
430#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
431
432#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
433#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
434#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
435#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
436
437#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
438#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
439
440#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
441#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
442
443#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
444#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
445
446/* Optional */
447#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
448#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
449
450/** Extended page table pointer. */
451#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
452#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
453
454/** VM-exit phyiscal address. */
455#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
456#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
457/** @} */
458
459
460/** 64 Bits guest fields
461 * @{
462 */
463#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
464#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
465#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
466#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
467#define VMX_VMCS_GUEST_PAT_FULL 0x2804
468#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
469#define VMX_VMCS_GUEST_EFER_FULL 0x2806
470#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
471#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /* MSR IA32_PERF_GLOBAL_CTRL */
472#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /* MSR IA32_PERF_GLOBAL_CTRL */
473#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
474#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
475#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
476#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
477#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
478#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
479#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
480#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
481/** @} */
482
483
484/** 32 Bits control fields
485 * @{
486 */
487#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
488#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
489#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
490#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
491#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
492#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
493#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
494#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
495#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
496#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
497#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
498#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
499#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
500#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
501/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
502#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
503/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
504#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
505/** @} */
506
507
508/** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
509 * @{
510 */
511/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
512#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
513/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
514#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
515/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
516/** @} */
517
518/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
519 * @{
520 */
521/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
522#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
523/* Use timestamp counter offset. */
524#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
525/* VM Exit when executing the HLT instruction. */
526#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
527/* VM Exit when executing the INVLPG instruction. */
528#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
529/* VM Exit when executing the MWAIT instruction. */
530#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
531/* VM Exit when executing the RDPMC instruction. */
532#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
533/* VM Exit when executing the RDTSC instruction. */
534#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
535/* VM Exit on CR8 loads. */
536#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
537/* VM Exit on CR8 stores. */
538#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
539/* Use TPR shadow. */
540#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
541/* VM Exit when executing a MOV DRx instruction. */
542#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
543/* VM Exit when executing IO instructions. */
544#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
545/* Use IO bitmaps. */
546#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
547/* Use MSR bitmaps. */
548#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
549/* VM Exit when executing the MONITOR instruction. */
550#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
551/* VM Exit when executing the PAUSE instruction. */
552#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
553/* Determines whether the secondary processor based VM-execution controls are used. */
554#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
555/** @} */
556
557/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
558 * @{
559 */
560/** Virtualize APIC access. */
561#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
562/** EPT supported/enabled. */
563#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
564/** VPID supported/enabled. */
565#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
566/** VM Exit when executing the WBINVD instruction. */
567#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
568/** @} */
569
570
571/** VMX_VMCS_CTRL_ENTRY_CONTROLS
572 * @{
573 */
574/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
575#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
576/** In SMM mode after VM-entry. */
577#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
578/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
579#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
580/** @} */
581
582
583/** VMX_VMCS_CTRL_EXIT_CONTROLS
584 * @{
585 */
586/** Return to long mode after a VM-exit. */
587#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
588/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
589#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
590/** @} */
591
592/** 32 Bits read-only fields
593 * @{
594 */
595#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
596#define VMX_VMCS_RO_EXIT_REASON 0x4402
597#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
598#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
599#define VMX_VMCS_RO_IDT_INFO 0x4408
600#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
601#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
602#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
603/** @} */
604
605/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
606 * @{
607 */
608#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
609#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
610#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
611#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
612#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
613#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
614#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
615#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
616/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
617#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
618/** @} */
619
620/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
621 * @{
622 */
623#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
624#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
625#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
626#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
627#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
628/** @} */
629
630
631/** 32 Bits guest state fields
632 * @{
633 */
634#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
635#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
636#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
637#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
638#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
639#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
640#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
641#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
642#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
643#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
644#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
645#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
646#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
647#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
648#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
649#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
650#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
651#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
652#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
653#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
654#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
655/** @} */
656
657
658/** VMX_VMCS_GUEST_ACTIVITY_STATE
659 * @{
660 */
661/* The logical processor is active. */
662#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
663/* The logical processor is inactive, because executed a HLT instruction. */
664#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
665/* The logical processor is inactive, because of a triple fault or other serious error. */
666#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
667/* The logical processor is inactive, because it's waiting for a startup-IPI */
668#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
669/** @} */
670
671
672/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
673 * @{
674 */
675#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
676#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
677#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
678#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
679/** @} */
680
681
682/** 32 Bits host state fields
683 * @{
684 */
685#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
686/** @} */
687
688/** Natural width control fields
689 * @{
690 */
691#define VMX_VMCS_CTRL_CR0_MASK 0x6000
692#define VMX_VMCS_CTRL_CR4_MASK 0x6002
693#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
694#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
695#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
696#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
697#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
698#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
699/** @} */
700
701
702/** Natural width read-only data fields
703 * @{
704 */
705#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
706#define VMX_VMCS_RO_IO_RCX 0x6402
707#define VMX_VMCS_RO_IO_RSX 0x6404
708#define VMX_VMCS_RO_IO_RDI 0x6406
709#define VMX_VMCS_RO_IO_RIP 0x6408
710#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
711/** @} */
712
713
714/** VMX_VMCS_RO_EXIT_QUALIFICATION
715 * @{
716 */
717
718/** DRx moves
719 * @{
720 */
721/** 0-2: Debug register number */
722#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
723/** 3: Reserved; cleared to 0. */
724#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
725/** 4: Direction of move (0 = write, 1 = read) */
726#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
727/** 5-7: Reserved; cleared to 0. */
728#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
729/** 8-11: General purpose register number. */
730#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
731/** Rest: reserved. */
732
733/** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
734 * @{
735 */
736#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
737#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
738/** @} */
739
740/** @} */
741
742
743/** CRx accesses
744 * @{
745 */
746/** 0-3: Control register number (0 for CLTS & LMSW) */
747#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
748/** 4-5: Access type. */
749#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
750/** 6: LMSW operand type */
751#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
752/** 7: Reserved; cleared to 0. */
753#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
754/** 8-11: General purpose register number (0 for CLTS & LMSW). */
755#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
756/** 12-15: Reserved; cleared to 0. */
757#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
758/** 16-31: LMSW source data (else 0). */
759#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
760/** Rest: reserved. */
761
762
763/** VMX_EXIT_QUALIFICATION_CRX_ACCESS
764 * @{
765 */
766#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
767#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
768#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
769#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
770/** @} */
771
772/** @} */
773
774
775/** VMX_EXIT_PORT_IO
776 * @{
777 */
778/** 0-2: IO operation width. */
779#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
780/** 3: IO operation direction. */
781#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
782/** 4: String IO operation. */
783#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
784/** 5: Repeated IO operation. */
785#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
786/** 6: Operand encoding. */
787#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
788/** 16-31: IO Port (0-0xffff). */
789#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
790/* Rest reserved. */
791/** @} */
792
793/** VMX_EXIT_QUALIFICATION_IO_DIRECTION
794 * @{
795 */
796#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
797#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
798/** @} */
799
800
801/** VMX_EXIT_QUALIFICATION_IO_ENCODING
802 * @{
803 */
804#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
805#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
806/** @} */
807
808/** @} */
809
810/** Natural width guest state fields
811 * @{
812 */
813#define VMX_VMCS_GUEST_CR0 0x6800
814#define VMX_VMCS_GUEST_CR3 0x6802
815#define VMX_VMCS_GUEST_CR4 0x6804
816#define VMX_VMCS_GUEST_ES_BASE 0x6806
817#define VMX_VMCS_GUEST_CS_BASE 0x6808
818#define VMX_VMCS_GUEST_SS_BASE 0x680A
819#define VMX_VMCS_GUEST_DS_BASE 0x680C
820#define VMX_VMCS_GUEST_FS_BASE 0x680E
821#define VMX_VMCS_GUEST_GS_BASE 0x6810
822#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
823#define VMX_VMCS_GUEST_TR_BASE 0x6814
824#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
825#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
826#define VMX_VMCS_GUEST_DR7 0x681A
827#define VMX_VMCS_GUEST_RSP 0x681C
828#define VMX_VMCS_GUEST_RIP 0x681E
829#define VMX_VMCS_GUEST_RFLAGS 0x6820
830#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
831#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
832#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
833/** @} */
834
835
836/** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
837 * @{
838 */
839/* Hardware breakpoint 0 was met. */
840#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
841/* Hardware breakpoint 1 was met. */
842#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
843/* Hardware breakpoint 2 was met. */
844#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
845/* Hardware breakpoint 3 was met. */
846#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
847/* At least one data or IO breakpoint was hit. */
848#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
849/* A debug exception would have been triggered by single-step execution mode. */
850#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
851/* Bits 4-11, 13 and 15-63 are reserved. */
852
853
854
855
856/** @} */
857
858/** Natural width host state fields
859 * @{
860 */
861#define VMX_VMCS_HOST_CR0 0x6C00
862#define VMX_VMCS_HOST_CR3 0x6C02
863#define VMX_VMCS_HOST_CR4 0x6C04
864#define VMX_VMCS_HOST_FS_BASE 0x6C06
865#define VMX_VMCS_HOST_GS_BASE 0x6C08
866#define VMX_VMCS_HOST_TR_BASE 0x6C0A
867#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
868#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
869#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
870#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
871#define VMX_VMCS_HOST_RSP 0x6C14
872#define VMX_VMCS_HOST_RIP 0x6C16
873/** @} */
874
875/** @} */
876
877
878#if RT_INLINE_ASM_GNU_STYLE
879# define __STR(x) #x
880# define STR(x) __STR(x)
881#endif
882
883
884/** @} */
885
886/** @defgroup grp_vmx_asm vmx assembly helpers
887 * @ingroup grp_vmx
888 * @{
889 */
890
891/**
892 * Executes VMXON
893 *
894 * @returns VBox status code
895 * @param pVMXOn Physical address of VMXON structure
896 */
897#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
898DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
899#else
900DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
901{
902 int rc = VINF_SUCCESS;
903# if RT_INLINE_ASM_GNU_STYLE
904 __asm__ __volatile__ (
905 "push %3 \n\t"
906 "push %2 \n\t"
907 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
908 "ja 2f \n\t"
909 "je 1f \n\t"
910 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
911 "jmp 2f \n\t"
912 "1: \n\t"
913 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
914 "2: \n\t"
915 "add $8, %%esp \n\t"
916 :"=rm"(rc)
917 :"0"(VINF_SUCCESS),
918 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
919 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
920 :"memory"
921 );
922# else
923 __asm
924 {
925 push dword ptr [pVMXOn+4]
926 push dword ptr [pVMXOn]
927 _emit 0xF3
928 _emit 0x0F
929 _emit 0xC7
930 _emit 0x34
931 _emit 0x24 /* VMXON [esp] */
932 jnc vmxon_good
933 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
934 jmp the_end
935
936vmxon_good:
937 jnz the_end
938 mov dword ptr [rc], VERR_VMX_GENERIC
939the_end:
940 add esp, 8
941 }
942# endif
943 return rc;
944}
945#endif
946
947
948/**
949 * Executes VMXOFF
950 */
951#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
952DECLASM(void) VMXDisable(void);
953#else
954DECLINLINE(void) VMXDisable(void)
955{
956# if RT_INLINE_ASM_GNU_STYLE
957 __asm__ __volatile__ (
958 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
959 );
960# else
961 __asm
962 {
963 _emit 0x0F
964 _emit 0x01
965 _emit 0xC4 /* VMXOFF */
966 }
967# endif
968}
969#endif
970
971
972/**
973 * Executes VMCLEAR
974 *
975 * @returns VBox status code
976 * @param pVMCS Physical address of VM control structure
977 */
978#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
979DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
980#else
981DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
982{
983 int rc = VINF_SUCCESS;
984# if RT_INLINE_ASM_GNU_STYLE
985 __asm__ __volatile__ (
986 "push %3 \n\t"
987 "push %2 \n\t"
988 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
989 "jnc 1f \n\t"
990 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
991 "1: \n\t"
992 "add $8, %%esp \n\t"
993 :"=rm"(rc)
994 :"0"(VINF_SUCCESS),
995 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
996 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
997 :"memory"
998 );
999# else
1000 __asm
1001 {
1002 push dword ptr [pVMCS+4]
1003 push dword ptr [pVMCS]
1004 _emit 0x66
1005 _emit 0x0F
1006 _emit 0xC7
1007 _emit 0x34
1008 _emit 0x24 /* VMCLEAR [esp] */
1009 jnc success
1010 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1011success:
1012 add esp, 8
1013 }
1014# endif
1015 return rc;
1016}
1017#endif
1018
1019
1020/**
1021 * Executes VMPTRLD
1022 *
1023 * @returns VBox status code
1024 * @param pVMCS Physical address of VMCS structure
1025 */
1026#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1027DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1028#else
1029DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1030{
1031 int rc = VINF_SUCCESS;
1032# if RT_INLINE_ASM_GNU_STYLE
1033 __asm__ __volatile__ (
1034 "push %3 \n\t"
1035 "push %2 \n\t"
1036 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1037 "jnc 1f \n\t"
1038 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1039 "1: \n\t"
1040 "add $8, %%esp \n\t"
1041 :"=rm"(rc)
1042 :"0"(VINF_SUCCESS),
1043 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1044 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1045 );
1046# else
1047 __asm
1048 {
1049 push dword ptr [pVMCS+4]
1050 push dword ptr [pVMCS]
1051 _emit 0x0F
1052 _emit 0xC7
1053 _emit 0x34
1054 _emit 0x24 /* VMPTRLD [esp] */
1055 jnc success
1056 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1057
1058success:
1059 add esp, 8
1060 }
1061# endif
1062 return rc;
1063}
1064#endif
1065
1066
1067/**
1068 * Executes VMWRITE
1069 *
1070 * @returns VBox status code
1071 * @param idxField VMCS index
1072 * @param u64Val 16, 32 or 64 bits value
1073 */
1074DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1075
1076/**
1077 * Executes VMWRITE
1078 *
1079 * @returns VBox status code
1080 * @param idxField VMCS index
1081 * @param u32Val 32 bits value
1082 */
1083#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1084DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1085#else
1086DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1087{
1088 int rc = VINF_SUCCESS;
1089# if RT_INLINE_ASM_GNU_STYLE
1090 __asm__ __volatile__ (
1091 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1092 "ja 2f \n\t"
1093 "je 1f \n\t"
1094 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1095 "jmp 2f \n\t"
1096 "1: \n\t"
1097 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1098 "2: \n\t"
1099 :"=rm"(rc)
1100 :"0"(VINF_SUCCESS),
1101 "a"(idxField),
1102 "d"(u32Val)
1103 );
1104# else
1105 __asm
1106 {
1107 push dword ptr [u32Val]
1108 mov eax, [idxField]
1109 _emit 0x0F
1110 _emit 0x79
1111 _emit 0x04
1112 _emit 0x24 /* VMWRITE eax, [esp] */
1113 jnc valid_vmcs
1114 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1115 jmp the_end
1116
1117valid_vmcs:
1118 jnz the_end
1119 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1120the_end:
1121 add esp, 4
1122 }
1123# endif
1124 return rc;
1125}
1126#endif
1127
1128#if HC_ARCH_BITS == 64
1129#define VMXWriteVMCS VMXWriteVMCS64
1130#else
1131#define VMXWriteVMCS VMXWriteVMCS32
1132#endif /* HC_ARCH_BITS == 64 */
1133
1134
1135/**
1136 * Executes VMREAD
1137 *
1138 * @returns VBox status code
1139 * @param idxField VMCS index
1140 * @param pData Ptr to store VM field value
1141 */
1142DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1143
1144/**
1145 * Executes VMREAD
1146 *
1147 * @returns VBox status code
1148 * @param idxField VMCS index
1149 * @param pData Ptr to store VM field value
1150 */
1151#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1152DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1153#else
1154DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1155{
1156 int rc = VINF_SUCCESS;
1157# if RT_INLINE_ASM_GNU_STYLE
1158 __asm__ __volatile__ (
1159 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1160 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1161 "ja 2f \n\t"
1162 "je 1f \n\t"
1163 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1164 "jmp 2f \n\t"
1165 "1: \n\t"
1166 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1167 "2: \n\t"
1168 :"=&r"(rc),
1169 "=d"(*pData)
1170 :"a"(idxField),
1171 "d"(0)
1172 );
1173# else
1174 __asm
1175 {
1176 sub esp, 4
1177 mov dword ptr [esp], 0
1178 mov eax, [idxField]
1179 _emit 0x0F
1180 _emit 0x78
1181 _emit 0x04
1182 _emit 0x24 /* VMREAD eax, [esp] */
1183 mov edx, pData
1184 pop dword ptr [edx]
1185 jnc valid_vmcs
1186 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1187 jmp the_end
1188
1189valid_vmcs:
1190 jnz the_end
1191 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1192the_end:
1193 }
1194# endif
1195 return rc;
1196}
1197#endif
1198
1199#if HC_ARCH_BITS == 64
1200#define VMXReadVMCS VMXReadVMCS64
1201#else
1202#define VMXReadVMCS VMXReadVMCS32
1203#endif /* HC_ARCH_BITS == 64 */
1204
1205/**
1206 * Gets the last instruction error value from the current VMCS
1207 *
1208 * @returns error value
1209 */
1210DECLINLINE(uint32_t) VMXGetLastError(void)
1211{
1212#if HC_ARCH_BITS == 64
1213 uint64_t uLastError = 0;
1214 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1215 AssertRC(rc);
1216 return (uint32_t)uLastError;
1217
1218#else /* 32-bit host: */
1219 uint32_t lasterr = 0;
1220 int rc;
1221
1222 rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
1223 AssertRC(rc);
1224 return lasterr;
1225#endif
1226}
1227
1228/** @} */
1229
1230#endif
1231
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