VirtualBox

source: vbox/trunk/include/VBox/hwacc_vmx.h@ 10820

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1/** @file
2 * HWACC/VMX - VMX Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_vmx_h
31#define ___VBox_vmx_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_vmx vmx Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43/**
44 * Extended Page Directory Pointer. Bit view.
45 */
46#pragma pack(1)
47typedef struct VTXEPTPBITS
48{
49 /** EPT Table Memory Type. */
50 uint64_t u3ETMT : 3;
51 /** Guest Address Width. */
52 uint64_t u3GAW : 3;
53 /** Reserved. */
54 uint64_t u6Reserved : 6;
55 /** Address Space Root; page frame address of the first level EPT page. Actual width depends on the maximum physical address width of the CPU. */
56 uint64_t u52ASR : 52;
57} VTXEPTPBITS;
58#pragma pack()
59/** Pointer to an extended page directory pointer. */
60typedef VTXEPTPBITS *PVTXEPTPBITS;
61/** Pointer to a const extended page directory pointer. */
62typedef const VTXEPTPBITS *PCVTXEPTPBITS;
63
64/**
65 * Extended Page Directory Pointer.
66 */
67#pragma pack(1)
68typedef union VTXEPTP
69{
70 VTXEPTPBITS n;
71 /** 64 bit unsigned integer view. */
72 uint64_t au64[1];
73} VTXEPTP;
74#pragma pack()
75/** Pointer to an extended page directory pointer. */
76typedef VTXEPTP *PVTXEPTP;
77/** Pointer to a const extended page directory pointer. */
78typedef const VTXEPTP *PCVTXEPTP;
79
80
81/**
82 * Extended Page Directory Table Entry. Bit view.
83 */
84#pragma pack(1)
85typedef union VTXEPTEBITS
86{
87 /** Readable bit. */
88 uint64_t u1Readable : 1;
89 /** Writable bit. */
90 uint64_t u1Writable : 1;
91 /** Executable bit. */
92 uint64_t u1Executable : 1;
93 /** EPT Table Memory Type. MBZ for non-leaf nodes. */
94 uint64_t u3EMT : 3;
95 /** IGMT (Ignore Guest Memory Type) (leaf nodes). MBZ for non-leaf nodes. */
96 uint64_t u1IGMT : 1;
97 /** Super page (non-leaf) / available (leaf). */
98 uint64_t u1SP : 1;
99 /** Available for software. */
100 uint64_t u4Available : 4;
101 /** Physical address of next leaf/super page. Restricted by maximum physical address width of the cpu. */
102 uint64_t u45PhysAddr : 45;
103 /** Reserved (MBZ). */
104 uint64_t u5Reserved : 5;
105 /** Availabe for software. */
106 uint64_t u2Available : 2;
107} VTXEPTEBITS;
108#pragma pack()
109/** Pointer to an extended page table entry. */
110typedef VTXEPTEBITS *PVTXEPTEBITS;
111/** Pointer to a const extended table entry. */
112typedef const VTXEPTEBITS *PCVTXEPTEBITS;
113
114/**
115 * Extended Page Directory Table Entry.
116 */
117#pragma pack(1)
118typedef union VTXEPTE
119{
120 VTXEPTEBITS n;
121 /** 64 bit unsigned integer view. */
122 uint64_t au64[1];
123} VTXEPTE;
124#pragma pack()
125/** Pointer to an extended page table entry. */
126typedef VTXEPTE *PVTXEPTE;
127/** Pointer to a const extended table entry. */
128typedef const VTXEPTE *PCVTXEPTE;
129
130/** VMX Basic Exit Reasons.
131 * @{
132 */
133/* And-mask for setting reserved bits to zero */
134#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
135/* Or-mask for setting reserved bits to 1 */
136#define VMX_EFLAGS_RESERVED_1 0x00000002
137/** @} */
138
139/** VMX Basic Exit Reasons.
140 * @{
141 */
142/** 0 Exception or non-maskable interrupt (NMI). */
143#define VMX_EXIT_EXCEPTION 0
144/** 1 External interrupt. */
145#define VMX_EXIT_EXTERNAL_IRQ 1
146/** 2 Triple fault. */
147#define VMX_EXIT_TRIPLE_FAULT 2
148/** 3 INIT signal. */
149#define VMX_EXIT_INIT_SIGNAL 3
150/** 4 Start-up IPI (SIPI). */
151#define VMX_EXIT_SIPI 4
152/** 5 I/O system-management interrupt (SMI). */
153#define VMX_EXIT_IO_SMI_IRQ 5
154/** 6 Other SMI. */
155#define VMX_EXIT_SMI_IRQ 6
156/** 7 Interrupt window. */
157#define VMX_EXIT_IRQ_WINDOW 7
158/** 9 Task switch. */
159#define VMX_EXIT_TASK_SWITCH 9
160/** 10 Guest software attempted to execute CPUID. */
161#define VMX_EXIT_CPUID 10
162/** 12 Guest software attempted to execute HLT. */
163#define VMX_EXIT_HLT 12
164/** 13 Guest software attempted to execute INVD. */
165#define VMX_EXIT_INVD 13
166/** 14 Guest software attempted to execute INVPG. */
167#define VMX_EXIT_INVPG 14
168/** 15 Guest software attempted to execute RDPMC. */
169#define VMX_EXIT_RDPMC 15
170/** 16 Guest software attempted to execute RDTSC. */
171#define VMX_EXIT_RDTSC 16
172/** 17 Guest software attempted to execute RSM in SMM. */
173#define VMX_EXIT_RSM 17
174/** 18 Guest software executed VMCALL. */
175#define VMX_EXIT_VMCALL 18
176/** 19 Guest software executed VMCLEAR. */
177#define VMX_EXIT_VMCLEAR 19
178/** 20 Guest software executed VMLAUNCH. */
179#define VMX_EXIT_VMLAUNCH 20
180/** 21 Guest software executed VMPTRLD. */
181#define VMX_EXIT_VMPTRLD 21
182/** 22 Guest software executed VMPTRST. */
183#define VMX_EXIT_VMPTRST 22
184/** 23 Guest software executed VMREAD. */
185#define VMX_EXIT_VMREAD 23
186/** 24 Guest software executed VMRESUME. */
187#define VMX_EXIT_VMRESUME 24
188/** 25 Guest software executed VMWRITE. */
189#define VMX_EXIT_VMWRITE 25
190/** 26 Guest software executed VMXOFF. */
191#define VMX_EXIT_VMXOFF 26
192/** 27 Guest software executed VMXON. */
193#define VMX_EXIT_VMXON 27
194/** 28 Control-register accesses. */
195#define VMX_EXIT_CRX_MOVE 28
196/** 29 Debug-register accesses. */
197#define VMX_EXIT_DRX_MOVE 29
198/** 30 I/O instruction. */
199#define VMX_EXIT_PORT_IO 30
200/** 31 RDMSR. Guest software attempted to execute RDMSR. */
201#define VMX_EXIT_RDMSR 31
202/** 32 WRMSR. Guest software attempted to execute WRMSR. */
203#define VMX_EXIT_WRMSR 32
204/** 33 VM-entry failure due to invalid guest state. */
205#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
206/** 34 VM-entry failure due to MSR loading. */
207#define VMX_EXIT_ERR_MSR_LOAD 34
208/** 36 Guest software executed MWAIT. */
209#define VMX_EXIT_MWAIT 36
210/** 39 Guest software attempted to execute MONITOR. */
211#define VMX_EXIT_MONITOR 39
212/** 40 Guest software attempted to execute PAUSE. */
213#define VMX_EXIT_PAUSE 40
214/** 41 VM-entry failure due to machine-check. */
215#define VMX_EXIT_ERR_MACHINE_CHECK 41
216/** 43 TPR below threshold. Guest software executed MOV to CR8. */
217#define VMX_EXIT_TPR 43
218
219/** @} */
220
221
222/** VM Instruction Errors
223 * @{
224 */
225/** 1 VMCALL executed in VMX root operation. */
226#define VMX_ERROR_VMCALL 1
227/** 2 VMCLEAR with invalid physical address. */
228#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
229/** 3 VMCLEAR with VMXON pointer. */
230#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
231/** 4 VMLAUNCH with non-clear VMCS. */
232#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
233/** 5 VMRESUME with non-launched VMCS. */
234#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
235/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
236#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
237/** 7 VM entry with invalid control field(s). */
238#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
239/** 8 VM entry with invalid host-state field(s). */
240#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
241/** 9 VMPTRLD with invalid physical address. */
242#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
243/** 10 VMPTRLD with VMXON pointer. */
244#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
245/** 11 VMPTRLD with incorrect VMCS revision identifier. */
246#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
247/** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
248#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
249#define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
250/** 13 VMWRITE to read-only VMCS component. */
251#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
252/** 15 VMXON executed in VMX root operation. */
253#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
254/** 16 VM entry with invalid executive-VMCS pointer. */
255#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
256/** 17 VM entry with non-launched executive VMCS. */
257#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
258/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
259#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
260/** 19 VMCALL with non-clear VMCS. */
261#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
262/** 20 VMCALL with invalid VM-exit control fields. */
263#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
264/** 22 VMCALL with incorrect MSEG revision identifier. */
265#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
266/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
267#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
268/** 24 VMCALL with invalid SMM-monitor features. */
269#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
270/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
271#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
272/** 26 VM entry with events blocked by MOV SS. */
273#define VMX_ERROR_VMENTRY_MOV_SS 26
274
275/** @} */
276
277
278/** VMX MSR bit definitions
279 * @{
280 */
281
282/** Basic VMX information.
283 * @{
284 */
285/** VMCS revision identifier used by the processor. */
286#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
287/** Size of the VMCS. */
288#define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
289/** Width of physical address used for the VMCS.
290 * 0 -> limited to the available amount of physical ram
291 * 1 -> within the first 4 GB
292 */
293#define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
294/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
295#define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
296/** Memory type that must be used for the VMCS. */
297#define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
298/** @} */
299
300
301/** Misc VMX info.
302 * @{
303 */
304/** Activity states supported by the implementation. */
305#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
306/** Number of CR3 target values supported by the processor. (0-256) */
307#define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
308/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
309#define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
310/** MSEG revision identifier used by the processor. */
311#define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
312/** @} */
313
314
315/** VMCS enumeration field info
316 * @{
317 */
318/** Highest field index. */
319#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
320
321/** @} */
322
323
324/** MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR
325 * @{
326 */
327#define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)
328#define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)
329#define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)
330#define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)
331#define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)
332#define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)
333#define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)
334#define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)
335#define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)
336#define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)
337#define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)
338#define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)
339#define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)
340#define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)
341#define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)
342#define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)
343#define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)
344#define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)
345#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)
346#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)
347#define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)
348#define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)
349#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)
350#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)
351#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)
352#define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)
353
354/** @} */
355
356/** @} */
357
358
359/** VMCS field encoding
360 * @{
361 */
362
363/* 16 bits guest fields
364 * @{
365 */
366#define VMX_VMCS_GUEST_FIELD_VPID 0x0
367#define VMX_VMCS_GUEST_FIELD_ES 0x800
368#define VMX_VMCS_GUEST_FIELD_CS 0x802
369#define VMX_VMCS_GUEST_FIELD_SS 0x804
370#define VMX_VMCS_GUEST_FIELD_DS 0x806
371#define VMX_VMCS_GUEST_FIELD_FS 0x808
372#define VMX_VMCS_GUEST_FIELD_GS 0x80A
373#define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
374#define VMX_VMCS_GUEST_FIELD_TR 0x80E
375/** @} */
376
377/** 16 bits host fields
378 * @{
379 */
380#define VMX_VMCS_HOST_FIELD_ES 0xC00
381#define VMX_VMCS_HOST_FIELD_CS 0xC02
382#define VMX_VMCS_HOST_FIELD_SS 0xC04
383#define VMX_VMCS_HOST_FIELD_DS 0xC06
384#define VMX_VMCS_HOST_FIELD_FS 0xC08
385#define VMX_VMCS_HOST_FIELD_GS 0xC0A
386#define VMX_VMCS_HOST_FIELD_TR 0xC0C
387/** @} */
388
389/** 64 bits host fields
390 * @{
391 */
392#define VMX_VMCS_HOST_FIELD_PAT_FULL 0x2C00
393#define VMX_VMCS_HOST_FIELD_PAT_HIGH 0x2C01
394#define VMX_VMCS_HOST_FIELD_EFER_FULL 0x2C02
395#define VMX_VMCS_HOST_FIELD_EFER_HIGH 0x2C03
396#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_FULL 0x2C04 /* MSR IA32_PERF_GLOBAL_CTRL */
397#define VMX_VMCS_HOST_PERF_GLOBAL_CTRL_HIGH 0x2C05 /* MSR IA32_PERF_GLOBAL_CTRL */
398/** @} */
399
400
401/** 64 Bits control fields
402 * @{
403 */
404#define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
405#define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
406#define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
407#define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
408
409/* Optional */
410#define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
411#define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
412
413#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
414#define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
415#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
416#define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
417
418#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
419#define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
420
421#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
422#define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
423
424#define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
425#define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
426
427/* Optional */
428#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
429#define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
430
431/** Extended page table pointer. */
432#define VMX_VMCS_CTRL_EPTP_FULL 0x201a
433#define VMX_VMCS_CTRL_EPTP_HIGH 0x201b
434
435/** VM-exit phyiscal address. */
436#define VMX_VMCS_EXIT_PHYS_ADDR_FULL 0x2400
437#define VMX_VMCS_EXIT_PHYS_ADDR_HIGH 0x2401
438/** @} */
439
440
441/** 64 Bits guest fields
442 * @{
443 */
444#define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
445#define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
446#define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
447#define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
448#define VMX_VMCS_GUEST_PAT_FULL 0x2804
449#define VMX_VMCS_GUEST_PAT_HIGH 0x2805
450#define VMX_VMCS_GUEST_EFER_FULL 0x2806
451#define VMX_VMCS_GUEST_EFER_HIGH 0x2807
452#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808 /* MSR IA32_PERF_GLOBAL_CTRL */
453#define VMX_VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809 /* MSR IA32_PERF_GLOBAL_CTRL */
454#define VMX_VMCS_GUEST_PDPTR0_FULL 0x280A
455#define VMX_VMCS_GUEST_PDPTR0_HIGH 0x280B
456#define VMX_VMCS_GUEST_PDPTR1_FULL 0x280C
457#define VMX_VMCS_GUEST_PDPTR1_HIGH 0x280D
458#define VMX_VMCS_GUEST_PDPTR2_FULL 0x280E
459#define VMX_VMCS_GUEST_PDPTR2_HIGH 0x280F
460#define VMX_VMCS_GUEST_PDPTR3_FULL 0x2810
461#define VMX_VMCS_GUEST_PDPTR3_HIGH 0x2811
462/** @} */
463
464
465/** 32 Bits control fields
466 * @{
467 */
468#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
469#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
470#define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
471#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
472#define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
473#define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
474#define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
475#define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
476#define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
477#define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
478#define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
479#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
480#define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
481#define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
482/** This field exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution control. */
483#define VMX_VMCS_CTRL_TPR_THRESHOLD 0x401C
484/** This field exists only on processors that support the 1-setting of the “activate secondary controls” VM-execution control. */
485#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 0x401E
486/** @} */
487
488
489/** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
490 * @{
491 */
492/* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
493#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
494/* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
495#define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
496/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
497/** @} */
498
499/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
500 * @{
501 */
502/* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
503#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
504/* Use timestamp counter offset. */
505#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
506/* VM Exit when executing the HLT instruction. */
507#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
508/* VM Exit when executing the INVLPG instruction. */
509#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
510/* VM Exit when executing the MWAIT instruction. */
511#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
512/* VM Exit when executing the RDPMC instruction. */
513#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
514/* VM Exit when executing the RDTSC instruction. */
515#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
516/* VM Exit on CR8 loads. */
517#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
518/* VM Exit on CR8 stores. */
519#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
520/* Use TPR shadow. */
521#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
522/* VM Exit when executing a MOV DRx instruction. */
523#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
524/* VM Exit when executing IO instructions. */
525#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
526/* Use IO bitmaps. */
527#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
528/* Use MSR bitmaps. */
529#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
530/* VM Exit when executing the MONITOR instruction. */
531#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
532/* VM Exit when executing the PAUSE instruction. */
533#define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
534/* Determines whether the secondary processor based VM-execution controls are used. */
535#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL RT_BIT(31)
536/** @} */
537
538/** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
539 * @{
540 */
541/** Virtualize APIC access. */
542#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
543/** EPT supported/enabled. */
544#define VMX_VMCS_CTRL_PROC_EXEC2_EPT RT_BIT(1)
545/** VPID supported/enabled. */
546#define VMX_VMCS_CTRL_PROC_EXEC2_VPID RT_BIT(5)
547/** VM Exit when executing the WBINVD instruction. */
548#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT RT_BIT(6)
549/** @} */
550
551
552/** VMX_VMCS_CTRL_ENTRY_CONTROLS
553 * @{
554 */
555/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
556#define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
557/** In SMM mode after VM-entry. */
558#define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
559/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
560#define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
561/** @} */
562
563
564/** VMX_VMCS_CTRL_EXIT_CONTROLS
565 * @{
566 */
567/** Return to long mode after a VM-exit. */
568#define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
569/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
570#define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
571/** @} */
572
573/** 32 Bits read-only fields
574 * @{
575 */
576#define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
577#define VMX_VMCS_RO_EXIT_REASON 0x4402
578#define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
579#define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
580#define VMX_VMCS_RO_IDT_INFO 0x4408
581#define VMX_VMCS_RO_IDT_ERRCODE 0x440A
582#define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
583#define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
584/** @} */
585
586/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
587 * @{
588 */
589#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
590#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
591#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
592#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
593#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
594#define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
595#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
596#define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
597/* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
598#define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
599/** @} */
600
601/** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
602 * @{
603 */
604#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
605#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
606#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
607#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
608#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
609/** @} */
610
611
612/** 32 Bits guest state fields
613 * @{
614 */
615#define VMX_VMCS_GUEST_ES_LIMIT 0x4800
616#define VMX_VMCS_GUEST_CS_LIMIT 0x4802
617#define VMX_VMCS_GUEST_SS_LIMIT 0x4804
618#define VMX_VMCS_GUEST_DS_LIMIT 0x4806
619#define VMX_VMCS_GUEST_FS_LIMIT 0x4808
620#define VMX_VMCS_GUEST_GS_LIMIT 0x480A
621#define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
622#define VMX_VMCS_GUEST_TR_LIMIT 0x480E
623#define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
624#define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
625#define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
626#define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
627#define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
628#define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
629#define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
630#define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
631#define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
632#define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
633#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
634#define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
635#define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
636/** @} */
637
638
639/** VMX_VMCS_GUEST_ACTIVITY_STATE
640 * @{
641 */
642/* The logical processor is active. */
643#define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
644/* The logical processor is inactive, because executed a HLT instruction. */
645#define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
646/* The logical processor is inactive, because of a triple fault or other serious error. */
647#define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
648/* The logical processor is inactive, because it's waiting for a startup-IPI */
649#define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
650/** @} */
651
652
653/** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
654 * @{
655 */
656#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
657#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
658#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
659#define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
660/** @} */
661
662
663/** 32 Bits host state fields
664 * @{
665 */
666#define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
667/** @} */
668
669/** Natural width control fields
670 * @{
671 */
672#define VMX_VMCS_CTRL_CR0_MASK 0x6000
673#define VMX_VMCS_CTRL_CR4_MASK 0x6002
674#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
675#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
676#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
677#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
678#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
679#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
680/** @} */
681
682
683/** Natural width read-only data fields
684 * @{
685 */
686#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
687#define VMX_VMCS_RO_IO_RCX 0x6402
688#define VMX_VMCS_RO_IO_RSX 0x6404
689#define VMX_VMCS_RO_IO_RDI 0x6406
690#define VMX_VMCS_RO_IO_RIP 0x6408
691#define VMX_VMCS_EXIT_GUEST_LINEAR_ADDR 0x640A
692/** @} */
693
694
695/** VMX_VMCS_RO_EXIT_QUALIFICATION
696 * @{
697 */
698
699/** DRx moves
700 * @{
701 */
702/** 0-2: Debug register number */
703#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
704/** 3: Reserved; cleared to 0. */
705#define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
706/** 4: Direction of move (0 = write, 1 = read) */
707#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
708/** 5-7: Reserved; cleared to 0. */
709#define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
710/** 8-11: General purpose register number. */
711#define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
712/** Rest: reserved. */
713
714/** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
715 * @{
716 */
717#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
718#define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
719/** @} */
720
721/** @} */
722
723
724/** CRx accesses
725 * @{
726 */
727/** 0-3: Control register number (0 for CLTS & LMSW) */
728#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
729/** 4-5: Access type. */
730#define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
731/** 6: LMSW operand type */
732#define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
733/** 7: Reserved; cleared to 0. */
734#define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
735/** 8-11: General purpose register number (0 for CLTS & LMSW). */
736#define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
737/** 12-15: Reserved; cleared to 0. */
738#define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
739/** 16-31: LMSW source data (else 0). */
740#define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
741/** Rest: reserved. */
742
743
744/** VMX_EXIT_QUALIFICATION_CRX_ACCESS
745 * @{
746 */
747#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
748#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
749#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
750#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
751/** @} */
752
753/** @} */
754
755
756/** VMX_EXIT_PORT_IO
757 * @{
758 */
759/** 0-2: IO operation width. */
760#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
761/** 3: IO operation direction. */
762#define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
763/** 4: String IO operation. */
764#define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
765/** 5: Repeated IO operation. */
766#define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
767/** 6: Operand encoding. */
768#define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
769/** 16-31: IO Port (0-0xffff). */
770#define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
771/* Rest reserved. */
772/** @} */
773
774/** VMX_EXIT_QUALIFICATION_IO_DIRECTION
775 * @{
776 */
777#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
778#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
779/** @} */
780
781
782/** VMX_EXIT_QUALIFICATION_IO_ENCODING
783 * @{
784 */
785#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
786#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
787/** @} */
788
789/** @} */
790
791/** Natural width guest state fields
792 * @{
793 */
794#define VMX_VMCS_GUEST_CR0 0x6800
795#define VMX_VMCS_GUEST_CR3 0x6802
796#define VMX_VMCS_GUEST_CR4 0x6804
797#define VMX_VMCS_GUEST_ES_BASE 0x6806
798#define VMX_VMCS_GUEST_CS_BASE 0x6808
799#define VMX_VMCS_GUEST_SS_BASE 0x680A
800#define VMX_VMCS_GUEST_DS_BASE 0x680C
801#define VMX_VMCS_GUEST_FS_BASE 0x680E
802#define VMX_VMCS_GUEST_GS_BASE 0x6810
803#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
804#define VMX_VMCS_GUEST_TR_BASE 0x6814
805#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
806#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
807#define VMX_VMCS_GUEST_DR7 0x681A
808#define VMX_VMCS_GUEST_RSP 0x681C
809#define VMX_VMCS_GUEST_RIP 0x681E
810#define VMX_VMCS_GUEST_RFLAGS 0x6820
811#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
812#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
813#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
814/** @} */
815
816
817/** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
818 * @{
819 */
820/* Hardware breakpoint 0 was met. */
821#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
822/* Hardware breakpoint 1 was met. */
823#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
824/* Hardware breakpoint 2 was met. */
825#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
826/* Hardware breakpoint 3 was met. */
827#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
828/* At least one data or IO breakpoint was hit. */
829#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
830/* A debug exception would have been triggered by single-step execution mode. */
831#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
832/* Bits 4-11, 13 and 15-63 are reserved. */
833
834
835
836
837/** @} */
838
839/** Natural width host state fields
840 * @{
841 */
842#define VMX_VMCS_HOST_CR0 0x6C00
843#define VMX_VMCS_HOST_CR3 0x6C02
844#define VMX_VMCS_HOST_CR4 0x6C04
845#define VMX_VMCS_HOST_FS_BASE 0x6C06
846#define VMX_VMCS_HOST_GS_BASE 0x6C08
847#define VMX_VMCS_HOST_TR_BASE 0x6C0A
848#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
849#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
850#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
851#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
852#define VMX_VMCS_HOST_RSP 0x6C14
853#define VMX_VMCS_HOST_RIP 0x6C16
854/** @} */
855
856/** @} */
857
858
859#if RT_INLINE_ASM_GNU_STYLE
860# define __STR(x) #x
861# define STR(x) __STR(x)
862#endif
863
864
865/** @} */
866
867/** @defgroup grp_vmx_asm vmx assembly helpers
868 * @ingroup grp_vmx
869 * @{
870 */
871
872/**
873 * Executes VMXON
874 *
875 * @returns VBox status code
876 * @param pVMXOn Physical address of VMXON structure
877 */
878#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
879DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
880#else
881DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
882{
883 int rc = VINF_SUCCESS;
884# if RT_INLINE_ASM_GNU_STYLE
885 __asm__ __volatile__ (
886 "push %3 \n\t"
887 "push %2 \n\t"
888 ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
889 "ja 2f \n\t"
890 "je 1f \n\t"
891 "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
892 "jmp 2f \n\t"
893 "1: \n\t"
894 "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
895 "2: \n\t"
896 "add $8, %%esp \n\t"
897 :"=rm"(rc)
898 :"0"(VINF_SUCCESS),
899 "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
900 "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
901 :"memory"
902 );
903# else
904 __asm
905 {
906 push dword ptr [pVMXOn+4]
907 push dword ptr [pVMXOn]
908 _emit 0xF3
909 _emit 0x0F
910 _emit 0xC7
911 _emit 0x34
912 _emit 0x24 /* VMXON [esp] */
913 jnc vmxon_good
914 mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
915 jmp the_end
916
917vmxon_good:
918 jnz the_end
919 mov dword ptr [rc], VERR_VMX_GENERIC
920the_end:
921 add esp, 8
922 }
923# endif
924 return rc;
925}
926#endif
927
928
929/**
930 * Executes VMXOFF
931 */
932#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
933DECLASM(void) VMXDisable(void);
934#else
935DECLINLINE(void) VMXDisable(void)
936{
937# if RT_INLINE_ASM_GNU_STYLE
938 __asm__ __volatile__ (
939 ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
940 );
941# else
942 __asm
943 {
944 _emit 0x0F
945 _emit 0x01
946 _emit 0xC4 /* VMXOFF */
947 }
948# endif
949}
950#endif
951
952
953/**
954 * Executes VMCLEAR
955 *
956 * @returns VBox status code
957 * @param pVMCS Physical address of VM control structure
958 */
959#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
960DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
961#else
962DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
963{
964 int rc = VINF_SUCCESS;
965# if RT_INLINE_ASM_GNU_STYLE
966 __asm__ __volatile__ (
967 "push %3 \n\t"
968 "push %2 \n\t"
969 ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
970 "jnc 1f \n\t"
971 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
972 "1: \n\t"
973 "add $8, %%esp \n\t"
974 :"=rm"(rc)
975 :"0"(VINF_SUCCESS),
976 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
977 "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
978 :"memory"
979 );
980# else
981 __asm
982 {
983 push dword ptr [pVMCS+4]
984 push dword ptr [pVMCS]
985 _emit 0x66
986 _emit 0x0F
987 _emit 0xC7
988 _emit 0x34
989 _emit 0x24 /* VMCLEAR [esp] */
990 jnc success
991 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
992success:
993 add esp, 8
994 }
995# endif
996 return rc;
997}
998#endif
999
1000
1001/**
1002 * Executes VMPTRLD
1003 *
1004 * @returns VBox status code
1005 * @param pVMCS Physical address of VMCS structure
1006 */
1007#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1008DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
1009#else
1010DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
1011{
1012 int rc = VINF_SUCCESS;
1013# if RT_INLINE_ASM_GNU_STYLE
1014 __asm__ __volatile__ (
1015 "push %3 \n\t"
1016 "push %2 \n\t"
1017 ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
1018 "jnc 1f \n\t"
1019 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1020 "1: \n\t"
1021 "add $8, %%esp \n\t"
1022 :"=rm"(rc)
1023 :"0"(VINF_SUCCESS),
1024 "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
1025 "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
1026 );
1027# else
1028 __asm
1029 {
1030 push dword ptr [pVMCS+4]
1031 push dword ptr [pVMCS]
1032 _emit 0x0F
1033 _emit 0xC7
1034 _emit 0x34
1035 _emit 0x24 /* VMPTRLD [esp] */
1036 jnc success
1037 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1038
1039success:
1040 add esp, 8
1041 }
1042# endif
1043 return rc;
1044}
1045#endif
1046
1047
1048/**
1049 * Executes VMWRITE
1050 *
1051 * @returns VBox status code
1052 * @param idxField VMCS index
1053 * @param u64Val 16, 32 or 64 bits value
1054 */
1055DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
1056
1057/**
1058 * Executes VMWRITE
1059 *
1060 * @returns VBox status code
1061 * @param idxField VMCS index
1062 * @param u32Val 32 bits value
1063 */
1064#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1065DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
1066#else
1067DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
1068{
1069 int rc = VINF_SUCCESS;
1070# if RT_INLINE_ASM_GNU_STYLE
1071 __asm__ __volatile__ (
1072 ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
1073 "ja 2f \n\t"
1074 "je 1f \n\t"
1075 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1076 "jmp 2f \n\t"
1077 "1: \n\t"
1078 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1079 "2: \n\t"
1080 :"=rm"(rc)
1081 :"0"(VINF_SUCCESS),
1082 "a"(idxField),
1083 "d"(u32Val)
1084 );
1085# else
1086 __asm
1087 {
1088 push dword ptr [u32Val]
1089 mov eax, [idxField]
1090 _emit 0x0F
1091 _emit 0x79
1092 _emit 0x04
1093 _emit 0x24 /* VMWRITE eax, [esp] */
1094 jnc valid_vmcs
1095 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1096 jmp the_end
1097
1098valid_vmcs:
1099 jnz the_end
1100 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1101the_end:
1102 add esp, 4
1103 }
1104# endif
1105 return rc;
1106}
1107#endif
1108
1109#if HC_ARCH_BITS == 64
1110#define VMXWriteVMCS VMXWriteVMCS64
1111#else
1112#define VMXWriteVMCS VMXWriteVMCS32
1113#endif /* HC_ARCH_BITS == 64 */
1114
1115
1116/**
1117 * Executes VMREAD
1118 *
1119 * @returns VBox status code
1120 * @param idxField VMCS index
1121 * @param pData Ptr to store VM field value
1122 */
1123DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
1124
1125/**
1126 * Executes VMREAD
1127 *
1128 * @returns VBox status code
1129 * @param idxField VMCS index
1130 * @param pData Ptr to store VM field value
1131 */
1132#if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
1133DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
1134#else
1135DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
1136{
1137 int rc = VINF_SUCCESS;
1138# if RT_INLINE_ASM_GNU_STYLE
1139 __asm__ __volatile__ (
1140 "movl $"STR(VINF_SUCCESS)", %0 \n\t"
1141 ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
1142 "ja 2f \n\t"
1143 "je 1f \n\t"
1144 "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
1145 "jmp 2f \n\t"
1146 "1: \n\t"
1147 "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
1148 "2: \n\t"
1149 :"=&r"(rc),
1150 "=d"(*pData)
1151 :"a"(idxField),
1152 "d"(0)
1153 );
1154# else
1155 __asm
1156 {
1157 sub esp, 4
1158 mov dword ptr [esp], 0
1159 mov eax, [idxField]
1160 _emit 0x0F
1161 _emit 0x78
1162 _emit 0x04
1163 _emit 0x24 /* VMREAD eax, [esp] */
1164 mov edx, pData
1165 pop dword ptr [edx]
1166 jnc valid_vmcs
1167 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
1168 jmp the_end
1169
1170valid_vmcs:
1171 jnz the_end
1172 mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
1173the_end:
1174 }
1175# endif
1176 return rc;
1177}
1178#endif
1179
1180#if HC_ARCH_BITS == 64
1181#define VMXReadVMCS VMXReadVMCS64
1182#else
1183#define VMXReadVMCS VMXReadVMCS32
1184#endif /* HC_ARCH_BITS == 64 */
1185
1186/**
1187 * Gets the last instruction error value from the current VMCS
1188 *
1189 * @returns error value
1190 */
1191DECLINLINE(uint32_t) VMXGetLastError(void)
1192{
1193#if HC_ARCH_BITS == 64
1194 uint64_t uLastError = 0;
1195 int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
1196 AssertRC(rc);
1197 return (uint32_t)uLastError;
1198
1199#else /* 32-bit host: */
1200 uint32_t lasterr = 0;
1201 int rc;
1202
1203 rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
1204 AssertRC(rc);
1205 return lasterr;
1206#endif
1207}
1208
1209/** @} */
1210
1211#endif
1212
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