[1] | 1 | /** @file
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| 2 | * HWACC/VMX - VMX Structures and Definitions.
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| 3 | */
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| 4 |
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| 5 | /*
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[8155] | 6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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[1] | 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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[8155] | 24 | *
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| 25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 27 | * additional information or have any questions.
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[1] | 28 | */
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| 29 |
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[3632] | 30 | #ifndef ___VBox_vmx_h
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| 31 | #define ___VBox_vmx_h
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[1] | 32 |
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| 33 | #include <VBox/types.h>
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| 34 | #include <VBox/err.h>
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| 35 | #include <iprt/assert.h>
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| 36 | #include <iprt/asm.h>
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| 37 |
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| 38 | /** @defgroup grp_vmx vmx Types and Definitions
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| 39 | * @ingroup grp_hwaccm
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| 40 | * @{
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| 41 | */
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| 42 |
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| 43 | /** VMX Basic Exit Reasons.
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| 44 | * @{
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| 45 | */
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| 46 | /* And-mask for setting reserved bits to zero */
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| 47 | #define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
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| 48 | /* Or-mask for setting reserved bits to 1 */
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| 49 | #define VMX_EFLAGS_RESERVED_1 0x00000002
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| 50 | /** @} */
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| 51 |
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| 52 | /** VMX Basic Exit Reasons.
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| 53 | * @{
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| 54 | */
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| 55 | /** 0 Exception or non-maskable interrupt (NMI). */
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| 56 | #define VMX_EXIT_EXCEPTION 0
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| 57 | /** 1 External interrupt. */
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| 58 | #define VMX_EXIT_EXTERNAL_IRQ 1
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| 59 | /** 2 Triple fault. */
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| 60 | #define VMX_EXIT_TRIPLE_FAULT 2
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| 61 | /** 3 INIT signal. */
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| 62 | #define VMX_EXIT_INIT_SIGNAL 3
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| 63 | /** 4 Start-up IPI (SIPI). */
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| 64 | #define VMX_EXIT_SIPI 4
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| 65 | /** 5 I/O system-management interrupt (SMI). */
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| 66 | #define VMX_EXIT_IO_SMI_IRQ 5
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| 67 | /** 6 Other SMI. */
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| 68 | #define VMX_EXIT_SMI_IRQ 6
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| 69 | /** 7 Interrupt window. */
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| 70 | #define VMX_EXIT_IRQ_WINDOW 7
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| 71 | /** 9 Task switch. */
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| 72 | #define VMX_EXIT_TASK_SWITCH 9
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| 73 | /** 10 Guest software attempted to execute CPUID. */
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| 74 | #define VMX_EXIT_CPUID 10
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| 75 | /** 12 Guest software attempted to execute HLT. */
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| 76 | #define VMX_EXIT_HLT 12
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| 77 | /** 13 Guest software attempted to execute INVD. */
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| 78 | #define VMX_EXIT_INVD 13
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| 79 | /** 14 Guest software attempted to execute INVPG. */
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| 80 | #define VMX_EXIT_INVPG 14
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| 81 | /** 15 Guest software attempted to execute RDPMC. */
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| 82 | #define VMX_EXIT_RDPMC 15
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| 83 | /** 16 Guest software attempted to execute RDTSC. */
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| 84 | #define VMX_EXIT_RDTSC 16
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| 85 | /** 17 Guest software attempted to execute RSM in SMM. */
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| 86 | #define VMX_EXIT_RSM 17
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| 87 | /** 18 Guest software executed VMCALL. */
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| 88 | #define VMX_EXIT_VMCALL 18
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| 89 | /** 19 Guest software executed VMCLEAR. */
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| 90 | #define VMX_EXIT_VMCLEAR 19
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| 91 | /** 20 Guest software executed VMLAUNCH. */
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| 92 | #define VMX_EXIT_VMLAUNCH 20
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| 93 | /** 21 Guest software executed VMPTRLD. */
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| 94 | #define VMX_EXIT_VMPTRLD 21
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| 95 | /** 22 Guest software executed VMPTRST. */
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| 96 | #define VMX_EXIT_VMPTRST 22
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| 97 | /** 23 Guest software executed VMREAD. */
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| 98 | #define VMX_EXIT_VMREAD 23
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| 99 | /** 24 Guest software executed VMRESUME. */
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| 100 | #define VMX_EXIT_VMRESUME 24
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| 101 | /** 25 Guest software executed VMWRITE. */
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| 102 | #define VMX_EXIT_VMWRITE 25
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| 103 | /** 26 Guest software executed VMXOFF. */
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| 104 | #define VMX_EXIT_VMXOFF 26
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| 105 | /** 27 Guest software executed VMXON. */
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| 106 | #define VMX_EXIT_VMXON 27
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| 107 | /** 28 Control-register accesses. */
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| 108 | #define VMX_EXIT_CRX_MOVE 28
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| 109 | /** 29 Debug-register accesses. */
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| 110 | #define VMX_EXIT_DRX_MOVE 29
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| 111 | /** 30 I/O instruction. */
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| 112 | #define VMX_EXIT_PORT_IO 30
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| 113 | /** 31 RDMSR. Guest software attempted to execute RDMSR. */
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| 114 | #define VMX_EXIT_RDMSR 31
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| 115 | /** 32 WRMSR. Guest software attempted to execute WRMSR. */
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| 116 | #define VMX_EXIT_WRMSR 32
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| 117 | /** 33 VM-entry failure due to invalid guest state. */
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| 118 | #define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
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| 119 | /** 34 VM-entry failure due to MSR loading. */
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| 120 | #define VMX_EXIT_ERR_MSR_LOAD 34
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| 121 | /** 36 Guest software executed MWAIT. */
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| 122 | #define VMX_EXIT_MWAIT 36
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| 123 | /** 39 Guest software attempted to execute MONITOR. */
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| 124 | #define VMX_EXIT_MONITOR 39
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| 125 | /** 40 Guest software attempted to execute PAUSE. */
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| 126 | #define VMX_EXIT_PAUSE 40
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| 127 | /** 41 VM-entry failure due to machine-check. */
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| 128 | #define VMX_EXIT_ERR_MACHINE_CHECK 41
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| 129 | /** 43 TPR below threshold. Guest software executed MOV to CR8. */
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| 130 | #define VMX_EXIT_TPR 43
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| 131 |
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| 132 | /** @} */
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| 133 |
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| 134 |
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| 135 | /** VM Instruction Errors
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| 136 | * @{
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| 137 | */
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| 138 | /** 1 VMCALL executed in VMX root operation. */
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| 139 | #define VMX_ERROR_VMCALL 1
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| 140 | /** 2 VMCLEAR with invalid physical address. */
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| 141 | #define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
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| 142 | /** 3 VMCLEAR with VMXON pointer. */
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| 143 | #define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
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| 144 | /** 4 VMLAUNCH with non-clear VMCS. */
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| 145 | #define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
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| 146 | /** 5 VMRESUME with non-launched VMCS. */
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| 147 | #define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
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| 148 | /** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
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| 149 | #define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
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| 150 | /** 7 VM entry with invalid control field(s). */
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| 151 | #define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
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| 152 | /** 8 VM entry with invalid host-state field(s). */
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| 153 | #define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
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| 154 | /** 9 VMPTRLD with invalid physical address. */
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| 155 | #define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
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| 156 | /** 10 VMPTRLD with VMXON pointer. */
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| 157 | #define VMX_ERROR_VMPTRLD_VMXON_PTR 10
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| 158 | /** 11 VMPTRLD with incorrect VMCS revision identifier. */
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| 159 | #define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
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| 160 | /** 12 VMREAD/VMWRITE from/to unsupported VMCS component. */
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| 161 | #define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
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| 162 | #define VMX_ERROR_VMWRITE_INVALID_COMPONENT VMX_ERROR_VMREAD_INVALID_COMPONENT
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| 163 | /** 13 VMWRITE to read-only VMCS component. */
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| 164 | #define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
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| 165 | /** 15 VMXON executed in VMX root operation. */
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| 166 | #define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
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| 167 | /** 16 VM entry with invalid executive-VMCS pointer. */
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| 168 | #define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
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| 169 | /** 17 VM entry with non-launched executive VMCS. */
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| 170 | #define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
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| 171 | /** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
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| 172 | #define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
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| 173 | /** 19 VMCALL with non-clear VMCS. */
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| 174 | #define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
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| 175 | /** 20 VMCALL with invalid VM-exit control fields. */
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| 176 | #define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
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| 177 | /** 22 VMCALL with incorrect MSEG revision identifier. */
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| 178 | #define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
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| 179 | /** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
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| 180 | #define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
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| 181 | /** 24 VMCALL with invalid SMM-monitor features. */
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| 182 | #define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
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| 183 | /** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
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| 184 | #define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
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| 185 | /** 26 VM entry with events blocked by MOV SS. */
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| 186 | #define VMX_ERROR_VMENTRY_MOV_SS 26
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| 187 |
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| 188 | /** @} */
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| 189 |
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| 190 |
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| 191 | /** VMX MSR bit definitions
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| 192 | * @{
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| 193 | */
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| 194 |
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| 195 | /** Basic VMX information.
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| 196 | * @{
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| 197 | */
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| 198 | /** VMCS revision identifier used by the processor. */
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| 199 | #define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
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| 200 | /** Size of the VMCS. */
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[7452] | 201 | #define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a) ((a >> 32ULL) & 0xFFF)
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[1] | 202 | /** Width of physical address used for the VMCS.
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| 203 | * 0 -> limited to the available amount of physical ram
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| 204 | * 1 -> within the first 4 GB
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| 205 | */
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| 206 | #define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a) ((a >> 48ULL) & 1)
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| 207 | /** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
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| 208 | #define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a) ((a >> 49ULL) & 1)
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| 209 | /** Memory type that must be used for the VMCS. */
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| 210 | #define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a) ((a >> 50ULL) & 0xF)
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| 211 | /** @} */
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| 212 |
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| 213 |
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| 214 | /** Misc VMX info.
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| 215 | * @{
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| 216 | */
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| 217 | /** Activity states supported by the implementation. */
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| 218 | #define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a) ((a >> 6ULL) & 0x7)
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| 219 | /** Number of CR3 target values supported by the processor. (0-256) */
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| 220 | #define MSR_IA32_VMX_MISC_CR3_TARGET(a) ((a >> 16ULL) & 0x1FF)
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| 221 | /** Maximum nr of MSRs in the VMCS. (N+1)*512. */
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[2763] | 222 | #define MSR_IA32_VMX_MISC_MAX_MSR(a) ((((a >> 25ULL) & 0x7) + 1) * 512)
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[1] | 223 | /** MSEG revision identifier used by the processor. */
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| 224 | #define MSR_IA32_VMX_MISC_MSEG_ID(a) (a >> 32ULL)
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| 225 | /** @} */
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| 226 |
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| 227 |
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| 228 | /** VMCS enumeration field info
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| 229 | * @{
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| 230 | */
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| 231 | /** Highest field index. */
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[3362] | 232 | #define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a) ((a >> 1ULL) & 0x1FF)
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[1] | 233 |
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| 234 | /** @} */
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| 235 |
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| 236 | /** @} */
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| 237 |
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| 238 |
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| 239 | /** VMCS field encoding
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| 240 | * @{
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| 241 | */
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| 242 |
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| 243 | /* 16 bits guest fields
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| 244 | * @{
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| 245 | */
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| 246 | #define VMX_VMCS_GUEST_FIELD_ES 0x800
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| 247 | #define VMX_VMCS_GUEST_FIELD_CS 0x802
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| 248 | #define VMX_VMCS_GUEST_FIELD_SS 0x804
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| 249 | #define VMX_VMCS_GUEST_FIELD_DS 0x806
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| 250 | #define VMX_VMCS_GUEST_FIELD_FS 0x808
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| 251 | #define VMX_VMCS_GUEST_FIELD_GS 0x80A
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| 252 | #define VMX_VMCS_GUEST_FIELD_LDTR 0x80C
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| 253 | #define VMX_VMCS_GUEST_FIELD_TR 0x80E
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| 254 | /** @} */
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| 255 |
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| 256 | /** 16 bits host fields
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| 257 | * @{
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| 258 | */
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| 259 | #define VMX_VMCS_HOST_FIELD_ES 0xC00
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| 260 | #define VMX_VMCS_HOST_FIELD_CS 0xC02
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| 261 | #define VMX_VMCS_HOST_FIELD_SS 0xC04
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| 262 | #define VMX_VMCS_HOST_FIELD_DS 0xC06
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| 263 | #define VMX_VMCS_HOST_FIELD_FS 0xC08
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| 264 | #define VMX_VMCS_HOST_FIELD_GS 0xC0A
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| 265 | #define VMX_VMCS_HOST_FIELD_TR 0xC0C
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| 266 | /** @} */
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| 267 |
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| 268 | /** 64 Bits control fields
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| 269 | * @{
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| 270 | */
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| 271 | #define VMX_VMCS_CTRL_IO_BITMAP_A_FULL 0x2000
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| 272 | #define VMX_VMCS_CTRL_IO_BITMAP_A_HIGH 0x2001
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| 273 | #define VMX_VMCS_CTRL_IO_BITMAP_B_FULL 0x2002
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| 274 | #define VMX_VMCS_CTRL_IO_BITMAP_B_HIGH 0x2003
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| 275 |
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| 276 | /* Optional */
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| 277 | #define VMX_VMCS_CTRL_MSR_BITMAP_FULL 0x2004
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| 278 | #define VMX_VMCS_CTRL_MSR_BITMAP_HIGH 0x2005
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| 279 |
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| 280 | #define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL 0x2006
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| 281 | #define VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH 0x2007
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| 282 | #define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL 0x2008
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| 283 | #define VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH 0x2009
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| 284 |
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| 285 | #define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL 0x200A
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| 286 | #define VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH 0x200B
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| 287 |
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| 288 | #define VMX_VMCS_CTRL_EXEC_VMCS_PTR_FULL 0x200C
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| 289 | #define VMX_VMCS_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
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| 290 |
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| 291 | #define VMX_VMCS_CTRL_TSC_OFFSET_FULL 0x2010
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| 292 | #define VMX_VMCS_CTRL_TSC_OFFSET_HIGH 0x2011
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| 293 |
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| 294 | /* Optional */
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| 295 | #define VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL 0x2012
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| 296 | #define VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
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| 297 | /** @} */
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| 298 |
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| 299 |
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| 300 | /** 64 Bits guest fields
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| 301 | * @{
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| 302 | */
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| 303 | #define VMX_VMCS_GUEST_LINK_PTR_FULL 0x2800
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| 304 | #define VMX_VMCS_GUEST_LINK_PTR_HIGH 0x2801
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| 305 | #define VMX_VMCS_GUEST_DEBUGCTL_FULL 0x2802 /* MSR IA32_DEBUGCTL */
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| 306 | #define VMX_VMCS_GUEST_DEBUGCTL_HIGH 0x2803 /* MSR IA32_DEBUGCTL */
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| 307 | /** @} */
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| 308 |
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| 309 |
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| 310 | /** 32 Bits control fields
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| 311 | * @{
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| 312 | */
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| 313 | #define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS 0x4000
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| 314 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS 0x4002
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| 315 | #define VMX_VMCS_CTRL_EXCEPTION_BITMAP 0x4004
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| 316 | #define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK 0x4006
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| 317 | #define VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
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| 318 | #define VMX_VMCS_CTRL_CR3_TARGET_COUNT 0x400A
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| 319 | #define VMX_VMCS_CTRL_EXIT_CONTROLS 0x400C
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| 320 | #define VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT 0x400E
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| 321 | #define VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
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| 322 | #define VMX_VMCS_CTRL_ENTRY_CONTROLS 0x4012
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| 323 | #define VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
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| 324 | #define VMX_VMCS_CTRL_ENTRY_IRQ_INFO 0x4016
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| 325 | #define VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
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| 326 | #define VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH 0x401A
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| 327 | /* Optional */
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| 328 | #define VMX_VMCS_CTRL_TPR_TRESHOLD 0x401C
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| 329 | /** @} */
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| 330 |
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| 331 |
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| 332 | /** VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
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| 333 | * @{
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| 334 | */
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| 335 | /* External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
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[5605] | 336 | #define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT RT_BIT(0)
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[1] | 337 | /* Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
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[5605] | 338 | #define VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT RT_BIT(3)
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[1] | 339 | /* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
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| 340 | /** @} */
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| 341 |
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| 342 |
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| 343 | /** VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
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| 344 | * @{
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| 345 | */
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| 346 | /* VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
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[5605] | 347 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT RT_BIT(2)
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[1] | 348 | /* Use timestamp counter offset. */
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[5605] | 349 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET RT_BIT(3)
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[1] | 350 | /* VM Exit when executing the HLT instruction. */
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[5605] | 351 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT RT_BIT(7)
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[1] | 352 | /* VM Exit when executing the INVLPG instruction. */
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[5605] | 353 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT RT_BIT(9)
|
---|
[1] | 354 | /* VM Exit when executing the MWAIT instruction. */
|
---|
[5605] | 355 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT RT_BIT(10)
|
---|
[1] | 356 | /* VM Exit when executing the RDPMC instruction. */
|
---|
[5605] | 357 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT RT_BIT(11)
|
---|
[1] | 358 | /* VM Exit when executing the RDTSC instruction. */
|
---|
[5605] | 359 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT RT_BIT(12)
|
---|
[1] | 360 | /* VM Exit on CR8 loads. */
|
---|
[5605] | 361 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT RT_BIT(19)
|
---|
[1] | 362 | /* VM Exit on CR8 stores. */
|
---|
[5605] | 363 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT RT_BIT(20)
|
---|
[1] | 364 | /* Use TPR shadow. */
|
---|
[5605] | 365 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW RT_BIT(21)
|
---|
[1] | 366 | /* VM Exit when executing a MOV DRx instruction. */
|
---|
[5605] | 367 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT RT_BIT(23)
|
---|
[1] | 368 | /* VM Exit when executing IO instructions. */
|
---|
[5605] | 369 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT RT_BIT(24)
|
---|
[1] | 370 | /* Use IO bitmaps. */
|
---|
[5605] | 371 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS RT_BIT(25)
|
---|
[1] | 372 | /* Use MSR bitmaps. */
|
---|
[5605] | 373 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS RT_BIT(28)
|
---|
[1] | 374 | /* VM Exit when executing the MONITOR instruction. */
|
---|
[5605] | 375 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT RT_BIT(29)
|
---|
[1] | 376 | /* VM Exit when executing the PAUSE instruction. */
|
---|
[5605] | 377 | #define VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT RT_BIT(30)
|
---|
[1] | 378 | /** @} */
|
---|
| 379 |
|
---|
| 380 |
|
---|
| 381 | /** VMX_VMCS_CTRL_ENTRY_CONTROLS
|
---|
| 382 | * @{
|
---|
| 383 | */
|
---|
| 384 | /** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
|
---|
[5605] | 385 | #define VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE RT_BIT(9)
|
---|
[1] | 386 | /** In SMM mode after VM-entry. */
|
---|
[5605] | 387 | #define VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM RT_BIT(10)
|
---|
[1] | 388 | /** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
|
---|
[5605] | 389 | #define VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON RT_BIT(11)
|
---|
[1] | 390 | /** @} */
|
---|
| 391 |
|
---|
| 392 |
|
---|
| 393 | /** VMX_VMCS_CTRL_EXIT_CONTROLS
|
---|
| 394 | * @{
|
---|
| 395 | */
|
---|
| 396 | /** Return to long mode after a VM-exit. */
|
---|
[5605] | 397 | #define VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 RT_BIT(9)
|
---|
[1] | 398 | /** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
|
---|
[5605] | 399 | #define VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ RT_BIT(15)
|
---|
[1] | 400 | /** @} */
|
---|
| 401 |
|
---|
| 402 | /** 32 Bits read-only fields
|
---|
| 403 | * @{
|
---|
| 404 | */
|
---|
| 405 | #define VMX_VMCS_RO_VM_INSTR_ERROR 0x4400
|
---|
| 406 | #define VMX_VMCS_RO_EXIT_REASON 0x4402
|
---|
| 407 | #define VMX_VMCS_RO_EXIT_INTERRUPTION_INFO 0x4404
|
---|
| 408 | #define VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE 0x4406
|
---|
| 409 | #define VMX_VMCS_RO_IDT_INFO 0x4408
|
---|
| 410 | #define VMX_VMCS_RO_IDT_ERRCODE 0x440A
|
---|
| 411 | #define VMX_VMCS_RO_EXIT_INSTR_LENGTH 0x440C
|
---|
| 412 | #define VMX_VMCS_RO_EXIT_INSTR_INFO 0x440E
|
---|
| 413 | /** @} */
|
---|
| 414 |
|
---|
| 415 | /** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO
|
---|
| 416 | * @{
|
---|
| 417 | */
|
---|
| 418 | #define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
|
---|
| 419 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
|
---|
| 420 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) ((a >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
|
---|
[5605] | 421 | #define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11)
|
---|
[1] | 422 | #define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
|
---|
[5605] | 423 | #define VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(a) (a & RT_BIT(12))
|
---|
[1] | 424 | #define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
|
---|
[5605] | 425 | #define VMX_EXIT_INTERRUPTION_INFO_VALID(a) (a & RT_BIT(31))
|
---|
[1] | 426 | /* Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
|
---|
[5605] | 427 | #define VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) (a & ~RT_BIT(12))
|
---|
[1] | 428 | /** @} */
|
---|
| 429 |
|
---|
| 430 | /** VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
|
---|
| 431 | * @{
|
---|
| 432 | */
|
---|
| 433 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT 0
|
---|
| 434 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
|
---|
| 435 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT 3
|
---|
| 436 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW 4 /* int xx */
|
---|
| 437 | #define VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT 6
|
---|
| 438 | /** @} */
|
---|
| 439 |
|
---|
| 440 |
|
---|
| 441 | /** 32 Bits guest state fields
|
---|
| 442 | * @{
|
---|
| 443 | */
|
---|
| 444 | #define VMX_VMCS_GUEST_ES_LIMIT 0x4800
|
---|
| 445 | #define VMX_VMCS_GUEST_CS_LIMIT 0x4802
|
---|
| 446 | #define VMX_VMCS_GUEST_SS_LIMIT 0x4804
|
---|
| 447 | #define VMX_VMCS_GUEST_DS_LIMIT 0x4806
|
---|
| 448 | #define VMX_VMCS_GUEST_FS_LIMIT 0x4808
|
---|
| 449 | #define VMX_VMCS_GUEST_GS_LIMIT 0x480A
|
---|
| 450 | #define VMX_VMCS_GUEST_LDTR_LIMIT 0x480C
|
---|
| 451 | #define VMX_VMCS_GUEST_TR_LIMIT 0x480E
|
---|
| 452 | #define VMX_VMCS_GUEST_GDTR_LIMIT 0x4810
|
---|
| 453 | #define VMX_VMCS_GUEST_IDTR_LIMIT 0x4812
|
---|
| 454 | #define VMX_VMCS_GUEST_ES_ACCESS_RIGHTS 0x4814
|
---|
| 455 | #define VMX_VMCS_GUEST_CS_ACCESS_RIGHTS 0x4816
|
---|
| 456 | #define VMX_VMCS_GUEST_SS_ACCESS_RIGHTS 0x4818
|
---|
| 457 | #define VMX_VMCS_GUEST_DS_ACCESS_RIGHTS 0x481A
|
---|
| 458 | #define VMX_VMCS_GUEST_FS_ACCESS_RIGHTS 0x481C
|
---|
| 459 | #define VMX_VMCS_GUEST_GS_ACCESS_RIGHTS 0x481E
|
---|
| 460 | #define VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x4820
|
---|
| 461 | #define VMX_VMCS_GUEST_TR_ACCESS_RIGHTS 0x4822
|
---|
| 462 | #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 0x4824
|
---|
| 463 | #define VMX_VMCS_GUEST_ACTIVITY_STATE 0x4826
|
---|
| 464 | #define VMX_VMCS_GUEST_SYSENTER_CS 0x482A /* MSR IA32_SYSENTER_CS */
|
---|
| 465 | /** @} */
|
---|
| 466 |
|
---|
| 467 |
|
---|
| 468 | /** VMX_VMCS_GUEST_ACTIVITY_STATE
|
---|
| 469 | * @{
|
---|
| 470 | */
|
---|
| 471 | /* The logical processor is active. */
|
---|
| 472 | #define VMX_CMS_GUEST_ACTIVITY_ACTIVE 0x0
|
---|
| 473 | /* The logical processor is inactive, because executed a HLT instruction. */
|
---|
| 474 | #define VMX_CMS_GUEST_ACTIVITY_HLT 0x1
|
---|
| 475 | /* The logical processor is inactive, because of a triple fault or other serious error. */
|
---|
| 476 | #define VMX_CMS_GUEST_ACTIVITY_SHUTDOWN 0x2
|
---|
| 477 | /* The logical processor is inactive, because it's waiting for a startup-IPI */
|
---|
| 478 | #define VMX_CMS_GUEST_ACTIVITY_SIPI_WAIT 0x3
|
---|
| 479 | /** @} */
|
---|
| 480 |
|
---|
| 481 |
|
---|
| 482 | /** VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
|
---|
| 483 | * @{
|
---|
| 484 | */
|
---|
[5605] | 485 | #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0)
|
---|
| 486 | #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1)
|
---|
| 487 | #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2)
|
---|
| 488 | #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3)
|
---|
[1] | 489 | /** @} */
|
---|
| 490 |
|
---|
| 491 |
|
---|
| 492 | /** 32 Bits host state fields
|
---|
| 493 | * @{
|
---|
| 494 | */
|
---|
| 495 | #define VMX_VMCS_HOST_SYSENTER_CS 0x4C00
|
---|
| 496 | /** @} */
|
---|
| 497 |
|
---|
| 498 | /** Natural width control fields
|
---|
| 499 | * @{
|
---|
| 500 | */
|
---|
| 501 | #define VMX_VMCS_CTRL_CR0_MASK 0x6000
|
---|
| 502 | #define VMX_VMCS_CTRL_CR4_MASK 0x6002
|
---|
| 503 | #define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
|
---|
| 504 | #define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
|
---|
| 505 | #define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
|
---|
| 506 | #define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
|
---|
| 507 | #define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
|
---|
| 508 | #define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
|
---|
| 509 | /** @} */
|
---|
| 510 |
|
---|
| 511 |
|
---|
| 512 | /** Natural width read-only data fields
|
---|
| 513 | * @{
|
---|
| 514 | */
|
---|
| 515 | #define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
|
---|
| 516 | #define VMX_VMCS_RO_IO_RCX 0x6402
|
---|
| 517 | #define VMX_VMCS_RO_IO_RSX 0x6404
|
---|
| 518 | #define VMX_VMCS_RO_IO_RDI 0x6406
|
---|
| 519 | #define VMX_VMCS_RO_IO_RIP 0x6408
|
---|
| 520 | #define VMX_VMCS_GUEST_LINEAR_ADDR 0x640A
|
---|
| 521 | /** @} */
|
---|
| 522 |
|
---|
| 523 |
|
---|
| 524 | /** VMX_VMCS_RO_EXIT_QUALIFICATION
|
---|
| 525 | * @{
|
---|
| 526 | */
|
---|
| 527 |
|
---|
| 528 | /** DRx moves
|
---|
| 529 | * @{
|
---|
| 530 | */
|
---|
| 531 | /** 0-2: Debug register number */
|
---|
| 532 | #define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
|
---|
| 533 | /** 3: Reserved; cleared to 0. */
|
---|
| 534 | #define VMX_EXIT_QUALIFICATION_DRX_RES1(a) ((a >> 3) & 1)
|
---|
| 535 | /** 4: Direction of move (0 = write, 1 = read) */
|
---|
| 536 | #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a) ((a >> 4) & 1)
|
---|
| 537 | /** 5-7: Reserved; cleared to 0. */
|
---|
| 538 | #define VMX_EXIT_QUALIFICATION_DRX_RES2(a) ((a >> 5) & 7)
|
---|
| 539 | /** 8-11: General purpose register number. */
|
---|
| 540 | #define VMX_EXIT_QUALIFICATION_DRX_GENREG(a) ((a >> 8) & 0xF)
|
---|
| 541 | /** Rest: reserved. */
|
---|
| 542 |
|
---|
| 543 | /** VMX_EXIT_QUALIFICATION_DRX_DIRECTION
|
---|
| 544 | * @{
|
---|
| 545 | */
|
---|
| 546 | #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE 0
|
---|
| 547 | #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ 1
|
---|
| 548 | /** @} */
|
---|
| 549 |
|
---|
| 550 | /** @} */
|
---|
| 551 |
|
---|
| 552 |
|
---|
| 553 | /** CRx accesses
|
---|
| 554 | * @{
|
---|
| 555 | */
|
---|
| 556 | /** 0-3: Control register number (0 for CLTS & LMSW) */
|
---|
| 557 | #define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
|
---|
| 558 | /** 4-5: Access type. */
|
---|
| 559 | #define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a) ((a >> 4) & 3)
|
---|
| 560 | /** 6: LMSW operand type */
|
---|
| 561 | #define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a) ((a >> 6) & 1)
|
---|
| 562 | /** 7: Reserved; cleared to 0. */
|
---|
| 563 | #define VMX_EXIT_QUALIFICATION_CRX_RES1(a) ((a >> 7) & 1)
|
---|
| 564 | /** 8-11: General purpose register number (0 for CLTS & LMSW). */
|
---|
| 565 | #define VMX_EXIT_QUALIFICATION_CRX_GENREG(a) ((a >> 8) & 0xF)
|
---|
| 566 | /** 12-15: Reserved; cleared to 0. */
|
---|
| 567 | #define VMX_EXIT_QUALIFICATION_CRX_RES2(a) ((a >> 12) & 0xF)
|
---|
| 568 | /** 16-31: LMSW source data (else 0). */
|
---|
| 569 | #define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a) ((a >> 16) & 0xFFFF)
|
---|
| 570 | /** Rest: reserved. */
|
---|
| 571 |
|
---|
| 572 |
|
---|
| 573 | /** VMX_EXIT_QUALIFICATION_CRX_ACCESS
|
---|
| 574 | * @{
|
---|
| 575 | */
|
---|
| 576 | #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
|
---|
| 577 | #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
|
---|
| 578 | #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
|
---|
| 579 | #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
|
---|
| 580 | /** @} */
|
---|
| 581 |
|
---|
| 582 | /** @} */
|
---|
| 583 |
|
---|
| 584 |
|
---|
| 585 | /** VMX_EXIT_PORT_IO
|
---|
| 586 | * @{
|
---|
| 587 | */
|
---|
| 588 | /** 0-2: IO operation width. */
|
---|
| 589 | #define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
|
---|
| 590 | /** 3: IO operation direction. */
|
---|
| 591 | #define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a) ((a >> 3) & 1)
|
---|
| 592 | /** 4: String IO operation. */
|
---|
| 593 | #define VMX_EXIT_QUALIFICATION_IO_STRING(a) ((a >> 4) & 1)
|
---|
| 594 | /** 5: Repeated IO operation. */
|
---|
| 595 | #define VMX_EXIT_QUALIFICATION_IO_REP(a) ((a >> 5) & 1)
|
---|
| 596 | /** 6: Operand encoding. */
|
---|
| 597 | #define VMX_EXIT_QUALIFICATION_IO_ENCODING(a) ((a >> 6) & 1)
|
---|
| 598 | /** 16-31: IO Port (0-0xffff). */
|
---|
| 599 | #define VMX_EXIT_QUALIFICATION_IO_PORT(a) ((a >> 16) & 0xffff)
|
---|
| 600 | /* Rest reserved. */
|
---|
| 601 | /** @} */
|
---|
| 602 |
|
---|
| 603 | /** VMX_EXIT_QUALIFICATION_IO_DIRECTION
|
---|
| 604 | * @{
|
---|
| 605 | */
|
---|
| 606 | #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
|
---|
| 607 | #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
|
---|
| 608 | /** @} */
|
---|
| 609 |
|
---|
| 610 |
|
---|
| 611 | /** VMX_EXIT_QUALIFICATION_IO_ENCODING
|
---|
| 612 | * @{
|
---|
| 613 | */
|
---|
| 614 | #define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
|
---|
| 615 | #define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
|
---|
| 616 | /** @} */
|
---|
| 617 |
|
---|
| 618 | /** @} */
|
---|
| 619 |
|
---|
| 620 | /** Natural width guest state fields
|
---|
| 621 | * @{
|
---|
| 622 | */
|
---|
| 623 | #define VMX_VMCS_GUEST_CR0 0x6800
|
---|
| 624 | #define VMX_VMCS_GUEST_CR3 0x6802
|
---|
| 625 | #define VMX_VMCS_GUEST_CR4 0x6804
|
---|
| 626 | #define VMX_VMCS_GUEST_ES_BASE 0x6806
|
---|
| 627 | #define VMX_VMCS_GUEST_CS_BASE 0x6808
|
---|
| 628 | #define VMX_VMCS_GUEST_SS_BASE 0x680A
|
---|
| 629 | #define VMX_VMCS_GUEST_DS_BASE 0x680C
|
---|
| 630 | #define VMX_VMCS_GUEST_FS_BASE 0x680E
|
---|
| 631 | #define VMX_VMCS_GUEST_GS_BASE 0x6810
|
---|
| 632 | #define VMX_VMCS_GUEST_LDTR_BASE 0x6812
|
---|
| 633 | #define VMX_VMCS_GUEST_TR_BASE 0x6814
|
---|
| 634 | #define VMX_VMCS_GUEST_GDTR_BASE 0x6816
|
---|
| 635 | #define VMX_VMCS_GUEST_IDTR_BASE 0x6818
|
---|
| 636 | #define VMX_VMCS_GUEST_DR7 0x681A
|
---|
| 637 | #define VMX_VMCS_GUEST_RSP 0x681C
|
---|
| 638 | #define VMX_VMCS_GUEST_RIP 0x681E
|
---|
| 639 | #define VMX_VMCS_GUEST_RFLAGS 0x6820
|
---|
| 640 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 0x6822
|
---|
| 641 | #define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /* MSR IA32_SYSENTER_ESP */
|
---|
| 642 | #define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /* MSR IA32_SYSENTER_EIP */
|
---|
| 643 | /** @} */
|
---|
| 644 |
|
---|
| 645 |
|
---|
| 646 | /** VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
|
---|
| 647 | * @{
|
---|
| 648 | */
|
---|
| 649 | /* Hardware breakpoint 0 was met. */
|
---|
[5605] | 650 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
|
---|
[1] | 651 | /* Hardware breakpoint 1 was met. */
|
---|
[5605] | 652 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B1 RT_BIT(1)
|
---|
[1] | 653 | /* Hardware breakpoint 2 was met. */
|
---|
[5605] | 654 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B2 RT_BIT(2)
|
---|
[1] | 655 | /* Hardware breakpoint 3 was met. */
|
---|
[5605] | 656 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B3 RT_BIT(3)
|
---|
[1] | 657 | /* At least one data or IO breakpoint was hit. */
|
---|
[5605] | 658 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BREAKPOINT_ENABLED RT_BIT(12)
|
---|
[1] | 659 | /* A debug exception would have been triggered by single-step execution mode. */
|
---|
[5605] | 660 | #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14)
|
---|
[1] | 661 | /* Bits 4-11, 13 and 15-63 are reserved. */
|
---|
| 662 |
|
---|
| 663 |
|
---|
| 664 |
|
---|
| 665 |
|
---|
| 666 | /** @} */
|
---|
| 667 |
|
---|
| 668 | /** Natural width host state fields
|
---|
| 669 | * @{
|
---|
| 670 | */
|
---|
| 671 | #define VMX_VMCS_HOST_CR0 0x6C00
|
---|
| 672 | #define VMX_VMCS_HOST_CR3 0x6C02
|
---|
| 673 | #define VMX_VMCS_HOST_CR4 0x6C04
|
---|
| 674 | #define VMX_VMCS_HOST_FS_BASE 0x6C06
|
---|
| 675 | #define VMX_VMCS_HOST_GS_BASE 0x6C08
|
---|
| 676 | #define VMX_VMCS_HOST_TR_BASE 0x6C0A
|
---|
| 677 | #define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
|
---|
| 678 | #define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
|
---|
| 679 | #define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
|
---|
| 680 | #define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
|
---|
| 681 | #define VMX_VMCS_HOST_RSP 0x6C14
|
---|
| 682 | #define VMX_VMCS_HOST_RIP 0x6C16
|
---|
| 683 | /** @} */
|
---|
| 684 |
|
---|
| 685 | /** @} */
|
---|
| 686 |
|
---|
| 687 |
|
---|
| 688 | #if RT_INLINE_ASM_GNU_STYLE
|
---|
| 689 | # define __STR(x) #x
|
---|
| 690 | # define STR(x) __STR(x)
|
---|
| 691 | #endif
|
---|
| 692 |
|
---|
| 693 |
|
---|
| 694 | /** @} */
|
---|
| 695 |
|
---|
| 696 | /** @defgroup grp_vmx_asm vmx assembly helpers
|
---|
| 697 | * @ingroup grp_vmx
|
---|
| 698 | * @{
|
---|
| 699 | */
|
---|
| 700 |
|
---|
| 701 | /**
|
---|
| 702 | * Executes VMXON
|
---|
| 703 | *
|
---|
| 704 | * @returns VBox status code
|
---|
| 705 | * @param pVMXOn Physical address of VMXON structure
|
---|
| 706 | */
|
---|
[73] | 707 | #if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
|
---|
[1] | 708 | DECLASM(int) VMXEnable(RTHCPHYS pVMXOn);
|
---|
| 709 | #else
|
---|
| 710 | DECLINLINE(int) VMXEnable(RTHCPHYS pVMXOn)
|
---|
| 711 | {
|
---|
| 712 | int rc = VINF_SUCCESS;
|
---|
| 713 | # if RT_INLINE_ASM_GNU_STYLE
|
---|
| 714 | __asm__ __volatile__ (
|
---|
| 715 | "push %3 \n\t"
|
---|
| 716 | "push %2 \n\t"
|
---|
| 717 | ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
|
---|
| 718 | "ja 2f \n\t"
|
---|
| 719 | "je 1f \n\t"
|
---|
| 720 | "movl $"STR(VERR_VMX_INVALID_VMXON_PTR)", %0 \n\t"
|
---|
| 721 | "jmp 2f \n\t"
|
---|
| 722 | "1: \n\t"
|
---|
| 723 | "movl $"STR(VERR_VMX_GENERIC)", %0 \n\t"
|
---|
| 724 | "2: \n\t"
|
---|
| 725 | "add $8, %%esp \n\t"
|
---|
| 726 | :"=rm"(rc)
|
---|
| 727 | :"0"(VINF_SUCCESS),
|
---|
| 728 | "ir"((uint32_t)pVMXOn), /* don't allow direct memory reference here, */
|
---|
| 729 | "ir"((uint32_t)(pVMXOn >> 32)) /* this would not work with -fomit-frame-pointer */
|
---|
[3362] | 730 | :"memory"
|
---|
[1] | 731 | );
|
---|
| 732 | # else
|
---|
| 733 | __asm
|
---|
| 734 | {
|
---|
| 735 | push dword ptr [pVMXOn+4]
|
---|
| 736 | push dword ptr [pVMXOn]
|
---|
| 737 | _emit 0xF3
|
---|
| 738 | _emit 0x0F
|
---|
| 739 | _emit 0xC7
|
---|
| 740 | _emit 0x34
|
---|
| 741 | _emit 0x24 /* VMXON [esp] */
|
---|
| 742 | jnc vmxon_good
|
---|
| 743 | mov dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
|
---|
| 744 | jmp the_end
|
---|
| 745 |
|
---|
| 746 | vmxon_good:
|
---|
| 747 | jnz the_end
|
---|
| 748 | mov dword ptr [rc], VERR_VMX_GENERIC
|
---|
| 749 | the_end:
|
---|
| 750 | add esp, 8
|
---|
| 751 | }
|
---|
| 752 | # endif
|
---|
| 753 | return rc;
|
---|
| 754 | }
|
---|
| 755 | #endif
|
---|
| 756 |
|
---|
| 757 |
|
---|
| 758 | /**
|
---|
| 759 | * Executes VMXOFF
|
---|
| 760 | */
|
---|
[73] | 761 | #if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
|
---|
[1] | 762 | DECLASM(void) VMXDisable(void);
|
---|
| 763 | #else
|
---|
| 764 | DECLINLINE(void) VMXDisable(void)
|
---|
| 765 | {
|
---|
| 766 | # if RT_INLINE_ASM_GNU_STYLE
|
---|
| 767 | __asm__ __volatile__ (
|
---|
| 768 | ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
|
---|
| 769 | );
|
---|
| 770 | # else
|
---|
| 771 | __asm
|
---|
| 772 | {
|
---|
| 773 | _emit 0x0F
|
---|
| 774 | _emit 0x01
|
---|
| 775 | _emit 0xC4 /* VMXOFF */
|
---|
| 776 | }
|
---|
| 777 | # endif
|
---|
| 778 | }
|
---|
| 779 | #endif
|
---|
| 780 |
|
---|
| 781 |
|
---|
| 782 | /**
|
---|
| 783 | * Executes VMCLEAR
|
---|
| 784 | *
|
---|
| 785 | * @returns VBox status code
|
---|
| 786 | * @param pVMCS Physical address of VM control structure
|
---|
| 787 | */
|
---|
[73] | 788 | #if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
|
---|
[1] | 789 | DECLASM(int) VMXClearVMCS(RTHCPHYS pVMCS);
|
---|
| 790 | #else
|
---|
| 791 | DECLINLINE(int) VMXClearVMCS(RTHCPHYS pVMCS)
|
---|
| 792 | {
|
---|
| 793 | int rc = VINF_SUCCESS;
|
---|
| 794 | # if RT_INLINE_ASM_GNU_STYLE
|
---|
| 795 | __asm__ __volatile__ (
|
---|
| 796 | "push %3 \n\t"
|
---|
| 797 | "push %2 \n\t"
|
---|
| 798 | ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
|
---|
| 799 | "jnc 1f \n\t"
|
---|
| 800 | "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
|
---|
| 801 | "1: \n\t"
|
---|
| 802 | "add $8, %%esp \n\t"
|
---|
| 803 | :"=rm"(rc)
|
---|
| 804 | :"0"(VINF_SUCCESS),
|
---|
| 805 | "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
|
---|
| 806 | "ir"((uint32_t)(pVMCS >> 32)) /* this would not work with -fomit-frame-pointer */
|
---|
[3362] | 807 | :"memory"
|
---|
[1] | 808 | );
|
---|
| 809 | # else
|
---|
| 810 | __asm
|
---|
| 811 | {
|
---|
| 812 | push dword ptr [pVMCS+4]
|
---|
| 813 | push dword ptr [pVMCS]
|
---|
| 814 | _emit 0x66
|
---|
| 815 | _emit 0x0F
|
---|
| 816 | _emit 0xC7
|
---|
| 817 | _emit 0x34
|
---|
| 818 | _emit 0x24 /* VMCLEAR [esp] */
|
---|
| 819 | jnc success
|
---|
| 820 | mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
|
---|
| 821 | success:
|
---|
| 822 | add esp, 8
|
---|
| 823 | }
|
---|
| 824 | # endif
|
---|
| 825 | return rc;
|
---|
| 826 | }
|
---|
| 827 | #endif
|
---|
| 828 |
|
---|
| 829 |
|
---|
| 830 | /**
|
---|
| 831 | * Executes VMPTRLD
|
---|
| 832 | *
|
---|
| 833 | * @returns VBox status code
|
---|
| 834 | * @param pVMCS Physical address of VMCS structure
|
---|
| 835 | */
|
---|
[73] | 836 | #if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
|
---|
[1] | 837 | DECLASM(int) VMXActivateVMCS(RTHCPHYS pVMCS);
|
---|
| 838 | #else
|
---|
| 839 | DECLINLINE(int) VMXActivateVMCS(RTHCPHYS pVMCS)
|
---|
| 840 | {
|
---|
| 841 | int rc = VINF_SUCCESS;
|
---|
| 842 | # if RT_INLINE_ASM_GNU_STYLE
|
---|
| 843 | __asm__ __volatile__ (
|
---|
| 844 | "push %3 \n\t"
|
---|
| 845 | "push %2 \n\t"
|
---|
| 846 | ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
|
---|
| 847 | "jnc 1f \n\t"
|
---|
| 848 | "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
|
---|
| 849 | "1: \n\t"
|
---|
| 850 | "add $8, %%esp \n\t"
|
---|
| 851 | :"=rm"(rc)
|
---|
| 852 | :"0"(VINF_SUCCESS),
|
---|
| 853 | "ir"((uint32_t)pVMCS), /* don't allow direct memory reference here, */
|
---|
| 854 | "ir"((uint32_t)(pVMCS >> 32)) /* this will not work with -fomit-frame-pointer */
|
---|
| 855 | );
|
---|
| 856 | # else
|
---|
| 857 | __asm
|
---|
| 858 | {
|
---|
| 859 | push dword ptr [pVMCS+4]
|
---|
| 860 | push dword ptr [pVMCS]
|
---|
| 861 | _emit 0x0F
|
---|
| 862 | _emit 0xC7
|
---|
| 863 | _emit 0x34
|
---|
| 864 | _emit 0x24 /* VMPTRLD [esp] */
|
---|
| 865 | jnc success
|
---|
| 866 | mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
|
---|
| 867 |
|
---|
| 868 | success:
|
---|
| 869 | add esp, 8
|
---|
| 870 | }
|
---|
| 871 | # endif
|
---|
| 872 | return rc;
|
---|
| 873 | }
|
---|
| 874 | #endif
|
---|
| 875 |
|
---|
| 876 |
|
---|
| 877 | /**
|
---|
| 878 | * Executes VMWRITE
|
---|
| 879 | *
|
---|
| 880 | * @returns VBox status code
|
---|
| 881 | * @param idxField VMCS index
|
---|
| 882 | * @param u64Val 16, 32 or 64 bits value
|
---|
| 883 | */
|
---|
[2737] | 884 | DECLASM(int) VMXWriteVMCS64(uint32_t idxField, uint64_t u64Val);
|
---|
[1] | 885 |
|
---|
| 886 | /**
|
---|
| 887 | * Executes VMWRITE
|
---|
| 888 | *
|
---|
| 889 | * @returns VBox status code
|
---|
| 890 | * @param idxField VMCS index
|
---|
| 891 | * @param u32Val 32 bits value
|
---|
| 892 | */
|
---|
[73] | 893 | #if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
|
---|
[1] | 894 | DECLASM(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val);
|
---|
| 895 | #else
|
---|
| 896 | DECLINLINE(int) VMXWriteVMCS32(uint32_t idxField, uint32_t u32Val)
|
---|
| 897 | {
|
---|
| 898 | int rc = VINF_SUCCESS;
|
---|
| 899 | # if RT_INLINE_ASM_GNU_STYLE
|
---|
| 900 | __asm__ __volatile__ (
|
---|
| 901 | ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
|
---|
| 902 | "ja 2f \n\t"
|
---|
| 903 | "je 1f \n\t"
|
---|
| 904 | "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
|
---|
| 905 | "jmp 2f \n\t"
|
---|
| 906 | "1: \n\t"
|
---|
| 907 | "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
|
---|
| 908 | "2: \n\t"
|
---|
| 909 | :"=rm"(rc)
|
---|
| 910 | :"0"(VINF_SUCCESS),
|
---|
| 911 | "a"(idxField),
|
---|
| 912 | "d"(u32Val)
|
---|
| 913 | );
|
---|
| 914 | # else
|
---|
| 915 | __asm
|
---|
| 916 | {
|
---|
| 917 | push dword ptr [u32Val]
|
---|
| 918 | mov eax, [idxField]
|
---|
| 919 | _emit 0x0F
|
---|
| 920 | _emit 0x79
|
---|
| 921 | _emit 0x04
|
---|
| 922 | _emit 0x24 /* VMWRITE eax, [esp] */
|
---|
| 923 | jnc valid_vmcs
|
---|
| 924 | mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
|
---|
| 925 | jmp the_end
|
---|
| 926 |
|
---|
| 927 | valid_vmcs:
|
---|
| 928 | jnz the_end
|
---|
| 929 | mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
|
---|
| 930 | the_end:
|
---|
| 931 | add esp, 4
|
---|
| 932 | }
|
---|
| 933 | # endif
|
---|
| 934 | return rc;
|
---|
| 935 | }
|
---|
| 936 | #endif
|
---|
| 937 |
|
---|
| 938 | #if HC_ARCH_BITS == 64
|
---|
| 939 | #define VMXWriteVMCS VMXWriteVMCS64
|
---|
| 940 | #else
|
---|
| 941 | #define VMXWriteVMCS VMXWriteVMCS32
|
---|
| 942 | #endif /* HC_ARCH_BITS == 64 */
|
---|
| 943 |
|
---|
| 944 |
|
---|
| 945 | /**
|
---|
| 946 | * Executes VMREAD
|
---|
| 947 | *
|
---|
| 948 | * @returns VBox status code
|
---|
| 949 | * @param idxField VMCS index
|
---|
| 950 | * @param pData Ptr to store VM field value
|
---|
| 951 | */
|
---|
[2737] | 952 | DECLASM(int) VMXReadVMCS64(uint32_t idxField, uint64_t *pData);
|
---|
[1] | 953 |
|
---|
| 954 | /**
|
---|
| 955 | * Executes VMREAD
|
---|
| 956 | *
|
---|
| 957 | * @returns VBox status code
|
---|
| 958 | * @param idxField VMCS index
|
---|
| 959 | * @param pData Ptr to store VM field value
|
---|
| 960 | */
|
---|
[73] | 961 | #if RT_INLINE_ASM_EXTERNAL || HC_ARCH_BITS == 64
|
---|
[1] | 962 | DECLASM(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData);
|
---|
| 963 | #else
|
---|
| 964 | DECLINLINE(int) VMXReadVMCS32(uint32_t idxField, uint32_t *pData)
|
---|
| 965 | {
|
---|
| 966 | int rc = VINF_SUCCESS;
|
---|
| 967 | # if RT_INLINE_ASM_GNU_STYLE
|
---|
| 968 | __asm__ __volatile__ (
|
---|
| 969 | "movl $"STR(VINF_SUCCESS)", %0 \n\t"
|
---|
| 970 | ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
|
---|
| 971 | "ja 2f \n\t"
|
---|
| 972 | "je 1f \n\t"
|
---|
| 973 | "movl $"STR(VERR_VMX_INVALID_VMCS_PTR)", %0 \n\t"
|
---|
| 974 | "jmp 2f \n\t"
|
---|
| 975 | "1: \n\t"
|
---|
| 976 | "movl $"STR(VERR_VMX_INVALID_VMCS_FIELD)", %0 \n\t"
|
---|
| 977 | "2: \n\t"
|
---|
| 978 | :"=&r"(rc),
|
---|
| 979 | "=d"(*pData)
|
---|
| 980 | :"a"(idxField),
|
---|
| 981 | "d"(0)
|
---|
| 982 | );
|
---|
| 983 | # else
|
---|
| 984 | __asm
|
---|
| 985 | {
|
---|
| 986 | sub esp, 4
|
---|
| 987 | mov dword ptr [esp], 0
|
---|
| 988 | mov eax, [idxField]
|
---|
| 989 | _emit 0x0F
|
---|
| 990 | _emit 0x78
|
---|
| 991 | _emit 0x04
|
---|
| 992 | _emit 0x24 /* VMREAD eax, [esp] */
|
---|
| 993 | mov edx, pData
|
---|
| 994 | pop dword ptr [edx]
|
---|
| 995 | jnc valid_vmcs
|
---|
| 996 | mov dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
|
---|
| 997 | jmp the_end
|
---|
| 998 |
|
---|
| 999 | valid_vmcs:
|
---|
| 1000 | jnz the_end
|
---|
| 1001 | mov dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
|
---|
| 1002 | the_end:
|
---|
| 1003 | }
|
---|
| 1004 | # endif
|
---|
| 1005 | return rc;
|
---|
| 1006 | }
|
---|
| 1007 | #endif
|
---|
| 1008 |
|
---|
| 1009 | #if HC_ARCH_BITS == 64
|
---|
| 1010 | #define VMXReadVMCS VMXReadVMCS64
|
---|
| 1011 | #else
|
---|
| 1012 | #define VMXReadVMCS VMXReadVMCS32
|
---|
| 1013 | #endif /* HC_ARCH_BITS == 64 */
|
---|
| 1014 |
|
---|
| 1015 | /**
|
---|
| 1016 | * Prepares for and executes VMLAUNCH
|
---|
| 1017 | *
|
---|
| 1018 | * @returns VBox status code
|
---|
| 1019 | * @param pCtx Guest context
|
---|
| 1020 | */
|
---|
| 1021 | DECLASM(int) VMXStartVM(PCPUMCTX pCtx);
|
---|
| 1022 |
|
---|
| 1023 | /**
|
---|
| 1024 | * Prepares for and executes VMRESUME
|
---|
| 1025 | *
|
---|
| 1026 | * @returns VBox status code
|
---|
| 1027 | * @param pCtx Guest context
|
---|
| 1028 | */
|
---|
| 1029 | DECLASM(int) VMXResumeVM(PCPUMCTX pCtx);
|
---|
| 1030 |
|
---|
| 1031 | /**
|
---|
| 1032 | * Gets the last instruction error value from the current VMCS
|
---|
| 1033 | *
|
---|
| 1034 | * @returns error value
|
---|
| 1035 | */
|
---|
[73] | 1036 | DECLINLINE(uint32_t) VMXGetLastError(void)
|
---|
[1] | 1037 | {
|
---|
[73] | 1038 | #if HC_ARCH_BITS == 64
|
---|
| 1039 | uint64_t uLastError = 0;
|
---|
| 1040 | int rc = VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &uLastError);
|
---|
| 1041 | AssertRC(rc);
|
---|
| 1042 | return (uint32_t)uLastError;
|
---|
| 1043 |
|
---|
| 1044 | #else /* 32-bit host: */
|
---|
[1] | 1045 | uint32_t lasterr = 0;
|
---|
| 1046 | int rc;
|
---|
| 1047 |
|
---|
| 1048 | rc = VMXReadVMCS32(VMX_VMCS_RO_VM_INSTR_ERROR, &lasterr);
|
---|
| 1049 | AssertRC(rc);
|
---|
| 1050 | return lasterr;
|
---|
[73] | 1051 | #endif
|
---|
[1] | 1052 | }
|
---|
| 1053 |
|
---|
| 1054 | /** @} */
|
---|
| 1055 |
|
---|
| 1056 | #endif
|
---|
| 1057 |
|
---|