VirtualBox

source: vbox/trunk/include/VBox/gic.h@ 103224

Last change on this file since 103224 was 100100, checked in by vboxsync, 16 months ago

VMM/GIC: Fixes and updates to the implementation in order to support SMP, requires the sledgehammer approach wrt locking right now which needs to be me more fine grained, bugref:10404 bugref:10454

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File size: 28.9 KB
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1/** @file
2 * ARMv8 Generic Interrupt Controller Architecture v3 (GICv3) definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_gic_h
37#define VBOX_INCLUDED_gic_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <iprt/types.h>
43#include <iprt/armv8.h>
44
45/** @name INTIDs - Interrupt identifier ranges.
46 * @{ */
47/** Start of the SGI (Software Generated Interrupts) range. */
48#define GIC_INTID_RANGE_SGI_START 0
49/** Last valid SGI (Software Generated Interrupts) identifier. */
50#define GIC_INTID_RANGE_SGI_LAST 15
51
52/** Start of the PPI (Private Peripheral Interrupts) range. */
53#define GIC_INTID_RANGE_PPI_START 16
54/** Last valid PPI (Private Peripheral Interrupts) identifier. */
55#define GIC_INTID_RANGE_PPI_LAST 31
56
57/** Start of the SPI (Shared Peripheral Interrupts) range. */
58#define GIC_INTID_RANGE_SPI_START 32
59/** Last valid SPI (Shared Peripheral Interrupts) identifier. */
60#define GIC_INTID_RANGE_SPI_LAST 1019
61
62/** Start of the special interrupt range. */
63#define GIC_INTID_RANGE_SPECIAL_START 1020
64/** Last valid special interrupt identifier. */
65#define GIC_INTID_RANGE_SPECIAL_LAST 1023
66/** Value for an interrupt acknowledge if no pending interrupt with sufficient
67 * priority, security state or interrupt group. */
68# define GIC_INTID_RANGE_SPECIAL_NO_INTERRUPT 1023
69
70/** Start of the extended PPI (Private Peripheral Interrupts) range. */
71#define GIC_INTID_RANGE_EPPI_START 1056
72/** Last valid extended PPI (Private Peripheral Interrupts) identifier. */
73#define GIC_INTID_RANGE_EPPI_LAST 1119
74
75/** Start of the extended SPI (Shared Peripheral Interrupts) range. */
76#define GIC_INTID_RANGE_ESPI_START 4096
77/** Last valid extended SPI (Shared Peripheral Interrupts) identifier. */
78#define GIC_INTID_RANGE_ESPI_LAST 5119
79
80/** Start of the LPI (Locality-specific Peripheral Interrupts) range. */
81#define GIC_INTID_RANGE_LPI_START 8192
82/** @} */
83
84
85/** @name GICD - GIC Distributor registers.
86 * @{ */
87/** Size of the distributor register frame. */
88#define GIC_DIST_REG_FRAME_SIZE _64K
89
90/** Distributor Control Register - RW. */
91#define GIC_DIST_REG_CTLR_OFF 0x0000
92/** Bit 0 - Enable Group 0 interrupts. */
93# define GIC_DIST_REG_CTRL_ENABLE_GRP0 RT_BIT_32(0)
94# define GIC_DIST_REG_CTRL_ENABLE_GRP0_BIT 0
95/** Bit 1 - Enable Non-secure Group 1 interrupts. */
96# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS RT_BIT_32(1)
97# define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS_BIT 1
98/** Bit 2 - Enable Secure Group 1 interrupts. */
99# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S RT_BIT_32(2)
100# define GIC_DIST_REG_CTRL_ENABLE_GRP1_S_BIT 2
101/** Bit 4 - Affinity Routing Enable, Secure state. */
102# define GIC_DIST_REG_CTRL_ARE_S RT_BIT_32(4)
103# define GIC_DIST_REG_CTRL_ARE_S_BIT 4
104/** Bit 5 - Affinity Routing Enable, Non-secure state. */
105# define GIC_DIST_REG_CTRL_ARE_NS RT_BIT_32(5)
106# define GIC_DIST_REG_CTRL_ARE_NS_BIT 5
107/** Bit 6 - Disable Security. */
108# define GIC_DIST_REG_CTRL_DS RT_BIT_32(6)
109# define GIC_DIST_REG_CTRL_DS_BIT 6
110/** Bit 7 - Enable 1 of N Wakeup Functionality. */
111# define GIC_DIST_REG_CTRL_E1NWF RT_BIT_32(7)
112# define GIC_DIST_REG_CTRL_E1NWF_BIT 7
113/** Bit 31 - Register Write Pending. */
114# define GIC_DIST_REG_CTRL_RWP RT_BIT_32(31)
115# define GIC_DIST_REG_CTRL_RWP_BIT 31
116
117/** Interrupt Controller Type Register - RO. */
118#define GIC_DIST_REG_TYPER_OFF 0x0004
119/** Bit 0 - 4 - Maximum number of SPIs supported. */
120# define GIC_DIST_REG_TYPER_NUM_ITLINES ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT(2) \
121 | RT_BIT_32(3) | RT_BIT_32(4))
122# define GIC_DIST_REG_TYPER_NUM_ITLINES_SET(a_NumSpis) ((a_NumSpis) & GIC_DIST_REG_TYPER_NUM_ITLINES)
123/** Bit 5 - 7 - Reports number of PEs that can be used when affinity routing is not enabled, minus 1. */
124# define GIC_DIST_REG_TYPER_NUM_PES (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT(7))
125# define GIC_DIST_REG_TYPER_NUM_PES_SET(a_Pes) (((a_Pes) << 5) & GIC_DIST_REG_TYPER_NUM_PES)
126/** Bit 8 - Extended SPI range implemented. */
127# define GIC_DIST_REG_TYPER_ESPI RT_BIT_32(8)
128# define GIC_DIST_REG_TYPER_ESPI_BIT 8
129/** Bit 9 - Non-maskable interrupt priority supported. */
130# define GIC_DIST_REG_TYPER_NMI RT_BIT_32(9)
131# define GIC_DIST_REG_TYPER_NMI_BIT 9
132/** Bit 10 - Indicates whether the implementation supports two security states. */
133# define GIC_DIST_REG_TYPER_SECURITY_EXTN RT_BIT_32(10)
134# define GIC_DIST_REG_TYPER_SECURITY_EXTN_BIT 10
135/** Bit 11 - 15 - The number of supported LPIs. */
136# define GIC_DIST_REG_TYPER_NUM_LPIS ( RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT(13) \
137 | RT_BIT_32(14) | RT_BIT_32(15))
138# define GIC_DIST_REG_TYPER_NUM_LPIS_SET(a_Lpis) (((a_Lpis) << 11) & GIC_DIST_REG_TYPER_NUM_LPIS)
139/** Bit 16 - Indicates whether the implementation supports message based interrupts by writing to Distributor registers. */
140# define GIC_DIST_REG_TYPER_MBIS RT_BIT_32(16)
141# define GIC_DIST_REG_TYPER_MBIS_BIT 16
142/** Bit 17 - Indicates whether the implementation supports LPIs. */
143# define GIC_DIST_REG_TYPER_LPIS RT_BIT_32(17)
144# define GIC_DIST_REG_TYPER_LPIS_BIT 17
145/** Bit 18 - Indicates whether the implementation supports Direct Virtual LPI injection (FEAT_GICv4). */
146# define GIC_DIST_REG_TYPER_DVIS RT_BIT_32(18)
147# define GIC_DIST_REG_TYPER_DVIS_BIT 18
148/** Bit 19 - 23 - The number of interrupt identifer bits supported, minus one. */
149# define GIC_DIST_REG_TYPER_IDBITS ( RT_BIT_32(19) | RT_BIT_32(20) | RT_BIT(21) \
150 | RT_BIT_32(22) | RT_BIT_32(23))
151# define GIC_DIST_REG_TYPER_IDBITS_SET(a_Bits) (((a_Bits) << 19) & GIC_DIST_REG_TYPER_IDBITS)
152/** Bit 24 - Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3. */
153# define GIC_DIST_REG_TYPER_A3V RT_BIT_32(24)
154# define GIC_DIST_REG_TYPER_A3V_BIT 24
155/** Bit 25 - Indicates whether 1 of N SPI interrupts are supported. */
156# define GIC_DIST_REG_TYPER_NO1N RT_BIT_32(25)
157# define GIC_DIST_REG_TYPER_NO1N_BIT 25
158/** Bit 26 - Range Selector Support. */
159# define GIC_DIST_REG_TYPER_RSS RT_BIT_32(26)
160# define GIC_DIST_REG_TYPER_RSS_BIT 26
161/** Bit 27 - 31 - Indicates maximum INTID in the Extended SPI range. */
162# define GIC_DIST_REG_TYPER_ESPI_RANGE ( RT_BIT_32(27) | RT_BIT_32(28) | RT_BIT(29) \
163 | RT_BIT_32(30) | RT_BIT_32(31))
164# define GIC_DIST_REG_TYPER_ESPI_RANGE_SET(a_Range) (((a_Range) << 27) & GIC_DIST_REG_TYPER_ESPI_RANGE)
165
166/** Distributor Implementer Identification Register - RO. */
167#define GIC_DIST_REG_IIDR_OFF 0x0008
168/** Interrupt Controller Type Register 2 - RO. */
169#define GIC_DIST_REG_TYPER2_OFF 0x000c
170/** Error Reporting Status Register (optional) - RW. */
171#define GIC_DIST_REG_STATUSR_OFF 0x0010
172/** Set SPI Register - WO. */
173#define GIC_DIST_REG_SETSPI_NSR_OFF 0x0040
174/** Clear SPI Register - WO. */
175#define GIC_DIST_REG_CLRSPI_NSR_OFF 0x0048
176/** Set SPI, Secure Register - WO. */
177#define GIC_DIST_REG_SETSPI_SR_OFF 0x0050
178/** Clear SPI, Secure Register - WO. */
179#define GIC_DIST_REG_CLRSPI_SR_OFF 0x0058
180
181/** Interrupt Group Registers, start offset - RW. */
182#define GIC_DIST_REG_IGROUPRn_OFF_START 0x0080
183/** Interrupt Group Registers, last offset - RW. */
184#define GIC_DIST_REG_IGROUPRn_OFF_LAST 0x00fc
185
186/** Interrupt Set Enable Registers, start offset - RW. */
187#define GIC_DIST_REG_ISENABLERn_OFF_START 0x0100
188/** Interrupt Set Enable Registers, last offset - RW. */
189#define GIC_DIST_REG_ISENABLERn_OFF_LAST 0x017c
190/** Interrupt Clear Enable Registers, start offset - RW. */
191#define GIC_DIST_REG_ICENABLERn_OFF_START 0x0180
192/** Interrupt Clear Enable Registers, last offset - RW. */
193#define GIC_DIST_REG_ICENABLERn_OFF_LAST 0x01fc
194
195/** Interrupt Set Pending Registers, start offset - RW. */
196#define GIC_DIST_REG_ISPENDRn_OFF_START 0x0200
197/** Interrupt Set Pending Registers, last offset - RW. */
198#define GIC_DIST_REG_ISPENDRn_OFF_LAST 0x027c
199/** Interrupt Clear Pending Registers, start offset - RW. */
200#define GIC_DIST_REG_ICPENDRn_OFF_START 0x0280
201/** Interrupt Clear Pending Registers, last offset - RW. */
202#define GIC_DIST_REG_ICPENDRn_OFF_LAST 0x02fc
203
204/** Interrupt Set Active Registers, start offset - RW. */
205#define GIC_DIST_REG_ISACTIVERn_OFF_START 0x0300
206/** Interrupt Set Active Registers, last offset - RW. */
207#define GIC_DIST_REG_ISACTIVERn_OFF_LAST 0x037c
208/** Interrupt Clear Active Registers, start offset - RW. */
209#define GIC_DIST_REG_ICACTIVERn_OFF_START 0x0380
210/** Interrupt Clear Active Registers, last offset - RW. */
211#define GIC_DIST_REG_ICACTIVERn_OFF_LAST 0x03fc
212
213/** Interrupt Priority Registers, start offset - RW. */
214#define GIC_DIST_REG_IPRIORITYn_OFF_START 0x0400
215/** Interrupt Priority Registers, last offset - RW. */
216#define GIC_DIST_REG_IPRIORITYn_OFF_LAST 0x07f8
217
218/** Interrupt Processor Targets Registers, start offset - RO/RW. */
219#define GIC_DIST_REG_ITARGETSRn_OFF_START 0x0800
220/** Interrupt Processor Targets Registers, last offset - RO/RW. */
221#define GIC_DIST_REG_ITARGETSRn_OFF_LAST 0x0bf8
222
223/** Interrupt Configuration Registers, start offset - RW. */
224#define GIC_DIST_REG_ICFGRn_OFF_START 0x0c00
225/** Interrupt Configuration Registers, last offset - RW. */
226#define GIC_DIST_REG_ICFGRn_OFF_LAST 0x0cfc
227
228/** Interrupt Group Modifier Registers, start offset - RW. */
229#define GIC_DIST_REG_IGRPMODRn_OFF_START 0x0d00
230/** Interrupt Group Modifier Registers, last offset - RW. */
231#define GIC_DIST_REG_IGRPMODRn_OFF_LAST 0x0d7c
232
233/** Non-secure Access Control Registers, start offset - RW. */
234#define GIC_DIST_REG_NSACRn_OFF_START 0x0e00
235/** Non-secure Access Control Registers, last offset - RW. */
236#define GIC_DIST_REG_NSACRn_OFF_LAST 0x0efc
237
238/** Software Generated Interrupt Register - RW. */
239#define GIC_DIST_REG_SGIR_OFF 0x0f00
240
241/** SGI Clear Pending Registers, start offset - RW. */
242#define GIC_DIST_REG_CPENDSGIRn_OFF_START 0x0f10
243/** SGI Clear Pending Registers, last offset - RW. */
244#define GIC_DIST_REG_CPENDSGIRn_OFF_LAST 0x0f1c
245/** SGI Set Pending Registers, start offset - RW. */
246#define GIC_DIST_REG_SPENDSGIRn_OFF_START 0x0f20
247/** SGI Set Pending Registers, last offset - RW. */
248#define GIC_DIST_REG_SPENDSGIRn_OFF_LAST 0x0f2c
249
250/** Non-maskable Interrupt Registers, start offset - RW. */
251#define GIC_DIST_REG_INMIn_OFF_START 0x0f80
252/** Non-maskable Interrupt Registers, last offset - RW. */
253#define GIC_DIST_REG_INMIn_OFF_LAST 0x0ffc
254
255
256/** Interrupt Group Registers for extended SPI range, start offset - RW. */
257#define GIC_DIST_REG_IGROUPRnE_OFF_START 0x1000
258/** Interrupt Group Registers for extended SPI range, last offset - RW. */
259#define GIC_DIST_REG_IGROUPRnE_OFF_LAST 0x107c
260
261/** Interrupt Set Enable Registers for extended SPI range, start offset - RW. */
262#define GIC_DIST_REG_ISENABLERnE_OFF_START 0x1200
263/** Interrupt Set Enable Registers for extended SPI range, last offset - RW. */
264#define GIC_DIST_REG_ISENABLERnE_OFF_LAST 0x127c
265/** Interrupt Clear Enable Registers for extended SPI range, start offset - RW. */
266#define GIC_DIST_REG_ICENABLERnE_OFF_START 0x1400
267/** Interrupt Clear Enable Registers for extended SPI range, last offset - RW. */
268#define GIC_DIST_REG_ICENABLERnE_OFF_LAST 0x147c
269
270/** Interrupt Set Pending Registers for extended SPI range, start offset - RW. */
271#define GIC_DIST_REG_ISPENDRnE_OFF_START 0x1600
272/** Interrupt Set Pending Registers for extended SPI range, last offset - RW. */
273#define GIC_DIST_REG_ISPENDRnE_OFF_LAST 0x167c
274/** Interrupt Clear Pending Registers for extended SPI range, start offset - RW. */
275#define GIC_DIST_REG_ICPENDRnE_OFF_START 0x1800
276/** Interrupt Clear Pending Registers for extended SPI range, last offset - RW. */
277#define GIC_DIST_REG_ICPENDRnE_OFF_LAST 0x187c
278
279/** Interrupt Set Active Registers for extended SPI range, start offset - RW. */
280#define GIC_DIST_REG_ISACTIVERnE_OFF_START 0x1a00
281/** Interrupt Set Active Registers for extended SPI range, last offset - RW. */
282#define GIC_DIST_REG_ISACTIVERnE_OFF_LAST 0x1a7c
283/** Interrupt Clear Active Registers for extended SPI range, start offset - RW. */
284#define GIC_DIST_REG_ICACTIVERnE_OFF_START 0x1c00
285/** Interrupt Clear Active Registers for extended SPI range, last offset - RW. */
286#define GIC_DIST_REG_ICACTIVERnE_OFF_LAST 0x1c7c
287
288/** Interrupt Priority Registers for extended SPI range, start offset - RW. */
289#define GIC_DIST_REG_IPRIORITYnE_OFF_START 0x2000
290/** Interrupt Priority Registers for extended SPI range, last offset - RW. */
291#define GIC_DIST_REG_IPRIORITYnE_OFF_LAST 0x23fc
292
293/** Interrupt Configuration Registers for extended SPI range, start offset - RW. */
294#define GIC_DIST_REG_ICFGRnE_OFF_START 0x3000
295/** Interrupt Configuration Registers for extended SPI range, last offset - RW. */
296#define GIC_DIST_REG_ICFGRnE_OFF_LAST 0x30fc
297
298/** Interrupt Group Modifier Registers for extended SPI range, start offset - RW. */
299#define GIC_DIST_REG_IGRPMODRnE_OFF_START 0x3400
300/** Interrupt Group Modifier Registers for extended SPI range, last offset - RW. */
301#define GIC_DIST_REG_IGRPMODRnE_OFF_LAST 0x347c
302
303/** Non-secure Access Control Registers for extended SPI range, start offset - RW. */
304#define GIC_DIST_REG_NSACRnE_OFF_START 0x3600
305/** Non-secure Access Control Registers for extended SPI range, last offset - RW. */
306#define GIC_DIST_REG_NSACRnE_OFF_LAST 0x367c
307
308/** Non-maskable Interrupt Registers for extended SPIs, start offset - RW. */
309#define GIC_DIST_REG_INMInE_OFF_START 0x3b00
310/** Non-maskable Interrupt Registers for extended SPIs, last offset - RW. */
311#define GIC_DIST_REG_INMInE_OFF_LAST 0x3b7c
312
313/** Interrupt Routing Registers, start offset - RW. */
314#define GIC_DIST_REG_IROUTERn_OFF_START 0x6100
315/** Interrupt Routing Registers, last offset - RW. */
316#define GIC_DIST_REG_IROUTERn_OFF_LAST 0x7fd8
317/** Interrupt Routing Registers for extended SPI range, start offset - RW. */
318#define GIC_DIST_REG_IROUTERnE_OFF_START 0x8000
319/** Interrupt Routing Registers for extended SPI range, last offset - RW. */
320#define GIC_DIST_REG_IROUTERnE_OFF_LAST 0x9ffc
321
322/** Distributor Peripheral ID2 Register - RO. */
323#define GIC_DIST_REG_PIDR2_OFF 0xffe8
324/** Bit 4 - 7 - GIC architecture revision */
325# define GIC_DIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \
326 | RT_BIT_32(7))
327# define GIC_DIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
328/** GICv1 architecture revision. */
329# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV1 0x1
330/** GICv2 architecture revision. */
331# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV2 0x2
332/** GICv3 architecture revision. */
333# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV3 0x3
334/** GICv4 architecture revision. */
335# define GIC_DIST_REG_PIDR2_ARCH_REV_GICV4 0x4
336/** @} */
337
338
339/** @name GICD - GIC Redistributor registers.
340 * @{ */
341/** Size of the redistributor register frame. */
342#define GIC_REDIST_REG_FRAME_SIZE _64K
343/** Redistributor Control Register - RW. */
344#define GIC_REDIST_REG_CTLR_OFF 0x0000
345/** Implementer Identification Register - RO. */
346#define GIC_REDIST_REG_IIDR_OFF 0x0004
347
348/** Redistributor Type Register - RO. */
349#define GIC_REDIST_REG_TYPER_OFF 0x0008
350/** Bit 0 - Indicates whether the GIC implementation supports physical LPIs. */
351# define GIC_REDIST_REG_TYPER_PLPIS RT_BIT_32(0)
352# define GIC_REDIST_REG_TYPER_PLPIS_BIT 0
353/** Bit 1 - Indicates whether the GIC implementation supports virtual LPIs and the direct injection of those. */
354# define GIC_REDIST_REG_TYPER_VLPIS RT_BIT_32(1)
355# define GIC_REDIST_REG_TYPER_VLPIS_BIT 1
356/** Bit 2 - Controls the functionality of GICR_VPENDBASER.Dirty. */
357# define GIC_REDIST_REG_TYPER_DIRTY RT_BIT_32(2)
358# define GIC_REDIST_REG_TYPER_DIRTY_BIT 2
359/** Bit 3 - Indicates whether the redistributor supports direct injection of LPIs. */
360# define GIC_REDIST_REG_TYPER_DIRECT_LPI RT_BIT_32(3)
361# define GIC_REDIST_REG_TYPER_DIRECT_LPI_BIT 3
362/** Bit 4 - Indicates whether this redistributor is the highest numbered Redistributor in a series. */
363# define GIC_REDIST_REG_TYPER_LAST RT_BIT_32(4)
364# define GIC_REDIST_REG_TYPER_LAST_BIT 4
365/** Bit 5 - Sets support for GICR_CTLR.DPG* bits. */
366# define GIC_REDIST_REG_TYPER_DPGS RT_BIT_32(5)
367# define GIC_REDIST_REG_TYPER_DPGS_BIT 5
368/** Bit 6 - Indicates whether MPAM is supported. */
369# define GIC_REDIST_REG_TYPER_MPAM RT_BIT_32(6)
370# define GIC_REDIST_REG_TYPER_MPAM_BIT 6
371/** Bit 7 - Indicates how the resident vPE is specified. */
372# define GIC_REDIST_REG_TYPER_RVPEID RT_BIT_32(7)
373# define GIC_REDIST_REG_TYPER_RVPEID_BIT 7
374/** Bit 8 - 23 - A unique identifier for the PE. */
375# define GIC_REDIST_REG_TYPER_CPU_NUMBER UINT32_C(0x00ffff00)
376# define GIC_REDIST_REG_TYPER_CPU_NUMBER_SET(a_CpuNum) (((a_CpuNum) << 8) & GIC_REDIST_REG_TYPER_CPU_NUMBER)
377/** Bit 24 - 25 - The affinity level at Redistributorsshare an LPI Configuration table. */
378# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF (RT_BIT_32(24) | RT_BIT_32(25))
379# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_SET(a_LpiAff) (((a_LpiAff) << 24) & GIC_REDIST_REG_TYPER_CMN_LPI_AFF)
380/** All Redistributors must share an LPI Configuration table. */
381# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_ALL 0
382/** All Redistributors with the same affinity 3 value must share an LPI Configuration table. */
383# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3 1
384/** All Redistributors with the same affinity 3.2 value must share an LPI Configuration table. */
385# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3_2 2
386/** All Redistributors with the same affinity 3.2.1 value must share an LPI Configuration table. */
387# define GIC_REDIST_REG_TYPER_CMN_LPI_AFF_3_2_1 3
388/** Bit 26 - Indicates whether vSGIs are supported. */
389# define GIC_REDIST_REG_TYPER_VSGI RT_BIT_32(26)
390# define GIC_REDIST_REG_TYPER_VSGI_BIT 26
391/** Bit 27 - 31 - Indicates the maximum PPI INTID that a GIC implementation can support. */
392# define GIC_REDIST_REG_TYPER_PPI_NUM ( RT_BIT_32(27) | RT_BIT_32(28) | RT_BIT_32(29) \
393 | RT_BIT_32(30) | RT_BIT_32(31))
394# define GIC_REDIST_REG_TYPER_PPI_NUM_SET(a_PpiNum) (((a_PpiNum) << 27) & GIC_REDIST_REG_TYPER_PPI_NUM)
395/** Maximum PPI INTID is 31. */
396# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_31 0
397/** Maximum PPI INTID is 1087. */
398# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 1
399/** Maximum PPI INTID is 1119. */
400# define GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119 2
401
402/** Redistributor Type Register (the affinity value of the 64-bit register) - RO. */
403#define GIC_REDIST_REG_TYPER_AFFINITY_OFF 0x000c
404/** Bit 0 - 31 - The identity of the PE associated with this Redistributor. */
405# define GIC_REDIST_REG_TYPER_AFFINITY_VALUE UINT32_C(0xffffffff)
406# define GIC_REDIST_REG_TYPER_AFFINITY_VALUE_SET(a_Aff) ((a_Aff) & GIC_REDIST_REG_TYPER_AFFINITY_VALUE)
407
408
409/** Redistributor Error Reporting Status Register (optional) - RW. */
410#define GIC_REDIST_REG_STATUSR_OFF 0x0010
411/** Redistributor Wake Register - RW. */
412#define GIC_REDIST_REG_WAKER_OFF 0x0014
413/** Redistributor Report maximum PARTID and PMG Register - RO. */
414#define GIC_REDIST_REG_MPAMIDR_OFF 0x0018
415/** Redistributor Set PARTID and PMG Register - RW. */
416#define GIC_REDIST_REG_PARTIDR_OFF 0x001c
417/** Redistributor Set LPI Pending Register - WO. */
418#define GIC_REDIST_REG_SETLPIR_OFF 0x0040
419/** Redistributor Clear LPI Pending Register - WO. */
420#define GIC_REDIST_REG_CLRLPIR_OFF 0x0048
421/** Redistributor Properties Base Address Register - RW. */
422#define GIC_REDIST_REG_PROPBASER_OFF 0x0070
423/** Redistributor LPI Pending Table Base Address Register - RW. */
424#define GIC_REDIST_REG_PENDBASER_OFF 0x0078
425/** Redistributor Invalidate LPI Register - WO. */
426#define GIC_REDIST_REG_INVLPIR_OFF 0x00a0
427/** Redistributor Invalidate All Register - WO. */
428#define GIC_REDIST_REG_INVALLR_OFF 0x00b0
429/** Redistributor Synchronize Register - RO. */
430#define GIC_REDIST_REG_SYNCR_OFF 0x00c0
431
432/** Redistributor Peripheral ID2 Register - RO. */
433#define GIC_REDIST_REG_PIDR2_OFF 0xffe8
434/** Bit 4 - 7 - GIC architecture revision */
435# define GIC_REDIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \
436 | RT_BIT_32(7))
437# define GIC_REDIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
438/** GICv1 architecture revision. */
439# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV1 0x1
440/** GICv2 architecture revision. */
441# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV2 0x2
442/** GICv3 architecture revision. */
443# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3 0x3
444/** GICv4 architecture revision. */
445# define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV4 0x4
446/** @} */
447
448
449/** @name GICD - GIC SGI and PPI Redistributor registers (Adjacent to the GIC Redistributor register space).
450 * @{ */
451/** Size of the SGI and PPI redistributor register frame. */
452#define GIC_REDIST_SGI_PPI_REG_FRAME_SIZE _64K
453
454/** Interrupt Group Register 0 - RW. */
455#define GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF 0x0080
456/** Interrupt Group Register 1 for extended PPI range - RW. */
457#define GIC_REDIST_SGI_PPI_REG_IGROUPR1E_OFF 0x0084
458/** Interrupt Group Register 2 for extended PPI range - RW. */
459#define GIC_REDIST_SGI_PPI_REG_IGROUPR2E_OFF 0x0084
460
461/** Interrupt Set Enable Register 0 - RW. */
462#define GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF 0x0100
463/** Interrupt Set Enable Register 1 for extended PPI range - RW. */
464#define GIC_REDIST_SGI_PPI_REG_ISENABLER1E_OFF 0x0104
465/** Interrupt Set Enable Register 2 for extended PPI range - RW. */
466#define GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF 0x0108
467
468/** Interrupt Clear Enable Register 0 - RW. */
469#define GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF 0x0180
470/** Interrupt Clear Enable Register 1 for extended PPI range - RW. */
471#define GIC_REDIST_SGI_PPI_REG_ICENABLER1E_OFF 0x0184
472/** Interrupt Clear Enable Register 2 for extended PPI range - RW. */
473#define GIC_REDIST_SGI_PPI_REG_ICENABLER2E_OFF 0x0188
474
475/** Interrupt Set Pend Register 0 - RW. */
476#define GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF 0x0200
477/** Interrupt Set Pend Register 1 for extended PPI range - RW. */
478#define GIC_REDIST_SGI_PPI_REG_ISPENDR1E_OFF 0x0204
479/** Interrupt Set Pend Register 2 for extended PPI range - RW. */
480#define GIC_REDIST_SGI_PPI_REG_ISPENDR2E_OFF 0x0208
481
482/** Interrupt Clear Pend Register 0 - RW. */
483#define GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF 0x0280
484/** Interrupt Clear Pend Register 1 for extended PPI range - RW. */
485#define GIC_REDIST_SGI_PPI_REG_ICPENDR1E_OFF 0x0284
486/** Interrupt Clear Pend Register 2 for extended PPI range - RW. */
487#define GIC_REDIST_SGI_PPI_REG_ICPENDR2E_OFF 0x0288
488
489/** Interrupt Set Active Register 0 - RW. */
490#define GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF 0x0300
491/** Interrupt Set Active Register 1 for extended PPI range - RW. */
492#define GIC_REDIST_SGI_PPI_REG_ISACTIVER1E_OFF 0x0304
493/** Interrupt Set Active Register 2 for extended PPI range - RW. */
494#define GIC_REDIST_SGI_PPI_REG_ISACTIVER2E_OFF 0x0308
495
496/** Interrupt Clear Active Register 0 - RW. */
497#define GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF 0x0380
498/** Interrupt Clear Active Register 1 for extended PPI range - RW. */
499#define GIC_REDIST_SGI_PPI_REG_ICACTIVER1E_OFF 0x0384
500/** Interrupt Clear Active Register 2 for extended PPI range - RW. */
501#define GIC_REDIST_SGI_PPI_REG_ICACTIVER2E_OFF 0x0388
502
503/** Interrupt Priority Registers, start offset - RW. */
504#define GIC_REDIST_SGI_PPI_REG_IPRIORITYn_OFF_START 0x0400
505/** Interrupt Priority Registers, last offset - RW. */
506#define GIC_REDIST_SGI_PPI_REG_IPRIORITYn_OFF_LAST 0x041c
507/** Interrupt Priority Registers for extended PPI range, start offset - RW. */
508#define GIC_REDIST_SGI_PPI_REG_IPRIORITYnE_OFF_START 0x0420
509/** Interrupt Priority Registers for extended PPI range, last offset - RW. */
510#define GIC_REDIST_SGI_PPI_REG_IPRIORITYnE_OFF_LAST 0x045c
511
512/** SGI Configuration Register - RW. */
513#define GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF 0x0c00
514/** PPI Configuration Register - RW. */
515#define GIC_REDIST_SGI_PPI_REG_ICFGR1_OFF 0x0c04
516/** Extended PPI Configuration Register, start offset - RW. */
517#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_START 0x0c08
518/** Extended PPI Configuration Register, last offset - RW. */
519#define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST 0x0c14
520
521/** Interrupt Group Modifier Register 0 - RW. */
522#define GIC_REDIST_SGI_PPI_REG_IGRPMODR0_OFF 0x0d00
523/** Interrupt Group Modifier Register 1 for extended PPI range - RW. */
524#define GIC_REDIST_SGI_PPI_REG_IGRPMODR1E_OFF 0x0d04
525/** Interrupt Group Modifier Register 2 for extended PPI range - RW. */
526#define GIC_REDIST_SGI_PPI_REG_IGRPMODR2E_OFF 0x0d08
527
528/** Non Secure Access Control Register - RW. */
529#define GIC_REDIST_SGI_PPI_REG_NSACR_OFF 0x0e00
530
531/** Non maskable Interrupt Register for PPIs - RW. */
532#define GIC_REDIST_SGI_PPI_REG_INMIR0_OFF 0x0f80
533/** Non maskable Interrupt Register for Extended PPIs, start offset - RW. */
534#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_START 0x0f84
535/** Non maskable Interrupt Register for Extended PPIs, last offset - RW. */
536#define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_LAST 0x0ffc
537/** @} */
538
539
540#endif /* !VBOX_INCLUDED_gic_h */
541
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