gic-its.h

Last change on this file was 109226, checked in by vboxsync, 12 days ago
VMM/GIC: bugref:10877 GIC ITS, MSI/LPIs work-in-progress.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 36.9 KB

Line
1	/** @file
2	* ARMv8 GIC Interrupt Translation Service (ITS) definitions.
3	*/
4
5	/*
6	* Copyright (C) 2025 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_gic_its_h
37	#define VBOX_INCLUDED_gic_its_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/types.h>
43	#include <iprt/assertcompile.h>
44
45	/** Size of the ITS register frame. */
46	#define GITS_REG_FRAME_SIZE _64K
47	/** The offset mask for an ITS register within a frame. */
48	#define GITS_REG_OFFSET_MASK (_64K - 1)
49
50	/** The GITS command queue page size. */
51	#define GITS_CMD_QUEUE_PAGE_SIZE 0x1000
52	/** The GITS command queue page offset mask. */
53	#define GITS_CMD_QUEUE_PAGE_OFFSET_MASK 0xfff
54	/** The guest page shift (x86). */
55	#define GITS_CMD_QUEUE_PAGE_SHIFT 12
56
57	/** The GITS command size in bytes. */
58	#define GITS_CMD_SIZE 32
59
60	/** GITS_CTLR: Control register - RW. */
61	#define GITS_CTRL_REG_CTLR_OFF 0x0000
62	/** GITS_CTLR: Enabled. */
63	#define GITS_BF_CTRL_REG_CTLR_ENABLED_SHIFT 0
64	#define GITS_BF_CTRL_REG_CTLR_ENABLED_MASK UINT32_C(0x00000001)
65	/** GITS_CTLR: ImDe - Implementation Defined. */
66	#define GITS_BF_CTRL_REG_CTLR_IM_DE_SHIFT 1
67	#define GITS_BF_CTRL_REG_CTLR_IM_DE_MASK UINT32_C(0x00000002)
68	/** GITS_CTLR: Reserved (bits 3:2). */
69	#define GITS_BF_CTRL_REG_CTLR_RSVD_3_2_SHIFT 2
70	#define GITS_BF_CTRL_REG_CTLR_RSVD_3_2_MASK UINT32_C(0x0000000c)
71	/** GITS_CTLR: ITS_Number (0 for GICv3). */
72	#define GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_SHIFT 4
73	#define GITS_BF_CTRL_REG_CTLR_ITS_NUMBER_MASK UINT32_C(0x000000f0)
74	/** GITS_CTLR: UMSIirq - Unmapped MSI reporting interrupt enable. */
75	#define GITS_BF_CTRL_REG_CTLR_UMSI_IRQ_SHIFT 8
76	#define GITS_BF_CTRL_REG_CTLR_UMSI_IRQ_MASK UINT32_C(0x00000100)
77	/** GITS_CTLR: Reserved (bits 30:9). */
78	#define GITS_BF_CTRL_REG_CTLR_RSVD_30_9_SHIFT 9
79	#define GITS_BF_CTRL_REG_CTLR_RSVD_30_9_MASK UINT32_C(0x7ffffe00)
80	/** GITS_CTLR: Quiescent. */
81	#define GITS_BF_CTRL_REG_CTLR_QUIESCENT_SHIFT 31
82	#define GITS_BF_CTRL_REG_CTLR_QUIESCENT_MASK UINT32_C(0x80000000)
83	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CTLR_, UINT32_C(0), UINT32_MAX,
84	(ENABLED, IM_DE, RSVD_3_2, ITS_NUMBER, UMSI_IRQ, RSVD_30_9, QUIESCENT));
85	/** GITS_CTLR: Mask of valid read-write bits. */
86	#define GITS_BF_CTRL_REG_CTLR_RW_MASK ( GITS_BF_CTRL_REG_CTLR_ENABLED_MASK \
87	\| GITS_BF_CTRL_REG_CTLR_IM_DE_MASK)
88
89	/** GITS_IIDR: Implementer and revision register - RO. */
90	#define GITS_CTRL_REG_IIDR_OFF 0x0004
91	/** GITS_IIDR: Implementer - JEP106 identification code. */
92	#define GITS_BF_CTRL_REG_IIDR_IMPL_ID_CODE_SHIFT 0
93	#define GITS_BF_CTRL_REG_IIDR_IMPL_ID_CODE_MASK UINT32_C(0x0000007f)
94	/** GITS_IIDR: Implementer - Reserved (bit 7). */
95	#define GITS_BF_CTRL_REG_IIDR_IMPL_ZERO_7_SHIFT 7
96	#define GITS_BF_CTRL_REG_IIDR_IMPL_ZERO_7_MASK UINT32_C(0x00000080)
97	/** GITS_IIDR: Implementer - JEP106 continuation code. */
98	#define GITS_BF_CTRL_REG_IIDR_IMPL_CONT_CODE_SHIFT 8
99	#define GITS_BF_CTRL_REG_IIDR_IMPL_CONT_CODE_MASK UINT32_C(0x00000f00)
100	/** GITS_IIDR: Revision. */
101	#define GITS_BF_CTRL_REG_IIDR_REVISION_SHIFT 12
102	#define GITS_BF_CTRL_REG_IIDR_REVISION_MASK UINT32_C(0x0000f000)
103	/** GITS_IIDR: Variant. */
104	#define GITS_BF_CTRL_REG_IIDR_VARIANT_SHIFT 16
105	#define GITS_BF_CTRL_REG_IIDR_VARIANT_MASK UINT32_C(0x000f0000)
106	/** GITS_IIDR: Reserved (bits 23:20). */
107	#define GITS_BF_CTRL_REG_IIDR_RSVD_23_20_SHIFT 20
108	#define GITS_BF_CTRL_REG_IIDR_RSVD_23_20_MASK UINT32_C(0x00f00000)
109	/** GITS_IIDR: Product ID. */
110	#define GITS_BF_CTRL_REG_IIDR_PRODUCT_ID_SHIFT 24
111	#define GITS_BF_CTRL_REG_IIDR_PRODUCT_ID_MASK UINT32_C(0xff000000)
112	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_IIDR_, UINT32_C(0), UINT32_MAX,
113	(IMPL_ID_CODE, IMPL_ZERO_7, IMPL_CONT_CODE, REVISION, VARIANT, RSVD_23_20, PRODUCT_ID));
114
115	/** GITS_TYPER: Feature register - RO. */
116	#define GITS_CTRL_REG_TYPER_OFF 0x0008
117	/** GITS_TYPER: Physical - Physical LPI support. */
118	#define GITS_BF_CTRL_REG_TYPER_PHYSICAL_SHIFT 0
119	#define GITS_BF_CTRL_REG_TYPER_PHYSICAL_MASK UINT64_C(0x0000000000000001)
120	/** GITS_TYPER: Virtual - Virtual LPI support. */
121	#define GITS_BF_CTRL_REG_TYPER_VIRTUAL_SHIFT 1
122	#define GITS_BF_CTRL_REG_TYPER_VIRTUAL_MASK UINT64_C(0x0000000000000002)
123	/** GITS_TYPER: CCT - Cumulative Collections Table. */
124	#define GITS_BF_CTRL_REG_TYPER_CCT_SHIFT 2
125	#define GITS_BF_CTRL_REG_TYPER_CCT_MASK UINT64_C(0x0000000000000004)
126	/** GITS_TYPER: Implementation Defined. */
127	#define GITS_BF_CTRL_REG_TYPER_IM_DE_SHIFT 3
128	#define GITS_BF_CTRL_REG_TYPER_IM_DE_MASK UINT64_C(0x0000000000000008)
129	/** GITS_TYPER: ITT_entry_size - Size of translation table entry. */
130	#define GITS_BF_CTRL_REG_TYPER_ITT_ENTRY_SIZE_SHIFT 4
131	#define GITS_BF_CTRL_REG_TYPER_ITT_ENTRY_SIZE_MASK UINT64_C(0x00000000000000f0)
132	/** GITS_TYPER: ID_bits - Number of event ID bits implemented (minus one). */
133	#define GITS_BF_CTRL_REG_TYPER_ID_BITS_SHIFT 8
134	#define GITS_BF_CTRL_REG_TYPER_ID_BITS_MASK UINT64_C(0x0000000000001f00)
135	/** GITS_TYPER: Devbits - Number of device ID bits implemented (minus one). */
136	#define GITS_BF_CTRL_REG_TYPER_DEV_BITS_SHIFT 13
137	#define GITS_BF_CTRL_REG_TYPER_DEV_BITS_MASK UINT64_C(0x000000000003e000)
138	/** GITS_TYPER: SEIS - SEI support for virtual CPUs. */
139	#define GITS_BF_CTRL_REG_TYPER_SEIS_SHIFT 18
140	#define GITS_BF_CTRL_REG_TYPER_SEIS_MASK UINT64_C(0x0000000000040000)
141	/** GITS_TYPER: PTA - Physical target address format. */
142	#define GITS_BF_CTRL_REG_TYPER_PTA_SHIFT 19
143	#define GITS_BF_CTRL_REG_TYPER_PTA_MASK UINT64_C(0x0000000000080000)
144	/** GITS_TYPER: Reserved (bits 23:20). */
145	#define GITS_BF_CTRL_REG_TYPER_RSVD_23_20_SHIFT 20
146	#define GITS_BF_CTRL_REG_TYPER_RSVD_23_20_MASK UINT64_C(0x0000000000f00000)
147	/** GITS_TYPER: HCC - Hardware collection count. */
148	#define GITS_BF_CTRL_REG_TYPER_HCC_SHIFT 24
149	#define GITS_BF_CTRL_REG_TYPER_HCC_MASK UINT64_C(0x00000000ff000000)
150	/** GITS_TYPER: CIDbits - Number of collection ID bits (minus one). */
151	#define GITS_BF_CTRL_REG_TYPER_CID_BITS_SHIFT 32
152	#define GITS_BF_CTRL_REG_TYPER_CID_BITS_MASK UINT64_C(0x0000000f00000000)
153	/** GITS_TYPER: CIL - Collection ID limit. */
154	#define GITS_BF_CTRL_REG_TYPER_CIL_SHIFT 36
155	#define GITS_BF_CTRL_REG_TYPER_CIL_MASK UINT64_C(0x0000001000000000)
156	/** GITS_TYPER: VMOVP - Form of VMOVP command. */
157	#define GITS_BF_CTRL_REG_TYPER_VMOVP_SHIFT 37
158	#define GITS_BF_CTRL_REG_TYPER_VMOVP_MASK UINT64_C(0x0000002000000000)
159	/** GITS_TYPER: MPAM - Memory partitioning and monitoring support. */
160	#define GITS_BF_CTRL_REG_TYPER_MPAM_SHIFT 38
161	#define GITS_BF_CTRL_REG_TYPER_MPAM_MASK UINT64_C(0x0000004000000000)
162	/** GITS_TYPER: VSGI - Direct injection of virtual SGI support. */
163	#define GITS_BF_CTRL_REG_TYPER_VSGI_SHIFT 39
164	#define GITS_BF_CTRL_REG_TYPER_VSGI_MASK UINT64_C(0x0000008000000000)
165	/** GITS_TYPER: VMAPP - VMAPP command support. */
166	#define GITS_BF_CTRL_REG_TYPER_VMAPP_SHIFT 40
167	#define GITS_BF_CTRL_REG_TYPER_VMAPP_MASK UINT64_C(0x0000010000000000)
168	/** GITS_TYPER: SVPET - Shared VPE table configuration. */
169	#define GITS_BF_CTRL_REG_TYPER_SVPET_SHIFT 41
170	#define GITS_BF_CTRL_REG_TYPER_SVPET_MASK UINT64_C(0x0000060000000000)
171	/** GITS_TYPER: nID - Individual doorbell interrupt support. */
172	#define GITS_BF_CTRL_REG_TYPER_NID_SHIFT 43
173	#define GITS_BF_CTRL_REG_TYPER_NID_MASK UINT64_C(0x0000080000000000)
174	/** GITS_TYPER: UMSI - Support for reporting receipts of unmapped MSI. */
175	#define GITS_BF_CTRL_REG_TYPER_UMSI_SHIFT 44
176	#define GITS_BF_CTRL_REG_TYPER_UMSI_MASK UINT64_C(0x0000100000000000)
177	/** GITS_TYPER: UMSIirq - Support for generating interrupt on receiving unmapped MSI. */
178	#define GITS_BF_CTRL_REG_TYPER_UMSI_IRQ_SHIFT 45
179	#define GITS_BF_CTRL_REG_TYPER_UMSI_IRQ_MASK UINT64_C(0x0000200000000000)
180	/** GITS_TYPER: INV - Invalidate ITS cache on disable. */
181	#define GITS_BF_CTRL_REG_TYPER_INV_SHIFT 46
182	#define GITS_BF_CTRL_REG_TYPER_INV_MASK UINT64_C(0x0000400000000000)
183	/** GITS_TYPER: Reserved (bits 63:47). */
184	#define GITS_BF_CTRL_REG_TYPER_RSVD_63_47_SHIFT 47
185	#define GITS_BF_CTRL_REG_TYPER_RSVD_63_47_MASK UINT64_C(0xffff800000000000)
186	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_TYPER_, UINT64_C(0), UINT64_MAX,
187	(PHYSICAL, VIRTUAL, CCT, IM_DE, ITT_ENTRY_SIZE, ID_BITS, DEV_BITS, SEIS, PTA, RSVD_23_20, HCC,
188	CID_BITS, CIL, VMOVP, MPAM, VSGI, VMAPP, SVPET, NID, UMSI, UMSI_IRQ, INV, RSVD_63_47));
189
190	/** GITS_MPAMIDR: Memory partitioning ID sizes. */
191	#define GITS_CTRL_REG_MPAMIDR_OFF 0x0010
192	/** GITS_MPAMIDR: PARTIDmax - Maximum PARTID value supported. */
193	#define GITS_BF_CTRL_REG_MPAMIDR_PARTID_MAX_SHIFT 0
194	#define GITS_BF_CTRL_REG_MPAMIDR_PARTID_MAX_MASK UINT32_C(0x0000ffff)
195	/** GITS_MPAMIDR: PMGmax - Maximum PMG value supported. */
196	#define GITS_BF_CTRL_REG_MPAMIDR_PMG_MAX_SHIFT 16
197	#define GITS_BF_CTRL_REG_MPAMIDR_PMG_MAX_MASK UINT32_C(0x00ff0000)
198	/** GITS_MPAMIDR: Reserved (bits 24:31). */
199	#define GITS_BF_CTRL_REG_MPAMIDR_RSVD_31_24_SHIFT 24
200	#define GITS_BF_CTRL_REG_MPAMIDR_RSVD_31_24_MASK UINT32_C(0xff000000)
201	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_MPAMIDR_, UINT32_C(0), UINT32_MAX, (PARTID_MAX, PMG_MAX, RSVD_31_24));
202
203	/** GITS_PARTID: PARTID and PMG values register. */
204	#define GITS_CTRL_REG_PARTIDR_OFF 0x0014
205	/** GITS_PARTID: PARTID - PARTID when ITS accesses memory. */
206	#define GITS_BF_CTRL_REG_PARTIDR_PARTID_SHIFT 0
207	#define GITS_BF_CTRL_REG_PARTIDR_PARTID_MASK UINT32_C(0x0000ffff)
208	/** GITS_PARTID: PMG - PMG value when ITS accesses memory. */
209	#define GITS_BF_CTRL_REG_PARTIDR_PMG_SHIFT 16
210	#define GITS_BF_CTRL_REG_PARTIDR_PMG_MASK UINT32_C(0x00ff0000)
211	/** GITS_PARTID: Reserved (bits 24:31). */
212	#define GITS_BF_CTRL_REG_PARTIDR_RSVD_31_24_SHIFT 24
213	#define GITS_BF_CTRL_REG_PARTIDR_RSVD_31_24_MASK UINT32_C(0xff000000)
214	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PARTIDR_, UINT32_C(0), UINT32_MAX, (PARTID, PMG, RSVD_31_24));
215
216	#define GITS_CTRL_REG_MPIDR_OFF 0x0018
217	#define GITS_CTRL_REG_STATUSR_OFF 0x0040
218	#define GITS_CTRL_REG_UMSIR_OFF 0x0048
219
220	/** GITS_CBASER: ITS command queue base register - RW. */
221	#define GITS_CTRL_REG_CBASER_OFF 0x0080
222	#define GITS_BF_CTRL_REG_CBASER_SIZE_SHIFT 0
223	#define GITS_BF_CTRL_REG_CBASER_SIZE_MASK UINT64_C(0x00000000000000ff)
224	#define GITS_BF_CTRL_REG_CBASER_RSVD_9_8_SHIFT 8
225	#define GITS_BF_CTRL_REG_CBASER_RSVD_9_8_MASK UINT64_C(0x0000000000000300)
226	#define GITS_BF_CTRL_REG_CBASER_SHAREABILITY_SHIFT 10
227	#define GITS_BF_CTRL_REG_CBASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
228	#define GITS_BF_CTRL_REG_CBASER_PHYS_ADDR_SHIFT 12
229	#define GITS_BF_CTRL_REG_CBASER_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
230	#define GITS_BF_CTRL_REG_CBASER_RSVD_52_SHIFT 52
231	#define GITS_BF_CTRL_REG_CBASER_RSVD_52_MASK UINT64_C(0x0010000000000000)
232	#define GITS_BF_CTRL_REG_CBASER_OUTER_CACHE_SHIFT 53
233	#define GITS_BF_CTRL_REG_CBASER_OUTER_CACHE_MASK UINT64_C(0x00e0000000000000)
234	#define GITS_BF_CTRL_REG_CBASER_RSVD_58_56_SHIFT 56
235	#define GITS_BF_CTRL_REG_CBASER_RSVD_58_56_MASK UINT64_C(0x0700000000000000)
236	#define GITS_BF_CTRL_REG_CBASER_INNER_CACHE_SHIFT 59
237	#define GITS_BF_CTRL_REG_CBASER_INNER_CACHE_MASK UINT64_C(0x3800000000000000)
238	#define GITS_BF_CTRL_REG_CBASER_RSVD_62_SHIFT 62
239	#define GITS_BF_CTRL_REG_CBASER_RSVD_62_MASK UINT64_C(0x4000000000000000)
240	#define GITS_BF_CTRL_REG_CBASER_VALID_SHIFT 63
241	#define GITS_BF_CTRL_REG_CBASER_VALID_MASK UINT64_C(0x8000000000000000)
242	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CBASER_, UINT64_C(0), UINT64_MAX,
243	(SIZE, RSVD_9_8, SHAREABILITY, PHYS_ADDR, RSVD_52, OUTER_CACHE, RSVD_58_56, INNER_CACHE, RSVD_62,
244	VALID));
245	/** GITS_CBASER: Physical address bits [15:12] are reserved MBZ. */
246	#define GITS_CTRL_REG_CBASER_PHYS_ADDR_RSVD_15_12_MASK UINT64_C(0x000000000000f000)
247	/** GITS_CBASER: Mask of valid read-write bits. */
248	#define GITS_CTRL_REG_CBASER_RW_MASK (UINT64_MAX & ~(GITS_BF_CTRL_REG_CBASER_RSVD_9_8_MASK \| \
249	GITS_BF_CTRL_REG_CBASER_RSVD_52_MASK \| \
250	GITS_BF_CTRL_REG_CBASER_RSVD_58_56_MASK \| \
251	GITS_BF_CTRL_REG_CBASER_RSVD_62_MASK \| \
252	GITS_CTRL_REG_CBASER_PHYS_ADDR_RSVD_15_12_MASK))
253
254	/** GITS_CWRITER: ITS command queue write register - RW. */
255	#define GITS_CTRL_REG_CWRITER_OFF 0x0088
256	#define GITS_BF_CTRL_REG_CWRITER_RETRY_SHIFT 0
257	#define GITS_BF_CTRL_REG_CWRITER_RETRY_MASK UINT64_C(0x0000000000000001)
258	#define GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_SHIFT 1
259	#define GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_MASK UINT64_C(0x000000000000001e)
260	#define GITS_BF_CTRL_REG_CWRITER_OFFSET_SHIFT 5
261	#define GITS_BF_CTRL_REG_CWRITER_OFFSET_MASK UINT64_C(0x00000000000fffe0)
262	#define GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_SHIFT 20
263	#define GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
264	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CWRITER_, UINT64_C(0), UINT64_MAX,
265	(RETRY, RSVD_4_1, OFFSET, RSVD_63_20));
266	#define GITS_CTRL_REG_CWRITER_RW_MASK (UINT64_MAX & ~(GITS_BF_CTRL_REG_CWRITER_RSVD_4_1_MASK \| \
267	GITS_BF_CTRL_REG_CWRITER_RSVD_63_20_MASK))
268
269	/** GITS_CREADR: Command read register - RO. */
270	#define GITS_CTRL_REG_CREADR_OFF 0x0090
271	#define GITS_BF_CTRL_REG_CREADR_STALLED_SHIFT 0
272	#define GITS_BF_CTRL_REG_CREADR_STALLED_MASK UINT64_C(0x0000000000000001)
273	#define GITS_BF_CTRL_REG_CREADR_RSVD_4_1_SHIFT 1
274	#define GITS_BF_CTRL_REG_CREADR_RSVD_4_1_MASK UINT64_C(0x000000000000001e)
275	#define GITS_BF_CTRL_REG_CREADR_OFFSET_SHIFT 5
276	#define GITS_BF_CTRL_REG_CREADR_OFFSET_MASK UINT64_C(0x00000000000fffe0)
277	#define GITS_BF_CTRL_REG_CREADR_RSVD_63_20_SHIFT 20
278	#define GITS_BF_CTRL_REG_CREADR_RSVD_63_20_MASK UINT64_C(0xfffffffffff00000)
279	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_CREADR_, UINT64_C(0), UINT64_MAX,
280	(STALLED, RSVD_4_1, OFFSET, RSVD_63_20));
281
282	/** GITS_BASER: ITS Table Descriptors - RW. */
283	#define GITS_CTRL_REG_BASER_OFF_FIRST 0x0100
284	#define GITS_CTRL_REG_BASER_OFF_LAST 0x0138
285	#define GITS_CTRL_REG_BASER_RANGE_SIZE (GITS_CTRL_REG_BASER_OFF_LAST + sizeof(uint64_t) - GITS_CTRL_REG_BASER_OFF_FIRST)
286	/** GITS_BASER: Size - Number of pages allocated to the table minus one. */
287	#define GITS_BF_CTRL_REG_BASER_SIZE_SHIFT 0
288	#define GITS_BF_CTRL_REG_BASER_SIZE_MASK UINT64_C(0x00000000000000ff)
289	/** GITS_BASER: Page_Size - Size of the page that the table uses. */
290	#define GITS_BF_CTRL_REG_BASER_PAGESIZE_SHIFT 8
291	#define GITS_BF_CTRL_REG_BASER_PAGESIZE_MASK UINT64_C(0x0000000000000300)
292	/** GITS_BASER: Shareability attributes of the table. */
293	#define GITS_BF_CTRL_REG_BASER_SHAREABILITY_SHIFT 10
294	#define GITS_BF_CTRL_REG_BASER_SHAREABILITY_MASK UINT64_C(0x0000000000000c00)
295	/** GITS_BASER: Physical_Address - Physical address of the table. */
296	#define GITS_BF_CTRL_REG_BASER_PHYS_ADDR_SHIFT 12
297	#define GITS_BF_CTRL_REG_BASER_PHYS_ADDR_MASK UINT64_C(0x0000fffffffff000)
298	/** GITS_BASER: Entry_Size - Size of each table entry minus one in bytes. */
299	#define GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_SHIFT 48
300	#define GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_MASK UINT64_C(0x001f000000000000)
301	/** GITS_BASER: OuterCache - Outer cacheability attributes of the table. */
302	#define GITS_BF_CTRL_REG_BASER_OUTER_CACHE_SHIFT 53
303	#define GITS_BF_CTRL_REG_BASER_OUTER_CACHE_MASK UINT64_C(0x00e0000000000000)
304	/** GITS_BASER: Type - The type of entity. */
305	#define GITS_BF_CTRL_REG_BASER_TYPE_SHIFT 56
306	#define GITS_BF_CTRL_REG_BASER_TYPE_MASK UINT64_C(0x0700000000000000)
307	/** GITS_BASER: InnerCache - Inner cacheability attribtues of the table. */
308	#define GITS_BF_CTRL_REG_BASER_INNER_CACHE_SHIFT 59
309	#define GITS_BF_CTRL_REG_BASER_INNER_CACHE_MASK UINT64_C(0x3800000000000000)
310	/** GITS_BASER: Indirect - Whether this is a single or two-level table. */
311	#define GITS_BF_CTRL_REG_BASER_INDIRECT_SHIFT 62
312	#define GITS_BF_CTRL_REG_BASER_INDIRECT_MASK UINT64_C(0x4000000000000000)
313	/** GITS_BASER: Valid - Whether memory has been allocated for the table. */
314	#define GITS_BF_CTRL_REG_BASER_VALID_SHIFT 63
315	#define GITS_BF_CTRL_REG_BASER_VALID_MASK UINT64_C(0x8000000000000000)
316	/* Sigh C macros... "PAGE_SIZE" is already defined here, just use "PAGESIZE" instead of temporarily undef, redef. */
317	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_BASER_, UINT64_C(0), UINT64_MAX,
318	(SIZE, PAGESIZE, SHAREABILITY, PHYS_ADDR, ENTRY_SIZE, OUTER_CACHE, TYPE, INNER_CACHE, INDIRECT,
319	VALID));
320	/** GITS_BASER: Mask of valid read-write bits. */
321	#define GITS_CTRL_REG_BASER_RW_MASK (UINT64_MAX & ~( GITS_BF_CTRL_REG_BASER_ENTRY_SIZE_MASK \
322	\| GITS_BF_CTRL_REG_BASER_TYPE_MASK))
323
324	/** GITS_BASER: Table type - Unimplemented (not a table). */
325	#define GITS_BASER_TYPE_UNIMPL 0
326	/** GITS_BASER: Table type - Devices. */
327	#define GITS_BASER_TYPE_DEVICES 1
328	/** GITS_BASER: Table type - vPE. */
329	#define GITS_BASER_TYPE_VPES 2
330	/** GITS_BASER: Table type - Interrupt Collections. */
331	#define GITS_BASER_TYPE_INTR_COLLECTION 3
332
333	/** GITS_BASER: Page_Size: 4K. */
334	#define GITS_BASER_PAGE_SIZE_4K 0
335	/** GITS_BASER: Page_Size: 16K. */
336	#define GITS_BASER_PAGE_SIZE_16K 1
337	/** GITS_BASER: Page_Size: 64K. */
338	#define GITS_BASER_PAGE_SIZE_64K 2
339	/** GITS_BASER: Page_Size: Reserved (treated as 64K). */
340	#define GITS_BASER_PAGE_SIZE_RSVD 3
341
342	/** GITS_PIDR2: ITS Peripheral ID2 register - RO. */
343	#define GITS_CTRL_REG_PIDR2_OFF 0xffe8
344	/** GITS_PIDR2: JEDEC - JEP code. */
345	#define GITS_BF_CTRL_REG_PIDR2_JEDEC_SHIFT 0
346	#define GITS_BF_CTRL_REG_PIDR2_JEDEC_MASK UINT32_C(0x00000007)
347	/** GITS_PIDR2: DES_1 - JEP106 identification code (bits 6:4). */
348	#define GITS_BF_CTRL_REG_PIDR2_DES_1_SHIFT 3
349	#define GITS_BF_CTRL_REG_PIDR2_DES_1_MASK UINT32_C(0x00000008)
350	/** GITS_PIDR2: Architecture revision . */
351	#define GITS_BF_CTRL_REG_PIDR2_ARCHREV_SHIFT 4
352	#define GITS_BF_CTRL_REG_PIDR2_ARCHREV_MASK UINT32_C(0x000000f0)
353	/** GITS_PIDR2: Reserved (bits 31:8). */
354	#define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_SHIFT 8
355	#define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_MASK UINT32_C(0xffffff00)
356	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PIDR2_, UINT32_C(0), UINT32_MAX,
357	(JEDEC, DES_1, ARCHREV, RSVD_31_8));
358
359	/** GITS_PIDR2: GICv1 architecture revision. */
360	#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV1 0x1
361	/** GITS_PIDR2: GICv2 architecture revision. */
362	#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV2 0x2
363	/** GITS_PIDR2: GICv3 architecture revision. */
364	#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV3 0x3
365	/** GITS_PIDR2: GICv4 architecture revision. */
366	#define GITS_CTRL_REG_PIDR2_ARCHREV_GICV4 0x4
367
368	/** GITS_TRANSLATER register. */
369	#define GITS_TRANSLATION_REG_TRANSLATER 0x0040
370
371	/** GITS indirect table level-1 entry (4K page size). */
372	#define GITS_BF_ITE_INDIRECT_LVL1_4K_RSVD_11_0_SHIFT 0
373	#define GITS_BF_ITE_INDIRECT_LVL1_4K_RSVD_11_0_MASK UINT64_C(0x0000000000000fff)
374	#define GITS_BF_ITE_INDIRECT_LVL1_4K_PHYS_ADDR_SHIFT 12
375	#define GITS_BF_ITE_INDIRECT_LVL1_4K_PHYS_ADDR_MASK UINT64_C(0x000ffffffffff000)
376	#define GITS_BF_ITE_INDIRECT_LVL1_4K_RSVD_62_52_SHIFT 52
377	#define GITS_BF_ITE_INDIRECT_LVL1_4K_RSVD_62_52_MASK UINT64_C(0x7ff0000000000000)
378	#define GITS_BF_ITE_INDIRECT_LVL1_4K_VALID_SHIFT 63
379	#define GITS_BF_ITE_INDIRECT_LVL1_4K_VALID_MASK UINT64_C(0x8000000000000000)
380	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_ITE_INDIRECT_LVL1_4K_, UINT64_C(0), UINT64_MAX,
381	(RSVD_11_0, PHYS_ADDR, RSVD_62_52, VALID));
382
383	/** GITS indirect table level-1 entry (16K page size). */
384	#define GITS_BF_ITE_INDIRECT_LVL1_16K_RSVD_14_0_SHIFT 0
385	#define GITS_BF_ITE_INDIRECT_LVL1_16K_RSVD_14_0_MASK UINT64_C(0x0000000000003fff)
386	#define GITS_BF_ITE_INDIRECT_LVL1_16K_PHYS_ADDR_SHIFT 14
387	#define GITS_BF_ITE_INDIRECT_LVL1_16K_PHYS_ADDR_MASK UINT64_C(0x000fffffffffc000)
388	#define GITS_BF_ITE_INDIRECT_LVL1_16K_RSVD_62_52_SHIFT 52
389	#define GITS_BF_ITE_INDIRECT_LVL1_16K_RSVD_62_52_MASK UINT64_C(0x7ff0000000000000)
390	#define GITS_BF_ITE_INDIRECT_LVL1_16K_VALID_SHIFT 63
391	#define GITS_BF_ITE_INDIRECT_LVL1_16K_VALID_MASK UINT64_C(0x8000000000000000)
392	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_ITE_INDIRECT_LVL1_16K_, UINT64_C(0), UINT64_MAX,
393	(RSVD_14_0, PHYS_ADDR, RSVD_62_52, VALID));
394
395	/** GITS indirect table level-1 entry (64K page size). */
396	#define GITS_BF_ITE_INDIRECT_LVL1_64K_RSVD_15_0_SHIFT 0
397	#define GITS_BF_ITE_INDIRECT_LVL1_64K_RSVD_15_0_MASK UINT64_C(0x000000000000ffff)
398	#define GITS_BF_ITE_INDIRECT_LVL1_64K_PHYS_ADDR_SHIFT 16
399	#define GITS_BF_ITE_INDIRECT_LVL1_64K_PHYS_ADDR_MASK UINT64_C(0x000fffffffff0000)
400	#define GITS_BF_ITE_INDIRECT_LVL1_64K_RSVD_62_52_SHIFT 52
401	#define GITS_BF_ITE_INDIRECT_LVL1_64K_RSVD_62_52_MASK UINT64_C(0x7ff0000000000000)
402	#define GITS_BF_ITE_INDIRECT_LVL1_64K_VALID_SHIFT 63
403	#define GITS_BF_ITE_INDIRECT_LVL1_64K_VALID_MASK UINT64_C(0x8000000000000000)
404	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_ITE_INDIRECT_LVL1_64K_, UINT64_C(0), UINT64_MAX,
405	(RSVD_15_0, PHYS_ADDR, RSVD_62_52, VALID));
406
407	/** GITS indirect table level-1 entry size in bytes. */
408	#define GITS_ITE_INDIRECT_LVL1_SIZE 8
409
410	/**
411	* Memory shareability attributes.
412	* In accordance to the ARM GIC spec.
413	*/
414	typedef enum GITSATTRSHARE
415	{
416	GITSATTRSHARE_NON_SHAREABLE = 0,
417	GITSATTRSHARE_INNER_SHAREABLE,
418	GITSATTRSHARE_OUTER_SHAREABLE,
419	GITSATTRSHARE_RSVD
420	} GITSATTRSHARE;
421
422	/**
423	* Memory cacheability attribute.
424	* In accordance to the ARM GIC spec.
425	*/
426	typedef enum GITSATTRMEM
427	{
428	GITSATTRMEM_DEFAULT = 0,
429	GITSATTRMEM_NOCACHE,
430	GITSATTRMEM_CACHE_RD_ALLOC_WT,
431	GITSATTRMEM_CACHE_RD_ALLOC_WB,
432	GITSATTRMEM_CACHE_WR_ALLOC_WT,
433	GITSATTRMEM_CACHE_WR_ALLOC_WB,
434	GITSATTRMEM_CACHE_RW_ALLOC_WT,
435	GITSATTRMEM_CACHE_RW_ALLOC_WB
436	} GITSMEMATTR;
437
438	/**
439	* GITS entry type.
440	* In accordance to the ARM GIC spec.
441	*/
442	typedef enum GITSITSTYPE
443	{
444	GITSITSTYPE_UNIMPLEMENTED = 0,
445	GITSITSTYPE_DEVICES,
446	GITSITSTYPE_VPES,
447	GITSITSTYPE_INTR_COLLECTIONS
448	} GITSITSTYPE;
449
450	/**
451	* ITS command.
452	* In accordance to the ARM GIC spec.
453	*/
454	typedef union GITSCMD
455	{
456	RTUINT64U au64[4];
457	struct
458	{
459	uint8_t uCmdId;
460	uint8_t auData[31];
461	} common;
462	} GITSCMD;
463	/** Pointer to an ITS command. */
464	typedef GITSCMD *PGITSCMD;
465	/** Pointer to a const ITS command. */
466	typedef GITSCMD const *PCGITSCMD;
467	AssertCompileSize(GITSCMD, GITS_CMD_SIZE);
468
469	/** @name GITS command IDs.
470	* @{ */
471	#define GITS_CMD_ID_CLEAR 0x04
472	#define GITS_CMD_ID_DISCARD 0x0f
473	#define GITS_CMD_ID_INT 0x03
474	#define GITS_CMD_ID_INV 0x0c
475	#define GITS_CMD_ID_INVALL 0x0d
476	#define GITS_CMD_ID_INVDB 0x2e
477	#define GITS_CMD_ID_MAPC 0x09
478	#define GITS_CMD_ID_MAPD 0x08
479	#define GITS_CMD_ID_MAPI 0x0b
480	#define GITS_CMD_ID_MAPTI 0x0a
481	#define GITS_CMD_ID_MOVALL 0x0e
482	#define GITS_CMD_ID_MOVI 0x01
483	#define GITS_CMD_ID_SYNC 0x05
484	#define GITS_CMD_ID_VINVALL 0x2d
485	#define GITS_CMD_ID_VMAPI 0x2b
486	#define GITS_CMD_ID_VMAPP 0x29
487	#define GITS_CMD_ID_VMAPTI 0x2a
488	#define GITS_CMD_ID_VMOVI 0x21
489	#define GITS_CMD_ID_VMOVP 0x22
490	#define GITS_CMD_ID_VSGI 0x23
491	#define GITS_CMD_ID_VSYNC 0x25
492	/** @} */
493
494	/** @name GITS command: MAPC.
495	* @{ */
496	/** MAPC DW0: Command ID. */
497	#define GITS_BF_CMD_MAPC_DW0_CMD_ID_SHIFT 0
498	#define GITS_BF_CMD_MAPC_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
499	/** MAPC DW0: Reserved (bits 63:8). */
500	#define GITS_BF_CMD_MAPC_DW0_RSVD_63_8_SHIFT 8
501	#define GITS_BF_CMD_MAPC_DW0_RSVD_63_8_MASK UINT64_C(0xffffffffffffff00)
502	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPC_DW0_, UINT64_C(0), UINT64_MAX,
503	(CMD_ID, RSVD_63_8));
504
505	/** MAPC DW1: Reserved (bits 63:0). */
506	#define GITS_BF_CMD_MAPC_DW1_RSVD_63_0_MASK UINT64_MAX
507
508	/** MAPC DW2: IC ID - The interrupt collection ID. */
509	#define GITS_BF_CMD_MAPC_DW2_IC_ID_SHIFT 0
510	#define GITS_BF_CMD_MAPC_DW2_IC_ID_MASK UINT64_C(0x000000000000ffff)
511	/** MAPC DW2: RDBase - The target redistributor base address or PE number. */
512	#define GITS_BF_CMD_MAPC_DW2_RDBASE_SHIFT 16
513	#define GITS_BF_CMD_MAPC_DW2_RDBASE_MASK UINT64_C(0x0007ffffffff0000)
514	/** MAPC DW2: Reserved (bits 62:51). */
515	#define GITS_BF_CMD_MAPC_DW2_RSVD_62_51_SHIFT 51
516	#define GITS_BF_CMD_MAPC_DW2_RSVD_62_51_MASK UINT64_C(0x7ff8000000000000)
517	/** MAPC DW2: Valid bit. */
518	#define GITS_BF_CMD_MAPC_DW2_VALID_SHIFT 63
519	#define GITS_BF_CMD_MAPC_DW2_VALID_MASK UINT64_C(0x8000000000000000)
520	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPC_DW2_, UINT64_C(0), UINT64_MAX,
521	(IC_ID, RDBASE, RSVD_62_51, VALID));
522
523	/** MAPC DW3: Reserved (bits 63:0). */
524	#define GITS_BF_CMD_MAPC_DW3_RSVD_63_0_MASK UINT64_MAX
525	/** @} */
526
527	/** @name GITS command: MAPD.
528	* @{ */
529	/** MAPD DW0: Command ID. */
530	#define GITS_BF_CMD_MAPD_DW0_CMD_ID_SHIFT 0
531	#define GITS_BF_CMD_MAPD_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
532	/** MAPD DW0: Reserved (bits 31:8). */
533	#define GITS_BF_CMD_MAPD_DW0_RSVD_31_8_SHIFT 8
534	#define GITS_BF_CMD_MAPD_DW0_RSVD_31_8_MASK UINT64_C(0x00000000ffffff00)
535	/** MAPD DW0: Device ID. */
536	#define GITS_BF_CMD_MAPD_DW0_DEV_ID_SHIFT 32
537	#define GITS_BF_CMD_MAPD_DW0_DEV_ID_MASK UINT64_C(0xffffffff00000000)
538	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPD_DW0_, UINT64_C(0), UINT64_MAX,
539	(CMD_ID, RSVD_31_8, DEV_ID));
540
541	/** MAPD DW1: Size. */
542	#define GITS_BF_CMD_MAPD_DW1_SIZE_SHIFT 0
543	#define GITS_BF_CMD_MAPD_DW1_SIZE_MASK UINT64_C(0x000000000000001f)
544	/** MAPD DW1: Reserved (bits 63:5). */
545	#define GITS_BF_CMD_MAPD_DW1_RSVD_63_5_SHIFT 5
546	#define GITS_BF_CMD_MAPD_DW1_RSVD_63_5_MASK UINT64_C(0xffffffffffffffe0)
547	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPD_DW1_, UINT64_C(0), UINT64_MAX,
548	(SIZE, RSVD_63_5));
549
550	/** MAPD: DW2: Reserved (bits 7:0). */
551	#define GITS_BF_CMD_MAPD_DW2_RSVD_7_0_SHIFT 0
552	#define GITS_BF_CMD_MAPD_DW2_RSVD_7_0_MASK UINT64_C(0x00000000000000ff)
553	/** MAPD: DW2: ITT address. */
554	#define GITS_BF_CMD_MAPD_DW2_ITT_ADDR_SHIFT 8
555	#define GITS_BF_CMD_MAPD_DW2_ITT_ADDR_MASK UINT64_C(0x000fffffffffff00)
556	/** MAPD: DW2: Reserved (bits 62:52). */
557	#define GITS_BF_CMD_MAPD_DW2_RSVD_62_52_SHIFT 52
558	#define GITS_BF_CMD_MAPD_DW2_RSVD_62_52_MASK UINT64_C(0x7ff0000000000000)
559	/** MAPD: DW2: Valid. */
560	#define GITS_BF_CMD_MAPD_DW2_VALID_SHIFT 63
561	#define GITS_BF_CMD_MAPD_DW2_VALID_MASK UINT64_C(0x8000000000000000)
562	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPD_DW2_, UINT64_C(0), UINT64_MAX,
563	(RSVD_7_0, ITT_ADDR, RSVD_62_52, VALID));
564	/** @} */
565
566	/** @name GITS command: MAPTI.
567	* @{ */
568	/** MAPTI DW0: Command ID. */
569	#define GITS_BF_CMD_MAPTI_DW0_CMD_ID_SHIFT 0
570	#define GITS_BF_CMD_MAPTI_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
571	/** MAPTI DW0: Reserved (bits 31:8). */
572	#define GITS_BF_CMD_MAPTI_DW0_RSVD_31_8_SHIFT 8
573	#define GITS_BF_CMD_MAPTI_DW0_RSVD_31_8_MASK UINT64_C(0x00000000ffffff00)
574	/** MAPTI DW0: Device ID. */
575	#define GITS_BF_CMD_MAPTI_DW0_DEV_ID_SHIFT 32
576	#define GITS_BF_CMD_MAPTI_DW0_DEV_ID_MASK UINT64_C(0xffffffff00000000)
577	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPTI_DW0_, UINT64_C(0), UINT64_MAX,
578	(CMD_ID, RSVD_31_8, DEV_ID));
579
580	/** MAPTI DW1: Event ID. */
581	#define GITS_BF_CMD_MAPTI_DW1_EVENT_ID_SHIFT 0
582	#define GITS_BF_CMD_MAPTI_DW1_EVENT_ID_MASK UINT64_C(0x00000000ffffffff)
583	/** MAPTI DW1: Physical INTID. */
584	#define GITS_BF_CMD_MAPTI_DW1_PHYS_INTID_SHIFT 32
585	#define GITS_BF_CMD_MAPTI_DW1_PHYS_INTID_MASK UINT64_C(0xffffffff00000000)
586	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPTI_DW1_, UINT64_C(0), UINT64_MAX,
587	(EVENT_ID, PHYS_INTID));
588
589	/** MAPTI DW2: ICID. */
590	#define GITS_BF_CMD_MAPTI_DW2_IC_ID_SHIFT 0
591	#define GITS_BF_CMD_MAPTI_DW2_IC_ID_MASK UINT64_C(0x000000000000ffff)
592	/** MAPTI DW2: Reserved (bits 63:16). */
593	#define GITS_BF_CMD_MAPTI_DW2_RSVD_63_16_SHIFT 16
594	#define GITS_BF_CMD_MAPTI_DW2_RSVD_63_16_MASK UINT64_C(0xffffffffffff0000)
595	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_MAPTI_DW2_, UINT64_C(0), UINT64_MAX,
596	(IC_ID, RSVD_63_16));
597	/** @} */
598
599	/** @name GITS command: INV.
600	* @{ */
601	/** INV DW0: Command ID. */
602	#define GITS_BF_CMD_INV_DW0_CMD_ID_SHIFT 0
603	#define GITS_BF_CMD_INV_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
604	/** INV DW0: Reserved (bits 31:8). */
605	#define GITS_BF_CMD_INV_DW0_RSVD_31_8_SHIFT 8
606	#define GITS_BF_CMD_INV_DW0_RSVD_31_8_MASK UINT64_C(0x00000000ffffff00)
607	/** INV DW0: Device ID. */
608	#define GITS_BF_CMD_INV_DW0_DEV_ID_SHIFT 32
609	#define GITS_BF_CMD_INV_DW0_DEV_ID_MASK UINT64_C(0xffffffff00000000)
610	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_INV_DW0_, UINT64_C(0), UINT64_MAX,
611	(CMD_ID, RSVD_31_8, DEV_ID));
612
613	/** INV DW1: Event ID. */
614	#define GITS_BF_CMD_INV_DW1_EVENT_ID_SHIFT 0
615	#define GITS_BF_CMD_INV_DW1_EVENT_ID_MASK UINT64_C(0x00000000ffffffff)
616	/** INV DW1: Reserved (bits 63:32). */
617	#define GITS_BF_CMD_INV_DW1_RSVD_63_32_SHIFT 32
618	#define GITS_BF_CMD_INV_DW1_RSVD_63_32_MASK UINT64_C(0xffffffff00000000)
619	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_INV_DW1_, UINT64_C(0), UINT64_MAX,
620	(EVENT_ID, RSVD_63_32));
621	/** @} */
622
623	/** @name GITS command: INVALL.
624	* @{ */
625	/** INVALL DW0: Command ID. */
626	#define GITS_BF_CMD_INVALL_DW0_CMD_ID_SHIFT 0
627	#define GITS_BF_CMD_INVALL_DW0_CMD_ID_MASK UINT64_C(0x00000000000000ff)
628	/** INVALL DW0: Reserved (bits 63:8). */
629	#define GITS_BF_CMD_INVALL_DW0_RSVD_63_8_SHIFT 8
630	#define GITS_BF_CMD_INVALL_DW0_RSVD_63_8_MASK UINT64_C(0xffffffffffffff00)
631	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_INVALL_DW0_, UINT64_C(0), UINT64_MAX,
632	(CMD_ID, RSVD_63_8));
633
634	/** INVALL DW1: Reserved (bits 63:0). */
635	#define GITS_BF_CMD_INVALL_DW1_RSVD_63_0_MASK UINT64_MAX
636
637	/** INVALL DW2: IC ID - The interrupt collection ID. */
638	#define GITS_BF_CMD_INVALL_DW2_IC_ID_SHIFT 0
639	#define GITS_BF_CMD_INVALL_DW2_IC_ID_MASK UINT64_C(0x000000000000ffff)
640	/** INVALL DW2: Reserved (bits 63:16). */
641	#define GITS_BF_CMD_INVALL_DW2_RSVD_63_16_SHIFT 16
642	#define GITS_BF_CMD_INVALL_DW2_RSVD_63_16_MASK UINT64_C(0xffffffffffff0000)
643	RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CMD_INVALL_DW2_, UINT64_C(0), UINT64_MAX,
644	(IC_ID, RSVD_63_16));
645
646	/** INVALL DW3: Reserved (bits 63:0). */
647	#define GITS_BF_CMD_INVALL_DW3_RSVD_63_0_MASK UINT64_MAX
648	/** @} */
649
650	#endif /* !VBOX_INCLUDED_gic_its_h */
651

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source: vbox/trunk/include/VBox/gic-its.h

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