VirtualBox

source: vbox/trunk/include/VBox/disopcode.h@ 73768

Last change on this file since 73768 was 70612, checked in by vboxsync, 6 years ago

VMM: Expose PCID, INVPCID, FSGSBASE features to guests. Implemented the relevant instructions in IEM.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 28.5 KB
Line 
1/** @file
2 * Disassembler - Opcodes
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_disopcode_h
27#define ___VBox_disopcode_h
28
29#include <iprt/assert.h>
30
31#define MODRM_MOD(a) (a>>6)
32#define MODRM_REG(a) ((a>>3)&0x7)
33#define MODRM_RM(a) (a&0x7)
34#define MAKE_MODRM(mod, reg, rm) (((mod&3) << 6) | ((reg&7) << 3) | (rm&7))
35
36#define SIB_SCALE(a) (a>>6)
37#define SIB_INDEX(a) ((a>>3)&0x7)
38#define SIB_BASE(a) (a&0x7)
39
40
41/** @defgroup grp_dis_opcodes Opcodes (DISOPCODE::uOpCode)
42 * @ingroup grp_dis
43 * @{
44 */
45enum OPCODES
46{
47/** @name Full Intel X86 opcode list
48 * @{ */
49 OP_INVALID = 0,
50 OP_OPSIZE,
51 OP_ADDRSIZE,
52 OP_SEG,
53 OP_REPNE,
54 OP_REPE,
55 OP_REX,
56 OP_LOCK,
57#ifndef IN_SLICKEDIT
58 OP_LAST_PREFIX = OP_LOCK, /**< Last prefix for disassembler. */
59#else
60 OP_LAST_PREFIX = 7, /**< Last prefix for disassembler. */
61#endif
62 OP_AND,
63 OP_OR,
64 OP_DAA,
65 OP_SUB,
66 OP_DAS,
67 OP_XOR,
68 OP_AAA,
69 OP_CMP,
70 OP_IMM_GRP1,
71 OP_AAS,
72 OP_INC,
73 OP_DEC,
74 OP_PUSHA,
75 OP_POPA,
76 OP_BOUND,
77 OP_ARPL,
78 OP_PUSH,
79 OP_POP,
80 OP_IMUL,
81 OP_INSB,
82 OP_INSWD,
83 OP_OUTSB,
84 OP_OUTSWD,
85 OP_JO,
86 OP_JNO,
87 OP_JC,
88 OP_JNC,
89 OP_JE,
90 OP_JNE,
91 OP_JBE,
92 OP_JNBE,
93 OP_JS,
94 OP_JNS,
95 OP_JP,
96 OP_JNP,
97 OP_JL,
98 OP_JNL,
99 OP_JLE,
100 OP_JNLE,
101 OP_ADD,
102 OP_TEST,
103 OP_XCHG,
104 OP_MOV,
105 OP_LEA,
106 OP_NOP,
107 OP_CBW,
108 OP_CWD,
109 OP_CALL,
110 OP_WAIT,
111 OP_PUSHF,
112 OP_POPF,
113 OP_SAHF,
114 OP_LAHF,
115 OP_MOVSB,
116 OP_MOVSWD,
117 OP_CMPSB,
118 OP_CMPWD,
119 OP_STOSB,
120 OP_STOSWD,
121 OP_LODSB,
122 OP_LODSWD,
123 OP_SCASB,
124 OP_SCASWD,
125 OP_SHIFT_GRP2,
126 OP_RETN,
127 OP_LES,
128 OP_LDS,
129 OP_ENTER,
130 OP_LEAVE,
131 OP_RETF,
132 OP_INT3,
133 OP_INT,
134 OP_INTO,
135 OP_IRET,
136 OP_AAM,
137 OP_AAD,
138 OP_XLAT,
139 OP_ESCF0,
140 OP_ESCF1,
141 OP_ESCF2,
142 OP_ESCF3,
143 OP_ESCF4,
144 OP_ESCF5,
145 OP_ESCF6,
146 OP_ESCF7,
147 OP_LOOPNE,
148 OP_LOOPE,
149 OP_LOOP,
150 OP_JECXZ,
151 OP_IN,
152 OP_OUT,
153 OP_JMP,
154 OP_2B_ESC,
155 OP_ADC,
156 OP_SBB,
157 OP_HLT,
158 OP_CMC,
159 OP_UNARY_GRP3,
160 OP_CLC,
161 OP_STC,
162 OP_CLI,
163 OP_STI,
164 OP_CLD,
165 OP_STD,
166 OP_INC_GRP4,
167 OP_IND_GRP5,
168 OP_GRP6,
169 OP_GRP7,
170 OP_LAR,
171 OP_LSL,
172 OP_SYSCALL,
173 OP_CLTS,
174 OP_SYSRET,
175 OP_INVD,
176 OP_WBINVD,
177 OP_ILLUD2,
178 OP_FEMMS,
179 OP_3DNOW,
180 OP_MOVUPS,
181 OP_MOVLPS,
182 OP_MOVHLPS = OP_MOVLPS, /**< @todo OP_MOVHLPS */
183 OP_UNPCKLPS,
184 OP_MOVHPS,
185 OP_MOVLHPS = OP_MOVHPS, /**< @todo OP_MOVLHPS */
186 OP_UNPCKHPS,
187 OP_PREFETCH_GRP16,
188 OP_MOV_CR,
189 OP_MOVAPS,
190 OP_CVTPI2PS,
191 OP_MOVNTPS,
192 OP_CVTTPS2PI,
193 OP_CVTPS2PI,
194 OP_UCOMISS,
195 OP_COMISS,
196 OP_WRMSR,
197 OP_RDTSC,
198 OP_RDMSR,
199 OP_RDPMC,
200 OP_SYSENTER,
201 OP_SYSEXIT,
202 OP_GETSEC,
203 OP_PAUSE,
204 OP_CMOVO,
205 OP_CMOVNO,
206 OP_CMOVC,
207 OP_CMOVNC,
208 OP_CMOVZ,
209 OP_CMOVNZ,
210 OP_CMOVBE,
211 OP_CMOVNBE,
212 OP_CMOVS,
213 OP_CMOVNS,
214 OP_CMOVP,
215 OP_CMOVNP,
216 OP_CMOVL,
217 OP_CMOVNL,
218 OP_CMOVLE,
219 OP_CMOVNLE,
220 OP_MOVMSKPS,
221 OP_SQRTPS,
222 OP_RSQRTPS,
223 OP_RCPPS,
224 OP_ANDPS,
225 OP_ANDNPS,
226 OP_ORPS,
227 OP_XORPS,
228 OP_ADDPS,
229 OP_MULPS,
230 OP_CVTPS2PD,
231 OP_CVTDQ2PS,
232 OP_SUBPS,
233 OP_MINPS,
234 OP_DIVPS,
235 OP_MAXPS,
236 OP_PUNPCKLBW,
237 OP_PUNPCKLWD,
238 OP_PUNPCKLDQ,
239 OP_PACKSSWB,
240 OP_PCMPGTB,
241 OP_PCMPGTW,
242 OP_PCMPGTD,
243 OP_PCMPGTQ,
244 OP_PACKUSWB,
245 OP_PUNPCKHBW,
246 OP_PUNPCKHWD,
247 OP_PUNPCKHDQ,
248 OP_PACKSSDW,
249 OP_MOVD,
250 OP_MOVQ,
251 OP_PSHUFW,
252 OP_3B_ESC4,
253 OP_3B_ESC5,
254 OP_PCMPEQB,
255 OP_PCMPEQW,
256 OP_PCMPEQD,
257 OP_PCMPEQQ,
258 OP_SETO,
259 OP_SETNO,
260 OP_SETC,
261 OP_SETNC,
262 OP_SETE,
263 OP_SETNE,
264 OP_SETBE,
265 OP_SETNBE,
266 OP_SETS,
267 OP_SETNS,
268 OP_SETP,
269 OP_SETNP,
270 OP_SETL,
271 OP_SETNL,
272 OP_SETLE,
273 OP_SETNLE,
274 OP_CPUID,
275 OP_BT,
276 OP_SHLD,
277 OP_RSM,
278 OP_BTS,
279 OP_SHRD,
280 OP_GRP15,
281 OP_CMPXCHG,
282 OP_LSS,
283 OP_BTR,
284 OP_LFS,
285 OP_LGS,
286 OP_MOVZX,
287 OP_GRP10_INV,
288 OP_GRP8,
289 OP_BTC,
290 OP_BSF,
291 OP_BSR,
292 OP_MOVSX,
293 OP_XADD,
294 OP_CMPPS,
295 OP_MOVNTI,
296 OP_PINSRW,
297 OP_PEXTRW,
298 OP_SHUFPS,
299 OP_GRP9,
300 OP_BSWAP,
301 OP_ADDSUBPS,
302 OP_ADDSUBPD,
303 OP_PSRLW,
304 OP_PSRLD,
305 OP_PSRLQ,
306 OP_PADDQ,
307 OP_PMULLW,
308 OP_PMOVMSKB,
309 OP_PSUBUSB,
310 OP_PSUBUSW,
311 OP_PMINUB,
312 OP_PAND,
313 OP_PADDUSB,
314 OP_PADDUSW,
315 OP_PMAXUB,
316 OP_PANDN,
317 OP_PAVGB,
318 OP_PSRAW,
319 OP_PSRAD,
320 OP_PAVGW,
321 OP_PMULHUW,
322 OP_PMULHW,
323 OP_MOVNTQ,
324 OP_PSUBSB,
325 OP_PSUBSW,
326 OP_PMINSW,
327 OP_POR,
328 OP_PADDSB,
329 OP_PADDSW,
330 OP_PMAXSW,
331 OP_PXOR,
332 OP_LDDQU,
333 OP_PSLLW,
334 OP_PSLLD,
335 OP_PSSQ,
336 OP_PMULUDQ,
337 OP_PMADDWD,
338 OP_PSADBW,
339 OP_MASKMOVQ,
340 OP_PSUBB,
341 OP_PSUBW,
342 OP_PSUBD,
343 OP_PSUBQ,
344 OP_PADDB,
345 OP_PADDW,
346 OP_PADDD,
347 OP_MOVUPD,
348 OP_MOVLPD,
349 OP_UNPCKLPD,
350 OP_UNPCKHPD,
351 OP_MOVHPD,
352 OP_MOVAPD,
353 OP_CVTPI2PD,
354 OP_MOVNTPD,
355 OP_CVTTPD2PI,
356 OP_CVTPD2PI,
357 OP_UCOMISD,
358 OP_COMISD,
359 OP_MOVMSKPD,
360 OP_SQRTPD,
361 OP_ANDPD,
362 OP_ANDNPD,
363 OP_ORPD,
364 OP_XORPD,
365 OP_ADDPD,
366 OP_MULPD,
367 OP_CVTPD2PS,
368 OP_CVTPS2DQ,
369 OP_SUBPD,
370 OP_MINPD,
371 OP_DIVPD,
372 OP_MAXPD,
373 OP_GRP12,
374 OP_GRP13,
375 OP_GRP14,
376 OP_EMMS,
377 OP_MMX_UD78,
378 OP_MMX_UD79,
379 OP_MMX_UD7A,
380 OP_MMX_UD7B,
381 OP_MMX_UD7C,
382 OP_MMX_UD7D,
383 OP_PUNPCKLQDQ,
384 OP_PUNPCKHQDQ,
385 OP_MOVDQA,
386 OP_PSHUFD,
387 OP_CMPPD,
388 OP_SHUFPD,
389 OP_CVTTPD2DQ,
390 OP_MOVNTDQ,
391 OP_MOVNTDQA,
392 OP_PACKUSDW,
393 OP_PSHUFB,
394 OP_PHADDW,
395 OP_PHADDD,
396 OP_PHADDSW,
397 OP_HADDPS,
398 OP_HADDPD,
399 OP_PMADDUBSW,
400 OP_PHSUBW,
401 OP_PHSUBD,
402 OP_PHSUBSW,
403 OP_HSUBPS,
404 OP_HSUBPD,
405 OP_PSIGNB,
406 OP_PSIGNW,
407 OP_PSIGND,
408 OP_PMULHRSW,
409 OP_PERMILPS,
410 OP_PERMILPD,
411 OP_TESTPS,
412 OP_TESTPD,
413 OP_PBLENDVB,
414 OP_CVTPH2PS,
415 OP_BLENDVPS,
416 OP_BLENDVPD,
417 OP_PERMPS,
418 OP_PERMD,
419 OP_PTEST,
420 OP_BROADCASTSS,
421 OP_BROADCASTSD,
422 OP_BROADCASTF128,
423 OP_PABSB,
424 OP_PABSW,
425 OP_PABSD,
426 OP_PMOVSX,
427 OP_PMOVZX,
428 OP_PMULDQ,
429 OP_PMINSB,
430 OP_PMINSD,
431 OP_PMINUW,
432 OP_PMINUD,
433 OP_PMAXSB,
434 OP_PMAXSD,
435 OP_PMAXUW,
436 OP_PMAXUD,
437 OP_PMULLD,
438 OP_PHMINPOSUW,
439 OP_PSRLVD,
440 OP_PSRAVD,
441 OP_PSLLVD,
442 OP_PBROADCASTD,
443 OP_PBROADCASTQ,
444 OP_PBROADCASTI128,
445 OP_PBROADCASTB,
446 OP_PBROADCASTW,
447 OP_PMASKMOVD,
448 OP_GATHER,
449 OP_FMADDSUB132PS,
450 OP_FMSUBADD132PS,
451 OP_FMADD132PS,
452 OP_FMADD132SS,
453 OP_FMSUB132PS,
454 OP_FMSUB132SS,
455 OP_FNMADD132PS,
456 OP_FNMADD132SS,
457 OP_FNMSUB132PS,
458 OP_FNMSUB132SS,
459 OP_FMADDSUB213PS,
460 OP_FMSUBADD213PS,
461 OP_FMADD213PS,
462 OP_FMADD213SS,
463 OP_FMSUB213PS,
464 OP_FMSUB213SS,
465 OP_FNMADD213PS,
466 OP_FNMADD213SS,
467 OP_FNMSUB213PS,
468 OP_FNMSUB213SS,
469 OP_FMADDSUB231PS,
470 OP_FMSUBADD231PS,
471 OP_FMADD231PS,
472 OP_FMADD231SS,
473 OP_FMSUB231PS,
474 OP_FMSUB231SS,
475 OP_FNMADD231PS,
476 OP_FNMADD231SS,
477 OP_FNMSUB231PS,
478 OP_FNMSUB231SS,
479 OP_AESIMC,
480 OP_AESENC,
481 OP_AESENCLAST,
482 OP_AESDEC,
483 OP_AESDECLAST,
484 OP_MOVBEGM,
485 OP_MOVBEMG,
486 OP_CRC32GDEB,
487 OP_CRC32GDEY,
488 OP_POPCNT,
489 OP_TZCNT,
490 OP_LZCNT,
491 OP_ADCX,
492 OP_ADOX,
493 OP_ANDN,
494 OP_BZHI,
495 OP_BEXTR,
496 OP_PEXT,
497 OP_SARX,
498 OP_PDEP,
499 OP_SHRX,
500 OP_MULX,
501 OP_MASKMOVDQU,
502 OP_MASKMOVPS,
503 OP_MASKMOVPD,
504 OP_MOVSD,
505 OP_CVTSI2SD,
506 OP_CVTTSD2SI,
507 OP_CVTSD2SI,
508 OP_SQRTSD,
509 OP_ADDSD,
510 OP_MULSD,
511 OP_CVTSD2SS,
512 OP_SUBSD,
513 OP_MINSD,
514 OP_DIVSD,
515 OP_MAXSD,
516 OP_PSHUFLW,
517 OP_CMPSD,
518 OP_MOVDQ2Q,
519 OP_CVTPD2DQ,
520 OP_MOVSS,
521 OP_MOVSLDUP,
522 OP_MOVDDUP,
523 OP_MOVSHDUP,
524 OP_CVTSI2SS,
525 OP_CVTTSS2SI,
526 OP_CVTSS2SI,
527 OP_CVTSS2SD,
528 OP_SQRTSS,
529 OP_RSQRTSS,
530 OP_RCPSS,
531 OP_ADDSS,
532 OP_MULSS,
533 OP_CVTTPS2DQ,
534 OP_SUBSS,
535 OP_MINSS,
536 OP_DIVSS,
537 OP_MAXSS,
538 OP_MOVDQU,
539 OP_PSHUFHW,
540 OP_CMPSS,
541 OP_MOVQ2DQ,
542 OP_CVTDQ2PD,
543 OP_PERMQ,
544 OP_PERMPD,
545 OP_PBLENDD,
546 OP_PERM2F128,
547 OP_ROUNDPS,
548 OP_ROUNDPD,
549 OP_ROUNDSS,
550 OP_ROUNDSD,
551 OP_BLENDPS,
552 OP_BLENDPD,
553 OP_PBLENDW,
554 OP_PALIGNR,
555 OP_PEXTRB,
556 OP_PEXTRD,
557 OP_EXTRACTPS,
558 OP_INSERTF128,
559 OP_EXTRACTF128,
560 OP_CVTPS2PH,
561 OP_PINSRB,
562 OP_PINSRD,
563 OP_INSERTPS,
564 OP_INSERTI128,
565 OP_EXTRACTI128,
566 OP_DPPS,
567 OP_DPPD,
568 OP_MPSADBW,
569 OP_PCLMULQDQ,
570 OP_PERM2I128,
571 OP_PCMPESTRM,
572 OP_PCMPESTRI,
573 OP_PCMPISTRM,
574 OP_PCMPISTRI,
575 OP_AESKEYGEN,
576 OP_RORX,
577 OP_VEX3B,
578 OP_VEX2B,
579/** @} */
580
581/** @name Floating point ops
582 * @{ */
583 OP_FADD,
584 OP_FMUL,
585 OP_FCOM,
586 OP_FCOMP,
587 OP_FSUB,
588 OP_FSUBR,
589 OP_FDIV,
590 OP_FDIVR,
591 OP_FLD,
592 OP_FST,
593 OP_FSTP,
594 OP_FLDENV,
595 OP_FSTENV,
596 OP_FSTCW,
597 OP_FXCH,
598 OP_FNOP,
599 OP_FCHS,
600 OP_FABS,
601 OP_FLD1,
602 OP_FLDL2T,
603 OP_FLDL2E,
604 OP_FLDPI,
605 OP_FLDLG2,
606 OP_FLDLN2,
607 OP_FLDZ,
608 OP_F2XM1,
609 OP_FYL2X,
610 OP_FPTAN,
611 OP_FPATAN,
612 OP_FXTRACT,
613 OP_FREM1,
614 OP_FDECSTP,
615 OP_FINCSTP,
616 OP_FPREM,
617 OP_FYL2XP1,
618 OP_FSQRT,
619 OP_FSINCOS,
620 OP_FRNDINT,
621 OP_FSCALE,
622 OP_FSIN,
623 OP_FCOS,
624 OP_FIADD,
625 OP_FIMUL,
626 OP_FISUB,
627 OP_FISUBR,
628 OP_FIDIV,
629 OP_FIDIVR,
630 OP_FCMOVB,
631 OP_FCMOVE,
632 OP_FCMOVBE,
633 OP_FCMOVU,
634 OP_FUCOMPP,
635 OP_FILD,
636 OP_FIST,
637 OP_FISTP,
638 OP_FCMOVNB,
639 OP_FCMOVNE,
640 OP_FCMOVNBE,
641 OP_FCMOVNU,
642 OP_FCLEX,
643 OP_FINIT,
644 OP_FUCOMI,
645 OP_FCOMI,
646 OP_FRSTOR,
647 OP_FSAVE,
648 OP_FNSTSW,
649 OP_FFREE,
650 OP_FUCOM,
651 OP_FUCOMP,
652 OP_FICOM,
653 OP_FICOMP,
654 OP_FADDP,
655 OP_FMULP,
656 OP_FCOMPP,
657 OP_FSUBRP,
658 OP_FSUBP,
659 OP_FDIVRP,
660 OP_FDIVP,
661 OP_FBLD,
662 OP_FBSTP,
663 OP_FCOMIP,
664 OP_FUCOMIP,
665/** @} */
666
667/** @name 3DNow!
668 * @{ */
669 OP_PI2FW,
670 OP_PI2FD,
671 OP_PF2IW,
672 OP_PF2ID,
673 OP_PFPNACC,
674 OP_PFCMPGE,
675 OP_PFMIN,
676 OP_PFRCP,
677 OP_PFRSQRT,
678 OP_PFSUB,
679 OP_PFADD,
680 OP_PFCMPGT,
681 OP_PFMAX,
682 OP_PFRCPIT1,
683 OP_PFRSQRTIT1,
684 OP_PFSUBR,
685 OP_PFACC,
686 OP_PFCMPEQ,
687 OP_PFMUL,
688 OP_PFRCPIT2,
689 OP_PFMULHRW,
690 OP_PFSWAPD,
691 OP_PAVGUSB,
692 OP_PFNACC,
693/** @} */
694 OP_ROL,
695 OP_ROR,
696 OP_RCL,
697 OP_RCR,
698 OP_SHL,
699 OP_SHR,
700 OP_SAR,
701 OP_NOT,
702 OP_NEG,
703 OP_MUL,
704 OP_DIV,
705 OP_IDIV,
706 OP_SLDT,
707 OP_STR,
708 OP_LLDT,
709 OP_LTR,
710 OP_VERR,
711 OP_VERW,
712 OP_SGDT,
713 OP_LGDT,
714 OP_SIDT,
715 OP_LIDT,
716 OP_SMSW,
717 OP_LMSW,
718 OP_INVLPG,
719 OP_CMPXCHG8B,
720 OP_PSLLQ,
721 OP_PSRLDQ,
722 OP_PSLLDQ,
723 OP_FXSAVE,
724 OP_FXRSTOR,
725 OP_LDMXCSR,
726 OP_STMXCSR,
727 OP_XSAVE,
728 OP_XSAVEOPT,
729 OP_XRSTOR,
730 OP_RDFSBASE,
731 OP_RDGSBASE,
732 OP_WRFSBASE,
733 OP_WRGSBASE,
734 OP_LFENCE,
735 OP_MFENCE,
736 OP_SFENCE,
737 OP_PREFETCH,
738 OP_MONITOR,
739 OP_MWAIT,
740 OP_CLFLUSH,
741 OP_CLFLUSHOPT,
742 OP_MOV_DR,
743 OP_MOV_TR,
744 OP_SWAPGS,
745 OP_UD1,
746 OP_UD2,
747/** @name VT-x instructions
748 * @{ */
749 OP_VMREAD,
750 OP_VMWRITE,
751 OP_VMCALL,
752 OP_VMXON,
753 OP_VMXOFF,
754 OP_VMCLEAR,
755 OP_VMLAUNCH,
756 OP_VMRESUME,
757 OP_VMPTRLD,
758 OP_VMPTRST,
759 OP_INVEPT,
760 OP_INVVPID,
761 OP_INVPCID,
762 OP_VMFUNC,
763/** @} */
764/** @name AMD-V instructions
765 * @{ */
766 OP_VMMCALL,
767 OP_VMRUN,
768 OP_VMLOAD,
769 OP_VMSAVE,
770 OP_CLGI,
771 OP_STGI,
772 OP_INVLPGA,
773 OP_SKINIT,
774/** @} */
775/** @name 64 bits instruction
776 * @{ */
777 OP_MOVSXD,
778/** @} */
779/** @name AVX instructions
780 * @{ */
781 OP_VLDMXCSR,
782 OP_VSTMXCSR,
783 OP_VMOVUPS,
784 OP_VMOVUPD,
785 OP_VMOVSS,
786 OP_VMOVSD,
787 OP_VMOVHLPS,
788 OP_VMOVLPS,
789 OP_VMOVLPD,
790 OP_VMOVSLDUP,
791 OP_VMOVDDUP,
792 OP_VMOVAPS,
793 OP_VMOVAPD,
794 OP_VMOVNTPS,
795 OP_VMOVNTPD,
796 OP_VMOVD,
797 OP_VMOVQ,
798 OP_VMOVDQA,
799 OP_VMOVDQU,
800 OP_VMOVNTDQ,
801 OP_VMOVNTDQA,
802/** @} */
803 OP_END_OF_OPCODES
804};
805AssertCompile(OP_LOCK == 7);
806/** @} */
807
808
809/** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1,
810 * DISOPCODE::fParam2, DISOPCODE::fParam3)
811 * @ingroup grp_dis
812 * @{
813 */
814
815/**
816 * @remarks Register order is important for translations!!
817 */
818enum OP_PARM
819{
820 OP_PARM_NONE,
821
822 OP_PARM_REG_EAX,
823 OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX,
824 OP_PARM_REG_ECX,
825 OP_PARM_REG_EDX,
826 OP_PARM_REG_EBX,
827 OP_PARM_REG_ESP,
828 OP_PARM_REG_EBP,
829 OP_PARM_REG_ESI,
830 OP_PARM_REG_EDI,
831 OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI,
832
833 OP_PARM_REG_ES,
834 OP_PARM_REG_SEG_START = OP_PARM_REG_ES,
835 OP_PARM_REG_CS,
836 OP_PARM_REG_SS,
837 OP_PARM_REG_DS,
838 OP_PARM_REG_FS,
839 OP_PARM_REG_GS,
840 OP_PARM_REG_SEG_END = OP_PARM_REG_GS,
841
842 OP_PARM_REG_AX,
843 OP_PARM_REG_GEN16_START = OP_PARM_REG_AX,
844 OP_PARM_REG_CX,
845 OP_PARM_REG_DX,
846 OP_PARM_REG_BX,
847 OP_PARM_REG_SP,
848 OP_PARM_REG_BP,
849 OP_PARM_REG_SI,
850 OP_PARM_REG_DI,
851 OP_PARM_REG_GEN16_END = OP_PARM_REG_DI,
852
853 OP_PARM_REG_AL,
854 OP_PARM_REG_GEN8_START = OP_PARM_REG_AL,
855 OP_PARM_REG_CL,
856 OP_PARM_REG_DL,
857 OP_PARM_REG_BL,
858 OP_PARM_REG_AH,
859 OP_PARM_REG_CH,
860 OP_PARM_REG_DH,
861 OP_PARM_REG_BH,
862 OP_PARM_REG_GEN8_END = OP_PARM_REG_BH,
863
864 OP_PARM_REGFP_0,
865 OP_PARM_REG_FP_START = OP_PARM_REGFP_0,
866 OP_PARM_REGFP_1,
867 OP_PARM_REGFP_2,
868 OP_PARM_REGFP_3,
869 OP_PARM_REGFP_4,
870 OP_PARM_REGFP_5,
871 OP_PARM_REGFP_6,
872 OP_PARM_REGFP_7,
873 OP_PARM_REG_FP_END = OP_PARM_REGFP_7,
874
875 OP_PARM_NTA,
876 OP_PARM_T0,
877 OP_PARM_T1,
878 OP_PARM_T2,
879 OP_PARM_1,
880
881 OP_PARM_REX,
882 OP_PARM_REX_START = OP_PARM_REX,
883 OP_PARM_REX_B,
884 OP_PARM_REX_X,
885 OP_PARM_REX_XB,
886 OP_PARM_REX_R,
887 OP_PARM_REX_RB,
888 OP_PARM_REX_RX,
889 OP_PARM_REX_RXB,
890 OP_PARM_REX_W,
891 OP_PARM_REX_WB,
892 OP_PARM_REX_WX,
893 OP_PARM_REX_WXB,
894 OP_PARM_REX_WR,
895 OP_PARM_REX_WRB,
896 OP_PARM_REX_WRX,
897 OP_PARM_REX_WRXB,
898
899 OP_PARM_REG_RAX,
900 OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX,
901 OP_PARM_REG_RCX,
902 OP_PARM_REG_RDX,
903 OP_PARM_REG_RBX,
904 OP_PARM_REG_RSP,
905 OP_PARM_REG_RBP,
906 OP_PARM_REG_RSI,
907 OP_PARM_REG_RDI,
908 OP_PARM_REG_R8,
909 OP_PARM_REG_R9,
910 OP_PARM_REG_R10,
911 OP_PARM_REG_R11,
912 OP_PARM_REG_R12,
913 OP_PARM_REG_R13,
914 OP_PARM_REG_R14,
915 OP_PARM_REG_R15,
916 OP_PARM_REG_GEN64_END = OP_PARM_REG_R15
917};
918
919
920/* 8-bit GRP aliases (for IEM). */
921#define OP_PARM_AL OP_PARM_REG_AL
922
923/* GPR aliases for op-size specified register sizes (for IEM). */
924#define OP_PARM_rAX OP_PARM_REG_EAX
925#define OP_PARM_rCX OP_PARM_REG_ECX
926#define OP_PARM_rDX OP_PARM_REG_EDX
927#define OP_PARM_rBX OP_PARM_REG_EBX
928#define OP_PARM_rSP OP_PARM_REG_ESP
929#define OP_PARM_rBP OP_PARM_REG_EBP
930#define OP_PARM_rSI OP_PARM_REG_ESI
931#define OP_PARM_rDI OP_PARM_REG_EDI
932
933/* SREG aliases (for IEM). */
934#define OP_PARM_ES OP_PARM_REG_ES
935#define OP_PARM_CS OP_PARM_REG_CS
936#define OP_PARM_SS OP_PARM_REG_SS
937#define OP_PARM_DS OP_PARM_REG_DS
938#define OP_PARM_FS OP_PARM_REG_FS
939#define OP_PARM_GS OP_PARM_REG_GS
940
941/*
942 * Note! We don't document anything here if we can help it, because it we love
943 * wasting other peoples time figuring out crypting crap. The new VEX
944 * stuff of course uphelds this vexing tradition. Aaaaaaaaaaaaaaaaaaarg!
945 */
946
947#define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0)
948#define OP_PARM_VSUBTYPE(a) ((unsigned)a & 0x01F)
949
950#define OP_PARM_A 0x100
951#define OP_PARM_VARIABLE OP_PARM_A
952#define OP_PARM_E 0x120
953#define OP_PARM_F 0x140
954#define OP_PARM_G 0x160
955#define OP_PARM_I 0x180
956#define OP_PARM_J 0x1A0
957#define OP_PARM_M 0x1C0
958#define OP_PARM_O 0x1E0
959#define OP_PARM_R 0x200
960#define OP_PARM_X 0x220
961#define OP_PARM_Y 0x240
962
963/* Grouped rare parameters for optimization purposes */
964#define IS_OP_PARM_RARE(a) ((a & 0xF00) >= 0x300)
965#define OP_PARM_C 0x300 /* control register */
966#define OP_PARM_D 0x320 /* debug register */
967#define OP_PARM_S 0x340 /* segment register */
968#define OP_PARM_T 0x360 /* test register */
969#define OP_PARM_Q 0x380
970#define OP_PARM_P 0x3A0 /* mmx register */
971#define OP_PARM_W 0x3C0 /* xmm register */
972#define OP_PARM_V 0x3E0
973#define OP_PARM_U 0x400 /* The R/M field of the ModR/M byte selects XMM/YMM register. */
974#define OP_PARM_B 0x420 /* VEX.vvvv field select general purpose register. */
975#define OP_PARM_H 0x440
976#define OP_PARM_L 0x460
977
978#define OP_PARM_NONE 0
979#define OP_PARM_a 0x1 /**< Operand to bound instruction. */
980#define OP_PARM_b 0x2 /**< Byte (always). */
981#define OP_PARM_d 0x3 /**< Double word (always). */
982#define OP_PARM_dq 0x4 /**< Double quad word (always). */
983#define OP_PARM_p 0x5 /**< Far pointer (subject to opsize). */
984#define OP_PARM_pd 0x6 /**< 128-bit or 256-bit double precision floating point data. */
985#define OP_PARM_pi 0x7 /**< Quad word MMX register. */
986#define OP_PARM_ps 0x8 /**< 128-bit or 256-bit single precision floating point data. */
987#define OP_PARM_q 0xA /**< Quad word (always). */
988#define OP_PARM_s 0xB /**< Descriptor table size (SIDT/LIDT/SGDT/LGDT). */
989#define OP_PARM_sd 0xC /**< Scalar element of 128-bit double precision floating point data. */
990#define OP_PARM_ss 0xD /**< Scalar element of 128-bit single precision floating point data. */
991#define OP_PARM_v 0xE /**< Word, double word, or quad word depending on opsize. */
992#define OP_PARM_w 0xF /**< Word (always). */
993#define OP_PARM_x 0x10 /**< Double quad word (dq) or quad quad word (qq) depending on opsize. */
994#define OP_PARM_y 0x11 /**< Double word or quad word depending on opsize. */
995#define OP_PARM_z 0x12 /**< Word (16-bit opsize) or double word (32-bit/64-bit opsize). */
996#define OP_PARM_qq 0x13 /**< Quad quad word. */
997
998
999#define OP_PARM_Ap (OP_PARM_A+OP_PARM_p)
1000#define OP_PARM_By (OP_PARM_B+OP_PARM_y)
1001#define OP_PARM_Cd (OP_PARM_C+OP_PARM_d)
1002#define OP_PARM_Dd (OP_PARM_D+OP_PARM_d)
1003#define OP_PARM_Eb (OP_PARM_E+OP_PARM_b)
1004#define OP_PARM_Ed (OP_PARM_E+OP_PARM_d)
1005#define OP_PARM_Ep (OP_PARM_E+OP_PARM_p)
1006#define OP_PARM_Ev (OP_PARM_E+OP_PARM_v)
1007#define OP_PARM_Ew (OP_PARM_E+OP_PARM_w)
1008#define OP_PARM_Ey (OP_PARM_E+OP_PARM_y)
1009#define OP_PARM_Fv (OP_PARM_F+OP_PARM_v)
1010#define OP_PARM_Gb (OP_PARM_G+OP_PARM_b)
1011#define OP_PARM_Gd (OP_PARM_G+OP_PARM_d)
1012#define OP_PARM_Gv (OP_PARM_G+OP_PARM_v)
1013#define OP_PARM_Gw (OP_PARM_G+OP_PARM_w)
1014#define OP_PARM_Gy (OP_PARM_G+OP_PARM_y)
1015#define OP_PARM_Hq (OP_PARM_H+OP_PARM_q)
1016#define OP_PARM_Hps (OP_PARM_H+OP_PARM_ps)
1017#define OP_PARM_Hpd (OP_PARM_H+OP_PARM_pd)
1018#define OP_PARM_Hdq (OP_PARM_H+OP_PARM_dq)
1019#define OP_PARM_Hqq (OP_PARM_H+OP_PARM_qq)
1020#define OP_PARM_Hsd (OP_PARM_H+OP_PARM_sd)
1021#define OP_PARM_Hss (OP_PARM_H+OP_PARM_ss)
1022#define OP_PARM_Hx (OP_PARM_H+OP_PARM_x)
1023#define OP_PARM_Ib (OP_PARM_I+OP_PARM_b)
1024#define OP_PARM_Id (OP_PARM_I+OP_PARM_d)
1025#define OP_PARM_Iq (OP_PARM_I+OP_PARM_q)
1026#define OP_PARM_Iw (OP_PARM_I+OP_PARM_w)
1027#define OP_PARM_Iv (OP_PARM_I+OP_PARM_v)
1028#define OP_PARM_Iz (OP_PARM_I+OP_PARM_z)
1029#define OP_PARM_Jb (OP_PARM_J+OP_PARM_b)
1030#define OP_PARM_Jv (OP_PARM_J+OP_PARM_v)
1031#define OP_PARM_Ma (OP_PARM_M+OP_PARM_a)
1032#define OP_PARM_Mb (OP_PARM_M+OP_PARM_b)
1033#define OP_PARM_Mw (OP_PARM_M+OP_PARM_w)
1034#define OP_PARM_Md (OP_PARM_M+OP_PARM_d)
1035#define OP_PARM_Mp (OP_PARM_M+OP_PARM_p)
1036#define OP_PARM_Mq (OP_PARM_M+OP_PARM_q)
1037#define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq)
1038#define OP_PARM_Ms (OP_PARM_M+OP_PARM_s)
1039#define OP_PARM_Mx (OP_PARM_M+OP_PARM_x)
1040#define OP_PARM_My (OP_PARM_M+OP_PARM_y)
1041#define OP_PARM_Mps (OP_PARM_M+OP_PARM_ps)
1042#define OP_PARM_Mpd (OP_PARM_M+OP_PARM_pd)
1043#define OP_PARM_Ob (OP_PARM_O+OP_PARM_b)
1044#define OP_PARM_Ov (OP_PARM_O+OP_PARM_v)
1045#define OP_PARM_Pq (OP_PARM_P+OP_PARM_q)
1046#define OP_PARM_Pd (OP_PARM_P+OP_PARM_d)
1047#define OP_PARM_Qd (OP_PARM_Q+OP_PARM_d)
1048#define OP_PARM_Qq (OP_PARM_Q+OP_PARM_q)
1049#define OP_PARM_Rd (OP_PARM_R+OP_PARM_d)
1050#define OP_PARM_Rw (OP_PARM_R+OP_PARM_w)
1051#define OP_PARM_Ry (OP_PARM_R+OP_PARM_y)
1052#define OP_PARM_Sw (OP_PARM_S+OP_PARM_w)
1053#define OP_PARM_Td (OP_PARM_T+OP_PARM_d)
1054#define OP_PARM_Ux (OP_PARM_U+OP_PARM_x)
1055#define OP_PARM_Vq (OP_PARM_V+OP_PARM_q)
1056#define OP_PARM_Vx (OP_PARM_V+OP_PARM_x)
1057#define OP_PARM_Vy (OP_PARM_V+OP_PARM_y)
1058#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1059//#define OP_PARM_Ws (OP_PARM_W+OP_PARM_s) - wtf? Same as lgdt (OP_PARM_Ms)?
1060#define OP_PARM_Wx (OP_PARM_W+OP_PARM_x)
1061#define OP_PARM_Xb (OP_PARM_X+OP_PARM_b)
1062#define OP_PARM_Xv (OP_PARM_X+OP_PARM_v)
1063#define OP_PARM_Yb (OP_PARM_Y+OP_PARM_b)
1064#define OP_PARM_Yv (OP_PARM_Y+OP_PARM_v)
1065
1066#define OP_PARM_Vps (OP_PARM_V+OP_PARM_ps)
1067#define OP_PARM_Vss (OP_PARM_V+OP_PARM_ss)
1068#define OP_PARM_Vpd (OP_PARM_V+OP_PARM_pd)
1069#define OP_PARM_Vdq (OP_PARM_V+OP_PARM_dq)
1070#define OP_PARM_Wps (OP_PARM_W+OP_PARM_ps)
1071#define OP_PARM_Wpd (OP_PARM_W+OP_PARM_pd)
1072#define OP_PARM_Wss (OP_PARM_W+OP_PARM_ss)
1073#define OP_PARM_Ww (OP_PARM_W+OP_PARM_w)
1074#define OP_PARM_Wd (OP_PARM_W+OP_PARM_d)
1075#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1076#define OP_PARM_Wdq (OP_PARM_W+OP_PARM_dq)
1077#define OP_PARM_Wqq (OP_PARM_W+OP_PARM_qq)
1078#define OP_PARM_Ppi (OP_PARM_P+OP_PARM_pi)
1079#define OP_PARM_Qpi (OP_PARM_Q+OP_PARM_pi)
1080#define OP_PARM_Qdq (OP_PARM_Q+OP_PARM_dq)
1081#define OP_PARM_Vsd (OP_PARM_V+OP_PARM_sd)
1082#define OP_PARM_Wsd (OP_PARM_W+OP_PARM_sd)
1083#define OP_PARM_Vqq (OP_PARM_V+OP_PARM_qq)
1084#define OP_PARM_Pdq (OP_PARM_P+OP_PARM_dq)
1085#define OP_PARM_Ups (OP_PARM_U+OP_PARM_ps)
1086#define OP_PARM_Upd (OP_PARM_U+OP_PARM_pd)
1087#define OP_PARM_Udq (OP_PARM_U+OP_PARM_dq)
1088#define OP_PARM_Lx (OP_PARM_L+OP_PARM_x)
1089
1090/* For making IEM / bs3-cpu-generated-1 happy: */
1091#define OP_PARM_Ed_WO OP_PARM_Ed /**< Annotates write only operand. */
1092#define OP_PARM_Eq (OP_PARM_E+OP_PARM_q)
1093#define OP_PARM_Eq_WO OP_PARM_Eq /**< Annotates write only operand. */
1094#define OP_PARM_Gv_RO OP_PARM_Gv /**< Annotates read only first operand (default is readwrite). */
1095#define OP_PARM_HssHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:32]. */
1096#define OP_PARM_HsdHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:64]. */
1097#define OP_PARM_HqHi OP_PARM_Hx /**< Register referenced by VEX.vvvv, bits [127:64]. */
1098#define OP_PARM_M_RO OP_PARM_M /**< Annotates read only memory of variable operand size (xrstor). */
1099#define OP_PARM_M_RW OP_PARM_M /**< Annotates read-write memory of variable operand size (xsave). */
1100#define OP_PARM_Mb_RO OP_PARM_Mb /**< Annotates read only memory byte operand. */
1101#define OP_PARM_Md_RO OP_PARM_Md /**< Annotates read only memory operand. */
1102#define OP_PARM_Md_WO OP_PARM_Md /**< Annotates write only memory operand. */
1103#define OP_PARM_Mdq_WO OP_PARM_Mdq /**< Annotates write only memory operand. */
1104#define OP_PARM_Mq_WO OP_PARM_Mq /**< Annotates write only memory quad word operand. */
1105#define OP_PARM_Mps_WO OP_PARM_Mps /**< Annotates write only memory operand. */
1106#define OP_PARM_Mpd_WO OP_PARM_Mpd /**< Annotates write only memory operand. */
1107#define OP_PARM_Mx_WO OP_PARM_Mx /**< Annotates write only memory operand. */
1108#define OP_PARM_PdZx_WO OP_PARM_Pd /**< Annotates write only operand and zero extends to 64-bit. */
1109#define OP_PARM_Pq_WO OP_PARM_Pq /**< Annotates write only operand. */
1110#define OP_PARM_Qq_WO OP_PARM_Qq /**< Annotates write only operand. */
1111#define OP_PARM_Nq OP_PARM_Qq /**< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. */
1112#define OP_PARM_Uq (OP_PARM_U+OP_PARM_q)
1113#define OP_PARM_UqHi (OP_PARM_U+OP_PARM_dq)
1114#define OP_PARM_Uss (OP_PARM_U+OP_PARM_ss)
1115#define OP_PARM_Uss_WO OP_PARM_Uss /**< Annotates write only operand. */
1116#define OP_PARM_Usd (OP_PARM_U+OP_PARM_sd)
1117#define OP_PARM_Usd_WO OP_PARM_Usd /**< Annotates write only operand. */
1118#define OP_PARM_Vd (OP_PARM_V+OP_PARM_d)
1119#define OP_PARM_Vd_WO OP_PARM_Vd /**< Annotates write only operand. */
1120#define OP_PARM_VdZx_WO OP_PARM_Vd /**< Annotates that the registers get their upper bits cleared */
1121#define OP_PARM_Vdq_WO OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are accessed. */
1122#define OP_PARM_Vpd_WO OP_PARM_Vpd /**< Annotates write only operand. */
1123#define OP_PARM_Vps_WO OP_PARM_Vps /**< Annotates write only operand. */
1124#define OP_PARM_Vq_WO OP_PARM_Vq /**< Annotates write only operand. */
1125#define OP_PARM_VqHi OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are accessed. */
1126#define OP_PARM_VqHi_WO OP_PARM_Vdq /**< Annotates that only YMM/XMM[127:64] are written. */
1127#define OP_PARM_VqZx_WO OP_PARM_Vq /**< Annotates that the registers get their upper bits cleared */
1128#define OP_PARM_VsdZx_WO OP_PARM_Vsd /**< Annotates that the registers get their upper bits cleared. */
1129#define OP_PARM_VssZx_WO OP_PARM_Vss /**< Annotates that the registers get their upper bits cleared. */
1130#define OP_PARM_Vss_WO OP_PARM_Vss /**< Annotates write only operand. */
1131#define OP_PARM_Vsd_WO OP_PARM_Vsd /**< Annotates write only operand. */
1132#define OP_PARM_Vx_WO OP_PARM_Vx /**< Annotates write only operand. */
1133#define OP_PARM_Wpd_WO OP_PARM_Wpd /**< Annotates write only operand. */
1134#define OP_PARM_Wps_WO OP_PARM_Wps /**< Annotates write only operand. */
1135#define OP_PARM_Wq_WO OP_PARM_Wq /**< Annotates write only operand. */
1136#define OP_PARM_WqZxReg_WO OP_PARM_Wq /**< Annotates that register targets get their upper bits cleared. */
1137#define OP_PARM_Wss_WO OP_PARM_Wss /**< Annotates write only operand. */
1138#define OP_PARM_Wsd_WO OP_PARM_Wsd /**< Annotates write only operand. */
1139#define OP_PARM_Wx_WO OP_PARM_Wx /**< Annotates write only operand. */
1140
1141/** @} */
1142
1143#endif
1144
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