[1] | 1 | /** @file
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| 2 | * DIS - The VirtualBox Disassembler.
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| 3 | */
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| 4 |
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| 5 | /*
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[8155] | 6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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[1] | 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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[8155] | 24 | *
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| 25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 27 | * additional information or have any questions.
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[1] | 28 | */
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| 29 |
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[3632] | 30 | #ifndef ___VBox_disasm_h
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| 31 | #define ___VBox_disasm_h
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[1] | 32 |
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| 33 | #include <VBox/cdefs.h>
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| 34 | #include <VBox/types.h>
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[1829] | 35 | #include <VBox/disopcode.h>
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[1] | 36 |
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[3783] | 37 | #if defined(__L4ENV__)
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[1] | 38 | #include <setjmp.h>
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| 39 | #endif
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| 40 |
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[20374] | 41 | RT_C_DECLS_BEGIN
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[1] | 42 |
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| 43 |
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| 44 | /** CPU mode flags (DISCPUSTATE::mode).
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| 45 | * @{
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| 46 | */
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[4953] | 47 | typedef enum
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| 48 | {
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| 49 | CPUMODE_16BIT = 1,
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| 50 | CPUMODE_32BIT = 2,
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[7015] | 51 | CPUMODE_64BIT = 3,
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| 52 | /** hack forcing the size of the enum to 32-bits. */
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| 53 | CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
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[4953] | 54 | } DISCPUMODE;
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[1] | 55 | /** @} */
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| 56 |
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| 57 | /** Prefix byte flags
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| 58 | * @{
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| 59 | */
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| 60 | #define PREFIX_NONE 0
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| 61 | /** non-default address size. */
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[8299] | 62 | #define PREFIX_ADDRSIZE RT_BIT(0)
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[1] | 63 | /** non-default operand size. */
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[8299] | 64 | #define PREFIX_OPSIZE RT_BIT(1)
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[1] | 65 | /** lock prefix. */
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[8299] | 66 | #define PREFIX_LOCK RT_BIT(2)
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[1] | 67 | /** segment prefix. */
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[8299] | 68 | #define PREFIX_SEG RT_BIT(3)
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[1] | 69 | /** rep(e) prefix (not a prefix, but we'll treat is as one). */
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[8299] | 70 | #define PREFIX_REP RT_BIT(4)
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[1] | 71 | /** rep(e) prefix (not a prefix, but we'll treat is as one). */
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[8299] | 72 | #define PREFIX_REPNE RT_BIT(5)
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[7000] | 73 | /** REX prefix (64 bits) */
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[8299] | 74 | #define PREFIX_REX RT_BIT(6)
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[1] | 75 | /** @} */
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| 76 |
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[7134] | 77 | /** 64 bits prefix byte flags
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[7000] | 78 | * @{
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| 79 | */
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[8299] | 80 | #define PREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
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| 81 | #define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
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| 82 | #define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
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| 83 | #define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
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| 84 | #define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
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| 85 | #define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
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| 86 | #define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
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| 87 | #define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
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| 88 | #define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
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| 89 | #define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
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| 90 | #define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
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| 91 | #define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
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| 92 | #define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
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| 93 | #define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
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| 94 | #define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
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| 95 | #define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
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| 96 | #define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
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[7000] | 97 | /** @} */
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| 98 |
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[1] | 99 | /**
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| 100 | * Operand type.
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| 101 | */
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[7000] | 102 | #define OPTYPE_INVALID RT_BIT(0)
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| 103 | #define OPTYPE_HARMLESS RT_BIT(1)
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| 104 | #define OPTYPE_CONTROLFLOW RT_BIT(2)
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| 105 | #define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
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| 106 | #define OPTYPE_DANGEROUS RT_BIT(4)
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| 107 | #define OPTYPE_PORTIO RT_BIT(5)
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| 108 | #define OPTYPE_PRIVILEGED RT_BIT(6)
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| 109 | #define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
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| 110 | #define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
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| 111 | #define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
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| 112 | #define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
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| 113 | #define OPTYPE_INTERRUPT RT_BIT(11)
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| 114 | #define OPTYPE_ILLEGAL RT_BIT(12)
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| 115 | #define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
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| 116 | #define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
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| 117 | #define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
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| 118 | #define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
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| 119 | #define OPTYPE_PORTIO_READ RT_BIT(17)
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| 120 | #define OPTYPE_PORTIO_WRITE RT_BIT(18)
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| 121 | #define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
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| 122 | #define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
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| 123 | #define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
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[7134] | 124 | #define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
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[8357] | 125 | #define OPTYPE_REXB_EXTENDS_OPREG RT_BIT(23) /**< REX.B extends the register field in the opcode byte */
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[21187] | 126 | #define OPTYPE_MOD_FIXED_11 RT_BIT(24) /**< modrm.mod is always 11b */
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| 127 | #define OPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
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[7000] | 128 | #define OPTYPE_ALL (0xffffffff)
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[1] | 129 |
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| 130 | /** Parameter usage flags.
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| 131 | * @{
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| 132 | */
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[8149] | 133 | #define USE_BASE RT_BIT_64(0)
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| 134 | #define USE_INDEX RT_BIT_64(1)
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| 135 | #define USE_SCALE RT_BIT_64(2)
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| 136 | #define USE_REG_GEN8 RT_BIT_64(3)
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| 137 | #define USE_REG_GEN16 RT_BIT_64(4)
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| 138 | #define USE_REG_GEN32 RT_BIT_64(5)
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| 139 | #define USE_REG_GEN64 RT_BIT_64(6)
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| 140 | #define USE_REG_FP RT_BIT_64(7)
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| 141 | #define USE_REG_MMX RT_BIT_64(8)
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| 142 | #define USE_REG_XMM RT_BIT_64(9)
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| 143 | #define USE_REG_CR RT_BIT_64(10)
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| 144 | #define USE_REG_DBG RT_BIT_64(11)
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| 145 | #define USE_REG_SEG RT_BIT_64(12)
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| 146 | #define USE_REG_TEST RT_BIT_64(13)
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| 147 | #define USE_DISPLACEMENT8 RT_BIT_64(14)
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| 148 | #define USE_DISPLACEMENT16 RT_BIT_64(15)
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| 149 | #define USE_DISPLACEMENT32 RT_BIT_64(16)
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[8336] | 150 | #define USE_DISPLACEMENT64 RT_BIT_64(17)
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[8352] | 151 | #define USE_RIPDISPLACEMENT32 RT_BIT_64(18)
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| 152 | #define USE_IMMEDIATE8 RT_BIT_64(19)
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| 153 | #define USE_IMMEDIATE8_REL RT_BIT_64(20)
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| 154 | #define USE_IMMEDIATE16 RT_BIT_64(21)
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| 155 | #define USE_IMMEDIATE16_REL RT_BIT_64(22)
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| 156 | #define USE_IMMEDIATE32 RT_BIT_64(23)
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| 157 | #define USE_IMMEDIATE32_REL RT_BIT_64(24)
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| 158 | #define USE_IMMEDIATE64 RT_BIT_64(25)
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[8999] | 159 | #define USE_IMMEDIATE64_REL RT_BIT_64(26)
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| 160 | #define USE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
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| 161 | #define USE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
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| 162 | #define USE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
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| 163 | #define USE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
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[1] | 164 | /** DS:ESI */
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[8999] | 165 | #define USE_POINTER_DS_BASED RT_BIT_64(31)
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[1] | 166 | /** ES:EDI */
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[8999] | 167 | #define USE_POINTER_ES_BASED RT_BIT_64(32)
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| 168 | #define USE_IMMEDIATE16_SX8 RT_BIT_64(33)
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| 169 | #define USE_IMMEDIATE32_SX8 RT_BIT_64(34)
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[10273] | 170 | #define USE_IMMEDIATE64_SX8 RT_BIT_64(36)
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[1] | 171 |
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[10273] | 172 | #define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE64_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8|USE_IMMEDIATE64_SX8)
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[1] | 173 |
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[9761] | 174 | #define DIS_IS_EFFECTIVE_ADDR(flags) !!((flags) & (USE_BASE|USE_INDEX|USE_DISPLACEMENT32|USE_DISPLACEMENT64|USE_DISPLACEMENT16|USE_DISPLACEMENT8|USE_RIPDISPLACEMENT32))
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[1] | 175 | /** @} */
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| 176 |
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[8142] | 177 | /** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
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| 178 | * @{
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| 179 | */
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| 180 | #define USE_REG_RAX 0
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| 181 | #define USE_REG_RCX 1
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| 182 | #define USE_REG_RDX 2
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| 183 | #define USE_REG_RBX 3
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| 184 | #define USE_REG_RSP 4
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| 185 | #define USE_REG_RBP 5
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| 186 | #define USE_REG_RSI 6
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| 187 | #define USE_REG_RDI 7
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| 188 | #define USE_REG_R8 8
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| 189 | #define USE_REG_R9 9
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| 190 | #define USE_REG_R10 10
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| 191 | #define USE_REG_R11 11
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| 192 | #define USE_REG_R12 12
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| 193 | #define USE_REG_R13 13
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| 194 | #define USE_REG_R14 14
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| 195 | #define USE_REG_R15 15
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| 196 | /** @} */
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| 197 |
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[9919] | 198 | /** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"}
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[1] | 199 | * @{
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| 200 | */
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| 201 | #define USE_REG_EAX 0
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| 202 | #define USE_REG_ECX 1
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| 203 | #define USE_REG_EDX 2
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| 204 | #define USE_REG_EBX 3
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| 205 | #define USE_REG_ESP 4
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| 206 | #define USE_REG_EBP 5
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| 207 | #define USE_REG_ESI 6
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| 208 | #define USE_REG_EDI 7
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[9924] | 209 | #define USE_REG_R8D 8
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| 210 | #define USE_REG_R9D 9
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[9919] | 211 | #define USE_REG_R10D 10
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| 212 | #define USE_REG_R11D 11
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| 213 | #define USE_REG_R12D 12
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| 214 | #define USE_REG_R13D 13
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| 215 | #define USE_REG_R14D 14
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| 216 | #define USE_REG_R15D 15
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| 217 |
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[1] | 218 | /** @} */
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[9919] | 219 | /** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"}
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[1] | 220 | * @{
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| 221 | */
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| 222 | #define USE_REG_AX 0
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| 223 | #define USE_REG_CX 1
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| 224 | #define USE_REG_DX 2
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| 225 | #define USE_REG_BX 3
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| 226 | #define USE_REG_SP 4
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| 227 | #define USE_REG_BP 5
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| 228 | #define USE_REG_SI 6
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| 229 | #define USE_REG_DI 7
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[9924] | 230 | #define USE_REG_R8W 8
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| 231 | #define USE_REG_R9W 9
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[9919] | 232 | #define USE_REG_R10W 10
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| 233 | #define USE_REG_R11W 11
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| 234 | #define USE_REG_R12W 12
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| 235 | #define USE_REG_R13W 13
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| 236 | #define USE_REG_R14W 14
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| 237 | #define USE_REG_R15W 15
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[1] | 238 | /** @} */
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| 239 |
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[9921] | 240 | /** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"}
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[1] | 241 | * @{
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| 242 | */
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| 243 | #define USE_REG_AL 0
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| 244 | #define USE_REG_CL 1
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| 245 | #define USE_REG_DL 2
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| 246 | #define USE_REG_BL 3
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| 247 | #define USE_REG_AH 4
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| 248 | #define USE_REG_CH 5
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| 249 | #define USE_REG_DH 6
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| 250 | #define USE_REG_BH 7
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[9919] | 251 | #define USE_REG_R8B 8
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| 252 | #define USE_REG_R9B 9
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| 253 | #define USE_REG_R10B 10
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| 254 | #define USE_REG_R11B 11
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| 255 | #define USE_REG_R12B 12
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| 256 | #define USE_REG_R13B 13
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| 257 | #define USE_REG_R14B 14
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| 258 | #define USE_REG_R15B 15
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[9921] | 259 | #define USE_REG_SPL 16
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| 260 | #define USE_REG_BPL 17
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| 261 | #define USE_REG_SIL 18
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| 262 | #define USE_REG_DIL 19
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[9919] | 263 |
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[1] | 264 | /** @} */
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| 265 |
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| 266 | /** index in {ES, CS, SS, DS, FS, GS}
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| 267 | * @{
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| 268 | */
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[9675] | 269 | typedef enum
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| 270 | {
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| 271 | DIS_SELREG_ES = 0,
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| 272 | DIS_SELREG_CS = 1,
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| 273 | DIS_SELREG_SS = 2,
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| 274 | DIS_SELREG_DS = 3,
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| 275 | DIS_SELREG_FS = 4,
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| 276 | DIS_SELREG_GS = 5,
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| 277 | /** The usual 32-bit paranoia. */
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| 278 | DIS_SEGREG_32BIT_HACK = 0x7fffffff
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| 279 | } DIS_SELREG;
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[1] | 280 | /** @} */
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| 281 |
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| 282 | #define USE_REG_FP0 0
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| 283 | #define USE_REG_FP1 1
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| 284 | #define USE_REG_FP2 2
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| 285 | #define USE_REG_FP3 3
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| 286 | #define USE_REG_FP4 4
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| 287 | #define USE_REG_FP5 5
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| 288 | #define USE_REG_FP6 6
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| 289 | #define USE_REG_FP7 7
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| 290 |
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| 291 | #define USE_REG_CR0 0
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| 292 | #define USE_REG_CR1 1
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| 293 | #define USE_REG_CR2 2
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| 294 | #define USE_REG_CR3 3
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| 295 | #define USE_REG_CR4 4
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[10107] | 296 | #define USE_REG_CR8 8
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[1] | 297 |
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| 298 | #define USE_REG_DR0 0
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| 299 | #define USE_REG_DR1 1
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| 300 | #define USE_REG_DR2 2
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| 301 | #define USE_REG_DR3 3
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| 302 | #define USE_REG_DR4 4
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| 303 | #define USE_REG_DR5 5
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| 304 | #define USE_REG_DR6 6
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| 305 | #define USE_REG_DR7 7
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| 306 |
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| 307 | #define USE_REG_MMX0 0
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| 308 | #define USE_REG_MMX1 1
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| 309 | #define USE_REG_MMX2 2
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| 310 | #define USE_REG_MMX3 3
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| 311 | #define USE_REG_MMX4 4
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| 312 | #define USE_REG_MMX5 5
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| 313 | #define USE_REG_MMX6 6
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| 314 | #define USE_REG_MMX7 7
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| 315 |
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| 316 | #define USE_REG_XMM0 0
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| 317 | #define USE_REG_XMM1 1
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| 318 | #define USE_REG_XMM2 2
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| 319 | #define USE_REG_XMM3 3
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| 320 | #define USE_REG_XMM4 4
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| 321 | #define USE_REG_XMM5 5
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| 322 | #define USE_REG_XMM6 6
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| 323 | #define USE_REG_XMM7 7
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| 324 |
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| 325 | /** Used by DISQueryParamVal & EMIQueryParamVal
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| 326 | * @{
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| 327 | */
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[5605] | 328 | #define PARAM_VAL8 RT_BIT(0)
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| 329 | #define PARAM_VAL16 RT_BIT(1)
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| 330 | #define PARAM_VAL32 RT_BIT(2)
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| 331 | #define PARAM_VAL64 RT_BIT(3)
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| 332 | #define PARAM_VALFARPTR16 RT_BIT(4)
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| 333 | #define PARAM_VALFARPTR32 RT_BIT(5)
|
---|
[1] | 334 |
|
---|
| 335 | #define PARMTYPE_REGISTER 1
|
---|
| 336 | #define PARMTYPE_ADDRESS 2
|
---|
| 337 | #define PARMTYPE_IMMEDIATE 3
|
---|
| 338 |
|
---|
| 339 | typedef struct
|
---|
| 340 | {
|
---|
| 341 | uint32_t type;
|
---|
| 342 | uint32_t size;
|
---|
[8149] | 343 | uint64_t flags;
|
---|
[1] | 344 |
|
---|
| 345 | union
|
---|
| 346 | {
|
---|
| 347 | uint8_t val8;
|
---|
| 348 | uint16_t val16;
|
---|
| 349 | uint32_t val32;
|
---|
| 350 | uint64_t val64;
|
---|
| 351 |
|
---|
| 352 | struct
|
---|
| 353 | {
|
---|
| 354 | uint16_t sel;
|
---|
| 355 | uint32_t offset;
|
---|
| 356 | } farptr;
|
---|
| 357 | } val;
|
---|
| 358 |
|
---|
| 359 | } OP_PARAMVAL;
|
---|
| 360 | /** Pointer to opcode parameter value. */
|
---|
| 361 | typedef OP_PARAMVAL *POP_PARAMVAL;
|
---|
| 362 |
|
---|
| 363 | typedef enum
|
---|
| 364 | {
|
---|
| 365 | PARAM_DEST,
|
---|
| 366 | PARAM_SOURCE
|
---|
| 367 | } PARAM_TYPE;
|
---|
| 368 |
|
---|
| 369 | /** @} */
|
---|
| 370 |
|
---|
| 371 | /**
|
---|
| 372 | * Operand Parameter.
|
---|
| 373 | */
|
---|
| 374 | typedef struct _OP_PARAMETER
|
---|
| 375 | {
|
---|
[9266] | 376 | /** @todo switch param and parval and move disp64 and flags up here with the other 64-bit vars to get more natural alignment and save space. */
|
---|
[1] | 377 | int param;
|
---|
| 378 | uint64_t parval;
|
---|
[9266] | 379 | #ifndef DIS_SEPARATE_FORMATTER
|
---|
[1] | 380 | char szParam[32];
|
---|
[9266] | 381 | #endif
|
---|
[1] | 382 |
|
---|
| 383 | int32_t disp8, disp16, disp32;
|
---|
| 384 | uint32_t size;
|
---|
| 385 |
|
---|
[8336] | 386 | int64_t disp64;
|
---|
[8149] | 387 | uint64_t flags;
|
---|
| 388 |
|
---|
[1] | 389 | union
|
---|
| 390 | {
|
---|
[8234] | 391 | uint32_t reg_gen;
|
---|
[1] | 392 | /** ST(0) - ST(7) */
|
---|
| 393 | uint32_t reg_fp;
|
---|
| 394 | /** MMX0 - MMX7 */
|
---|
| 395 | uint32_t reg_mmx;
|
---|
| 396 | /** XMM0 - XMM7 */
|
---|
| 397 | uint32_t reg_xmm;
|
---|
| 398 | /** {ES, CS, SS, DS, FS, GS} */
|
---|
[9675] | 399 | DIS_SELREG reg_seg;
|
---|
[1] | 400 | /** TR0-TR7 (?) */
|
---|
| 401 | uint32_t reg_test;
|
---|
| 402 | /** CR0-CR4 */
|
---|
[8228] | 403 | uint32_t reg_ctrl;
|
---|
[1] | 404 | /** DR0-DR7 */
|
---|
| 405 | uint32_t reg_dbg;
|
---|
| 406 | } base;
|
---|
| 407 | union
|
---|
| 408 | {
|
---|
| 409 | uint32_t reg_gen;
|
---|
| 410 | } index;
|
---|
| 411 |
|
---|
| 412 | /** 2, 4 or 8. */
|
---|
| 413 | uint32_t scale;
|
---|
| 414 |
|
---|
| 415 | } OP_PARAMETER;
|
---|
| 416 | /** Pointer to opcode parameter. */
|
---|
| 417 | typedef OP_PARAMETER *POP_PARAMETER;
|
---|
| 418 | /** Pointer to opcode parameter. */
|
---|
| 419 | typedef const OP_PARAMETER *PCOP_PARAMETER;
|
---|
| 420 |
|
---|
| 421 |
|
---|
| 422 | struct _OPCODE;
|
---|
| 423 | /** Pointer to opcode. */
|
---|
| 424 | typedef struct _OPCODE *POPCODE;
|
---|
| 425 | /** Pointer to const opcode. */
|
---|
| 426 | typedef const struct _OPCODE *PCOPCODE;
|
---|
| 427 |
|
---|
[9216] | 428 | typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, unsigned size, void *pvUserdata);
|
---|
[1] | 429 | typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
|
---|
| 430 |
|
---|
| 431 | /* forward decl */
|
---|
| 432 | struct _DISCPUSTATE;
|
---|
| 433 | /** Pointer to the disassembler CPU state. */
|
---|
| 434 | typedef struct _DISCPUSTATE *PDISCPUSTATE;
|
---|
| 435 |
|
---|
| 436 | /** Parser callback.
|
---|
| 437 | * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
|
---|
[4953] | 438 | typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
|
---|
[1] | 439 | typedef FNDISPARSE *PFNDISPARSE;
|
---|
| 440 |
|
---|
| 441 | typedef struct _DISCPUSTATE
|
---|
| 442 | {
|
---|
| 443 | /* Global setting */
|
---|
[7015] | 444 | DISCPUMODE mode;
|
---|
[1] | 445 |
|
---|
| 446 | /* Per instruction prefix settings */
|
---|
| 447 | uint32_t prefix;
|
---|
| 448 | /** segment prefix value. */
|
---|
[9675] | 449 | DIS_SELREG enmPrefixSeg;
|
---|
[7000] | 450 | /** rex prefix value (64 bits only */
|
---|
| 451 | uint32_t prefix_rex;
|
---|
[1] | 452 | /** addressing mode (16 or 32 bits). (CPUMODE_*) */
|
---|
[7015] | 453 | DISCPUMODE addrmode;
|
---|
[1] | 454 | /** operand mode (16 or 32 bits). (CPUMODE_*) */
|
---|
[7015] | 455 | DISCPUMODE opmode;
|
---|
[1] | 456 |
|
---|
| 457 | OP_PARAMETER param1;
|
---|
| 458 | OP_PARAMETER param2;
|
---|
| 459 | OP_PARAMETER param3;
|
---|
| 460 |
|
---|
[8333] | 461 | /** ModRM fields. */
|
---|
| 462 | union
|
---|
| 463 | {
|
---|
| 464 | /* Bitfield view */
|
---|
| 465 | struct
|
---|
| 466 | {
|
---|
| 467 | unsigned Rm : 4;
|
---|
| 468 | unsigned Reg : 4;
|
---|
| 469 | unsigned Mod : 2;
|
---|
| 470 | } Bits;
|
---|
| 471 | /* unsigned view */
|
---|
| 472 | unsigned u;
|
---|
| 473 | } ModRM;
|
---|
[1] | 474 |
|
---|
[8333] | 475 | /** SIB fields. */
|
---|
| 476 | union
|
---|
| 477 | {
|
---|
| 478 | /* Bitfield view */
|
---|
| 479 | struct
|
---|
| 480 | {
|
---|
| 481 | unsigned Base : 4;
|
---|
| 482 | unsigned Index : 4;
|
---|
| 483 | unsigned Scale : 2;
|
---|
| 484 | } Bits;
|
---|
| 485 | /* unsigned view */
|
---|
| 486 | unsigned u;
|
---|
| 487 | } SIB;
|
---|
| 488 |
|
---|
[1] | 489 | int32_t disp;
|
---|
| 490 |
|
---|
| 491 | /** First opcode byte of instruction. */
|
---|
| 492 | uint8_t opcode;
|
---|
| 493 | /** Last prefix byte (for SSE2 extension tables) */
|
---|
| 494 | uint8_t lastprefix;
|
---|
| 495 | RTUINTPTR opaddr;
|
---|
| 496 | uint32_t opsize;
|
---|
| 497 | #ifndef DIS_CORE_ONLY
|
---|
| 498 | /** Opcode format string for current instruction. */
|
---|
[2333] | 499 | const char *pszOpcode;
|
---|
[1] | 500 | #endif
|
---|
| 501 |
|
---|
| 502 | /** Internal: pointer to disassembly function table */
|
---|
| 503 | PFNDISPARSE *pfnDisasmFnTable;
|
---|
| 504 | /** Internal: instruction filter */
|
---|
| 505 | uint32_t uFilter;
|
---|
| 506 |
|
---|
| 507 | /** Pointer to the current instruction. */
|
---|
| 508 | PCOPCODE pCurInstr;
|
---|
| 509 |
|
---|
[4953] | 510 | void *apvUserData[3];
|
---|
[1] | 511 |
|
---|
| 512 | /** Optional read function */
|
---|
| 513 | PFN_DIS_READBYTES pfnReadBytes;
|
---|
| 514 | #ifdef __L4ENV__
|
---|
| 515 | jmp_buf *pJumpBuffer;
|
---|
| 516 | #endif /* __L4ENV__ */
|
---|
| 517 | } DISCPUSTATE;
|
---|
| 518 |
|
---|
[9266] | 519 | /** Pointer to a const disassembler CPU state. */
|
---|
| 520 | typedef DISCPUSTATE const *PCDISCPUSTATE;
|
---|
| 521 |
|
---|
[20530] | 522 | /** The storage padding sufficient to hold the largest DISCPUSTATE in all
|
---|
| 523 | * contexts (R3, R0 and RC). Used various places in the VMM internals. */
|
---|
[20537] | 524 | #define DISCPUSTATE_PADDING_SIZE (HC_ARCH_BITS == 64 ? 0x1a0 : 0x180)
|
---|
[20530] | 525 |
|
---|
[1] | 526 | /** Opcode. */
|
---|
| 527 | #pragma pack(4)
|
---|
| 528 | typedef struct _OPCODE
|
---|
| 529 | {
|
---|
| 530 | #ifndef DIS_CORE_ONLY
|
---|
[2333] | 531 | const char *pszOpcode;
|
---|
[1] | 532 | #endif
|
---|
| 533 | uint8_t idxParse1;
|
---|
| 534 | uint8_t idxParse2;
|
---|
| 535 | uint8_t idxParse3;
|
---|
| 536 | uint16_t opcode;
|
---|
| 537 | uint16_t param1;
|
---|
| 538 | uint16_t param2;
|
---|
| 539 | uint16_t param3;
|
---|
| 540 |
|
---|
[8357] | 541 | unsigned optype;
|
---|
[1] | 542 | } OPCODE;
|
---|
| 543 | #pragma pack()
|
---|
| 544 |
|
---|
| 545 |
|
---|
| 546 | /**
|
---|
| 547 | * Disassembles a code block.
|
---|
| 548 | *
|
---|
[4953] | 549 | * @returns VBox error code
|
---|
[1] | 550 | * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
|
---|
| 551 | * set correctly.
|
---|
| 552 | * @param pvCodeBlock Pointer to the strunction to disassemble.
|
---|
| 553 | * @param cbMax Maximum number of bytes to disassemble.
|
---|
| 554 | * @param pcbSize Where to store the size of the instruction.
|
---|
| 555 | * NULL is allowed.
|
---|
| 556 | *
|
---|
| 557 | *
|
---|
| 558 | * @todo Define output callback.
|
---|
| 559 | * @todo Using signed integers as sizes is a bit odd. There are still
|
---|
| 560 | * some GCC warnings about mixing signed and unsigend integers.
|
---|
| 561 | * @todo Need to extend this interface to include a code address so we
|
---|
| 562 | * can dissassemble GC code. Perhaps a new function is better...
|
---|
| 563 | * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
|
---|
| 564 | * This means *pcbSize >= cbMax sometimes.
|
---|
| 565 | */
|
---|
[4953] | 566 | DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
|
---|
[1] | 567 |
|
---|
| 568 | /**
|
---|
| 569 | * Disassembles one instruction
|
---|
| 570 | *
|
---|
[4953] | 571 | * @returns VBox error code
|
---|
[1] | 572 | * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
|
---|
| 573 | * set correctly.
|
---|
| 574 | * @param pu8Instruction Pointer to the instrunction to disassemble.
|
---|
| 575 | * @param u32EipOffset Offset to add to instruction address to get the real virtual address
|
---|
| 576 | * @param pcbSize Where to store the size of the instruction.
|
---|
| 577 | * NULL is allowed.
|
---|
| 578 | * @param pszOutput Storage for disassembled instruction
|
---|
| 579 | *
|
---|
| 580 | * @todo Define output callback.
|
---|
| 581 | */
|
---|
[4953] | 582 | DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
|
---|
[1] | 583 |
|
---|
| 584 | /**
|
---|
| 585 | * Disassembles one instruction
|
---|
| 586 | *
|
---|
[4953] | 587 | * @returns VBox error code
|
---|
[1] | 588 | * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
|
---|
| 589 | * set correctly.
|
---|
| 590 | * @param pu8Instruction Pointer to the strunction to disassemble.
|
---|
| 591 | * @param u32EipOffset Offset to add to instruction address to get the real virtual address
|
---|
| 592 | * @param pcbSize Where to store the size of the instruction.
|
---|
| 593 | * NULL is allowed.
|
---|
| 594 | * @param pszOutput Storage for disassembled instruction
|
---|
| 595 | * @param uFilter Instruction type filter
|
---|
| 596 | *
|
---|
| 597 | * @todo Define output callback.
|
---|
| 598 | */
|
---|
[4953] | 599 | DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
|
---|
| 600 | char *pszOutput, unsigned uFilter);
|
---|
[1] | 601 |
|
---|
| 602 | /**
|
---|
| 603 | * Parses one instruction.
|
---|
| 604 | * The result is found in pCpu.
|
---|
| 605 | *
|
---|
[4953] | 606 | * @returns VBox error code
|
---|
[1] | 607 | * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
|
---|
| 608 | * @param InstructionAddr Pointer to the instruction to parse.
|
---|
| 609 | * @param pcbInstruction Where to store the size of the instruction.
|
---|
| 610 | * NULL is allowed.
|
---|
| 611 | */
|
---|
[4953] | 612 | DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
|
---|
[1] | 613 |
|
---|
| 614 | /**
|
---|
| 615 | * Parses one guest instruction.
|
---|
[7015] | 616 | * The result is found in pCpu and pcbInstruction.
|
---|
[1] | 617 | *
|
---|
| 618 | * @returns VBox status code.
|
---|
| 619 | * @param InstructionAddr Address of the instruction to decode. What this means
|
---|
| 620 | * is left to the pfnReadBytes function.
|
---|
[7015] | 621 | * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
|
---|
[1] | 622 | * @param pfnReadBytes Callback for reading instruction bytes.
|
---|
[7015] | 623 | * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
|
---|
[1] | 624 | * @param pCpu Pointer to cpu structure. Will be initialized.
|
---|
| 625 | * @param pcbInstruction Where to store the size of the instruction.
|
---|
| 626 | * NULL is allowed.
|
---|
| 627 | */
|
---|
[7015] | 628 | DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
|
---|
[1] | 629 | PDISCPUSTATE pCpu, unsigned *pcbInstruction);
|
---|
| 630 |
|
---|
[9675] | 631 | DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
|
---|
| 632 | DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
|
---|
| 633 | DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
|
---|
[1] | 634 |
|
---|
| 635 | /**
|
---|
| 636 | * Returns the value of the parameter in pParam
|
---|
| 637 | *
|
---|
| 638 | * @returns VBox error code
|
---|
| 639 | * @param pCtx Exception structure pointer
|
---|
| 640 | * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
|
---|
| 641 | * set correctly.
|
---|
| 642 | * @param pParam Pointer to the parameter to parse
|
---|
| 643 | * @param pParamVal Pointer to parameter value (OUT)
|
---|
| 644 | * @param parmtype Parameter type
|
---|
| 645 | *
|
---|
| 646 | * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
|
---|
| 647 | *
|
---|
| 648 | */
|
---|
| 649 | DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
|
---|
[8149] | 650 | DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize);
|
---|
[1] | 651 |
|
---|
[10016] | 652 | DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
|
---|
| 653 | DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
|
---|
| 654 | DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
|
---|
| 655 | DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
|
---|
| 656 | DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal);
|
---|
| 657 | DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
|
---|
[8142] | 658 | DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
|
---|
| 659 | DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
|
---|
| 660 | DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
|
---|
| 661 | DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
|
---|
[9675] | 662 | DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val);
|
---|
[8142] | 663 | DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
|
---|
| 664 | DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
|
---|
| 665 | DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
|
---|
| 666 | DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
|
---|
[1] | 667 |
|
---|
[9266] | 668 |
|
---|
| 669 | /**
|
---|
| 670 | * Try resolve an address into a symbol name.
|
---|
| 671 | *
|
---|
| 672 | * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
|
---|
| 673 | *
|
---|
| 674 | * @returns VBox status code.
|
---|
| 675 | * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
|
---|
| 676 | * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
|
---|
| 677 | * content of pszBuf is truncated and zero terminated.
|
---|
| 678 | * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
|
---|
| 679 | *
|
---|
| 680 | * @param pCpu Pointer to the disassembler CPU state.
|
---|
| 681 | * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
|
---|
| 682 | * DIS_FMT_SEL_GET_REG to access this.
|
---|
| 683 | * @param uAddress The segment address.
|
---|
| 684 | * @param pszBuf Where to store the symbol name
|
---|
| 685 | * @param cchBuf The size of the buffer.
|
---|
| 686 | * @param poff If not a perfect match, then this is where the offset from the return
|
---|
| 687 | * symbol to the specified address is returned.
|
---|
| 688 | * @param pvUser The user argument.
|
---|
| 689 | */
|
---|
[9272] | 690 | typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
|
---|
[9266] | 691 | /** Pointer to a FNDISGETSYMBOL(). */
|
---|
| 692 | typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
|
---|
| 693 |
|
---|
| 694 | /**
|
---|
| 695 | * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
|
---|
| 696 | */
|
---|
| 697 | #define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
|
---|
| 698 |
|
---|
| 699 | /**
|
---|
| 700 | * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
|
---|
| 701 | * @returns Selector value.
|
---|
| 702 | */
|
---|
| 703 | #define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
|
---|
| 704 |
|
---|
| 705 | /**
|
---|
| 706 | * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
|
---|
| 707 | * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
|
---|
| 708 | */
|
---|
| 709 | #define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
|
---|
| 710 |
|
---|
| 711 | /** @internal */
|
---|
| 712 | #define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
|
---|
| 713 | /** @internal */
|
---|
| 714 | #define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
|
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| 715 |
|
---|
| 716 |
|
---|
| 717 | /** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
|
---|
| 718 | * @{
|
---|
| 719 | */
|
---|
| 720 | /** Put the address to the right. */
|
---|
| 721 | #define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
|
---|
| 722 | /** Put the address to the left. */
|
---|
| 723 | #define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
|
---|
| 724 | /** Put the address in comments.
|
---|
| 725 | * For some assemblers this implies placing it to the right. */
|
---|
| 726 | #define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
|
---|
| 727 | /** Put the instruction bytes to the right of the disassembly. */
|
---|
| 728 | #define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
|
---|
| 729 | /** Put the instruction bytes to the left of the disassembly. */
|
---|
| 730 | #define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
|
---|
| 731 | /** Put the instruction bytes in comments.
|
---|
| 732 | * For some assemblers this implies placing the bytes to the right. */
|
---|
| 733 | #define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
|
---|
| 734 | /** Put the bytes in square brackets. */
|
---|
| 735 | #define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
|
---|
| 736 | /** Put spaces between the bytes. */
|
---|
| 737 | #define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
|
---|
| 738 | /** Display the relative +/- offset of branch instructions that uses relative addresses,
|
---|
| 739 | * and put the target address in parenthesis. */
|
---|
| 740 | #define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
|
---|
[9271] | 741 | /** Strict assembly. The assembly should, when ever possible, make the
|
---|
| 742 | * assembler reproduce the exact same binary. (Refers to the yasm
|
---|
| 743 | * strict keyword.) */
|
---|
| 744 | #define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
|
---|
[9266] | 745 | /** Checks if the given flags are a valid combination. */
|
---|
| 746 | #define DIS_FMT_FLAGS_IS_VALID(fFlags) \
|
---|
[9271] | 747 | ( !((fFlags) & ~UINT32_C(0x000003ff)) \
|
---|
[9266] | 748 | && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
|
---|
| 749 | && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
|
---|
| 750 | || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
|
---|
| 751 | && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
|
---|
| 752 | && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
|
---|
| 753 | || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
|
---|
| 754 | )
|
---|
| 755 | /** @} */
|
---|
| 756 |
|
---|
| 757 | DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
|
---|
| 758 | DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
|
---|
| 759 | DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
|
---|
| 760 | DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
|
---|
| 761 | DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
|
---|
| 762 | DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
|
---|
| 763 |
|
---|
| 764 | /** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
|
---|
| 765 |
|
---|
| 766 |
|
---|
[20374] | 767 | RT_C_DECLS_END
|
---|
[1] | 768 |
|
---|
| 769 | #endif
|
---|
| 770 |
|
---|