| 1 | /** @file
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| 2 | * X86 (and AMD64) Local APIC registers (VMM,++).
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| 3 | *
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| 4 | * apic.mac is generated from this file by running 'kmk incs' in the root.
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| 5 | */
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| 6 |
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| 7 | /*
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| 8 | * Copyright (C) 2010-2017 Oracle Corporation
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| 9 | *
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| 10 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 11 | * available from http://www.virtualbox.org. This file is free software;
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| 12 | * you can redistribute it and/or modify it under the terms of the GNU
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| 13 | * General Public License (GPL) as published by the Free Software
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| 14 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 15 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 16 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 17 | *
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| 18 | * The contents of this file may alternatively be used under the terms
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| 19 | * of the Common Development and Distribution License Version 1.0
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| 20 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 21 | * VirtualBox OSE distribution, in which case the provisions of the
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| 22 | * CDDL are applicable instead of those of the GPL.
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| 23 | *
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| 24 | * You may elect to license modified versions of this file under the
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| 25 | * terms and conditions of either the GPL or the CDDL or both.
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| 26 | */
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| 27 |
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| 28 | #ifndef ___VBox_apic_h
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| 29 | #define ___VBox_apic_h
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| 30 |
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| 31 | #include <iprt/types.h>
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| 32 |
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| 33 | #define APIC_REG_VERSION 0x0030
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| 34 | #define APIC_REG_VERSION_GET_VER(u32) (u32 & 0xff)
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| 35 | #define APIC_REG_VERSION_GET_MAX_LVT(u32) ((u32 & 0xff0000) >> 16)
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| 36 |
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| 37 | /* Defines according to Figure 10-8 of the Intel Software Developers Manual Vol 3A */
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| 38 | #define APIC_REG_LVT_LINT0 0x0350
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| 39 | #define APIC_REG_LVT_LINT1 0x0360
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| 40 | #define APIC_REG_LVT_ERR 0x0370
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| 41 | #define APIC_REG_LVT_PC 0x0340
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| 42 | #define APIC_REG_LVT_THMR 0x0330
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| 43 | #define APIC_REG_LVT_CMCI 0x02F0
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| 44 | #define APIC_REG_EILVT0 0x0500
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| 45 | #define APIC_REG_EILVT1 0x0510
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| 46 | #define APIC_REG_EILVT2 0x0520
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| 47 | #define APIC_REG_EILVT3 0x0530
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| 48 | #define APIC_REG_LVT_MODE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
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| 49 | #define APIC_REG_LVT_MODE_FIXED 0
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| 50 | #define APIC_REG_LVT_MODE_NMI RT_BIT(10)
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| 51 | #define APIC_REG_LVT_MODE_EXTINT (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
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| 52 | #define APIC_REG_LVT_PIN_POLARIY RT_BIT(13)
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| 53 | #define APIC_REG_LVT_REMOTE_IRR RT_BIT(14)
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| 54 | #define APIC_REG_LVT_LEVEL_TRIGGER RT_BIT(15)
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| 55 | #define APIC_REG_LVT_MASKED RT_BIT(16)
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| 56 |
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| 57 | DECLINLINE(uint32_t) ApicRegRead(void *pvBase, uint32_t offReg)
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| 58 | {
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| 59 | return *(const volatile uint32_t *)((uintptr_t)pvBase + offReg);
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| 60 | }
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| 61 |
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| 62 |
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| 63 | #ifdef ___iprt_asm_amd64_x86_h
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| 64 | /**
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| 65 | * Reads an X2APIC register.
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| 66 | *
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| 67 | * @param offReg MMIO offset, APIC_REG_XXX.
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| 68 | */
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| 69 | DECLINLINE(uint32_t) ApicX2RegRead32(uint32_t offReg)
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| 70 | {
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| 71 | return ASMRdMsr((offReg >> 4) + MSR_IA32_X2APIC_START);
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| 72 | }
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| 73 | #endif
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| 74 |
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| 75 | #endif
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| 76 |
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