| 1 | AMD Athlon(tm) 64 X2 Dual Core Processor 6000+
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| 2 | AMD64 Family 15 Model 107 Stepping 2, AuthenticAMD
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| 3 |
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| 4 | Host VM
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| 5 | HTT * - Hyperthreading enabled
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| 6 | HYPERVISOR - - Hypervisor is present
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| 7 | VMX - - Supports Intel hardware-assisted virtualization
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| 8 | SVM * - Supports AMD hardware-assisted virtualization
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| 9 | EM64T * * Supports 64-bit mode
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| 10 |
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| 11 | SMX - - Supports Intel trusted execution
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| 12 | SKINIT - - Supports AMD SKINIT
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| 13 | EIST - - Supports Enhanced Intel Speedstep
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| 14 |
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| 15 | NX * * Supports no-execute page protection
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| 16 | PAGE1GB - - Supports 1 GB large pages
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| 17 | PAE * * Supports > 32-bit physical addresses
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| 18 | PAT * * Supports Page Attribute Table
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| 19 | PSE * * Supports 4 MB pages
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| 20 | PSE36 * * Supports > 32-bit address 4 MB pages
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| 21 | PGE * * Supports global bit in page tables
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| 22 | SS - - Supports bus snooping for cache operations
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| 23 | VME * * Supports Virtual-8086 mode
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| 24 |
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| 25 | FPU * * Implements i387 floating point instructions
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| 26 | MMX * * Supports MMX instruction set
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| 27 | MMXEXT * - Implements AMD MMX extensions
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| 28 | 3DNOW * * Supports 3DNow! instructions
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| 29 | 3DNOWEXT * * Supports 3DNow! extension instructions
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| 30 | SSE * * Supports Streaming SIMD Extensions
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| 31 | SSE2 * * Supports Streaming SIMD Extensions 2
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| 32 | SSE3 * * Supports Streaming SIMD Extensions 3
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| 33 | SSSE3 - - Supports Supplemental SIMD Extensions 3
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| 34 | SSE4.1 - - Supports Streaming SIMD Extensions 4.1
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| 35 | SSE4.2 - - Supports Streaming SIMD Extensions 4.2
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| 36 |
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| 37 | AES - - Supports AES extensions
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| 38 | AVX - - Supports AVX intruction extensions
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| 39 | FMA - - Supports FMA extensions using YMM state
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| 40 | MSR * * Implements RDMSR/WRMSR instructions
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| 41 | MTTR * * Supports Memory Type Range Registers
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| 42 | XSAVE - - Supports XSAVE/XRSTOR instructions
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| 43 | OSXSAVE - - Supports XSETBV/XGETBV instructions
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| 44 |
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| 45 | CMOV * * Supports CMOVcc instruction
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| 46 | CLFSH * * Supports CLFLUSH instruction
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| 47 | CX8 * * Supports compare and exchange 8-byte instructions
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| 48 | CX16 * - Supprots CMPXCHG16B instruction
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| 49 | DCA - - Supports prefetch from memory-mapped device
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| 50 | F16C - - Supports half-precision instruction
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| 51 | FXSR * * Supports FXSAVE/FXSTOR instructions
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| 52 | FFXSR * * Supports optimized FXSAVE/FSRSTOR instruction
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| 53 | MONITOR - - Supports MONITOR and MWAIT instructions
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| 54 | MOVBE - - Supports MOVBE instruction
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| 55 | PCLULDQ - - Supports PCLMULDQ instruction
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| 56 | POPCNT - - Supports POPCNT instruction
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| 57 | SEP * * Supports fast system call instructions
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| 58 |
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| 59 | DE * * Supports I/O breakpoints including CR4.DE
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| 60 | DTES64 - - Can write history of 64-bit branch addresses
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| 61 | DS - - Implements memory-resident debug buffer
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| 62 | DS-CPL - - Supports Debug Store feature with CPL
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| 63 | PCID - - Supports PCIDs and settable CR4.PCIDE
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| 64 | PDCM - - Supports Performance Capabilities MSR
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| 65 | RDTSCP * * Supports RDTSCP instruction
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| 66 | TSC * * Supports RDTSC instruction
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| 67 | TSC-DEADLINE - - Local APIC supports one-shot deadline timer
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| 68 | TSC-INVARIANT * * TSC runs at constant rate
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| 69 | xTPR - - Supports disabling task priority messages
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| 70 |
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| 71 | ACPI - - Implements MSR for power management
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| 72 | TM - - Implements thermal monitor circuitry
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| 73 | TM2 - - Implements Thermal Monitor 2 control
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| 74 | APIC * * Implements software-accessible local APIC
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| 75 | x2APIC - - Supports x2APIC
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| 76 |
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| 77 | CNXT-ID - - L1 data cache mode adaptive or BIOS
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| 78 |
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| 79 | MCE * * Supports Machine Check, INT18 and CR4.MCE
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| 80 | MCA * * Implements Machine Check Architecture
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| 81 | PBE - - Supports use of FERR#/PBE# pin
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| 82 |
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| 83 | PSN - - Implements 96-bit processor serial number
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| 84 |
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| 85 | Host VM
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| 86 | Logical to Physical Processor Map: Logical to Physical Processor Map:
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| 87 | *- Physical Processor 0 * Physical Processor 0
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| 88 | -* Physical Processor 1
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| 89 | Logical Processor to Socket Map:
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| 90 | Logical Processor to Socket Map: * Socket 0
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| 91 | ** Socket 0
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| 92 | Logical Processor to NUMA Node Map:
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| 93 | Logical Processor to NUMA Node Map: * NUMA Node 0
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| 94 | ** NUMA Node 0
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| 95 | Logical Processor to Cache Map:
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| 96 | Logical Processor to Cache Map: * Data Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
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| 97 | *- Data Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64 * Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64
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| 98 | *- Instruction Cache 0, Level 1, 64 KB, Assoc 2, LineSize 64 * Unified Cache 0, Level 2, 512 KB, Assoc 16, LineSize 64
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| 99 | *- Unified Cache 0, Level 2, 512 KB, Assoc 16, LineSize 64
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| 100 | -* Data Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64 Logical Processor to Group Map:
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| 101 | -* Instruction Cache 1, Level 1, 64 KB, Assoc 2, LineSize 64 * Group 0
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| 102 | -* Unified Cache 1, Level 2, 512 KB, Assoc 16, LineSize 64
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| 103 |
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| 104 | Logical Processor to Group Map:
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| 105 | ** Group 0
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