;; @file ; IPRT - X86 and AMD64 Structures and Definitions. ; ; Automatically generated by various.sed. DO NOT EDIT! ; ; ; Copyright (C) 2006-2023 Oracle and/or its affiliates. ; ; This file is part of VirtualBox base platform packages, as ; available from https://www.virtualbox.org. ; ; This program is free software; you can redistribute it and/or ; modify it under the terms of the GNU General Public License ; as published by the Free Software Foundation, in version 3 of the ; License. ; ; This program is distributed in the hope that it will be useful, but ; WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ; General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, see . ; ; The contents of this file may alternatively be used under the terms ; of the Common Development and Distribution License Version 1.0 ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included ; in the VirtualBox distribution, in which case the provisions of the ; CDDL are applicable instead of those of the GPL. ; ; You may elect to license modified versions of this file under the ; terms and conditions of either the GPL or the CDDL or both. ; ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0 ; %ifndef IPRT_INCLUDED_x86_h %define IPRT_INCLUDED_x86_h %ifndef RT_WITHOUT_PRAGMA_ONCE %endif %ifndef VBOX_FOR_DTRACE_LIB %ifndef __ASSEMBLER__ %else %endif %else %endif %ifdef RT_OS_SOLARIS %endif %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_EFL_CF RT_BIT_32(0) %define X86_EFL_CF_BIT 0 %define X86_EFL_1 RT_BIT_32(1) %define X86_EFL_PF RT_BIT_32(2) %define X86_EFL_PF_BIT 2 %define X86_EFL_AF RT_BIT_32(4) %define X86_EFL_AF_BIT 4 %define X86_EFL_ZF RT_BIT_32(6) %define X86_EFL_ZF_BIT 6 %define X86_EFL_SF RT_BIT_32(7) %define X86_EFL_SF_BIT 7 %define X86_EFL_TF RT_BIT_32(8) %define X86_EFL_TF_BIT 8 %define X86_EFL_IF RT_BIT_32(9) %define X86_EFL_IF_BIT 9 %define X86_EFL_DF RT_BIT_32(10) %define X86_EFL_DF_BIT 10 %define X86_EFL_OF RT_BIT_32(11) %define X86_EFL_OF_BIT 11 %define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13)) %define X86_EFL_NT RT_BIT_32(14) %define X86_EFL_NT_BIT 14 %define X86_EFL_RF RT_BIT_32(16) %define X86_EFL_RF_BIT 16 %define X86_EFL_VM RT_BIT_32(17) %define X86_EFL_VM_BIT 17 %define X86_EFL_AC RT_BIT_32(18) %define X86_EFL_AC_BIT 18 %define X86_EFL_VIF RT_BIT_32(19) %define X86_EFL_VIF_BIT 19 %define X86_EFL_VIP RT_BIT_32(20) %define X86_EFL_VIP_BIT 20 %define X86_EFL_ID RT_BIT_32(21) %define X86_EFL_ID_BIT 21 %define X86_EFL_LIVE_MASK 0x003f7fd5 %define X86_EFL_RA1_MASK RT_BIT_32(1) %define X86_EFL_RAZ_MASK 0xffc08028 %define X86_EFL_RAZ_LO_MASK 0x00008028 %define X86_EFL_IOPL_SHIFT 12 %define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3) %define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \ | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID ) %define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \ | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT ) %define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF ) %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %else %endif %ifndef VBOX_FOR_DTRACE_LIB %else %endif %endif %define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 %define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e %define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 %define X86_CPUID_VENDOR_AMD_EBX 0x68747541 %define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 %define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 %define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 %define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 %define X86_CPUID_VENDOR_VIA_EDX 0x48727561 %define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 %define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 %define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 %define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 %define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 %define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e %define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0) %define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1) %define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2) %define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3) %define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4) %define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5) %define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6) %define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7) %define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8) %define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9) %define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10) %define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11) %define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12) %define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13) %define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14) %define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15) %define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17) %define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18) %define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19) %define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20) %define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21) %define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22) %define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23) %define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24) %define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25) %define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26) %define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27) %define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28) %define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29) %define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30) %define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31) %define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0) %define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1) %define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2) %define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3) %define X86_CPUID_FEATURE_EDX_PSE_BIT 3 %define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4) %define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5) %define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6) %define X86_CPUID_FEATURE_EDX_PAE_BIT 6 %define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7) %define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8) %define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9) %define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11) %define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12) %define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13) %define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14) %define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15) %define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16) %define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17) %define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18) %define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19) %define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21) %define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22) %define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23) %define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24) %define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25) %define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26) %define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27) %define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28) %define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29) %define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31) %define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0) %define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1) %define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0) %define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1) %define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2) %define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4) %define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5) %define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6) %define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7) %define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8) %define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9) %define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10) %define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11) %define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13) %define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14) %define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15) %define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16) %define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17) %define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0) %define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0) %define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1) %define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2) %define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3) %define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4) %define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5) %define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6) %define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7) %define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8) %define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9) %define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10) %define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11) %define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12) %define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13) %define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14) %define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15) %define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16) %define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18) %define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19) %define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20) %define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23) %define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25) %define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26) %define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27) %define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28) %define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29) %define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0) %define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2) %define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3) %define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4) %define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7) %define X86_CPUID_STEXT_FEATURE_ECX_MAWAU 0x003e0000 %define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2) %define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30) %define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10) %define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20) %define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26) %define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27) %define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28) %define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29) %define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30) %define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31) %define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0) %define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11) %define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20) %define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26) %define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27) %define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29) %define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0) %define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1) %define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2) %define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3) %define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4) %define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5) %define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6) %define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7) %define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8) %define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9) %define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12) %define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13) %define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14) %define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15) %define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16) %define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17) %define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22) %define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23) %define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24) %define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25) %define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30) %define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31) %define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1) %define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2) %define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3) %define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4) %define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5) %define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6) %define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7) %define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8) %define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9) %define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10) %define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11) %define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12) %define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13) %define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15) %define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16) %define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19) %define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21) %define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22) %define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0) %define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1) %define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2) %define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3) %define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4) %define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5) %define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6) %define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7) %define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8) %define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9) %define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10) %define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11) %define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12) %define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0) %define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1) %define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2) %define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4) %define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8) %define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12) %define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14) %define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15) %define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16) %define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17) %define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18) %define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24) %define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25) %define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26) %define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0) %define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1) %define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2) %define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3) %define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4) %define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5) %define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6) %define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7) %define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10) %define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12) %define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13) %define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15) %define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16) %define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17) %define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18) %define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19) %define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20) %define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21) %define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23) %define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24) %define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25) %define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26) %define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27) %define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28) %define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29) %define X86_CR0_PE RT_BIT_32(0) %define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0) %define X86_CR0_PE_BIT 0 %define X86_CR0_MP RT_BIT_32(1) %define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1) %define X86_CR0_MP_BIT 1 %define X86_CR0_EM RT_BIT_32(2) %define X86_CR0_EMULATE_FPU RT_BIT_32(2) %define X86_CR0_EM_BIT 2 %define X86_CR0_TS RT_BIT_32(3) %define X86_CR0_TASK_SWITCH RT_BIT_32(3) %define X86_CR0_TS_BIT 3 %define X86_CR0_ET RT_BIT_32(4) %define X86_CR0_EXTENSION_TYPE RT_BIT_32(4) %define X86_CR0_ET_BIT 4 %define X86_CR0_NE RT_BIT_32(5) %define X86_CR0_NUMERIC_ERROR RT_BIT_32(5) %define X86_CR0_NE_BIT 5 %define X86_CR0_WP RT_BIT_32(16) %define X86_CR0_WRITE_PROTECT RT_BIT_32(16) %define X86_CR0_WP_BIT 16 %define X86_CR0_AM RT_BIT_32(18) %define X86_CR0_ALIGMENT_MASK RT_BIT_32(18) %define X86_CR0_AM_BIT 18 %define X86_CR0_NW RT_BIT_32(29) %define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29) %define X86_CR0_NW_BIT 29 %define X86_CR0_CD RT_BIT_32(30) %define X86_CR0_CACHE_DISABLE RT_BIT_32(30) %define X86_CR0_CD_BIT 30 %define X86_CR0_PG RT_BIT_32(31) %define X86_CR0_PAGING RT_BIT_32(31) %define X86_CR0_BIT_PG 31 %define X86_CR3_PWT RT_BIT_32(3) %define X86_CR3_PWT_BIT 3 %define X86_CR3_PCD RT_BIT_32(4) %define X86_CR3_PCD_BIT 4 %define X86_CR3_PAGE_MASK (0xfffff000) %define X86_CR3_PAE_PAGE_MASK (0xffffffe0) %define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000 %define X86_CR3_EPT_PAGE_MASK 0x000ffffffffff000 %define X86_CR4_VME RT_BIT_32(0) %define X86_CR4_VME_BIT 0 %define X86_CR4_PVI RT_BIT_32(1) %define X86_CR4_PVI_BIT 1 %define X86_CR4_TSD RT_BIT_32(2) %define X86_CR4_TSD_BIT 2 %define X86_CR4_DE RT_BIT_32(3) %define X86_CR4_DE_BIT 3 %define X86_CR4_PSE RT_BIT_32(4) %define X86_CR4_PSE_BIT 4 %define X86_CR4_PAE RT_BIT_32(5) %define X86_CR4_PAE_BIT 5 %define X86_CR4_MCE RT_BIT_32(6) %define X86_CR4_MCE_BIT 6 %define X86_CR4_PGE RT_BIT_32(7) %define X86_CR4_PGE_BIT 7 %define X86_CR4_PCE RT_BIT_32(8) %define X86_CR4_PCE_BIT 8 %define X86_CR4_OSFXSR RT_BIT_32(9) %define X86_CR4_OSFXSR_BIT 9 %define X86_CR4_OSXMMEEXCPT RT_BIT_32(10) %define X86_CR4_OSXMMEEXCPT_BIT 10 %define X86_CR4_UMIP RT_BIT_32(11) %define X86_CR4_UMIP_BIT 11 %define X86_CR4_VMXE RT_BIT_32(13) %define X86_CR4_VMXE_BIT 13 %define X86_CR4_SMXE RT_BIT_32(14) %define X86_CR4_SMXE_BIT 14 %define X86_CR4_FSGSBASE RT_BIT_32(16) %define X86_CR4_FSGSBASE_BIT 16 %define X86_CR4_PCIDE RT_BIT_32(17) %define X86_CR4_PCIDE_BIT 17 %define X86_CR4_OSXSAVE RT_BIT_32(18) %define X86_CR4_OSXSAVE_BIT 18 %define X86_CR4_SMEP RT_BIT_32(20) %define X86_CR4_SMEP_BIt 20 %define X86_CR4_SMAP RT_BIT_32(21) %define X86_CR4_SMAP_BIT 21 %define X86_CR4_PKE RT_BIT_32(22) %define X86_CR4_PKE_BIT 22 %define X86_CR4_CET RT_BIT_32(23) %define X86_CR4_CET_BIT 23 %define X86_DR6_B0 RT_BIT_32(0) %define X86_DR6_B1 RT_BIT_32(1) %define X86_DR6_B2 RT_BIT_32(2) %define X86_DR6_B3 RT_BIT_32(3) %define X86_DR6_B_MASK 0x0000000f %define X86_DR6_BD RT_BIT_32(13) %define X86_DR6_BS RT_BIT_32(14) %define X86_DR6_BT RT_BIT_32(15) %define X86_DR6_RTM RT_BIT_32(16) %define X86_DR6_INIT_VAL 0xffff0ff0 %define X86_DR6_RA1_MASK 0xffff0ff0 %define X86_DR6_RA1_MASK_RTM 0xfffe0ff0 %define X86_DR6_RAZ_MASK RT_BIT_64(12) %define X86_DR6_MBZ_MASK 0xffffffff00000000 %define X86_DR6_B(iBp) RT_BIT_64(iBp) %define X86_DR7_L0 RT_BIT_32(0) %define X86_DR7_G0 RT_BIT_32(1) %define X86_DR7_L1 RT_BIT_32(2) %define X86_DR7_G1 RT_BIT_32(3) %define X86_DR7_L2 RT_BIT_32(4) %define X86_DR7_G2 RT_BIT_32(5) %define X86_DR7_L3 RT_BIT_32(6) %define X86_DR7_G3 RT_BIT_32(7) %define X86_DR7_LE RT_BIT_32(8) %define X86_DR7_GE RT_BIT_32(9) %define X86_DR7_LE_ALL 0x0000000000000055 %define X86_DR7_GE_ALL 0x00000000000000aa %define X86_DR7_RTM RT_BIT_32(11) %define X86_DR7_ICE_IR RT_BIT_32(12) %define X86_DR7_GD RT_BIT_32(13) %define X86_DR7_ICE_TR1 RT_BIT_32(14) %define X86_DR7_ICE_TR2 RT_BIT_32(15) %define X86_DR7_RW0_MASK (3 << 16) %define X86_DR7_LEN0_MASK (3 << 18) %define X86_DR7_RW1_MASK (3 << 20) %define X86_DR7_LEN1_MASK (3 << 22) %define X86_DR7_RW2_MASK (3 << 24) %define X86_DR7_LEN2_MASK (3 << 26) %define X86_DR7_RW3_MASK (3 << 28) %define X86_DR7_LEN3_MASK (3 << 30) %define X86_DR7_RA1_MASK RT_BIT_32(10) %define X86_DR7_RAZ_MASK 0x0000d800 %define X86_DR7_MBZ_MASK 0xffffffff00000000 %define X86_DR7_L(iBp) ( 1 << (iBp * 2) ) %define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) ) %define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) ) %define X86_DR7_RW_EO 0 %define X86_DR7_RW_WO 1 %define X86_DR7_RW_IO 2 %define X86_DR7_RW_RW 3 %define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) ) %define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 ) %define X86_DR7_RW_ALL_MASKS 0x33330000 %ifndef VBOX_FOR_DTRACE_LIB %define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (0x000f0000 << ((a_iBp) * 4))) == 0 ) %define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \ ( ((a_uDR7) & (0x03 << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ) %define X86_DR7_ANY_EO_ENABLED(a_uDR7) \ ( (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \ || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \ || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \ || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) ) %define X86_DR7_ANY_RW_IO(uDR7) \ ( ( 0x22220000 & (uDR7) ) %endif %define X86_DR7_LEN_BYTE 0 %define X86_DR7_LEN_WORD 1 %define X86_DR7_LEN_QWORD 2 %define X86_DR7_LEN_DWORD 3 %define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) ) %define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 ) %define X86_DR7_ENABLED_MASK 0x000000ff %define X86_DR7_LEN_ALL_MASKS 0xcccc0000 %define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000 %define X86_DR7_INIT_VAL 0x400 %define MSR_P5_MC_ADDR 0x00000000 %define MSR_P5_MC_TYPE 0x00000001 %define MSR_IA32_TSC 0x10 %define MSR_IA32_CESR 0x00000011 %define MSR_IA32_CTR0 0x00000012 %define MSR_IA32_CTR1 0x00000013 %define MSR_IA32_PLATFORM_ID 0x17 %ifndef MSR_IA32_APICBASE %define MSR_IA32_APICBASE 0x1b %define MSR_IA32_APICBASE_EN RT_BIT_64(11) %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10) %define MSR_IA32_APICBASE_BSP RT_BIT_64(8) %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK) %endif %define MSR_MEMORY_CTRL 0x33 %define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27) %define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28) %define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29) %define MSR_CORE_THREAD_COUNT 0x35 %define MSR_IA32_FEATURE_CONTROL 0x3A %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0) %define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1) %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13) %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14) %define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15) %define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17) %define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18) %define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20) %define MSR_IA32_TSC_ADJUST 0x3B %define MSR_IA32_SPEC_CTRL 0x48 %define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0) %define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1) %define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2) %define MSR_IA32_PRED_CMD 0x49 %define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0) %define MSR_IA32_BIOS_UPDT_TRIG 0x79 %define MSR_IA32_BIOS_SIGN_ID 0x8B %define MSR_IA32_SMM_MONITOR_CTL 0x9B %define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0) %define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2) %define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & 0xfffff) %define MSR_IA32_SMBASE 0x9E %define MSR_IA32_PMC0 0xC1 %define MSR_IA32_PMC1 0xC2 %define MSR_IA32_PMC2 0xC3 %define MSR_IA32_PMC3 0xC4 %define MSR_IA32_PMC4 0xC5 %define MSR_IA32_PMC5 0xC6 %define MSR_IA32_PMC6 0xC7 %define MSR_IA32_PMC7 0xC8 %define MSR_IA32_PLATFORM_INFO 0xCE %define MSR_IA32_CORE_CAPABILITIES 0xCF %define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0) %define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2) %define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3) %define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4) %define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5) %define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6) %define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7) %define MSR_IA32_FSB_CLOCK_STS 0xCD %define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 %define MSR_IA32_MPERF 0xE7 %define MSR_IA32_APERF 0xE8 %define MSR_IA32_MTRR_CAP 0xFE %define MSR_IA32_MTRR_CAP_VCNT_MASK 0x00000000000000ff %define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8) %define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10) %define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11) %define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12) %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_MTRR_MT_UC 0 %define X86_MTRR_MT_WC 1 %define X86_MTRR_MT_WT 4 %define X86_MTRR_MT_WP 5 %define X86_MTRR_MT_WB 6 %define MSR_IA32_ARCH_CAPABILITIES 0x10a %define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0) %define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1) %define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2) %define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3) %define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4) %define MSR_IA32_FLUSH_CMD 0x10b %define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0) %define MSR_BBL_CR_CTL3 0x11e %ifndef MSR_IA32_SYSENTER_CS %define MSR_IA32_SYSENTER_CS 0x174 %define MSR_IA32_SYSENTER_ESP 0x175 %define MSR_IA32_SYSENTER_EIP 0x176 %endif %define MSR_IA32_MCG_CAP 0x179 %define MSR_IA32_MCG_STATUS 0x17A %define MSR_IA32_MCG_CTRL 0x17B %define MSR_IA32_CR_PAT 0x277 %define MSR_IA32_CR_PAT_INIT_VAL 0x0007040600070406 %define MSR_IA32_PAT_MT_UC 0 %define MSR_IA32_PAT_MT_WC 1 %define MSR_IA32_PAT_MT_RSVD_2 2 %define MSR_IA32_PAT_MT_RSVD_3 3 %define MSR_IA32_PAT_MT_WT 4 %define MSR_IA32_PAT_MT_WP 5 %define MSR_IA32_PAT_MT_WB 6 %define MSR_IA32_PAT_MT_UCD 7 %define MSR_IA32_PERFEVTSEL0 0x186 %define MSR_IA32_PERFEVTSEL1 0x187 %define MSR_IA32_PERFEVTSEL2 0x188 %define MSR_IA32_PERFEVTSEL3 0x189 %define MSR_FLEX_RATIO 0x194 %define MSR_IA32_PERF_STATUS 0x198 %define MSR_IA32_PERF_CTL 0x199 %define MSR_IA32_THERM_STATUS 0x19c %define MSR_OFFCORE_RSP_0 0x1a6 %define MSR_OFFCORE_RSP_1 0x1a7 %define MSR_IA32_MISC_ENABLE 0x1A0 %define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0) %define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3) %define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7) %define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11) %define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12) %define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16) %define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18) %define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22) %define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23) %define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34) %define MSR_IA32_DEBUGCTL 0x000001d9 %define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0) %define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1) %define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2) %define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3) %define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4) %define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5) %define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6) %define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7) %define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8) %define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9) %define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10) %define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11) %define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12) %define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14) %define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15) %define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \ | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \ | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \ | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \ | MSR_IA32_DEBUGCTL_RTM) %define MSR_P4_LASTBRANCH_0 0x1db %define MSR_P4_LASTBRANCH_1 0x1dc %define MSR_P4_LASTBRANCH_2 0x1dd %define MSR_P4_LASTBRANCH_3 0x1de %define MSR_P4_LASTBRANCH_TOS 0x1da %define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40 %define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41 %define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42 %define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43 %define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60 %define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61 %define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62 %define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63 %define MSR_CORE2_LASTBRANCH_TOS 0x1c9 %define MSR_LASTBRANCH_0_FROM_IP 0x680 %define MSR_LASTBRANCH_1_FROM_IP 0x681 %define MSR_LASTBRANCH_2_FROM_IP 0x682 %define MSR_LASTBRANCH_3_FROM_IP 0x683 %define MSR_LASTBRANCH_4_FROM_IP 0x684 %define MSR_LASTBRANCH_5_FROM_IP 0x685 %define MSR_LASTBRANCH_6_FROM_IP 0x686 %define MSR_LASTBRANCH_7_FROM_IP 0x687 %define MSR_LASTBRANCH_8_FROM_IP 0x688 %define MSR_LASTBRANCH_9_FROM_IP 0x689 %define MSR_LASTBRANCH_10_FROM_IP 0x68a %define MSR_LASTBRANCH_11_FROM_IP 0x68b %define MSR_LASTBRANCH_12_FROM_IP 0x68c %define MSR_LASTBRANCH_13_FROM_IP 0x68d %define MSR_LASTBRANCH_14_FROM_IP 0x68e %define MSR_LASTBRANCH_15_FROM_IP 0x68f %define MSR_LASTBRANCH_16_FROM_IP 0x690 %define MSR_LASTBRANCH_17_FROM_IP 0x691 %define MSR_LASTBRANCH_18_FROM_IP 0x692 %define MSR_LASTBRANCH_19_FROM_IP 0x693 %define MSR_LASTBRANCH_20_FROM_IP 0x694 %define MSR_LASTBRANCH_21_FROM_IP 0x695 %define MSR_LASTBRANCH_22_FROM_IP 0x696 %define MSR_LASTBRANCH_23_FROM_IP 0x697 %define MSR_LASTBRANCH_24_FROM_IP 0x698 %define MSR_LASTBRANCH_25_FROM_IP 0x699 %define MSR_LASTBRANCH_26_FROM_IP 0x69a %define MSR_LASTBRANCH_27_FROM_IP 0x69b %define MSR_LASTBRANCH_28_FROM_IP 0x69c %define MSR_LASTBRANCH_29_FROM_IP 0x69d %define MSR_LASTBRANCH_30_FROM_IP 0x69e %define MSR_LASTBRANCH_31_FROM_IP 0x69f %define MSR_LASTBRANCH_0_TO_IP 0x6c0 %define MSR_LASTBRANCH_1_TO_IP 0x6c1 %define MSR_LASTBRANCH_2_TO_IP 0x6c2 %define MSR_LASTBRANCH_3_TO_IP 0x6c3 %define MSR_LASTBRANCH_4_TO_IP 0x6c4 %define MSR_LASTBRANCH_5_TO_IP 0x6c5 %define MSR_LASTBRANCH_6_TO_IP 0x6c6 %define MSR_LASTBRANCH_7_TO_IP 0x6c7 %define MSR_LASTBRANCH_8_TO_IP 0x6c8 %define MSR_LASTBRANCH_9_TO_IP 0x6c9 %define MSR_LASTBRANCH_10_TO_IP 0x6ca %define MSR_LASTBRANCH_11_TO_IP 0x6cb %define MSR_LASTBRANCH_12_TO_IP 0x6cc %define MSR_LASTBRANCH_13_TO_IP 0x6cd %define MSR_LASTBRANCH_14_TO_IP 0x6ce %define MSR_LASTBRANCH_15_TO_IP 0x6cf %define MSR_LASTBRANCH_16_TO_IP 0x6d0 %define MSR_LASTBRANCH_17_TO_IP 0x6d1 %define MSR_LASTBRANCH_18_TO_IP 0x6d2 %define MSR_LASTBRANCH_19_TO_IP 0x6d3 %define MSR_LASTBRANCH_20_TO_IP 0x6d4 %define MSR_LASTBRANCH_21_TO_IP 0x6d5 %define MSR_LASTBRANCH_22_TO_IP 0x6d6 %define MSR_LASTBRANCH_23_TO_IP 0x6d7 %define MSR_LASTBRANCH_24_TO_IP 0x6d8 %define MSR_LASTBRANCH_25_TO_IP 0x6d9 %define MSR_LASTBRANCH_26_TO_IP 0x6da %define MSR_LASTBRANCH_27_TO_IP 0x6db %define MSR_LASTBRANCH_28_TO_IP 0x6dc %define MSR_LASTBRANCH_29_TO_IP 0x6dd %define MSR_LASTBRANCH_30_TO_IP 0x6de %define MSR_LASTBRANCH_31_TO_IP 0x6df %define MSR_LASTBRANCH_0_INFO 0xdc0 %define MSR_LASTBRANCH_1_INFO 0xdc1 %define MSR_LASTBRANCH_2_INFO 0xdc2 %define MSR_LASTBRANCH_3_INFO 0xdc3 %define MSR_LASTBRANCH_4_INFO 0xdc4 %define MSR_LASTBRANCH_5_INFO 0xdc5 %define MSR_LASTBRANCH_6_INFO 0xdc6 %define MSR_LASTBRANCH_7_INFO 0xdc7 %define MSR_LASTBRANCH_8_INFO 0xdc8 %define MSR_LASTBRANCH_9_INFO 0xdc9 %define MSR_LASTBRANCH_10_INFO 0xdca %define MSR_LASTBRANCH_11_INFO 0xdcb %define MSR_LASTBRANCH_12_INFO 0xdcc %define MSR_LASTBRANCH_13_INFO 0xdcd %define MSR_LASTBRANCH_14_INFO 0xdce %define MSR_LASTBRANCH_15_INFO 0xdcf %define MSR_LASTBRANCH_16_INFO 0xdd0 %define MSR_LASTBRANCH_17_INFO 0xdd1 %define MSR_LASTBRANCH_18_INFO 0xdd2 %define MSR_LASTBRANCH_19_INFO 0xdd3 %define MSR_LASTBRANCH_20_INFO 0xdd4 %define MSR_LASTBRANCH_21_INFO 0xdd5 %define MSR_LASTBRANCH_22_INFO 0xdd6 %define MSR_LASTBRANCH_23_INFO 0xdd7 %define MSR_LASTBRANCH_24_INFO 0xdd8 %define MSR_LASTBRANCH_25_INFO 0xdd9 %define MSR_LASTBRANCH_26_INFO 0xdda %define MSR_LASTBRANCH_27_INFO 0xddb %define MSR_LASTBRANCH_28_INFO 0xddc %define MSR_LASTBRANCH_29_INFO 0xddd %define MSR_LASTBRANCH_30_INFO 0xdde %define MSR_LASTBRANCH_31_INFO 0xddf %define MSR_LASTBRANCH_SELECT 0x1c8 %define MSR_LASTBRANCH_TOS 0x1c9 %define MSR_LER_FROM_IP 0x1dd %define MSR_LER_TO_IP 0x1de %define MSR_IA32_TSX_CTRL 0x122 %define MSR_IA32_MTRR_PHYSBASE0 0x200 %define MSR_IA32_MTRR_PHYSMASK0 0x201 %define MSR_IA32_MTRR_PHYSBASE1 0x202 %define MSR_IA32_MTRR_PHYSMASK1 0x203 %define MSR_IA32_MTRR_PHYSBASE2 0x204 %define MSR_IA32_MTRR_PHYSMASK2 0x205 %define MSR_IA32_MTRR_PHYSBASE3 0x206 %define MSR_IA32_MTRR_PHYSMASK3 0x207 %define MSR_IA32_MTRR_PHYSBASE4 0x208 %define MSR_IA32_MTRR_PHYSMASK4 0x209 %define MSR_IA32_MTRR_PHYSBASE5 0x20a %define MSR_IA32_MTRR_PHYSMASK5 0x20b %define MSR_IA32_MTRR_PHYSBASE6 0x20c %define MSR_IA32_MTRR_PHYSMASK6 0x20d %define MSR_IA32_MTRR_PHYSBASE7 0x20e %define MSR_IA32_MTRR_PHYSMASK7 0x20f %define MSR_IA32_MTRR_PHYSBASE8 0x210 %define MSR_IA32_MTRR_PHYSMASK8 0x211 %define MSR_IA32_MTRR_PHYSBASE9 0x212 %define MSR_IA32_MTRR_PHYSMASK9 0x213 %define MSR_IA32_MTRR_FIX64K_00000 0x250 %define MSR_IA32_MTRR_FIX16K_80000 0x258 %define MSR_IA32_MTRR_FIX16K_A0000 0x259 %define MSR_IA32_MTRR_FIX4K_C0000 0x268 %define MSR_IA32_MTRR_FIX4K_C8000 0x269 %define MSR_IA32_MTRR_FIX4K_D0000 0x26a %define MSR_IA32_MTRR_FIX4K_D8000 0x26b %define MSR_IA32_MTRR_FIX4K_E0000 0x26c %define MSR_IA32_MTRR_FIX4K_E8000 0x26d %define MSR_IA32_MTRR_FIX4K_F0000 0x26e %define MSR_IA32_MTRR_FIX4K_F8000 0x26f %define MSR_IA32_MTRR_DEF_TYPE 0x2FF %define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF %define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10) %define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11) %define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \ | MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \ | MSR_IA32_MTRR_DEF_TYPE_MTRR_EN) %define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11) %define MSR_IA32_MTRR_PHYSBASE_MT_MASK 0xff %define MSR_IA32_PERF_GLOBAL_STATUS 0x38E %define MSR_IA32_PERF_GLOBAL_CTRL 0x38F %define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390 %define MSR_IA32_PEBS_ENABLE 0x3F1 %define MSR_IA32_MC0_CTL 0x400 %define MSR_IA32_MC0_STATUS 0x401 %define MSR_IA32_VMX_BASIC 0x480 %define MSR_IA32_VMX_PINBASED_CTLS 0x481 %define MSR_IA32_VMX_PROCBASED_CTLS 0x482 %define MSR_IA32_VMX_EXIT_CTLS 0x483 %define MSR_IA32_VMX_ENTRY_CTLS 0x484 %define MSR_IA32_VMX_MISC 0x485 %define MSR_IA32_VMX_CR0_FIXED0 0x486 %define MSR_IA32_VMX_CR0_FIXED1 0x487 %define MSR_IA32_VMX_CR4_FIXED0 0x488 %define MSR_IA32_VMX_CR4_FIXED1 0x489 %define MSR_IA32_VMX_VMCS_ENUM 0x48A %define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B %define MSR_IA32_VMX_EPT_VPID_CAP 0x48C %define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D %define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E %define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F %define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 %define MSR_IA32_VMX_VMFUNC 0x491 %define MSR_IA32_VMX_PROCBASED_CTLS3 0x492 %define MSR_IA32_VMX_EXIT_CTLS2 0x493 %define MSR_IA32_RTIT_CTL 0x570 %define MSR_IA32_DS_AREA 0x600 %define MSR_RAPL_POWER_UNIT 0x606 %define MSR_PKGC3_IRTL 0x60a %define MSR_PKGC_IRTL1 0x60b %define MSR_PKGC_IRTL2 0x60c %define MSR_PKG_C2_RESIDENCY 0x60d %define MSR_PKG_POWER_LIMIT 0x610 %define MSR_PKG_ENERGY_STATUS 0x611 %define MSR_PKG_PERF_STATUS 0x613 %define MSR_PKG_POWER_INFO 0x614 %define MSR_DRAM_POWER_LIMIT 0x618 %define MSR_DRAM_ENERGY_STATUS 0x619 %define MSR_DRAM_PERF_STATUS 0x61b %define MSR_DRAM_POWER_INFO 0x61c %define MSR_PKG_C10_RESIDENCY 0x632 %define MSR_PP0_ENERGY_STATUS 0x639 %define MSR_PP1_ENERGY_STATUS 0x641 %define MSR_TURBO_ACTIVATION_RATIO 0x64c %define MSR_CORE_PERF_LIMIT_REASONS 0x64f %define MSR_IA32_U_CET 0x6a0 %define MSR_IA32_S_CET 0x6a2 %define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0) %define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1) %define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2) %define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3) %define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4) %define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5) %define MSR_IA32_CET_SUPPRESS RT_BIT_64(10) %define MSR_IA32_CET_TRACKER RT_BIT_64(11) %define MSR_IA32_CET_EB_LEG_BITMAP_BASE 0xfffffffffffff000 %define MSR_IA32_X2APIC_START 0x800 %define MSR_IA32_X2APIC_ID 0x802 %define MSR_IA32_X2APIC_VERSION 0x803 %define MSR_IA32_X2APIC_TPR 0x808 %define MSR_IA32_X2APIC_PPR 0x80A %define MSR_IA32_X2APIC_EOI 0x80B %define MSR_IA32_X2APIC_LDR 0x80D %define MSR_IA32_X2APIC_SVR 0x80F %define MSR_IA32_X2APIC_ISR0 0x810 %define MSR_IA32_X2APIC_ISR1 0x811 %define MSR_IA32_X2APIC_ISR2 0x812 %define MSR_IA32_X2APIC_ISR3 0x813 %define MSR_IA32_X2APIC_ISR4 0x814 %define MSR_IA32_X2APIC_ISR5 0x815 %define MSR_IA32_X2APIC_ISR6 0x816 %define MSR_IA32_X2APIC_ISR7 0x817 %define MSR_IA32_X2APIC_TMR0 0x818 %define MSR_IA32_X2APIC_TMR1 0x819 %define MSR_IA32_X2APIC_TMR2 0x81A %define MSR_IA32_X2APIC_TMR3 0x81B %define MSR_IA32_X2APIC_TMR4 0x81C %define MSR_IA32_X2APIC_TMR5 0x81D %define MSR_IA32_X2APIC_TMR6 0x81E %define MSR_IA32_X2APIC_TMR7 0x81F %define MSR_IA32_X2APIC_IRR0 0x820 %define MSR_IA32_X2APIC_IRR1 0x821 %define MSR_IA32_X2APIC_IRR2 0x822 %define MSR_IA32_X2APIC_IRR3 0x823 %define MSR_IA32_X2APIC_IRR4 0x824 %define MSR_IA32_X2APIC_IRR5 0x825 %define MSR_IA32_X2APIC_IRR6 0x826 %define MSR_IA32_X2APIC_IRR7 0x827 %define MSR_IA32_X2APIC_ESR 0x828 %define MSR_IA32_X2APIC_LVT_CMCI 0x82F %define MSR_IA32_X2APIC_ICR 0x830 %define MSR_IA32_X2APIC_LVT_TIMER 0x832 %define MSR_IA32_X2APIC_LVT_THERMAL 0x833 %define MSR_IA32_X2APIC_LVT_PERF 0x834 %define MSR_IA32_X2APIC_LVT_LINT0 0x835 %define MSR_IA32_X2APIC_LVT_LINT1 0x836 %define MSR_IA32_X2APIC_LVT_ERROR 0x837 %define MSR_IA32_X2APIC_TIMER_ICR 0x838 %define MSR_IA32_X2APIC_TIMER_CCR 0x839 %define MSR_IA32_X2APIC_TIMER_DCR 0x83E %define MSR_IA32_X2APIC_SELF_IPI 0x83F %define MSR_IA32_X2APIC_END 0x8FF %define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER %define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR %define MSR_K6_EFER 0xc0000080 %define MSR_K6_EFER_SCE RT_BIT_32(0) %define MSR_K6_EFER_LME RT_BIT_32(8) %define MSR_K6_EFER_BIT_LME 8 %define MSR_K6_EFER_LMA RT_BIT_32(10) %define MSR_K6_EFER_BIT_LMA 10 %define MSR_K6_EFER_NXE RT_BIT_32(11) %define MSR_K6_EFER_BIT_NXE 11 %define MSR_K6_EFER_SVME RT_BIT_32(12) %define MSR_K6_EFER_LMSLE RT_BIT_32(13) %define MSR_K6_EFER_FFXSR RT_BIT_32(14) %define MSR_K6_EFER_TCE RT_BIT_32(15) %define MSR_K6_EFER_MCOMMIT RT_BIT_32(17) %define MSR_K6_STAR 0xc0000081 %define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48 %define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32 %define MSR_K6_STAR_SEL_MASK 0xffff %define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff %define MSR_K6_WHCR 0xc0000082 %define MSR_K6_UWCCR 0xc0000085 %define MSR_K6_PSOR 0xc0000087 %define MSR_K6_PFIR 0xc0000088 %define MSR_K7_EVNTSEL0 0xc0010000 %define MSR_K7_EVNTSEL1 0xc0010001 %define MSR_K7_EVNTSEL2 0xc0010002 %define MSR_K7_EVNTSEL3 0xc0010003 %define MSR_K7_PERFCTR0 0xc0010004 %define MSR_K7_PERFCTR1 0xc0010005 %define MSR_K7_PERFCTR2 0xc0010006 %define MSR_K7_PERFCTR3 0xc0010007 %define MSR_K8_LSTAR 0xc0000082 %define MSR_K8_CSTAR 0xc0000083 %define MSR_K8_SF_MASK 0xc0000084 %define MSR_K8_FS_BASE 0xc0000100 %define MSR_K8_GS_BASE 0xc0000101 %define MSR_K8_KERNEL_GS_BASE 0xc0000102 %define MSR_K8_TSC_AUX 0xc0000103 %define MSR_K8_SYSCFG 0xc0010010 %define MSR_K8_HWCR 0xc0010015 %define MSR_K8_IORRBASE0 0xc0010016 %define MSR_K8_IORRMASK0 0xc0010017 %define MSR_K8_IORRBASE1 0xc0010018 %define MSR_K8_IORRMASK1 0xc0010019 %define MSR_K8_TOP_MEM1 0xc001001a %define MSR_K8_TOP_MEM2 0xc001001d %define MSR_K7_SMBASE 0xc0010111 %define MSR_K7_SMM_ADDR 0xc0010112 %define MSR_K7_SMM_MASK 0xc0010113 %define MSR_K8_NB_CFG 0xc001001f %define MSR_K8_INT_PENDING 0xc0010055 %define MSR_K8_VM_CR 0xc0010114 %define MSR_K8_VM_CR_DPD RT_BIT_32(0) %define MSR_K8_VM_CR_R_INIT RT_BIT_32(1) %define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2) %define MSR_K8_VM_CR_LOCK RT_BIT_32(3) %define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4) %define MSR_K8_IGNNE 0xc0010115 %define MSR_K8_SMM_CTL 0xc0010116 %define MSR_K8_VM_HSAVE_PA 0xc0010117 %define MSR_AMD_VIRT_SPEC_CTL 0xc001011f %define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2) %ifndef __ASSEMBLER__ %endif %define X86_PG_ENTRIES 1024 %ifndef __ASSEMBLER__ %endif %define X86_PG_PAE_ENTRIES 512 %define X86_PG_PAE_PDPE_ENTRIES 4 %define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES %define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES %define X86_PAGE_SIZE X86_PAGE_4K_SIZE %define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT %define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK %define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK %define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32 %define X86_PAGE_4K_SIZE _4K %define X86_PAGE_4K_SHIFT 12 %define X86_PAGE_4K_OFFSET_MASK 0xfff %define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000 %define X86_PAGE_4K_BASE_MASK_32 0xfffff000 %define X86_PAGE_2M_SIZE _2M %define X86_PAGE_2M_SHIFT 21 %define X86_PAGE_2M_OFFSET_MASK 0x001fffff %define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000 %define X86_PAGE_2M_BASE_MASK_32 0xffe00000 %define X86_PAGE_4M_SIZE _4M %define X86_PAGE_4M_SHIFT 22 %define X86_PAGE_4M_OFFSET_MASK 0x003fffff %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000 %define X86_PAGE_4M_BASE_MASK_32 0xffc00000 %define X86_PAGE_1G_SIZE _1G %define X86_PAGE_1G_SHIFT 30 %define X86_PAGE_1G_OFFSET_MASK 0x3fffffff %define X86_PAGE_1G_BASE_MASK 0xffffffffc0000000 %define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000)) %define X86_GET_PAGE_BASE_MASK(a_cShift) (0xffffffffffffffff << (a_cShift)) %define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift)) %define X86_PTE_BIT_P 0 %define X86_PTE_BIT_RW 1 %define X86_PTE_BIT_US 2 %define X86_PTE_BIT_PWT 3 %define X86_PTE_BIT_PCD 4 %define X86_PTE_BIT_A 5 %define X86_PTE_BIT_D 6 %define X86_PTE_BIT_PAT 7 %define X86_PTE_BIT_G 8 %define X86_PTE_PAE_BIT_NX 63 %define X86_PTE_P RT_BIT_32(0) %define X86_PTE_RW RT_BIT_32(1) %define X86_PTE_US RT_BIT_32(2) %define X86_PTE_PWT RT_BIT_32(3) %define X86_PTE_PCD RT_BIT_32(4) %define X86_PTE_A RT_BIT_32(5) %define X86_PTE_D RT_BIT_32(6) %define X86_PTE_PAT RT_BIT_32(7) %define X86_PTE_G RT_BIT_32(8) %define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11)) %define X86_PTE_PG_MASK ( 0xfffff000 ) %define X86_PTE_PAE_PG_MASK 0x000ffffffffff000 %define X86_PTE_PAE_NX RT_BIT_64(63) %define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000 %define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000 %define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000 %define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PT_SHIFT 12 %define X86_PT_MASK 0x3ff %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PT_PAE_SHIFT 12 %define X86_PT_PAE_MASK 0x1ff %define X86_PDE_P RT_BIT_32(0) %define X86_PDE_RW RT_BIT_32(1) %define X86_PDE_US RT_BIT_32(2) %define X86_PDE_PWT RT_BIT_32(3) %define X86_PDE_PCD RT_BIT_32(4) %define X86_PDE_A RT_BIT_32(5) %define X86_PDE_PS RT_BIT_32(7) %define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11)) %define X86_PDE_PG_MASK ( 0xfffff000 ) %define X86_PDE_PAE_PG_MASK 0x000ffffffffff000 %define X86_PDE_PAE_NX RT_BIT_64(63) %define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080 %define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080 %define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080 %define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PDE4M_P RT_BIT_32(0) %define X86_PDE4M_RW RT_BIT_32(1) %define X86_PDE4M_US RT_BIT_32(2) %define X86_PDE4M_PWT RT_BIT_32(3) %define X86_PDE4M_PCD RT_BIT_32(4) %define X86_PDE4M_A RT_BIT_32(5) %define X86_PDE4M_D RT_BIT_32(6) %define X86_PDE4M_PS RT_BIT_32(7) %define X86_PDE4M_G RT_BIT_32(8) %define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11)) %define X86_PDE4M_PAT RT_BIT_32(12) %define X86_PDE4M_PAT_SHIFT (12 - 7) %define X86_PDE4M_PG_MASK ( 0xffc00000 ) %define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 ) %define X86_PDE4M_PG_HIGH_SHIFT 19 %define X86_PDE4M_MBZ_MASK RT_BIT_32(21) %define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000 %define X86_PDE2M_PAE_NX RT_BIT_64(63) %define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000 %define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000 %define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000 %define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %ifndef __ASSEMBLER__ %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PD_SHIFT 22 %define X86_PD_MASK 0x3ff %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PD_PAE_SHIFT 21 %define X86_PD_PAE_MASK 0x1ff %define X86_PDPE_P RT_BIT_32(0) %define X86_PDPE_RW RT_BIT_32(1) %define X86_PDPE_US RT_BIT_32(2) %define X86_PDPE_PWT RT_BIT_32(3) %define X86_PDPE_PCD RT_BIT_32(4) %define X86_PDPE_A RT_BIT_32(5) %define X86_PDPE_LM_PS RT_BIT_32(7) %define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11)) %define X86_PDPE_PG_MASK 0x000ffffffffff000 %define X86_PDPE1G_PG_MASK 0x000fffffc0000000 %define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6 %define X86_PDPE_LM_NX RT_BIT_64(63) %define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180 %define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180 %define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000 %define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PDPT_SHIFT 30 %define X86_PDPT_MASK_PAE 0x3 %define X86_PDPT_MASK_AMD64 0x1ff %define X86_PML4E_P RT_BIT_32(0) %define X86_PML4E_RW RT_BIT_32(1) %define X86_PML4E_US RT_BIT_32(2) %define X86_PML4E_PWT RT_BIT_32(3) %define X86_PML4E_PCD RT_BIT_32(4) %define X86_PML4E_A RT_BIT_32(5) %define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11)) %define X86_PML4E_PG_MASK 0x000ffffffffff000 %define X86_PML4E_MBZ_MASK_NX 0x0000000000000080 %define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080 %define X86_PML4E_NX RT_BIT_64(63) %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_PML4_SHIFT 39 %define X86_PML4_MASK 0x1ff %define X86_INVPCID_TYPE_INDV_ADDR 0 %define X86_INVPCID_TYPE_SINGLE_CONTEXT 1 %define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2 %define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3 %define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL %define X86_FPU_INT64_INDEFINITE INT64_MIN %define X86_FPU_INT32_INDEFINITE INT32_MIN %define X86_FPU_INT16_INDEFINITE INT16_MIN %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_OFF_FXSTATE_RSVD 0x1d0 %define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b %ifndef VBOX_FOR_DTRACE_LIB %endif %define X86_FSW_IE RT_BIT_32(0) %define X86_FSW_IE_BIT 0 %define X86_FSW_DE RT_BIT_32(1) %define X86_FSW_DE_BIT 1 %define X86_FSW_ZE RT_BIT_32(2) %define X86_FSW_ZE_BIT 2 %define X86_FSW_OE RT_BIT_32(3) %define X86_FSW_OE_BIT 3 %define X86_FSW_UE RT_BIT_32(4) %define X86_FSW_UE_BIT 4 %define X86_FSW_PE RT_BIT_32(5) %define X86_FSW_PE_BIT 5 %define X86_FSW_SF RT_BIT_32(6) %define X86_FSW_SF_BIT 6 %define X86_FSW_ES RT_BIT_32(7) %define X86_FSW_ES_BIT 7 %define X86_FSW_XCPT_MASK 0x007f %define X86_FSW_XCPT_ES_MASK 0x00ff %define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT) %define X86_FSW_C0_BIT 8 %define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT) %define X86_FSW_C1_BIT 9 %define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT) %define X86_FSW_C2_BIT 10 %define X86_FSW_TOP_MASK 0x3800 %define X86_FSW_TOP_SHIFT 11 %define X86_FSW_TOP_SMASK 0x0007 %define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK) %define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK) %define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT) %define X86_FSW_C3_BIT 14 %define X86_FSW_C_MASK 0x4700 %define X86_FSW_B RT_BIT_32(15) %define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \ ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \ | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \ | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) ) %define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \ ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \ | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \ | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) ) %define X86_FCW_IM RT_BIT_32(0) %define X86_FCW_IM_BIT 0 %define X86_FCW_DM RT_BIT_32(1) %define X86_FCW_DM_BIT 1 %define X86_FCW_ZM RT_BIT_32(2) %define X86_FCW_ZM_BIT 2 %define X86_FCW_OM RT_BIT_32(3) %define X86_FCW_OM_BIT 3 %define X86_FCW_UM RT_BIT_32(4) %define X86_FCW_UM_BIT 4 %define X86_FCW_PM RT_BIT_32(5) %define X86_FCW_PM_BIT 5 %define X86_FCW_MASK_ALL 0x007f %define X86_FCW_XCPT_MASK 0x003f %define X86_FCW_PC_MASK 0x0300 %define X86_FCW_PC_SHIFT 8 %define X86_FCW_PC_24 0x0000 %define X86_FCW_PC_RSVD 0x0100 %define X86_FCW_PC_53 0x0200 %define X86_FCW_PC_64 0x0300 %define X86_FCW_RC_MASK 0x0c00 %define X86_FCW_RC_SHIFT 10 %define X86_FCW_RC_NEAREST 0x0000 %define X86_FCW_RC_DOWN 0x0400 %define X86_FCW_RC_UP 0x0800 %define X86_FCW_RC_ZERO 0x0c00 %define X86_FCW_IC_MASK 0x1000 %define X86_FCW_IC_AFFINE 0x1000 %define X86_FCW_IC_PROJECTIVE 0x0000 %define X86_FCW_ZERO_MASK 0xf080 %define X86_MXCSR_IE RT_BIT_32(0) %define X86_MXCSR_DE RT_BIT_32(1) %define X86_MXCSR_ZE RT_BIT_32(2) %define X86_MXCSR_OE RT_BIT_32(3) %define X86_MXCSR_UE RT_BIT_32(4) %define X86_MXCSR_PE RT_BIT_32(5) %define X86_MXCSR_XCPT_FLAGS 0x003f %define X86_MXCSR_DAZ RT_BIT_32(6) %define X86_MXCSR_IM RT_BIT_32(7) %define X86_MXCSR_DM RT_BIT_32(8) %define X86_MXCSR_ZM RT_BIT_32(9) %define X86_MXCSR_OM RT_BIT_32(10) %define X86_MXCSR_UM RT_BIT_32(11) %define X86_MXCSR_PM RT_BIT_32(12) %define X86_MXCSR_XCPT_MASK 0x1f80 %define X86_MXCSR_XCPT_MASK_SHIFT 7 %define X86_MXCSR_RC_MASK 0x6000 %define X86_MXCSR_RC_SHIFT 13 %define X86_MXCSR_RC_NEAREST 0x0000 %define X86_MXCSR_RC_DOWN 0x2000 %define X86_MXCSR_RC_UP 0x4000 %define X86_MXCSR_RC_ZERO 0x6000 %define X86_MXCSR_FZ RT_BIT_32(15) %define X86_MXCSR_MM RT_BIT_32(17) %define X86_MXCSR_ZERO_MASK 0xfffd0000 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define XSAVE_C_X87_BIT 0 %define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT) %define XSAVE_C_SSE_BIT 1 %define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT) %define XSAVE_C_YMM_BIT 2 %define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT) %define XSAVE_C_BNDREGS_BIT 3 %define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT) %define XSAVE_C_BNDCSR_BIT 4 %define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT) %define XSAVE_C_OPMASK_BIT 5 %define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT) %define XSAVE_C_ZMM_HI256_BIT 6 %define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT) %define XSAVE_C_ZMM_16HI_BIT 7 %define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT) %define XSAVE_C_PKRU_BIT 9 %define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT) %define XSAVE_C_LWP_BIT 62 %define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT) %define XSAVE_C_X_BIT 63 %define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT) %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86DESCATTR_TYPE 0x0000000f %define X86DESCATTR_DT 0x00000010 %define X86DESCATTR_DPL 0x00000060 %define X86DESCATTR_DPL_SHIFT 5 %define X86DESCATTR_P 0x00000080 %define X86DESCATTR_LIMIT_HIGH 0x00000f00 %define X86DESCATTR_AVL 0x00001000 %define X86DESCATTR_L 0x00002000 %define X86DESCATTR_D 0x00004000 %define X86DESCATTR_G 0x00008000 %define X86DESCATTR_UNUSABLE 0x00010000 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %ifndef VBOX_FOR_DTRACE_LIB %ifndef __ASSEMBLER__ %endif %define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) %define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) %define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) %define X86DESCGENERIC_BIT_OFF_TYPE (40) %define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) %define X86DESCGENERIC_BIT_OFF_DPL (45) %define X86DESCGENERIC_BIT_OFF_PRESENT (47) %define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) %define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) %define X86DESCGENERIC_BIT_OFF_LONG (53) %define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) %define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) %define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) %define X86LAR_F_TYPE 0x0f00 %define X86LAR_F_DT 0x1000 %define X86LAR_F_DPL 0x6000 %define X86LAR_F_DPL_SHIFT 13 %define X86LAR_F_P 0x8000 %define X86LAR_F_AVL 0x00100000 %define X86LAR_F_L 0x00200000 %define X86LAR_F_D 0x00400000 %define X86LAR_F_G 0x00800000 %ifndef __ASSEMBLER__ %endif %endif %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %if HC_ARCH_BITS == 64 %else %endif %if HC_ARCH_BITS == 64 %else %endif %if HC_ARCH_BITS == 64 %else %endif %endif %define X86_SEL_TYPE_CODE 8 %define X86_SEL_TYPE_MEMORY RT_BIT_32(4) %define X86_SEL_TYPE_ACCESSED 1 %define X86_SEL_TYPE_DOWN 4 %define X86_SEL_TYPE_CONF 4 %define X86_SEL_TYPE_WRITE 2 %define X86_SEL_TYPE_READ 2 %define X86_SEL_TYPE_READ_BIT 1 %define X86_SEL_TYPE_RO 0 %define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_RW 2 %define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_RO_DOWN 4 %define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_RW_DOWN 6 %define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE) %define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE) %define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE) %define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE) %define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED) %define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2 %define X86_SEL_TYPE_SYS_UNDEFINED 0 %define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1 %define X86_SEL_TYPE_SYS_LDT 2 %define X86_SEL_TYPE_SYS_286_TSS_BUSY 3 %define X86_SEL_TYPE_SYS_286_CALL_GATE 4 %define X86_SEL_TYPE_SYS_TASK_GATE 5 %define X86_SEL_TYPE_SYS_286_INT_GATE 6 %define X86_SEL_TYPE_SYS_286_TRAP_GATE 7 %define X86_SEL_TYPE_SYS_UNDEFINED2 8 %define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9 %define X86_SEL_TYPE_SYS_UNDEFINED3 0xA %define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB %define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC %define X86_SEL_TYPE_SYS_UNDEFINED4 0xD %define X86_SEL_TYPE_SYS_386_INT_GATE 0xE %define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF %define AMD64_SEL_TYPE_SYS_LDT 2 %define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9 %define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB %define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC %define AMD64_SEL_TYPE_SYS_INT_GATE 0xE %define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF %define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11)) %define X86_DESC_S RT_BIT_32(12) %define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14)) %define X86_DESC_P RT_BIT_32(15) %define X86_DESC_AVL RT_BIT_32(20) %define X86_DESC_DB RT_BIT_32(22) %define X86_DESC_G RT_BIT_32(23) %define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b %define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67 %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %ifndef VBOX_FOR_DTRACE_LIB %endif %endif %define X86_SEL_SHIFT 3 %define X86_SEL_MASK 0xfff8 %define X86_SEL_MASK_OFF_RPL 0xfffc %define X86_SEL_LDT 0x0004 %define X86_SEL_RPL 0x0003 %define X86_SEL_RPL_LDT 0x0007 %ifndef __ASSEMBLER__ %endif %define X86_XCPT_LAST 0x1f %define X86_TRAP_ERR_EXTERNAL 1 %define X86_TRAP_ERR_IDT 2 %define X86_TRAP_ERR_TI 4 %define X86_TRAP_ERR_SEL_MASK 0xfff8 %define X86_TRAP_ERR_SEL_SHIFT 3 %define X86_TRAP_PF_P RT_BIT_32(0) %define X86_TRAP_PF_RW RT_BIT_32(1) %define X86_TRAP_PF_US RT_BIT_32(2) %define X86_TRAP_PF_RSVD RT_BIT_32(3) %define X86_TRAP_PF_ID RT_BIT_32(4) %define X86_TRAP_PF_PK RT_BIT_32(5) %ifndef __ASSEMBLER__ %ifndef VBOX_FOR_DTRACE_LIB %else %endif %ifndef VBOX_FOR_DTRACE_LIB %else %endif %endif %define X86_MODRM_RM_MASK 0x07 %define X86_MODRM_REG_MASK 0x38 %define X86_MODRM_REG_SMASK 0x07 %define X86_MODRM_REG_SHIFT 3 %define X86_MODRM_MOD_MASK 0xc0 %define X86_MODRM_MOD_SMASK 0x03 %define X86_MODRM_MOD_SHIFT 6 %define X86_MOD_MEM0 0 %define X86_MOD_MEM1 1 %define X86_MOD_MEM4 2 %define X86_MOD_REG 3 %ifndef VBOX_FOR_DTRACE_LIB %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem)) %endif %define X86_SIB_BASE_MASK 0x07 %define X86_SIB_INDEX_MASK 0x38 %define X86_SIB_INDEX_SMASK 0x07 %define X86_SIB_INDEX_SHIFT 3 %define X86_SIB_SCALE_MASK 0xc0 %define X86_SIB_SCALE_SMASK 0x03 %define X86_SIB_SCALE_SHIFT 6 %ifndef VBOX_FOR_DTRACE_LIB %define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \ (((a_Scale) << X86_SIB_SCALE_SHIFT) | ((a_IndexReg) << X86_SIB_INDEX_SHIFT) | (a_BaseReg)) %endif %define X86_GREG_xAX 0 %define X86_GREG_xCX 1 %define X86_GREG_xDX 2 %define X86_GREG_xBX 3 %define X86_GREG_xSP 4 %define X86_GREG_xBP 5 %define X86_GREG_xSI 6 %define X86_GREG_xDI 7 %define X86_GREG_x8 8 %define X86_GREG_x9 9 %define X86_GREG_x10 10 %define X86_GREG_x11 11 %define X86_GREG_x12 12 %define X86_GREG_x13 13 %define X86_GREG_x14 14 %define X86_GREG_x15 15 %define X86_GREG_COUNT 16 %define X86_SREG_ES 0 %define X86_SREG_CS 1 %define X86_SREG_SS 2 %define X86_SREG_DS 3 %define X86_SREG_FS 4 %define X86_SREG_GS 5 %define X86_SREG_COUNT 6 %define X86_OP_PRF_CS 0x2e %define X86_OP_PRF_SS 0x36 %define X86_OP_PRF_DS 0x3e %define X86_OP_PRF_ES 0x26 %define X86_OP_PRF_FS 0x64 %define X86_OP_PRF_GS 0x65 %define X86_OP_PRF_SIZE_OP 0x66 %define X86_OP_PRF_SIZE_ADDR 0x67 %define X86_OP_PRF_LOCK 0xf0 %define X86_OP_PRF_REPZ 0xf3 %define X86_OP_PRF_REPNZ 0xf2 %define X86_OP_REX 0x40 %define X86_OP_REX_B 0x41 %define X86_OP_REX_X 0x42 %define X86_OP_REX_R 0x44 %define X86_OP_REX_W 0x48 %define X86_OP_VEX3 0xc4 %define X86_OP_VEX2 0xc5 %define X86_OP_VEX2_BYTE1_P_MASK 0x3 %define X86_OP_VEX2_BYTE1_P_NO_PRF 0 %define X86_OP_VEX2_BYTE1_P_066H 1 %define X86_OP_VEX2_BYTE1_P_0F3H 2 %define X86_OP_VEX2_BYTE1_P_0F2H 3 %define X86_OP_VEX2_BYTE1_L RT_BIT(2) %define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78 %define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3 %define X86_OP_VEX2_BYTE1_VVVV_NONE 15 %define X86_OP_VEX2_BYTE1_R RT_BIT(7) %define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \ ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \ | (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \ | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \ | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK)) %define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \ ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \ | (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \ | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \ | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK)) %define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f %define X86_OP_VEX3_BYTE1_B RT_BIT(5) %define X86_OP_VEX3_BYTE1_X RT_BIT(6) %define X86_OP_VEX3_BYTE1_R RT_BIT(7) %define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \ ( (uint8_t)(a_idxMap) \ | ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \ | ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \ | ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R)) %define X86_OP_VEX3_BYTE2_P_MASK 0x3 %define X86_OP_VEX3_BYTE2_P_NO_PRF 0 %define X86_OP_VEX3_BYTE2_P_066H 1 %define X86_OP_VEX3_BYTE2_P_0F3H 2 %define X86_OP_VEX3_BYTE2_P_0F2H 3 %define X86_OP_VEX3_BYTE2_L RT_BIT(2) %define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78 %define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3 %define X86_OP_VEX3_BYTE2_VVVV_NONE 15 %define X86_OP_VEX3_BYTE2_W RT_BIT(7) %define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \ ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \ | ((~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \ | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \ | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK)) %define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \ ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \ | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \ | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \ | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK)) %endif %include "iprt/x86extra.mac"